[Arch]: remove additional definition of "reset" port for the fp16_sop2_accum DSP slice

        in the "k6FracN10LB_mem20K_complexDSP_customSB_22nm" architecture

Signed-off-by: Seyed Alireza Damghani <[email protected]>

Author: sdamghan

vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml

@@ -423,7 +423,6 @@
     <model name="fp16_sop2_accum">
       <input_ports>
         <port name="clk" is_clock="1"/>  
-        <port name="reset" clock="clk" combinational_sink_ports="result chainout"/>
         <port name="mode_sigs" clock="clk" combinational_sink_ports="result chainout"/>
         <port name="reset" clock="clk" combinational_sink_ports="result chainout"/>
         <port name="top_a" clock="clk" combinational_sink_ports="result chainout"/>