[test] update strong tileable golden result

Author: amin1377

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/golden_results.txt

@@ -1,4 +1,4 @@
-arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	yosys_synth_time	max_yosys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-k4_N4_tileable_90nm.xml	diffeq.blif	common	9.82	vpr	61.45 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	417	64	-1	-1	success	v8.0.0-6725-gff83963de-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64	2022-11-01T15:38:22	LAPTOP-CVNHOGSN	/home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks	62920	64	39	1935	1974	1	1104	520	23	23	529	clb	auto	18.8 MiB	0.14	10227	61.2 MiB	0.57	0.01	6.71028	-1587.65	-6.71028	6.71028	0.25	0.0007736	0.0005813	0.0896507	0.0699632	34	17207	50	983127	929624	921133.	1741.27	7.25	0.536827	0.433199	14874	22	8645	29434	2727679	902790	6.8984	6.8984	-1779.84	-6.8984	0	0	1.17586e+06	2222.80	0.07	0.39	0.058014	0.0505961	
-k4_N4_tileable_90nm.xml	ex5p.blif	common	15.22	vpr	52.07 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	346	8	-1	-1	success	v8.0.0-6725-gff83963de-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64	2022-11-01T15:38:22	LAPTOP-CVNHOGSN	/home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks	53324	8	63	1072	1135	0	909	417	21	21	441	clb	auto	14.2 MiB	0.10	11660	52.1 MiB	0.46	0.00	7.1886	-311.061	-7.1886	nan	0.20	0.000496	0.0003719	0.0573232	0.0458367	56	22886	46	804782	771343	1.13430e+06	2572.11	12.88	0.310125	0.253318	18533	21	8880	28500	4332796	1534540	7.97924	nan	-339.269	-7.97924	0	0	1.45200e+06	3292.52	0.08	0.50	0.0368923	0.0322975	
-k4_N4_tileable_90nm.xml	s298.blif	common	21.05	vpr	75.85 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	571	4	-1	-1	success	v8.0.0-6725-gff83963de-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64	2022-11-01T15:38:22	LAPTOP-CVNHOGSN	/home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks	77672	4	6	1942	1948	1	1193	581	26	26	676	clb	auto	21.3 MiB	0.14	14254	75.9 MiB	0.69	0.01	13.2884	-103	-13.2884	13.2884	0.33	0.0008181	0.0006197	0.0966404	0.0764946	42	26119	42	1.28409e+06	1.27294e+06	1.41510e+06	2093.35	17.58	0.615507	0.493511	22147	19	9442	45483	4771423	1297512	13.6006	13.6006	-107.558	-13.6006	0	0	1.86822e+06	2210.912	0.19	0.67	0.0640435	0.0560669	
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
+k4_N4_tileable_90nm.xml	diffeq.blif	common	19.81	vpr	62.34 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	438	64	-1	-1	success	v8.0.0-13020-g9db19397a	Release IPO VTR_ASSERT_LEVEL=3	GNU 13.3.0 on Linux-6.8.0-57-generic x86_64	2025-04-20T14:55:09	agent-3	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	63832	64	39	1935	1974	1	1077	541	23	23	529	clb	auto	23.1 MiB	0.33	23383	10407	130518	33236	93921	3361	62.3 MiB	1.45	0.02	13.1424	7.01436	-1186.76	-7.01436	7.01436	0.50	0.00278506	0.0021586	0.190009	0.145283	-1	-1	-1	-1	30	18484	49	983127	976439	713134.	1348.08	14.21	1.06254	0.869067	34090	111051	-1	19671	23	8649	30686	3584279	1256529	7.46036	7.46036	-1487.87	-7.46036	0	0	855979.	1618.11	0.12	1.13	-1	-1	-1	0.12	0.186892	0.161913	
+k4_N4_tileable_90nm.xml	ex5p.blif	common	24.85	vpr	58.21 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	366	8	-1	-1	success	v8.0.0-13020-g9db19397a	Release IPO VTR_ASSERT_LEVEL=3	GNU 13.3.0 on Linux-6.8.0-57-generic x86_64	2025-04-20T14:55:09	agent-3	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	59604	8	63	1072	1135	0	894	437	22	22	484	clb	auto	19.0 MiB	0.26	20320	12148	81630	19773	60101	1756	58.1 MiB	0.95	0.02	7.91494	5.42874	-233.124	-5.42874	nan	0.46	0.00184499	0.00135252	0.103436	0.0807114	-1	-1	-1	-1	58	21250	25	891726	815929	1.11794e+06	2309.80	19.84	0.848059	0.694504	50136	186432	-1	21807	22	9790	33292	5274291	1466232	5.49118	nan	-247.625	-5.49118	0	0	1.39817e+06	2888.78	0.20	1.26	-1	-1	-1	0.20	0.112893	0.0976021	
+k4_N4_tileable_90nm.xml	s298.blif	common	37.04	vpr	68.60 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	580	4	-1	-1	success	v8.0.0-13020-g9db19397a	Release IPO VTR_ASSERT_LEVEL=3	GNU 13.3.0 on Linux-6.8.0-57-generic x86_64	2025-04-20T14:55:09	agent-3	/home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks	70248	4	6	1942	1948	1	1169	590	27	27	729	clb	auto	25.2 MiB	0.34	27324	13487	148970	40500	107491	979	68.6 MiB	1.82	0.03	15.4416	9.90815	-77.1816	-9.90815	9.90815	0.71	0.0031275	0.00242	0.2127	0.16542	-1	-1	-1	-1	34	24602	39	1.39333e+06	1.29301e+06	1.12707e+06	1546.05	28.80	1.56376	1.28245	50282	172723	-1	28340	30	12129	58881	11129903	3411240	10.0924	10.0924	-86.1832	-10.0924	0	0	1.32680e+06	1820.03	0.17	2.63	-1	-1	-1	0.17	0.220331	0.186786