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moving func_multiclock
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‎vtr_flow/tasks/regression_tests/vtr_reg_multiclock/README.md

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##ODIN-II Regression
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`task_list.txt` in this directory points to a set of tasks in the VTR regression suite, `vtr_reg_nightly_test2`. These tasks are referred to in
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[`light_suite`](https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/ODIN_II/regression_test/benchmark/suite/light_suite/task_list.conf) which is part of a series of ODIN-II regression tests. `light_suite` is currently being run by CI under the name`odin_reg_basic`. Not the whole of VTR_flow is tested in ODIN-II regressions tests (only logic synthesis and elaboration) hence why these tasks are put under `vtr_reg_nightly_test2` so that entirety of the flow gets tested by the CI.
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`task_list.txt` in this directory points to a set of tasks in the same directory. These tasks are referred to in
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[`light_suite`](https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/ODIN_II/regression_test/benchmark/suite/light_suite/task_list.conf) which is part of a series of ODIN-II regression tests. `light_suite` is currently being run by CI under the name`odin_reg_basic`. First, Odin specific tests are run then the task_list is run by `run_vtr_task.py`. Thus, the entirety of the flow is tested for `vtr_reg_multiclock` tasks by CI.

‎vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/README.md

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The tasks inside this directory tests that VTR can correctly handle multi-clock designs in different ways. The default way to handle multiple clocks is iterative.

‎vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/config.txt

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##############################################
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# Configuration file for running experiments
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##############################################
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script_params=-blanket_bb -use_odin_simulation
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# Path to directory of circuits to use
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circuits_dir=benchmarks/verilog
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# Path to directory of architectures to use
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archs_dir=arch/timing
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# Add circuits to list to sweep (basic bm)
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circuit_list_add=multiclock_output_and_latch.v
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circuit_list_add=multiclock_reader_writer.v
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circuit_list_add=multiclock_separate_and_latch.v
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# Add architectures to list to sweep
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arch_list_add=k6_frac_N10_mem32K_40nm.xml
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# Parse info and how to parse
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parse_file=vpr_standard.txt
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# How to parse QoR info
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qor_parse_file=qor_standard.txt
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# Pass requirements
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pass_requirements_file=pass_requirements.txt

‎vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt

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arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time
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k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.26 0.01 6744 1 0.02 -1 -1 35528 -1 -1 2 6 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 25080 6 1 13 14 2 8 9 4 4 16 clb auto 0.00 13 0.00 0.00 0.875884 -3.21829 -0.875884 0.545 0.01 9.152e-06 6.411e-06 0.00127579 0.000834052 20 13 2 107788 107788 10441.3 652.579 0.02 0.00190451 0.00132149 13 11 27 27 298 166 1.17974 0.545 -3.80732 -1.17974 0 0 13748.8 859.301 0.00 0.00 0.000371941 0.000300732
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k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.37 0.02 7180 1 0.02 -1 -1 35560 -1 -1 2 3 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 25104 3 1 25 26 2 8 6 4 4 16 clb auto 0.01 16 0.00 0.00 0.571 -8.56916 -0.571 0.557849 0.01 2.6811e-05 1.912e-05 0.000267223 0.000232957 20 21 4 107788 107788 10441.3 652.579 0.02 0.00146154 0.00126639 14 2 7 7 87 53 0.639606 0.557849 -8.83917 -0.639606 0 0 13748.8 859.301 0.00 0.00 0.000657086 0.000610546
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k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 0.24 0.01 6708 1 0.00 -1 -1 33668 -1 -1 2 6 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 25196 6 2 10 12 2 8 10 4 4 16 clb auto 0.00 12 0.00 0.00 0.543757 -1.83465 -0.543757 nan 0.01 7.375e-06 4.815e-06 0.000820477 0.000473849 20 15 6 107788 107788 10441.3 652.579 0.02 0.00127841 0.000806185 12 3 10 10 126 76 0.641597 nan -2.12623 -0.641597 0 0 13748.8 859.301 0.00 0.00 0.000145432 0.000113509

‎vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/config.txt

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##############################################
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# Configuration file for running experiments
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##############################################
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script_params=-iterative_bb -use_odin_simulation
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# Path to directory of circuits to use
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circuits_dir=benchmarks/verilog
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# Path to directory of architectures to use
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archs_dir=arch/timing
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# Add circuits to list to sweep (basic bm)
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circuit_list_add=multiclock_output_and_latch.v
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circuit_list_add=multiclock_reader_writer.v
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circuit_list_add=multiclock_separate_and_latch.v
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# Add architectures to list to sweep
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arch_list_add=k6_frac_N10_mem32K_40nm.xml
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# Parse info and how to parse
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parse_file=vpr_standard.txt
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# How to parse QoR info
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qor_parse_file=qor_standard.txt
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# Pass requirements
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pass_requirements_file=pass_requirements.txt

‎vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt

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arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time
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k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.32 0.01 6736 1 0.02 -1 -1 35432 -1 -1 2 6 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 25056 6 1 13 14 2 8 9 4 4 16 clb auto 0.00 13 0.00 0.00 0.875884 -3.21829 -0.875884 0.545 0.01 9.133e-06 6.332e-06 0.00137103 0.000893379 20 13 2 107788 107788 10441.3 652.579 0.02 0.00202846 0.00140832 13 11 27 27 298 166 1.17974 0.545 -3.80732 -1.17974 0 0 13748.8 859.301 0.00 0.00 0.000363437 0.000297087
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k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.44 0.02 7156 1 0.02 -1 -1 35752 -1 -1 2 3 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 25232 3 1 23 24 2 8 6 4 4 16 clb auto 0.01 16 0.00 0.00 0.571 -8.02416 -0.571 0.557849 0.01 2.6392e-05 1.8474e-05 0.000392837 0.000356428 20 21 4 107788 107788 10441.3 652.579 0.02 0.00161969 0.00141089 14 2 7 7 87 53 0.639606 0.557849 -8.29417 -0.639606 0 0 13748.8 859.301 0.00 0.00 0.000617072 0.000570262
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k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 0.29 0.01 6724 1 0.01 -1 -1 33208 -1 -1 2 6 0 0 success v8.0.0-3544-g00617ff76 Release VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-53-generic x86_64 2021-05-24T22:53:36 CASA44 /home/casauser/Desktop/Repos/sdamghan 24812 6 2 10 12 2 8 10 4 4 16 clb auto 0.00 12 0.00 0.00 0.543757 -1.83465 -0.543757 nan 0.01 9.515e-06 6.506e-06 0.000866896 0.000551504 20 16 8 107788 107788 10441.3 652.579 0.02 0.00144256 0.000972468 21 4 13 13 358 237 0.81248 nan -2.64176 -0.81248 0 0 13748.8 859.301 0.00 0.00 0.000169618 0.000131886

‎vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/config.txt

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##############################################
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# Configuration file for running experiments #
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##############################################
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# Path to directory of circuits to use
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circuits_dir=benchmarks/blif
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# Path to directory of architectures to use
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archs_dir=arch/timing
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# Add circuits to list to sweep
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# Single-clock
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circuit_list_add=bigkey.blif
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circuit_list_add=clma.blif
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circuit_list_add=diffeq.blif
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circuit_list_add=dsip.blif
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circuit_list_add=elliptic.blif
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circuit_list_add=frisc.blif
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circuit_list_add=s298.blif
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circuit_list_add=s38417.blif
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circuit_list_add=s38584.1.blif
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circuit_list_add=tseng.blif
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# Combinational
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#circuit_list_add=alu4.blif
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#circuit_list_add=apex2.blif
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#circuit_list_add=apex4.blif
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#circuit_list_add=des.blif
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#circuit_list_add=ex1010.blif
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#circuit_list_add=ex5p.blif
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#circuit_list_add=misex3.blif
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#circuit_list_add=pdc.blif
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#circuit_list_add=seq.blif
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#circuit_list_add=spla.blif
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# Add architectures to list to sweep
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arch_list_add=k6_frac_N10_40nm.xml
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# Parse info and how to parse
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parse_file=vpr_standard.txt
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# How to parse QoR info
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qor_parse_file=qor_standard.txt
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# Pass requirements
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pass_requirements_file=pass_requirements.txt
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# Script parameters
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script_params=-starting_stage abc

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