Update max mem usage

Author: jmah76

vtr_flow/parse/pass_requirements/common/pass_requirements.vpr_route_fixed_chan_width.txt

@@ -13,4 +13,4 @@ crit_path_route_time;RangeAbs(0.10,10.0,2)
 #We set a 100MiB minimum threshold since the memory 
 #alloctor (e.g. TBB vs glibc) can cause a difference
 #particularly on small benchmarks
-max_vpr_mem;RangeAbs(0.8,1.2,102400)
+max_vpr_mem;RangeAbs(0.8,1.203,102400)

vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt

@@ -21,4 +21,4 @@ stratixiv_arch.timing.xml	ucsb_152_tap_fir_stratixiv_arch_timing.blif	common	54.
 stratixiv_arch.timing.xml	uoft_raytracer_stratixiv_arch_timing.blif	common	678.97		964	982	19	34	0	0	success	v8.0.0-4099-g0082ba205	release IPO VTR_ASSERT_LEVEL=2	GNU 7.5.0 on Linux-4.15.0-60-generic x86_64	2021-08-02T02:41:49	betzgrp-wintermute.eecg.utoronto.ca	/home/ahmadi55/vtr-verilog-to-routing/vtr_flow	2781748	542	422	37277	26038	1	20655	1999	147	109	16023	io	auto	41.73	267816	73.62	0.80	7.80246	-38033.5	-6.80246	7.6263	258.47	0.0892357	0.0697083	13.6631	10.2442	362796	92851	202881	211513388	35702086	0	0	2.96650e+08	18514.0	55	8.53312	8.20447	-44732.7	-7.53312	0	0	41.77	24.7555	19.7387	200.64	
 stratixiv_arch.timing.xml	wb_conmax_stratixiv_arch_timing.blif	common	799.35		1107	724	0	0	0	0	success	v8.0.0-4099-g0082ba205	release IPO VTR_ASSERT_LEVEL=2	GNU 7.5.0 on Linux-4.15.0-60-generic x86_64	2021-08-02T02:41:49	betzgrp-wintermute.eecg.utoronto.ca	/home/ahmadi55/vtr-verilog-to-routing/vtr_flow	3223976	403	704	15490	16194	1	8415	1831	167	124	20708	io	auto	37.55	190229	16.71	0.14	11.4027	-21636.9	-10.4027	4.89489	400.55	0.0371088	0.0262547	5.13621	3.50481	233299	26413	105009	64404491	4696027	0	0	3.84012e+08	18544.1	14	11.8994	5.31154	-27542.3	-10.8994	0	0	7.34	6.87555	4.97917	259.42	
 stratixiv_arch.timing.xml	picosoc_stratixiv_arch_timing.blif	common	89.94		35	730	0	6	0	0	success	v8.0.0-4099-g0082ba205	release IPO VTR_ASSERT_LEVEL=2	GNU 7.5.0 on Linux-4.15.0-60-generic x86_64	2021-08-02T02:41:49	betzgrp-wintermute.eecg.utoronto.ca	/home/ahmadi55/vtr-verilog-to-routing/vtr_flow	1046032	18	17	16969	16357	1	6291	771	39	29	1131	LAB	auto	39.14	82220	9.36	0.08	6.86051	-43809.9	-5.86051	6.86051	4.27	0.0198281	0.0155483	3.08359	2.01596	116615	27639	146882	73829529	5721062	0	0	2.05958e+07	18210.3	43	7.27333	7.27333	-49633.6	-6.27333	0	0	10.96	6.52073	4.82028	9.83	
-stratixiv_arch.timing.xml	murax_stratixiv_arch_timing.blif	common	16.85		35	76	0	8	0	0	success	v8.0.0-4099-g0082ba205	release IPO VTR_ASSERT_LEVEL=2	GNU 7.5.0 on Linux-4.15.0-60-generic x86_64	2021-08-02T02:41:49	betzgrp-wintermute.eecg.utoronto.ca	/home/ahmadi55/vtr-verilog-to-routing/vtr_flow	120200	18	17	2291	2142	1	1504	119	16	12	192	LAB M9K	auto	4.08	10271	0.96	0.01	4.965	-3328.06	-3.965	3.70554	0.09	0.00544208	0.00414461	0.470524	0.35424	14141	4076	9559	7859416	739818	0	0	3.35078e+06	17452.0	20	5.1517	3.94454	-3676.27	-4.1517	0	0	0.88	0.737841	0.591727	0.41	
+stratixiv_arch.timing.xml	murax_stratixiv_arch_timing.blif	common	16.85		35	76	0	8	0	0	success	v8.0.0-4099-g0082ba205	release IPO VTR_ASSERT_LEVEL=2	GNU 7.5.0 on Linux-4.15.0-60-generic x86_64	2021-08-02T02:41:49	betzgrp-wintermute.eecg.utoronto.ca	/home/ahmadi55/vtr-verilog-to-routing/vtr_flow	812136	18	17	2291	2142	1	1504	119	16	12	192	LAB M9K	auto	4.08	10271	0.96	0.01	4.965	-3328.06	-3.965	3.70554	0.09	0.00544208	0.00414461	0.470524	0.35424	14141	4076	9559	7859416	739818	0	0	3.35078e+06	17452.0	20	5.1517	3.94454	-3676.27	-4.1517	0	0	0.88	0.737841	0.591727	0.41