verilog-to-routing
diff --git a/‎vtr_flow/scripts/python_libs/vtr/__init__.py
Lines changed: 1 addition & 1 deletion b/‎vtr_flow/scripts/python_libs/vtr/__init__.py
Lines changed: 1 addition & 1 deletion
diff --git a/‎vtr_flow/scripts/python_libs/vtr/inspect.py renamed to ‎vtr_flow/scripts/python_libs/vtr/log_parse.py b/‎vtr_flow/scripts/python_libs/vtr/inspect.py renamed to ‎vtr_flow/scripts/python_libs/vtr/log_parse.py
@@ -19,7 +19,7 @@
     pretty_print_table,
     find_task_dir,
 )
-from .inspect import (
+from .log_parse import (
     determine_lut_size,
     determine_min_w,
     determine_memory_addr_width,
Original file line number	Diff line number	Diff line change
`@@ -19,7 +19,7 @@`
`19`	`19`	`pretty_print_table,`
`20`	`20`	`find_task_dir,`
`21`	`21`	`)`
`22`		`-from .inspect import (`
	`22`	`+from .log_parse import (`
`23`	`23`	`determine_lut_size,`
`24`	`24`	`determine_min_w,`
`25`	`25`	`determine_memory_addr_width,`