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Passes a Verilog/SystemVerilog/UHDM file to Yosys for performing elaboration.
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Passes a Verilog/SystemVerilog/UHDM file to Yosys to perform elaboration.
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The BLIF elaboration and partial mapping phases will be executed on the generated netlist by Odin-II, and all latches in the Yosys+Odin-II output file will be rising edge.
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Then ABC and VPR perform the default behaviour for the VTR flow, respectively.
Notifies ODIN II if the input BLIF is coarse-grained
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Notifies ODIN II if the input BLIF is coarse-grained.
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**Default:** False
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.. note::
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A coarse-grained BLIF file is defined as a BLIF file inclduing unmapped cells with the Yosys internal cell (listed `here <https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/b913727959e22ae7a535ac8b907d0aaa9a3eda3d/ODIN_II/SRC/enum_str.cpp#L402-L494>`_) format which are represented by the ``.subckt`` tag in coarse-grained BLIF.
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.. option:: -fflegalize
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Makes flip-flops rising edge for coarse-grained input BLIFs in the partial technology mapping phase (ODIN II synthesis flow generates rising edge FFs by default, should be used for Yosys+Odin-II)
Specify a parser for the Yosys synthesizer [yosys (Verilog-2005), surelog (UHDM), yosys-plugin (SystemVerilog)].
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The script considers the Yosys conventional Verilog parser if this argument is not used.
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The script uses the Yosys conventional Verilog parser if this argument is not used.
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**Default:** yosys
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.. note::
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The ``-parser`` option is only available for the Yosys standalone front-end.
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On the other hand, the Yosys+Odin-II front-end automatically determine the Yosys HDL parser according to the input file extension.
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If the input HDL type is not supported by the Yosys conventional Verilog front-end (i.e., ``read_verilog -sv``) and the Yosys plugins are not installed, the Yosys+Odin-II flow results in failure.
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Universal Hardware Data Model (UHDM) is a complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener.
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UHDM is used as a compiled interchange format in between SystemVerilog tools.
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The ``yosys-plugins`` parser, which represents the ``read_systemverilog`` command, reads SystemVerilog files directly in Yosys.
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It executes Surelog with provided filenames and converts them (in memory) into UHDM file. Then, this UHDM file is converted into Yosys AST. `[Yosys-SystemVerilog] <https://github.com/antmicro/yosys-systemverilog#usage>`_
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On the other hand, the ``surelog`` parser, which uses the ``read_uhdm`` Yosys command, walks the design tree and converts its nodes into Yosys AST nodes using Surelog. `[UHDM-Yosys <https://github.com/chipsalliance/UHDM-integration-tests#uhdm-yosys>`_, `Surelog] <https://github.com/chipsalliance/Surelog#surelog>`_
The following are simple command-line arguments and a description of what they do.
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It is assumed that they are being performed in the Odin-II directory.
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The following commands pass a Verilog/SystemVerilog/UHDM HDL file to Yosys for elaboration, then Odin-II performs the partial mapping and optimization into pure soft logic.
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Warnings and errors may appear regarding the HDL code by Yosys.
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.. code-block:: bash
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# Elaborate the input file using Yosys convetional Verilog parser and then partial map the coarse-grained netlist using Odin-II
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# Elaborate the input file using Yosys conventional Verilog parser and then partial map the coarse-grained netlist using Odin-II
Passes a Verilog/SystemVerilog/UHDM HDL file to Yosys for elaboration, then Odin-II performs the partial mapping and optimization.
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Warnings and errors may appear regarding the HDL code by Yosys.
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.. note::
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The entire log file of the Yosys elaboration for each run is outputted into a file called ``elaboration.yosys.log`` located in the same directory of the final output BLIF file.
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.. code-block:: bash
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./odin_II --elaborator yosys -v <path/to/Verilog/File> -a <path/to/arch/file> -o output.blif
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Passes a Verilog HDL file and architecture to Yosys+Odin-II, where it is synthesized.
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The following command passes a Verilog HDL file and architecture to Yosys+Odin-II, where it is synthesized.
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Yosys will use the HDL files to perform elaboration.
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Then, Odin-II will use the architecture to do partial technology mapping, and will output the BLIF in the current directory at ``./output.blif``.
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If the output BLIF file is not specified, ``default_out.blif`` is considered the output file name, again located in the current directory.
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.. code-block:: bash
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./odin_II --elaborator yosys -v <path/to/Verilog/File> -a <path/to/arch/file> -o output.blif
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.. note::
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Once the elaboration is fully executed, Yosys generates a coarse-grained BLIF file that the Odin-II BLIF reader will read to create a netlist. This file is named ``coarsen_netlist.yosys.blif`` located in the current directory.
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The following command passes a Tcl script file, including commands for the elaboration by Yosys, along with the architecture file.
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.. code-block:: bash
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./odin_II -S <path/to/Tcl/File> -a <path/to/arch/file> -o myModel.blif
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Passes a Tcl script file, including commands for the elaboration by Yosys, along with the architecture file.
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.. note::
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The Tcl script file should follow the same generic synthesis flow, brought as an example in the `$VTR_ROOT/ODIN_II/regression_test/tools/synth.tcl`.
Copy file name to clipboardExpand all lines: doc/src/yosys/quickstart.rst
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@@ -30,7 +30,7 @@ Building
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--------
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To build the VTR flow with the Yosys front-end you may use the VTR Makefile wrapper, by calling the ``make CMAKE_PARAMS="-DWITH_YOSYS=ON"`` command in the `$VTR_ROOT` directory.
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The compile flag ``-DWITH_YOSYS=ON`` should be passed to the CMake parameters to enable Yosys compilation process.
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The compile flag ``-DWITH_YOSYS=ON`` should be passed to the CMake parameters to enable the Yosys compilation process.
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