Adding comments based on review.

Also fixing a mistake in some no_complex_dsp tasks.
By mistake the complex_dsp_include file was included.

Author: aman26kbm

ODIN_II/regression_test/benchmark/task/koios/task.conf

@@ -6,15 +6,24 @@ regression_params=--disable_simulation --disable_parallel_jobs --verbose
 script_synthesis_params=--limit_ressource --time_limit 14400s
 script_simulation_params=--limit_ressource --time_limit 14400s
 
-# setup the architecture
+#-------------------------------------------------------
+# specify the directory to look for architecture file in
+#-------------------------------------------------------
 archs_dir=../vtr_flow/arch/COFFE_22nm
+
+#-------------------------------------------------------
+# specify the architecture file
+#-------------------------------------------------------
 arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml
 
-# setup the benchmarks
+#-------------------------------------------------------
+# specify the directory to look for benchmarks in
+#-------------------------------------------------------
 circuits_dir=../../../../vtr_flow/benchmarks/verilog/koios
-includes_dir=benchmarks/verilog/koios
-include_list_add=complex_dsp_include.v
 
+#-------------------------------------------------------
+# specify the benchmarks
+#-------------------------------------------------------
 circuit_list_add=tpu_like.small.v
 circuit_list_add=dla_like.small.v
 circuit_list_add=bnn.v
@@ -28,4 +37,18 @@ circuit_list_add=reduction_layer.v
 circuit_list_add=spmv.v
 circuit_list_add=softmax.v
 
+#-------------------------------------------------------
+# specify the directory to look for include file in
+#-------------------------------------------------------
+includes_dir=../../../../vtr_flow/benchmarks/verilog/koios
+
+#-------------------------------------------------------
+# specify the include files
+#-------------------------------------------------------
+# Some benchmarks instantiate complex dsp blocks to implement features
+# like native floating point math, cascade chains, etc. This functionality
+# is guarded under the `complex_dsp` macro. The complex_dsp_include.v file 
+# defines this macro, thereby enabling instantiations of the complex dsp.
+include_list_add=complex_dsp_include.v
+
 synthesis_parse_file=regression_test/parse_result/conf/synth.toml

vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios/config/config.txt

@@ -29,7 +29,11 @@ circuit_list_add=softmax.v
 # Add architectures to list to sweep
 arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml
 
-# Add include files to the list
+# Add include files to the list.
+# Some benchmarks instantiate complex dsp blocks to implement features
+# like native floating point math, cascade chains, etc. This functionality
+# is guarded under the `complex_dsp` macro. The complex_dsp_include.v file 
+# defines this macro, thereby enabling instantiations of the complex dsp.
 include_list_add=complex_dsp_include.v
 
 # Parse info and how to parse

vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_multi_arch/config/config.txt

@@ -28,7 +28,11 @@ arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.xml
 arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.densest.xml
 arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.denser.xml
 
-# Add include files to the list
+# Add include files to the list.
+# Some benchmarks instantiate complex dsp blocks to implement features
+# like native floating point math, cascade chains, etc. This functionality
+# is guarded under the `complex_dsp` macro. The complex_dsp_include.v file 
+# defines this macro, thereby enabling instantiations of the complex dsp.
 include_list_add=complex_dsp_include.v
 
 # Parse info and how to parse

vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_no_complex_dsp/config/config.txt

@@ -9,7 +9,12 @@ circuits_dir=benchmarks/verilog/koios
 # Path to directory of architectures to use
 archs_dir=arch/timing
 
-# Add circuits to list to sweep
+# Add circuits to list to sweep.
+# Some of these benchmarks are designs with complex_dsp blocks 
+# but in this task, we're running them without enabling these
+# blocks (that is, the macro `complex_dsp` is not defined).
+# Equivalent functionality is obtained through behavioral logic 
+# that gets mapped to soft logic.
 circuit_list_add=tpu_like.small.v
 circuit_list_add=dla_like.small.v
 circuit_list_add=bnn.v

vtr_flow/tasks/regression_tests/vtr_reg_strong/koios/config/config.txt

@@ -18,7 +18,11 @@ circuit_list_add=test.v
 # Add architectures to list to sweep
 arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml
 
-# Add include files to the list
+# Add include files to the list.
+# Some benchmarks instantiate complex dsp blocks to implement features
+# like native floating point math, cascade chains, etc. This functionality
+# is guarded under the `complex_dsp` macro. The complex_dsp_include.v file 
+# defines this macro, thereby enabling instantiations of the complex dsp.
 include_list_add=complex_dsp_include.v
 
 # Parse info and how to parse

vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_no_complex_dsp/config/config.txt

@@ -9,18 +9,17 @@ circuits_dir=benchmarks/verilog/koios
 # Path to directory of architectures to use
 archs_dir=arch/COFFE_22nm
 
-# Directory containing the verilog includes file(s)
-includes_dir=benchmarks/verilog/koios
-
-# Add circuits to list to sweep
+# Add circuits to list to sweep.
+# Some of these benchmarks are designs with complex_dsp blocks 
+# but in this task, we're running them without enabling these
+# blocks (that is, the macro `complex_dsp` is not defined).
+# Equivalent functionality is obtained through behavioral logic 
+# that gets mapped to soft logic.
 circuit_list_add=test.v
 
 # Add architectures to list to sweep
 arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml
 
-# Add include files to the list
-include_list_add=complex_dsp_include.v
-
 # Parse info and how to parse
 parse_file=vpr_standard.txt
 

vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios/config/config.txt

@@ -26,6 +26,10 @@ circuit_list_add=dla_like.medium.v
 arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml
 
 # Add include files to the list
+# Some benchmarks instantiate complex dsp blocks to implement features
+# like native floating point math, cascade chains, etc. This functionality
+# is guarded under the `complex_dsp` macro. The complex_dsp_include.v file 
+# defines this macro, thereby enabling instantiations of the complex dsp.
 include_list_add=complex_dsp_include.v
 
 # Parse info and how to parse

vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_no_complex_dsp/config/config.txt

@@ -9,10 +9,12 @@ circuits_dir=benchmarks/verilog/koios
 # Path to directory of architectures to use
 archs_dir=arch/COFFE_22nm
 
-# Directory containing the verilog includes file(s)
-includes_dir=benchmarks/verilog/koios
-
-# Add circuits to list to sweep
+# Add circuits to list to sweep.
+# Some of these benchmarks are designs with complex_dsp blocks 
+# but in this task, we're running them without enabling these
+# blocks (that is, the macro `complex_dsp` is not defined).
+# Equivalent functionality is obtained through behavioral logic 
+# that gets mapped to soft logic.
 circuit_list_add=clstm_like.small.v
 circuit_list_add=clstm_like.medium.v
 circuit_list_add=clstm_like.large.v
@@ -26,9 +28,6 @@ circuit_list_add=dla_like.medium.v
 # Add architectures to list to sweep
 arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml
 
-# Add include files to the list
-include_list_add=complex_dsp_include.v
-
 # Parse info and how to parse
 parse_file=vpr_standard.txt