vpr: interchange: add interchange netlist reading support

Signed-off-by: Alessandro Comodi <[email protected]>

Author: acomodi

libs/libarchfpga/src/physical_types.h

@@ -1732,6 +1732,12 @@ struct t_clock_arch_spec {
     std::vector<t_clock_connection_arch> clock_connections_arch;
 };
 
+struct t_lut_cell {
+    std::string name;
+    std::string init_param;
+    std::vector<std::string> inputs;
+};
+
 /*   Detailed routing architecture */
 struct t_arch {
     mutable vtr::string_internment strings;
@@ -1750,11 +1756,23 @@ struct t_arch {
     int num_switches;
     t_direct_inf* Directs = nullptr;
     int num_directs = 0;
+
     t_model* models = nullptr;
     t_model* model_library = nullptr;
+
     t_power_arch* power = nullptr;
     t_clock_arch* clocks = nullptr;
 
+    // Constants
+    std::string gnd_cell;
+    std::string vcc_cell;
+
+    std::string gnd_net = "$__gnd_net";
+    std::string vcc_net = "$__vcc_net";
+
+    // Luts
+    std::vector<t_lut_cell> lut_cells;
+
     //The name of the switch used for the input connection block (i.e. to
     //connect routing tracks to block pins).
     //This should correspond to a switch in Switches

libs/libarchfpga/src/read_fpga_interchange_arch.cpp

@@ -46,6 +46,7 @@ struct ArchReader {
     }
 
     void read_arch() {
+        process_luts();
         process_models();
     }
 
@@ -151,6 +152,14 @@ struct ArchReader {
                                "Model output ports can not have combinational sink ports");
             }
 
+            model_port->min_size = 1;
+            model_port->size = 1;
+            if (port.isBus()) {
+                int s = port.getBus().getBusStart();
+                int e = port.getBus().getBusEnd();
+                model_port->size = std::abs(e - s) + 1;
+            }
+
             port_names.insert(std::pair<std::string, enum PORTS>(model_port->name, dir));
             //Add the port
             if (dir == IN_PORT) {
@@ -163,6 +172,25 @@ struct ArchReader {
             }
         }
     }
+
+    void process_luts() {
+        // Add LUT Cell definitions
+        // This is helpful to understand which cells are LUTs
+        auto lut_def = ar_.getLutDefinitions();
+
+        for (auto lut_cell : lut_def.getLutCells()) {
+            t_lut_cell cell;
+            cell.name = lut_cell.getCell().cStr();
+            for (auto input : lut_cell.getInputPins())
+                cell.inputs.push_back(input.cStr());
+
+            auto equation = lut_cell.getEquation();
+            if (equation.isInitParam())
+                cell.init_param = equation.getInitParam().cStr();
+
+            arch_->lut_cells.push_back(cell);
+        }
+    }
 };
 
 void FPGAInterchangeReadArch(const char* FPGAInterchangeDeviceFile,

libs/libvtrutil/src/vtr_hash.h

@@ -15,6 +15,16 @@ inline void hash_combine(std::size_t& seed, const T& v) {
     seed ^= hasher(v) + 0x9e3779b9 + (seed << 6) + (seed >> 2);
 }
 
+struct hash_pair {
+    template<class T1, class T2>
+    std::size_t operator()(const std::pair<T1, T2>& pair) const noexcept {
+        auto hash1 = std::hash<T1>{}(pair.first);
+        auto hash2 = std::hash<T2>{}(pair.second);
+
+        return hash1 ^ hash2;
+    }
+};
+
 } // namespace vtr
 
 #endif

vpr/src/base/atom_netlist_utils.cpp

@@ -95,7 +95,10 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist) {
             AtomPinId pin = *netlist.block_pins(blk_id).begin();
 
             std::string blk_name = netlist.block_name(blk_id);
-            std::string out_name(blk_name.begin() + 4, blk_name.end()); //+4 to trim out: prefix
+
+            std::string out_prefix("out:");
+            int strip_size = blk_name.substr(0, out_prefix.size()) == out_prefix ? out_prefix.size() : 0;
+            std::string out_name(blk_name.begin() + strip_size, blk_name.end()); //+4 to trim out: prefix if present
 
             fprintf(f, "%s%s", INDENT, out_name.c_str());
 
@@ -307,7 +310,7 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist) {
             ports.push_back(port_id);
         }
 
-        fprintf(f, ".subckt %s \\\n", blk_model->name);
+        fprintf(f, ".subckt %s \\\n", netlist.block_name(blk_id).c_str());
         for (size_t i = 0; i < ports.size(); i++) {
             auto width = netlist.port_width(ports[i]);
             for (size_t j = 0; j < width; ++j) {

vpr/src/base/read_circuit.cpp

@@ -1,5 +1,6 @@
 #include "read_circuit.h"
 #include "read_blif.h"
+#include "read_interchange_netlist.h"
 #include "atom_netlist.h"
 #include "atom_netlist_utils.h"
 #include "echo_files.h"
@@ -21,20 +22,23 @@ static void process_circuit(AtomNetlist& netlist,
 
 static void show_circuit_stats(const AtomNetlist& netlist);
 
-AtomNetlist read_and_process_circuit(e_circuit_format circuit_format,
-                                     const char* circuit_file,
-                                     const t_model* user_models,
-                                     const t_model* library_models,
-                                     e_const_gen_inference const_gen_inference,
-                                     bool should_absorb_buffers,
-                                     bool should_sweep_dangling_primary_ios,
-                                     bool should_sweep_dangling_nets,
-                                     bool should_sweep_dangling_blocks,
-                                     bool should_sweep_constant_primary_outputs,
-                                     int verbosity) {
+AtomNetlist read_and_process_circuit(e_circuit_format circuit_format, t_vpr_setup& vpr_setup, t_arch& arch) {
+    // Options
+    const char* circuit_file = vpr_setup.PackerOpts.circuit_file_name.c_str();
+    const t_model* user_models = vpr_setup.user_models;
+    const t_model* library_models = vpr_setup.library_models;
+    e_const_gen_inference const_gen_inference = vpr_setup.NetlistOpts.const_gen_inference;
+    bool should_absorb_buffers = vpr_setup.NetlistOpts.absorb_buffer_luts;
+    bool should_sweep_dangling_primary_ios = vpr_setup.NetlistOpts.sweep_dangling_primary_ios;
+    bool should_sweep_dangling_nets = vpr_setup.NetlistOpts.sweep_dangling_nets;
+    bool should_sweep_dangling_blocks = vpr_setup.NetlistOpts.sweep_dangling_blocks;
+    bool should_sweep_constant_primary_outputs = vpr_setup.NetlistOpts.sweep_constant_primary_outputs;
+    bool verbosity = vpr_setup.NetlistOpts.netlist_verbosity;
+
     if (circuit_format == e_circuit_format::AUTO) {
         auto name_ext = vtr::split_ext(circuit_file);
 
+        VTR_LOG("%s\n", circuit_file);
         if (name_ext[1] == ".blif") {
             circuit_format = e_circuit_format::BLIF;
         } else if (name_ext[1] == ".eblif") {
@@ -49,10 +53,18 @@ AtomNetlist read_and_process_circuit(e_circuit_format circuit_format,
     {
         vtr::ScopedStartFinishTimer t("Load circuit");
 
-        VTR_ASSERT(circuit_format == e_circuit_format::BLIF
-                   || circuit_format == e_circuit_format::EBLIF);
-
-        netlist = read_blif(circuit_format, circuit_file, user_models, library_models);
+        switch (circuit_format) {
+            case e_circuit_format::BLIF:
+            case e_circuit_format::EBLIF:
+                netlist = read_blif(circuit_format, circuit_file, user_models, library_models);
+                break;
+            case e_circuit_format::FPGA_INTERCHANGE:
+                netlist = read_interchange_netlist(circuit_file, arch);
+                break;
+            default:
+                VTR_ASSERT(false);
+                break;
+        }
     }
 
     if (isEchoFileEnabled(E_ECHO_ATOM_NETLIST_ORIG)) {

vpr/src/base/read_circuit.h

@@ -5,20 +5,11 @@
 #include "vpr_types.h"
 
 enum class e_circuit_format {
-    AUTO, ///<Infer from file extension
-    BLIF, ///<Strict structural BLIF
-    EBLIF ///<Structural blif with extensions
+    AUTO,            ///<Infer from file extension
+    BLIF,            ///<Strict structural BLIF
+    EBLIF,           ///<Structural blif with extensions
+    FPGA_INTERCHANGE ///<FPGA Interhange logical netlis format
 };
 
-AtomNetlist read_and_process_circuit(const e_circuit_format circuit_format,
-                                     const char* circuit_file,
-                                     const t_model* user_models,
-                                     const t_model* library_models,
-                                     e_const_gen_inference const_gen_inference,
-                                     bool should_absorb_buffers,
-                                     bool should_sweep_dangling_primary_ios,
-                                     bool should_sweep_dangling_nets,
-                                     bool should_sweep_dangling_blocks,
-                                     bool should_sweep_constant_primary_outputs,
-                                     int verbosity);
+AtomNetlist read_and_process_circuit(e_circuit_format circuit_format, t_vpr_setup& vpr_setup, t_arch& arch);
 #endif