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Odin: Update defparam tests
 this commit update the defparams test to test for different overrides hierarchy depth
1 parent f617a87 commit 27645d4

11 files changed

+346
-1
lines changed

‎ODIN_II/regression_test/benchmark/verilog/keywords/defparam/defparam_depth_1.v

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module simple_op(in1,in2,out1,out2);
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parameter width1 = 2;
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parameter width2 = 8;
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input [width1-1:0] in1;
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input [width2-1:0] in2;
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output [width1-1:0] out1;
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output [width2-1:0] out2;
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defparam m1.width = 2;
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defparam m2.width = 8;
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assg m1 (in1,out1);
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assg m2 (in2,out2);
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endmodule
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module assg(in,out);
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parameter width = 3;
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input [width-1:0] in;
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output [width-1:0] out;
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assign out = in;
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endmodule

‎ODIN_II/regression_test/benchmark/verilog/keywords/defparam/defparam_depth_1_failure.v

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module simple_op(in1,in2,out1,out2);
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parameter width1 = 2;
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parameter width2 = 8;
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input [width1-1:0] in1;
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input [width2-1:0] in2;
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output [width1-1:0] out1;
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output [width2-1:0] out2;
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defparam m1.width = 2;
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defparam m2.width = 8;
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assg m1 (in1,out1);
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assg m2 (in2,out2);
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endmodule
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module assg(in,out);
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localparam width = 3;
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input [width-1:0] in;
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output [width-1:0] out;
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assign out = in;
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endmodule

‎ODIN_II/regression_test/benchmark/verilog/keywords/defparam/defparam_depth_1_failure_input

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GLOBAL_SIM_BASE_CLK in1 in2
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1 0X2 0X67
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0 0X2 0X41
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1 0X1 0X3c
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0 0X3 0Xf5
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1 0X1 0X2a
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0 0X0 0Xae
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1 0X3 0X55
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0 0X1 0Xc1
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1 0X1 0X08
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0 0X1 0X5c
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1 0X2 0X5c
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0 0X3 0X7f
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1 0X1 0X4d
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0 0X3 0Xa8
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1 0X1 0X8f
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0 0X1 0Xd0
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1 0X3 0X6c
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0 0X2 0Xcf
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1 0X1 0X0e
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0 0X0 0Xa7
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1 0X1 0X99
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0 0X0 0X27
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1 0X1 0Xe8
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0 0X2 0X20
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1 0X0 0Xc1
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0 0X2 0X97
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1 0X3 0X4e
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0 0X0 0X60
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1 0X2 0X18
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0 0X2 0X7d
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1 0X1 0X0b
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0 0X2 0X02
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1 0X1 0X11
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0 0X3 0Xc9
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1 0X0 0Xe9
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0 0X2 0X09
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1 0X1 0X04
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0 0X1 0X47

‎ODIN_II/regression_test/benchmark/verilog/keywords/defparam/defparam_depth_1_failure_output

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out1 out2
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0X2 0X7
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0X2 0X1
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0X1 0X4
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0X3 0X5
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0X1 0X2
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0X0 0X6
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0X3 0X5
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0X1 0X1
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0X1 0X0
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0X1 0X4
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0X2 0X4
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0X3 0X7
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0X1 0X5
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0X3 0X0
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0X1 0X7
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0X1 0X0
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0X3 0X4
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0X2 0X7
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0X1 0X6
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0X0 0X7
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0X1 0X1
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0X0 0X7
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0X1 0X0
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0X2 0X0
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0X0 0X1
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0X2 0X7
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0X3 0X6
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0X0 0X0
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0X2 0X0
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0X2 0X5
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0X1 0X3
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0X2 0X2
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0X1 0X1
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0X3 0X1
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0X0 0X1
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0X2 0X1
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0X1 0X4
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0X1 0X7

‎ODIN_II/regression_test/benchmark/verilog/keywords/defparam/defparam_depth_1_input

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GLOBAL_SIM_BASE_CLK in1 in2
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1 0X2 0X67
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0 0X2 0X41
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1 0X1 0X3c
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0 0X3 0Xf5
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1 0X1 0X2a
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0 0X0 0Xae
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1 0X3 0X55
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0 0X1 0Xc1
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1 0X1 0X08
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0 0X1 0X5c
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1 0X2 0X5c
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0 0X3 0X7f
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1 0X1 0X4d
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0 0X3 0Xa8
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1 0X1 0X8f
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0 0X1 0Xd0
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1 0X3 0X6c
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0 0X2 0Xcf
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1 0X1 0X0e
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0 0X0 0Xa7
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1 0X1 0X99
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0 0X0 0X27
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1 0X1 0Xe8
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0 0X2 0X20
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1 0X0 0Xc1
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0 0X2 0X97
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1 0X3 0X4e
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0 0X0 0X60
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1 0X2 0X18
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0 0X2 0X7d
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1 0X1 0X0b
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0 0X2 0X02
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1 0X1 0X11
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0 0X3 0Xc9
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1 0X0 0Xe9
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0 0X2 0X09
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1 0X1 0X04
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0 0X1 0X47

‎ODIN_II/regression_test/benchmark/verilog/keywords/defparam/defparam_depth_1_output

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out1 out2
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0X2 0X67
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0X2 0X41
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0X1 0X3c
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0X3 0Xf5
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0X1 0X2a
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0X0 0Xae
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0X3 0X55
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0X1 0Xc1
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0X1 0X08
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0X1 0X5c
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0X2 0X5c
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0X3 0X7f
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0X1 0X4d
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0X3 0Xa8
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0X1 0X8f
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0X1 0Xd0
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0X3 0X6c
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0X2 0Xcf
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0X1 0X0e
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0X0 0Xa7
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0X1 0X99
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0X0 0X27
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0X1 0Xe8
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0X2 0X20
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0X0 0Xc1
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0X2 0X97
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0X3 0X4e
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0X0 0X60
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0X2 0X18
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0X2 0X7d
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0X1 0X0b
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0X2 0X02
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0X1 0X11
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0X3 0Xc9
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0X0 0Xe9
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0X2 0X09
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0X1 0X04
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0X1 0X47

‎ODIN_II/regression_test/benchmark/verilog/keywords/defparam/defparam_depth_2.v

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module simple_op(in1,in2,out1,out2);
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parameter width1 = 2;
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parameter width2 = 8;
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input [width1-1:0] in1;
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input [width2-1:0] in2;
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output [width1-1:0] out1;
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output [width2-1:0] out2;
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defparam m1.width = 2;
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defparam m2.width = 8;
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defparam m1.g1.width = 2;
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defparam m2.g1.width = 8;
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assg1 m1 (in1,out1);
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assg1 m2 (in2,out2);
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endmodule
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module assg1(in,out);
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parameter width = 3;
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input [width-1:0] in;
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output [width-1:0] out;
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assg2 g1 (in,out);
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endmodule
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module assg2(in,out);
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parameter width = 2;
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input [width-1:0] in;
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output [width-1:0] out;
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assign out = in;
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endmodule

‎ODIN_II/regression_test/benchmark/verilog/keywords/defparam/defparam_depth_2_input

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GLOBAL_SIM_BASE_CLK in1 in2
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1 0X2 0X67
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0 0X2 0X41
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1 0X1 0X3c
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0 0X3 0Xf5
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1 0X1 0X2a
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0 0X0 0Xae
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1 0X3 0X55
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0 0X1 0Xc1
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1 0X1 0X08
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0 0X1 0X5c
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1 0X2 0X5c
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0 0X3 0X7f
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1 0X1 0X4d
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0 0X3 0Xa8
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1 0X1 0X8f
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0 0X1 0Xd0
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1 0X3 0X6c
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0 0X2 0Xcf
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1 0X1 0X0e
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0 0X0 0Xa7
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1 0X1 0X99
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0 0X0 0X27
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1 0X1 0Xe8
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0 0X2 0X20
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1 0X0 0Xc1
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0 0X2 0X97
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1 0X3 0X4e
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0 0X0 0X60
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1 0X2 0X18
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0 0X2 0X7d
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1 0X1 0X0b
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0 0X2 0X02
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1 0X1 0X11
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0 0X3 0Xc9
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1 0X0 0Xe9
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0 0X2 0X09
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1 0X1 0X04
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0 0X1 0X47

‎ODIN_II/regression_test/benchmark/verilog/keywords/defparam/defparam_depth_2_output

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out1 out2
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0X2 0X67
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0X2 0X41
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0X1 0X3c
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0X3 0Xf5
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0X1 0X2a
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0X0 0Xae
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0X3 0X55
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0X1 0Xc1
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0X1 0X08
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0X1 0X5c
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0X2 0X5c
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0X3 0X7f
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0X1 0X4d
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0X3 0Xa8
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0X1 0X8f
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0X1 0Xd0
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0X3 0X6c
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0X2 0Xcf
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0X1 0X0e
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0X0 0Xa7
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0X1 0X99
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0X0 0X27
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0X1 0Xe8
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0X2 0X20
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0X0 0Xc1
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0X2 0X97
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0X3 0X4e
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0X0 0X60
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0X2 0X18
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0X2 0X7d
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0X1 0X0b
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0X2 0X02
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0X1 0X11
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0X3 0Xc9
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0X0 0Xe9
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0X2 0X09
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0X1 0X04
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0X1 0X47

‎ODIN_II/regression_test/benchmark/verilog/keywords/defparam/defparam_failure.v

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module simple_op(in1,in2,out1,out2);
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parameter width1 = 3;
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parameter width2 = 6;
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parameter width2 = 4;
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input [width1-1:0] in1;
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input [width2-1:0] in2;

‎ODIN_II/regression_test/benchmark/verilog/keywords/defparam/defparam_simple_failure.v

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module simple_op(in1,out1);
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parameter width1 = 4;
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input [width1-1:0] in1;
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output [width1-1:0] out1;
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assg m1 (in1,out1);
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endmodule
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module assg(in,out);
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localparam width = 3;
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input [width-1:0] in;
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output [width-1:0] out;
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assign out = in;
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endmodule
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module params;
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defparam
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simple_op.m1.width = 4;
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endmodule

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