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Adding support for multiple input ports on the CLB. This is common in newer arch files.
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-17
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+21
-17
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vpr/src/power/power_sizing.cpp

Lines changed: 21 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -79,24 +79,28 @@ static double power_count_transistors_connectionbox() {
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auto& power_ctx = g_vpr_ctx.power();
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auto type = find_most_common_block_type(device_ctx.grid);
82-
VTR_ASSERT(type->pb_graph_head->num_input_ports == 1);
83-
inputs = type->pb_graph_head->num_input_pins[0];
84-
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/* Buffers from Tracks */
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buffer_size = power_ctx.commonly_used->max_seg_to_IPIN_fanout
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* (power_ctx.commonly_used->NMOS_1X_C_d
88-
/ power_ctx.commonly_used->INV_1X_C_in)
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/ power_ctx.arch->logical_effort_factor;
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buffer_size = std::max(1.0F, buffer_size);
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transistor_cnt += power_ctx.solution_inf.channel_width
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* power_count_transistors_buffer(buffer_size);
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94-
/* Muxes to IPINs */
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transistor_cnt += inputs
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* power_count_transistors_mux(
97-
power_get_mux_arch(power_ctx.commonly_used->max_IPIN_fanin,
98-
power_ctx.arch->mux_transistor_size));
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83+
//For each port on the most common block, look at the number of
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//input pins this port has and estimate the transistor count based
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//on the size muxes that drive these input pins.
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for (int i=0; i < type->pb_graph_head->num_input_ports; i++) {
87+
inputs = type->pb_graph_head->num_input_pins[i];
88+
89+
/* Buffers from Tracks */
90+
buffer_size = power_ctx.commonly_used->max_seg_to_IPIN_fanout
91+
* (power_ctx.commonly_used->NMOS_1X_C_d
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/ power_ctx.commonly_used->INV_1X_C_in)
93+
/ power_ctx.arch->logical_effort_factor;
94+
buffer_size = std::max(1.0F, buffer_size);
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transistor_cnt += power_ctx.solution_inf.channel_width
96+
* power_count_transistors_buffer(buffer_size);
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/* Muxes to IPINs */
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transistor_cnt += inputs
100+
* power_count_transistors_mux(
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power_get_mux_arch(power_ctx.commonly_used->max_IPIN_fanin,
102+
power_ctx.arch->mux_transistor_size));
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}
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return transistor_cnt;
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}
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