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amirarjmand93amirarjmand93
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yosys_update -> v0.38
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‎yosys/.github/workflows/codeql.yml

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@@ -14,10 +14,10 @@ jobs:
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run: sudo apt-get install bison flex libreadline-dev tcl-dev libffi-dev
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- name: Checkout repository
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uses: actions/checkout@v3
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uses: actions/checkout@v4
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- name: Initialize CodeQL
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uses: github/codeql-action/init@v2
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uses: github/codeql-action/init@v3
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with:
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languages: cpp
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queries: security-extended,security-and-quality
@@ -26,4 +26,4 @@ jobs:
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run: make yosys -j6
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- name: Perform CodeQL Analysis
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uses: github/codeql-action/analyze@v2
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uses: github/codeql-action/analyze@v3

‎yosys/.github/workflows/emcc.yml

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@@ -6,13 +6,13 @@ jobs:
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emcc:
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runs-on: ubuntu-latest
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steps:
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- uses: mymindstorm/setup-emsdk@v11
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- uses: actions/checkout@v3
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- uses: mymindstorm/setup-emsdk@v14
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- uses: actions/checkout@v4
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- name: Build
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run: |
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make config-emcc
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make YOSYS_VER=latest
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- uses: actions/upload-artifact@v3
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- uses: actions/upload-artifact@v4
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with:
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name: yosysjs
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path: yosysjs-latest.zip

‎yosys/.github/workflows/test-linux.yml

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@@ -43,6 +43,7 @@ jobs:
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sudo apt-get install $CC $CXX
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echo "CC=$CC" >> $GITHUB_ENV
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echo "CXX=$CXX" >> $GITHUB_ENV
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echo "CXXFLAGS=-Wp,-D_GLIBCXX_ASSERTIONS" >> $GITHUB_ENV
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env:
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CC: ${{ matrix.compiler }}
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$CXX --version
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- name: Checkout Yosys
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uses: actions/checkout@v3
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uses: actions/checkout@v4
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- name: Get iverilog
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shell: bash
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run: |
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git clone https://github.com/steveicarus/iverilog.git
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cd iverilog
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git checkout 192b6aec96fde982e6ddcb28b346d5893aa8e874
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echo "IVERILOG_GIT=$(git rev-parse HEAD)" >> $GITHUB_ENV
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- name: Cache iverilog
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id: cache-iverilog
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uses: actions/cache@v3
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uses: actions/cache@v4
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with:
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path: .local/
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key: ${{ matrix.os.id }}-${{ hashFiles('iverilog/.git/refs/heads/master') }}
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key: ${{ matrix.os.id }}-${{ env.IVERILOG_GIT }}
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- name: Build iverilog
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if: steps.cache-iverilog.outputs.cache-hit != 'true'
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shell: bash
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run: |
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make config-${CC%%-*}
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make -j${{ env.procs }} CCXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC
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make -j${{ env.procs }} CXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC
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- name: Run tests
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if: (matrix.cpp_std == 'c++11') && (matrix.compiler == 'gcc-11')
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shell: bash
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run: |
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make -j${{ env.procs }} test CXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC
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- name: Log yosys-config output
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run: |
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./yosys-config || true

‎yosys/.github/workflows/test-macos.yml

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@@ -8,7 +8,7 @@ jobs:
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strategy:
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matrix:
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os:
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- { id: macos-11, name: 'Big Sur' }
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- { id: macos-13, name: 'Ventura' }
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cpp_std:
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- 'c++11'
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- 'c++17'
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cc --version
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- name: Checkout Yosys
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uses: actions/checkout@v3
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uses: actions/checkout@v4
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- name: Get iverilog
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shell: bash
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run: |
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git clone https://github.com/steveicarus/iverilog.git
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cd iverilog
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git checkout 192b6aec96fde982e6ddcb28b346d5893aa8e874
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echo "IVERILOG_GIT=$(git rev-parse HEAD)" >> $GITHUB_ENV
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- name: Cache iverilog
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id: cache-iverilog
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uses: actions/cache@v3
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uses: actions/cache@v4
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with:
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path: .local/
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key: ${{ matrix.os.id }}-${{ hashFiles('iverilog/.git/refs/heads/master') }}
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key: ${{ matrix.os.id }}-${{ env.IVERILOG_GIT }}
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- name: Build iverilog
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if: steps.cache-iverilog.outputs.cache-hit != 'true'

‎yosys/.github/workflows/version.yml

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runs-on: ubuntu-latest
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steps:
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- name: Checkout
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uses: actions/checkout@v3
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uses: actions/checkout@v4
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with:
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fetch-depth: 0
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- name: Take last commit

‎yosys/.github/workflows/vs.yml

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yosys-vcxsrc:
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runs-on: ubuntu-latest
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steps:
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- uses: actions/checkout@v3
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- uses: actions/checkout@v4
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- name: Build
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run: make vcxsrc YOSYS_VER=latest
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- uses: actions/upload-artifact@v3
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- uses: actions/upload-artifact@v4
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with:
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name: vcxsrc
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path: yosys-win32-vcxsrc-latest.zip
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runs-on: windows-2019
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needs: yosys-vcxsrc
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steps:
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- uses: actions/download-artifact@v3
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- uses: actions/download-artifact@v4
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with:
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name: vcxsrc
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path: .

‎yosys/.github/workflows/wasi.yml

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name: WASI Build
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on: [push, pull_request]
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jobs:
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wasi:
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runs-on: ubuntu-latest
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steps:
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- uses: actions/checkout@v4
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- name: Build
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run: |
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WASI_SDK=wasi-sdk-19.0
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WASI_SDK_URL=https://github.com/WebAssembly/wasi-sdk/releases/download/wasi-sdk-19/wasi-sdk-19.0-linux.tar.gz
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if ! [ -d ${WASI_SDK} ]; then curl -L ${WASI_SDK_URL} | tar xzf -; fi
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mkdir -p build
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cat > build/Makefile.conf <<END
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export PATH := $(pwd)/${WASI_SDK}/bin:${PATH}
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WASI_SYSROOT := $(pwd)/${WASI_SDK}/share/wasi-sysroot
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CONFIG := wasi
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PREFIX := /
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ENABLE_TCL := 0
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ENABLE_READLINE := 0
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ENABLE_PLUGINS := 0
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ENABLE_ZLIB := 0
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END
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make -C build -f ../Makefile CXX=clang -j$(nproc)

‎yosys/.gitignore

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*.o
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*.d
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*.dwo
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.*.swp
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*.gch
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*.gcda
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*.gcno
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*~
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__pycache__
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/.cproject
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/.project

‎yosys/CHANGELOG

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List of major changes and improvements between releases
33
=======================================================
44

5+
Yosys 0.37 .. Yosys 0.38
6+
--------------------------
7+
* New commands and options
8+
- Added option "-tech" to "opt_lut" pass.
9+
- Added option "-nokeep_prints" to "hierarchy" pass.
10+
- Added option "-nolower" to "async2sync" and "clk2fflogic" pass.
11+
- Added option "-lower" to "chformal" pass.
12+
13+
* Various
14+
- Added $check cell to represent assertions with messages.
15+
- Allow capturing $print cell output in CXXRTL.
16+
- Added API to overwrite existing pass from plugin.
17+
- Follow the XDG Base Directory Specification for storing history files.
18+
- Without a known top module, derive all deferred modules (hierarchy pass).
19+
- Detect and error out on combinational loops in write_aiger.
20+
21+
* Verific support
22+
- Added option "-no-split-complex-ports" to "verific -import".
23+
24+
Yosys 0.36 .. Yosys 0.37
25+
--------------------------
26+
* New commands and options
27+
- Added option "-nodisplay" to read_verilog.
28+
29+
* SystemVerilog
30+
- Correct hierarchical path names for structs and unions.
31+
32+
* Various
33+
- Print hierarchy for failed assertions in "sim" pass.
34+
- Add "--present-only" option to "yosys-witness" to omit unused signals.
35+
- Implement a generic record/replay interface for CXXRTL.
36+
- Improved readability of emitted code with "write_verilog".
37+
38+
Yosys 0.35 .. Yosys 0.36
39+
--------------------------
40+
* New commands and options
41+
- Added option "--" to pass arguments down to tcl when using -c option.
42+
- Added ability on MacOS and Windows to pass options after arguments on cli.
43+
- Added option "-cmp2softlogic" to synth_lattice.
44+
- Added option "-lowpower" to "booth" pass.
45+
46+
* QuickLogic support
47+
- Added "K6N10f" support.
48+
- Added "-nodsp", "-nocarry", "-nobram" and "-bramtypes" options to
49+
"synth_quicklogic" pass.
50+
- Added "ql_bram_merge" pass to merge 18K BRAM cells into TDP36K.
51+
- Added "ql_bram_types" pass to change TDP36K depending on configuration.
52+
- Added "ql_dsp_io_regs" pass to update QL_DSP2 depending on configuration.
53+
- Added "ql_dsp_macc" pass to infer multiplier-accumulator DSP cells.
54+
- Added "ql_dsp_simd" pass to merge DSP pairs to operate in SIMD mode.
55+
56+
* ECP5,iCE40 and Gowin support
57+
- Enabled abc9 by default, added "-noabc9" option to disable.
58+
59+
* MachXO3 support
60+
- Quality of results improvements.
61+
- Enabled "booth" pass by default for it in "synth_lattice".
62+
63+
* Various
64+
- Improved "peepopt" by adding shiftadd pattern support.
65+
- Added "--incremental" mode to smtbmc.
66+
67+
Yosys 0.34 .. Yosys 0.35
68+
--------------------------
69+
* Various
70+
- Improvements on "peepopt" shiftmul matcher.
71+
- Improvements on "ram_style" attributes handling.
72+
73+
* Verific support
74+
- Improved static elaboration for VHDL and mixed HDL designs.
75+
- Expose "hdlname" attribute with original module name.
76+
- Expose "architecture" attribute with VHDL architecture name.
77+
78+
Yosys 0.33 .. Yosys 0.34
79+
--------------------------
80+
* New commands and options
81+
- Added option "-assert" to "sim" pass.
82+
- Added option "-noinitstate" to "sim" pass.
83+
- Added option "-dont_use" to "abc" pass.
84+
- Added "dft_tag" pass to create tagging logic for data flow tracking.
85+
- Added "future" pass to resolve future sampled value functions.
86+
- Added "booth" pass to map $mul cells to Booth multipliers.
87+
- Added option "-booth" to "synth" pass.
88+
89+
* SystemVerilog
90+
- Added support for assignments within expressions, e.g., `x[y++] = z;` or
91+
`x = (y *= 2) - 1;`.
92+
93+
* Verific support
94+
- "src" attribute contain full location info.
95+
- module parameters are kept after import.
96+
- accurate access order semantics in memory inference.
97+
- better "bind" support for mixed language projects.
98+
99+
* Various
100+
- "show" command displays dot instead of box for wire aliases.
101+
102+
Yosys 0.32 .. Yosys 0.33
103+
--------------------------
104+
* Various
105+
- Added "$print" cell, produced by "$display" and "$write"
106+
Verilog tasks.
107+
- Added "$print" cell handling in CXXRTL.
108+
109+
* Lattice FPGA support
110+
- Added generic "synth_lattice" pass (for now MachXO2/XO3/XO3D)
111+
- Removed "synth_machxo2" pass
112+
- Pass "ecp5_gsr" renamed to "lattice_gsr"
113+
- "synth_machxo2" equivalent is "synth_lattice -family xo2"
114+
5115
Yosys 0.31 .. Yosys 0.32
6116
--------------------------
7117
* Verific support

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