Fixed slack cost routine bug and updated golden results. Added code documentation for options --place_algorithm and --place_quench_algorithm (same as the documentation on developer's page.

Author: Bill-hbrhbr

vpr/src/base/read_options.cpp

@@ -1683,13 +1683,21 @@ argparse::ArgumentParser create_arg_parser(std::string prog_name, t_options& arg
         .show_in(argparse::ShowIn::HELP_ONLY);
 
     place_grp.add_argument<e_place_algorithm, ParsePlaceAlgorithm>(args.PlaceAlgorithm, "--place_algorithm")
-        .help("Controls which placement algorithm is used")
+        .help(
+            "Controls which placement algorithm is used. Valid options:\n"
+            " * bounding_box: Focuses purely on minimizing the bounding box wirelength of the circuit. Turns off timing analysis if specified.\n"
+            " * criticality_timing: Focuses on minimizing both the wirelength and the connection timing costs (criticality * delay).\n"
+            " * slack_timing: Focuses on improving the circuit slack values to reduce critical path delay.\n")
         .default_value("criticality_timing")
         .choices({"bounding_box", "criticality_timing", "slack_timing"})
         .show_in(argparse::ShowIn::HELP_ONLY);
 
     place_grp.add_argument<e_place_algorithm, ParsePlaceAlgorithm>(args.PlaceQuenchAlgorithm, "--place_quench_algorithm")
-        .help("Controls which placement algorithm is used during placement quench")
+        .help(
+            "Controls which placement algorithm is used during placement quench. Valid options:\n"
+            " * bounding_box: Focuses purely on minimizing the bounding box wirelength of the circuit. Turns off timing analysis if specified.\n"
+            " * criticality_timing: Focuses on minimizing both the wirelength and the connection timing costs (criticality * delay).\n"
+            " * slack_timing: Focuses on improving the circuit slack values to reduce critical path delay.\n")
         .default_value("criticality_timing")
         .choices({"bounding_box", "criticality_timing", "slack_timing"})
         .show_in(argparse::ShowIn::HELP_ONLY);

vpr/src/place/place.cpp

@@ -1251,7 +1251,7 @@ static void placement_inner_loop(float t,
             num_swap_rejected++;
         }
 
-        if (placer_opts.place_algorithm.is_timing_driven()) {
+        if (place_algorithm.is_timing_driven()) {
             /* Do we want to re-timing analyze the circuit to get updated slack and criticality values?
              * We do this only once in a while, since it is expensive.
              */
@@ -1688,11 +1688,11 @@ static e_move_result try_swap(float t,
             /*in this case we redefine delta_c as a combination of timing and bb.  *
              *additionally, we normalize all values, therefore delta_c is in       *
              *relation to 1*/
-
             delta_c = (1 - timing_tradeoff) * bb_delta_c * prev_inverse_costs->bb_cost
                       + timing_tradeoff * timing_delta_c * prev_inverse_costs->timing_cost;
 
-        } else { //place_algorithm == BOUNDING_BOX_PLACE (wiring cost)
+        } else {
+            VTR_ASSERT(place_algorithm == BOUNDING_BOX_PLACE);
             delta_c = bb_delta_c;
         }
 
@@ -2010,7 +2010,7 @@ static float analyze_setup_slack_cost(const PlacerSetupSlacks* setup_slacks) {
     //Check the first pair of slack values that are different
     //If found, return their difference
     for (size_t idiff = 0; idiff < original_setup_slacks.size(); ++idiff) {
-        float slack_diff = original_setup_slacks[idiff] != proposed_setup_slacks[idiff];
+        float slack_diff = original_setup_slacks[idiff] - proposed_setup_slacks[idiff];
 
         if (slack_diff != 0) {
             return slack_diff;

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt

@@ -1,2 +1,2 @@
 arch                  	circuit        	script_params	vtr_flow_elapsed_time	error	odin_synth_time	max_odin_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision                	vpr_build_info                	vpr_compiler                               	vpr_compiled       	hostname                           	rundir                                                                                                                                                                    	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_time	placed_wirelength_est	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	crit_path_route_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time
-k6_N10_mem32K_40nm.xml	stereovision3.v	common       	1.63                 	     	0.05           	9248        	4        	0.11          	-1          	-1          	33212      	-1      	-1         	19     	11    	0           	0       	success   	v8.0.0-2369-gdd2cfe245-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 7.5.0 on Linux-4.15.0-60-generic x86_64	2020-09-01T03:44:11	betzgrp-wintermute.eecg.utoronto.ca	/home/hubingra/master/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/run002/k6_N10_mem32K_40nm.xml/stereovision3.v/common	29064      	11                	30                 	262                	292                  	2                 	104                 	60                    	7           	7            	49               	clb                      	auto       	0.05     	395                  	0.24      	0.13             	2.22041       	-166.35             	-2.22041            	2.11404                                                      	0.131181                         	0.10474              	0.162837                        	0.12936             	20            	710              	35                                    	1.07788e+06           	1.02399e+06          	49980.0                          	1020.00                             	0.33                     	0.261832                                 	0.208973                     	526                        	24                               	854                        	2107                              	65873                      	19424                    	2.36384            	2.31477                                           	-185.592 	-2.36384 	0       	0       	65453.8                     	1335.79                        	0.03                	0.0178836                           	0.0152135               
+k6_N10_mem32K_40nm.xml	stereovision3.v	common       	2.19                 	     	0.07           	9296        	4        	0.16          	-1          	-1          	32824      	-1      	-1         	19     	11    	0           	0       	success   	v8.0.0-2579-g270d1efd9-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 7.5.0 on Linux-4.15.0-60-generic x86_64	2020-09-04T06:15:46	betzgrp-wintermute.eecg.utoronto.ca	/home/hubingra/master/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/run003/k6_N10_mem32K_40nm.xml/stereovision3.v/common	28964      	11                	30                 	262                	292                  	2                 	104                 	60                    	7           	7            	49               	clb                      	auto       	0.05     	453                  	0.24      	0.13             	2.18141       	-165.789            	-2.18141            	2.0954                                                       	0.12497                          	0.10019              	0.156789                        	0.124805            	26            	608              	25                                    	1.07788e+06           	1.02399e+06          	65453.8                          	1335.79                             	0.27                     	0.252669                                 	0.202403                     	608                        	25                               	973                        	2367                              	87670                      	24993                    	2.53264            	2.50992                                           	-189.166 	-2.53264 	0       	0       	80140.9                     	1635.53                        	0.03                	0.0187426                           	0.0157532