Merge branch 'verilog-to-routing:master' into fixed_chan_width_bug

Author: ArashAhmadian

dev/nix/shell.nix

@@ -7,7 +7,6 @@ let
     lxml
     python-utils
   ];
-  python27 = pkgs.python27.withPackages python_packages;
   python3 = pkgs.python3.withPackages python_packages;
 in
 stdenv.mkDerivation rec {
@@ -27,7 +26,6 @@ stdenv.mkDerivation rec {
     clang-tools
     gperftools
     perl
-    python27
     python3
     time
   ];

vtr_flow/scripts/run_vtr_task.py

@@ -227,11 +227,11 @@ def vtr_command_main(arg_list, prog=None):
 
         config_files = [find_task_config_file(task_name) for task_name in task_names]
         configs = []
-        common_task_prefix = None  # common task prefix to shorten task names
+        common_task_prefix = ""  # common task prefix to shorten task names
         for config_file in config_files:
             config = load_task_config(config_file)
             configs += [config]
-            if common_task_prefix is None:
+            if not common_task_prefix:
                 common_task_prefix = config.task_name
             else:
                 match = SequenceMatcher(