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Updated genfasm test
Signed-off-by: Maciej Kurc <[email protected]>
1 parent d290f47 commit 20c051c

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‎utils/fasm/test/test_fasm.cpp

Lines changed: 113 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77
#include "fasm_utils.h"
88
#include "arch_util.h"
99
#include "rr_graph_writer.h"
10+
#include "post_routing_pb_pin_fixup.h"
1011
#include <sstream>
1112
#include <fstream>
1213
#include <regex>
@@ -168,6 +169,54 @@ TEST_CASE("match_lut_init", "[fasm]") {
168169
CHECK(match_lut_init("16'b0000000011111111", "16'b0000111100001111"));
169170
}
170171

172+
std::string get_pin_feature (size_t inode) {
173+
auto& device_ctx = g_vpr_ctx.device();
174+
175+
// Get tile physical tile and the pin number
176+
int ilow = device_ctx.rr_nodes[inode].xlow();
177+
int jlow = device_ctx.rr_nodes[inode].ylow();
178+
auto physical_tile = device_ctx.grid[ilow][jlow].type;
179+
int pin_num = device_ctx.rr_nodes[inode].ptc_num();
180+
181+
// Get the sub tile (type, not instance)
182+
const t_sub_tile* sub_tile_type = nullptr;
183+
int sub_tile_pin = -1;
184+
185+
for (auto& sub_tile : physical_tile->sub_tiles) {
186+
auto max_inst_pins = sub_tile.num_phy_pins / sub_tile.capacity.total();
187+
for (int pin = 0; pin < sub_tile.num_phy_pins; pin++) {
188+
if (sub_tile.sub_tile_to_tile_pin_indices[pin] == pin_num) {
189+
sub_tile_type = &sub_tile;
190+
sub_tile_pin = pin % max_inst_pins;
191+
break;
192+
}
193+
}
194+
195+
if (sub_tile_type != nullptr) {
196+
break;
197+
}
198+
}
199+
200+
REQUIRE(sub_tile_type != nullptr);
201+
REQUIRE(sub_tile_pin != -1);
202+
203+
// Find the sub tile port and pin index
204+
for (const auto& port : sub_tile_type->ports) {
205+
int pin_lo = port.absolute_first_pin_index;
206+
int pin_hi = pin_lo + port.num_pins;
207+
208+
if (sub_tile_pin >= pin_lo && sub_tile_pin < pin_hi) {
209+
int port_pin = sub_tile_pin - pin_lo;
210+
fprintf(stderr, " %zu %s %d\n", inode, port.name, port_pin);
211+
return vtr::string_fmt("PIN_%d_%d_%s_%s_%d", ilow, jlow, sub_tile_type->name, port.name, port_pin);
212+
}
213+
}
214+
215+
// Pin not found
216+
REQUIRE(false);
217+
return std::string();
218+
}
219+
171220
TEST_CASE("fasm_integration_test", "[fasm]") {
172221
{
173222
t_vpr_setup vpr_setup;
@@ -193,6 +242,15 @@ TEST_CASE("fasm_integration_test", "[fasm]") {
193242
auto switch_id = device_ctx.rr_nodes[inode].edge_switch(iedge);
194243
auto value = vtr::string_fmt("%d_%d_%zu",
195244
inode, sink_inode, switch_id);
245+
246+
// Add additional features to edges that go to CLB.I[11:0] pins
247+
// to correlate them with features of CLB input mux later.
248+
auto sink_type = device_ctx.rr_nodes[sink_inode].type();
249+
if (sink_type == IPIN) {
250+
auto pin_feature = get_pin_feature(sink_inode);
251+
value = value + "\n" + pin_feature;
252+
}
253+
196254
vpr::add_rr_edge_metadata(inode, sink_inode, switch_id,
197255
vtr::string_view("fasm_features"), vtr::string_view(value.data(), value.size()));
198256
}
@@ -227,6 +285,17 @@ TEST_CASE("fasm_integration_test", "[fasm]") {
227285
bool flow_succeeded = vpr_flow(vpr_setup, arch);
228286
REQUIRE(flow_succeeded == true);
229287

288+
/* Sync netlist to the actual routing (necessary if there are block
289+
ports with equivalent pins) */
290+
if (flow_succeeded) {
291+
sync_netlists_to_routing(g_vpr_ctx.device(),
292+
g_vpr_ctx.mutable_atom(),
293+
g_vpr_ctx.mutable_clustering(),
294+
g_vpr_ctx.placement(),
295+
g_vpr_ctx.routing(),
296+
vpr_setup.PackerOpts.pack_verbosity > 2);
297+
}
298+
230299
std::stringstream fasm_string;
231300
fasm::FasmWriterVisitor visitor(&arch.strings, fasm_string);
232301
NetlistWalker nl_walker(visitor);
@@ -272,6 +341,8 @@ TEST_CASE("fasm_integration_test", "[fasm]") {
272341
fasm_string.clear();
273342
fasm_string.seekg(0);
274343

344+
std::set<std::string> xbar_features;
345+
std::set<std::tuple<int, int, std::string, std::string, int>> routed_pins; // x, y, tile, port, pin
275346
std::set<std::tuple<int, int, short>> routing_edges;
276347
std::set<std::tuple<int, int>> occupied_locs;
277348
bool found_lut5 = false;
@@ -313,7 +384,21 @@ TEST_CASE("fasm_integration_test", "[fasm]") {
313384
}
314385
}
315386

316-
if(line.find("FLE") != std::string::npos) {
387+
// A feature representing block pin used by the router
388+
if(line.find("PIN_") != std::string::npos) {
389+
auto parts = vtr::split(line, "_");
390+
REQUIRE(parts.size() == 6);
391+
392+
auto x = vtr::atoi(parts[1]);
393+
auto y = vtr::atoi(parts[2]);
394+
auto tile = parts[3];
395+
auto port = parts[4];
396+
auto pin = vtr::atoi(parts[5]);
397+
398+
routed_pins.insert(std::make_tuple(x, y, tile, port, pin));
399+
}
400+
401+
else if(line.find("FLE") != std::string::npos) {
317402

318403
// Check correlation with top-level prefixes with X coordinates
319404
// as defined in the architecture
@@ -335,6 +420,11 @@ TEST_CASE("fasm_integration_test", "[fasm]") {
335420
// Check presence of LOC prefix substitutions
336421
CHECK_THAT(line, MatchesRegex(".*X\\d+Y\\d+.*"));
337422

423+
// Add to xbar features
424+
if (line.find("_XBAR_") != std::string::npos) {
425+
xbar_features.insert(line);
426+
}
427+
338428
// Extract loc from tag
339429
std::smatch locMatch;
340430
REQUIRE(std::regex_match(line, locMatch, std::regex(".*X(\\d+)Y(\\d+).*")));
@@ -472,6 +562,28 @@ TEST_CASE("fasm_integration_test", "[fasm]") {
472562
}
473563
}
474564

565+
// Verify CLB crossbar mux features against routed pin features.
566+
for (const auto& xbar_feature : xbar_features) {
567+
568+
// Decompose the xbar feature - extract only the necessary information
569+
// such as block location and pin index.
570+
std::smatch m;
571+
fprintf(stderr, "%s\n", xbar_feature.c_str());
572+
auto res = std::regex_match(xbar_feature, m, std::regex(
573+
".*_X([0-9]+)Y([0-9]+)\\.IN([0-9])_XBAR_I([0-9]+)$"));
574+
REQUIRE(res == true);
575+
576+
int x = vtr::atoi(m.str(1));
577+
int y = vtr::atoi(m.str(2));
578+
std::string mux = m.str(3);
579+
int pin = vtr::atoi(m.str(4));
580+
581+
// Check if there is a corresponding routed pin feature
582+
auto pin_feature = std::make_tuple(x, y, std::string("clb"), std::string("I"), pin);
583+
size_t count = routed_pins.count(pin_feature);
584+
REQUIRE(count == 1);
585+
}
586+
475587
// Verify that all LUTs defined in the BLIF file ended up in fasm
476588
CHECK(lut_defs.size() == 0);
477589

‎utils/fasm/test/test_fasm_arch.xml

Lines changed: 125 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -431,10 +431,6 @@
431431
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[1:1].in"/>
432432
<delay_constant max="75e-12" in_port="fle[1:0].out" out_port="fle[1:1].in"/>
433433
</complete>
434-
<complete name="crossbar0" input="clb.I fle[1:0].out" output="fle[0:0].in[5:1]">
435-
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[0:0].in[5:1]"/>
436-
<delay_constant max="75e-12" in_port="fle[1:0].out" out_port="fle[0:0].in[5:1]"/>
437-
</complete>
438434
<mux name="mux_fle0_in0" output="fle[0].in[0]"
439435
input="clb.I[0] clb.I[1] clb.I[2] clb.I[3] clb.I[4] clb.I[5] clb.I[6] clb.I[7] clb.I[8] clb.I[9] clb.I[10] clb.I[11] fle[0].out[0] fle[0].out[1] fle[1].out[0] fle[1].out[1]">
440436
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[0].in[0]"/>
@@ -460,6 +456,131 @@
460456
</meta>
461457
</metadata>
462458
</mux>
459+
<mux name="mux_fle0_in1" output="fle[0].in[1]"
460+
input="clb.I[0] clb.I[1] clb.I[2] clb.I[3] clb.I[4] clb.I[5] clb.I[6] clb.I[7] clb.I[8] clb.I[9] clb.I[10] clb.I[11] fle[0].out[0] fle[0].out[1] fle[1].out[0] fle[1].out[1]">
461+
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[0].in[1]"/>
462+
<delay_constant max="75e-12" in_port="fle[1:0].out" out_port="fle[0].in[1]"/>
463+
<metadata>
464+
<meta name="fasm_mux">
465+
clb.I[0] : FLE0{SING}_{LOC}.IN1_XBAR_I0
466+
clb.I[1] : FLE0{SING}_{LOC}.IN1_XBAR_I1
467+
clb.I[2] : FLE0{SING}_{LOC}.IN1_XBAR_I2
468+
clb.I[3] : FLE0{SING}_{LOC}.IN1_XBAR_I3
469+
clb.I[4] : FLE0{SING}_{LOC}.IN1_XBAR_I4
470+
clb.I[5] : FLE0{SING}_{LOC}.IN1_XBAR_I5
471+
clb.I[6] : FLE0{SING}_{LOC}.IN1_XBAR_I6
472+
clb.I[7] : FLE0{SING}_{LOC}.IN1_XBAR_I7
473+
clb.I[8] : FLE0{SING}_{LOC}.IN1_XBAR_I8
474+
clb.I[9] : FLE0{SING}_{LOC}.IN1_XBAR_I9
475+
clb.I[10] : FLE0{SING}_{LOC}.IN1_XBAR_I10
476+
clb.I[11] : FLE0{SING}_{LOC}.IN1_XBAR_I11
477+
fle[0].out[0] : FLE0{SING}_{LOC}.IN1_XBAR_FLE0_OUT0
478+
fle[0].out[1] : FLE0{SING}_{LOC}.IN1_XBAR_FLE0_OUT1
479+
fle[1].out[0] : FLE0{SING}_{LOC}.IN1_XBAR_FLE1_OUT0
480+
fle[1].out[1] : FLE0{SING}_{LOC}.IN1_XBAR_FLE1_OUT1
481+
</meta>
482+
</metadata>
483+
</mux>
484+
<mux name="mux_fle0_in2" output="fle[0].in[2]"
485+
input="clb.I[0] clb.I[1] clb.I[2] clb.I[3] clb.I[4] clb.I[5] clb.I[6] clb.I[7] clb.I[8] clb.I[9] clb.I[10] clb.I[11] fle[0].out[0] fle[0].out[1] fle[1].out[0] fle[1].out[1]">
486+
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[0].in[2]"/>
487+
<delay_constant max="75e-12" in_port="fle[1:0].out" out_port="fle[0].in[2]"/>
488+
<metadata>
489+
<meta name="fasm_mux">
490+
clb.I[0] : FLE0{SING}_{LOC}.IN2_XBAR_I0
491+
clb.I[1] : FLE0{SING}_{LOC}.IN2_XBAR_I1
492+
clb.I[2] : FLE0{SING}_{LOC}.IN2_XBAR_I2
493+
clb.I[3] : FLE0{SING}_{LOC}.IN2_XBAR_I3
494+
clb.I[4] : FLE0{SING}_{LOC}.IN2_XBAR_I4
495+
clb.I[5] : FLE0{SING}_{LOC}.IN2_XBAR_I5
496+
clb.I[6] : FLE0{SING}_{LOC}.IN2_XBAR_I6
497+
clb.I[7] : FLE0{SING}_{LOC}.IN2_XBAR_I7
498+
clb.I[8] : FLE0{SING}_{LOC}.IN2_XBAR_I8
499+
clb.I[9] : FLE0{SING}_{LOC}.IN2_XBAR_I9
500+
clb.I[10] : FLE0{SING}_{LOC}.IN2_XBAR_I10
501+
clb.I[11] : FLE0{SING}_{LOC}.IN2_XBAR_I11
502+
fle[0].out[0] : FLE0{SING}_{LOC}.IN2_XBAR_FLE0_OUT0
503+
fle[0].out[1] : FLE0{SING}_{LOC}.IN2_XBAR_FLE0_OUT1
504+
fle[1].out[0] : FLE0{SING}_{LOC}.IN2_XBAR_FLE1_OUT0
505+
fle[1].out[1] : FLE0{SING}_{LOC}.IN2_XBAR_FLE1_OUT1
506+
</meta>
507+
</metadata>
508+
</mux>
509+
<mux name="mux_fle0_in3" output="fle[0].in[3]"
510+
input="clb.I[0] clb.I[1] clb.I[2] clb.I[3] clb.I[4] clb.I[5] clb.I[6] clb.I[7] clb.I[8] clb.I[9] clb.I[10] clb.I[11] fle[0].out[0] fle[0].out[1] fle[1].out[0] fle[1].out[1]">
511+
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[0].in[3]"/>
512+
<delay_constant max="75e-12" in_port="fle[1:0].out" out_port="fle[0].in[3]"/>
513+
<metadata>
514+
<meta name="fasm_mux">
515+
clb.I[0] : FLE0{SING}_{LOC}.IN3_XBAR_I0
516+
clb.I[1] : FLE0{SING}_{LOC}.IN3_XBAR_I1
517+
clb.I[2] : FLE0{SING}_{LOC}.IN3_XBAR_I2
518+
clb.I[3] : FLE0{SING}_{LOC}.IN3_XBAR_I3
519+
clb.I[4] : FLE0{SING}_{LOC}.IN3_XBAR_I4
520+
clb.I[5] : FLE0{SING}_{LOC}.IN3_XBAR_I5
521+
clb.I[6] : FLE0{SING}_{LOC}.IN3_XBAR_I6
522+
clb.I[7] : FLE0{SING}_{LOC}.IN3_XBAR_I7
523+
clb.I[8] : FLE0{SING}_{LOC}.IN3_XBAR_I8
524+
clb.I[9] : FLE0{SING}_{LOC}.IN3_XBAR_I9
525+
clb.I[10] : FLE0{SING}_{LOC}.IN3_XBAR_I10
526+
clb.I[11] : FLE0{SING}_{LOC}.IN3_XBAR_I11
527+
fle[0].out[0] : FLE0{SING}_{LOC}.IN3_XBAR_FLE0_OUT0
528+
fle[0].out[1] : FLE0{SING}_{LOC}.IN3_XBAR_FLE0_OUT1
529+
fle[1].out[0] : FLE0{SING}_{LOC}.IN3_XBAR_FLE1_OUT0
530+
fle[1].out[1] : FLE0{SING}_{LOC}.IN3_XBAR_FLE1_OUT1
531+
</meta>
532+
</metadata>
533+
</mux>
534+
<mux name="mux_fle0_in4" output="fle[0].in[4]"
535+
input="clb.I[0] clb.I[1] clb.I[2] clb.I[3] clb.I[4] clb.I[5] clb.I[6] clb.I[7] clb.I[8] clb.I[9] clb.I[10] clb.I[11] fle[0].out[0] fle[0].out[1] fle[1].out[0] fle[1].out[1]">
536+
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[0].in[4]"/>
537+
<delay_constant max="75e-12" in_port="fle[1:0].out" out_port="fle[0].in[4]"/>
538+
<metadata>
539+
<meta name="fasm_mux">
540+
clb.I[0] : FLE0{SING}_{LOC}.IN4_XBAR_I0
541+
clb.I[1] : FLE0{SING}_{LOC}.IN4_XBAR_I1
542+
clb.I[2] : FLE0{SING}_{LOC}.IN4_XBAR_I2
543+
clb.I[3] : FLE0{SING}_{LOC}.IN4_XBAR_I3
544+
clb.I[4] : FLE0{SING}_{LOC}.IN4_XBAR_I4
545+
clb.I[5] : FLE0{SING}_{LOC}.IN4_XBAR_I5
546+
clb.I[6] : FLE0{SING}_{LOC}.IN4_XBAR_I6
547+
clb.I[7] : FLE0{SING}_{LOC}.IN4_XBAR_I7
548+
clb.I[8] : FLE0{SING}_{LOC}.IN4_XBAR_I8
549+
clb.I[9] : FLE0{SING}_{LOC}.IN4_XBAR_I9
550+
clb.I[10] : FLE0{SING}_{LOC}.IN4_XBAR_I10
551+
clb.I[11] : FLE0{SING}_{LOC}.IN4_XBAR_I11
552+
fle[0].out[0] : FLE0{SING}_{LOC}.IN4_XBAR_FLE0_OUT0
553+
fle[0].out[1] : FLE0{SING}_{LOC}.IN4_XBAR_FLE0_OUT1
554+
fle[1].out[0] : FLE0{SING}_{LOC}.IN4_XBAR_FLE1_OUT0
555+
fle[1].out[1] : FLE0{SING}_{LOC}.IN4_XBAR_FLE1_OUT1
556+
</meta>
557+
</metadata>
558+
</mux>
559+
<mux name="mux_fle0_in5" output="fle[0].in[5]"
560+
input="clb.I[0] clb.I[1] clb.I[2] clb.I[3] clb.I[4] clb.I[5] clb.I[6] clb.I[7] clb.I[8] clb.I[9] clb.I[10] clb.I[11] fle[0].out[0] fle[0].out[1] fle[1].out[0] fle[1].out[1]">
561+
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[0].in[5]"/>
562+
<delay_constant max="75e-12" in_port="fle[1:0].out" out_port="fle[0].in[5]"/>
563+
<metadata>
564+
<meta name="fasm_mux">
565+
clb.I[0] : FLE0{SING}_{LOC}.IN5_XBAR_I0
566+
clb.I[1] : FLE0{SING}_{LOC}.IN5_XBAR_I1
567+
clb.I[2] : FLE0{SING}_{LOC}.IN5_XBAR_I2
568+
clb.I[3] : FLE0{SING}_{LOC}.IN5_XBAR_I3
569+
clb.I[4] : FLE0{SING}_{LOC}.IN5_XBAR_I4
570+
clb.I[5] : FLE0{SING}_{LOC}.IN5_XBAR_I5
571+
clb.I[6] : FLE0{SING}_{LOC}.IN5_XBAR_I6
572+
clb.I[7] : FLE0{SING}_{LOC}.IN5_XBAR_I7
573+
clb.I[8] : FLE0{SING}_{LOC}.IN5_XBAR_I8
574+
clb.I[9] : FLE0{SING}_{LOC}.IN5_XBAR_I9
575+
clb.I[10] : FLE0{SING}_{LOC}.IN5_XBAR_I10
576+
clb.I[11] : FLE0{SING}_{LOC}.IN5_XBAR_I11
577+
fle[0].out[0] : FLE0{SING}_{LOC}.IN5_XBAR_FLE0_OUT0
578+
fle[0].out[1] : FLE0{SING}_{LOC}.IN5_XBAR_FLE0_OUT1
579+
fle[1].out[0] : FLE0{SING}_{LOC}.IN5_XBAR_FLE1_OUT0
580+
fle[1].out[1] : FLE0{SING}_{LOC}.IN5_XBAR_FLE1_OUT1
581+
</meta>
582+
</metadata>
583+
</mux>
463584
<complete name="clks" input="clb.clk" output="fle[1:0].clk">
464585
</complete>
465586
<direct name="clbouts1" input="fle[1:0].out[0:0]" output="clb.O[1:0]"/>

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