vpr: base: netlist writer: change formatting

Signed-off-by: Paweł Czarnecki <[email protected]>

Author: lpawelcz

vpr/src/base/netlist_writer.cpp

@@ -2433,9 +2433,6 @@ void print_verilog_port(std::ostream& os, size_t& unconn_count, const std::strin
         }
     };
 
-    //Port name
-    os << indent(depth) << "." << port_name << "(";
-
     //Pins
     if (nets.size() == 1) {
         //Single-bit port
@@ -2470,11 +2467,9 @@ void print_verilog_port(std::ostream& os, size_t& unconn_count, const std::strin
             // Empty connection
         } else {
             // Individual bits
-            os << "{"
-               << "\n";
             for (int ipin = (int)nets.size() - 1; ipin >= 0; --ipin) { //Reverse order to match endianess
-		std::string name = port_name + "[" + std::to_string(ipin) + "]";
-		os << indent(depth) << "." << escape_verilog_identifier(name) << " (";
+                std::string name = port_name + "[" + std::to_string(ipin) + "]";
+                os << indent(depth) << "." << escape_verilog_identifier(name) << "(";
                 if (nets[ipin].empty()) {
                     //Disconnected
                     if (type == PortType::INPUT || type == PortType::CLOCK) {
@@ -2490,12 +2485,12 @@ void print_verilog_port(std::ostream& os, size_t& unconn_count, const std::strin
                     //Connected
                     os << escape_verilog_identifier(nets[ipin]);
                 }
-                if (ipin != 0) {
-                    os << ",";
-                }
+                if (ipin != 0)
+                    os << "),";
+                else
+                    os << ")";
                 os << "\n";
             }
-            os << indent(depth) + " }";
         }
     }
 }