Merge branch 'master' into draw_net_fix

Author: SamuelHo10

.github/workflows/nightly_test_manual.yml

@@ -114,3 +114,23 @@ jobs:
           vtr_flow/**/*.log
           vtr_flow/**/vpr.out
           vtr_flow/**/parse_results*.txt
+
+    - name: Generate golden results
+      if: success() || failure()
+      run: |
+        source .venv/bin/activate
+        ./run_reg_test.py vtr_reg_nightly_test1 -create_golden
+        ./run_reg_test.py vtr_reg_nightly_test2 -create_golden
+        ./run_reg_test.py vtr_reg_nightly_test3 -create_golden
+        ./run_reg_test.py vtr_reg_nightly_test4 -create_golden
+        ./run_reg_test.py vtr_reg_nightly_test5 -create_golden
+        ./run_reg_test.py vtr_reg_nightly_test6 -create_golden
+        ./run_reg_test.py vtr_reg_nightly_test7 -create_golden
+
+    - name: Upload golden results
+      if: success() || failure()
+      uses: actions/upload-artifact@v4
+      with:
+        name: nightly_tests_golden
+        path: |
+          vtr_flow/**/vtr_reg_nightly*/**/golden_results.txt

CMakeLists.txt

@@ -227,18 +227,17 @@ foreach(flag ${FLEX_BISON_WARN_SUPPRESS_FLAGS_TO_CHECK})
     endif()
 endforeach()
 
-#Suppress IPO link warnings
-set(IPO_LINK_WARN_SUPRESS_FLAGS " ")
-set(IPO_LINK_WARN_SUPRESS_FLAGS_TO_CHECK
-    "-Wno-null-dereference"
-    )
-foreach(flag ${IPO_LINK_WARN_SUPRESS_FLAGS_TO_CHECK})
-    CHECK_CXX_COMPILER_FLAG(${flag} CXX_COMPILER_SUPPORTS_${flag})
-    if(CXX_COMPILER_SUPPORTS_${flag})
-        #Flag supported, so enable it
-        set(IPO_LINK_WARN_SUPRESS_FLAGS "${IPO_LINK_WARN_SUPRESS_FLAGS} ${flag}")
-    endif()
-endforeach()
+# Suppress IPO link warnings.
+# When IPO is turned on, it sometimes leads to false positives for warnings
+# since it checks for warnings after some of the source files have been compiled.
+# We globally suppress these warnings here. Any CMake executable which is added
+# after this line will have these warnings suppressed at link time.
+if (CMAKE_INTERPROCEDURAL_OPTIMIZATION)
+    message(STATUS "IPO: Suppressing known VTR warnings.")
+    add_link_options(-Wno-alloc-size-larger-than  # libarchfpga allocates C-style arrays using integers.
+                     -Wno-stringop-overflow       # EXTERNAL/capnproto has some string overflow warnings.
+                     )
+endif()
 
 #
 # Sanitizer flags

blifexplorer/CMakeLists.txt

@@ -56,13 +56,6 @@ else()
                             ${CMAKE_DL_LIBS}
     )
 
-    #Supress IPO link warnings if IPO is enabled
-    get_target_property(TEST_BLIFEXPLORER_USES_IPO blifexplorer INTERPROCEDURAL_OPTIMIZATION)
-    if (TEST_BLIFEXPLORER_USES_IPO)
-        set_property(TARGET blifexplorer APPEND PROPERTY LINK_FLAGS ${IPO_LINK_WARN_SUPRESS_FLAGS})
-    endif()
-
-
     install(TARGETS blifexplorer DESTINATION bin)
 
 endif()

dev/vtr_test_suite_verifier/test_suites_info.json

@@ -19,14 +19,12 @@
         "name": "vtr_reg_strong",
         "ignored_tasks": [
             "strong_router_heap",
-            "strong_verify_rr_graph_3d",
-            "strong_xilinx_support"
+            "strong_verify_rr_graph_3d"
         ]
     },
     {
         "name": "vtr_reg_strong_odin",
         "ignored_tasks": [
-            "strong_xilinx_support",
             "strong_router_heap",
             "strong_cluster_seed_type"
         ]
@@ -44,8 +42,7 @@
         "name": "vtr_reg_nightly_test2",
         "ignored_tasks": [
             "complex_switch",
-            "vpr_verify_custom_sb_diff_chan_width",
-            "vtr_xilinx_qor"
+            "vpr_verify_custom_sb_diff_chan_width"
         ]
     },
     {

doc/src/arch/reference.rst

@@ -1167,6 +1167,24 @@ The following tags are common to all ``<tile>`` tags:
 
                 **Default:** ``0``
 
+            If the subtile capacity is greater than 1, you can specify the capacity range when defining the pin locations. For example:
+
+            .. code-block:: xml
+
+                <sub_tile name="io_bottom" capacity="6">
+                    <equivalent_sites>
+                        <site pb_type="io"/>
+                    </equivalent_sites>
+                    <input name="outpad" num_pins="1"/>
+                    <output name="inpad" num_pins="1"/>
+                    <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+                    <pinlocations pattern="custom">
+                        <loc side="top">io_bottom[0:1].outpad io_bottom[0:3].inpad io_bottom[2:5].outpad io_bottom[4:5].inpad</loc>
+                    </pinlocations>
+                </sub_tile>
+            
+            If no capacity range is specified, it is assumed that the location applies to all capacity instances.
+
         Physical equivalence for a pin is specified by listing a pin more than once for different locations.
         For example, a LUT whose output can exit from the top and bottom of a block will have its output pin specified twice: once for the top and once for the bottom.
 

doc/src/vpr/command_line_usage.rst

@@ -1324,6 +1324,14 @@ Analytical Placement is generally split into three stages:
 
     **Default:** ``auto``
 
+.. option:: --ap_high_fanout_threshold <int>
+
+    Defines the threshold for high fanout nets within AP flow.
+
+    Ignores the nets that have higher fanouts than the threshold for the analytical solver.
+
+    **Default:** ``256``
+
 .. option:: --ap_verbosity <int>
 
     Controls the verbosity of the AP flow output.

doc/src/vtr/run_vtr_flow.rst

@@ -90,6 +90,13 @@ Enable Synlig tool with the ``-DSYNLIG_SYSTEMVERILOG=ON`` compile flag for the P
 
 Will run the VTR flow (default configuration) with Yosys frontend using Parmys plugin as partial mapper. To utilize the Parmys plugin, the ``-DYOSYS_PARMYS_PLUGIN=ON`` compile flag should be passed while building the VTR project with Yosys as a frontend.
 
+.. code-block:: bash
+
+    # Using the Parmys (Partial Mapper for Yosys) plugin as partial mapper with include files
+    ./run_vtr_flow <path/to/Verilog/File> <path/to/arch/file> -include <path/to/include/directory>/*.v*
+
+Will run the VTR flow (default configuration) with Yosys frontend using Parmys plugin as partial mapper. In addition to the main circuit passed in with the architecture, it will also pass in every HDL file with the specified file type within the include directory.
+
 Detailed Command-line Options
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -123,6 +130,15 @@ Detailed Command-line Options
       * ``vpr``
 
     **Default:** ``vpr``
+    
+.. option:: -include <path_to_file(s)>/*.<file_type(s)>
+
+    List of include files to a benchmark circuit 
+    (pass to VTR frontends as a benchmark design set).
+    
+    Include files can be any file supported by yosys+parmys (normally .v or .vh files).
+    
+    The include directory should not contain the circuit passed in with the architecture.
 
 .. option:: -power
 

libs/libarchfpga/CMakeLists.txt

@@ -57,12 +57,6 @@ target_compile_definitions(libarchfpga PUBLIC ${INTERCHANGE_SCHEMA_HEADERS})
 add_executable(read_arch ${READ_ARCH_EXEC_SRC})
 target_link_libraries(read_arch libarchfpga)
 
-#Supress IPO link warnings if IPO is enabled
-get_target_property(READ_ARCH_USES_IPO read_arch INTERPROCEDURAL_OPTIMIZATION)
-if(READ_ARCH_USES_IPO)
-    set_property(TARGET read_arch APPEND PROPERTY LINK_FLAGS ${IPO_LINK_WARN_SUPRESS_FLAGS})
-endif()
-
 install(TARGETS libarchfpga DESTINATION bin)
 install(FILES ${LIB_HEADERS} DESTINATION include/libarchfpga)
 

libs/libarchfpga/src/logic_types.h

@@ -62,10 +62,8 @@ struct t_model {
     bool never_prune = false;               ///< Don't remove from the netlist even if a block of this type has no output ports used and, therefore, unconnected to the rest of the netlist
 };
 
-// Tag for the logical model ID
-struct logical_model_id_tag;
 // A unique ID that represents a logical model in the architecture.
-typedef vtr::StrongId<logical_model_id_tag, size_t> LogicalModelId;
+typedef vtr::StrongId<struct logical_model_id_tag, size_t> LogicalModelId;
 
 /**
  * @brief A storage class containing all of the logical models in an FPGA

libs/libarchfpga/src/main.cpp

@@ -43,7 +43,7 @@ int main(int argc, char** argv) {
         printf("Reading in architecture\n");
 
         /* function declarations */
-        XmlReadArch(argv[1], atoi(argv[2]), &arch, physical_tile_types, logical_block_types);
+        xml_read_arch(argv[1], atoi(argv[2]), &arch, physical_tile_types, logical_block_types);
 
         printf("Printing Results\n");
 

libs/libarchfpga/src/physical_types.h

@@ -97,6 +97,13 @@ class t_metadata_value {
     // Return string value.
     vtr::interned_string as_string() const { return value_; }
 
+    t_metadata_value& operator=(const t_metadata_value& o) noexcept {
+        if (this != &o) {
+            value_ = o.value_;
+        }
+        return *this;
+    }
+
   private:
     vtr::interned_string value_;
 };