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vtr: modified architecture definitions to add sub tiles
Signed-off-by: Alessandro Comodi <[email protected]>
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libs/libarchfpga/arch/mult_luts_arch.xml

Lines changed: 50 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -52,54 +52,62 @@
5252
</model>
5353
</models>
5454
<tiles>
55-
<tile name="io" capacity="7">
56-
<equivalent_sites>
57-
<site pb_type="io"/>
58-
</equivalent_sites>
59-
<input name="outpad" num_pins="1" equivalent="none"/>
60-
<output name="inpad" num_pins="1"/>
61-
<clock name="clock" num_pins="1"/>
62-
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.125"/>
63-
<pinlocations pattern="custom">
64-
<loc side="left">io.outpad io.inpad io.clock</loc>
65-
<loc side="top">io.outpad io.inpad io.clock</loc>
66-
<loc side="right">io.outpad io.inpad io.clock</loc>
67-
<loc side="bottom">io.outpad io.inpad io.clock</loc>
68-
</pinlocations>
55+
<tile name="io">
56+
<sub_tile name="io" capacity="7">
57+
<equivalent_sites>
58+
<site pb_type="io" pin_mapping="direct"/>
59+
</equivalent_sites>
60+
<input name="outpad" num_pins="1" equivalent="none"/>
61+
<output name="inpad" num_pins="1"/>
62+
<clock name="clock" num_pins="1"/>
63+
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.125"/>
64+
<pinlocations pattern="custom">
65+
<loc side="left">io.outpad io.inpad io.clock</loc>
66+
<loc side="top">io.outpad io.inpad io.clock</loc>
67+
<loc side="right">io.outpad io.inpad io.clock</loc>
68+
<loc side="bottom">io.outpad io.inpad io.clock</loc>
69+
</pinlocations>
70+
</sub_tile>
6971
</tile>
7072
<tile name="clb">
71-
<equivalent_sites>
72-
<site pb_type="clb"/>
73-
</equivalent_sites>
74-
<input name="I" num_pins="56" equivalent="full"/>
75-
<output name="O" num_pins="16"/>
76-
<clock name="clk" num_pins="1"/>
77-
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.125"/>
78-
<pinlocations pattern="spread"/>
73+
<sub_tile name="clb">
74+
<equivalent_sites>
75+
<site pb_type="clb" pin_mapping="direct"/>
76+
</equivalent_sites>
77+
<input name="I" num_pins="56" equivalent="full"/>
78+
<output name="O" num_pins="16"/>
79+
<clock name="clk" num_pins="1"/>
80+
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.125"/>
81+
<pinlocations pattern="spread"/>
82+
</sub_tile>
7983
</tile>
8084
<tile name="memory" height="4">
81-
<equivalent_sites>
82-
<site pb_type="memory"/>
83-
</equivalent_sites>
84-
<input name="addr1" num_pins="16"/>
85-
<input name="addr2" num_pins="16"/>
86-
<input name="data" num_pins="64"/>
87-
<input name="we1" num_pins="1"/>
88-
<input name="we2" num_pins="1"/>
89-
<output name="out" num_pins="64"/>
90-
<clock name="clk" num_pins="1"/>
91-
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.125"/>
92-
<pinlocations pattern="spread"/>
85+
<sub_tile name="memory">
86+
<equivalent_sites>
87+
<site pb_type="memory" pin_mapping="direct"/>
88+
</equivalent_sites>
89+
<input name="addr1" num_pins="16"/>
90+
<input name="addr2" num_pins="16"/>
91+
<input name="data" num_pins="64"/>
92+
<input name="we1" num_pins="1"/>
93+
<input name="we2" num_pins="1"/>
94+
<output name="out" num_pins="64"/>
95+
<clock name="clk" num_pins="1"/>
96+
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.125"/>
97+
<pinlocations pattern="spread"/>
98+
</sub_tile>
9399
</tile>
94100
<tile name="mult_36" height="3">
95-
<equivalent_sites>
96-
<site pb_type="mult_36"/>
97-
</equivalent_sites>
98-
<input name="a" num_pins="36"/>
99-
<input name="b" num_pins="36"/>
100-
<output name="out" num_pins="72"/>
101-
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.125"/>
102-
<pinlocations pattern="spread"/>
101+
<sub_tile name="mult_36">
102+
<equivalent_sites>
103+
<site pb_type="mult_36" pin_mapping="direct"/>
104+
</equivalent_sites>
105+
<input name="a" num_pins="36"/>
106+
<input name="b" num_pins="36"/>
107+
<output name="out" num_pins="72"/>
108+
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.125"/>
109+
<pinlocations pattern="spread"/>
110+
</sub_tile>
103111
</tile>
104112
</tiles>
105113
<!-- jluu and ken: ODIN II specific config ends -->

libs/libarchfpga/arch/sample_arch.xml

Lines changed: 50 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -133,54 +133,62 @@
133133
</model>
134134
</models>
135135
<tiles>
136-
<tile name="io" capacity="8">
137-
<equivalent_sites>
138-
<site pb_type="io"/>
139-
</equivalent_sites>
140-
<input name="outpad" num_pins="1"/>
141-
<output name="inpad" num_pins="1"/>
142-
<clock name="clock" num_pins="1"/>
143-
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
144-
<pinlocations pattern="custom">
145-
<loc side="left">io.outpad io.inpad io.clock</loc>
146-
<loc side="top">io.outpad io.inpad io.clock</loc>
147-
<loc side="right">io.outpad io.inpad io.clock</loc>
148-
<loc side="bottom">io.outpad io.inpad io.clock</loc>
149-
</pinlocations>
136+
<tile name="io">
137+
<sub_tile name="io" capacity="8">
138+
<equivalent_sites>
139+
<site pb_type="io" pin_mapping="direct"/>
140+
</equivalent_sites>
141+
<input name="outpad" num_pins="1"/>
142+
<output name="inpad" num_pins="1"/>
143+
<clock name="clock" num_pins="1"/>
144+
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
145+
<pinlocations pattern="custom">
146+
<loc side="left">io.outpad io.inpad io.clock</loc>
147+
<loc side="top">io.outpad io.inpad io.clock</loc>
148+
<loc side="right">io.outpad io.inpad io.clock</loc>
149+
<loc side="bottom">io.outpad io.inpad io.clock</loc>
150+
</pinlocations>
151+
</sub_tile>
150152
</tile>
151153
<tile name="clb">
152-
<equivalent_sites>
153-
<site pb_type="clb"/>
154-
</equivalent_sites>
155-
<input name="I" num_pins="33" equivalent="full"/>
156-
<output name="O" num_pins="20" equivalent="none"/>
157-
<clock name="clk" num_pins="1"/>
158-
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
159-
<pinlocations pattern="spread"/>
154+
<sub_tile name="clb">
155+
<equivalent_sites>
156+
<site pb_type="clb" pin_mapping="direct"/>
157+
</equivalent_sites>
158+
<input name="I" num_pins="33" equivalent="full"/>
159+
<output name="O" num_pins="20" equivalent="none"/>
160+
<clock name="clk" num_pins="1"/>
161+
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
162+
<pinlocations pattern="spread"/>
163+
</sub_tile>
160164
</tile>
161165
<tile name="mult_36" height="4">
162-
<equivalent_sites>
163-
<site pb_type="mult_36"/>
164-
</equivalent_sites>
165-
<input name="a" num_pins="36"/>
166-
<input name="b" num_pins="36"/>
167-
<output name="out" num_pins="72"/>
168-
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
169-
<pinlocations pattern="spread"/>
166+
<sub_tile name="mult_36">
167+
<equivalent_sites>
168+
<site pb_type="mult_36" pin_mapping="direct"/>
169+
</equivalent_sites>
170+
<input name="a" num_pins="36"/>
171+
<input name="b" num_pins="36"/>
172+
<output name="out" num_pins="72"/>
173+
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
174+
<pinlocations pattern="spread"/>
175+
</sub_tile>
170176
</tile>
171177
<tile name="memory" height="6">
172-
<equivalent_sites>
173-
<site pb_type="memory"/>
174-
</equivalent_sites>
175-
<input name="addr1" num_pins="15"/>
176-
<input name="addr2" num_pins="15"/>
177-
<input name="data" num_pins="64"/>
178-
<input name="we1" num_pins="1"/>
179-
<input name="we2" num_pins="1"/>
180-
<output name="out" num_pins="64"/>
181-
<clock name="clk" num_pins="1"/>
182-
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
183-
<pinlocations pattern="spread"/>
178+
<sub_tile name="memory">
179+
<equivalent_sites>
180+
<site pb_type="memory" pin_mapping="direct"/>
181+
</equivalent_sites>
182+
<input name="addr1" num_pins="15"/>
183+
<input name="addr2" num_pins="15"/>
184+
<input name="data" num_pins="64"/>
185+
<input name="we1" num_pins="1"/>
186+
<input name="we2" num_pins="1"/>
187+
<output name="out" num_pins="64"/>
188+
<clock name="clk" num_pins="1"/>
189+
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
190+
<pinlocations pattern="spread"/>
191+
</sub_tile>
184192
</tile>
185193
</tiles>
186194
<!-- ODIN II specific config ends -->

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