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ODIN_II/SRC/partial_map.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,7 @@ void partial_map_node(nnode_t* node, short traverse_number, netlist_t* netlist);
5858
void instantiate_not_logic(nnode_t* node, short mark, netlist_t* netlist);
5959
bool eliminate_buffer(nnode_t* node, short, netlist_t*);
6060
void instantiate_bitwise_logic(nnode_t* node, operation_list op, short mark, netlist_t* netlist);
61-
void instantiate_bitwise_reduction(nnode_t* node, operation_list op, short mark, netlist_t* netlist);
61+
void instantiate_bitwise_reduction(nnode_t* node, operation_list op, short mark);
6262
void instantiate_logical_logic(nnode_t* node, operation_list op, short mark, netlist_t* netlist);
6363
void instantiate_EQUAL(nnode_t* node, operation_list type, short mark, netlist_t* netlist);
6464
void instantiate_GE(nnode_t* node, operation_list type, short mark, netlist_t* netlist);
@@ -627,11 +627,11 @@ void instantiate_logical_logic(nnode_t* node, operation_list op, short mark, net
627627
/* connect inputs. In the case that a signal is smaller than the other then zero pad */
628628
for (i = 0; i < width_a; i++) {
629629
/* Joining the inputs to the input 1 of that gate */
630-
remap_pin_to_new_node(node->input_pins[i], reduction1, i);
630+
remap_pin_to_new_node(node->input_pins[i], reduction1, i);
631631
}
632632
for (i = 0; i < width_b; i++) {
633633
/* Joining the inputs to the input 1 of that gate */
634-
remap_pin_to_new_node(node->input_pins[i + port_B_offset], reduction2, i);
634+
remap_pin_to_new_node(node->input_pins[i + port_B_offset], reduction2, i);
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}
636636

637637
connect_nodes(reduction1, 0, new_logic_cell, 0);
@@ -647,7 +647,7 @@ void instantiate_logical_logic(nnode_t* node, operation_list op, short mark, net
647647
* (function: instantiate_bitwise_reduction )
648648
* Makes 2 input gates to break into bitwise
649649
*-------------------------------------------------------------------------------------------*/
650-
void instantiate_bitwise_reduction(nnode_t* node, operation_list op, short mark, netlist_t* netlist) {
650+
void instantiate_bitwise_reduction(nnode_t* node, operation_list op, short mark) {
651651
int i;
652652
int width_a;
653653
nnode_t* new_logic_cell;
@@ -695,7 +695,7 @@ void instantiate_bitwise_reduction(nnode_t* node, operation_list op, short mark,
695695
/* connect inputs. In the case that a signal is smaller than the other then zero pad */
696696
for (i = 0; i < width_a; i++) {
697697
/* Joining the inputs to the input 1 of that gate */
698-
remap_pin_to_new_node(node->input_pins[i], new_logic_cell, i);
698+
remap_pin_to_new_node(node->input_pins[i], new_logic_cell, i);
699699
}
700700

701701
remap_pin_to_new_node(node->output_pins[0], new_logic_cell, 0);

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