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Merge pull request #1930 from RapidSilicon/edge_switch/edge_sink_node
RRGraphView edge_sink_node()/edge_switch() Implementation
2 parents ac252ad + 52a60bf commit 1333ba7

22 files changed

+98
-114
lines changed

README.developers.md

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -92,7 +92,7 @@ The overall approach is similar, but we call out the differences below.
9292
9393
## Commit Messages
9494
95-
Commit messages are an important part of understanding the code base and it's history.
95+
Commit messages are an important part of understanding the code base and its history.
9696
It is therefore *extremely* important to provide the following information in the commit message:
9797
9898
* What is being changed?

README.md

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
[![Build Status](https://github.com/verilog-to-routing/vtr-verilog-to-routing/workflows/Test/badge.svg)](https://github.com/verilog-to-routing/vtr-verilog-to-routing/actions?query=workflow%3ATest) [![Documentation Status](https://readthedocs.org/projects/vtr/badge/?version=latest)](http://docs.verilogtorouting.org/en/latest/)
44

55
## Introduction
6-
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development.
6+
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide an open-source framework for conducting FPGA architecture and CAD research and development.
77
The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
88
It then performs:
99
* Elaboration & Synthesis (ODIN II)

utils/fasm/test/test_fasm.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -256,8 +256,8 @@ TEST_CASE("fasm_integration_test", "[fasm]") {
256256
const auto& rr_graph = device_ctx.rr_graph;
257257
for(size_t inode = 0; inode < device_ctx.rr_nodes.size(); ++inode) {
258258
for(t_edge_size iedge = 0; iedge < rr_graph.num_edges(RRNodeId(inode)); ++iedge) {
259-
auto sink_inode = device_ctx.rr_nodes[inode].edge_sink_node(iedge);
260-
auto switch_id = device_ctx.rr_nodes[inode].edge_switch(iedge);
259+
auto sink_inode = size_t(rr_graph.edge_sink_node(RRNodeId(inode), iedge));
260+
auto switch_id = rr_graph.edge_switch(RRNodeId(inode), iedge);
261261
auto value = vtr::string_fmt("%d_%d_%zu",
262262
inode, sink_inode, switch_id);
263263

vpr/src/device/rr_graph_view.h

Lines changed: 19 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -258,6 +258,18 @@ class RRGraphView {
258258
inline const char* node_side_string(RRNodeId node) const {
259259
return node_storage_.node_side_string(node);
260260
}
261+
/** @brief Get the switch id that represents the iedge'th outgoing edge from a specific node
262+
* TODO: We may need to revisit this API and think about higher level APIs, like ``switch_delay()``
263+
**/
264+
inline short edge_switch(RRNodeId id, t_edge_size iedge) const {
265+
return node_storage_.edge_switch(id, iedge);
266+
}
267+
/** @brief Get the destination node for the iedge'th edge from specified RRNodeId.
268+
* This method should generally not be used, and instead first_edge and
269+
* last_edge should be used.*/
270+
inline RRNodeId edge_sink_node(RRNodeId id, t_edge_size iedge) const {
271+
return node_storage_.edge_sink_node(id, iedge);
272+
}
261273

262274
/** @brief Get the number of configurable edges. This function is inlined for runtime optimization. */
263275
inline t_edge_size num_configurable_edges(RRNodeId node) const {
@@ -305,13 +317,6 @@ class RRGraphView {
305317
* This API is very powerful and developers should not use it unless it is necessary,
306318
* e.g the node type is unknown. If the node type is known, the more specific routines, `node_pin_num()`,
307319
* `node_track_num()`and `node_class_num()`, for different types of nodes should be used.*/
308-
/** @brief Return detailed routing segment information with a given id* @note The routing segments here may not be exactly same as those defined in architecture file. They have been
309-
* adapted to fit the context of routing resource graphs.
310-
*/
311-
312-
inline const t_segment_inf& rr_segments(RRSegmentId seg_id) const {
313-
return rr_segments_[seg_id];
314-
}
315320
inline short node_ptc_num(RRNodeId node) const {
316321
return node_storage_.node_ptc_num(node);
317322
}
@@ -338,6 +343,13 @@ class RRGraphView {
338343
RRIndexedDataId node_cost_index(RRNodeId node) const {
339344
return node_storage_.node_cost_index(node);
340345
}
346+
/** @brief Return detailed routing segment information with a given id* @note The routing segments here may not be exactly same as those defined in architecture file. They have been
347+
* adapted to fit the context of routing resource graphs.
348+
*/
349+
350+
inline const t_segment_inf& rr_segments(RRSegmentId seg_id) const {
351+
return rr_segments_[seg_id];
352+
}
341353

342354
/** @brief Return the fast look-up data structure for queries from client functions */
343355
const RRSpatialLookup& node_lookup() const {

vpr/src/draw/draw.cpp

Lines changed: 13 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1686,10 +1686,10 @@ static void draw_rr_edges(int inode, ezgl::renderer* g) {
16861686
return; /* Nothing to draw. */
16871687
}
16881688

1689-
from_ptc_num = rr_graph.node_ptc_num(RRNodeId(inode));
1689+
from_ptc_num = rr_graph.node_ptc_num(rr_node);
16901690

16911691
for (t_edge_size iedge = 0, l = rr_graph.num_edges(RRNodeId(inode)); iedge < l; iedge++) {
1692-
to_node = device_ctx.rr_nodes[inode].edge_sink_node(iedge);
1692+
to_node = size_t(rr_graph.edge_sink_node(rr_node, iedge));
16931693
to_type = rr_graph.node_type(RRNodeId(to_node));
16941694
to_ptc_num = rr_graph.node_ptc_num(RRNodeId(to_node));
16951695
bool edge_configurable = device_ctx.rr_nodes[inode].edge_is_configurable(iedge);
@@ -1772,8 +1772,8 @@ static void draw_rr_edges(int inode, ezgl::renderer* g) {
17721772
} else {
17731773
g->set_color(blk_DARKGREEN);
17741774
}
1775-
switch_type = device_ctx.rr_nodes[inode].edge_switch(iedge);
1776-
draw_chanx_to_chanx_edge(RRNodeId(inode), RRNodeId(to_node),
1775+
switch_type = rr_graph.edge_switch(rr_node, iedge);
1776+
draw_chanx_to_chanx_edge(rr_node, RRNodeId(to_node),
17771777
to_ptc_num, switch_type, g);
17781778
break;
17791779

@@ -1789,7 +1789,7 @@ static void draw_rr_edges(int inode, ezgl::renderer* g) {
17891789
} else {
17901790
g->set_color(blk_DARKGREEN);
17911791
}
1792-
switch_type = device_ctx.rr_nodes[inode].edge_switch(iedge);
1792+
switch_type = rr_graph.edge_switch(rr_node, iedge);
17931793
draw_chanx_to_chany_edge(inode, from_ptc_num, to_node,
17941794
to_ptc_num, FROM_X_TO_Y, switch_type, g);
17951795
break;
@@ -1842,7 +1842,7 @@ static void draw_rr_edges(int inode, ezgl::renderer* g) {
18421842
} else {
18431843
g->set_color(blk_DARKGREEN);
18441844
}
1845-
switch_type = device_ctx.rr_nodes[inode].edge_switch(iedge);
1845+
switch_type = rr_graph.edge_switch(rr_node, iedge);
18461846
draw_chanx_to_chany_edge(to_node, to_ptc_num, inode,
18471847
from_ptc_num, FROM_Y_TO_X, switch_type, g);
18481848
break;
@@ -1860,8 +1860,8 @@ static void draw_rr_edges(int inode, ezgl::renderer* g) {
18601860
} else {
18611861
g->set_color(blk_DARKGREEN);
18621862
}
1863-
switch_type = device_ctx.rr_nodes[inode].edge_switch(iedge);
1864-
draw_chany_to_chany_edge(RRNodeId(inode), RRNodeId(to_node),
1863+
switch_type = rr_graph.edge_switch(rr_node, iedge);
1864+
draw_chany_to_chany_edge(rr_node, RRNodeId(to_node),
18651865
to_ptc_num, switch_type, g);
18661866
break;
18671867

@@ -2519,7 +2519,7 @@ void draw_partial_route(const std::vector<int>& rr_nodes_to_draw, ezgl::renderer
25192519
auto prev_type = rr_graph.node_type(RRNodeId(prev_node));
25202520

25212521
auto iedge = find_edge(prev_node, inode);
2522-
auto switch_type = device_ctx.rr_nodes[prev_node].edge_switch(iedge);
2522+
auto switch_type = rr_graph.edge_switch(RRNodeId(prev_node), iedge);
25232523

25242524
switch (rr_type) {
25252525
case OPIN: {
@@ -2698,12 +2698,11 @@ void draw_highlight_fan_in_fan_out(const std::set<int>& nodes) {
26982698
t_draw_state* draw_state = get_draw_state_vars();
26992699
auto& device_ctx = g_vpr_ctx.device();
27002700
const auto& rr_graph = device_ctx.rr_graph;
2701-
27022701
for (auto node : nodes) {
27032702
/* Highlight the fanout nodes in red. */
27042703
for (t_edge_size iedge = 0, l = rr_graph.num_edges(RRNodeId(node));
27052704
iedge < l; iedge++) {
2706-
int fanout_node = device_ctx.rr_nodes[node].edge_sink_node(iedge);
2705+
int fanout_node = size_t(rr_graph.edge_sink_node(RRNodeId(node), iedge));
27072706

27082707
if (draw_state->draw_rr_node[node].color == ezgl::MAGENTA
27092708
&& draw_state->draw_rr_node[fanout_node].color
@@ -2722,8 +2721,7 @@ void draw_highlight_fan_in_fan_out(const std::set<int>& nodes) {
27222721
for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
27232722
for (t_edge_size iedge = 0, l = rr_graph.num_edges(RRNodeId(inode)); iedge < l;
27242723
iedge++) {
2725-
int fanout_node = device_ctx.rr_nodes[inode].edge_sink_node(
2726-
iedge);
2724+
int fanout_node = size_t(rr_graph.edge_sink_node(RRNodeId(node), iedge));
27272725
if (fanout_node == node) {
27282726
if (draw_state->draw_rr_node[node].color == ezgl::MAGENTA
27292727
&& draw_state->draw_rr_node[inode].color
@@ -2825,13 +2823,12 @@ void draw_expand_non_configurable_rr_nodes_recurr(int from_node,
28252823
std::set<int>& expanded_nodes) {
28262824
auto& device_ctx = g_vpr_ctx.device();
28272825
const auto& rr_graph = device_ctx.rr_graph;
2828-
28292826
expanded_nodes.insert(from_node);
28302827

28312828
for (t_edge_size iedge = 0;
28322829
iedge < rr_graph.num_edges(RRNodeId(from_node)); ++iedge) {
28332830
bool edge_configurable = device_ctx.rr_nodes[from_node].edge_is_configurable(iedge);
2834-
int to_node = device_ctx.rr_nodes[from_node].edge_sink_node(iedge);
2831+
int to_node = size_t(rr_graph.edge_sink_node(RRNodeId(from_node), iedge));
28352832

28362833
if (!edge_configurable && !expanded_nodes.count(to_node)) {
28372834
draw_expand_non_configurable_rr_nodes_recurr(to_node,
@@ -3788,7 +3785,7 @@ static t_edge_size find_edge(int prev_inode, int inode) {
37883785
const auto& rr_graph = device_ctx.rr_graph;
37893786
for (t_edge_size iedge = 0;
37903787
iedge < rr_graph.num_edges(RRNodeId(prev_inode)); ++iedge) {
3791-
if (device_ctx.rr_nodes[prev_inode].edge_sink_node(iedge) == inode) {
3788+
if (size_t(rr_graph.edge_sink_node(RRNodeId(prev_inode), iedge)) == size_t(inode)) {
37923789
return iedge;
37933790
}
37943791
}

vpr/src/place/timing_place_lookup.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1161,22 +1161,21 @@ bool directconnect_exists(int src_rr_node, int sink_rr_node) {
11611161
//which starts at src_rr_node and ends at sink_rr_node
11621162
auto& device_ctx = g_vpr_ctx.device();
11631163
const auto& rr_graph = device_ctx.rr_graph;
1164-
auto& rr_nodes = device_ctx.rr_nodes;
11651164

11661165
VTR_ASSERT(rr_graph.node_type(RRNodeId(src_rr_node)) == SOURCE && rr_graph.node_type(RRNodeId(sink_rr_node)) == SINK);
11671166

11681167
//TODO: This is a constant depth search, but still may be too slow
11691168
for (t_edge_size i_src_edge = 0; i_src_edge < rr_graph.num_edges(RRNodeId(src_rr_node)); ++i_src_edge) {
1170-
int opin_rr_node = rr_nodes[src_rr_node].edge_sink_node(i_src_edge);
1169+
int opin_rr_node = size_t(rr_graph.edge_sink_node(RRNodeId(src_rr_node), i_src_edge));
11711170

11721171
if (rr_graph.node_type(RRNodeId(opin_rr_node)) != OPIN) continue;
11731172

11741173
for (t_edge_size i_opin_edge = 0; i_opin_edge < rr_graph.num_edges(RRNodeId(opin_rr_node)); ++i_opin_edge) {
1175-
int ipin_rr_node = rr_nodes[opin_rr_node].edge_sink_node(i_opin_edge);
1174+
int ipin_rr_node = size_t(rr_graph.edge_sink_node(RRNodeId(opin_rr_node), i_opin_edge));
11761175
if (rr_graph.node_type(RRNodeId(ipin_rr_node)) != IPIN) continue;
11771176

11781177
for (t_edge_size i_ipin_edge = 0; i_ipin_edge < rr_graph.num_edges(RRNodeId(ipin_rr_node)); ++i_ipin_edge) {
1179-
if (sink_rr_node == rr_nodes[ipin_rr_node].edge_sink_node(i_ipin_edge)) {
1178+
if (size_t(sink_rr_node) == size_t(rr_graph.edge_sink_node(RRNodeId(ipin_rr_node), i_ipin_edge))) {
11801179
return true;
11811180
}
11821181
}

vpr/src/power/power.cpp

Lines changed: 10 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -814,16 +814,15 @@ static void power_usage_routing(t_power_usage* power_usage,
814814
t_trace* trace;
815815

816816
for (trace = route_ctx.trace[net_id].head; trace != nullptr; trace = trace->next) {
817-
auto node = device_ctx.rr_nodes[trace->index];
818817
t_rr_node_power* node_power = &rr_node_power[trace->index];
819818

820819
if (node_power->visited) {
821820
continue;
822821
}
823822

824823
for (t_edge_size edge_idx = 0; edge_idx < rr_graph.num_edges(RRNodeId(trace->index)); edge_idx++) {
825-
const auto& next_node_id = node.edge_sink_node(edge_idx);
826-
if (next_node_id != OPEN) {
824+
const auto& next_node_id = size_t(rr_graph.edge_sink_node(RRNodeId(trace->index), edge_idx));
825+
if (next_node_id != size_t(OPEN)) {
827826
t_rr_node_power* next_node_power = &rr_node_power[next_node_id];
828827

829828
switch (rr_graph.node_type(RRNodeId(next_node_id))) {
@@ -857,7 +856,6 @@ static void power_usage_routing(t_power_usage* power_usage,
857856
/* Calculate power of all routing entities */
858857
for (size_t rr_node_idx = 0; rr_node_idx < device_ctx.rr_nodes.size(); rr_node_idx++) {
859858
t_power_usage sub_power_usage;
860-
auto node = device_ctx.rr_nodes[rr_node_idx];
861859
RRNodeId rr_node = RRNodeId(rr_node_idx);
862860
t_rr_node_power* node_power = &rr_node_power[rr_node_idx];
863861
float C_wire;
@@ -982,9 +980,9 @@ static void power_usage_routing(t_power_usage* power_usage,
982980
connectionbox_fanout = 0;
983981
switchbox_fanout = 0;
984982
for (t_edge_size iedge = 0; iedge < rr_graph.num_edges(rr_node); iedge++) {
985-
if (node.edge_switch(iedge) == routing_arch->wire_to_rr_ipin_switch) {
983+
if (rr_graph.edge_switch(rr_node, iedge) == routing_arch->wire_to_rr_ipin_switch) {
986984
connectionbox_fanout++;
987-
} else if (node.edge_switch(iedge) == routing_arch->delayless_switch) {
985+
} else if (rr_graph.edge_switch(rr_node, iedge) == routing_arch->delayless_switch) {
988986
/* Do nothing */
989987
} else {
990988
switchbox_fanout++;
@@ -1209,7 +1207,6 @@ void power_routing_init(const t_det_routing_arch* routing_arch) {
12091207
for (size_t rr_node_idx = 0; rr_node_idx < device_ctx.rr_nodes.size(); rr_node_idx++) {
12101208
t_edge_size fanout_to_IPIN = 0;
12111209
t_edge_size fanout_to_seg = 0;
1212-
auto node = device_ctx.rr_nodes[rr_node_idx];
12131210
t_rr_node_power* node_power = &rr_node_power[rr_node_idx];
12141211
const t_edge_size node_fan_in = rr_graph.node_fan_in(RRNodeId(rr_node_idx));
12151212

@@ -1226,9 +1223,9 @@ void power_routing_init(const t_det_routing_arch* routing_arch) {
12261223
case CHANX:
12271224
case CHANY:
12281225
for (t_edge_size iedge = 0; iedge < rr_graph.num_edges(RRNodeId(rr_node_idx)); iedge++) {
1229-
if (node.edge_switch(iedge) == routing_arch->wire_to_rr_ipin_switch) {
1226+
if (rr_graph.edge_switch(RRNodeId(rr_node_idx), iedge) == routing_arch->wire_to_rr_ipin_switch) {
12301227
fanout_to_IPIN++;
1231-
} else if (node.edge_switch(iedge) != routing_arch->delayless_switch) {
1228+
} else if (rr_graph.edge_switch(RRNodeId(rr_node_idx), iedge) != routing_arch->delayless_switch) {
12321229
fanout_to_seg++;
12331230
}
12341231
}
@@ -1258,14 +1255,12 @@ void power_routing_init(const t_det_routing_arch* routing_arch) {
12581255

12591256
/* Populate driver switch type */
12601257
for (size_t rr_node_idx = 0; rr_node_idx < device_ctx.rr_nodes.size(); rr_node_idx++) {
1261-
auto node = device_ctx.rr_nodes[rr_node_idx];
1262-
12631258
for (t_edge_size edge_idx = 0; edge_idx < rr_graph.num_edges(RRNodeId(rr_node_idx)); edge_idx++) {
1264-
if (node.edge_sink_node(edge_idx) != OPEN) {
1265-
if (rr_node_power[node.edge_sink_node(edge_idx)].driver_switch_type == OPEN) {
1266-
rr_node_power[node.edge_sink_node(edge_idx)].driver_switch_type = node.edge_switch(edge_idx);
1259+
if (size_t(rr_graph.edge_sink_node(RRNodeId(rr_node_idx), edge_idx))) {
1260+
if (rr_node_power[size_t(rr_graph.edge_sink_node(RRNodeId(rr_node_idx), edge_idx))].driver_switch_type == OPEN) {
1261+
rr_node_power[size_t(rr_graph.edge_sink_node(RRNodeId(rr_node_idx), edge_idx))].driver_switch_type = rr_graph.edge_switch(RRNodeId(rr_node_idx), edge_idx);
12671262
} else {
1268-
VTR_ASSERT(rr_node_power[node.edge_sink_node(edge_idx)].driver_switch_type == node.edge_switch(edge_idx));
1263+
VTR_ASSERT(rr_node_power[size_t(rr_graph.edge_sink_node(RRNodeId(rr_node_idx), edge_idx))].driver_switch_type == rr_graph.edge_switch(RRNodeId(rr_node_idx), edge_idx));
12691264
}
12701265
}
12711266
}

vpr/src/route/check_route.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -310,7 +310,7 @@ static bool check_adjacent(int from_node, int to_node) {
310310
reached = false;
311311

312312
for (t_edge_size iconn = 0; iconn < rr_graph.num_edges(RRNodeId(from_node)); iconn++) {
313-
if (device_ctx.rr_nodes[from_node].edge_sink_node(iconn) == to_node) {
313+
if (size_t(rr_graph.edge_sink_node(RRNodeId(from_node), iconn)) == size_t(to_node)) {
314314
reached = true;
315315
break;
316316
}

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