Merge branch 'master' into 3d_track_to_track_conn

Author: saaramahmoudi

blifexplorer/src/container.cpp

@@ -929,25 +929,23 @@ void Container::showActivity()
 
 void Container::getActivityInformation()
 {
-    //right now it is a dummy function. the activity values are
-    //generated randomly
+    // Right now, it is a dummy function. The activity values are
+    // generated randomly.
     QHash<QString, nnode_t *>::const_iterator blockIterator = odinTable.constBegin();
 
     while(blockIterator != odinTable.constEnd()){
-         QString name = blockIterator.key();
-         LogicUnit* visNode = unithashtable[name];
-         //get all connections outgoing and advise them to
-         //represent the activity by color
-         QList<Wire*> outgoingWires = visNode->getOutCons();
-         foreach(Wire* wire, outgoingWires){
-             int act = qrand() % 255;
-             wire->setActivity(act);
-
-         }
+        QString name = blockIterator.key();
+        LogicUnit* visNode = unithashtable[name];
+        // Get all connections outgoing and advise them to
+        // represent the activity by color.
+        QList<Wire*> outgoingWires = visNode->getOutCons();
+        foreach(Wire* wire, outgoingWires){
+            int act = QRandomGenerator::global()->bounded(255); // Use QRandomGenerator
+            wire->setActivity(act);
+        }
         ++blockIterator;
     }
 }
-
 /*---------------------------------------------------------------------------------------------
  * (function: showSimulationStep)
  *-------------------------------------------------------------------------------------------*/

blifexplorer/src/mainwindow.cpp

@@ -271,10 +271,10 @@ void MainWindow::fontSizeChanged(const QString &)
  *-------------------------------------------------------------------------------------------*/
 void MainWindow::sceneScaleChanged(int scale)
 {
-    double newScale = scale/100.0;
-    QMatrix oldMatrix = view->matrix();
-    view->resetMatrix();
-    view->translate(oldMatrix.dx(), oldMatrix.dy());
+    double newScale = scale / 100.0;
+    QTransform oldTransform = view->transform(); // Use transform() instead of matrix()
+    view->resetTransform(); // Changed from resetMatrix() to resetTransform()
+    view->translate(oldTransform.dx(), oldTransform.dy()); // Use dx() and dy() from QTransform
     view->scale(newScale, newScale);
 }
 
@@ -915,7 +915,7 @@ void MainWindow::openFileWithOdin(){
                                                    tr("Open BLIF"),
                                                    QDir::homePath(),
                                                    tr("BLIF files (*.blif);;All files (*.*)"),
-                                                   0,
+                                                nullptr, // No parent,
                                                    QFileDialog::DontUseNativeDialog);
 
     myContainer->setFilename(actBlifFilename);
@@ -925,10 +925,10 @@ void MainWindow::openFileWithOdin(){
         //An error occured
         QMessageBox msgBox(QMessageBox::Warning, tr("No Structure Found in File"),
                            "The file you tried to explore does not contain any structures or could not be opened. Please select another file."
-                           , 0, this);
-        msgBox.addButton(tr("Open &Again"), QMessageBox::AcceptRole);
-        msgBox.addButton(tr("&Continue"), QMessageBox::RejectRole);
-        if (msgBox.exec() == QMessageBox::AcceptRole)
+                           
+                           , QMessageBox::Open | QMessageBox::Cancel, this);
+        msgBox.setDefaultButton(QMessageBox::Open);
+        if (msgBox.exec() == QMessageBox::Open)
             openFileWithOdin();
 
     }else{

doc/src/quickstart/index.rst

@@ -48,6 +48,12 @@ On most unix-like systems you can run:
 
     > make
 
+The default front-end for VTR is :ref:`Parmys<parmys>`, but you can build with ODIN II instead using the command below. This is required to run :ref:`Synthesizing with ODIN II<synthesizing_with_odin_ii>`.
+
+.. code-block:: bash
+
+    > make CMAKE_PARAMS="-DWITH_ODIN=on"
+
 from the VTR root directory (hereafter referred to as :term:`$VTR_ROOT`) to build VTR.
 
 .. note:: 
@@ -63,6 +69,8 @@ from the VTR root directory (hereafter referred to as :term:`$VTR_ROOT`) to buil
     * define VTR_ROOT as a variable in your shell (e.g. if ``~/trees/vtr`` is the path to the VTR source tree on your machine, run the equivalent of ``VTR_ROOT=~/trees/vtr`` in BASH) which will allow you to run the commands as written in this guide, or
     * manually replace `$VTR_ROOT` in the example commands below with your path to the VTR source tree.
 
+
+
 For more details on building VTR on various operating systems/platforms see :doc:`Building VTR</BUILDING>`.
 
 
@@ -235,6 +243,7 @@ Next we need to run the three main sets of tools:
 * :ref:`ABC` performs 'logic optimization' which simplifies the circuit logic, and 'technology mapping' which converts logic equations into the Look-Up-Tables (LUTs) available on an FPGA, and
 * :ref:`VPR` which performs packing, placement and routing of the circuit to implement it on the targetted FPGA architecture.
 
+.. _synthesizing_with_odin_ii:
 Synthesizing with ODIN II
 ~~~~~~~~~~~~~~~~~~~~~~~~~
 

doc/src/tutorials/flow/basic_flow.rst

@@ -17,16 +17,9 @@ The following steps show you to run the VTR design flow to map a sample circuit
 
         $VTR_ROOT/vtr_flow/scripts/run_vtr_task.py basic_no_timing 
         
-    The subdirectory ``regression_tests/vtr_reg_basic`` contains tests that are to be run before each commit. They check for basic functionallity to make sure nothing was           extremely out of order. This command runs the VTR flow on a set of circuits and a single architecture. 
+    The subdirectory ``regression_tests/vtr_reg_basic`` contains tests that are to be run before each commit. They check for basic functionality to make sure nothing was extremely out of order. This command runs the VTR flow on a set of circuits and a single architecture. 
     The files generated from the run are stored in ``basic_no_timing/run[#]`` where ``[#]`` is the number of runs you have done.
-    If this is your first time running the flow, the results will be stored in basic_no_timing/run001.
-    When the script completes, enter the following command:
-
-    .. code-block:: shell
-
-         ../../../scripts/python_libs/vtr/parse_vtr_task.py basic_no_timing/
-
-    This parses out the information of the VTR run and outputs the results in a text file called ``run[#]/parse_results.txt``.
+    If this is your first time running the flow, the results will be stored in basic_no_timing/run001. The command parses out the information of the VTR run and outputs the results in a text file called ``run[#]/parse_results.txt``.
 
     More info on how to run the flow on multiple circuits and architectures along with different options later.
     Before that, we need to ensure that the run that you have done works.

doc/src/vpr/basic_flow.rst

@@ -4,7 +4,7 @@ Basic flow
 The Place and Route process in VPR consists of several steps:
 
 - Packing (combinines primitives into complex blocks)
-- Placment (places complex blocks within the FPGA grid)
+- Placement (places complex blocks within the FPGA grid)
 - Routing (determines interconnections between blocks)
 - Analysis (analyzes the implementation)
 

doc/src/vpr/command_line_usage.rst

@@ -1299,6 +1299,7 @@ The following options are only valid when the router is in timing-driven mode (t
     **Default:** ``1.2``
 
 .. option:: --router_profiler_astar_fac <float>
+    
     Controls the directedness of the timing-driven router's exploration when doing router delay profiling of an architecture.
     The router delay profiling step is currently used to calculate the place delay matrix lookup.
     Values between 1 and 2 are resonable; higher values trade some quality for reduced run-time.

libs/libarchfpga/src/device_grid.cpp

@@ -1,14 +1,16 @@
 #include "device_grid.h"
 
+#include <utility>
+
 DeviceGrid::DeviceGrid(std::string grid_name, vtr::NdMatrix<t_grid_tile, 3> grid)
-    : name_(grid_name)
-    , grid_(grid) {
+    : name_(std::move(grid_name))
+    , grid_(std::move(grid)) {
     count_instances();
 }
 
 DeviceGrid::DeviceGrid(std::string grid_name, vtr::NdMatrix<t_grid_tile, 3> grid, std::vector<t_logical_block_type_ptr> limiting_res)
-    : DeviceGrid(grid_name, grid) {
-    limiting_resources_ = limiting_res;
+    : DeviceGrid(std::move(grid_name), std::move(grid)) {
+    limiting_resources_ = std::move(limiting_res);
 }
 
 size_t DeviceGrid::num_instances(t_physical_tile_type_ptr type, int layer_num) const {

libs/libarchfpga/src/echo_arch.cpp

@@ -13,6 +13,10 @@
 
 using vtr::t_linked_vptr;
 
+/// @brief indices to lookup IPIN connection block switch name
+constexpr int ipin_cblock_switch_index_within_die = 0;
+constexpr int ipin_cblock_switch_index_between_dice = 1;
+
 void PrintArchInfo(FILE* Echo, const t_arch* arch);
 static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level);
 static void PrintPb_types_recPower(FILE* Echo,
@@ -231,10 +235,14 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
             break;
     }
 
-    fprintf(Echo, "\tInput Connect Block Switch Name Within a Same Die: %s\n", arch->ipin_cblock_switch_name[0].c_str());
+    fprintf(Echo, "\tInput Connect Block Switch Name Within a Same Die: %s\n", arch->ipin_cblock_switch_name[ipin_cblock_switch_index_within_die].c_str());
+    
     //if there is more than one layer available, print the connection block switch name that is used for connection between two dice
-    if (arch->grid_layouts.size() > 1) {
-        fprintf(Echo, "\tInput Connect Block Switch Name Between Two Dice: %s\n", arch->ipin_cblock_switch_name[1].c_str());
+    for(const auto& layout : arch->grid_layouts){
+        int num_layers = (int)layout.layers.size();
+        if(num_layers > 1){
+            fprintf(Echo, "\tInput Connect Block Switch Name Between Two Dice: %s\n", arch->ipin_cblock_switch_name[ipin_cblock_switch_index_between_dice].c_str());
+        }
     }
 
     fprintf(Echo, "*************************************************\n\n");
@@ -287,9 +295,12 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
             fprintf(Echo, "\t\t\t\ttype unidir mux_name for within die connections: %s\n",
                     arch->Switches[seg.arch_wire_switch].name.c_str());
             //if there is more than one layer available, print the segment switch name that is used for connection between two dice
-            if (arch->grid_layouts.size() > 1) {
-                fprintf(Echo, "\t\t\t\ttype unidir mux_name for between two dice connections: %s\n",
+            for(const auto& layout : arch->grid_layouts){
+                int num_layers = (int)layout.layers.size();
+                if(num_layers > 1){
+                    fprintf(Echo, "\t\t\t\ttype unidir mux_name for between two dice connections: %s\n",
                         arch->Switches[seg.arch_opin_between_dice_switch].name.c_str());
+                }
             }
         } else { //Should be bidir
             fprintf(Echo, "\t\t\t\ttype bidir wire_switch %s arch_opin_switch %s\n",

libs/libvqm/vqm_dll.cpp

@@ -112,13 +112,13 @@ VQM_DLL_API t_module *vqm_parse_file(char *filename)
 
 VQM_DLL_API int vqm_get_error_message(char *message_buffer, int length)
 {
-	int result = -1;
-	int temp = strlen(most_recent_error);
+    int result = -1;
+    int temp = strlen(most_recent_error);
 
-	if (temp <= length)
-	{
-		strcpy(message_buffer, message_buffer);
-		result = temp;
-	}
-	return result;
+    if (temp < length) // Note: Changed to '<' to avoid buffer overflow
+    {
+        strcpy(message_buffer, most_recent_error); // Copy 'most_recent_error' to 'message_buffer'
+        result = temp;
+    }
+    return result;
 }

libs/libvqm/vqm_parser.y

@@ -38,11 +38,11 @@ extern int yylex(void);
 
 %union
 {
-	uintptr_t value;
-	char *string;
+    uintptr_t value;
+    char *string;
 }
 %parse-param {t_parse_info* parse_info}
-%error-verbose
+%define parse.error verbose
 /********************************************************/
 /**** DEFINE TOKENS *************************************/
 /********************************************************/

libs/libvtrutil/src/vtr_ndmatrix.h

@@ -288,7 +288,7 @@ class NdMatrixBase {
         data_ = std::make_unique<T[]>(size());
     }
 
-    ///@brief Returns the size of the matrix (number of elements) calucated from the current dimensions
+    ///@brief Returns the size of the matrix (number of elements) calculated from the current dimensions
     size_t calc_size() const {
         ///@brief Size is the product of all dimension sizes
         size_t cnt = dim_size(0);
@@ -310,7 +310,7 @@ class NdMatrixBase {
  * 
  * Examples:
  * 
- *       //A 2-dimensional matrix with indicies [0..4][0..9]
+ *       //A 2-dimensional matrix with indices [0..4][0..9]
  *       NdMatrix<int,2> m1({5,10});
  * 
  *       //Accessing an element
@@ -319,17 +319,17 @@ class NdMatrixBase {
  *       //Setting an element
  *       m1[2][8] = 0;
  * 
- *       //A 3-dimensional matrix with indicies [0..4][0..9][0..19]
+ *       //A 3-dimensional matrix with indices [0..4][0..9][0..19]
  *       NdMatrix<int,3> m2({5,10,20});
  * 
- *       //A 2-dimensional matrix with indicies [0..4][0..9], with all entries
+ *       //A 2-dimensional matrix with indices [0..4][0..9], with all entries
  *       //initialized to 42
  *       NdMatrix<int,2> m3({5,10}, 42);
  * 
  *       //Filling all entries with value 101
  *       m3.fill(101);
  * 
- *       //Resizing an existing matrix (all values reset to default constucted value)
+ *       //Resizing an existing matrix (all values reset to default constructed value)
  *       m3.resize({5,5})
  * 
  *       //Resizing an existing matrix (all elements set to value 88)

odin_ii/src/ast/ast_loop_unroll.cpp

@@ -312,19 +312,18 @@ bool is_unsupported_post(ast_node_t* node, ast_node_t* symbol) {
 
 post_condition_function resolve_binary_operation(ast_node_t* node) {
     if (node->type == NUMBERS) {
-        return [=](long value) {
-            /* 
-             * this lambda triggers a warning for unused variable unless
-             * we use value to generate a 0
-             */
-            return node->types.vnumber->get_value() + (value - value);
+        return [=](long value) noexcept {
+            (void)value; // Indicate that value is unused
+            return node->types.vnumber->get_value();
         };
     } else if (node->type == IDENTIFIERS) {
-        return [=](long value) {
+        return [=](long value) noexcept {
+            (void)value; // Indicate that value is unused
             return value;
         };
     } else {
-        return [=](long value) {
+        return [=](long value) noexcept {
+            (void)value; // Indicate that value is unused
             post_condition_function left_func = resolve_binary_operation(node->children[0]);
             post_condition_function right_func = resolve_binary_operation(node->children[1]);
             switch (node->types.operation.op) {
@@ -343,6 +342,7 @@ post_condition_function resolve_binary_operation(ast_node_t* node) {
     }
 }
 
+
 /*
  *  (function: resolve_post_condition)
  *  return a lambda which gives the next value

odin_ii/src/verilog/verilog_bison.y

@@ -52,6 +52,7 @@ int yylex(void);
 %define parse.error verbose
 
 %locations
+%expect 2
 
 %union{
 	char *id_name;
@@ -208,6 +209,8 @@ int yylex(void);
 %type <node> list_of_generate_block_items generate_item generate_block_item generate loop_generate_construct if_generate_construct 
 %type <node> case_generate_construct case_generate_item_list case_generate_items generate_block generate_localparam_declaration generate_defparam_declaration
 
+
+
 /* capture wether an operation is signed or not */
 %type <op> var_signedness
 

requirements.txt

@@ -4,7 +4,7 @@ psutil
 
 # Python linter and formatter
 click==8.0.2 # Our version of black needs an older version of click (https://stackoverflow.com/questions/71673404/importerror-cannot-import-name-unicodefun-from-click)
-black==20.8b1
+black==21.4b0
 pylint==2.7.4
 
 # Surelog

vpr/src/base/CheckSetup.cpp

@@ -31,33 +31,39 @@ void CheckSetup(const t_packer_opts& PackerOpts,
             "This is allowed, but strange, and circuit speed will suffer.\n");
     }
 
-    if ((false == Timing.timing_analysis_enabled)
+    if (!Timing.timing_analysis_enabled
         && (PlacerOpts.place_algorithm.is_timing_driven())) {
         /* May work, not tested */
         VPR_FATAL_ERROR(VPR_ERROR_OTHER,
                         "Timing analysis must be enabled for timing-driven placement.\n");
     }
 
-    if (!PlacerOpts.doPlacement && ("" != PlacerOpts.constraints_file)) {
+    if (!PlacerOpts.doPlacement && (!PlacerOpts.constraints_file.empty())) {
         VPR_FATAL_ERROR(VPR_ERROR_OTHER,
                         "A block location file requires that placement is enabled.\n");
     }
 
-    if (PlacerOpts.place_static_move_prob.size() != NUM_PL_MOVE_TYPES) {
+    if (PlacerOpts.place_algorithm.is_timing_driven() &&
+        PlacerOpts.place_static_move_prob.size() > NUM_PL_MOVE_TYPES) {
         VPR_FATAL_ERROR(VPR_ERROR_OTHER,
-                        "The number of placer move probabilities should equal to the total number of supported moves. %d\n", PlacerOpts.place_static_move_prob.size());
+                        "The number of provided placer move probabilities (%d) should equal or less than the total number of supported moves (%d).\n",
+                        PlacerOpts.place_static_move_prob.size(),
+                        NUM_PL_MOVE_TYPES);
     }
 
-    if (PlacerOpts.place_static_notiming_move_prob.size() != NUM_PL_NONTIMING_MOVE_TYPES) {
+    if (!PlacerOpts.place_algorithm.is_timing_driven() &&
+        PlacerOpts.place_static_move_prob.size() > NUM_PL_NONTIMING_MOVE_TYPES) {
         VPR_FATAL_ERROR(VPR_ERROR_OTHER,
-                        "The number of placer non timing move probabilities should equal to the total number of supported moves. %d\n", PlacerOpts.place_static_notiming_move_prob.size());
+                        "The number of placer non timing move probabilities (%d) should equal to or less than the total number of supported moves (%d).\n",
+                        PlacerOpts.place_static_move_prob.size(),
+                        NUM_PL_MOVE_TYPES);
     }
 
     if (RouterOpts.doRouting) {
         if (!Timing.timing_analysis_enabled
             && (DEMAND_ONLY != RouterOpts.base_cost_type && DEMAND_ONLY_NORMALIZED_LENGTH != RouterOpts.base_cost_type)) {
             VPR_FATAL_ERROR(VPR_ERROR_OTHER,
-                            "base_cost_type must be demand_only or demand_only_normailzed_length when timing analysis is disabled.\n");
+                            "base_cost_type must be demand_only or demand_only_normalized_length when timing analysis is disabled.\n");
         }
     }