Merge branch 'openfpga' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into rem_warnings

Author: behzadmehmood

.gitignore

@@ -153,4 +153,4 @@ tags
 .idea
 cmake-build-debug
 cmake-build-release
-/.metadata/
+/.metadata/

doc/src/api/vprinternals/index.rst

@@ -10,3 +10,4 @@ VPR INTERNALS
    vpr_ui
    draw_files
    vpr_noc
+   vpr_router

doc/src/api/vprinternals/router_heap.rst

@@ -0,0 +1,31 @@
+==============
+Router Heap
+==============
+
+t_heap
+----------
+.. doxygenstruct:: t_heap
+   :project: vpr
+   :members:
+
+HeapInterface
+----------
+.. doxygenclass:: HeapInterface
+   :project: vpr
+   :members:
+
+HeapStorage
+----------
+.. doxygenclass:: HeapStorage
+   :project: vpr
+   :members:
+
+KAryHeap
+----------
+.. doxygenclass:: KAryHeap
+   :project: vpr
+
+FourAryHeap
+----------
+.. doxygenclass:: FourAryHeap
+   :project: vpr

doc/src/api/vprinternals/vpr_router.rst

@@ -0,0 +1,10 @@
+.. _router:
+
+=======
+VPR Router
+=======
+
+.. toctree::
+   :maxdepth: 1
+
+   router_heap

libs/libarchfpga/src/arch_util.cpp

@@ -35,7 +35,7 @@ const char* get_arch_file_name() {
     return arch_file_name;
 }
 
-InstPort::InstPort(std::string str) {
+InstPort::InstPort(const std::string& str) {
     std::vector<std::string> inst_port = vtr::split(str, ".");
 
     if (inst_port.size() == 1) {

libs/libarchfpga/src/arch_util.h

@@ -22,7 +22,7 @@ class InstPort {
     static constexpr int UNSPECIFIED = -1;
 
     InstPort() = default;
-    InstPort(std::string str);
+    InstPort(const std::string& str);
     std::string instance_name() const { return instance_.name; }
     std::string port_name() const { return port_.name; }
 

libs/libarchfpga/src/physical_types.h

@@ -2009,6 +2009,7 @@ struct t_arch {
 
     /* Xifan Tang: options for tileable routing architectures */
     bool tileable;
+    bool perimeter_cb;
     bool shrink_boundary;
     bool through_channel;
     bool opin2all_sides;

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -168,7 +168,7 @@ static void ProcessEquivalentSiteCustomConnection(pugi::xml_node Parent,
                                                   t_sub_tile* SubTile,
                                                   t_physical_tile_type* PhysicalTileType,
                                                   t_logical_block_type* LogicalBlockType,
-                                                  std::string site_name,
+                                                  const std::string& site_name,
                                                   const pugiutil::loc_data& loc_data);
 static void ProcessPinLocations(pugi::xml_node Locations,
                                 t_physical_tile_type* PhysicalTileType,
@@ -374,7 +374,7 @@ static bool attribute_to_bool(const pugi::xml_node node,
 
 static int find_switch_by_name(const t_arch& arch, const std::string& switch_name);
 
-e_side string_to_side(const std::string& side_str);
+static e_side string_to_side(const std::string& side_str);
 
 template<typename T>
 static T* get_type_by_name(const char* type_name, std::vector<T>& types);
@@ -1668,10 +1668,10 @@ static void ProcessPb_TypePort_Power(pugi::xml_node Parent, t_port* port, e_powe
 static void ProcessPb_TypePort(pugi::xml_node Parent, t_port* port, e_power_estimation_method power_method, const bool is_root_pb_type, const pugiutil::loc_data& loc_data) {
     std::vector<std::string> expected_attributes = {"name", "num_pins", "port_class"};
     if (is_root_pb_type) {
-        expected_attributes.push_back("equivalent");
+        expected_attributes.emplace_back("equivalent");
 
         if (Parent.name() == "input"s || Parent.name() == "clock"s) {
-            expected_attributes.push_back("is_non_clock_global");
+            expected_attributes.emplace_back("is_non_clock_global");
         }
     }
 
@@ -2535,6 +2535,7 @@ static void ProcessLayout(pugi::xml_node layout_tag, t_arch* arch, const pugiuti
     //expect_only_attributes(layout_tag, {}, loc_data);
 
     arch->tileable = get_attribute(layout_tag, "tileable", loc_data, ReqOpt::OPTIONAL).as_bool(false);
+    arch->perimeter_cb = get_attribute(layout_tag, "perimeter_cb", loc_data, ReqOpt::OPTIONAL).as_bool(false);
     arch->shrink_boundary = get_attribute(layout_tag, "shrink_boundary", loc_data, ReqOpt::OPTIONAL).as_bool(false);
     arch->through_channel = get_attribute(layout_tag, "through_channel", loc_data, ReqOpt::OPTIONAL).as_bool(false);
     arch->opin2all_sides = get_attribute(layout_tag, "opin2all_sides", loc_data, ReqOpt::OPTIONAL).as_bool(false);
@@ -2939,7 +2940,7 @@ static void ProcessDevice(pugi::xml_node Node, t_arch* arch, t_default_fc_spec&
     //<connection_block> tag
     Cur = get_single_child(Node, "connection_block", loc_data);
     expect_only_attributes(Cur, {"input_switch_name", "input_inter_die_switch_name"}, loc_data);
-    arch->ipin_cblock_switch_name.push_back(get_attribute(Cur, "input_switch_name", loc_data).as_string());
+    arch->ipin_cblock_switch_name.emplace_back(get_attribute(Cur, "input_switch_name", loc_data).as_string());
     std::string inter_die_conn = get_attribute(Cur, "input_inter_die_switch_name", loc_data, ReqOpt::OPTIONAL).as_string("");
     if (inter_die_conn != "") {
         arch->ipin_cblock_switch_name.push_back(inter_die_conn);
@@ -3359,7 +3360,7 @@ static void ProcessEquivalentSiteCustomConnection(pugi::xml_node Parent,
                                                   t_sub_tile* SubTile,
                                                   t_physical_tile_type* PhysicalTileType,
                                                   t_logical_block_type* LogicalBlockType,
-                                                  std::string site_name,
+                                                  const std::string& site_name,
                                                   const pugiutil::loc_data& loc_data) {
     pugi::xml_node CurDirect;
 
@@ -3542,7 +3543,7 @@ static void ProcessPinLocations(pugi::xml_node Locations,
                 for (int h = 0; h < PhysicalTileType->height; ++h) {
                     for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) {
                         for (const auto& token : pin_locs->assignments[sub_tile_index][w][h][l][side]) {
-                            InstPort inst_port(token.c_str());
+                            InstPort inst_port(token);
 
                             //A pin specification should contain only the block name, and not any instance count information
                             //A pin specification may contain instance count, but should be in the range of capacity
@@ -3909,8 +3910,8 @@ static void ProcessSegments(pugi::xml_node Parent,
 
         if (!Segs[i].longline) {
             //Long line doesn't accpet <sb> or <cb> since it assumes full population
-            expected_subtags.push_back("sb");
-            expected_subtags.push_back("cb");
+            expected_subtags.emplace_back("sb");
+            expected_subtags.emplace_back("cb");
         }
 
         /* Get the type */
@@ -3919,16 +3920,16 @@ static void ProcessSegments(pugi::xml_node Parent,
             Segs[i].directionality = BI_DIRECTIONAL;
 
             //Bidir requires the following tags
-            expected_subtags.push_back("wire_switch");
-            expected_subtags.push_back("opin_switch");
+            expected_subtags.emplace_back("wire_switch");
+            expected_subtags.emplace_back("opin_switch");
         }
 
         else if (0 == strcmp(tmp, "unidir")) {
             Segs[i].directionality = UNI_DIRECTIONAL;
 
             //Unidir requires the following tags
-            expected_subtags.push_back("mux");
-            expected_subtags.push_back("mux_inter_die");
+            expected_subtags.emplace_back("mux");
+            expected_subtags.emplace_back("mux_inter_die");
         }
 
         else {
@@ -4114,8 +4115,6 @@ static void ProcessSwitchblocks(pugi::xml_node Parent, t_arch* arch, const pugiu
 
         Node = Node.next_sibling(Node.name());
     }
-
-    return;
 }
 
 static void ProcessCB_SB(pugi::xml_node Node, std::vector<bool>& list, const pugiutil::loc_data& loc_data) {
@@ -4876,7 +4875,7 @@ static int find_switch_by_name(const t_arch& arch, const std::string& switch_nam
     return OPEN;
 }
 
-e_side string_to_side(const std::string& side_str) {
+static e_side string_to_side(const std::string& side_str) {
     e_side side = NUM_SIDES;
     if (side_str.empty()) {
         side = NUM_SIDES;
@@ -4905,4 +4904,4 @@ static T* get_type_by_name(const char* type_name, std::vector<T>& types) {
 
     archfpga_throw(__FILE__, __LINE__,
                    "Could not find type: %s\n", type_name);
-}
+}

libs/librrgraph/src/base/check_rr_graph.cpp

@@ -412,7 +412,7 @@ void check_rr_node(const RRGraphView& rr_graph,
             break;
 
         case CHANX:
-            if (xlow < 1 || xhigh > int(grid.width()) - 2 || yhigh > int(grid.height()) - 2 || yhigh != ylow) {
+            if (xhigh > int(grid.width()) - 1 || yhigh > int(grid.height()) - 2 || yhigh != ylow) {
                 VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
                                 "in check_rr_node: CHANX out of range for endpoints (%d,%d) and (%d,%d)\n", xlow, ylow, xhigh, yhigh);
             }
@@ -423,7 +423,7 @@ void check_rr_node(const RRGraphView& rr_graph,
             break;
 
         case CHANY:
-            if (xhigh > int(grid.width()) - 2 || ylow < 1 || yhigh > int(grid.height()) - 2 || xlow != xhigh) {
+            if (xhigh > int(grid.width()) - 2 || yhigh > int(grid.height()) - 1 || xlow != xhigh) {
                 VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
                                 "Error in check_rr_node: CHANY out of range for endpoints (%d,%d) and (%d,%d)\n", xlow, ylow, xhigh, yhigh);
             }

utils/route_diag/src/main.cpp

@@ -103,9 +103,9 @@ static void do_one_route(const Netlist<>& net_list,
                                                   segment_inf,
                                                   is_flat);
 
-    ConnectionRouter<BinaryHeap> router(
-            device_ctx.grid,
-            *router_lookahead,
+    ConnectionRouter<FourAryHeap> router(
+        device_ctx.grid,
+        *router_lookahead,
             device_ctx.rr_graph.rr_nodes(),
             &device_ctx.rr_graph,
             device_ctx.rr_rc_data,

vpr/src/base/SetupVPR.cpp

@@ -423,6 +423,7 @@ static void SetupRoutingArch(const t_arch& Arch,
 
     /* Copy the tileable routing setting */
     RoutingArch->tileable = Arch.tileable;
+    RoutingArch->perimeter_cb = Arch.perimeter_cb;
     RoutingArch->shrink_boundary = Arch.shrink_boundary;
     RoutingArch->through_channel = Arch.through_channel;
     RoutingArch->opin2all_sides = Arch.opin2all_sides;