Skip to content

Commit 0cc966d

Browse files
vaughnbetzvaughnbetz
authored
Merge pull request #2687 from verilog-to-routing/rr_graph_seg_length
[RR Graph] Add length attribute to segment tag
2 parents 75210e1 + c768992 commit 0cc966d

File tree

7 files changed

+65
-21
lines changed

7 files changed

+65
-21
lines changed

‎libs/librrgraph/src/io/gen/README.gen.md

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,4 +2,4 @@
22
`rr_graph_uxsdcxx_interface.h` are generated via uxsdcxx and are checked in to
33
avoid requiring python3 and the uxsdcxx depedencies to build VPR.
44

5-
See `vpr/src/route/gen/SCHEMA_GENERATOR.md` for details.
5+
See `$VTR_DIR/libs/librrgraph/src/base/SCHEMA_GENERATOR.md` for details.

‎libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h

Lines changed: 33 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -4,9 +4,9 @@
44
* https://github.com/duck2/uxsdcxx
55
* Modify only if your build process doesn't involve regenerating this file.
66
*
7-
* Cmdline: /home/talaeikh/uxsdcxx/uxsdcxx.py /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
8-
* Input file: /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
9-
* md5sum of input file: 9c14a0ddd3c6bc1e690ca6abf467bae6
7+
* Cmdline: uxsdcxx/uxsdcxx.py /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
8+
* Input file: /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
9+
* md5sum of input file: 65eddcc840064bbb91d7f4cf0b8bf821
1010
*/
1111

1212
#include <functional>
@@ -247,8 +247,8 @@ constexpr const char *atok_lookup_t_segment_timing[] = {"C_per_meter", "R_per_me
247247

248248
enum class gtok_t_segment {TIMING};
249249
constexpr const char *gtok_lookup_t_segment[] = {"timing"};
250-
enum class atok_t_segment {ID, NAME, RES_TYPE};
251-
constexpr const char *atok_lookup_t_segment[] = {"id", "name", "res_type"};
250+
enum class atok_t_segment {ID, LENGTH, NAME, RES_TYPE};
251+
constexpr const char *atok_lookup_t_segment[] = {"id", "length", "name", "res_type"};
252252

253253
enum class gtok_t_segments {SEGMENT};
254254
constexpr const char *gtok_lookup_t_segments[] = {"segment"};
@@ -792,6 +792,24 @@ inline atok_t_segment lex_attr_t_segment(const char *in, const std::function<voi
792792
default: break;
793793
}
794794
break;
795+
case 6:
796+
switch(*((triehash_uu32*)&in[0])){
797+
case onechar('l', 0, 32) | onechar('e', 8, 32) | onechar('n', 16, 32) | onechar('g', 24, 32):
798+
switch(in[4]){
799+
case onechar('t', 0, 8):
800+
switch(in[5]){
801+
case onechar('h', 0, 8):
802+
return atok_t_segment::LENGTH;
803+
break;
804+
default: break;
805+
}
806+
break;
807+
default: break;
808+
}
809+
break;
810+
default: break;
811+
}
812+
break;
795813
case 8:
796814
switch(*((triehash_uu64*)&in[0])){
797815
case onechar('r', 0, 64) | onechar('e', 8, 64) | onechar('s', 16, 64) | onechar('_', 24, 64) | onechar('t', 32, 64) | onechar('y', 40, 64) | onechar('p', 48, 64) | onechar('e', 56, 64):
@@ -2325,7 +2343,7 @@ inline void load_switch_required_attributes(const pugi::xml_node &root, int * id
23252343
}
23262344

23272345
inline void load_segment_required_attributes(const pugi::xml_node &root, int * id, const std::function<void(const char *)> * report_error){
2328-
std::bitset<3> astate = 0;
2346+
std::bitset<4> astate = 0;
23292347
for(pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()){
23302348
atok_t_segment in = lex_attr_t_segment(attr.name(), report_error);
23312349
if(astate[(int)in] == 0) astate[(int)in] = 1;
@@ -2334,6 +2352,9 @@ inline void load_segment_required_attributes(const pugi::xml_node &root, int * i
23342352
case atok_t_segment::ID:
23352353
*id = load_int(attr.value(), report_error);
23362354
break;
2355+
case atok_t_segment::LENGTH:
2356+
/* Attribute length set after element init */
2357+
break;
23372358
case atok_t_segment::NAME:
23382359
/* Attribute name set after element init */
23392360
break;
@@ -2343,7 +2364,7 @@ inline void load_segment_required_attributes(const pugi::xml_node &root, int * i
23432364
default: break; /* Not possible. */
23442365
}
23452366
}
2346-
std::bitset<3> test_astate = astate | std::bitset<3>(0b100);
2367+
std::bitset<4> test_astate = astate | std::bitset<4>(0b1010);
23472368
if(!test_astate.all()) attr_error(test_astate, atok_lookup_t_segment, report_error);
23482369
}
23492370

@@ -2936,6 +2957,9 @@ inline void load_segment(const pugi::xml_node &root, T &out, Context &context, c
29362957
case atok_t_segment::ID:
29372958
/* Attribute id is already set */
29382959
break;
2960+
case atok_t_segment::LENGTH:
2961+
out.set_segment_length(load_int(attr.value(), report_error), context);
2962+
break;
29392963
case atok_t_segment::NAME:
29402964
out.set_segment_name(attr.value(), context);
29412965
break;
@@ -4006,6 +4030,8 @@ inline void write_segments(T &in, std::ostream &os, Context &context){
40064030
auto child_context = in.get_segments_segment(i, context);
40074031
os << "<segment";
40084032
os << " id=\"" << in.get_segment_id(child_context) << "\"";
4033+
if((bool)in.get_segment_length(child_context))
4034+
os << " length=\"" << in.get_segment_length(child_context) << "\"";
40094035
os << " name=\"" << in.get_segment_name(child_context) << "\"";
40104036
if((bool)in.get_segment_res_type(child_context))
40114037
os << " res_type=\"" << lookup_segment_res_type[(int)in.get_segment_res_type(child_context)] << "\"";

‎libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,9 +4,9 @@
44
* https://github.com/duck2/uxsdcxx
55
* Modify only if your build process doesn't involve regenerating this file.
66
*
7-
* Cmdline: /home/talaeikh/uxsdcxx/uxsdcap.py /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
8-
* Input file: /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
9-
* md5sum of input file: 9c14a0ddd3c6bc1e690ca6abf467bae6
7+
* Cmdline: uxsdcxx/uxsdcap.py /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
8+
* Input file: /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
9+
* md5sum of input file: 65eddcc840064bbb91d7f4cf0b8bf821
1010
*/
1111

1212
#include <functional>
@@ -601,6 +601,7 @@ inline void load_segment_capnp_type(const ucap::Segment::Reader &root, T &out, C
601601
(void)report_error;
602602
(void)stack;
603603

604+
out.set_segment_length(root.getLength(), context);
604605
out.set_segment_name(root.getName().cStr(), context);
605606
out.set_segment_res_type(conv_enum_segment_res_type(root.getResType(), report_error), context);
606607
stack->push_back(std::make_pair("getTiming", 0));
@@ -1101,6 +1102,8 @@ inline void write_segments_capnp_type(T &in, ucap::Segments::Builder &root, Cont
11011102
auto segments_segment = segments_segments[i];
11021103
auto child_context = in.get_segments_segment(i, context);
11031104
segments_segment.setId(in.get_segment_id(child_context));
1105+
if((bool)in.get_segment_length(child_context))
1106+
segments_segment.setLength(in.get_segment_length(child_context));
11041107
segments_segment.setName(in.get_segment_name(child_context));
11051108
if((bool)in.get_segment_res_type(child_context))
11061109
segments_segment.setResType(conv_to_enum_segment_res_type(in.get_segment_res_type(child_context)));

‎libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,9 +4,9 @@
44
* https://github.com/duck2/uxsdcxx
55
* Modify only if your build process doesn't involve regenerating this file.
66
*
7-
* Cmdline: /home/talaeikh/uxsdcxx/uxsdcxx.py /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
8-
* Input file: /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
9-
* md5sum of input file: 9c14a0ddd3c6bc1e690ca6abf467bae6
7+
* Cmdline: uxsdcxx/uxsdcxx.py /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
8+
* Input file: /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
9+
* md5sum of input file: 65eddcc840064bbb91d7f4cf0b8bf821
1010
*/
1111

1212
#include <functional>
@@ -245,11 +245,14 @@ class RrGraphBase {
245245
* <xs:element minOccurs="0" name="timing" type="segment_timing" />
246246
* </xs:all>
247247
* <xs:attribute name="id" type="xs:int" use="required" />
248+
* <xs:attribute name="length" type="xs:int" />
248249
* <xs:attribute name="name" type="xs:string" use="required" />
249250
* <xs:attribute name="res_type" type="segment_res_type" />
250251
* </xs:complexType>
251252
*/
252253
virtual inline int get_segment_id(typename ContextTypes::SegmentReadContext &ctx) = 0;
254+
virtual inline int get_segment_length(typename ContextTypes::SegmentReadContext &ctx) = 0;
255+
virtual inline void set_segment_length(int length, typename ContextTypes::SegmentWriteContext &ctx) = 0;
253256
virtual inline const char * get_segment_name(typename ContextTypes::SegmentReadContext &ctx) = 0;
254257
virtual inline void set_segment_name(const char * name, typename ContextTypes::SegmentWriteContext &ctx) = 0;
255258
virtual inline enum_segment_res_type get_segment_res_type(typename ContextTypes::SegmentReadContext &ctx) = 0;

‎libs/librrgraph/src/io/rr_graph.xsd

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -155,6 +155,7 @@
155155
<xs:element name="timing" type="segment_timing" minOccurs="0"/>
156156
</xs:all>
157157
<xs:attribute name="id" type="xs:int" use="required"/>
158+
<xs:attribute name="length" type="xs:int"/>
158159
<xs:attribute name="name" type="xs:string" use="required"/>
159160
<xs:attribute name="res_type" type="segment_res_type"/>
160161
</xs:complexType>

‎libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1347,13 +1347,23 @@ class RrGraphSerializer final : public uxsd::RrGraphBase<RrGraphContextTypes> {
13471347
inline const char* get_segment_name(const t_segment_inf*& segment) final {
13481348
return segment->name.c_str();
13491349
}
1350+
inline int get_segment_length(const t_segment_inf*& segment) final {
1351+
return segment->length;
1352+
}
13501353
inline void set_segment_name(const char* name, const t_segment_inf*& segment) final {
13511354
if (segment->name != name) {
13521355
report_error(
13531356
"Architecture file does not match RR graph's segment name: arch uses %s, RR graph uses %s",
13541357
segment->name.c_str(), name);
13551358
}
13561359
}
1360+
inline void set_segment_length(int length, const t_segment_inf*& segment) final {
1361+
if (segment->length != length) {
1362+
report_error(
1363+
"Architecture file does not match RR graph's length: arch uses %d, RR graph uses %d",
1364+
segment->length, length);
1365+
}
1366+
}
13571367
inline uxsd::enum_segment_res_type get_segment_res_type(const t_segment_inf*& segment) final {
13581368
return to_uxsd_segment_res_type(segment->res_type);
13591369
}

‎libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2,11 +2,11 @@
22
# https://github.com/duck2/uxsdcxx
33
# Modify only if your build process doesn't involve regenerating this file.
44
#
5-
# Cmdline: /home/talaeikh/uxsdcxx/uxsdcap.py /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
6-
# Input file: /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
7-
# md5sum of input file: 9c14a0ddd3c6bc1e690ca6abf467bae6
5+
# Cmdline: uxsdcxx/uxsdcap.py /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
6+
# Input file: /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
7+
# md5sum of input file: 65eddcc840064bbb91d7f4cf0b8bf821
88

9-
@0xa136dd28cdc8783b;
9+
@0xe787bf7696810419;
1010
using Cxx = import "/capnp/c++.capnp";
1111
$Cxx.namespace("ucap");
1212

@@ -129,9 +129,10 @@ struct SegmentTiming {
129129

130130
struct Segment {
131131
id @0 :Int32;
132-
name @1 :Text;
133-
resType @2 :SegmentResType;
134-
timing @3 :SegmentTiming;
132+
length @1 :Int32;
133+
name @2 :Text;
134+
resType @3 :SegmentResType;
135+
timing @4 :SegmentTiming;
135136
}
136137

137138
struct Segments {

0 commit comments

Comments
 (0)