Merge remote-tracking branch 'origin/master' into temp_net_cost_ref

Author: soheilshahrouz

CMakeLists.txt

@@ -130,11 +130,6 @@ endif()
 # Build type flags
 #
 
-set(EXTRA_FLAGS "")
-if(VPR_ENABLE_INTERCHANGE)
-    set(EXTRA_FLAGS "-lz")
-endif()
-
 if(NOT MSVC)
     # for GCC and Clang
     set(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -O0 -g3")
@@ -298,6 +293,7 @@ endif()
 #
 # Increased debugging vebosity
 #
+set(EXTRA_FLAGS "")
 if(VTR_ENABLE_VERBOSE)
     set(EXTRA_FLAGS "${EXTRA_FLAGS} -DVTR_ENABLE_DEBUG_LOGGING")
     message(STATUS "Enabling increased debugging verbosity")

doc/src/arch/index.rst

@@ -4,7 +4,7 @@ FPGA Architecture Description
 =============================
 
 VTR uses an XML-based architecture description language to describe the targeted FPGA architecture.
-This flexible description langauge allows the user to describe a large number of hypothetical and commercial-like FPGA architectures.
+This flexible description language allows the user to describe a large number of hypothetical and commercial-like FPGA architectures.
 
 See the :ref:`arch_tutorial` for an introduction to the architecture description langauge.
 For a detailed reference on the supported options see the :ref:`arch_reference`.

doc/src/arch/reference.rst

@@ -2036,6 +2036,12 @@ The ``<segment>`` tag and its contents are described below.
 
     Tag must be included and ``name`` must be the same as the name you give in ``<switch type="mux" name="...``
 
+.. arch:tag:: <mux_inter_die name="string"/>
+
+    :req_param name: Name of the mux switch type used to drive this segment type when the driver (block outputs and other wires) is located on a different die than the segment. This information is utilized during rr-graph construction.
+
+    Tag must be included and ``name`` must be the same as the name you give in ``<switch type="mux" name="...``
+
 .. arch:tag:: <wire_switch name="string"/>
 
     :req_param name: Name of the switch type used by other wires to drive this type of segment by default. This information is used during rr-graph construction, and a custom switch block can override this switch type for specific connections if desired.

doc/src/quickstart/index.rst

@@ -2,22 +2,22 @@
 VTR Quick Start
 ###############
 
-This is a quick introduction to VTR which covers how to run VTR and some if its associated tools (:ref:`VPR`, :ref:`odin_ii`, :ref:`ABC`).
+This is a quick introduction to VTR which covers how to run VTR and some of its associated tools (:ref:`VPR`, :ref:`odin_ii`, :ref:`ABC`).
 
 Setting Up VTR
 ==============
 
 Download VTR
 ------------
 
-The first step is to `download VTR <https://verilogtorouting.org/download/>`_ and extract VTR on your local machine.
+The first step is to `download VTR <https://verilogtorouting.org/download/>`_ and extract it on your local machine.
 
 .. note:: Developers planning to modify VTR should clone the `VTR git repository <https://github.com/verilog-to-routing/vtr-verilog-to-routing/>`_.
 
 
 Environment Setup
 -----------------
-If you cloned the repository you will need to set up the git submodules (if you downloaded and extracted a release, you can skip this step):
+If you cloned the repository, you will need to set up the git submodules (if you downloaded and extracted a release, you can skip this step):
 
 .. code-block:: bash
 
@@ -77,12 +77,12 @@ For more details on building VTR on various operating systems/platforms see :doc
 Running VPR
 ===========
 
-Lets now try taking a simple pre-synthesized circuit (consisting of LUTs and Flip-Flops) and use the VPR tool to implement it on a specific FPGA architecture.
+Let's now try taking a simple pre-synthesized circuit (consisting of LUTs and Flip-Flops) and use the VPR tool to implement it on a specific FPGA architecture.
 
 Running VPR on a Pre-Synthesized Circuit
 ----------------------------------------
 
-First, lets make a directory in our home directory where we can work:
+First, let's make a directory in our home directory where we can work:
 
 .. code-block:: bash
 
@@ -211,13 +211,13 @@ Running the VTR Flow
 In the previous section we have implemented a pre-synthesized circuit onto a pre-existing FPGA architecture using VPR, and visualized the result.
 We now turn to how we can implement *our own circuit* on a pre-existing FPGA architecture.
 
-To do this we begin by describing a circuit behaviourly using the Verilog Hardware Description Language (HDL).
+To do this, we begin by describing a circuit behaviourally using the Verilog Hardware Description Language (HDL).
 This allows us to quickly and consisely define the circuit's behaviour.
 We will then use the VTR Flow to synthesize the behavioural Verilog description it into a circuit netlist, and implement it onto an FPGA.
 
 Example Circuit
 ---------------
-We will use the following simple example circuit, which causes it's output to toggle on and off:
+We will use the following simple example circuit, which causes its output to toggle on and off:
 
 .. literalinclude:: blink.v
     :language: verilog
@@ -230,7 +230,7 @@ If the count is below ``16`` it drives the output (``o_led``) high, otherwise it
 
 Manually Running the VTR Flow
 -----------------------------
-Lets start by making a fresh directory for us to work in:
+Let's start by making a fresh directory for us to work in:
 
 .. code-block:: bash
 
@@ -241,15 +241,15 @@ Next we need to run the three main sets of tools:
 
 * :ref:`odin_ii` performs 'synthesis' which converts our behavioural Verilog (``.v`` file) into a circuit netlist (``.blif`` file) consisting of logic equations and FPGA architecture primitives (Flip-Flops, adders etc.),
 * :ref:`ABC` performs 'logic optimization' which simplifies the circuit logic, and 'technology mapping' which converts logic equations into the Look-Up-Tables (LUTs) available on an FPGA, and
-* :ref:`VPR` which performs packing, placement and routing of the circuit to implement it on the targetted FPGA architecture.
+* :ref:`VPR` which performs packing, placement and routing of the circuit to implement it on the targeted FPGA architecture.
 
 .. _synthesizing_with_odin_ii:
 Synthesizing with ODIN II
 ~~~~~~~~~~~~~~~~~~~~~~~~~
 
 First we'll run ODIN II on our Verilog file to synthesize it into a circuit netlist, providing the options:
 
- * ``-a $VTR_ROOT/vtr_flow/arch/timing/EArch.xml`` which specifies what FPGA architecture we are targetting,
+ * ``-a $VTR_ROOT/vtr_flow/arch/timing/EArch.xml`` which specifies what FPGA architecture we are targeting,
  * ``-V $VTR_ROOT/doc/src/quickstart/blink.v`` which specifies the verilog file we want to synthesize, and
  * ``-o blink.odin.blif`` which specifies the name of the generated ``.blif`` circuit netlist.
 
@@ -400,7 +400,7 @@ Automatically Running the VTR Flow
 Running each stage of the flow manually is time consuming (and potentially error prone).
 For convenience, VTR provides a script (:ref:`run_vtr_flow`) which automates this process.
 
-First, make sure you sure you have activated the Python virtual environment created at the beginning of this tutorial:
+First, make sure you have activated the Python virtual environment created at the beginning of this tutorial:
 
 .. code-block:: bash
 

doc/src/vpr/file_formats.rst

@@ -623,7 +623,11 @@ All the following lines have the format::
 
     block_name    x        y   subtile_number
 
-The ``block_name`` is the name of this block, as given in the input .net formatted netlist.
+The ``block_name`` can refer to either:
+
+- The name of a clustered block, as given in the input .net formatted netlist.
+- The name of a primitive within a clustered block.
+
 ``x`` and ``y`` are the row and column in which the block is placed, respectively.
 
 .. note:: The blocks in a placement file can be listed in any order.

doc/src/vpr/vpr_constraints.rst

@@ -2,9 +2,7 @@ VPR Constraints
 =========================
 .. _vpr_constraints:
 
-VPR allows users to run the flow with placement constraints that enable primitives to be locked down to a specific region on the chip and global routing constraints that facilitate the routing of global nets through clock networks.
-
-Users can specify these constraints through a constraints file in XML format, as shown in the format below.
+Users can specify placement and/or global routing constraints on all or part of a design through a constraints file in XML format, as shown in the format below. These constraints are optional and allow detailed control of the region on the chip in which parts of the design are placed, and of the routing of global nets through dedicated (usually clock) networks. 
 
 .. code-block:: xml
    :caption: The overall format of a VPR constraints file

libs/EXTERNAL/libtatum/libtatum/tatum/tags/TimingTags.hpp

@@ -113,6 +113,7 @@ class TimingTags {
                 using value_type = T;
                 using pointer = T*;
                 using reference = T&;
+                using const_reference = const T&;
 
                 Iterator(): p_(nullptr) {}
                 Iterator(pointer p): p_(p) {}
@@ -123,7 +124,7 @@ class TimingTags {
                 friend bool operator!=(Iterator a, Iterator b) { return a.p_ != b.p_; }
 
                 reference operator*() { return *p_; }
-                const reference operator*() const { return *p_; } //Required for MSVC (gcc/clang are fine with only the non-cost version)
+                const_reference operator*() const { return *p_; } //Required for MSVC (gcc/clang are fine with only the non-cost version)
                 pointer operator->() { return p_; }
                 reference operator[](size_t n) { return *(p_ + n); }
 

libs/libvqm/vqm_common.c

@@ -559,7 +559,7 @@ void add_node(char* type, char *name, t_array_ref **ports, t_parse_info* parse_i
 				new_assoc->associated_net = net;
 				new_assoc->port_index = counter;
 				new_assoc->port_name = (char *) malloc(strlen(association->port_name)+1);
-				strcpy(new_assoc->port_name, (char*)malloc(strlen(association->port_name)));
+				strcpy(new_assoc->port_name, association->port_name);
 				new_assoc->wire_index = wire_index;
 				wire_index += change;
 				m_ports->array_size = insert_element_at_index((intptr_t) new_assoc, m_ports, counter);

vpr/CMakeLists.txt

@@ -109,21 +109,22 @@ endif ()
 set_target_properties(libvpr PROPERTIES PREFIX "") #Avoid extra 'lib' prefix
 
 #Specify link-time dependencies
+find_package(ZLIB)
 target_link_libraries(libvpr
-                        libvtrutil
-                        libarchfpga
-                        libsdcparse
-                        libblifparse
-                        libtatum
-                        libargparse
-                        libpugixml
-                        librrgraph
+                      libvtrutil
+                      libarchfpga
+                      libsdcparse
+                      libblifparse
+                      libtatum
+                      libargparse
+                      libpugixml
+                      librrgraph
+                      ZLIB::ZLIB
 )
 
 if(VPR_USE_SERVER)
     target_link_libraries(libvpr
                           sockpp-static
-                          -lz
     )
 endif()
 

vpr/src/base/ShowSetup.h

@@ -1,6 +1,13 @@
 #ifndef SHOWSETUP_H
 #define SHOWSETUP_H
 
+#include <ostream>
+#include <string>
+#include <vector>
+
+class t_logical_block_type;
+class t_vpr_setup;
+
 struct ClusteredNetlistStats {
   private:
     void writeHuman(std::ostream& output) const;

vpr/src/base/blk_loc_registry.cpp

@@ -0,0 +1,114 @@
+
+#include "blk_loc_registry.h"
+#include "globals.h"
+
+const vtr::vector_map<ClusterBlockId, t_block_loc>& BlkLocRegistry::block_locs() const {
+    return  block_locs_;
+}
+
+vtr::vector_map<ClusterBlockId, t_block_loc>& BlkLocRegistry::mutable_block_locs() {
+    return  block_locs_;
+}
+
+const GridBlock& BlkLocRegistry::grid_blocks() const {
+    return grid_blocks_;
+}
+
+GridBlock& BlkLocRegistry::mutable_grid_blocks() {
+    return grid_blocks_;
+}
+
+const vtr::vector_map<ClusterPinId, int>& BlkLocRegistry::physical_pins() const {
+    return physical_pins_;
+}
+
+vtr::vector_map<ClusterPinId, int>& BlkLocRegistry::mutable_physical_pins() {
+    return physical_pins_;
+}
+
+int BlkLocRegistry::tile_pin_index(const ClusterPinId pin) const {
+    return physical_pins_[pin];
+}
+
+int BlkLocRegistry::net_pin_to_tile_pin_index(const ClusterNetId net_id, int net_pin_index) const {
+    auto& cluster_ctx = g_vpr_ctx.clustering();
+
+    // Get the logical pin index of pin within its logical block type
+    ClusterPinId pin_id = cluster_ctx.clb_nlist.net_pin(net_id, net_pin_index);
+
+    return this->tile_pin_index(pin_id);
+}
+
+void BlkLocRegistry::set_block_location(ClusterBlockId blk_id, const t_pl_loc& location) {
+    auto& device_ctx = g_vpr_ctx.device();
+    auto& cluster_ctx = g_vpr_ctx.clustering();
+
+    const std::string& block_name = cluster_ctx.clb_nlist.block_name(blk_id);
+
+    //Check if block location is out of range of grid dimensions
+    if (location.x < 0 || location.x > int(device_ctx.grid.width() - 1)
+        || location.y < 0 || location.y > int(device_ctx.grid.height() - 1)) {
+        VPR_THROW(VPR_ERROR_PLACE, "Block %s with ID %d is out of range at location (%d, %d). \n",
+                  block_name.c_str(), blk_id, location.x, location.y);
+    }
+
+    //Set the location of the block
+    block_locs_[blk_id].loc = location;
+
+    //Check if block is at an illegal location
+    auto physical_tile = device_ctx.grid.get_physical_type({location.x, location.y, location.layer});
+    auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id);
+
+    if (location.sub_tile >= physical_tile->capacity || location.sub_tile < 0) {
+        VPR_THROW(VPR_ERROR_PLACE, "Block %s subtile number (%d) is out of range. \n", block_name.c_str(), location.sub_tile);
+    }
+
+    if (!is_sub_tile_compatible(physical_tile, logical_block, block_locs_[blk_id].loc.sub_tile)) {
+        VPR_THROW(VPR_ERROR_PLACE, "Attempt to place block %s with ID %d at illegal location (%d,%d,%d). \n",
+                  block_name.c_str(),
+                  blk_id,
+                  location.x,
+                  location.y,
+                  location.layer);
+    }
+
+    //Mark the grid location and usage of the block
+    grid_blocks_.set_block_at_location(location, blk_id);
+    grid_blocks_.increment_usage({location.x, location.y, location.layer});
+
+    place_sync_external_block_connections(blk_id);
+}
+
+void BlkLocRegistry::place_sync_external_block_connections(ClusterBlockId iblk) {
+    const auto& cluster_ctx = g_vpr_ctx.clustering();
+    const auto& clb_nlist = cluster_ctx.clb_nlist;
+
+    t_pl_loc block_loc = block_locs_[iblk].loc;
+
+    auto physical_tile = physical_tile_type(block_loc);
+    auto logical_block = clb_nlist.block_type(iblk);
+
+    int sub_tile_index = get_sub_tile_index(iblk, block_locs_);
+    auto sub_tile = physical_tile->sub_tiles[sub_tile_index];
+
+    VTR_ASSERT(sub_tile.num_phy_pins % sub_tile.capacity.total() == 0);
+
+    int max_num_block_pins = sub_tile.num_phy_pins / sub_tile.capacity.total();
+    /* Logical location and physical location is offset by z * max_num_block_pins */
+
+    int rel_capacity = block_loc.sub_tile - sub_tile.capacity.low;
+
+    for (ClusterPinId pin : clb_nlist.block_pins(iblk)) {
+        int logical_pin_index = clb_nlist.pin_logical_index(pin);
+        int sub_tile_pin_index = get_sub_tile_physical_pin(sub_tile_index, physical_tile, logical_block, logical_pin_index);
+
+        int new_physical_pin_index = sub_tile.sub_tile_to_tile_pin_indices[sub_tile_pin_index + rel_capacity * max_num_block_pins];
+
+        auto result = physical_pins_.find(pin);
+        if (result != physical_pins_.end()) {
+            physical_pins_[pin] = new_physical_pin_index;
+        } else {
+            physical_pins_.insert(pin, new_physical_pin_index);
+        }
+    }
+}