update min_chan_width_routing_area_total and min_chan_width_routing_area_per_tile for regression_tests/vtr_reg_strong_odin/strong_fix_pins_random

Author: soheilshahrouz

vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt

@@ -1,2 +1,2 @@
  arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
- k6_N10_mem32K_40nm.xml	  stereovision3.v	  common	  4.02	  vpr	  61.07 MiB	  	  0.13	  10072	  -1	  -1	  4	  0.16	  -1	  -1	  33252	  -1	  -1	  19	  11	  0	  0	  success	  v8.0.0-6793-gb52911b9f	  release IPO VTR_ASSERT_LEVEL=2	  GNU 7.5.0 on Linux-4.15.0-167-generic x86_64	  2022-11-27T15:52:14	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing	  62540	  11	  30	  262	  292	  2	  104	  60	  7	  7	  49	  clb	  auto	  22.4 MiB	  0.17	  491	  61.1 MiB	  0.14	  0.00	  2.22129	  -174.848	  -2.22129	  2.12256	  0.08	  0.000609229	  0.000514776	  0.0130362	  0.0113054	  30	  570	  24	  1.07788e+06	  1.02399e+06	  58936.16	  1202.776	  1.53	  0.218794	  0.187902	  537	  22	  693	  1872	  55819	  14529	  2.35993	  2.22897	  -183.816	  -2.35993	  0	  0	  90369.8	  1844.28	  0.02	  0.10	  0.0321781	  0.0283564
+ k6_N10_mem32K_40nm.xml	  stereovision3.v	  common	  4.02	  vpr	  61.07 MiB	  	  0.13	  10072	  -1	  -1	  4	  0.16	  -1	  -1	  33252	  -1	  -1	  19	  11	  0	  0	  success	  v8.0.0-6793-gb52911b9f	  release IPO VTR_ASSERT_LEVEL=2	  GNU 7.5.0 on Linux-4.15.0-167-generic x86_64	  2022-11-27T15:52:14	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing	  62540	  11	  30	  262	  292	  2	  104	  60	  7	  7	  49	  clb	  auto	  22.4 MiB	  0.17	  491	  61.1 MiB	  0.14	  0.00	  2.22129	  -174.848	  -2.22129	  2.12256	  0.08	  0.000609229	  0.000514776	  0.0130362	  0.0113054	  30	  570	  24	  1.07788e+06	  1.02399e+06	  77018.1	  1571.80	  1.53	  0.218794	  0.187902	  537	  22	  693	  1872	  55819	  14529	  2.35993	  2.22897	  -183.816	  -2.35993	  0	  0	  90369.8	  1844.28	  0.02	  0.10	  0.0321781	  0.0283564