Merge branch 'master' into ipa_it2_clean

Author: w0lek

doc/src/vpr/basic_flow.rst

@@ -4,7 +4,7 @@ Basic flow
 The Place and Route process in VPR consists of several steps:
 
 - Packing (combinines primitives into complex blocks)
-- Placment (places complex blocks within the FPGA grid)
+- Placement (places complex blocks within the FPGA grid)
 - Routing (determines interconnections between blocks)
 - Analysis (analyzes the implementation)
 

doc/src/vpr/command_line_usage.rst

@@ -1299,6 +1299,7 @@ The following options are only valid when the router is in timing-driven mode (t
     **Default:** ``1.2``
 
 .. option:: --router_profiler_astar_fac <float>
+    
     Controls the directedness of the timing-driven router's exploration when doing router delay profiling of an architecture.
     The router delay profiling step is currently used to calculate the place delay matrix lookup.
     Values between 1 and 2 are resonable; higher values trade some quality for reduced run-time.

odin_ii/src/verilog/verilog_bison.y

@@ -52,6 +52,7 @@ int yylex(void);
 %define parse.error verbose
 
 %locations
+%expect 2
 
 %union{
 	char *id_name;
@@ -208,6 +209,8 @@ int yylex(void);
 %type <node> list_of_generate_block_items generate_item generate_block_item generate loop_generate_construct if_generate_construct 
 %type <node> case_generate_construct case_generate_item_list case_generate_items generate_block generate_localparam_declaration generate_defparam_declaration
 
+
+
 /* capture wether an operation is signed or not */
 %type <op> var_signedness