Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into flat_routing

amin1377 · amin1377 · commit 02ad280948ee · 2022-08-29T09:30:52.000-04:00
diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp
@@ -3444,7 +3444,11 @@ static int get_opin_direct_connections(RRGraphBuilder& rr_graph_builder,
                             }
                         }
 
+                        //directs[i].sub_tile_offset is added to from_capacity(z) to get the
+                        // target_capacity
                         int target_cap = z + directs[i].sub_tile_offset;
+
+                        // Iterate over all sub_tiles to get the sub_tile which the target_cap belongs to.
                         const t_sub_tile* target_sub_tile = nullptr;
                         for (const auto& sub_tile : target_type->sub_tiles) {
                             if (sub_tile.capacity.is_in_range(target_cap)) {

Original file line number	Diff line number	Diff line change
`@@ -3444,7 +3444,11 @@ static int get_opin_direct_connections(RRGraphBuilder& rr_graph_builder,`
`3444`	`3444`	`}`
`3445`	`3445`	`}`
`3446`	`3446`
	`3447`	`+ //directs[i].sub_tile_offset is added to from_capacity(z) to get the`
	`3448`	`+ // target_capacity`
`3447`	`3449`	`int target_cap = z + directs[i].sub_tile_offset;`
	`3450`	`+`
	`3451`	`+ // Iterate over all sub_tiles to get the sub_tile which the target_cap belongs to.`
`3448`	`3452`	`const t_sub_tile* target_sub_tile = nullptr;`
`3449`	`3453`	`for (const auto& sub_tile : target_type->sub_tiles) {`
`3450`	`3454`	`if (sub_tile.capacity.is_in_range(target_cap)) {`