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VPR_FATAL_ERROR(VPR_ERROR_ARCH, "alloc_and_load_switchblock_connections: Switchblock %s does not match directionality of architecture\n", sb.name.c_str());
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}
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/* Iterate over the x,y coordinates spanning the FPGA. */
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for (size_t x_coord = 0; x_coord < grid.width(); x_coord++) {
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for (size_t y_coord = 0; y_coord <= grid.height(); y_coord++) {
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-
if (sb_not_here(grid, x_coord, y_coord, sb.location)) {
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if (sb_not_here(grid, x_coord, y_coord, sb.location, sb.x, sb.y)) {
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continue;
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}
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/* now we iterate over all the potential side1->side2 connections */
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