=================================================================
Logical (Complex) Block Graph:
=================================================================

EMPTY (root logical block)

io (root logical block)
└── io [1] (pb_type)
    ├── inpad (mode)
    │   └── inpad [1] (primitive pb_type | model: .input)
    └── outpad (mode)
        └── outpad [1] (primitive pb_type | model: .output)

clb (root logical block)
└── clb [1] (pb_type)
    └── default (mode)
        └── fle [10] (pb_type)
            ├── n2_lut5 (mode)
            │   └── lut5inter [1] (pb_type)
            │       └── default (mode)
            │           └── ble5 [2] (pb_type)
            │               ├── blut5 (mode)
            │               │   └── flut5 [1] (pb_type)
            │               │       └── default (mode)
            │               │           ├── lut5 [1] (pb_type)
            │               │           │   ├── wire (mode)
            │               │           │   └── lut5 (mode)
            │               │           │       └── lut [1] (primitive pb_type | model: .names)
            │               │           └── ff [1] (primitive pb_type | model: .latch)
            │               └── arithmetic (mode)
            │                   └── arithmetic [1] (pb_type)
            │                       └── default (mode)
            │                           ├── lut4 [2] (pb_type)
            │                           │   ├── wire (mode)
            │                           │   └── lut4 (mode)
            │                           │       └── lut [1] (primitive pb_type | model: .names)
            │                           ├── adder [1] (primitive pb_type | model: adder)
            │                           └── ff [1] (primitive pb_type | model: .latch)
            └── n1_lut6 (mode)
                └── ble6 [1] (pb_type)
                    └── default (mode)
                        ├── lut6 [1] (pb_type)
                        │   ├── wire (mode)
                        │   └── lut6 (mode)
                        │       └── lut [1] (primitive pb_type | model: .names)
                        └── ff [1] (primitive pb_type | model: .latch)

mult_36 (root logical block)
└── mult_36 [1] (pb_type)
    ├── two_divisible_mult_18x18 (mode)
    │   └── divisible_mult_18x18 [2] (pb_type)
    │       ├── two_mult_9x9 (mode)
    │       │   └── mult_9x9_slice [2] (pb_type)
    │       │       └── default (mode)
    │       │           └── mult_9x9 [1] (primitive pb_type | model: multiply)
    │       └── mult_18x18 (mode)
    │           └── mult_18x18_slice [1] (pb_type)
    │               └── default (mode)
    │                   └── mult_18x18 [1] (primitive pb_type | model: multiply)
    └── mult_36x36 (mode)
        └── mult_36x36_slice [1] (pb_type)
            └── default (mode)
                └── mult_36x36 [1] (primitive pb_type | model: multiply)

memory (root logical block)
└── memory [1] (pb_type)
    ├── mem_512x64_sp (mode)
    │   └── mem_512x64_sp [1] (pb_type)
    │       └── memory_slice (mode)
    │           └── memory_slice [64] (primitive pb_type | model: single_port_ram)
    ├── mem_1024x32_sp (mode)
    │   └── mem_1024x32_sp [1] (pb_type)
    │       └── memory_slice (mode)
    │           └── memory_slice [32] (primitive pb_type | model: single_port_ram)
    ├── mem_2048x16_sp (mode)
    │   └── mem_2048x16_sp [1] (pb_type)
    │       └── memory_slice (mode)
    │           └── memory_slice [16] (primitive pb_type | model: single_port_ram)
    ├── mem_4096x8_sp (mode)
    │   └── mem_4096x8_sp [1] (pb_type)
    │       └── memory_slice (mode)
    │           └── memory_slice [8] (primitive pb_type | model: single_port_ram)
    ├── mem_8192x4_sp (mode)
    │   └── mem_8192x4_sp [1] (pb_type)
    │       └── memory_slice (mode)
    │           └── memory_slice [4] (primitive pb_type | model: single_port_ram)
    ├── mem_16384x2_sp (mode)
    │   └── mem_16384x2_sp [1] (pb_type)
    │       └── memory_slice (mode)
    │           └── memory_slice [2] (primitive pb_type | model: single_port_ram)
    ├── mem_32768x1_sp (mode)
    │   └── mem_32768x1_sp [1] (pb_type)
    │       └── memory_slice (mode)
    │           └── memory_slice [1] (primitive pb_type | model: single_port_ram)
    ├── mem_1024x32_dp (mode)
    │   └── mem_1024x32_dp [1] (pb_type)
    │       └── memory_slice (mode)
    │           └── memory_slice [32] (primitive pb_type | model: dual_port_ram)
    ├── mem_2048x16_dp (mode)
    │   └── mem_2048x16_dp [1] (pb_type)
    │       └── memory_slice (mode)
    │           └── memory_slice [16] (primitive pb_type | model: dual_port_ram)
    ├── mem_2048x8_dp (mode)
    │   └── mem_2048x8_dp [1] (pb_type)
    │       └── memory_slice (mode)
    │           └── memory_slice [8] (primitive pb_type | model: dual_port_ram)
    ├── mem_8192x4_dp (mode)
    │   └── mem_8192x4_dp [1] (pb_type)
    │       └── memory_slice (mode)
    │           └── memory_slice [4] (primitive pb_type | model: dual_port_ram)
    ├── mem_16384x2_dp (mode)
    │   └── mem_16384x2_dp [1] (pb_type)
    │       └── memory_slice (mode)
    │           └── memory_slice [2] (primitive pb_type | model: dual_port_ram)
    └── mem_32768x1_dp (mode)
        └── mem_32768x1_dp [1] (pb_type)
            └── memory_slice (mode)
                └── memory_slice [1] (primitive pb_type | model: dual_port_ram)

=================================================================
Physical Tile Graph:
=================================================================

EMPTY (tile)

io (tile)
└── io [8] (sub-tile)
    └── io (equiv-site)

clb (tile)
└── clb [1] (sub-tile)
    └── clb (equiv-site)

mult_36 (tile)
└── mult_36 [1] (sub-tile)
    └── mult_36 (equiv-site)

memory (tile)
└── memory [1] (sub-tile)
    └── memory (equiv-site)

=================================================================
Logical Block Type Capacities:
=================================================================

EMPTY:

io:
	 .input: 1
	.output: 1

clb:
	 adder: 20
	.names: 40
	.latch: 20

mult_36:
	multiply: 4

memory:
	single_port_ram: 64
	  dual_port_ram: 32

=================================================================
Physical Tile Type Capacities:
=================================================================

EMPTY:

io:
	 .input: 8
	.output: 8

clb:
	 adder: 20
	.names: 40
	.latch: 20

mult_36:
	multiply: 4

memory:
	single_port_ram: 64
	  dual_port_ram: 32

=================================================================
Netlist Mass Utilization:
=================================================================

          Model: Total Netlist Mass | Total Grid Mass | Mass Utilization
         .input:                133 |            1280 |         0.103906
        .output:                179 |            1280 |         0.139844
         .latch:               2727 |           24000 |         0.113625
         .names:               9470 |           48000 |         0.197292
       multiply:                  0 |             200 |                0
single_port_ram:               1192 |            1920 |         0.620833
  dual_port_ram:                  0 |             960 |                0
          adder:                384 |           24000 |            0.016

          Model: Total Netlist Mass | Number of Blocks | Average Mass per Block
         .input:                133 |              133 |                      1
        .output:                179 |              179 |                      1
         .latch:               2727 |             2727 |                      1
         .names:               9470 |             9470 |                      1
       multiply:                  0 |                0 |                      0
single_port_ram:               1192 |             1192 |                      1
  dual_port_ram:                  0 |                0 |                      0
          adder:                384 |               39 |                9.84615

=================================================================
Expected Device Utilization:
=================================================================

Expected number of logical blocks:
	     io: 179
	    clb: 237
	mult_36: 0
	 memory: 19

Expected block utilization:
	     io: 0.139844
	    clb: 0.1975
	mult_36: 0
	 memory: 0.633333