From 2299de5ef99ee29b2887e23aad9775658f6227e8 Mon Sep 17 00:00:00 2001 From: me-no-dev Date: Tue, 1 Feb 2022 11:12:46 +0200 Subject: [PATCH 1/2] Initial SPI support and S3-Box variant --- boards.txt | 104 +++++++++++++++++ cores/esp32/esp32-hal-cpu.c | 2 +- cores/esp32/esp32-hal-spi.c | 178 +++++++++++++++++++---------- cores/esp32/esp32-hal-spi.h | 2 +- variants/esp32s3/pins_arduino.h | 8 +- variants/esp32s3box/pins_arduino.h | 76 ++++++++++++ 6 files changed, 302 insertions(+), 68 deletions(-) create mode 100644 variants/esp32s3box/pins_arduino.h diff --git a/boards.txt b/boards.txt index bced4f872d7..d10d9b268ca 100755 --- a/boards.txt +++ b/boards.txt @@ -844,6 +844,110 @@ pico32.menu.DebugLevel.verbose.build.code_debug=5 ############################################################## +esp32s3box.name=ESP32-S3-Box +esp32s3box.vid.0=0x303a +esp32s3box.pid.0=0x1001 + +esp32s3box.upload.tool=esptool_py +esp32s3box.upload.maximum_size=1310720 +esp32s3box.upload.maximum_data_size=327680 +esp32s3box.upload.speed=921600 +esp32s3box.upload.flags= +esp32s3box.upload.extra_flags= +esp32s3box.upload.use_1200bps_touch=false +esp32s3box.upload.wait_for_upload_port=false + +esp32s3box.serial.disableDTR=false +esp32s3box.serial.disableRTS=false + +esp32s3box.build.tarch=xtensa +esp32s3box.build.bootloader_addr=0x0 +esp32s3box.build.target=esp32s3 +esp32s3box.build.mcu=esp32s3 +esp32s3box.build.core=esp32 +esp32s3box.build.variant=esp32s3box +esp32s3box.build.board=ESP32_S3_BOX + +esp32s3box.build.usb_mode=1 +esp32s3box.build.cdc_on_boot=1 +esp32s3box.build.msc_on_boot=0 +esp32s3box.build.dfu_on_boot=0 +esp32s3box.build.f_cpu=240000000L +esp32s3box.build.flash_size=16MB +esp32s3box.build.flash_freq=80m +esp32s3box.build.flash_mode=dio +esp32s3box.build.boot=qio +esp32s3box.build.partitions=default +esp32s3box.build.defines=-DBOARD_HAS_PSRAM +esp32s3box.build.loop_core=-DARDUINO_RUNNING_CORE=1 +esp32s3box.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 + +esp32s3box.menu.USBMode.hwcdc=Hardware CDC and JTAG +esp32s3box.menu.USBMode.hwcdc.build.usb_mode=1 +esp32s3box.menu.USBMode.hwcdc.upload.use_1200bps_touch=false +esp32s3box.menu.USBMode.hwcdc.upload.wait_for_upload_port=false +esp32s3box.menu.USBMode.default=USB-OTG +esp32s3box.menu.USBMode.default.build.usb_mode=0 +esp32s3box.menu.USBMode.default.upload.use_1200bps_touch=true +esp32s3box.menu.USBMode.default.upload.wait_for_upload_port=true + +esp32s3box.menu.MSCOnBoot.default=Disabled +esp32s3box.menu.MSCOnBoot.default.build.msc_on_boot=0 +esp32s3box.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +esp32s3box.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +esp32s3box.menu.DFUOnBoot.default=Disabled +esp32s3box.menu.DFUOnBoot.default.build.dfu_on_boot=0 +esp32s3box.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +esp32s3box.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +esp32s3box.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32s3box.menu.PartitionScheme.default.build.partitions=default +esp32s3box.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32s3box.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32s3box.menu.PartitionScheme.default_8MB=8M Flash (3MB APP/1.5MB FAT) +esp32s3box.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32s3box.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32s3box.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32s3box.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32s3box.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32s3box.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32s3box.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32s3box.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32s3box.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32s3box.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32s3box.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32s3box.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32s3box.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32s3box.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32s3box.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32s3box.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32s3box.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32s3box.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS) +esp32s3box.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32s3box.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32s3box.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT) +esp32s3box.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32s3box.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32s3box.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS) +esp32s3box.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32s3box.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 + +esp32s3box.menu.DebugLevel.none=None +esp32s3box.menu.DebugLevel.none.build.code_debug=0 +esp32s3box.menu.DebugLevel.error=Error +esp32s3box.menu.DebugLevel.error.build.code_debug=1 +esp32s3box.menu.DebugLevel.warn=Warn +esp32s3box.menu.DebugLevel.warn.build.code_debug=2 +esp32s3box.menu.DebugLevel.info=Info +esp32s3box.menu.DebugLevel.info.build.code_debug=3 +esp32s3box.menu.DebugLevel.debug=Debug +esp32s3box.menu.DebugLevel.debug.build.code_debug=4 +esp32s3box.menu.DebugLevel.verbose=Verbose +esp32s3box.menu.DebugLevel.verbose.build.code_debug=5 + +############################################################## + esp32s2usb.name=ESP32S2 Native USB esp32s2usb.vid.0=0x303a esp32s2usb.pid.0=0x0003 diff --git a/cores/esp32/esp32-hal-cpu.c b/cores/esp32/esp32-hal-cpu.c index 8295efd7b19..d79803f6124 100644 --- a/cores/esp32/esp32-hal-cpu.c +++ b/cores/esp32/esp32-hal-cpu.c @@ -147,7 +147,7 @@ bool removeApbChangeCallback(void * arg, apb_change_cb_t cb){ } static uint32_t calculateApb(rtc_cpu_freq_config_t * conf){ -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 return APB_CLK_FREQ; #else if(conf->freq_mhz >= 80){ diff --git a/cores/esp32/esp32-hal-spi.c b/cores/esp32/esp32-hal-spi.c index ca514200252..39ad027be55 100644 --- a/cores/esp32/esp32-hal-spi.c +++ b/cores/esp32/esp32-hal-spi.c @@ -55,8 +55,6 @@ #include "esp_intr.h" #endif -#ifndef CONFIG_IDF_TARGET_ESP32S3 - struct spi_struct_t { spi_dev_t * dev; #if !CONFIG_DISABLE_HAL_LOCKS @@ -78,25 +76,20 @@ struct spi_struct_t { #define SPI_FSPI_SS_IDX(n) ((n==0)?FSPICS0_OUT_IDX:((n==1)?FSPICS1_OUT_IDX:((n==2)?FSPICS2_OUT_IDX:FSPICS0_OUT_IDX))) #define SPI_SS_IDX(p, n) ((p==0)?SPI_SPI_SS_IDX(n):((p==1)?SPI_SPI_SS_IDX(n):((p==2)?SPI_HSPI_SS_IDX(n):0))) -#define SPI_INTR_SOURCE(u) ((u==0)?ETS_SPI1_INTR_SOURCE:((u==1)?ETS_SPI2_INTR_SOURCE:((u==2)?ETS_SPI3_INTR_SOURCE:0))) - #elif CONFIG_IDF_TARGET_ESP32S3 // ESP32S3 #define SPI_COUNT (2) -#define SPI_CLK_IDX(p) ((p==0)?SPICLK_OUT_IDX:((p==1)?FSPICLK_OUT_IDX:0)) -#define SPI_MISO_IDX(p) ((p==0)?SPIQ_OUT_IDX:((p==1)?FSPIQ_OUT_IDX:0)) -#define SPI_MOSI_IDX(p) ((p==0)?SPID_IN_IDX:((p==1)?FSPID_IN_IDX:0)) +#define SPI_CLK_IDX(p) ((p==0)?FSPICLK_OUT_IDX:((p==1)?SPI3_CLK_OUT_IDX:0)) +#define SPI_MISO_IDX(p) ((p==0)?FSPIQ_OUT_IDX:((p==1)?SPI3_Q_OUT_IDX:0)) +#define SPI_MOSI_IDX(p) ((p==0)?FSPID_IN_IDX:((p==1)?SPI3_D_IN_IDX:0)) -#define SPI_SPI_SS_IDX(n) ((n==0)?SPICS0_OUT_IDX:((n==1)?SPICS1_OUT_IDX:0)) #define SPI_HSPI_SS_IDX(n) ((n==0)?SPI3_CS0_OUT_IDX:((n==1)?SPI3_CS1_OUT_IDX:0)) #define SPI_FSPI_SS_IDX(n) ((n==0)?FSPICS0_OUT_IDX:((n==1)?FSPICS1_OUT_IDX:0)) -#define SPI_SS_IDX(p, n) ((p==0)?SPI_SPI_SS_IDX(n):((p==1)?SPI_SPI_SS_IDX(n):0)) - -#define SPI_INTR_SOURCE(u) ((u==0)?ETS_SPI1_INTR_SOURCE:((u==1)?ETS_SPI2_INTR_SOURCE:0)) +#define SPI_SS_IDX(p, n) ((p==0)?SPI_FSPI_SS_IDX(n):((p==1)?SPI_HSPI_SS_IDX(n):0)) #elif CONFIG_IDF_TARGET_ESP32C3 -// ESP32S2 +// ESP32C3 #define SPI_COUNT (1) #define SPI_CLK_IDX(p) FSPICLK_OUT_IDX @@ -106,8 +99,6 @@ struct spi_struct_t { #define SPI_SPI_SS_IDX(n) ((n==0)?FSPICS0_OUT_IDX:((n==1)?FSPICS1_OUT_IDX:((n==2)?FSPICS2_OUT_IDX:FSPICS0_OUT_IDX))) #define SPI_SS_IDX(p, n) SPI_SPI_SS_IDX(n) -#define SPI_INTR_SOURCE(u) ETS_SPI2_INTR_SOURCE - #else // ESP32 #define SPI_COUNT (4) @@ -121,8 +112,6 @@ struct spi_struct_t { #define SPI_VSPI_SS_IDX(n) ((n==0)?VSPICS0_OUT_IDX:((n==1)?VSPICS1_OUT_IDX:((n==2)?VSPICS2_OUT_IDX:VSPICS0_OUT_IDX))) #define SPI_SS_IDX(p, n) ((p==0)?SPI_SPI_SS_IDX(n):((p==1)?SPI_SPI_SS_IDX(n):((p==2)?SPI_HSPI_SS_IDX(n):((p==3)?SPI_VSPI_SS_IDX(n):0)))) -#define SPI_INTR_SOURCE(u) ((u==0)?ETS_SPI0_INTR_SOURCE:((u==1)?ETS_SPI1_INTR_SOURCE:((u==2)?ETS_SPI2_INTR_SOURCE:((p==3)?ETS_SPI3_INTR_SOURCE:0)))) - #endif #if CONFIG_DISABLE_HAL_LOCKS @@ -135,8 +124,10 @@ static spi_t _spi_bus_array[] = { {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), 1}, {(volatile spi_dev_t *)(DR_REG_SPI3_BASE), 2} #elif CONFIG_IDF_TARGET_ESP32S3 - {(volatile spi_dev_t *)(DR_REG_SPI1_BASE), 0}, - {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), 1} + {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), 0}, + {(volatile spi_dev_t *)(DR_REG_SPI3_BASE), 1} +#elif CONFIG_IDF_TARGET_ESP32C3 + {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), 0} #else {(volatile spi_dev_t *)(DR_REG_SPI0_BASE), 0}, {(volatile spi_dev_t *)(DR_REG_SPI1_BASE), 1}, @@ -154,10 +145,10 @@ static spi_t _spi_bus_array[] = { {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), NULL, 1}, {(volatile spi_dev_t *)(DR_REG_SPI3_BASE), NULL, 2} #elif CONFIG_IDF_TARGET_ESP32S3 - {(volatile spi_dev_t *)(DR_REG_SPI1_BASE), NULL, 0}, - {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), NULL, 1} + {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), NULL, 0}, + {(volatile spi_dev_t *)(DR_REG_SPI3_BASE), NULL, 1} #elif CONFIG_IDF_TARGET_ESP32C3 - {(volatile spi_dev_t *)(&GPSPI2), NULL, FSPI} + {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), NULL, 0} #else {(volatile spi_dev_t *)(DR_REG_SPI0_BASE), NULL, 0}, {(volatile spi_dev_t *)(DR_REG_SPI1_BASE), NULL, 1}, @@ -173,13 +164,20 @@ void spiAttachSCK(spi_t * spi, int8_t sck) return; } if(sck < 0) { -#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 +#if CONFIG_IDF_TARGET_ESP32S2 if(spi->num == FSPI) { sck = 36; } else { log_e("HSPI Does not have default pins on ESP32S2!"); return; } +#elif CONFIG_IDF_TARGET_ESP32S3 + if(spi->num == FSPI) { + sck = 12; + } else { + log_e("HSPI Does not have default pins on ESP32S3!"); + return; + } #elif CONFIG_IDF_TARGET_ESP32 if(spi->num == HSPI) { sck = 14; @@ -203,13 +201,20 @@ void spiAttachMISO(spi_t * spi, int8_t miso) return; } if(miso < 0) { -#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 +#if CONFIG_IDF_TARGET_ESP32S2 if(spi->num == FSPI) { miso = 37; } else { log_e("HSPI Does not have default pins on ESP32S2!"); return; } +#elif CONFIG_IDF_TARGET_ESP32S3 + if(spi->num == FSPI) { + miso = 13; + } else { + log_e("HSPI Does not have default pins on ESP32S3!"); + return; + } #elif CONFIG_IDF_TARGET_ESP32 if(spi->num == HSPI) { miso = 12; @@ -242,6 +247,13 @@ void spiAttachMOSI(spi_t * spi, int8_t mosi) log_e("HSPI Does not have default pins on ESP32S2!"); return; } +#elif CONFIG_IDF_TARGET_ESP32S3 + if(spi->num == FSPI) { + mosi = 11; + } else { + log_e("HSPI Does not have default pins on ESP32S3!"); + return; + } #elif CONFIG_IDF_TARGET_ESP32 if(spi->num == HSPI) { mosi = 13; @@ -272,6 +284,13 @@ void spiDetachSCK(spi_t * spi, int8_t sck) log_e("HSPI Does not have default pins on ESP32S2!"); return; } +#elif CONFIG_IDF_TARGET_ESP32S3 + if(spi->num == FSPI) { + sck = 12; + } else { + log_e("HSPI Does not have default pins on ESP32S3!"); + return; + } #elif CONFIG_IDF_TARGET_ESP32 if(spi->num == HSPI) { sck = 14; @@ -302,6 +321,13 @@ void spiDetachMISO(spi_t * spi, int8_t miso) log_e("HSPI Does not have default pins on ESP32S2!"); return; } +#elif CONFIG_IDF_TARGET_ESP32S3 + if(spi->num == FSPI) { + miso = 13; + } else { + log_e("HSPI Does not have default pins on ESP32S3!"); + return; + } #elif CONFIG_IDF_TARGET_ESP32 if(spi->num == HSPI) { miso = 12; @@ -332,6 +358,13 @@ void spiDetachMOSI(spi_t * spi, int8_t mosi) log_e("HSPI Does not have default pins on ESP32S2!"); return; } +#elif CONFIG_IDF_TARGET_ESP32S3 + if(spi->num == FSPI) { + mosi = 11; + } else { + log_e("HSPI Does not have default pins on ESP32S3!"); + return; + } #elif CONFIG_IDF_TARGET_ESP32 if(spi->num == HSPI) { mosi = 13; @@ -359,13 +392,20 @@ void spiAttachSS(spi_t * spi, uint8_t cs_num, int8_t ss) } if(ss < 0) { cs_num = 0; -#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 +#if CONFIG_IDF_TARGET_ESP32S2 if(spi->num == FSPI) { ss = 34; } else { log_e("HSPI Does not have default pins on ESP32S2!"); return; } +#elif CONFIG_IDF_TARGET_ESP32S3 + if(spi->num == FSPI) { + ss = 10; + } else { + log_e("HSPI Does not have default pins on ESP32S3!"); + return; + } #elif CONFIG_IDF_TARGET_ESP32 if(spi->num == HSPI) { ss = 15; @@ -390,13 +430,20 @@ void spiDetachSS(spi_t * spi, int8_t ss) return; } if(ss < 0) { -#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 +#if CONFIG_IDF_TARGET_ESP32S2 if(spi->num == FSPI) { ss = 34; } else { log_e("HSPI Does not have default pins on ESP32S2!"); return; } +#elif CONFIG_IDF_TARGET_ESP32S3 + if(spi->num == FSPI) { + ss = 10; + } else { + log_e("HSPI Does not have default pins on ESP32S3!"); + return; + } #elif CONFIG_IDF_TARGET_ESP32 if(spi->num == HSPI) { ss = 15; @@ -615,7 +662,7 @@ static void _on_apb_change(void * arg, apb_change_ev_t ev_type, uint32_t old_apb static void spiInitBus(spi_t * spi) { -#ifndef CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 spi->dev->slave.trans_done = 0; #endif spi->dev->slave.val = 0; @@ -627,7 +674,7 @@ static void spiInitBus(spi_t * spi) spi->dev->user.val = 0; spi->dev->user1.val = 0; spi->dev->ctrl.val = 0; -#ifndef CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 spi->dev->ctrl1.val = 0; spi->dev->ctrl2.val = 0; #else @@ -669,7 +716,7 @@ spi_t * spiStartBus(uint8_t spi_num, uint32_t clockDiv, uint8_t dataMode, uint8_ } #endif -#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 +#if CONFIG_IDF_TARGET_ESP32S2 if(spi_num == FSPI) { DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI2_CLK_EN); DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI2_RST); @@ -680,6 +727,14 @@ spi_t * spiStartBus(uint8_t spi_num, uint32_t clockDiv, uint8_t dataMode, uint8_ DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI01_CLK_EN); DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI01_RST); } +#elif CONFIG_IDF_TARGET_ESP32S3 + if(spi_num == FSPI) { + periph_module_reset( PERIPH_SPI2_MODULE ); + periph_module_enable( PERIPH_SPI2_MODULE ); + } else if(spi_num == HSPI) { + periph_module_reset( PERIPH_SPI3_MODULE ); + periph_module_enable( PERIPH_SPI3_MODULE ); + } #elif CONFIG_IDF_TARGET_ESP32 if(spi_num == HSPI) { DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI2_CLK_EN); @@ -698,7 +753,7 @@ spi_t * spiStartBus(uint8_t spi_num, uint32_t clockDiv, uint8_t dataMode, uint8_ SPI_MUTEX_LOCK(); spiInitBus(spi); -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->clk_gate.clk_en = 1; spi->dev->clk_gate.mst_clk_sel = 1; spi->dev->clk_gate.mst_clk_active = 1; @@ -732,10 +787,10 @@ void spiWaitReady(spi_t * spi) while(spi->dev->cmd.usr); } -#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 +#if CONFIG_IDF_TARGET_ESP32S2 #define usr_mosi_dbitlen usr_mosi_bit_len #define usr_miso_dbitlen usr_miso_bit_len -#elif CONFIG_IDF_TARGET_ESP32C3 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 #define usr_mosi_dbitlen ms_data_bitlen #define usr_miso_dbitlen ms_data_bitlen #define mosi_dlen ms_dlen @@ -753,13 +808,13 @@ void spiWrite(spi_t * spi, const uint32_t *data, uint8_t len) } SPI_MUTEX_LOCK(); spi->dev->mosi_dlen.usr_mosi_dbitlen = (len * 32) - 1; -#ifndef CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 spi->dev->miso_dlen.usr_miso_dbitlen = 0; #endif for(i=0; idev->data_buf[i] = data[i]; } -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->cmd.update = 1; while (spi->dev->cmd.update); #endif @@ -783,7 +838,7 @@ void spiTransfer(spi_t * spi, uint32_t *data, uint8_t len) for(i=0; idev->data_buf[i] = data[i]; } -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->cmd.update = 1; while (spi->dev->cmd.update); #endif @@ -802,11 +857,11 @@ void spiWriteByte(spi_t * spi, uint8_t data) } SPI_MUTEX_LOCK(); spi->dev->mosi_dlen.usr_mosi_dbitlen = 7; -#ifndef CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 spi->dev->miso_dlen.usr_miso_dbitlen = 0; #endif spi->dev->data_buf[0] = data; -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->cmd.update = 1; while (spi->dev->cmd.update); #endif @@ -824,7 +879,7 @@ uint8_t spiTransferByte(spi_t * spi, uint8_t data) spi->dev->mosi_dlen.usr_mosi_dbitlen = 7; spi->dev->miso_dlen.usr_miso_dbitlen = 7; spi->dev->data_buf[0] = data; -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->cmd.update = 1; while (spi->dev->cmd.update); #endif @@ -855,11 +910,11 @@ void spiWriteWord(spi_t * spi, uint16_t data) } SPI_MUTEX_LOCK(); spi->dev->mosi_dlen.usr_mosi_dbitlen = 15; -#ifndef CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 spi->dev->miso_dlen.usr_miso_dbitlen = 0; #endif spi->dev->data_buf[0] = data; -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->cmd.update = 1; while (spi->dev->cmd.update); #endif @@ -880,7 +935,7 @@ uint16_t spiTransferWord(spi_t * spi, uint16_t data) spi->dev->mosi_dlen.usr_mosi_dbitlen = 15; spi->dev->miso_dlen.usr_miso_dbitlen = 15; spi->dev->data_buf[0] = data; -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->cmd.update = 1; while (spi->dev->cmd.update); #endif @@ -904,11 +959,11 @@ void spiWriteLong(spi_t * spi, uint32_t data) } SPI_MUTEX_LOCK(); spi->dev->mosi_dlen.usr_mosi_dbitlen = 31; -#ifndef CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 spi->dev->miso_dlen.usr_miso_dbitlen = 0; #endif spi->dev->data_buf[0] = data; -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->cmd.update = 1; while (spi->dev->cmd.update); #endif @@ -929,7 +984,7 @@ uint32_t spiTransferLong(spi_t * spi, uint32_t data) spi->dev->mosi_dlen.usr_mosi_dbitlen = 31; spi->dev->miso_dlen.usr_miso_dbitlen = 31; spi->dev->data_buf[0] = data; -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->cmd.update = 1; while (spi->dev->cmd.update); #endif @@ -972,7 +1027,7 @@ static void __spiTransferBytes(spi_t * spi, const uint8_t * data, uint8_t * out, spi->dev->data_buf[i] = wordsBuf[i]; //copy buffer to spi fifo } -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->cmd.update = 1; while (spi->dev->cmd.update); #endif @@ -1104,11 +1159,11 @@ void ARDUINO_ISR_ATTR spiWriteByteNL(spi_t * spi, uint8_t data) return; } spi->dev->mosi_dlen.usr_mosi_dbitlen = 7; -#ifndef CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 spi->dev->miso_dlen.usr_miso_dbitlen = 0; #endif spi->dev->data_buf[0] = data; -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->cmd.update = 1; while (spi->dev->cmd.update); #endif @@ -1124,7 +1179,7 @@ uint8_t spiTransferByteNL(spi_t * spi, uint8_t data) spi->dev->mosi_dlen.usr_mosi_dbitlen = 7; spi->dev->miso_dlen.usr_miso_dbitlen = 7; spi->dev->data_buf[0] = data; -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->cmd.update = 1; while (spi->dev->cmd.update); #endif @@ -1143,11 +1198,11 @@ void ARDUINO_ISR_ATTR spiWriteShortNL(spi_t * spi, uint16_t data) MSB_16_SET(data, data); } spi->dev->mosi_dlen.usr_mosi_dbitlen = 15; -#ifndef CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 spi->dev->miso_dlen.usr_miso_dbitlen = 0; #endif spi->dev->data_buf[0] = data; -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->cmd.update = 1; while (spi->dev->cmd.update); #endif @@ -1166,7 +1221,7 @@ uint16_t spiTransferShortNL(spi_t * spi, uint16_t data) spi->dev->mosi_dlen.usr_mosi_dbitlen = 15; spi->dev->miso_dlen.usr_miso_dbitlen = 15; spi->dev->data_buf[0] = data; -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->cmd.update = 1; while (spi->dev->cmd.update); #endif @@ -1188,11 +1243,11 @@ void ARDUINO_ISR_ATTR spiWriteLongNL(spi_t * spi, uint32_t data) MSB_32_SET(data, data); } spi->dev->mosi_dlen.usr_mosi_dbitlen = 31; -#ifndef CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 spi->dev->miso_dlen.usr_miso_dbitlen = 0; #endif spi->dev->data_buf[0] = data; -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->cmd.update = 1; while (spi->dev->cmd.update); #endif @@ -1211,7 +1266,7 @@ uint32_t spiTransferLongNL(spi_t * spi, uint32_t data) spi->dev->mosi_dlen.usr_mosi_dbitlen = 31; spi->dev->miso_dlen.usr_miso_dbitlen = 31; spi->dev->data_buf[0] = data; -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->cmd.update = 1; while (spi->dev->cmd.update); #endif @@ -1240,13 +1295,13 @@ void spiWriteNL(spi_t * spi, const void * data_in, uint32_t len){ c_longs = (longs > 16)?16:longs; spi->dev->mosi_dlen.usr_mosi_dbitlen = (c_len*8)-1; -#ifndef CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 spi->dev->miso_dlen.usr_miso_dbitlen = 0; #endif for (int i=0; idev->data_buf[i] = data[i]; } -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->cmd.update = 1; while (spi->dev->cmd.update); #endif @@ -1286,7 +1341,7 @@ void spiTransferBytesNL(spi_t * spi, const void * data_in, uint8_t * data_out, u spi->dev->data_buf[i] = 0xFFFFFFFF; } } -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->cmd.update = 1; while (spi->dev->cmd.update); #endif @@ -1345,7 +1400,7 @@ void spiTransferBitsNL(spi_t * spi, uint32_t data, uint32_t * out, uint8_t bits) spi->dev->mosi_dlen.usr_mosi_dbitlen = (bits - 1); spi->dev->miso_dlen.usr_miso_dbitlen = (bits - 1); spi->dev->data_buf[0] = data; -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->cmd.update = 1; while (spi->dev->cmd.update); #endif @@ -1381,7 +1436,7 @@ void ARDUINO_ISR_ATTR spiWritePixelsNL(spi_t * spi, const void * data_in, uint32 l_bytes = (c_len & 3); spi->dev->mosi_dlen.usr_mosi_dbitlen = (c_len*8)-1; -#ifndef CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 spi->dev->miso_dlen.usr_miso_dbitlen = 0; #endif for (int i=0; idev->data_buf[i] = data[i]; } } -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->cmd.update = 1; while (spi->dev->cmd.update); #endif @@ -1425,7 +1480,7 @@ typedef union { uint32_t clkcnt_l: 6; /*it must be equal to spi_clkcnt_N.*/ uint32_t clkcnt_h: 6; /*it must be floor((spi_clkcnt_N+1)/2-1).*/ uint32_t clkcnt_n: 6; /*it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/ -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 uint32_t clkdiv_pre: 4; /*it is pre-divider of spi_clk.*/ uint32_t reserved: 9; /*reserved*/ #else @@ -1472,7 +1527,7 @@ uint32_t spiFrequencyToClockDiv(uint32_t freq) while(calPreVari++ <= 1) { calPre = (((apb_freq / (reg.clkcnt_n + 1)) / freq) - 1) + calPreVari; -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 if(calPre > 0xF) { reg.clkdiv_pre = 0xF; #else @@ -1503,4 +1558,3 @@ uint32_t spiFrequencyToClockDiv(uint32_t freq) } return bestReg.value; } -#endif /* ifndef CONFIG_IDF_TARGET_ESP32S3 */ diff --git a/cores/esp32/esp32-hal-spi.h b/cores/esp32/esp32-hal-spi.h index 6fbb7b3dca7..89ceefccd60 100644 --- a/cores/esp32/esp32-hal-spi.h +++ b/cores/esp32/esp32-hal-spi.h @@ -25,7 +25,7 @@ extern "C" { #define SPI_HAS_TRANSACTION -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 #define FSPI 0 #define HSPI 1 #else diff --git a/variants/esp32s3/pins_arduino.h b/variants/esp32s3/pins_arduino.h index e5daaae3bb7..5cd22fa56c5 100644 --- a/variants/esp32s3/pins_arduino.h +++ b/variants/esp32s3/pins_arduino.h @@ -20,10 +20,10 @@ static const uint8_t RX = 44; static const uint8_t SDA = 8; static const uint8_t SCL = 9; -static const uint8_t SS = 34; -static const uint8_t MOSI = 35; -static const uint8_t MISO = 37; -static const uint8_t SCK = 36; +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; static const uint8_t A0 = 1; static const uint8_t A1 = 2; diff --git a/variants/esp32s3box/pins_arduino.h b/variants/esp32s3box/pins_arduino.h new file mode 100644 index 00000000000..687468251f9 --- /dev/null +++ b/variants/esp32s3box/pins_arduino.h @@ -0,0 +1,76 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +#define EXTERNAL_NUM_INTERRUPTS 46 +#define NUM_DIGITAL_PINS 48 +#define NUM_ANALOG_INPUTS 20 + +#define analogInputToDigitalPin(p) (((p)<20)?(esp32_adc2gpio[(p)]):-1) +#define digitalPinToInterrupt(p) (((p)<48)?(p):-1) +#define digitalPinHasPWM(p) (p < 46) + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 41; +static const uint8_t SCL = 40; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; + +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +// Wire1 for ES7210 MIC ADC, ES8311 I2S DAC, ICM-42607-P IMU and TT21100 Touch Panel +#define I2C_SDA 8 +#define I2C_SCL 18 + +#define ES7210_ADDR 0x40 //MIC ADC +#define ES8311_ADDR 0x18 //I2S DAC +#define ICM42607P_ADDR 0x68 //IMU +#define TT21100_ADDR 0x24 //Touch Panel + +#define TFT_DC 4 +#define TFT_CS 5 +#define TFT_MOSI 6 +#define TFT_CLK 7 +#define TFT_MISO 0 +#define TFT_BL 45 +#define TFT_RST 48 + +#define I2S_LRCK 47 +#define I2S_MCLK 2 +#define I2S_SCLK 17 +#define I2S_SDIN 16 +#define I2S_DOUT 15 + +#define SDMMC_CLK 13 +#define SDMMC_CMD 11 +#define SDMMC_D0 14 +#define SDMMC_D1 12 +#define SDMMC_D2 10 +#define SDMMC_D3 9 + +#define PA_PIN 46 //Audio Amp Power +#define MUTE_PIN 1 //MUTE Button +#define TS_IRQ 3 //Touch Screen IRQ + +#endif /* Pins_Arduino_h */ From e3eabf5621c81c1b8acaa7ad0cf580f039b9c3b4 Mon Sep 17 00:00:00 2001 From: Jason2866 <24528715+Jason2866@users.noreply.github.com> Date: Tue, 1 Feb 2022 10:55:37 +0100 Subject: [PATCH 2/2] Bootloader is at 0x0000 for S3 (#6215) --- tools/platformio-build-esp32s3.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/platformio-build-esp32s3.py b/tools/platformio-build-esp32s3.py index 9d3283a1006..f14f9f3eb04 100644 --- a/tools/platformio-build-esp32s3.py +++ b/tools/platformio-build-esp32s3.py @@ -324,7 +324,7 @@ ], FLASH_EXTRA_IMAGES=[ - ("0x1000", join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "bin", "bootloader_${BOARD_FLASH_MODE}_${__get_board_f_flash(__env__)}.bin")), + ("0x0000", join(FRAMEWORK_DIR, "tools", "sdk", "esp32s3", "bin", "bootloader_${BOARD_FLASH_MODE}_${__get_board_f_flash(__env__)}.bin")), ("0x8000", join(env.subst("$BUILD_DIR"), "partitions.bin")), ("0xe000", join(FRAMEWORK_DIR, "tools", "partitions", "boot_app0.bin")) ]