Merge pull request #89 from espressif/esp32-s3-support

Update 2 from 23022022

Author: Jason2866

.github/scripts/install-platformio-esp32.sh

@@ -3,9 +3,7 @@
 export PLATFORMIO_ESP32_PATH="$HOME/.platformio/packages/framework-arduinoespressif32"
 PLATFORMIO_ESP32_URL="https://github.com/platformio/platform-espressif32.git#feature/arduino-idf-master"
 
-XTENSA32_TOOLCHAIN_VERSION="8.4.0+2021r2-patch2"
-XTENSA32S2_TOOLCHAIN_VERSION="8.4.0+2021r2-patch2"
-RISCV_TOOLCHAIN_VERSION="8.4.0+2021r2-patch2"
+TOOLCHAIN_VERSION="8.4.0+2021r2-patch2"
 ESPTOOLPY_VERSION="~1.30100.0"
 ESPRESSIF_ORGANIZATION_NAME="espressif"
 
@@ -28,11 +26,13 @@ replace_script+="del data['packages']['framework-arduinoespressif32']['owner'];"
 # Use toolchain packages from the "espressif" organization
 replace_script+="data['packages']['toolchain-xtensa-esp32']['owner']='$ESPRESSIF_ORGANIZATION_NAME';"
 replace_script+="data['packages']['toolchain-xtensa-esp32s2']['owner']='$ESPRESSIF_ORGANIZATION_NAME';"
+replace_script+="data['packages']['toolchain-xtensa-esp32s3']['owner']='$ESPRESSIF_ORGANIZATION_NAME';"
 replace_script+="data['packages']['toolchain-riscv32-esp']['owner']='$ESPRESSIF_ORGANIZATION_NAME';"
 # Update versions to use the upstream
-replace_script+="data['packages']['toolchain-xtensa-esp32']['version']='$XTENSA32_TOOLCHAIN_VERSION';"
-replace_script+="data['packages']['toolchain-xtensa-esp32s2']['version']='$XTENSA32S2_TOOLCHAIN_VERSION';"
-replace_script+="data['packages']['toolchain-riscv32-esp']['version']='$RISCV_TOOLCHAIN_VERSION';"
+replace_script+="data['packages']['toolchain-xtensa-esp32']['version']='$TOOLCHAIN_VERSION';"
+replace_script+="data['packages']['toolchain-xtensa-esp32s2']['version']='$TOOLCHAIN_VERSION';"
+replace_script+="data['packages']['toolchain-xtensa-esp32s3']['version']='$TOOLCHAIN_VERSION';"
+replace_script+="data['packages']['toolchain-riscv32-esp']['version']='$TOOLCHAIN_VERSION';"
 # esptool.py may require an upstream version (for now platformio is the owner)
 replace_script+="data['packages']['tool-esptoolpy']['version']='$ESPTOOLPY_VERSION';"
 # Save results

.github/scripts/on-push.sh

@@ -63,6 +63,7 @@ if [ "$BUILD_PIO" -eq 0 ]; then
 
     FQBN_ESP32="espressif:esp32:esp32:PSRAM=enabled,PartitionScheme=huge_app"
     FQBN_ESP32S2="espressif:esp32:esp32s2:PSRAM=enabled,PartitionScheme=huge_app"
+    FQBN_ESP32S3="espressif:esp32:esp32s3:PSRAM=opi,PartitionScheme=huge_app"
     FQBN_ESP32C3="espressif:esp32:esp32c3:PartitionScheme=huge_app"
 
     SKETCHES_ESP32="\
@@ -78,6 +79,7 @@ if [ "$BUILD_PIO" -eq 0 ]; then
 
     build "esp32" $FQBN_ESP32 $CHUNK_INDEX $CHUNKS_CNT $SKETCHES_ESP32
     build "esp32s2" $FQBN_ESP32S2 $CHUNK_INDEX $CHUNKS_CNT $SKETCHES_ESP32XX
+    build "esp32s3" $FQBN_ESP32S3 $CHUNK_INDEX $CHUNKS_CNT $SKETCHES_ESP32
     build "esp32c3" $FQBN_ESP32C3 $CHUNK_INDEX $CHUNKS_CNT $SKETCHES_ESP32XX
 else
     source ./${SCRIPTS_DIR}/install-platformio-esp32.sh
@@ -96,6 +98,8 @@ else
     # build_pio_sketch "$BOARD" "$OPTIONS" "$PLATFORMIO_ESP32_PATH/libraries/WiFiClientSecure/examples/WiFiClientSecure/WiFiClientSecure.ino"
 
     python -m platformio ci --board "$BOARD" "$PLATFORMIO_ESP32_PATH/libraries/WiFi/examples/WiFiClient" --project-option="board_build.mcu = esp32s2" --project-option="board_build.partitions = huge_app.csv"
+    python -m platformio ci --board "$BOARD" "$PLATFORMIO_ESP32_PATH/libraries/WiFi/examples/WiFiClient" --project-option="board_build.mcu = esp32s3" --project-option="board_build.partitions = huge_app.csv"
+    python -m platformio ci --board "$BOARD" "$PLATFORMIO_ESP32_PATH/libraries/WiFi/examples/WiFiClient" --project-option="board_build.mcu = esp32c3" --project-option="board_build.partitions = huge_app.csv"
 
     #build_pio_sketches "$BOARD" "$OPTIONS" "$PLATFORMIO_ESP32_PATH/libraries"
 fi

platform.txt

@@ -304,7 +304,7 @@
         "UNITY_INCLUDE_CONFIG_H",
         "WITH_POSIX",
         "_GNU_SOURCE",
-        ("IDF_VER", '\\"v4.4-98-geb3797dc3f\\"'),
+        ("IDF_VER", '\\"v4.4-263-g000d3823bb\\"'),
         "ESP_PLATFORM",
         "_POSIX_READER_WRITER_LOCKS",
         "ARDUINO_ARCH_ESP32",

tools/esptool.py

@@ -294,7 +294,7 @@
         "UNITY_INCLUDE_CONFIG_H",
         "WITH_POSIX",
         "_GNU_SOURCE",
-        ("IDF_VER", '\\"v4.4-98-geb3797dc3f\\"'),
+        ("IDF_VER", '\\"v4.4-263-g000d3823bb\\"'),
         "ESP_PLATFORM",
         "_POSIX_READER_WRITER_LOCKS",
         "ARDUINO_ARCH_ESP32",

tools/platformio-build-esp32.py

@@ -291,7 +291,7 @@
         "UNITY_INCLUDE_CONFIG_H",
         "WITH_POSIX",
         "_GNU_SOURCE",
-        ("IDF_VER", '\\"v4.4-98-geb3797dc3f\\"'),
+        ("IDF_VER", '\\"v4.4-263-g000d3823bb\\"'),
         "ESP_PLATFORM",
         "_POSIX_READER_WRITER_LOCKS",
         "ARDUINO_ARCH_ESP32",

tools/platformio-build-esp32c3.py

@@ -308,7 +308,7 @@
         "UNITY_INCLUDE_CONFIG_H",
         "WITH_POSIX",
         "_GNU_SOURCE",
-        ("IDF_VER", '\\"v4.4-98-geb3797dc3f\\"'),
+        ("IDF_VER", '\\"v4.4-263-g000d3823bb\\"'),
         "ESP_PLATFORM",
         "_POSIX_READER_WRITER_LOCKS",
         "ARDUINO_ARCH_ESP32",

tools/platformio-build-esp32s2.py

@@ -419,6 +419,7 @@
 #define CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE 1
 #define CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC 1
 #define CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN 16384
+#define CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE 1
 #define CONFIG_MBEDTLS_CERTIFICATE_BUNDLE 1
 #define CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL 1
 #define CONFIG_MBEDTLS_HARDWARE_AES 1
@@ -554,6 +555,7 @@
 #define CONFIG_GC032A_SUPPORT 1
 #define CONFIG_GC0308_SUPPORT 1
 #define CONFIG_BF3005_SUPPORT 1
+#define CONFIG_BF20A6_SUPPORT 1
 #define CONFIG_SCCB_HARDWARE_I2C_PORT1 1
 #define CONFIG_SCCB_CLK_FREQ 100000
 #define CONFIG_GC_SENSOR_SUBSAMPLE_MODE 1

tools/platformio-build-esp32s3.py

@@ -27,6 +27,7 @@ typedef enum {
     GC032A_PID = 0x232a,
     GC0308_PID = 0x9b,
     BF3005_PID = 0x30,
+    BF20A6_PID = 0x20a6,
 } camera_pid_t;
 
 typedef enum {
@@ -40,6 +41,7 @@ typedef enum {
     CAMERA_GC032A,
     CAMERA_GC0308,
     CAMERA_BF3005,
+    CAMERA_BF20A6,
     CAMERA_MODEL_MAX,
     CAMERA_NONE,
 } camera_model_t;
@@ -55,6 +57,7 @@ typedef enum {
     GC032A_SCCB_ADDR   = 0x21,// 0x42 >> 1
     GC0308_SCCB_ADDR   = 0x21,// 0x42 >> 1
     BF3005_SCCB_ADDR   = 0x6E,
+    BF20A6_SCCB_ADDR   = 0x6E,
 } camera_sccb_addr_t;
 
 typedef enum {

tools/sdk/esp32/bin/bootloader_qio_40m.bin

@@ -1,16 +1,8 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #ifndef __ESP_ADC_CAL_H__
 #define __ESP_ADC_CAL_H__

tools/sdk/esp32/bin/bootloader_qio_80m.bin

@@ -33,6 +33,7 @@ typedef enum {
 #define CHIP_FEATURE_BLE            BIT(4)      //!< Chip has Bluetooth LE
 #define CHIP_FEATURE_BT             BIT(5)      //!< Chip has Bluetooth Classic
 #define CHIP_FEATURE_IEEE802154     BIT(6)      //!< Chip has IEEE 802.15.4
+#define CHIP_FEATURE_EMB_PSRAM      BIT(7)      //!< Chip has embedded psram
 
 /**
  * @brief The structure represents information about the chip

tools/sdk/esp32/bin/bootloader_qout_40m.bin

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,20 +22,6 @@ extern "C" {
  */
 typedef void (*esp_ipc_isr_func_t)(void* arg);
 
-/**
- * @brief Initialize the IPC ISR feature
- *
- * This function initializes the IPC ISR feature and must be called before any other esp_ipc_isr...() functions.
- * The IPC ISR feature allows for callbacks (written in assembly) to be run on a particular CPU in the context of a
- * High Priority Interrupt.
- *
- * - This function will register a High Priority Interrupt on each CPU. The priority of the interrupts is dependent on
- *   the CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL option.
- * - Callbacks written in assembly can then run in context of the registered High Priority Interrupts
- * - Callbacks can be executed by calling esp_ipc_isr_asm_call() or esp_ipc_isr_asm_call_blocking()
- */
-void esp_ipc_isr_init(void);
-
 /**
  * @brief Execute an assembly callback on the other CPU
  *

tools/sdk/esp32/bin/bootloader_qout_80m.bin

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -64,7 +64,7 @@ typedef struct {
         unsigned int hsync_idle_low: 1;  /*!< The hsync signal is low in IDLE state */
         unsigned int vsync_idle_low: 1;  /*!< The vsync signal is low in IDLE state */
         unsigned int de_idle_high: 1;    /*!< The de signal is high in IDLE state */
-        unsigned int pclk_active_neg: 1; /*!< The display will write data lines when there's a falling edge on PCLK */
+        unsigned int pclk_active_neg: 1; /*!< Whether the display data is clocked out at the falling edge of PCLK */
         unsigned int pclk_idle_high: 1;  /*!< The PCLK stays at high level in IDLE phase */
     } flags;
 } esp_lcd_rgb_timing_t;
@@ -92,6 +92,8 @@ typedef struct {
     lcd_clock_source_t clk_src;   /*!< Clock source for the RGB LCD peripheral */
     esp_lcd_rgb_timing_t timings; /*!< RGB timing parameters */
     size_t data_width;            /*!< Number of data lines */
+    size_t sram_trans_align;      /*!< Alignment for framebuffer that allocated in SRAM */
+    size_t psram_trans_align;     /*!< Alignment for framebuffer that allocated in PSRAM */
     int hsync_gpio_num;           /*!< GPIO used for HSYNC signal */
     int vsync_gpio_num;           /*!< GPIO used for VSYNC signal */
     int de_gpio_num;              /*!< GPIO used for DE signal, set to -1 if it's not used */

tools/sdk/esp32/include/config/sdkconfig.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -99,6 +99,13 @@ void phy_freq_mem_backup(bool backup_en, uint32_t *mem);
 void phy_bbpll_en_usb(bool en);
 #endif
 
+#if CONFIG_IDF_TARGET_ESP32S2
+/**
+ * @brief Phy version select for ESP32S2
+ */
+void phy_eco_version_sel(uint8_t chip_ver);
+#endif
+
 #ifdef __cplusplus
 }
 #endif

tools/sdk/esp32/include/esp32-camera/driver/include/sensor.h

@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #ifndef _ROM_RTC_H_
 #define _ROM_RTC_H_
@@ -124,7 +116,7 @@ _Static_assert((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "
 _Static_assert((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART");
 _Static_assert((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG");
 _Static_assert((soc_reset_reason_t)POWER_GLITCH_RESET == RESET_REASON_CORE_PWR_GLITCH, "POWER_GLITCH_RESET != RESET_REASON_CORE_PWR_GLITCH");
-_Static_assert((soc_reset_reason_t)JTAG_RESET == RESET_REASON_CPU_JTAG, "JTAG_RESET != RESET_REASON_CPU_JTAG");
+_Static_assert((soc_reset_reason_t)JTAG_RESET == RESET_REASON_CPU0_JTAG, "JTAG_RESET != RESET_REASON_CPU0_JTAG");
 
 typedef enum {
     NO_SLEEP        = 0,

tools/sdk/esp32/include/esp_adc_cal/include/esp_adc_cal.h

@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "sdkconfig.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef CONFIG_ESP_IPC_ISR_ENABLE
+
+/**
+ * @brief Initialize the IPC ISR feature, must be called for each CPU
+ *
+ * @note This function is called from ipc_task().
+ *
+ * This function initializes the IPC ISR feature and must be called before any other esp_ipc_isr...() functions.
+ * The IPC ISR feature allows for callbacks (written in assembly) to be run on a particular CPU in the context of a
+ * High Priority Interrupt.
+ *
+ * - This function will register a High Priority Interrupt for a CPU where it is called. The priority of the interrupts is dependent on
+ *   the CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL option.
+ * - Callbacks written in assembly can then run in context of the registered High Priority Interrupts
+ * - Callbacks can be executed by calling esp_ipc_isr_asm_call() or esp_ipc_isr_asm_call_blocking()
+ */
+void esp_ipc_isr_init(void);
+
+#endif // CONFIG_ESP_IPC_ISR_ENABLE
+
+#ifdef __cplusplus
+}
+#endif

tools/sdk/esp32/include/esp_hw_support/include/esp_chip_info.h

@@ -11,7 +11,7 @@
    Copyright (c) 2000-2005 Fred L. Drake, Jr. <[email protected]>
    Copyright (c) 2001-2002 Greg Stein <[email protected]>
    Copyright (c) 2002-2016 Karl Waclawek <[email protected]>
-   Copyright (c) 2016-2021 Sebastian Pipping <[email protected]>
+   Copyright (c) 2016-2022 Sebastian Pipping <[email protected]>
    Copyright (c) 2016      Cristian Rodríguez <[email protected]>
    Copyright (c) 2016      Thomas Beutlich <[email protected]>
    Copyright (c) 2017      Rhodri James <[email protected]>
@@ -1041,7 +1041,7 @@ XML_SetBillionLaughsAttackProtectionActivationThreshold(
 */
 #define XML_MAJOR_VERSION 2
 #define XML_MINOR_VERSION 4
-#define XML_MICRO_VERSION 1
+#define XML_MICRO_VERSION 3
 
 #ifdef __cplusplus
 }

tools/sdk/esp32/include/esp_ipc/include/esp_ipc_isr.h

@@ -63,7 +63,7 @@
 #define PACKAGE_NAME "expat"
 
 /* Define to the full name and version of this package. */
-#define PACKAGE_STRING "expat 2.2.5"
+#define PACKAGE_STRING "expat 2.4.3"
 
 /* Define to the one symbol short name of this package. */
 #define PACKAGE_TARNAME "expat"
@@ -72,13 +72,13 @@
 #define PACKAGE_URL ""
 
 /* Define to the version of this package. */
-#define PACKAGE_VERSION "2.2.5"
+#define PACKAGE_VERSION "2.4.3"
 
 /* Define to 1 if you have the ANSI C header files. */
 #define STDC_HEADERS 1
 
 /* Version number of package */
-#define VERSION "2.2.5"
+#define VERSION "2.4.3"
 
 /* whether byteorder is bigendian */
 /* #undef WORDS_BIGENDIAN */

tools/sdk/esp32/include/esp_lcd/include/esp_lcd_panel_rgb.h

@@ -22,6 +22,24 @@
 extern "C" {
 #endif
 
+#if __has_include("esp_check.h")
+#include "esp_check.h"
+
+#define MB_RETURN_ON_FALSE(a, err_code, tag, format, ...) ESP_RETURN_ON_FALSE(a, err_code, tag, format __VA_OPT__(,) __VA_ARGS__)
+
+#else
+
+// if cannot include esp_check then use custom check macro
+
+#define MB_RETURN_ON_FALSE(a, err_code, tag, format, ...) do {                                         \
+        if (!(a)) {                                                                              \
+            ESP_LOGE(tag, "%s(%d): " format, __FUNCTION__, __LINE__ __VA_OPT__(,) __VA_ARGS__);        \
+            return err_code;                                                                               \
+        }                                                                                                  \
+} while(0)
+
+#endif
+
 #define MB_CONTROLLER_STACK_SIZE            (CONFIG_FMB_CONTROLLER_STACK_SIZE)   // Stack size for Modbus controller
 #define MB_CONTROLLER_PRIORITY              (CONFIG_FMB_PORT_TASK_PRIO - 1)    // priority of MB controller task
 

tools/sdk/esp32/include/esp_phy/include/phy.h

@@ -25,6 +25,12 @@
 extern "C" {
 #endif
 
+#define MB_MASTER_CHECK(a, err_code, format, ...) MB_RETURN_ON_FALSE(a, err_code, TAG, format __VA_OPT__(,) __VA_ARGS__)
+
+#define MB_MASTER_ASSERT(con) do { \
+        if (!(con)) { ESP_LOGE(TAG, "assert errno:%d, errno_str: !(%s)", errno, strerror(errno)); assert(0 && #con); } \
+    } while (0)
+
 /*!
  * \brief Modbus descriptor table parameter type defines.
  */

tools/sdk/esp32/include/esp_rom/include/esp32h2/rom/rtc.h

@@ -28,6 +28,12 @@
 extern "C" {
 #endif
 
+#define MB_SLAVE_CHECK(a, err_code, format, ...) MB_RETURN_ON_FALSE(a, err_code, TAG, format __VA_OPT__(,) __VA_ARGS__)
+
+#define MB_SLAVE_ASSERT(con) do { \
+        if (!(con)) { ESP_LOGE(TAG, "assert errno:%d, errno_str: !(%s)", errno, strerror(errno)); assert(0 && #con); } \
+    } while (0)
+
 /**
  * @brief Parameter access event information type
  */