Merge pull request #3 from esp8266/master

Update

Author: Jason2866

README.md

@@ -135,3 +135,5 @@ ESP8266 core files are licensed under LGPL.
 [SoftwareSerial repo](https://github.com/plerup/espsoftwareserial)
 
 [Serial Monitor Arduino IDE plugin](https://github.com/mytrain/arduino-esp8266-serial-plugin) Original discussion [here](https://github.com/esp8266/Arduino/issues/1360), quick download [there](http://mytrain.fr/cms//images/mytrain/private/ESP8266SM.v3.zip).
+
+[FTP Client/Server Library](https://github.com/dplasa/FTPClientServer) 

bootloaders/eboot/eboot.c

@@ -12,7 +12,6 @@
 #include <string.h>
 #include "flash.h"
 #include "eboot_command.h"
-#include "spi_vendors.h"
 #include <uzlib.h>
 
 extern unsigned char _gzip_dict;
@@ -115,10 +114,12 @@ int uzlib_flash_read_cb(struct uzlib_uncomp *m)
 }
 
 unsigned char gzip_dict[32768];
+uint8_t buffer2[FLASH_SECTOR_SIZE]; // no room for this on the stack
 
 int copy_raw(const uint32_t src_addr,
              const uint32_t dst_addr,
-             const uint32_t size)
+             const uint32_t size,
+             const bool verify)
 {
     // require regions to be aligned
     if ((src_addr & 0xfff) != 0 ||
@@ -158,8 +159,10 @@ int copy_raw(const uint32_t src_addr,
 	gzip = true;
     }
     while (left > 0) {
-        if (SPIEraseSector(daddr/buffer_size)) {
-            return 2;
+        if (!verify) {
+           if (SPIEraseSector(daddr/buffer_size)) {
+               return 2;
+           }
         }
         if (!gzip) {
             if (SPIRead(saddr, buffer, buffer_size)) {
@@ -179,8 +182,17 @@ int copy_raw(const uint32_t src_addr,
                 buffer[i] = 0xff;
             }
         }
-        if (SPIWrite(daddr, buffer, buffer_size)) {
-            return 4;
+        if (verify) {
+            if (SPIRead(daddr, buffer2, buffer_size)) {
+                return 4;
+            }
+            if (memcmp(buffer, buffer2, buffer_size)) {
+                return 9;
+            }
+        } else {
+            if (SPIWrite(daddr, buffer, buffer_size)) {
+                return 4;
+            }
         }
         saddr += buffer_size;
         daddr += buffer_size;
@@ -190,29 +202,6 @@ int copy_raw(const uint32_t src_addr,
     return 0;
 }
 
-//#define XMC_SUPPORT
-#ifdef XMC_SUPPORT
-// Define a few SPI0 registers we need access to
-#define ESP8266_REG(addr) *((volatile uint32_t *)(0x60000000+(addr)))
-#define SPI0CMD ESP8266_REG(0x200)
-#define SPI0CLK ESP8266_REG(0x218)
-#define SPI0C   ESP8266_REG(0x208)
-#define SPI0W0  ESP8266_REG(0x240)
-
-#define SPICMDRDID (1 << 28)
-
-/* spi_flash_get_id()
-   Returns the flash chip ID - same as the SDK function.
-   We need our own version as the SDK isn't available here.
- */
-uint32_t __attribute__((noinline)) spi_flash_get_id() {
-  SPI0W0=0;
-  SPI0CMD=SPICMDRDID;
-  while (SPI0CMD) {}
-  return SPI0W0;
-}
-#endif // XMC_SUPPORT
-
 int main()
 {
     int res = 9;
@@ -235,47 +224,20 @@ int main()
     if (cmd.action == ACTION_COPY_RAW) {
         ets_putc('c'); ets_putc('p'); ets_putc(':');
 
-#ifdef XMC_SUPPORT
-        // save the flash access speed registers
-        uint32_t spi0clk = SPI0CLK;
-        uint32_t spi0c   = SPI0C;
-        
-        uint32_t vendor  = spi_flash_get_id() & 0x000000ff;
-        if (vendor == SPI_FLASH_VENDOR_XMC) {
-           uint32_t flashinfo=0;
-           if (SPIRead(0, &flashinfo, 4)) {
-              // failed to read the configured flash speed.
-              // Do not change anything,
-           } else {
-              // select an appropriate flash speed
-              // Register values are those used by ROM
-              switch ((flashinfo >> 24) & 0x0f) {
-                 case 0x0: // 40MHz, slow to 20
-                 case 0x1: // 26MHz, slow to 20
-                      SPI0CLK = 0x00003043;
-                      SPI0C   = 0x00EAA313;
-                      break;
-                 case 0x2: // 20MHz, no change
-                      break;
-                 case 0xf: // 80MHz, slow to 26
-                      SPI0CLK = 0x00002002;
-                      SPI0C   = 0x00EAA202;
-                      break;
-                 default:
-                      break;
-              }
-           }
-        }
-#endif // XMC_SUPPORT
         ets_wdt_disable();
-        res = copy_raw(cmd.args[0], cmd.args[1], cmd.args[2]);
+        res = copy_raw(cmd.args[0], cmd.args[1], cmd.args[2], false);
         ets_wdt_enable();
-        
-#ifdef XMC_SUPPORT
-        // restore the saved flash access speed registers
-        SPI0CLK = spi0clk;
-        SPI0C   = spi0c;
-#endif        
+
+        ets_putc('0'+res); ets_putc('\n');
+
+        // Verify the copy
+        ets_putc('c'); ets_putc('m'); ets_putc('p'); ets_putc(':');
+        if (res == 0) {
+            ets_wdt_disable();
+            res = copy_raw(cmd.args[0], cmd.args[1], cmd.args[2], true);
+            ets_wdt_enable();
+            }
+
         ets_putc('0'+res); ets_putc('\n');
         if (res == 0) {
             cmd.action = ACTION_LOAD_APP;

bootloaders/eboot/eboot.elf

@@ -64,7 +64,7 @@ class CallBackList
 	}
 
     template<typename... Args>
-    void execute(Args... params) {
+    int execute(Args... params) {
         for(auto it = std::begin(callBackEventList); it != std::end(callBackEventList); ) {
         	CallBackHandler &handler = *it;
             if (handler->allowRemove() && handler.unique()) {
@@ -75,6 +75,7 @@ class CallBackList
                 ++it;
             }
         }
+        return callBackEventList.size();
     }
 };
 

cores/esp8266/CallBackList.h

@@ -29,20 +29,28 @@ void EspClass::getHeapStats(uint32_t* hfree, uint16_t* hmax, uint8_t* hfrag)
     // Having getFreeHeap()=sum(hole-size), fragmentation is given by
     // 100 * (1 - sqrt(sum(hole-size²)) / sum(hole-size))
 
-    umm_info(NULL, 0);
+    umm_info(NULL, false);
     uint8_t block_size = umm_block_size();
-    uint32_t fh = ummHeapInfo.freeBlocks * block_size;
     if (hfree)
-        *hfree = fh;
+        *hfree = ummHeapInfo.freeBlocks * block_size;
     if (hmax)
-        *hmax = ummHeapInfo.maxFreeContiguousBlocks * block_size;
-    if (hfrag)
-        *hfrag = 100 - (sqrt32(ummHeapInfo.freeSize2) * 100) / fh;
+        *hmax = (uint16_t)ummHeapInfo.maxFreeContiguousBlocks * block_size;
+    if (hfrag) {
+      if (ummHeapInfo.freeBlocks) {
+        *hfrag = 100 - (sqrt32(ummHeapInfo.freeBlocksSquared) * 100) / ummHeapInfo.freeBlocks;
+      } else {
+        *hfrag = 0;
+      }
+    }
 }
 
 uint8_t EspClass::getHeapFragmentation()
 {
+#ifdef UMM_INLINE_METRICS
+    return (uint8_t)umm_fragmentation_metric();
+#else
     uint8_t hfrag;
     getHeapStats(nullptr, nullptr, &hfrag);
     return hfrag;
+#endif
 }

cores/esp8266/Esp-frag.cpp

@@ -92,6 +92,18 @@ static void ets_printf_P(const char *str, ...) {
     }
 }
 
+static void cut_here() {
+    ets_putc('\n');
+    for (auto i = 0; i < 15; i++ ) {
+        ets_putc('-');
+    }
+    ets_printf_P(PSTR(" CUT HERE FOR EXCEPTION DECODER "));
+    for (auto i = 0; i < 15; i++ ) {
+        ets_putc('-');
+    }
+    ets_putc('\n');
+}
+
 void __wrap_system_restart_local() {
     register uint32_t sp asm("a1");
     uint32_t sp_dump = sp;
@@ -113,6 +125,8 @@ void __wrap_system_restart_local() {
 
     ets_install_putc1(&uart_write_char_d);
 
+    cut_here();
+
     if (s_panic_line) {
         ets_printf_P(PSTR("\nPanic %S:%d %S"), s_panic_file, s_panic_line, s_panic_func);
         if (s_panic_what) {
@@ -193,6 +207,8 @@ void __wrap_system_restart_local() {
 #endif
     }
 
+    cut_here();
+
     custom_crash_callback( &rst_info, sp_dump + offset, stack_end );
 
     ets_delay_us(10000);

cores/esp8266/core_esp8266_postmortem.cpp

@@ -52,7 +52,7 @@ static SpiOpResult PRECACHE_ATTR
 _SPICommand(volatile uint32_t spiIfNum,
             uint32_t spic,uint32_t spiu,uint32_t spiu1,uint32_t spiu2,
             uint32_t *data,uint32_t writeWords,uint32_t readWords)
-{ 
+{
   if (spiIfNum>1)
      return SPI_RESULT_ERR;
 
@@ -69,8 +69,11 @@ _SPICommand(volatile uint32_t spiIfNum,
   volatile SpiFlashChip *fchip=flashchip;
   volatile uint32_t spicmdusr=SPICMDUSR;
 
+  uint32_t saved_ps=0;
+
   if (!spiIfNum) {
-     // Only need to precache when using SPI0
+     // Only need to disable interrupts and precache when using SPI0
+     saved_ps = xt_rsil(15);
      PRECACHE_START();
      Wait_SPI_Idlep((SpiFlashChip *)fchip);
   }
@@ -116,6 +119,9 @@ _SPICommand(volatile uint32_t spiIfNum,
   SPIREG(SPI0C) = oldSPI0C;
 
   PRECACHE_END();
+  if (!spiIfNum) {
+      xt_wsr_ps(saved_ps);
+  }
   return (timeout>0 ? SPI_RESULT_OK : SPI_RESULT_TIMEOUT);
 }
 

cores/esp8266/core_esp8266_spi_utils.cpp

@@ -20,7 +20,7 @@ extern "C" {
 #undef realloc
 #undef free
 
-#elif defined(DEBUG_ESP_OOM)
+#elif defined(DEBUG_ESP_OOM) || defined(UMM_INTEGRITY_CHECK)
 #define UMM_MALLOC(s)           umm_malloc(s)
 #define UMM_CALLOC(n,s)         umm_calloc(n,s)
 #define UMM_REALLOC_FL(p,s,f,l) umm_realloc(p,s)
@@ -314,7 +314,7 @@ size_t ICACHE_RAM_ATTR xPortWantedSizeAlign(size_t size)
 
 void system_show_malloc(void)
 {
-    umm_info(NULL, 1);
+    umm_info(NULL, true);
 }
 
 };

cores/esp8266/heap.cpp

@@ -49,6 +49,9 @@ What spiffs does not:
  - Presently, it does not detect or handle bad blocks.
  - One configuration, one binary. There's no generic spiffs binary that handles all types of configurations.
 
+## NOTICE
+
+0.4.0 is under construction. This is a full rewrite and will change the underlying structure. Hence, it will not be compatible with earlier versions of the filesystem. The API is the same, with minor modifications. Some config flags will be removed (as they are mandatory in 0.4.0) and some features might fall away until 0.4.1. If you have any worries or questions, it can be discussed in issue [#179](https://github.com/pellepl/spiffs/issues/179)
 
 ## MORE INFO 
 

cores/esp8266/spiffs/README.md

@@ -163,11 +163,17 @@ static s32_t spiffs_delete_obj_lazy(spiffs *fs, spiffs_obj_id obj_id) {
     return SPIFFS_OK;
   }
   SPIFFS_CHECK_RES(res);
-  u8_t flags = 0xff & ~SPIFFS_PH_FLAG_IXDELE;
+  u8_t flags = 0xff;
+#if SPIFFS_NO_BLIND_WRITES
+  res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU | SPIFFS_OP_C_READ,
+      0, SPIFFS_PAGE_TO_PADDR(fs, objix_hdr_pix) + offsetof(spiffs_page_header, flags),
+      sizeof(flags), &flags);
+  SPIFFS_CHECK_RES(res);
+#endif
+  flags &= ~SPIFFS_PH_FLAG_IXDELE;
   res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_LU | SPIFFS_OP_C_UPDT,
       0, SPIFFS_PAGE_TO_PADDR(fs, objix_hdr_pix) + offsetof(spiffs_page_header, flags),
-      sizeof(u8_t),
-      (u8_t *)&flags);
+      sizeof(flags), &flags);
   return res;
 }
 
@@ -425,10 +431,17 @@ static s32_t spiffs_lookup_check_validate(spiffs *fs, spiffs_obj_id lu_obj_id, s
           // just finalize
           SPIFFS_CHECK_DBG("LU: FIXUP: unfinalized page is referred, finalizing\n");
           CHECK_CB(fs, SPIFFS_CHECK_LOOKUP, SPIFFS_CHECK_FIX_LOOKUP, p_hdr->obj_id, p_hdr->span_ix);
-          u8_t flags = 0xff & ~SPIFFS_PH_FLAG_FINAL;
+          u8_t flags = 0xff;
+#if SPIFFS_NO_BLIND_WRITES
+          res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_READ,
+              0, SPIFFS_PAGE_TO_PADDR(fs, cur_pix) + offsetof(spiffs_page_header, flags),
+              sizeof(flags), &flags);
+          SPIFFS_CHECK_RES(res);
+#endif
+          flags &= ~SPIFFS_PH_FLAG_FINAL;
           res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_UPDT,
               0, SPIFFS_PAGE_TO_PADDR(fs, cur_pix) + offsetof(spiffs_page_header, flags),
-              sizeof(u8_t), (u8_t*)&flags);
+              sizeof(flags), &flags);
         }
       }
     }

cores/esp8266/spiffs/spiffs_check.cpp

@@ -326,6 +326,17 @@ typedef uint8_t u8_t;
 #define SPIFFS_IX_MAP                         1
 #endif
 
+// By default SPIFFS in some cases relies on the property of NOR flash that bits
+// cannot be set from 0 to 1 by writing and that controllers will ignore such
+// bit changes. This results in fewer reads as SPIFFS can in some cases perform
+// blind writes, with all bits set to 1 and only those it needs reset set to 0.
+// Most of the chips and controllers allow this behavior, so the default is to
+// use this technique. If your controller is one of the rare ones that don't,
+// turn this option on and SPIFFS will perform a read-modify-write instead.
+#ifndef SPIFFS_NO_BLIND_WRITES
+#define SPIFFS_NO_BLIND_WRITES                0
+#endif
+
 // Set SPIFFS_TEST_VISUALISATION to non-zero to enable SPIFFS_vis function
 // in the api. This function will visualize all filesystem using given printf
 // function.
@@ -354,11 +365,20 @@ typedef uint8_t u8_t;
 #endif
 #endif
 
+#ifndef SPIFFS_SECURE_ERASE
+#define SPIFFS_SECURE_ERASE 0
+#endif
+
 // Types depending on configuration such as the amount of flash bytes
 // given to spiffs file system in total (spiffs_file_system_size),
 // the logical block size (log_block_size), and the logical page size
 // (log_page_size)
+//
+// Set SPIFFS_TYPES_OVERRIDE if you wish to have your own
+// definitions for these types (for example, if you want them
+// to be u32_t)
 
+#ifndef SPIFFS_TYPES_OVERRIDE
 // Block index type. Make sure the size of this type can hold
 // the highest number of all blocks - i.e. spiffs_file_system_size / log_block_size
 typedef u16_t spiffs_block_ix;
@@ -373,5 +393,6 @@ typedef u16_t spiffs_obj_id;
 // hold the largest possible span index on the system -
 // i.e. (spiffs_file_system_size / log_page_size) - 1
 typedef u16_t spiffs_span_ix;
+#endif
 
 #endif /* SPIFFS_CONFIG_H_ */