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Add riscv32 to asm test
1 parent a8e78b9 commit 3507fef

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-5
lines changed

‎tests/asm-test/asm/riscv32imac-unknown-none-elf/atomic_memcpy_load_align1

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‎tests/asm-test/asm/riscv32imac-unknown-none-elf/atomic_memcpy_load_align16

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asm_test::atomic_memcpy_load_align16::acquire:
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lw a7, 24(a1)
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lw t0, 20(a1)
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lw a5, 16(a1)
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lw a2, 12(a1)
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lw a3, 8(a1)
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lw a4, 4(a1)
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lw a1, 0(a1)
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sw a1, 0(a0)
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sw a4, 4(a0)
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sw a3, 8(a0)
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sw a2, 12(a0)
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sw a5, 16(a0)
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sw t0, 20(a0)
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sw a7, 24(a0)
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sw a6, 28(a0)
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fence r, rw
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ret
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asm_test::atomic_memcpy_load_align16::read_volatile_acquire_fence:
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lw a7, 24(a1)
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lw t0, 20(a1)
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lw a5, 16(a1)
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lw a2, 12(a1)
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lw a3, 8(a1)
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lw a4, 4(a1)
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lw a1, 0(a1)
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sw a1, 0(a0)
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sw a4, 4(a0)
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sw a3, 8(a0)
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sw a2, 12(a0)
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sw a5, 16(a0)
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sw t0, 20(a0)
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sw a7, 24(a0)
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sw a6, 28(a0)
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fence r, rw
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ret

‎tests/asm-test/asm/riscv32imac-unknown-none-elf/atomic_memcpy_load_align2

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asm_test::atomic_memcpy_load_align2::acquire:
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sw ra, 44(sp)
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andi a2, a1, 3
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beqz a2, .LBB4_2
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lh a2, 0(a1)
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sh a2, 12(sp)
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lw a2, 2(a1)
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sh a2, 14(sp)
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srli a2, a2, 16
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sh a2, 16(sp)
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lw a2, 6(a1)
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sh a2, 18(sp)
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srli a2, a2, 16
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sh a2, 20(sp)
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lw a2, 10(a1)
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sh a2, 22(sp)
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srli a2, a2, 16
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sh a2, 24(sp)
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lw a2, 14(a1)
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sh a2, 26(sp)
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srli a2, a2, 16
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sh a2, 28(sp)
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lw a2, 18(a1)
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sh a2, 30(sp)
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srli a2, a2, 16
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sh a2, 32(sp)
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lw a2, 22(a1)
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sh a2, 34(sp)
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srli a2, a2, 16
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sh a2, 36(sp)
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lw a2, 26(a1)
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sh a2, 38(sp)
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srli a2, a2, 16
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sh a2, 40(sp)
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lh a1, 30(a1)
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sh a1, 42(sp)
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j .LBB4_3
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.LBB4_2:
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lw a2, 0(a1)
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sw a2, 12(sp)
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lw a2, 4(a1)
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sw a2, 16(sp)
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lw a2, 8(a1)
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sw a2, 20(sp)
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lw a2, 12(a1)
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sw a2, 24(sp)
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lw a2, 16(a1)
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sw a2, 28(sp)
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lw a2, 20(a1)
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sw a2, 32(sp)
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lw a2, 24(a1)
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sw a2, 36(sp)
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lw a1, 28(a1)
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sw a1, 40(sp)
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.LBB4_3:
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addi a1, sp, 12
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addi a2, zero, 32
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call memcpy@plt
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fence r, rw
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lw ra, 44(sp)
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addi sp, sp, 48
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ret
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.LBB6_2:
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lw a1, 32(sp)
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sw a1, 0(a0)
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lw a1, 36(sp)
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sw a1, 4(a0)
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lw a1, 40(sp)
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sw a1, 8(a0)
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lw a1, 44(sp)
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sw a1, 12(a0)
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lw a1, 48(sp)
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sw a1, 16(a0)
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lw a1, 52(sp)
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sw a1, 20(a0)
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lw a1, 56(sp)
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sw a1, 24(a0)
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lw a1, 60(sp)
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sw a1, 28(a0)
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addi sp, sp, 64
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ret
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asm_test::atomic_memcpy_load_align2::read_volatile_acquire_fence:
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sw s0, 12(sp)
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sw s1, 8(sp)
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lh a6, 30(a1)
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lh a7, 28(a1)
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lh t0, 26(a1)
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lh t1, 24(a1)
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lh t2, 22(a1)
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lh t3, 20(a1)
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lh t4, 18(a1)
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lh t5, 16(a1)
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lh t6, 14(a1)
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lh a3, 12(a1)
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lh a4, 10(a1)
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lh a5, 8(a1)
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lh a2, 6(a1)
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lh s0, 4(a1)
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lh s1, 2(a1)
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lh a1, 0(a1)
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sh a1, 0(a0)
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sh s1, 2(a0)
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sh s0, 4(a0)
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sh a2, 6(a0)
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sh a5, 8(a0)
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sh a4, 10(a0)
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sh a3, 12(a0)
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sh t6, 14(a0)
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sh t5, 16(a0)
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sh t4, 18(a0)
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sh t3, 20(a0)
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sh t2, 22(a0)
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sh t1, 24(a0)
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sh t0, 26(a0)
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sh a7, 28(a0)
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sh a6, 30(a0)
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fence r, rw
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lw s1, 8(sp)
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lw s0, 12(sp)
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addi sp, sp, 16
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ret
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.LBB6_2:
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lw a1, 32(sp)
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sw a1, 0(a0)
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lw a1, 36(sp)
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sw a1, 4(a0)
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lw a1, 40(sp)
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sw a1, 8(a0)
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lw a1, 44(sp)
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sw a1, 12(a0)
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lw a1, 48(sp)
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sw a1, 16(a0)
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lw a1, 52(sp)
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sw a1, 20(a0)
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lw a1, 56(sp)
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sw a1, 24(a0)
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lw a1, 60(sp)
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sw a1, 28(a0)
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addi sp, sp, 64
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ret

‎tests/asm-test/asm/riscv32imac-unknown-none-elf/atomic_memcpy_load_align4

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asm_test::atomic_memcpy_load_align4::acquire:
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lw a7, 24(a1)
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lw t0, 20(a1)
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lw a5, 16(a1)
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lw a2, 12(a1)
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lw a3, 8(a1)
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lw a4, 4(a1)
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lw a1, 0(a1)
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sw a1, 0(a0)
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sw a4, 4(a0)
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sw a3, 8(a0)
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sw a2, 12(a0)
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sw a5, 16(a0)
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sw t0, 20(a0)
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sw a7, 24(a0)
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sw a6, 28(a0)
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fence r, rw
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ret
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asm_test::atomic_memcpy_load_align4::read_volatile_acquire_fence:
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lw a7, 24(a1)
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lw t0, 20(a1)
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lw a5, 16(a1)
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lw a2, 12(a1)
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lw a3, 8(a1)
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lw a4, 4(a1)
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lw a1, 0(a1)
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sw a1, 0(a0)
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sw a4, 4(a0)
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sw a3, 8(a0)
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sw a2, 12(a0)
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sw a5, 16(a0)
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sw t0, 20(a0)
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sw a7, 24(a0)
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sw a6, 28(a0)
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fence r, rw
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ret

‎tests/asm-test/asm/riscv32imac-unknown-none-elf/atomic_memcpy_load_align8

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asm_test::atomic_memcpy_load_align8::acquire:
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lw a7, 24(a1)
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lw t0, 20(a1)
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lw a5, 16(a1)
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lw a2, 12(a1)
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lw a3, 8(a1)
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lw a4, 4(a1)
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lw a1, 0(a1)
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sw a1, 0(a0)
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sw a4, 4(a0)
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sw a3, 8(a0)
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sw a2, 12(a0)
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sw a5, 16(a0)
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sw t0, 20(a0)
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sw a7, 24(a0)
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sw a6, 28(a0)
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fence r, rw
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ret
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asm_test::atomic_memcpy_load_align8::read_volatile_acquire_fence:
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lw a7, 24(a1)
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lw t0, 20(a1)
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lw a5, 16(a1)
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lw a2, 12(a1)
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lw a3, 8(a1)
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lw a4, 4(a1)
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lw a1, 0(a1)
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sw a1, 0(a0)
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sw a4, 4(a0)
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sw a3, 8(a0)
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sw a2, 12(a0)
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sw a5, 16(a0)
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sw t0, 20(a0)
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sw a7, 24(a0)
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sw a6, 28(a0)
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fence r, rw
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ret

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