diff --git a/.github/workflows/build-stm.yml b/.github/workflows/build-stm.yml index 4de13860..fdb46f06 100644 --- a/.github/workflows/build-stm.yml +++ b/.github/workflows/build-stm.yml @@ -17,7 +17,7 @@ jobs: fail-fast: false matrix: example: [stm32-blink] - swift: [swift-DEVELOPMENT-SNAPSHOT-2024-12-04-a] + swift: [swift-DEVELOPMENT-SNAPSHOT-2025-03-04-a] steps: - name: Checkout repo diff --git a/Tools/SVDs/stm32f7x6.patched.svd b/Tools/SVDs/stm32f7x6.patched.svd new file mode 100644 index 00000000..db7cd9aa --- /dev/null +++ b/Tools/SVDs/stm32f7x6.patched.svd @@ -0,0 +1,54193 @@ + + + STM32F7x6 + 1.6 + STM32F7x6 + + CM7 + r0p1 + little + true + true + 4 + false + + 8 + 32 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RNG + Random number generator + RNG + 0x50060800 + + 0x0 + 0x400 + registers + + + HASH_RNG + Hash and Rng global interrupt + 80 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + IE + Interrupt enable + 3 + 1 + + + RNGEN + Random number generator enable + 2 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + 0x00000000 + + + SEIS + Seed error interrupt status + 6 + 1 + read-write + + + CEIS + Clock error interrupt status + 5 + 1 + read-write + + + SECS + Seed error current status + 2 + 1 + read-only + + + CECS + Clock error current status + 1 + 1 + read-only + + + DRDY + Data ready + 0 + 1 + read-only + + + + + DR + DR + data register + 0x8 + 0x20 + read-only + 0x00000000 + + + RNDATA + Random data + 0 + 32 + + + + + + + HASH + Hash processor + HASH + 0x50060400 + + 0x0 + 0x400 + registers + + + + CR + CR + control register + 0x0 + 0x20 + 0x00000000 + + + INIT + Initialize message digest calculation + 2 + 1 + write-only + + + DMAE + DMA enable + 3 + 1 + read-write + + + DATATYPE + Data type selection + 4 + 2 + read-write + + + MODE + Mode selection + 6 + 1 + read-write + + + ALGO0 + Algorithm selection + 7 + 1 + read-write + + + NBW + Number of words already pushed + 8 + 4 + read-only + + + DINNE + DIN not empty + 12 + 1 + read-only + + + MDMAT + Multiple DMA Transfers + 13 + 1 + read-write + + + LKEY + Long key selection + 16 + 1 + read-write + + + ALGO1 + ALGO + 18 + 1 + read-write + + + + + DIN + DIN + data input register + 0x4 + 0x20 + read-write + 0x00000000 + + + DATAIN + Data input + 0 + 32 + + + + + STR + STR + start register + 0x8 + 0x20 + 0x00000000 + + + DCAL + Digest calculation + 8 + 1 + write-only + + + NBLW + Number of valid bits in the last word of the message + 0 + 5 + read-write + + + + + 5 + 0x4 + 0-4 + HR%s + HR0 + digest registers + 0xC + 0x20 + read-only + 0x00000000 + + + H + H0 + 0 + 32 + + + + + IMR + IMR + interrupt enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + DCIE + Digest calculation completion interrupt enable + 1 + 1 + + + DINIE + Data input interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x24 + 0x20 + 0x00000001 + + + BUSY + Busy bit + 3 + 1 + read-only + + + DMAS + DMA Status + 2 + 1 + read-only + + + DCIS + Digest calculation completion interrupt status + 1 + 1 + read-write + + + DINIS + Data input interrupt status + 0 + 1 + read-write + + + + + 54 + 0x4 + 0-53 + CSR%s + CSR0 + context swap registers + 0xF8 + 0x20 + read-write + 0x00000000 + + + CSR + CSR0 + 0 + 32 + + + + + 8 + 0x4 + 0-7 + HASH_HR%s + HASH_HR0 + HASH digest register + 0x310 + 0x20 + read-only + 0x00000000 + + + H + H0 + 0 + 32 + + + + + + + CRYP + Cryptographic processor + CRYP + 0x50060000 + + 0x0 + 0x400 + registers + + + CRYP + CRYP crypto global interrupt + 79 + + + + CR + CR + control register + 0x0 + 0x20 + 0x00000000 + + + ALGODIR + Algorithm direction + 2 + 1 + read-write + + + ALGOMODE0 + Algorithm mode + 3 + 3 + read-write + + + DATATYPE + Data type selection + 6 + 2 + read-write + + + KEYSIZE + Key size selection (AES mode only) + 8 + 2 + read-write + + + FFLUSH + FIFO flush + 14 + 1 + write-only + + + CRYPEN + Cryptographic processor enable + 15 + 1 + read-write + + + GCM_CCMPH + GCM_CCMPH + 16 + 2 + read-write + + + ALGOMODE3 + ALGOMODE + 19 + 1 + read-write + + + + + SR + SR + status register + 0x4 + 0x20 + read-only + 0x00000003 + + + BUSY + Busy bit + 4 + 1 + + + OFFU + Output FIFO full + 3 + 1 + + + OFNE + Output FIFO not empty + 2 + 1 + + + IFNF + Input FIFO not full + 1 + 1 + + + IFEM + Input FIFO empty + 0 + 1 + + + + + DIN + DIN + data input register + 0x8 + 0x20 + read-write + 0x00000000 + + + DATAIN + Data input + 0 + 32 + + + + + DOUT + DOUT + data output register + 0xC + 0x20 + read-only + 0x00000000 + + + DATAOUT + Data output + 0 + 32 + + + + + DMACR + DMACR + DMA control register + 0x10 + 0x20 + read-write + 0x00000000 + + + DOEN + DMA output enable + 1 + 1 + + + DIEN + DMA input enable + 0 + 1 + + + + + IMSCR + IMSCR + interrupt mask set/clear register + 0x14 + 0x20 + read-write + 0x00000000 + + + OUTIM + Output FIFO service interrupt mask + 1 + 1 + + + INIM + Input FIFO service interrupt mask + 0 + 1 + + + + + RISR + RISR + raw interrupt status register + 0x18 + 0x20 + read-only + 0x00000001 + + + OUTRIS + Output FIFO service raw interrupt status + 1 + 1 + + + INRIS + Input FIFO service raw interrupt status + 0 + 1 + + + + + MISR + MISR + masked interrupt status register + 0x1C + 0x20 + read-only + 0x00000000 + + + OUTMIS + Output FIFO service masked interrupt status + 1 + 1 + + + INMIS + Input FIFO service masked interrupt status + 0 + 1 + + + + + 4 + 0x8 + 0-3 + KEY%s + Cluster KEY%s, containing K?LR, K?RR + 0x20 + + KLR + K0LR + key registers + 0x0 + 0x20 + write-only + 0x00000000 + + + b2 + b224 + 0 + 32 + + + + + KRR + K0RR + key registers + 0x4 + 0x20 + write-only + 0x00000000 + + + b + b192 + 0 + 32 + + + + + + 2 + 0x8 + 0-1 + INIT%s + Cluster INIT%s, containing IV?LR, IV?RR + 0x40 + + IVLR + IV0LR + initialization vector registers + 0x0 + 0x20 + read-write + 0x00000000 + + + IV + IV31 + 0 + 32 + + + + + IVRR + IV0RR + initialization vector registers + 0x4 + 0x20 + read-write + 0x00000000 + + + IV + IV63 + 0 + 32 + + + + + + 8 + 0x4 + 0-7 + CSGCMCCM%sR + CSGCMCCM0R + context swap register + 0x50 + 0x20 + read-write + 0x00000000 + + + CSGCMCCM0R + CSGCMCCM0R + 0 + 32 + + + + + 8 + 0x4 + 0-7 + CSGCM%sR + CSGCM0R + context swap register + 0x70 + 0x20 + read-write + 0x00000000 + + + CSGCMR + CSGCM0R + 0 + 32 + + + + + + + DCMI + Digital camera interface + DCMI + 0x50050000 + + 0x0 + 0x400 + registers + + + DCMI + DCMI global interrupt + 78 + + + + CR + CR + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + ENABLE + DCMI enable + 14 + 1 + + + EDM + Extended data mode + 10 + 2 + + + FCRC + Frame capture rate control + 8 + 2 + + + VSPOL + Vertical synchronization polarity + 7 + 1 + + + HSPOL + Horizontal synchronization polarity + 6 + 1 + + + PCKPOL + Pixel clock polarity + 5 + 1 + + + ESS + Embedded synchronization select + 4 + 1 + + + JPEG + JPEG format + 3 + 1 + + + CROP + Crop feature + 2 + 1 + + + CM + Capture mode + 1 + 1 + + + CAPTURE + Capture enable + 0 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + read-only + 0x00000000 + + + FNE + FIFO not empty + 2 + 1 + + + VSYNC + VSYNC + 1 + 1 + + + HSYNC + HSYNC + 0 + 1 + + + + + RIS + RIS + raw interrupt status register + 0x8 + 0x20 + read-only + 0x00000000 + + + LINE_RIS + Line raw interrupt status + 4 + 1 + + + VSYNC_RIS + VSYNC raw interrupt status + 3 + 1 + + + ERR_RIS + Synchronization error raw interrupt status + 2 + 1 + + + OVR_RIS + Overrun raw interrupt status + 1 + 1 + + + FRAME_RIS + Capture complete raw interrupt status + 0 + 1 + + + + + IER + IER + interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + LINE_IE + Line interrupt enable + 4 + 1 + + + VSYNC_IE + VSYNC interrupt enable + 3 + 1 + + + ERR_IE + Synchronization error interrupt enable + 2 + 1 + + + OVR_IE + Overrun interrupt enable + 1 + 1 + + + FRAME_IE + Capture complete interrupt enable + 0 + 1 + + + + + MIS + MIS + masked interrupt status register + 0x10 + 0x20 + read-only + 0x00000000 + + + LINE_MIS + Line masked interrupt status + 4 + 1 + + + VSYNC_MIS + VSYNC masked interrupt status + 3 + 1 + + + ERR_MIS + Synchronization error masked interrupt status + 2 + 1 + + + OVR_MIS + Overrun masked interrupt status + 1 + 1 + + + FRAME_MIS + Capture complete masked interrupt status + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x14 + 0x20 + write-only + 0x00000000 + + + LINE_ISC + line interrupt status clear + 4 + 1 + + + VSYNC_ISC + Vertical synch interrupt status clear + 3 + 1 + + + ERR_ISC + Synchronization error interrupt status clear + 2 + 1 + + + OVR_ISC + Overrun interrupt status clear + 1 + 1 + + + FRAME_ISC + Capture complete interrupt status clear + 0 + 1 + + + + + ESCR + ESCR + embedded synchronization code register + 0x18 + 0x20 + read-write + 0x00000000 + + + FEC + Frame end delimiter code + 24 + 8 + + + LEC + Line end delimiter code + 16 + 8 + + + LSC + Line start delimiter code + 8 + 8 + + + FSC + Frame start delimiter code + 0 + 8 + + + + + ESUR + ESUR + embedded synchronization unmask register + 0x1C + 0x20 + read-write + 0x00000000 + + + FEU + Frame end delimiter unmask + 24 + 8 + + + LEU + Line end delimiter unmask + 16 + 8 + + + LSU + Line start delimiter unmask + 8 + 8 + + + FSU + Frame start delimiter unmask + 0 + 8 + + + + + CWSTRT + CWSTRT + crop window start + 0x20 + 0x20 + read-write + 0x00000000 + + + VST + Vertical start line count + 16 + 13 + + + HOFFCNT + Horizontal offset count + 0 + 14 + + + + + CWSIZE + CWSIZE + crop window size + 0x24 + 0x20 + read-write + 0x00000000 + + + VLINE + Vertical line count + 16 + 14 + + + CAPCNT + Capture count + 0 + 14 + + + + + DR + DR + data register + 0x28 + 0x20 + read-only + 0x00000000 + + + Byte3 + Data byte 3 + 24 + 8 + + + Byte2 + Data byte 2 + 16 + 8 + + + Byte1 + Data byte 1 + 8 + 8 + + + Byte0 + Data byte 0 + 0 + 8 + + + + + + + FMC + Flexible memory controller + FSMC + 0xA0000000 + + 0x0 + 0x1000 + registers + + + FMC + FMC global interrupt + 48 + + + + BCR1 + BCR1 + SRAM/NOR-Flash chip-select control register 1 + 0x0 + 0x20 + read-write + 0x000030D0 + + + CCLKEN + CCLKEN + 20 + 1 + + CCLKEN + read-write + + Disabled + The FMC_CLK is generated continuously during asynchronous and synchronous access. The FMC_CLK clock is activated when the CCLKEN is set + 0 + + + Enabled + The FMC_CLK is only generated during the synchronous memory access (read/write transaction) + 1 + + + + + CBURSTRW + CBURSTRW + 19 + 1 + + CBURSTRW + read-write + + Disabled + Write operations are always performed in asynchronous mode + 0 + + + Enabled + Write operations are performed in synchronous mode + 1 + + + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + ASYNCWAIT + read-write + + Disabled + Wait signal not used in asynchronous mode + 0 + + + Enabled + Wait signal used even in asynchronous mode + 1 + + + + + EXTMOD + EXTMOD + 14 + 1 + + EXTMOD + read-write + + Disabled + Values inside the FMC_BWTR are not taken into account + 0 + + + Enabled + Values inside the FMC_BWTR are taken into account + 1 + + + + + WAITEN + WAITEN + 13 + 1 + + WAITEN + read-write + + Disabled + Values inside the FMC_BWTR are taken into account + 0 + + + Enabled + NWAIT signal enabled + 1 + + + + + WREN + WREN + 12 + 1 + + WREN + read-write + + Disabled + Write operations disabled for the bank by the FMC + 0 + + + Enabled + Write operations enabled for the bank by the FMC + 1 + + + + + WAITCFG + WAITCFG + 11 + 1 + + WAITCFG + read-write + + BeforeWaitState + NWAIT signal is active one data cycle before wait state + 0 + + + DuringWaitState + NWAIT signal is active during wait state + 1 + + + + + WAITPOL + WAITPOL + 9 + 1 + + WAITPOL + read-write + + ActiveLow + NWAIT active low + 0 + + + ActiveHigh + NWAIT active high + 1 + + + + + BURSTEN + BURSTEN + 8 + 1 + + BURSTEN + read-write + + Disabled + Burst mode disabled + 0 + + + Enabled + Burst mode enabled + 1 + + + + + FACCEN + FACCEN + 6 + 1 + + FACCEN + read-write + + Disabled + Corresponding NOR Flash memory access is disabled + 0 + + + Enabled + Corresponding NOR Flash memory access is enabled + 1 + + + + + MWID + MWID + 4 + 2 + + MWID + read-write + + Bits8 + Memory data bus width 8 bits + 0 + + + Bits16 + Memory data bus width 16 bits + 1 + + + Bits32 + Memory data bus width 32 bits + 2 + + + + + MTYP + MTYP + 2 + 2 + + MTYP + read-write + + SRAM + SRAM memory type + 0 + + + PSRAM + PSRAM (CRAM) memory type + 1 + + + Flash + NOR Flash/OneNAND Flash + 2 + + + + + MUXEN + MUXEN + 1 + 1 + + MUXEN + read-write + + Disabled + Address/Data non-multiplexed + 0 + + + Enabled + Address/Data multiplexed on databus + 1 + + + + + MBKEN + MBKEN + 0 + 1 + + MBKEN + read-write + + Disabled + Corresponding memory bank is disabled + 0 + + + Enabled + Corresponding memory bank is enabled + 1 + + + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WFDIS + Write FIFO disable + 21 + 1 + read-write + + WFDIS + read-write + + Enabled + Write FIFO enabled + 0 + + + Disabled + Write FIFO disabled + 1 + + + + + CPSIZE + CRAM page size + 16 + 3 + read-write + + CPSIZE + read-write + + NoBurstSplit + No burst split when crossing page boundary + 0 + + + Bytes128 + 128 bytes CRAM page size + 1 + + + Bytes256 + 256 bytes CRAM page size + 2 + + + Bytes512 + 512 bytes CRAM page size + 3 + + + Bytes1024 + 1024 bytes CRAM page size + 4 + + + + + + + 4 + 0x8 + 1-4 + BTR%s + BTR1 + SRAM/NOR-Flash chip-select timing register 1 + 0x4 + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + ACCMOD + read-write + + A + Access mode A + 0 + + + B + Access mode B + 1 + + + C + Access mode C + 2 + + + D + Access mode D + 3 + + + + + DATLAT + DATLAT + 24 + 4 + + + 0 + 15 + + + + + CLKDIV + CLKDIV + 20 + 4 + + + 1 + 15 + + + + + BUSTURN + BUSTURN + 16 + 4 + + + 0 + 15 + + + + + DATAST + DATAST + 8 + 8 + + + 1 + 255 + + + + + ADDHLD + ADDHLD + 4 + 4 + + + 1 + 15 + + + + + ADDSET + ADDSET + 0 + 4 + + + 0 + 15 + + + + + + + 3 + 0x8 + 2-4 + BCR%s + BCR2 + SRAM/NOR-Flash chip-select control register 2 + 0x8 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + CBURSTRW + read-write + + Disabled + Write operations are always performed in asynchronous mode + 0 + + + Enabled + Write operations are performed in synchronous mode + 1 + + + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + ASYNCWAIT + read-write + + Disabled + Wait signal not used in asynchronous mode + 0 + + + Enabled + Wait signal used even in asynchronous mode + 1 + + + + + EXTMOD + EXTMOD + 14 + 1 + + EXTMOD + read-write + + Disabled + Values inside the FMC_BWTR are not taken into account + 0 + + + Enabled + Values inside the FMC_BWTR are taken into account + 1 + + + + + WAITEN + WAITEN + 13 + 1 + + WAITEN + read-write + + Disabled + Values inside the FMC_BWTR are taken into account + 0 + + + Enabled + NWAIT signal enabled + 1 + + + + + WREN + WREN + 12 + 1 + + WREN + read-write + + Disabled + Write operations disabled for the bank by the FMC + 0 + + + Enabled + Write operations enabled for the bank by the FMC + 1 + + + + + WAITCFG + WAITCFG + 11 + 1 + + WAITCFG + read-write + + BeforeWaitState + NWAIT signal is active one data cycle before wait state + 0 + + + DuringWaitState + NWAIT signal is active during wait state + 1 + + + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + WAITPOL + read-write + + ActiveLow + NWAIT active low + 0 + + + ActiveHigh + NWAIT active high + 1 + + + + + BURSTEN + BURSTEN + 8 + 1 + + BURSTEN + read-write + + Disabled + Burst mode disabled + 0 + + + Enabled + Burst mode enabled + 1 + + + + + FACCEN + FACCEN + 6 + 1 + + FACCEN + read-write + + Disabled + Corresponding NOR Flash memory access is disabled + 0 + + + Enabled + Corresponding NOR Flash memory access is enabled + 1 + + + + + MWID + MWID + 4 + 2 + + MWID + read-write + + Bits8 + Memory data bus width 8 bits + 0 + + + Bits16 + Memory data bus width 16 bits + 1 + + + Bits32 + Memory data bus width 32 bits + 2 + + + + + MTYP + MTYP + 2 + 2 + + MTYP + read-write + + SRAM + SRAM memory type + 0 + + + PSRAM + PSRAM (CRAM) memory type + 1 + + + Flash + NOR Flash/OneNAND Flash + 2 + + + + + MUXEN + MUXEN + 1 + 1 + + MUXEN + read-write + + Disabled + Address/Data non-multiplexed + 0 + + + Enabled + Address/Data multiplexed on databus + 1 + + + + + MBKEN + MBKEN + 0 + 1 + + MBKEN + read-write + + Disabled + Corresponding memory bank is disabled + 0 + + + Enabled + Corresponding memory bank is enabled + 1 + + + + + CPSIZE + CRAM page size + 16 + 3 + read-write + + CPSIZE + read-write + + NoBurstSplit + No burst split when crossing page boundary + 0 + + + Bytes128 + 128 bytes CRAM page size + 1 + + + Bytes256 + 256 bytes CRAM page size + 2 + + + Bytes512 + 512 bytes CRAM page size + 3 + + + Bytes1024 + 1024 bytes CRAM page size + 4 + + + + + + + PCR + PCR + PC Card/NAND Flash control register + 0x80 + 0x20 + read-write + 0x00000018 + + + ECCPS + ECCPS + 17 + 3 + + ECCPS + read-write + + Bytes256 + ECC page size 256 bytes + 0 + + + Bytes512 + ECC page size 512 bytes + 1 + + + Bytes1024 + ECC page size 1024 bytes + 2 + + + Bytes2048 + ECC page size 2048 bytes + 3 + + + Bytes4096 + ECC page size 4096 bytes + 4 + + + Bytes8192 + ECC page size 8192 bytes + 5 + + + + + TAR + TAR + 13 + 4 + + + 0 + 15 + + + + + TCLR + TCLR + 9 + 4 + + + 0 + 15 + + + + + ECCEN + ECCEN + 6 + 1 + + ECCEN + read-write + + Disabled + ECC logic is disabled and reset + 0 + + + Enabled + ECC logic is enabled + 1 + + + + + PWID + PWID + 4 + 2 + + PWID + read-write + + Bits8 + External memory device width 8 bits + 0 + + + Bits16 + External memory device width 16 bits + 1 + + + + + PTYP + PTYP + 3 + 1 + + PTYP + read-write + + NANDFlash + NAND Flash + 1 + + + + + PBKEN + PBKEN + 2 + 1 + + PBKEN + read-write + + Disabled + Corresponding memory bank is disabled + 0 + + + Enabled + Corresponding memory bank is enabled + 1 + + + + + PWAITEN + PWAITEN + 1 + 1 + + PWAITEN + read-write + + Disabled + Wait feature disabled + 0 + + + Enabled + Wait feature enabled + 1 + + + + + + + SR + SR + FIFO status and interrupt register + 0x84 + 0x20 + 0x00000040 + + + FEMPT + FEMPT + 6 + 1 + read-only + + FEMPT + read + + NotEmpty + FIFO not empty + 0 + + + Empty + FIFO empty + 1 + + + + + IFEN + IFEN + 5 + 1 + read-write + + IFEN + read-write + + Disabled + Interrupt falling edge detection request disabled + 0 + + + Enabled + Interrupt falling edge detection request enabled + 1 + + + + + ILEN + ILEN + 4 + 1 + read-write + + ILEN + read-write + + Disabled + Interrupt high-level detection request disabled + 0 + + + Enabled + Interrupt high-level detection request enabled + 1 + + + + + IREN + IREN + 3 + 1 + read-write + + IREN + read-write + + Disabled + Interrupt rising edge detection request disabled + 0 + + + Enabled + Interrupt rising edge detection request enabled + 1 + + + + + IFS + IFS + 2 + 1 + read-write + + IFS + read-write + + DidNotOccur + Interrupt falling edge did not occur + 0 + + + Occurred + Interrupt falling edge occurred + 1 + + + + + ILS + ILS + 1 + 1 + read-write + + ILS + read-write + + DidNotOccur + Interrupt high-level did not occur + 0 + + + Occurred + Interrupt high-level occurred + 1 + + + + + IRS + IRS + 0 + 1 + read-write + + IRS + read-write + + DidNotOccur + Interrupt rising edge did not occur + 0 + + + Occurred + Interrupt rising edge occurred + 1 + + + + + + + PMEM + PMEM + Common memory space timing register + 0x88 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZ + MEMHIZx + 24 + 8 + + + 0 + 254 + + + + + MEMHOLD + MEMHOLDx + 16 + 8 + + + 1 + 254 + + + + + MEMWAIT + MEMWAITx + 8 + 8 + + + 1 + 254 + + + + + MEMSET + MEMSETx + 0 + 8 + + + 0 + 254 + + + + + + + PATT + PATT + Attribute memory space timing register + 0x8C + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZ + ATTHIZx + 24 + 8 + + + 0 + 254 + + + + + ATTHOLD + ATTHOLDx + 16 + 8 + + + 1 + 254 + + + + + ATTWAIT + ATTWAITx + 8 + 8 + + + 1 + 254 + + + + + ATTSET + ATTSETx + 0 + 8 + + + 0 + 254 + + + + + + + ECCR + ECCR + ECC result register + 0x94 + 0x20 + read-only + 0x00000000 + + + ECC + ECCx + 0 + 32 + + + 0 + 4294967295 + + + + + + + 4 + 0x8 + 1-4 + BWTR%s + BWTR1 + SRAM/NOR-Flash write timing registers 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + ACCMOD + read-write + + A + Access mode A + 0 + + + B + Access mode B + 1 + + + C + Access mode C + 2 + + + D + Access mode D + 3 + + + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + DATAST + DATAST + 8 + 8 + + + 1 + 255 + + + + + ADDHLD + ADDHLD + 4 + 4 + + + 1 + 15 + + + + + ADDSET + ADDSET + 0 + 4 + + + 0 + 15 + + + + + BUSTURN + Bus turnaround phase duration + 16 + 4 + read-write + + + 0 + 15 + + + + + + + 2 + 0x4 + 1-2 + SDCR%s + SDCR1 + SDRAM Control Register 1 + 0x140 + 0x20 + read-write + 0x000002D0 + + + NC + Number of column address bits + 0 + 2 + + NC + read-write + + Bits8 + 8 bits + 0 + + + Bits9 + 9 bits + 1 + + + Bits10 + 10 bits + 2 + + + Bits11 + 11 bits + 3 + + + + + NR + Number of row address bits + 2 + 2 + + NR + read-write + + Bits11 + 11 bits + 0 + + + Bits12 + 12 bits + 1 + + + Bits13 + 13 bits + 2 + + + + + MWID + Memory data bus width + 4 + 2 + + MWID + read-write + + Bits8 + Memory data bus width 8 bits + 0 + + + Bits16 + Memory data bus width 16 bits + 1 + + + Bits32 + Memory data bus width 32 bits + 2 + + + + + NB + Number of internal banks + 6 + 1 + + NB + read-write + + NB2 + Two internal Banks + 0 + + + NB4 + Four internal Banks + 1 + + + + + CAS + CAS latency + 7 + 2 + + CAS + read-write + + Clocks1 + 1 cycle + 1 + + + Clocks2 + 2 cycles + 2 + + + Clocks3 + 3 cycles + 3 + + + + + WP + Write protection + 9 + 1 + + WP + read-write + + Disabled + Write accesses allowed + 0 + + + Enabled + Write accesses ignored + 1 + + + + + SDCLK + SDRAM clock configuration + 10 + 2 + + SDCLK + read-write + + Disabled + SDCLK clock disabled + 0 + + + Div2 + SDCLK period = 2 x HCLK period + 2 + + + Div3 + SDCLK period = 3 x HCLK period + 3 + + + + + RBURST + Burst read + 12 + 1 + + RBURST + read-write + + Disabled + Single read requests are not managed as bursts + 0 + + + Enabled + Single read requests are always managed as bursts + 1 + + + + + RPIPE + Read pipe + 13 + 2 + + RPIPE + read-write + + NoDelay + No clock cycle delay + 0 + + + Clocks1 + One clock cycle delay + 1 + + + Clocks2 + Two clock cycles delay + 2 + + + + + + + 2 + 0x4 + 1-2 + SDTR%s + SDTR1 + SDRAM Timing register 1 + 0x148 + 0x20 + read-write + 0x0FFFFFFF + + + TMRD + Load Mode Register to Active + 0 + 4 + + + 0 + 15 + + + + + TXSR + Exit self-refresh delay + 4 + 4 + + + 0 + 15 + + + + + TRAS + Self refresh time + 8 + 4 + + + 0 + 15 + + + + + TRC + Row cycle delay + 12 + 4 + + + 0 + 15 + + + + + TWR + Recovery delay + 16 + 4 + + + 0 + 15 + + + + + TRP + Row precharge delay + 20 + 4 + + + 0 + 15 + + + + + TRCD + Row to column delay + 24 + 4 + + + 0 + 15 + + + + + + + SDCMR + SDCMR + SDRAM Command Mode register + 0x150 + 0x20 + 0x00000000 + + + MODE + Command mode + 0 + 3 + write-only + + MODE + write + + Normal + Normal Mode + 0 + + + ClockConfigurationEnable + Clock Configuration Enable + 1 + + + PALL + PALL (All Bank Precharge) command + 2 + + + AutoRefreshCommand + Auto-refresh command + 3 + + + LoadModeRegister + Load Mode Resgier + 4 + + + SelfRefreshCommand + Self-refresh command + 5 + + + PowerDownCommand + Power-down command + 6 + + + + + CTB2 + Command target bank 2 + 3 + 1 + write-only + + CTB2 + write + + NotIssued + Command not issued to SDRAM Bank 1 + 0 + + + Issued + Command issued to SDRAM Bank 1 + 1 + + + + + CTB1 + Command target bank 1 + 4 + 1 + write-only + + + + NRFS + Number of Auto-refresh + 5 + 4 + read-write + + + 0 + 15 + + + + + MRD + Mode Register definition + 9 + 13 + read-write + + + 0 + 8191 + + + + + + + SDRTR + SDRTR + SDRAM Refresh Timer register + 0x154 + 0x20 + 0x00000000 + + + CRE + Clear Refresh error flag + 0 + 1 + write-only + + CRE + write + + Clear + Refresh Error Flag is cleared + 1 + + + + + COUNT + Refresh Timer Count + 1 + 13 + read-write + + + 0 + 8191 + + + + + REIE + RES Interrupt Enable + 14 + 1 + read-write + + REIE + read-write + + Disabled + Interrupt is disabled + 0 + + + Enabled + Interrupt is generated if RE = 1 + 1 + + + + + + + SDSR + SDSR + SDRAM Status register + 0x158 + 0x20 + read-only + 0x00000000 + + + RE + Refresh error flag + 0 + 1 + + RE + read + + NoError + No refresh error has been detected + 0 + + + Error + A refresh error has been detected + 1 + + + + + MODES1 + Status Mode for Bank 1 + 1 + 2 + + MODES1 + read + + Normal + Normal Mode + 0 + + + SelfRefresh + Self-refresh mode + 1 + + + PowerDown + Power-down mode + 2 + + + + + MODES2 + Status Mode for Bank 2 + 3 + 2 + + + + BUSY + Busy status + 5 + 1 + + BUSY + read + + NotBusy + SDRAM Controller is ready to accept a new request + 0 + + + Busy + SDRAM Controller is not ready to accept a new request + 1 + + + + + + + + + DBGMCU + Debug support + DBG + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + IDCODE + 0x0 + 0x20 + read-only + 0x10006411 + + + DEV_ID + DEV_ID + 0 + 12 + + + REV_ID + REV_ID + 16 + 16 + + + + + CR + CR + Control Register + 0x4 + 0x20 + read-write + 0x00000000 + + + DBG_SLEEP + DBG_SLEEP + 0 + 1 + + + DBG_STOP + DBG_STOP + 1 + 1 + + + DBG_STANDBY + DBG_STANDBY + 2 + 1 + + + TRACE_IOEN + TRACE_IOEN + 5 + 1 + + + TRACE_MODE + TRACE_MODE + 6 + 2 + + + + + APB1_FZ + APB1_FZ + Debug MCU APB1 Freeze registe + 0x8 + 0x20 + read-write + 0x00000000 + + + DBG_TIM2_STOP + DBG_TIM2_STOP + 0 + 1 + + + DBG_TIM3_STOP + DBG_TIM3 _STOP + 1 + 1 + + + DBG_TIM4_STOP + DBG_TIM4_STOP + 2 + 1 + + + DBG_TIM5_STOP + DBG_TIM5_STOP + 3 + 1 + + + DBG_TIM6_STOP + DBG_TIM6_STOP + 4 + 1 + + + DBG_TIM7_STOP + DBG_TIM7_STOP + 5 + 1 + + + DBG_TIM12_STOP + DBG_TIM12_STOP + 6 + 1 + + + DBG_TIM13_STOP + DBG_TIM13_STOP + 7 + 1 + + + DBG_TIM14_STOP + DBG_TIM14_STOP + 8 + 1 + + + DBG_WWDG_STOP + DBG_WWDG_STOP + 11 + 1 + + + DBG_IWDG_STOP + DBG_IWDEG_STOP + 12 + 1 + + + DBG_J2C1_SMBUS_TIMEOUT + DBG_J2C1_SMBUS_TIMEOUT + 21 + 1 + + + DBG_J2C2_SMBUS_TIMEOUT + DBG_J2C2_SMBUS_TIMEOUT + 22 + 1 + + + DBG_J2C3SMBUS_TIMEOUT + DBG_J2C3SMBUS_TIMEOUT + 23 + 1 + + + DBG_CAN1_STOP + DBG_CAN1_STOP + 25 + 1 + + + DBG_CAN2_STOP + DBG_CAN2_STOP + 26 + 1 + + + + + APB2_FZ + APB2_FZ + Debug MCU APB2 Freeze registe + 0xC + 0x20 + read-write + 0x00000000 + + + DBG_TIM1_STOP + TIM1 counter stopped when core is halted + 0 + 1 + + + DBG_TIM8_STOP + TIM8 counter stopped when core is halted + 1 + 1 + + + DBG_TIM9_STOP + TIM9 counter stopped when core is halted + 16 + 1 + + + DBG_TIM10_STOP + TIM10 counter stopped when core is halted + 17 + 1 + + + DBG_TIM11_STOP + TIM11 counter stopped when core is halted + 18 + 1 + + + + + + + DMA2 + DMA controller + DMA + 0x40026400 + + 0x0 + 0x400 + registers + + + DMA2_Stream0 + DMA2 Stream0 global interrupt + 56 + + + DMA2_Stream1 + DMA2 Stream1 global interrupt + 57 + + + DMA2_Stream2 + DMA2 Stream2 global interrupt + 58 + + + DMA2_Stream3 + DMA2 Stream3 global interrupt + 59 + + + DMA2_Stream4 + DMA2 Stream4 global interrupt + 60 + + + DMA2_Stream5 + DMA2 Stream5 global interrupt + 68 + + + DMA2_Stream6 + DMA2 Stream6 global interrupt + 69 + + + DMA2_Stream7 + DMA2 Stream7 global interrupt + 70 + + + + LISR + LISR + low interrupt status register + 0x0 + 0x20 + read-only + 0x00000000 + + + TCIF3 + Stream x transfer complete interrupt flag (x = 3..0) + 27 + 1 + + + + HTIF3 + Stream x half transfer interrupt flag (x=3..0) + 26 + 1 + + + + TEIF3 + Stream x transfer error interrupt flag (x=3..0) + 25 + 1 + + + + DMEIF3 + Stream x direct mode error interrupt flag (x=3..0) + 24 + 1 + + + + FEIF3 + Stream x FIFO error interrupt flag (x=3..0) + 22 + 1 + + + + TCIF2 + Stream x transfer complete interrupt flag (x = 3..0) + 21 + 1 + + + + HTIF2 + Stream x half transfer interrupt flag (x=3..0) + 20 + 1 + + + + TEIF2 + Stream x transfer error interrupt flag (x=3..0) + 19 + 1 + + + + DMEIF2 + Stream x direct mode error interrupt flag (x=3..0) + 18 + 1 + + + + FEIF2 + Stream x FIFO error interrupt flag (x=3..0) + 16 + 1 + + + + TCIF1 + Stream x transfer complete interrupt flag (x = 3..0) + 11 + 1 + + + + HTIF1 + Stream x half transfer interrupt flag (x=3..0) + 10 + 1 + + + + TEIF1 + Stream x transfer error interrupt flag (x=3..0) + 9 + 1 + + + + DMEIF1 + Stream x direct mode error interrupt flag (x=3..0) + 8 + 1 + + + + FEIF1 + Stream x FIFO error interrupt flag (x=3..0) + 6 + 1 + + + + TCIF0 + Stream x transfer complete interrupt flag (x = 3..0) + 5 + 1 + + TCIF0 + read + + NotComplete + No transfer complete event on stream x + 0 + + + Complete + A transfer complete event occurred on stream x + 1 + + + + + HTIF0 + Stream x half transfer interrupt flag (x=3..0) + 4 + 1 + + HTIF0 + read + + NotHalf + No half transfer event on stream x + 0 + + + Half + A half transfer event occurred on stream x + 1 + + + + + TEIF0 + Stream x transfer error interrupt flag (x=3..0) + 3 + 1 + + TEIF0 + read + + NoError + No transfer error on stream x + 0 + + + Error + A transfer error occurred on stream x + 1 + + + + + DMEIF0 + Stream x direct mode error interrupt flag (x=3..0) + 2 + 1 + + DMEIF0 + read + + NoError + No Direct Mode error on stream x + 0 + + + Error + A Direct Mode error occurred on stream x + 1 + + + + + FEIF0 + Stream x FIFO error interrupt flag (x=3..0) + 0 + 1 + + FEIF0 + read + + NoError + No FIFO error event on stream x + 0 + + + Error + A FIFO error event occurred on stream x + 1 + + + + + + + HISR + HISR + high interrupt status register + 0x4 + 0x20 + read-only + 0x00000000 + + + TCIF7 + Stream x transfer complete interrupt flag (x=7..4) + 27 + 1 + + + + HTIF7 + Stream x half transfer interrupt flag (x=7..4) + 26 + 1 + + + + TEIF7 + Stream x transfer error interrupt flag (x=7..4) + 25 + 1 + + + + DMEIF7 + Stream x direct mode error interrupt flag (x=7..4) + 24 + 1 + + + + FEIF7 + Stream x FIFO error interrupt flag (x=7..4) + 22 + 1 + + + + TCIF6 + Stream x transfer complete interrupt flag (x=7..4) + 21 + 1 + + + + HTIF6 + Stream x half transfer interrupt flag (x=7..4) + 20 + 1 + + + + TEIF6 + Stream x transfer error interrupt flag (x=7..4) + 19 + 1 + + + + DMEIF6 + Stream x direct mode error interrupt flag (x=7..4) + 18 + 1 + + + + FEIF6 + Stream x FIFO error interrupt flag (x=7..4) + 16 + 1 + + + + TCIF5 + Stream x transfer complete interrupt flag (x=7..4) + 11 + 1 + + + + HTIF5 + Stream x half transfer interrupt flag (x=7..4) + 10 + 1 + + + + TEIF5 + Stream x transfer error interrupt flag (x=7..4) + 9 + 1 + + + + DMEIF5 + Stream x direct mode error interrupt flag (x=7..4) + 8 + 1 + + + + FEIF5 + Stream x FIFO error interrupt flag (x=7..4) + 6 + 1 + + + + TCIF4 + Stream x transfer complete interrupt flag (x=7..4) + 5 + 1 + + TCIF4 + read + + NotComplete + No transfer complete event on stream x + 0 + + + Complete + A transfer complete event occurred on stream x + 1 + + + + + HTIF4 + Stream x half transfer interrupt flag (x=7..4) + 4 + 1 + + HTIF4 + read + + NotHalf + No half transfer event on stream x + 0 + + + Half + A half transfer event occurred on stream x + 1 + + + + + TEIF4 + Stream x transfer error interrupt flag (x=7..4) + 3 + 1 + + TEIF4 + read + + NoError + No transfer error on stream x + 0 + + + Error + A transfer error occurred on stream x + 1 + + + + + DMEIF4 + Stream x direct mode error interrupt flag (x=7..4) + 2 + 1 + + DMEIF4 + read + + NoError + No Direct Mode error on stream x + 0 + + + Error + A Direct Mode error occurred on stream x + 1 + + + + + FEIF4 + Stream x FIFO error interrupt flag (x=7..4) + 0 + 1 + + FEIF4 + read + + NoError + No FIFO error event on stream x + 0 + + + Error + A FIFO error event occurred on stream x + 1 + + + + + + + LIFCR + LIFCR + low interrupt flag clear register + 0x8 + 0x20 + write-only + 0x00000000 + + + CTCIF3 + Stream x clear transfer complete interrupt flag (x = 3..0) + 27 + 1 + + + + CHTIF3 + Stream x clear half transfer interrupt flag (x = 3..0) + 26 + 1 + + + + CTEIF3 + Stream x clear transfer error interrupt flag (x = 3..0) + 25 + 1 + + + + CDMEIF3 + Stream x clear direct mode error interrupt flag (x = 3..0) + 24 + 1 + + + + CFEIF3 + Stream x clear FIFO error interrupt flag (x = 3..0) + 22 + 1 + + + + CTCIF2 + Stream x clear transfer complete interrupt flag (x = 3..0) + 21 + 1 + + + + CHTIF2 + Stream x clear half transfer interrupt flag (x = 3..0) + 20 + 1 + + + + CTEIF2 + Stream x clear transfer error interrupt flag (x = 3..0) + 19 + 1 + + + + CDMEIF2 + Stream x clear direct mode error interrupt flag (x = 3..0) + 18 + 1 + + + + CFEIF2 + Stream x clear FIFO error interrupt flag (x = 3..0) + 16 + 1 + + + + CTCIF1 + Stream x clear transfer complete interrupt flag (x = 3..0) + 11 + 1 + + + + CHTIF1 + Stream x clear half transfer interrupt flag (x = 3..0) + 10 + 1 + + + + CTEIF1 + Stream x clear transfer error interrupt flag (x = 3..0) + 9 + 1 + + + + CDMEIF1 + Stream x clear direct mode error interrupt flag (x = 3..0) + 8 + 1 + + + + CFEIF1 + Stream x clear FIFO error interrupt flag (x = 3..0) + 6 + 1 + + + + CTCIF0 + Stream x clear transfer complete interrupt flag (x = 3..0) + 5 + 1 + + CTCIF0 + write + + Clear + Clear the corresponding TCIFx flag + 1 + + + + + CHTIF0 + Stream x clear half transfer interrupt flag (x = 3..0) + 4 + 1 + + CHTIF0 + write + + Clear + Clear the corresponding HTIFx flag + 1 + + + + + CTEIF0 + Stream x clear transfer error interrupt flag (x = 3..0) + 3 + 1 + + CTEIF0 + write + + Clear + Clear the corresponding TEIFx flag + 1 + + + + + CDMEIF0 + Stream x clear direct mode error interrupt flag (x = 3..0) + 2 + 1 + + CDMEIF0 + write + + Clear + Clear the corresponding DMEIFx flag + 1 + + + + + CFEIF0 + Stream x clear FIFO error interrupt flag (x = 3..0) + 0 + 1 + + CFEIF0 + write + + Clear + Clear the corresponding CFEIFx flag + 1 + + + + + + + HIFCR + HIFCR + high interrupt flag clear register + 0xC + 0x20 + write-only + 0x00000000 + + + CTCIF7 + Stream x clear transfer complete interrupt flag (x = 7..4) + 27 + 1 + + + + CHTIF7 + Stream x clear half transfer interrupt flag (x = 7..4) + 26 + 1 + + + + CTEIF7 + Stream x clear transfer error interrupt flag (x = 7..4) + 25 + 1 + + + + CDMEIF7 + Stream x clear direct mode error interrupt flag (x = 7..4) + 24 + 1 + + + + CFEIF7 + Stream x clear FIFO error interrupt flag (x = 7..4) + 22 + 1 + + + + CTCIF6 + Stream x clear transfer complete interrupt flag (x = 7..4) + 21 + 1 + + + + CHTIF6 + Stream x clear half transfer interrupt flag (x = 7..4) + 20 + 1 + + + + CTEIF6 + Stream x clear transfer error interrupt flag (x = 7..4) + 19 + 1 + + + + CDMEIF6 + Stream x clear direct mode error interrupt flag (x = 7..4) + 18 + 1 + + + + CFEIF6 + Stream x clear FIFO error interrupt flag (x = 7..4) + 16 + 1 + + + + CTCIF5 + Stream x clear transfer complete interrupt flag (x = 7..4) + 11 + 1 + + + + CHTIF5 + Stream x clear half transfer interrupt flag (x = 7..4) + 10 + 1 + + + + CTEIF5 + Stream x clear transfer error interrupt flag (x = 7..4) + 9 + 1 + + + + CDMEIF5 + Stream x clear direct mode error interrupt flag (x = 7..4) + 8 + 1 + + + + CFEIF5 + Stream x clear FIFO error interrupt flag (x = 7..4) + 6 + 1 + + + + CTCIF4 + Stream x clear transfer complete interrupt flag (x = 7..4) + 5 + 1 + + CTCIF4 + write + + Clear + Clear the corresponding TCIFx flag + 1 + + + + + CHTIF4 + Stream x clear half transfer interrupt flag (x = 7..4) + 4 + 1 + + CHTIF4 + write + + Clear + Clear the corresponding HTIFx flag + 1 + + + + + CTEIF4 + Stream x clear transfer error interrupt flag (x = 7..4) + 3 + 1 + + CTEIF4 + write + + Clear + Clear the corresponding TEIFx flag + 1 + + + + + CDMEIF4 + Stream x clear direct mode error interrupt flag (x = 7..4) + 2 + 1 + + CDMEIF4 + write + + Clear + Clear the corresponding DMEIFx flag + 1 + + + + + CFEIF4 + Stream x clear FIFO error interrupt flag (x = 7..4) + 0 + 1 + + CFEIF4 + write + + Clear + Clear the corresponding CFEIFx flag + 1 + + + + + + + 8 + 0x18 + 0-7 + ST%s + Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers + 0x10 + + CR + S0CR + stream x configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + CHSEL + Channel selection + 25 + 3 + + + 0 + 7 + + + + + MBURST + Memory burst transfer configuration + 23 + 2 + + + + PBURST + Peripheral burst transfer configuration + 21 + 2 + + PBURST + read-write + + Single + Single transfer + 0 + + + INCR4 + Incremental burst of 4 beats + 1 + + + INCR8 + Incremental burst of 8 beats + 2 + + + INCR16 + Incremental burst of 16 beats + 3 + + + + + CT + Current target (only in double buffer mode) + 19 + 1 + + CT + read-write + + Memory0 + The current target memory is Memory 0 + 0 + + + Memory1 + The current target memory is Memory 1 + 1 + + + + + DBM + Double buffer mode + 18 + 1 + + DBM + read-write + + Disabled + No buffer switching at the end of transfer + 0 + + + Enabled + Memory target switched at the end of the DMA transfer + 1 + + + + + PL + Priority level + 16 + 2 + + PL + read-write + + Low + Low + 0 + + + Medium + Medium + 1 + + + High + High + 2 + + + VeryHigh + Very high + 3 + + + + + PINCOS + Peripheral increment offset size + 15 + 1 + + PINCOS + read-write + + PSIZE + The offset size for the peripheral address calculation is linked to the PSIZE + 0 + + + Fixed4 + The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment) + 1 + + + + + MSIZE + Memory data size + 13 + 2 + + + + PSIZE + Peripheral data size + 11 + 2 + + PSIZE + read-write + + Bits8 + Byte (8-bit) + 0 + + + Bits16 + Half-word (16-bit) + 1 + + + Bits32 + Word (32-bit) + 2 + + + + + MINC + Memory increment mode + 10 + 1 + + + + PINC + Peripheral increment mode + 9 + 1 + + PINC + read-write + + Fixed + Address pointer is fixed + 0 + + + Incremented + Address pointer is incremented after each data transfer + 1 + + + + + CIRC + Circular mode + 8 + 1 + + CIRC + read-write + + Disabled + Circular mode disabled + 0 + + + Enabled + Circular mode enabled + 1 + + + + + DIR + Data transfer direction + 6 + 2 + + DIR + read-write + + PeripheralToMemory + Peripheral-to-memory + 0 + + + MemoryToPeripheral + Memory-to-peripheral + 1 + + + MemoryToMemory + Memory-to-memory + 2 + + + + + PFCTRL + Peripheral flow controller + 5 + 1 + + PFCTRL + read-write + + DMA + The DMA is the flow controller + 0 + + + Peripheral + The peripheral is the flow controller + 1 + + + + + TCIE + Transfer complete interrupt enable + 4 + 1 + + TCIE + read-write + + Disabled + TC interrupt disabled + 0 + + + Enabled + TC interrupt enabled + 1 + + + + + HTIE + Half transfer interrupt enable + 3 + 1 + + HTIE + read-write + + Disabled + HT interrupt disabled + 0 + + + Enabled + HT interrupt enabled + 1 + + + + + TEIE + Transfer error interrupt enable + 2 + 1 + + TEIE + read-write + + Disabled + TE interrupt disabled + 0 + + + Enabled + TE interrupt enabled + 1 + + + + + DMEIE + Direct mode error interrupt enable + 1 + 1 + + DMEIE + read-write + + Disabled + DME interrupt disabled + 0 + + + Enabled + DME interrupt enabled + 1 + + + + + EN + Stream enable / flag stream ready when read low + 0 + 1 + + EN + read-write + + Disabled + Stream disabled + 0 + + + Enabled + Stream enabled + 1 + + + + + + + NDTR + S0NDTR + stream x number of data register + 0x4 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + 0 + 65535 + + + + + + + PAR + S0PAR + stream x peripheral address register + 0x8 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + M0AR + S0M0AR + stream x memory 0 address register + 0xC + 0x20 + read-write + 0x00000000 + + + M0A + Memory 0 address + 0 + 32 + + + + + M1AR + S0M1AR + stream x memory 1 address register + 0x10 + 0x20 + read-write + 0x00000000 + + + M1A + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + FCR + S0FCR + stream x FIFO control register + 0x14 + 0x20 + 0x00000021 + + + FEIE + FIFO error interrupt enable + 7 + 1 + read-write + + FEIE + read-write + + Disabled + FE interrupt disabled + 0 + + + Enabled + FE interrupt enabled + 1 + + + + + FS + FIFO status + 3 + 3 + read-only + + FS + read + + Quarter1 + 0 < fifo_level < 1/4 + 0 + + + Quarter2 + 1/4 <= fifo_level < 1/2 + 1 + + + Quarter3 + 1/2 <= fifo_level < 3/4 + 2 + + + Quarter4 + 3/4 <= fifo_level < full + 3 + + + Empty + FIFO is empty + 4 + + + Full + FIFO is full + 5 + + + + + DMDIS + Direct mode disable + 2 + 1 + read-write + + DMDIS + read-write + + Enabled + Direct mode is enabled + 0 + + + Disabled + Direct mode is disabled + 1 + + + + + FTH + FIFO threshold selection + 0 + 2 + read-write + + FTH + read-write + + Quarter + 1/4 full FIFO + 0 + + + Half + 1/2 full FIFO + 1 + + + ThreeQuarters + 3/4 full FIFO + 2 + + + Full + Full FIFO + 3 + + + + + + + + + + DMA1 + 0x40026000 + + DMA1_Stream0 + DMA1 Stream0 global interrupt + 11 + + + DMA1_Stream1 + DMA1 Stream1 global interrupt + 12 + + + DMA1_Stream2 + DMA1 Stream2 global interrupt + 13 + + + DMA1_Stream3 + DMA1 Stream3 global interrupt + 14 + + + DMA1_Stream4 + DMA1 Stream4 global interrupt + 15 + + + DMA1_Stream5 + DMA1 Stream5 global interrupt + 16 + + + DMA1_Stream6 + DMA1 Stream6 global interrupt + 17 + + + DMA1_Stream7 + DMA1 Stream7 global interrupt + 47 + + + + RCC + Reset and clock control + RCC + 0x40023800 + + 0x0 + 0x400 + registers + + + RCC + RCC global interrupt + 5 + + + + CR + CR + clock control register + 0x0 + 0x20 + 0x00000083 + + + PLLI2SRDY + PLLI2S clock ready flag + 27 + 1 + read-only + + + + PLLI2SON + PLLI2S enable + 26 + 1 + read-write + + + + PLLRDY + Main PLL (PLL) clock ready flag + 25 + 1 + read-only + + + + PLLON + Main PLL (PLL) enable + 24 + 1 + read-write + + + + CSSON + Clock security system enable + 19 + 1 + read-write + + CSSON + read-write + + Off + Clock security system disabled (clock detector OFF) + 0 + + + On + Clock security system enable (clock detector ON if the HSE is ready, OFF if not) + 1 + + + + + HSEBYP + HSE clock bypass + 18 + 1 + read-write + + HSEBYP + read-write + + NotBypassed + HSE crystal oscillator not bypassed + 0 + + + Bypassed + HSE crystal oscillator bypassed with external clock + 1 + + + + + HSERDY + HSE clock ready flag + 17 + 1 + read-only + + + + HSEON + HSE clock enable + 16 + 1 + read-write + + + + HSICAL + Internal high-speed clock calibration + 8 + 8 + read-only + + + 0 + 255 + + + + + HSITRIM + Internal high-speed clock trimming + 3 + 5 + read-write + + + 0 + 31 + + + + + HSIRDY + Internal high-speed clock ready flag + 1 + 1 + read-only + + HSIRDYR + read + + NotReady + Clock not ready + 0 + + + Ready + Clock ready + 1 + + + + + HSION + Internal high-speed clock enable + 0 + 1 + read-write + + HSION + read-write + + Off + Clock Off + 0 + + + On + Clock On + 1 + + + + + PLLSAIRDY + PLLSAI clock ready flag + 29 + 1 + read-only + + + + PLLSAION + PLLSAI enable + 28 + 1 + read-write + + + + + + PLLCFGR + PLLCFGR + PLL configuration register + 0x4 + 0x20 + read-write + 0x24003010 + + + PLLSRC + Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + 22 + 1 + + PLLSRC + read-write + + HSI + HSI clock selected as PLL and PLLI2S clock entry + 0 + + + HSE + HSE oscillator clock selected as PLL and PLLI2S clock entry + 1 + + + + + PLLM + Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + 0 + 6 + + + 2 + 63 + + + + + PLLN + Main PLL (PLL) multiplication factor for VCO + 6 + 9 + + + 50 + 432 + + + + + PLLP + Main PLL (PLL) division factor for main system clock + 16 + 2 + + PLLP + read-write + + Div2 + PLLP=2 + 0 + + + Div4 + PLLP=4 + 1 + + + Div6 + PLLP=6 + 2 + + + Div8 + PLLP=8 + 3 + + + + + PLLQ + Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + 24 + 4 + + + 2 + 15 + + + + + + + CFGR + CFGR + clock configuration register + 0x8 + 0x20 + 0x00000000 + + + MCO2 + Microcontroller clock output 2 + 30 + 2 + read-write + + MCO2 + read-write + + SYSCLK + System clock (SYSCLK) selected + 0 + + + PLLI2S + PLLI2S clock selected + 1 + + + HSE + HSE oscillator clock selected + 2 + + + PLL + PLL clock selected + 3 + + + + + MCO2PRE + MCO2 prescaler + 27 + 3 + read-write + + + + MCO1PRE + MCO1 prescaler + 24 + 3 + read-write + + MCO1PRE + read-write + + Div1 + No division + 0 + + + Div2 + Division by 2 + 4 + + + Div3 + Division by 3 + 5 + + + Div4 + Division by 4 + 6 + + + Div5 + Division by 5 + 7 + + + + + I2SSRC + I2S clock selection + 23 + 1 + read-write + + I2SSRC + read-write + + PLLI2S + PLLI2S clock used as I2S clock source + 0 + + + CKIN + External clock mapped on the I2S_CKIN pin used as I2S clock source + 1 + + + + + MCO1 + Microcontroller clock output 1 + 21 + 2 + read-write + + MCO1 + read-write + + HSI + HSI clock selected + 0 + + + LSE + LSE oscillator selected + 1 + + + HSE + HSE oscillator clock selected + 2 + + + PLL + PLL clock selected + 3 + + + + + RTCPRE + HSE division factor for RTC clock + 16 + 5 + read-write + + + 0 + 31 + + + + + PPRE2 + APB high-speed prescaler (APB2) + 13 + 3 + read-write + + + + PPRE1 + APB Low speed prescaler (APB1) + 10 + 3 + read-write + + PPRE1 + read-write + + Div1 + HCLK not divided + 0 + + + Div2 + HCLK divided by 2 + 4 + + + Div4 + HCLK divided by 4 + 5 + + + Div8 + HCLK divided by 8 + 6 + + + Div16 + HCLK divided by 16 + 7 + + + + + HPRE + AHB prescaler + 4 + 4 + read-write + + HPRE + read-write + + Div1 + SYSCLK not divided + 0 + + + Div2 + SYSCLK divided by 2 + 8 + + + Div4 + SYSCLK divided by 4 + 9 + + + Div8 + SYSCLK divided by 8 + 10 + + + Div16 + SYSCLK divided by 16 + 11 + + + Div64 + SYSCLK divided by 64 + 12 + + + Div128 + SYSCLK divided by 128 + 13 + + + Div256 + SYSCLK divided by 256 + 14 + + + Div512 + SYSCLK divided by 512 + 15 + + + + + SW + System clock switch + 0 + 2 + + SW + read-write + + HSI + HSI selected as system clock + 0 + + + HSE + HSE selected as system clock + 1 + + + PLL + PLL selected as system clock + 2 + + + + + SWS + System clock switch status + 2 + 2 + + SWSR + read + + HSI + HSI oscillator used as system clock + 0 + + + HSE + HSE oscillator used as system clock + 1 + + + PLL + PLL used as system clock + 2 + + + + + + + CIR + CIR + clock interrupt register + 0xC + 0x20 + 0x00000000 + + + CSSC + Clock security system interrupt clear + 23 + 1 + write-only + + CSSCW + write + + Clear + Clear CSSF flag + 1 + + + + + PLLSAIRDYC + PLLSAI Ready Interrupt Clear + 22 + 1 + write-only + + + + PLLI2SRDYC + PLLI2S ready interrupt clear + 21 + 1 + write-only + + + + PLLRDYC + Main PLL(PLL) ready interrupt clear + 20 + 1 + write-only + + + + HSERDYC + HSE ready interrupt clear + 19 + 1 + write-only + + + + HSIRDYC + HSI ready interrupt clear + 18 + 1 + write-only + + + + LSERDYC + LSE ready interrupt clear + 17 + 1 + write-only + + + + LSIRDYC + LSI ready interrupt clear + 16 + 1 + write-only + + LSIRDYCW + write + + Clear + Clear interrupt flag + 1 + + + + + PLLSAIRDYIE + PLLSAI Ready Interrupt Enable + 14 + 1 + read-write + + + + PLLI2SRDYIE + PLLI2S ready interrupt enable + 13 + 1 + read-write + + + + PLLRDYIE + Main PLL (PLL) ready interrupt enable + 12 + 1 + read-write + + + + HSERDYIE + HSE ready interrupt enable + 11 + 1 + read-write + + + + HSIRDYIE + HSI ready interrupt enable + 10 + 1 + read-write + + + + LSERDYIE + LSE ready interrupt enable + 9 + 1 + read-write + + + + LSIRDYIE + LSI ready interrupt enable + 8 + 1 + read-write + + LSIRDYIE + read-write + + Disabled + Interrupt disabled + 0 + + + Enabled + Interrupt enabled + 1 + + + + + CSSF + Clock security system interrupt flag + 7 + 1 + read-only + + CSSFR + read + + NotInterrupted + No clock security interrupt caused by HSE clock failure + 0 + + + Interrupted + Clock security interrupt caused by HSE clock failure + 1 + + + + + PLLSAIRDYF + PLLSAI ready interrupt flag + 6 + 1 + read-only + + + + PLLI2SRDYF + PLLI2S ready interrupt flag + 5 + 1 + read-only + + + + PLLRDYF + Main PLL (PLL) ready interrupt flag + 4 + 1 + read-only + + + + HSERDYF + HSE ready interrupt flag + 3 + 1 + read-only + + + + HSIRDYF + HSI ready interrupt flag + 2 + 1 + read-only + + + + LSERDYF + LSE ready interrupt flag + 1 + 1 + read-only + + + + LSIRDYF + LSI ready interrupt flag + 0 + 1 + read-only + + LSIRDYFR + read + + NotInterrupted + No clock ready interrupt + 0 + + + Interrupted + Clock ready interrupt + 1 + + + + + + + AHB1RSTR + AHB1RSTR + AHB1 peripheral reset register + 0x10 + 0x20 + read-write + 0x00000000 + + + OTGHSRST + USB OTG HS module reset + 29 + 1 + + + + ETHMACRST + Ethernet MAC reset + 25 + 1 + + + + DMA2DRST + DMA2D reset + 23 + 1 + + + + DMA2RST + DMA2 reset + 22 + 1 + + + + DMA1RST + DMA2 reset + 21 + 1 + + + + CRCRST + CRC reset + 12 + 1 + + + + GPIOKRST + IO port K reset + 10 + 1 + + + + GPIOJRST + IO port J reset + 9 + 1 + + + + GPIOIRST + IO port I reset + 8 + 1 + + + + GPIOHRST + IO port H reset + 7 + 1 + + + + GPIOGRST + IO port G reset + 6 + 1 + + + + GPIOFRST + IO port F reset + 5 + 1 + + + + GPIOERST + IO port E reset + 4 + 1 + + + + GPIODRST + IO port D reset + 3 + 1 + + + + GPIOCRST + IO port C reset + 2 + 1 + + + + GPIOBRST + IO port B reset + 1 + 1 + + + + GPIOARST + IO port A reset + 0 + 1 + + GPIOARST + read-write + + Reset + Reset the selected module + 1 + + + + + + + AHB2RSTR + AHB2RSTR + AHB2 peripheral reset register + 0x14 + 0x20 + read-write + 0x00000000 + + + OTGFSRST + USB OTG FS module reset + 7 + 1 + + + + RNGRST + Random number generator module reset + 6 + 1 + + + + HSAHRST + Hash module reset + 5 + 1 + + + + CRYPRST + Cryptographic module reset + 4 + 1 + + + + DCMIRST + Camera interface reset + 0 + 1 + + DCMIRST + read-write + + Reset + Reset the selected module + 1 + + + + + + + AHB3RSTR + AHB3RSTR + AHB3 peripheral reset register + 0x18 + 0x20 + read-write + 0x00000000 + + + FMCRST + Flexible memory controller module reset + 0 + 1 + + FMCRST + read-write + + Reset + Reset the selected module + 1 + + + + + QSPIRST + Quad SPI memory controller reset + 1 + 1 + + + + + + APB1RSTR + APB1RSTR + APB1 peripheral reset register + 0x20 + 0x20 + read-write + 0x00000000 + + + TIM2RST + TIM2 reset + 0 + 1 + + TIM2RST + read-write + + Reset + Reset the selected module + 1 + + + + + TIM3RST + TIM3 reset + 1 + 1 + + + + TIM4RST + TIM4 reset + 2 + 1 + + + + TIM5RST + TIM5 reset + 3 + 1 + + + + TIM6RST + TIM6 reset + 4 + 1 + + + + TIM7RST + TIM7 reset + 5 + 1 + + + + TIM12RST + TIM12 reset + 6 + 1 + + + + TIM13RST + TIM13 reset + 7 + 1 + + + + TIM14RST + TIM14 reset + 8 + 1 + + + + WWDGRST + Window watchdog reset + 11 + 1 + + + + SPI2RST + SPI 2 reset + 14 + 1 + + + + SPI3RST + SPI 3 reset + 15 + 1 + + + + USART2RST + USART 2 reset + 17 + 1 + + + + USART3RST + USART 3 reset + 18 + 1 + + + + UART4RST + USART 4 reset + 19 + 1 + + + + UART5RST + USART 5 reset + 20 + 1 + + + + I2C1RST + I2C 1 reset + 21 + 1 + + + + I2C2RST + I2C 2 reset + 22 + 1 + + + + I2C3RST + I2C3 reset + 23 + 1 + + + + CAN1RST + CAN1 reset + 25 + 1 + + + + CAN2RST + CAN2 reset + 26 + 1 + + + + PWRRST + Power interface reset + 28 + 1 + + + + DACRST + DAC reset + 29 + 1 + + + + UART7RST + UART7 reset + 30 + 1 + + + + UART8RST + UART8 reset + 31 + 1 + + + + SPDIFRXRST + SPDIF-RX reset + 16 + 1 + + + + CECRST + HDMI-CEC reset + 27 + 1 + + + + LPTIM1RST + Low power timer 1 reset + 9 + 1 + + + + I2C4RST + I2C 4 reset + 24 + 1 + + + + + + APB2RSTR + APB2RSTR + APB2 peripheral reset register + 0x24 + 0x20 + read-write + 0x00000000 + + + TIM1RST + TIM1 reset + 0 + 1 + + TIM1RST + read-write + + Reset + Reset the selected module + 1 + + + + + TIM8RST + TIM8 reset + 1 + 1 + + + + USART1RST + USART1 reset + 4 + 1 + + + + USART6RST + USART6 reset + 5 + 1 + + + + ADCRST + ADC interface reset (common to all ADCs) + 8 + 1 + + + + SPI1RST + SPI 1 reset + 12 + 1 + + + + SPI4RST + SPI4 reset + 13 + 1 + + + + SYSCFGRST + System configuration controller reset + 14 + 1 + + + + TIM9RST + TIM9 reset + 16 + 1 + + + + TIM10RST + TIM10 reset + 17 + 1 + + + + TIM11RST + TIM11 reset + 18 + 1 + + + + SPI5RST + SPI5 reset + 20 + 1 + + + + SPI6RST + SPI6 reset + 21 + 1 + + + + SAI1RST + SAI1 reset + 22 + 1 + + + + LTDCRST + LTDC reset + 26 + 1 + + + + SAI2RST + SAI2 reset + 23 + 1 + + + + SDMMC1RST + SDMMC1 reset + 11 + 1 + + + + + + AHB1ENR + AHB1ENR + AHB1 peripheral clock register + 0x30 + 0x20 + read-write + 0x00100000 + + + OTGHSULPIEN + USB OTG HSULPI clock enable + 30 + 1 + + + + OTGHSEN + USB OTG HS clock enable + 29 + 1 + + + + ETHMACPTPEN + Ethernet PTP clock enable + 28 + 1 + + + + ETHMACRXEN + Ethernet Reception clock enable + 27 + 1 + + + + ETHMACTXEN + Ethernet Transmission clock enable + 26 + 1 + + + + ETHMACEN + Ethernet MAC clock enable + 25 + 1 + + + + DMA2DEN + DMA2D clock enable + 23 + 1 + + + + DMA2EN + DMA2 clock enable + 22 + 1 + + + + DMA1EN + DMA1 clock enable + 21 + 1 + + + + DTCMRAMEN + CCM data RAM clock enable + 20 + 1 + + + + BKPSRAMEN + Backup SRAM interface clock enable + 18 + 1 + + + + CRCEN + CRC clock enable + 12 + 1 + + + + GPIOKEN + IO port K clock enable + 10 + 1 + + + + GPIOJEN + IO port J clock enable + 9 + 1 + + + + GPIOIEN + IO port I clock enable + 8 + 1 + + + + GPIOHEN + IO port H clock enable + 7 + 1 + + + + GPIOGEN + IO port G clock enable + 6 + 1 + + + + GPIOFEN + IO port F clock enable + 5 + 1 + + + + GPIOEEN + IO port E clock enable + 4 + 1 + + + + GPIODEN + IO port D clock enable + 3 + 1 + + + + GPIOCEN + IO port C clock enable + 2 + 1 + + + + GPIOBEN + IO port B clock enable + 1 + 1 + + + + GPIOAEN + IO port A clock enable + 0 + 1 + + GPIOAEN + read-write + + Disabled + The selected clock is disabled + 0 + + + Enabled + The selected clock is enabled + 1 + + + + + + + AHB2ENR + AHB2ENR + AHB2 peripheral clock enable register + 0x34 + 0x20 + read-write + 0x00000000 + + + OTGFSEN + USB OTG FS clock enable + 7 + 1 + + + + RNGEN + Random number generator clock enable + 6 + 1 + + + + HASHEN + Hash modules clock enable + 5 + 1 + + + + CRYPEN + Cryptographic modules clock enable + 4 + 1 + + + + DCMIEN + Camera interface enable + 0 + 1 + + DCMIEN + read-write + + Disabled + The selected clock is disabled + 0 + + + Enabled + The selected clock is enabled + 1 + + + + + + + AHB3ENR + AHB3ENR + AHB3 peripheral clock enable register + 0x38 + 0x20 + read-write + 0x00000000 + + + FMCEN + Flexible memory controller module clock enable + 0 + 1 + + FMCEN + read-write + + Disabled + The selected clock is disabled + 0 + + + Enabled + The selected clock is enabled + 1 + + + + + QSPIEN + Quad SPI memory controller clock enable + 1 + 1 + + + + + + APB1ENR + APB1ENR + APB1 peripheral clock enable register + 0x40 + 0x20 + read-write + 0x00000000 + + + TIM2EN + TIM2 clock enable + 0 + 1 + + TIM2EN + read-write + + Disabled + The selected clock is disabled + 0 + + + Enabled + The selected clock is enabled + 1 + + + + + TIM3EN + TIM3 clock enable + 1 + 1 + + + + TIM4EN + TIM4 clock enable + 2 + 1 + + + + TIM5EN + TIM5 clock enable + 3 + 1 + + + + TIM6EN + TIM6 clock enable + 4 + 1 + + + + TIM7EN + TIM7 clock enable + 5 + 1 + + + + TIM12EN + TIM12 clock enable + 6 + 1 + + + + TIM13EN + TIM13 clock enable + 7 + 1 + + + + TIM14EN + TIM14 clock enable + 8 + 1 + + + + WWDGEN + Window watchdog clock enable + 11 + 1 + + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + + SPI3EN + SPI3 clock enable + 15 + 1 + + + + USART2EN + USART 2 clock enable + 17 + 1 + + + + USART3EN + USART3 clock enable + 18 + 1 + + + + UART4EN + UART4 clock enable + 19 + 1 + + + + UART5EN + UART5 clock enable + 20 + 1 + + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + + I2C3EN + I2C3 clock enable + 23 + 1 + + + + CAN1EN + CAN 1 clock enable + 25 + 1 + + + + CAN2EN + CAN 2 clock enable + 26 + 1 + + + + PWREN + Power interface clock enable + 28 + 1 + + + + DACEN + DAC interface clock enable + 29 + 1 + + + + UART7EN + UART7 clock enable + 30 + 1 + + + + UART8EN + UART8 clock enable + 31 + 1 + + + + SPDIFRXEN + SPDIF-RX clock enable + 16 + 1 + + + + CECEN + HDMI-CEN clock enable + 27 + 1 + + + + LPTIM1EN + Low power timer 1 clock enable + 9 + 1 + + + + I2C4EN + I2C4 clock enable + 24 + 1 + + + + + + APB2ENR + APB2ENR + APB2 peripheral clock enable register + 0x44 + 0x20 + read-write + 0x00000000 + + + TIM1EN + TIM1 clock enable + 0 + 1 + + TIM1EN + read-write + + Disabled + The selected clock is disabled + 0 + + + Enabled + The selected clock is enabled + 1 + + + + + TIM8EN + TIM8 clock enable + 1 + 1 + + + + USART1EN + USART1 clock enable + 4 + 1 + + + + USART6EN + USART6 clock enable + 5 + 1 + + + + ADC1EN + ADC1 clock enable + 8 + 1 + + + + ADC2EN + ADC2 clock enable + 9 + 1 + + + + ADC3EN + ADC3 clock enable + 10 + 1 + + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + + SPI4EN + SPI4 clock enable + 13 + 1 + + + + SYSCFGEN + System configuration controller clock enable + 14 + 1 + + + + TIM9EN + TIM9 clock enable + 16 + 1 + + + + TIM10EN + TIM10 clock enable + 17 + 1 + + + + TIM11EN + TIM11 clock enable + 18 + 1 + + + + SPI5EN + SPI5 clock enable + 20 + 1 + + + + SPI6EN + SPI6 clock enable + 21 + 1 + + + + SAI1EN + SAI1 clock enable + 22 + 1 + + + + LTDCEN + LTDC clock enable + 26 + 1 + + + + SAI2EN + SAI2 clock enable + 23 + 1 + + + + SDMMC1EN + SDMMC1 clock enable + 11 + 1 + + + + + + AHB1LPENR + AHB1LPENR + AHB1 peripheral clock enable in low power mode register + 0x50 + 0x20 + read-write + 0x7E6791FF + + + GPIOALPEN + IO port A clock enable during sleep mode + 0 + 1 + + GPIOALPEN + read-write + + DisabledInSleep + Selected module is disabled during Sleep mode + 0 + + + EnabledInSleep + Selected module is enabled during Sleep mode + 1 + + + + + GPIOBLPEN + IO port B clock enable during Sleep mode + 1 + 1 + + + + GPIOCLPEN + IO port C clock enable during Sleep mode + 2 + 1 + + + + GPIODLPEN + IO port D clock enable during Sleep mode + 3 + 1 + + + + GPIOELPEN + IO port E clock enable during Sleep mode + 4 + 1 + + + + GPIOFLPEN + IO port F clock enable during Sleep mode + 5 + 1 + + + + GPIOGLPEN + IO port G clock enable during Sleep mode + 6 + 1 + + + + GPIOHLPEN + IO port H clock enable during Sleep mode + 7 + 1 + + + + GPIOILPEN + IO port I clock enable during Sleep mode + 8 + 1 + + + + GPIOJLPEN + IO port J clock enable during Sleep mode + 9 + 1 + + + + GPIOKLPEN + IO port K clock enable during Sleep mode + 10 + 1 + + + + CRCLPEN + CRC clock enable during Sleep mode + 12 + 1 + + + + FLITFLPEN + Flash interface clock enable during Sleep mode + 15 + 1 + + + + SRAM1LPEN + SRAM 1interface clock enable during Sleep mode + 16 + 1 + + + + SRAM2LPEN + SRAM 2 interface clock enable during Sleep mode + 17 + 1 + + + + BKPSRAMLPEN + Backup SRAM interface clock enable during Sleep mode + 18 + 1 + + + + SRAM3LPEN + SRAM 3 interface clock enable during Sleep mode + 19 + 1 + + + + DMA1LPEN + DMA1 clock enable during Sleep mode + 21 + 1 + + + + DMA2LPEN + DMA2 clock enable during Sleep mode + 22 + 1 + + + + DMA2DLPEN + DMA2D clock enable during Sleep mode + 23 + 1 + + + + ETHMACLPEN + Ethernet MAC clock enable during Sleep mode + 25 + 1 + + + + ETHMACTXLPEN + Ethernet transmission clock enable during Sleep mode + 26 + 1 + + + + ETHMACRXLPEN + Ethernet reception clock enable during Sleep mode + 27 + 1 + + + + ETHMACPTPLPEN + Ethernet PTP clock enable during Sleep mode + 28 + 1 + + + + OTGHSLPEN + USB OTG HS clock enable during Sleep mode + 29 + 1 + + + + OTGHSULPILPEN + USB OTG HS ULPI clock enable during Sleep mode + 30 + 1 + + + + AXILPEN + AXI to AHB bridge clock enable during Sleep mode + 13 + 1 + + + DTCMLPEN + DTCM RAM interface clock enable during Sleep mode + 20 + 1 + + + + + AHB2LPENR + AHB2LPENR + AHB2 peripheral clock enable in low power mode register + 0x54 + 0x20 + read-write + 0x000000F1 + + + OTGFSLPEN + USB OTG FS clock enable during Sleep mode + 7 + 1 + + + + RNGLPEN + Random number generator clock enable during Sleep mode + 6 + 1 + + + + HASHLPEN + Hash modules clock enable during Sleep mode + 5 + 1 + + + + CRYPLPEN + Cryptography modules clock enable during Sleep mode + 4 + 1 + + + + DCMILPEN + Camera interface enable during Sleep mode + 0 + 1 + + DCMILPEN + read-write + + DisabledInSleep + Selected module is disabled during Sleep mode + 0 + + + EnabledInSleep + Selected module is enabled during Sleep mode + 1 + + + + + + + AHB3LPENR + AHB3LPENR + AHB3 peripheral clock enable in low power mode register + 0x58 + 0x20 + read-write + 0x00000001 + + + FMCLPEN + Flexible memory controller module clock enable during Sleep mode + 0 + 1 + + FMCLPEN + read-write + + DisabledInSleep + Selected module is disabled during Sleep mode + 0 + + + EnabledInSleep + Selected module is enabled during Sleep mode + 1 + + + + + QSPILPEN + Quand SPI memory controller clock enable during Sleep mode + 1 + 1 + + + + + + APB1LPENR + APB1LPENR + APB1 peripheral clock enable in low power mode register + 0x60 + 0x20 + read-write + 0x36FEC9FF + + + TIM2LPEN + TIM2 clock enable during Sleep mode + 0 + 1 + + TIM2LPEN + read-write + + DisabledInSleep + Selected module is disabled during Sleep mode + 0 + + + EnabledInSleep + Selected module is enabled during Sleep mode + 1 + + + + + TIM3LPEN + TIM3 clock enable during Sleep mode + 1 + 1 + + + + TIM4LPEN + TIM4 clock enable during Sleep mode + 2 + 1 + + + + TIM5LPEN + TIM5 clock enable during Sleep mode + 3 + 1 + + + + TIM6LPEN + TIM6 clock enable during Sleep mode + 4 + 1 + + + + TIM7LPEN + TIM7 clock enable during Sleep mode + 5 + 1 + + + + TIM12LPEN + TIM12 clock enable during Sleep mode + 6 + 1 + + + + TIM13LPEN + TIM13 clock enable during Sleep mode + 7 + 1 + + + + TIM14LPEN + TIM14 clock enable during Sleep mode + 8 + 1 + + + + WWDGLPEN + Window watchdog clock enable during Sleep mode + 11 + 1 + + + + SPI2LPEN + SPI2 clock enable during Sleep mode + 14 + 1 + + + + SPI3LPEN + SPI3 clock enable during Sleep mode + 15 + 1 + + + + USART2LPEN + USART2 clock enable during Sleep mode + 17 + 1 + + + + USART3LPEN + USART3 clock enable during Sleep mode + 18 + 1 + + + + UART4LPEN + UART4 clock enable during Sleep mode + 19 + 1 + + + + UART5LPEN + UART5 clock enable during Sleep mode + 20 + 1 + + + + I2C1LPEN + I2C1 clock enable during Sleep mode + 21 + 1 + + + + I2C2LPEN + I2C2 clock enable during Sleep mode + 22 + 1 + + + + I2C3LPEN + I2C3 clock enable during Sleep mode + 23 + 1 + + + + CAN1LPEN + CAN 1 clock enable during Sleep mode + 25 + 1 + + + + CAN2LPEN + CAN 2 clock enable during Sleep mode + 26 + 1 + + + + PWRLPEN + Power interface clock enable during Sleep mode + 28 + 1 + + + + DACLPEN + DAC interface clock enable during Sleep mode + 29 + 1 + + + + UART7LPEN + UART7 clock enable during Sleep mode + 30 + 1 + + + + UART8LPEN + UART8 clock enable during Sleep mode + 31 + 1 + + + + SPDIFRXLPEN + SPDIF-RX clock enable during sleep mode + 16 + 1 + + + + CECLPEN + HDMI-CEN clock enable during Sleep mode + 27 + 1 + + + + LPTIM1LPEN + low power timer 1 clock enable during Sleep mode + 9 + 1 + + + + I2C4LPEN + I2C4 clock enable during Sleep mode + 24 + 1 + + + + + + APB2LPENR + APB2LPENR + APB2 peripheral clock enabled in low power mode register + 0x64 + 0x20 + read-write + 0x00075F33 + + + TIM1LPEN + TIM1 clock enable during Sleep mode + 0 + 1 + + TIM1LPEN + read-write + + DisabledInSleep + Selected module is disabled during Sleep mode + 0 + + + EnabledInSleep + Selected module is enabled during Sleep mode + 1 + + + + + TIM8LPEN + TIM8 clock enable during Sleep mode + 1 + 1 + + + + USART1LPEN + USART1 clock enable during Sleep mode + 4 + 1 + + + + USART6LPEN + USART6 clock enable during Sleep mode + 5 + 1 + + + + ADC1LPEN + ADC1 clock enable during Sleep mode + 8 + 1 + + + + ADC2LPEN + ADC2 clock enable during Sleep mode + 9 + 1 + + + + ADC3LPEN + ADC 3 clock enable during Sleep mode + 10 + 1 + + + + SPI1LPEN + SPI 1 clock enable during Sleep mode + 12 + 1 + + + + SPI4LPEN + SPI 4 clock enable during Sleep mode + 13 + 1 + + + + SYSCFGLPEN + System configuration controller clock enable during Sleep mode + 14 + 1 + + + + TIM9LPEN + TIM9 clock enable during sleep mode + 16 + 1 + + + + TIM10LPEN + TIM10 clock enable during Sleep mode + 17 + 1 + + + + TIM11LPEN + TIM11 clock enable during Sleep mode + 18 + 1 + + + + SPI5LPEN + SPI 5 clock enable during Sleep mode + 20 + 1 + + + + SPI6LPEN + SPI 6 clock enable during Sleep mode + 21 + 1 + + + + SAI1LPEN + SAI1 clock enable during sleep mode + 22 + 1 + + + + LTDCLPEN + LTDC clock enable during sleep mode + 26 + 1 + + + + SAI2LPEN + SAI2 clock enable during sleep mode + 23 + 1 + + + + SDMMC1LPEN + SDMMC1 clock enable during Sleep mode + 11 + 1 + + + + + + BDCR + BDCR + Backup domain control register + 0x70 + 0x20 + 0x00000000 + + + BDRST + Backup domain software reset + 16 + 1 + read-write + + BDRST + read-write + + Disabled + Reset not activated + 0 + + + Enabled + Reset the entire RTC domain + 1 + + + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + RTCEN + read-write + + Disabled + RTC clock disabled + 0 + + + Enabled + RTC clock enabled + 1 + + + + + LSEBYP + External low-speed oscillator bypass + 2 + 1 + read-write + + LSEBYP + read-write + + NotBypassed + LSE crystal oscillator not bypassed + 0 + + + Bypassed + LSE crystal oscillator bypassed with external clock + 1 + + + + + LSERDY + External low-speed oscillator ready + 1 + 1 + read-only + + LSERDYR + read + + NotReady + LSE oscillator not ready + 0 + + + Ready + LSE oscillator ready + 1 + + + + + LSEON + External low-speed oscillator enable + 0 + 1 + read-write + + LSEON + read-write + + Off + LSE oscillator Off + 0 + + + On + LSE oscillator On + 1 + + + + + LSEDRV + LSE oscillator drive capability + 3 + 2 + read-write + + LSEDRV + read-write + + Low + Low drive capacity + 0 + + + MediumHigh + Medium-high drive capacity + 1 + + + MediumLow + Medium-low drive capacity + 2 + + + High + High drive capacity + 3 + + + + + RTCSEL + RTC clock source selection + 8 + 2 + + RTCSEL + read-write + + NoClock + No clock + 0 + + + LSE + LSE oscillator clock used as RTC clock + 1 + + + LSI + LSI oscillator clock used as RTC clock + 2 + + + HSE + HSE oscillator clock divided by a prescaler used as RTC clock + 3 + + + + + + + CSR + CSR + clock control & status register + 0x74 + 0x20 + 0x0E000000 + + + LPWRRSTF + Low-power reset flag + 31 + 1 + read-write + + + + WWDGRSTF + Window watchdog reset flag + 30 + 1 + read-write + + + + WDGRSTF + Independent watchdog reset flag + 29 + 1 + read-write + + + + SFTRSTF + Software reset flag + 28 + 1 + read-write + + + + PORRSTF + POR/PDR reset flag + 27 + 1 + read-write + + + + PADRSTF + PIN reset flag + 26 + 1 + read-write + + + + BORRSTF + BOR reset flag + 25 + 1 + read-write + + BORRSTFR + read + + NoReset + No reset has occured + 0 + + + Reset + A reset has occured + 1 + + + + + RMVF + Remove reset flag + 24 + 1 + read-write + + RMVFW + write + + Clear + Clears the reset flag + 1 + + + + + LSIRDY + Internal low-speed oscillator ready + 1 + 1 + read-only + + LSIRDYR + read + + NotReady + LSI oscillator not ready + 0 + + + Ready + LSI oscillator ready + 1 + + + + + LSION + Internal low-speed oscillator enable + 0 + 1 + read-write + + LSION + read-write + + Off + LSI oscillator Off + 0 + + + On + LSI oscillator On + 1 + + + + + + + SSCGR + SSCGR + spread spectrum clock generation register + 0x80 + 0x20 + read-write + 0x00000000 + + + SSCGEN + Spread spectrum modulation enable + 31 + 1 + + SSCGEN + read-write + + Disabled + Spread spectrum modulation disabled + 0 + + + Enabled + Spread spectrum modulation enabled + 1 + + + + + SPREADSEL + Spread Select + 30 + 1 + + SPREADSEL + read-write + + Center + Center spread + 0 + + + Down + Down spread + 1 + + + + + INCSTEP + Incrementation step + 13 + 15 + + + 0 + 32767 + + + + + MODPER + Modulation period + 0 + 13 + + + 0 + 8191 + + + + + + + PLLI2SCFGR + PLLI2SCFGR + PLLI2S configuration register + 0x84 + 0x20 + read-write + 0x20003000 + + + PLLI2SR + PLLI2S division factor for I2S clocks + 28 + 3 + + + 2 + 7 + + + + + PLLI2SQ + PLLI2S division factor for SAI1 clock + 24 + 4 + + + 2 + 15 + + + + + PLLI2SN + PLLI2S multiplication factor for VCO + 6 + 9 + + + 50 + 432 + + + + + PLLI2SP + PLLI2S division factor for SPDIFRX clock + 16 + 2 + + PLLI2SP + read-write + + Div2 + PLL*P=2 + 0 + + + Div4 + PLL*P=4 + 1 + + + Div6 + PLL*P=6 + 2 + + + Div8 + PLL*P=8 + 3 + + + + + + + PLLSAICFGR + PLLSAICFGR + PLL configuration register + 0x88 + 0x20 + read-write + 0x20003000 + + + PLLSAIN + PLLSAI division factor for VCO + 6 + 9 + + + 50 + 432 + + + + + PLLSAIP + PLLSAI division factor for 48MHz clock + 16 + 2 + + PLLSAIP + read-write + + Div2 + PLL*P=2 + 0 + + + Div4 + PLL*P=4 + 1 + + + Div6 + PLL*P=6 + 2 + + + Div8 + PLL*P=8 + 3 + + + + + PLLSAIQ + PLLSAI division factor for SAI clock + 24 + 4 + + + 2 + 15 + + + + + PLLSAIR + PLLSAI division factor for LCD clock + 28 + 3 + + + 2 + 7 + + + + + + + DCKCFGR1 + DKCFGR1 + dedicated clocks configuration register + 0x8C + 0x20 + read-write + 0x00000000 + + + PLLI2SDIVQ + PLLI2S division factor for SAI1 clock + 0 + 5 + + PLLI2SDIVQ + read-write + + Div1 + PLLI2SDIVQ = /1 + 0 + + + Div2 + PLLI2SDIVQ = /2 + 1 + + + Div3 + PLLI2SDIVQ = /3 + 2 + + + Div4 + PLLI2SDIVQ = /4 + 3 + + + Div5 + PLLI2SDIVQ = /5 + 4 + + + Div6 + PLLI2SDIVQ = /6 + 5 + + + Div7 + PLLI2SDIVQ = /7 + 6 + + + Div8 + PLLI2SDIVQ = /8 + 7 + + + Div9 + PLLI2SDIVQ = /9 + 8 + + + Div10 + PLLI2SDIVQ = /10 + 9 + + + Div11 + PLLI2SDIVQ = /11 + 10 + + + Div12 + PLLI2SDIVQ = /12 + 11 + + + Div13 + PLLI2SDIVQ = /13 + 12 + + + Div14 + PLLI2SDIVQ = /14 + 13 + + + Div15 + PLLI2SDIVQ = /15 + 14 + + + Div16 + PLLI2SDIVQ = /16 + 15 + + + Div17 + PLLI2SDIVQ = /17 + 16 + + + Div18 + PLLI2SDIVQ = /18 + 17 + + + Div19 + PLLI2SDIVQ = /19 + 18 + + + Div20 + PLLI2SDIVQ = /20 + 19 + + + Div21 + PLLI2SDIVQ = /21 + 20 + + + Div22 + PLLI2SDIVQ = /22 + 21 + + + Div23 + PLLI2SDIVQ = /23 + 22 + + + Div24 + PLLI2SDIVQ = /24 + 23 + + + Div25 + PLLI2SDIVQ = /25 + 24 + + + Div26 + PLLI2SDIVQ = /26 + 25 + + + Div27 + PLLI2SDIVQ = /27 + 26 + + + Div28 + PLLI2SDIVQ = /28 + 27 + + + Div29 + PLLI2SDIVQ = /29 + 28 + + + Div30 + PLLI2SDIVQ = /30 + 29 + + + Div31 + PLLI2SDIVQ = /31 + 30 + + + Div32 + PLLI2SDIVQ = /32 + 31 + + + + + PLLSAIDIVQ + PLLSAI division factor for SAI1 clock + 8 + 5 + + PLLSAIDIVQ + read-write + + Div1 + PLLSAIDIVQ = /1 + 0 + + + Div2 + PLLSAIDIVQ = /2 + 1 + + + Div3 + PLLSAIDIVQ = /3 + 2 + + + Div4 + PLLSAIDIVQ = /4 + 3 + + + Div5 + PLLSAIDIVQ = /5 + 4 + + + Div6 + PLLSAIDIVQ = /6 + 5 + + + Div7 + PLLSAIDIVQ = /7 + 6 + + + Div8 + PLLSAIDIVQ = /8 + 7 + + + Div9 + PLLSAIDIVQ = /9 + 8 + + + Div10 + PLLSAIDIVQ = /10 + 9 + + + Div11 + PLLSAIDIVQ = /11 + 10 + + + Div12 + PLLSAIDIVQ = /12 + 11 + + + Div13 + PLLSAIDIVQ = /13 + 12 + + + Div14 + PLLSAIDIVQ = /14 + 13 + + + Div15 + PLLSAIDIVQ = /15 + 14 + + + Div16 + PLLSAIDIVQ = /16 + 15 + + + Div17 + PLLSAIDIVQ = /17 + 16 + + + Div18 + PLLSAIDIVQ = /18 + 17 + + + Div19 + PLLSAIDIVQ = /19 + 18 + + + Div20 + PLLSAIDIVQ = /20 + 19 + + + Div21 + PLLSAIDIVQ = /21 + 20 + + + Div22 + PLLSAIDIVQ = /22 + 21 + + + Div23 + PLLSAIDIVQ = /23 + 22 + + + Div24 + PLLSAIDIVQ = /24 + 23 + + + Div25 + PLLSAIDIVQ = /25 + 24 + + + Div26 + PLLSAIDIVQ = /26 + 25 + + + Div27 + PLLSAIDIVQ = /27 + 26 + + + Div28 + PLLSAIDIVQ = /28 + 27 + + + Div29 + PLLSAIDIVQ = /29 + 28 + + + Div30 + PLLSAIDIVQ = /30 + 29 + + + Div31 + PLLSAIDIVQ = /31 + 30 + + + Div32 + PLLSAIDIVQ = /32 + 31 + + + + + PLLSAIDIVR + division factor for LCD_CLK + 16 + 2 + + PLLSAIDIVR + read-write + + Div2 + PLLSAIDIVR = /2 + 0 + + + Div4 + PLLSAIDIVR = /4 + 1 + + + Div8 + PLLSAIDIVR = /8 + 2 + + + Div16 + PLLSAIDIVR = /16 + 3 + + + + + SAI1SEL + SAI1 clock source selection + 20 + 2 + + SAI1SEL + read-write + + PLLSAI + SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + 0 + + + PLLI2S + SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + 1 + + + AFIF + SAI1 clock frequency = Alternate function input frequency + 2 + + + HSI_HSE + SAI1 clock frequency = HSI or HSE + 3 + + + + + SAI2SEL + SAI2 clock source selection + 22 + 2 + + SAI2SEL + read-write + + PLLSAI + SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + 0 + + + PLLI2S + SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + 1 + + + AFIF + SAI2 clock frequency = Alternate function input frequency + 2 + + + HSI_HSE + SAI2 clock frequency = HSI or HSE + 3 + + + + + TIMPRE + Timers clocks prescalers selection + 24 + 1 + + TIMPRE + read-write + + Mul1Or2 + If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx + 0 + + + Mul1Or4 + If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx + 1 + + + + + + + DCKCFGR2 + DKCFGR2 + dedicated clocks configuration register + 0x90 + 0x20 + read-write + 0x00000000 + + + USART1SEL + USART 1 clock source selection + 0 + 2 + + USART1SEL + read-write + + APB2 + APB2 clock (PCLK2) is selected as USART clock + 0 + + + SYSCLK + System clock is selected as USART clock + 1 + + + HSI + HSI clock is selected as USART clock + 2 + + + LSE + LSE clock is selected as USART clock + 3 + + + + + USART2SEL + USART 2 clock source selection + 2 + 2 + + USART2SEL + read-write + + APB1 + APB1 clock (PCLK1) is selected as USART clock + 0 + + + SYSCLK + System clock is selected as USART clock + 1 + + + HSI + HSI clock is selected as USART clock + 2 + + + LSE + LSE clock is selected as USART clock + 3 + + + + + USART3SEL + USART 3 clock source selection + 4 + 2 + + + + UART4SEL + UART 4 clock source selection + 6 + 2 + + + + UART5SEL + UART 5 clock source selection + 8 + 2 + + + + USART6SEL + USART 6 clock source selection + 10 + 2 + + + + UART7SEL + UART 7 clock source selection + 12 + 2 + + + + UART8SEL + UART 8 clock source selection + 14 + 2 + + + + I2C1SEL + I2C1 clock source selection + 16 + 2 + + I2C1SEL + read-write + + APB + APB clock selected as I2C clock + 0 + + + SYSCLK + System clock selected as I2C clock + 1 + + + HSI + HSI clock selected as I2C clock + 2 + + + + + I2C2SEL + I2C2 clock source selection + 18 + 2 + + + + I2C3SEL + I2C3 clock source selection + 20 + 2 + + + + I2C4SEL + I2C4 clock source selection + 22 + 2 + + + + LPTIM1SEL + Low power timer 1 clock source selection + 24 + 2 + + LPTIM1SEL + read-write + + APB1 + APB1 clock (PCLK1) selected as LPTILM1 clock + 0 + + + LSI + LSI clock is selected as LPTILM1 clock + 1 + + + HSI + HSI clock is selected as LPTILM1 clock + 2 + + + LSE + LSE clock is selected as LPTILM1 clock + 3 + + + + + CECSEL + HDMI-CEC clock source selection + 26 + 1 + + CECSEL + read-write + + LSE + LSE clock is selected as HDMI-CEC clock + 0 + + + HSI_Div488 + HSI divided by 488 clock is selected as HDMI-CEC clock + 1 + + + + + CK48MSEL + 48MHz clock source selection + 27 + 1 + + CK48MSEL + read-write + + PLL + 48MHz clock from PLL is selected + 0 + + + PLLSAI + 48MHz clock from PLLSAI is selected + 1 + + + + + SDMMC1SEL + SDMMC clock source selection + 28 + 1 + + SDMMC1SEL + read-write + + CK48M + 48 MHz clock is selected as SD clock + 0 + + + SYSCLK + System clock is selected as SD clock + 1 + + + + + + + + + GPIOD + 0x40020C00 + + + GPIOC + 0x40020800 + + + GPIOK + 0x40022800 + + + GPIOJ + 0x40022400 + + + GPIOI + 0x40022000 + + + GPIOH + 0x40021C00 + + + GPIOG + 0x40021800 + + + GPIOF + 0x40021400 + + + GPIOE + 0x40021000 + + + GPIOB + 0x40020400 + + + GPIOA + General-purpose I/Os + GPIO + 0x40020000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xA8000000 + + + MODER15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + + MODER14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + + MODER13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + + MODER12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + + MODER11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + + MODER10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + + MODER9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + + MODER8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + + MODER7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + + MODER6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + + MODER5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + + MODER4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + + MODER3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + + MODER2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + + MODER1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + + MODER0 + Port x configuration bits (y = 0..15) + 0 + 2 + + MODER0 + read-write + + Input + Input mode (reset state) + 0 + + + Output + General purpose output mode + 1 + + + Alternate + Alternate function mode + 2 + + + Analog + Analog mode + 3 + + + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = 0..15) + 15 + 1 + + + + OT14 + Port x configuration bits (y = 0..15) + 14 + 1 + + + + OT13 + Port x configuration bits (y = 0..15) + 13 + 1 + + + + OT12 + Port x configuration bits (y = 0..15) + 12 + 1 + + + + OT11 + Port x configuration bits (y = 0..15) + 11 + 1 + + + + OT10 + Port x configuration bits (y = 0..15) + 10 + 1 + + + + OT9 + Port x configuration bits (y = 0..15) + 9 + 1 + + + + OT8 + Port x configuration bits (y = 0..15) + 8 + 1 + + + + OT7 + Port x configuration bits (y = 0..15) + 7 + 1 + + + + OT6 + Port x configuration bits (y = 0..15) + 6 + 1 + + + + OT5 + Port x configuration bits (y = 0..15) + 5 + 1 + + + + OT4 + Port x configuration bits (y = 0..15) + 4 + 1 + + + + OT3 + Port x configuration bits (y = 0..15) + 3 + 1 + + + + OT2 + Port x configuration bits (y = 0..15) + 2 + 1 + + + + OT1 + Port x configuration bits (y = 0..15) + 1 + 1 + + + + OT0 + Port x configuration bits (y = 0..15) + 0 + 1 + + OT0 + read-write + + PushPull + Output push-pull (reset state) + 0 + + + OpenDrain + Output open-drain + 1 + + + + + + + OSPEEDR + GPIOB_OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + + OSPEEDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + + OSPEEDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + + OSPEEDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + + OSPEEDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + + OSPEEDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + + OSPEEDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + + OSPEEDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + + OSPEEDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + + OSPEEDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + + OSPEEDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + + OSPEEDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + + OSPEEDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + + OSPEEDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + + OSPEEDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + + OSPEEDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + OSPEEDR0 + read-write + + LowSpeed + Low speed + 0 + + + MediumSpeed + Medium speed + 1 + + + HighSpeed + High speed + 2 + + + VeryHighSpeed + Very high speed + 3 + + + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x64000000 + + + PUPDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + + PUPDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + + PUPDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + + PUPDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + + PUPDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + + PUPDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + + PUPDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + + PUPDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + + PUPDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + + PUPDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + + PUPDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + + PUPDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + + PUPDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + + PUPDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + + PUPDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + + PUPDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + PUPDR0 + read-write + + Floating + No pull-up, pull-down + 0 + + + PullUp + Pull-up + 1 + + + PullDown + Pull-down + 2 + + + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = 0..15) + 15 + 1 + + + + IDR14 + Port input data (y = 0..15) + 14 + 1 + + + + IDR13 + Port input data (y = 0..15) + 13 + 1 + + + + IDR12 + Port input data (y = 0..15) + 12 + 1 + + + + IDR11 + Port input data (y = 0..15) + 11 + 1 + + + + IDR10 + Port input data (y = 0..15) + 10 + 1 + + + + IDR9 + Port input data (y = 0..15) + 9 + 1 + + + + IDR8 + Port input data (y = 0..15) + 8 + 1 + + + + IDR7 + Port input data (y = 0..15) + 7 + 1 + + + + IDR6 + Port input data (y = 0..15) + 6 + 1 + + + + IDR5 + Port input data (y = 0..15) + 5 + 1 + + + + IDR4 + Port input data (y = 0..15) + 4 + 1 + + + + IDR3 + Port input data (y = 0..15) + 3 + 1 + + + + IDR2 + Port input data (y = 0..15) + 2 + 1 + + + + IDR1 + Port input data (y = 0..15) + 1 + 1 + + + + IDR0 + Port input data (y = 0..15) + 0 + 1 + + IDR0 + read + + Low + Input is logic low + 0 + + + High + Input is logic high + 1 + + + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = 0..15) + 15 + 1 + + + + ODR14 + Port output data (y = 0..15) + 14 + 1 + + + + ODR13 + Port output data (y = 0..15) + 13 + 1 + + + + ODR12 + Port output data (y = 0..15) + 12 + 1 + + + + ODR11 + Port output data (y = 0..15) + 11 + 1 + + + + ODR10 + Port output data (y = 0..15) + 10 + 1 + + + + ODR9 + Port output data (y = 0..15) + 9 + 1 + + + + ODR8 + Port output data (y = 0..15) + 8 + 1 + + + + ODR7 + Port output data (y = 0..15) + 7 + 1 + + + + ODR6 + Port output data (y = 0..15) + 6 + 1 + + + + ODR5 + Port output data (y = 0..15) + 5 + 1 + + + + ODR4 + Port output data (y = 0..15) + 4 + 1 + + + + ODR3 + Port output data (y = 0..15) + 3 + 1 + + + + ODR2 + Port output data (y = 0..15) + 2 + 1 + + + + ODR1 + Port output data (y = 0..15) + 1 + 1 + + + + ODR0 + Port output data (y = 0..15) + 0 + 1 + + ODR0 + read-write + + Low + Set output to logic low + 0 + + + High + Set output to logic high + 1 + + + + + + + BSRR + BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = 0..15) + 31 + 1 + + + + BR14 + Port x reset bit y (y = 0..15) + 30 + 1 + + + + BR13 + Port x reset bit y (y = 0..15) + 29 + 1 + + + + BR12 + Port x reset bit y (y = 0..15) + 28 + 1 + + + + BR11 + Port x reset bit y (y = 0..15) + 27 + 1 + + + + BR10 + Port x reset bit y (y = 0..15) + 26 + 1 + + + + BR9 + Port x reset bit y (y = 0..15) + 25 + 1 + + + + BR8 + Port x reset bit y (y = 0..15) + 24 + 1 + + + + BR7 + Port x reset bit y (y = 0..15) + 23 + 1 + + + + BR6 + Port x reset bit y (y = 0..15) + 22 + 1 + + + + BR5 + Port x reset bit y (y = 0..15) + 21 + 1 + + + + BR4 + Port x reset bit y (y = 0..15) + 20 + 1 + + + + BR3 + Port x reset bit y (y = 0..15) + 19 + 1 + + + + BR2 + Port x reset bit y (y = 0..15) + 18 + 1 + + + + BR1 + Port x reset bit y (y = 0..15) + 17 + 1 + + + + BR0 + Port x set bit y (y= 0..15) + 16 + 1 + + BR0W + write + + Reset + Resets the corresponding ODRx bit + 1 + + + + + BS15 + Port x set bit y (y= 0..15) + 15 + 1 + + + + BS14 + Port x set bit y (y= 0..15) + 14 + 1 + + + + BS13 + Port x set bit y (y= 0..15) + 13 + 1 + + + + BS12 + Port x set bit y (y= 0..15) + 12 + 1 + + + + BS11 + Port x set bit y (y= 0..15) + 11 + 1 + + + + BS10 + Port x set bit y (y= 0..15) + 10 + 1 + + + + BS9 + Port x set bit y (y= 0..15) + 9 + 1 + + + + BS8 + Port x set bit y (y= 0..15) + 8 + 1 + + + + BS7 + Port x set bit y (y= 0..15) + 7 + 1 + + + + BS6 + Port x set bit y (y= 0..15) + 6 + 1 + + + + BS5 + Port x set bit y (y= 0..15) + 5 + 1 + + + + BS4 + Port x set bit y (y= 0..15) + 4 + 1 + + + + BS3 + Port x set bit y (y= 0..15) + 3 + 1 + + + + BS2 + Port x set bit y (y= 0..15) + 2 + 1 + + + + BS1 + Port x set bit y (y= 0..15) + 1 + 1 + + + + BS0 + Port x set bit y (y= 0..15) + 0 + 1 + + BS0W + write + + Set + Sets the corresponding ODRx bit + 1 + + + + + + + LCKR + LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= 0..15) + 16 + 1 + + LCKK + read-write + + NotActive + Port configuration lock key not active + 0 + + + Active + Port configuration lock key active + 1 + + + + + LCK15 + Port x lock bit y (y= 0..15) + 15 + 1 + + + + LCK14 + Port x lock bit y (y= 0..15) + 14 + 1 + + + + LCK13 + Port x lock bit y (y= 0..15) + 13 + 1 + + + + LCK12 + Port x lock bit y (y= 0..15) + 12 + 1 + + + + LCK11 + Port x lock bit y (y= 0..15) + 11 + 1 + + + + LCK10 + Port x lock bit y (y= 0..15) + 10 + 1 + + + + LCK9 + Port x lock bit y (y= 0..15) + 9 + 1 + + + + LCK8 + Port x lock bit y (y= 0..15) + 8 + 1 + + + + LCK7 + Port x lock bit y (y= 0..15) + 7 + 1 + + + + LCK6 + Port x lock bit y (y= 0..15) + 6 + 1 + + + + LCK5 + Port x lock bit y (y= 0..15) + 5 + 1 + + + + LCK4 + Port x lock bit y (y= 0..15) + 4 + 1 + + + + LCK3 + Port x lock bit y (y= 0..15) + 3 + 1 + + + + LCK2 + Port x lock bit y (y= 0..15) + 2 + 1 + + + + LCK1 + Port x lock bit y (y= 0..15) + 1 + 1 + + + + LCK0 + Port x lock bit y (y= 0..15) + 0 + 1 + + LCK0 + read-write + + Unlocked + Port configuration not locked + 0 + + + Locked + Port configuration locked + 1 + + + + + + + AFRL + AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x bit y (y = 0..7) + 28 + 4 + + + + AFRL6 + Alternate function selection for port x bit y (y = 0..7) + 24 + 4 + + + + AFRL5 + Alternate function selection for port x bit y (y = 0..7) + 20 + 4 + + + + AFRL4 + Alternate function selection for port x bit y (y = 0..7) + 16 + 4 + + + + AFRL3 + Alternate function selection for port x bit y (y = 0..7) + 12 + 4 + + + + AFRL2 + Alternate function selection for port x bit y (y = 0..7) + 8 + 4 + + + + AFRL1 + Alternate function selection for port x bit y (y = 0..7) + 4 + 4 + + + + AFRL0 + Alternate function selection for port x bit y (y = 0..7) + 0 + 4 + + AFRL0 + read-write + + AF0 + AF0 + 0 + + + AF1 + AF1 + 1 + + + AF2 + AF2 + 2 + + + AF3 + AF3 + 3 + + + AF4 + AF4 + 4 + + + AF5 + AF5 + 5 + + + AF6 + AF6 + 6 + + + AF7 + AF7 + 7 + + + AF8 + AF8 + 8 + + + AF9 + AF9 + 9 + + + AF10 + AF10 + 10 + + + AF11 + AF11 + 11 + + + AF12 + AF12 + 12 + + + AF13 + AF13 + 13 + + + AF14 + AF14 + 14 + + + AF15 + AF15 + 15 + + + + + + + AFRH + AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x bit y (y = 8..15) + 28 + 4 + + + + AFRH14 + Alternate function selection for port x bit y (y = 8..15) + 24 + 4 + + + + AFRH13 + Alternate function selection for port x bit y (y = 8..15) + 20 + 4 + + + + AFRH12 + Alternate function selection for port x bit y (y = 8..15) + 16 + 4 + + + + AFRH11 + Alternate function selection for port x bit y (y = 8..15) + 12 + 4 + + + + AFRH10 + Alternate function selection for port x bit y (y = 8..15) + 8 + 4 + + + + AFRH9 + Alternate function selection for port x bit y (y = 8..15) + 4 + 4 + + + + AFRH8 + Alternate function selection for port x bit y (y = 8..15) + 0 + 4 + + AFRH8 + read-write + + AF0 + AF0 + 0 + + + AF1 + AF1 + 1 + + + AF2 + AF2 + 2 + + + AF3 + AF3 + 3 + + + AF4 + AF4 + 4 + + + AF5 + AF5 + 5 + + + AF6 + AF6 + 6 + + + AF7 + AF7 + 7 + + + AF8 + AF8 + 8 + + + AF9 + AF9 + 9 + + + AF10 + AF10 + 10 + + + AF11 + AF11 + 11 + + + AF12 + AF12 + 12 + + + AF13 + AF13 + 13 + + + AF14 + AF14 + 14 + + + AF15 + AF15 + 15 + + + + + + + BRR + BRR + GPIO port bit reset register + 0x28 + 0x20 + read-write + 0x00000000 + + + BR0 + Port A Reset bit 0 + 0 + 1 + + + BR1 + Port A Reset bit 1 + 1 + 1 + + + BR2 + Port A Reset bit 2 + 2 + 1 + + + BR3 + Port A Reset bit 3 + 3 + 1 + + + BR4 + Port A Reset bit 4 + 4 + 1 + + + BR5 + Port A Reset bit 5 + 5 + 1 + + + BR6 + Port A Reset bit 6 + 6 + 1 + + + BR7 + Port A Reset bit 7 + 7 + 1 + + + BR8 + Port A Reset bit 8 + 8 + 1 + + + BR9 + Port A Reset bit 9 + 9 + 1 + + + BR10 + Port A Reset bit 10 + 10 + 1 + + + BR11 + Port A Reset bit 11 + 11 + 1 + + + BR12 + Port A Reset bit 12 + 12 + 1 + + + BR13 + Port A Reset bit 13 + 13 + 1 + + + BR14 + Port A Reset bit 14 + 14 + 1 + + + BR15 + Port A Reset bit 15 + 15 + 1 + + + + + + + SYSCFG + System configuration controller + SYSCFG + 0x40013800 + + 0x0 + 0x400 + registers + + + + MEMRMP + MEMRM + memory remap register + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_BOOT + Memory mapping selection + 0 + 1 + + + SWP_FMC + FMC memory mapping swap + 10 + 2 + + + + + PMC + PMC + peripheral mode configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + MII_RMII_SEL + Ethernet PHY interface selection + 23 + 1 + + + ADC1DC2 + ADC1DC2 + 16 + 1 + + + ADC2DC2 + ADC2DC2 + 17 + 1 + + + ADC3DC2 + ADC3DC2 + 18 + 1 + + + + + EXTICR1 + EXTICR1 + external interrupt configuration register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + EXTI3 + EXTI x configuration (x = 0 to 3) + 12 + 4 + + + EXTI2 + EXTI x configuration (x = 0 to 3) + 8 + 4 + + + EXTI1 + EXTI x configuration (x = 0 to 3) + 4 + 4 + + + EXTI0 + EXTI x configuration (x = 0 to 3) + 0 + 4 + + + + + EXTICR2 + EXTICR2 + external interrupt configuration register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + EXTI7 + EXTI x configuration (x = 4 to 7) + 12 + 4 + + + EXTI6 + EXTI x configuration (x = 4 to 7) + 8 + 4 + + + EXTI5 + EXTI x configuration (x = 4 to 7) + 4 + 4 + + + EXTI4 + EXTI x configuration (x = 4 to 7) + 0 + 4 + + + + + EXTICR3 + EXTICR3 + external interrupt configuration register 3 + 0x10 + 0x20 + read-write + 0x00000000 + + + EXTI11 + EXTI x configuration (x = 8 to 11) + 12 + 4 + + + EXTI10 + EXTI10 + 8 + 4 + + + EXTI9 + EXTI x configuration (x = 8 to 11) + 4 + 4 + + + EXTI8 + EXTI x configuration (x = 8 to 11) + 0 + 4 + + + + + EXTICR4 + EXTICR4 + external interrupt configuration register 4 + 0x14 + 0x20 + read-write + 0x00000000 + + + EXTI15 + EXTI x configuration (x = 12 to 15) + 12 + 4 + + + EXTI14 + EXTI x configuration (x = 12 to 15) + 8 + 4 + + + EXTI13 + EXTI x configuration (x = 12 to 15) + 4 + 4 + + + EXTI12 + EXTI x configuration (x = 12 to 15) + 0 + 4 + + + + + CMPCR + CMPCR + Compensation cell control register + 0x20 + 0x20 + read-only + 0x00000000 + + + READY + READY + 8 + 1 + + + CMP_PD + Compensation cell power-down + 0 + 1 + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + BIDIMODE + Bidirectional data mode enable + 15 + 1 + + BIDIMODE + read-write + + Unidirectional + 2-line unidirectional data mode selected + 0 + + + Bidirectional + 1-line bidirectional data mode selected + 1 + + + + + BIDIOE + Output enable in bidirectional mode + 14 + 1 + + BIDIOE + read-write + + OutputDisabled + Output disabled (receive-only mode) + 0 + + + OutputEnabled + Output enabled (transmit-only mode) + 1 + + + + + CRCEN + Hardware CRC calculation enable + 13 + 1 + + CRCEN + read-write + + Disabled + CRC calculation disabled + 0 + + + Enabled + CRC calculation enabled + 1 + + + + + CRCNEXT + CRC transfer next + 12 + 1 + + CRCNEXT + read-write + + TxBuffer + Next transmit value is from Tx buffer + 0 + + + CRC + Next transmit value is from Tx CRC register + 1 + + + + + CRCL + CRC length + 11 + 1 + + CRCL + read-write + + EightBit + 8-bit CRC length + 0 + + + SixteenBit + 16-bit CRC length + 1 + + + + + RXONLY + Receive only + 10 + 1 + + RXONLY + read-write + + FullDuplex + Full duplex (Transmit and receive) + 0 + + + OutputDisabled + Output disabled (Receive-only mode) + 1 + + + + + SSM + Software slave management + 9 + 1 + + SSM + read-write + + Disabled + Software slave management disabled + 0 + + + Enabled + Software slave management enabled + 1 + + + + + SSI + Internal slave select + 8 + 1 + + SSI + read-write + + SlaveSelected + 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored + 0 + + + SlaveNotSelected + 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored + 1 + + + + + LSBFIRST + Frame format + 7 + 1 + + LSBFIRST + read-write + + MSBFirst + Data is transmitted/received with the MSB first + 0 + + + LSBFirst + Data is transmitted/received with the LSB first + 1 + + + + + SPE + SPI enable + 6 + 1 + + SPE + read-write + + Disabled + Peripheral disabled + 0 + + + Enabled + Peripheral enabled + 1 + + + + + BR + Baud rate control + 3 + 3 + + BR + read-write + + Div2 + f_PCLK / 2 + 0 + + + Div4 + f_PCLK / 4 + 1 + + + Div8 + f_PCLK / 8 + 2 + + + Div16 + f_PCLK / 16 + 3 + + + Div32 + f_PCLK / 32 + 4 + + + Div64 + f_PCLK / 64 + 5 + + + Div128 + f_PCLK / 128 + 6 + + + Div256 + f_PCLK / 256 + 7 + + + + + MSTR + Master selection + 2 + 1 + + MSTR + read-write + + Slave + Slave configuration + 0 + + + Master + Master configuration + 1 + + + + + CPOL + Clock polarity + 1 + 1 + + CPOL + read-write + + IdleLow + CK to 0 when idle + 0 + + + IdleHigh + CK to 1 when idle + 1 + + + + + CPHA + Clock phase + 0 + 1 + + CPHA + read-write + + FirstEdge + The first clock transition is the first data capture edge + 0 + + + SecondEdge + The second clock transition is the first data capture edge + 1 + + + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000700 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + RXDMAEN + read-write + + Disabled + Rx buffer DMA disabled + 0 + + + Enabled + Rx buffer DMA enabled + 1 + + + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + TXDMAEN + read-write + + Disabled + Tx buffer DMA disabled + 0 + + + Enabled + Tx buffer DMA enabled + 1 + + + + + SSOE + SS output enable + 2 + 1 + + SSOE + read-write + + Disabled + SS output is disabled in master mode + 0 + + + Enabled + SS output is enabled in master mode + 1 + + + + + NSSP + NSS pulse management + 3 + 1 + + NSSP + read-write + + NoPulse + No NSS pulse + 0 + + + PulseGenerated + NSS pulse generated + 1 + + + + + FRF + Frame format + 4 + 1 + + FRF + read-write + + Motorola + SPI Motorola mode + 0 + + + TI + SPI TI mode + 1 + + + + + ERRIE + Error interrupt enable + 5 + 1 + + ERRIE + read-write + + Masked + Error interrupt masked + 0 + + + NotMasked + Error interrupt not masked + 1 + + + + + RXNEIE + RX buffer not empty interrupt enable + 6 + 1 + + RXNEIE + read-write + + Masked + RXE interrupt masked + 0 + + + NotMasked + RXE interrupt not masked + 1 + + + + + TXEIE + Tx buffer empty interrupt enable + 7 + 1 + + TXEIE + read-write + + Masked + TXE interrupt masked + 0 + + + NotMasked + TXE interrupt not masked + 1 + + + + + DS + Data size + 8 + 4 + + DS + read-write + + FourBit + 4-bit + 3 + + + FiveBit + 5-bit + 4 + + + SixBit + 6-bit + 5 + + + SevenBit + 7-bit + 6 + + + EightBit + 8-bit + 7 + + + NineBit + 9-bit + 8 + + + TenBit + 10-bit + 9 + + + ElevenBit + 11-bit + 10 + + + TwelveBit + 12-bit + 11 + + + ThirteenBit + 13-bit + 12 + + + FourteenBit + 14-bit + 13 + + + FifteenBit + 15-bit + 14 + + + SixteenBit + 16-bit + 15 + + + + + FRXTH + FIFO reception threshold + 12 + 1 + + FRXTH + read-write + + Half + RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) + 0 + + + Quarter + RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + 1 + + + + + LDMA_RX + Last DMA transfer for reception + 13 + 1 + + LDMA_RX + read-write + + Even + Number of data to transfer for receive is even + 0 + + + Odd + Number of data to transfer for receive is odd + 1 + + + + + LDMA_TX + Last DMA transfer for transmission + 14 + 1 + + LDMA_TX + read-write + + Even + Number of data to transfer for transmit is even + 0 + + + Odd + Number of data to transfer for transmit is odd + 1 + + + + + + + SR + SR + status register + 0x8 + 0x20 + 0x00000002 + + + FRE + Frame format error + 8 + 1 + read-only + + FRER + read + + NoError + No frame format error + 0 + + + Error + A frame format error occurred + 1 + + + + + BSY + Busy flag + 7 + 1 + read-only + + BSYR + read + + NotBusy + SPI not busy + 0 + + + Busy + SPI busy + 1 + + + + + OVR + Overrun flag + 6 + 1 + read-only + + OVRR + read + + NoOverrun + No overrun occurred + 0 + + + Overrun + Overrun occurred + 1 + + + + + MODF + Mode fault + 5 + 1 + read-only + + MODFR + read + + NoFault + No mode fault occurred + 0 + + + Fault + Mode fault occurred + 1 + + + + + CRCERR + CRC error flag + 4 + 1 + read-write + zeroToClear + + CRCERRR + read + + Match + CRC value received matches the SPIx_RXCRCR value + 0 + + + NoMatch + CRC value received does not match the SPIx_RXCRCR value + 1 + + + + CRCERRW + write + + Clear + Clear flag + 0 + + + + + UDR + Underrun flag + 3 + 1 + read-only + + UDRR + read + + NoUnderrun + No underrun occurred + 0 + + + Underrun + Underrun occurred + 1 + + + + + CHSIDE + Channel side + 2 + 1 + read-only + + CHSIDE + read + + Left + Channel left has to be transmitted or has been received + 0 + + + Right + Channel right has to be transmitted or has been received + 1 + + + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + TXE + read + + NotEmpty + Tx buffer not empty + 0 + + + Empty + Tx buffer empty + 1 + + + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + RXNE + read + + Empty + Rx buffer empty + 0 + + + NotEmpty + Rx buffer not empty + 1 + + + + + FRLVL + FIFO reception level + 9 + 2 + read-only + + FRLVLR + read + + Empty + Rx FIFO Empty + 0 + + + Quarter + Rx 1/4 FIFO + 1 + + + Half + Rx 1/2 FIFO + 2 + + + Full + Rx FIFO full + 3 + + + + + FTLVL + FIFO Transmission Level + 11 + 2 + read-only + + FTLVLR + read + + Empty + Tx FIFO Empty + 0 + + + Quarter + Tx 1/4 FIFO + 1 + + + Half + Tx 1/2 FIFO + 2 + + + Full + Tx FIFO full + 3 + + + + + + + DR + DR + data register + 0xC + 0x20 + read-write + 0x00000000 + + + DR + Data register + 0 + 16 + + + 0 + 65535 + + + + + + + CRCPR + CRCPR + CRC polynomial register + 0x10 + 0x20 + read-write + 0x00000007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + 0 + 65535 + + + + + + + RXCRCR + RXCRCR + RX CRC register + 0x14 + 0x20 + read-only + 0x00000000 + + + RxCRC + Rx CRC register + 0 + 16 + + + 0 + 65535 + + + + + + + TXCRCR + TXCRCR + TX CRC register + 0x18 + 0x20 + read-only + 0x00000000 + + + TxCRC + Tx CRC register + 0 + 16 + + + 0 + 65535 + + + + + + + I2SCFGR + I2SCFGR + I2S configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + I2SMOD + I2S mode selection + 11 + 1 + + I2SMOD + read-write + + SPIMode + SPI mode is selected + 0 + + + I2SMode + I2S mode is selected + 1 + + + + + I2SE + I2S Enable + 10 + 1 + + I2SE + read-write + + Disabled + I2S peripheral is disabled + 0 + + + Enabled + I2S peripheral is enabled + 1 + + + + + I2SCFG + I2S configuration mode + 8 + 2 + + I2SCFG + read-write + + SlaveTx + Slave - transmit + 0 + + + SlaveRx + Slave - receive + 1 + + + MasterTx + Master - transmit + 2 + + + MasterRx + Master - receive + 3 + + + + + PCMSYNC + PCM frame synchronization + 7 + 1 + + PCMSYNC + read-write + + Short + Short frame synchronisation + 0 + + + Long + Long frame synchronisation + 1 + + + + + I2SSTD + I2S standard selection + 4 + 2 + + I2SSTD + read-write + + Philips + I2S Philips standard + 0 + + + MSB + MSB justified standard + 1 + + + LSB + LSB justified standard + 2 + + + PCM + PCM standard + 3 + + + + + CKPOL + Steady state clock polarity + 3 + 1 + + CKPOL + read-write + + IdleLow + I2S clock inactive state is low level + 0 + + + IdleHigh + I2S clock inactive state is high level + 1 + + + + + DATLEN + Data length to be transferred + 1 + 2 + + DATLEN + read-write + + SixteenBit + 16-bit data length + 0 + + + TwentyFourBit + 24-bit data length + 1 + + + ThirtyTwoBit + 32-bit data length + 2 + + + + + CHLEN + Channel length (number of bits per audio channel) + 0 + 1 + + CHLEN + read-write + + SixteenBit + 16-bit wide + 0 + + + ThirtyTwoBit + 32-bit wide + 1 + + + + + ASTRTEN + Asynchronous start enable + 12 + 1 + + + + + I2SPR + I2SPR + I2S prescaler register + 0x20 + 0x20 + read-write + 0x0000000A + + + MCKOE + Master clock output enable + 9 + 1 + + MCKOE + read-write + + Disabled + Master clock output is disabled + 0 + + + Enabled + Master clock output is enabled + 1 + + + + + ODD + Odd factor for the prescaler + 8 + 1 + + ODD + read-write + + Even + Real divider value is I2SDIV * 2 + 0 + + + Odd + Real divider value is (I2SDIV * 2) + 1 + 1 + + + + + I2SDIV + I2S Linear prescaler + 0 + 8 + + + 2 + 255 + + + + + + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 51 + + + + SPI4 + 0x40013400 + + SPI4 + SPI 4 global interrupt + 84 + + + + SPI5 + 0x40015000 + + SPI5 + SPI 5 global interrupt + 85 + + + + SPI6 + 0x40015400 + + SPI6 + SPI 6 global interrupt + 86 + + + + SPI2 + Serial peripheral interface + SPI + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + ADC1 + Analog-to-digital converter + ADC + 0x40012000 + + 0x0 + 0x100 + registers + + + ADC + ADC1 global interrupt + 18 + + + + SR + SR + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OVR + Overrun + 5 + 1 + + + STRT + Regular channel start flag + 4 + 1 + zeroToClear + + STRTR + read + + NotStarted + No regular channel conversion started + 0 + + + Started + Regular channel conversion has started + 1 + + + + STRTW + write + + Clear + Clear flag + 0 + + + + + JSTRT + Injected channel start flag + 3 + 1 + zeroToClear + + JSTRTR + read + + NotStarted + No injected channel conversion started + 0 + + + Started + Injected channel conversion has started + 1 + + + + JSTRTW + write + + Clear + Clear flag + 0 + + + + + JEOC + Injected channel end of conversion + 2 + 1 + zeroToClear + + JEOCR + read + + NotComplete + Conversion is not complete + 0 + + + Complete + Conversion complete + 1 + + + + JEOCW + write + + Clear + Clear flag + 0 + + + + + EOC + Regular channel end of conversion + 1 + 1 + zeroToClear + + EOCR + read + + NotComplete + Conversion is not complete + 0 + + + Complete + Conversion complete + 1 + + + + EOCW + write + + Clear + Clear flag + 0 + + + + + AWD + Analog watchdog flag + 0 + 1 + zeroToClear + + AWDR + read + + NoEvent + No analog watchdog event occurred + 0 + + + Event + Analog watchdog event occurred + 1 + + + + AWDW + write + + Clear + Clear flag + 0 + + + + + + + CR1 + CR1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OVRIE + Overrun interrupt enable + 26 + 1 + + OVRIE + read-write + + Disabled + Overrun interrupt disabled + 0 + + + Enabled + Overrun interrupt enabled + 1 + + + + + RES + Resolution + 24 + 2 + + RES + read-write + + TwelveBit + 12-bit (15 ADCCLK cycles) + 0 + + + TenBit + 10-bit (13 ADCCLK cycles) + 1 + + + EightBit + 8-bit (11 ADCCLK cycles) + 2 + + + SixBit + 6-bit (9 ADCCLK cycles) + 3 + + + + + AWDEN + Analog watchdog enable on regular channels + 23 + 1 + + AWDEN + read-write + + Disabled + Analog watchdog disabled on regular channels + 0 + + + Enabled + Analog watchdog enabled on regular channels + 1 + + + + + JAWDEN + Analog watchdog enable on injected channels + 22 + 1 + + JAWDEN + read-write + + Disabled + Analog watchdog disabled on injected channels + 0 + + + Enabled + Analog watchdog enabled on injected channels + 1 + + + + + DISCNUM + Discontinuous mode channel count + 13 + 3 + + + 0 + 7 + + + + + JDISCEN + Discontinuous mode on injected channels + 12 + 1 + + JDISCEN + read-write + + Disabled + Discontinuous mode on injected channels disabled + 0 + + + Enabled + Discontinuous mode on injected channels enabled + 1 + + + + + DISCEN + Discontinuous mode on regular channels + 11 + 1 + + DISCEN + read-write + + Disabled + Discontinuous mode on regular channels disabled + 0 + + + Enabled + Discontinuous mode on regular channels enabled + 1 + + + + + JAUTO + Automatic injected group conversion + 10 + 1 + + JAUTO + read-write + + Disabled + Automatic injected group conversion disabled + 0 + + + Enabled + Automatic injected group conversion enabled + 1 + + + + + AWDSGL + Enable the watchdog on a single channel in scan mode + 9 + 1 + + AWDSGL + read-write + + AllChannels + Analog watchdog enabled on all channels + 0 + + + SingleChannel + Analog watchdog enabled on a single channel + 1 + + + + + SCAN + Scan mode + 8 + 1 + + SCAN + read-write + + Disabled + Scan mode disabled + 0 + + + Enabled + Scan mode enabled + 1 + + + + + JEOCIE + Interrupt enable for injected channels + 7 + 1 + + JEOCIE + read-write + + Disabled + JEOC interrupt disabled + 0 + + + Enabled + JEOC interrupt enabled + 1 + + + + + AWDIE + Analog watchdog interrupt enable + 6 + 1 + + AWDIE + read-write + + Disabled + Analogue watchdog interrupt disabled + 0 + + + Enabled + Analogue watchdog interrupt enabled + 1 + + + + + EOCIE + Interrupt enable for EOC + 5 + 1 + + EOCIE + read-write + + Disabled + EOC interrupt disabled + 0 + + + Enabled + EOC interrupt enabled + 1 + + + + + AWDCH + Analog watchdog channel select bits + 0 + 5 + + + 0 + 18 + + + + + + + CR2 + CR2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + SWSTART + Start conversion of regular channels + 30 + 1 + + SWSTARTW + write + + Start + Starts conversion of regular channels + 1 + + + + + EXTEN + External trigger enable for regular channels + 28 + 2 + + EXTEN + read-write + + Disabled + Trigger detection disabled + 0 + + + RisingEdge + Trigger detection on the rising edge + 1 + + + FallingEdge + Trigger detection on the falling edge + 2 + + + BothEdges + Trigger detection on both the rising and falling edges + 3 + + + + + EXTSEL + External event select for regular group + 24 + 4 + + EXTSEL + read-write + + TIM1CH1 + Timer 1 CH1 + 0 + + + TIM1CH2 + Timer 1 CH2 + 1 + + + TIM1CH3 + Timer 1 CH3 + 2 + + + TIM2CH2 + Timer 2 CH2 + 3 + + + TIM5TRGO + Timer 5 TRGO + 4 + + + TIM4CH4 + Timer 4 CH4 + 5 + + + TIM3CH4 + Timer 3 CH4 + 6 + + + TIM8TRGO + Timer 8 TRGO + 7 + + + TIM8TRGO2 + Timer 8 TRGO(2) + 8 + + + TIM1TRGO + Timer 1 TRGO + 9 + + + TIM1TRGO2 + Timer 1 TRGO(2) + 10 + + + TIM2TRGO + Timer 2 TRGO + 11 + + + TIM4TRGO + Timer 4 TRGO + 12 + + + TIM6TRGO + Timer 6 TRGO + 13 + + + EXTI11 + EXTI line 11 + 15 + + + + + JSWSTART + Start conversion of injected channels + 22 + 1 + + JSWSTARTW + write + + Start + Starts conversion of injected channels + 1 + + + + + JEXTEN + External trigger enable for injected channels + 20 + 2 + + JEXTEN + read-write + + Disabled + Trigger detection disabled + 0 + + + RisingEdge + Trigger detection on the rising edge + 1 + + + FallingEdge + Trigger detection on the falling edge + 2 + + + BothEdges + Trigger detection on both the rising and falling edges + 3 + + + + + JEXTSEL + External event select for injected group + 16 + 4 + + JEXTSEL + read-write + + TIM1TRGO + Timer 1 TRGO + 0 + + + TIM1CH4 + Timer 1 CH4 + 1 + + + TIM2TRGO + Timer 2 TRGO + 2 + + + TIM2CH1 + Timer 2 CH1 + 3 + + + TIM3CH4 + Timer 3 CH4 + 4 + + + TIM4TRGO + Timer 4 TRGO + 5 + + + TIM8CH4 + Timer 8 CH4 + 7 + + + TIM1TRGO2 + Timer 1 TRGO(2) + 8 + + + TIM8TRGO + Timer 8 TRGO + 9 + + + TIM8TRGO2 + Timer 8 TRGO(2) + 10 + + + TIM3CH3 + Timer 3 CH3 + 11 + + + TIM5TRGO + Timer 5 TRGO + 12 + + + TIM3CH1 + Timer 3 CH1 + 13 + + + TIM6TRGO + Timer 6 TRGO + 14 + + + + + ALIGN + Data alignment + 11 + 1 + + ALIGN + read-write + + Right + Right alignment + 0 + + + Left + Left alignment + 1 + + + + + EOCS + End of conversion selection + 10 + 1 + + EOCS + read-write + + EachSequence + The EOC bit is set at the end of each sequence of regular conversions + 0 + + + EachConversion + The EOC bit is set at the end of each regular conversion + 1 + + + + + DDS + DMA disable selection (for single ADC mode) + 9 + 1 + + DDS + read-write + + Single + No new DMA request is issued after the last transfer + 0 + + + Continuous + DMA requests are issued as long as data are converted and DMA=1 + 1 + + + + + DMA + Direct memory access mode (for single ADC mode) + 8 + 1 + + DMA + read-write + + Disabled + DMA mode disabled + 0 + + + Enabled + DMA mode enabled + 1 + + + + + CONT + Continuous conversion + 1 + 1 + + CONT + read-write + + Single + Single conversion mode + 0 + + + Continuous + Continuous conversion mode + 1 + + + + + ADON + A/D Converter ON / OFF + 0 + 1 + + ADON + read-write + + Disabled + Disable ADC conversion and go to power down mode + 0 + + + Enabled + Enable ADC + 1 + + + + + + + SMPR1 + SMPR1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + SMPx_x + Sample time bits + 0 + 32 + + SMPx_x + read-write + + Cycles3 + 3 cycles + 0 + + + Cycles15 + 15 cycles + 1 + + + Cycles28 + 28 cycles + 2 + + + Cycles56 + 56 cycles + 3 + + + Cycles84 + 84 cycles + 4 + + + Cycles112 + 112 cycles + 5 + + + Cycles144 + 144 cycles + 6 + + + Cycles480 + 480 cycles + 7 + + + + + + + SMPR2 + SMPR2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + SMPx_x + Sample time bits + 0 + 32 + + SMPx_x + read-write + + Cycles3 + 3 cycles + 0 + + + Cycles15 + 15 cycles + 1 + + + Cycles28 + 28 cycles + 2 + + + Cycles56 + 56 cycles + 3 + + + Cycles84 + 84 cycles + 4 + + + Cycles112 + 112 cycles + 5 + + + Cycles144 + 144 cycles + 6 + + + Cycles480 + 480 cycles + 7 + + + + + + + 4 + 0x4 + 1-4 + JOFR%s + JOFR1 + injected channel data offset register x + 0x14 + 0x20 + read-write + 0x00000000 + + + JOFFSET + Data offset for injected channel x + 0 + 12 + + + 0 + 4095 + + + + + + + HTR + HTR + watchdog higher threshold register + 0x24 + 0x20 + read-write + 0x00000FFF + + + HT + Analog watchdog higher threshold + 0 + 12 + + + 0 + 4095 + + + + + + + LTR + LTR + watchdog lower threshold register + 0x28 + 0x20 + read-write + 0x00000000 + + + LT + Analog watchdog lower threshold + 0 + 12 + + + 0 + 4095 + + + + + + + SQR1 + SQR1 + regular sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + L + Regular channel sequence length + 20 + 4 + + + 0 + 15 + + + + + SQ16 + 16th conversion in regular sequence + 15 + 5 + + + 0 + 18 + + + + + SQ15 + 15th conversion in regular sequence + 10 + 5 + + + 0 + 18 + + + + + SQ14 + 14th conversion in regular sequence + 5 + 5 + + + 0 + 18 + + + + + SQ13 + 13th conversion in regular sequence + 0 + 5 + + + 0 + 18 + + + + + + + SQR2 + SQR2 + regular sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ12 + 12th conversion in regular sequence + 25 + 5 + + + 0 + 18 + + + + + SQ11 + 11th conversion in regular sequence + 20 + 5 + + + 0 + 18 + + + + + SQ10 + 10th conversion in regular sequence + 15 + 5 + + + 0 + 18 + + + + + SQ9 + 9th conversion in regular sequence + 10 + 5 + + + 0 + 18 + + + + + SQ8 + 8th conversion in regular sequence + 5 + 5 + + + 0 + 18 + + + + + SQ7 + 7th conversion in regular sequence + 0 + 5 + + + 0 + 18 + + + + + + + SQR3 + SQR3 + regular sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ6 + 6th conversion in regular sequence + 25 + 5 + + + 0 + 18 + + + + + SQ5 + 5th conversion in regular sequence + 20 + 5 + + + 0 + 18 + + + + + SQ4 + 4th conversion in regular sequence + 15 + 5 + + + 0 + 18 + + + + + SQ3 + 3rd conversion in regular sequence + 10 + 5 + + + 0 + 18 + + + + + SQ2 + 2nd conversion in regular sequence + 5 + 5 + + + 0 + 18 + + + + + SQ1 + 1st conversion in regular sequence + 0 + 5 + + + 0 + 18 + + + + + + + JSQR + JSQR + injected sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + JL + Injected sequence length + 20 + 2 + + + 0 + 3 + + + + + JSQ4 + 4th conversion in injected sequence + 15 + 5 + + + 0 + 18 + + + + + JSQ3 + 3rd conversion in injected sequence + 10 + 5 + + + 0 + 18 + + + + + JSQ2 + 2nd conversion in injected sequence + 5 + 5 + + + 0 + 18 + + + + + JSQ1 + 1st conversion in injected sequence + 0 + 5 + + + 0 + 18 + + + + + + + 4 + 0x4 + 1-4 + JDR%s + JDR1 + injected data register x + 0x3C + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + DR + DR + regular data register + 0x4C + 0x20 + read-only + 0x00000000 + + + DATA + Regular data + 0 + 16 + + + + + + + ADC2 + 0x40012100 + + + ADC3 + 0x40012200 + + + DAC + Digital-to-analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAUDRIE2 + DAC channel2 DMA underrun interrupt enable + 29 + 1 + + + + DMAEN2 + DAC channel2 DMA enable + 28 + 1 + + + + MAMP2 + DAC channel2 mask/amplitude selector + 24 + 4 + + + 0 + 15 + + + + + WAVE2 + DAC channel2 noise/triangle wave generation enable + 22 + 2 + + WAVE2 + read-write + + Disabled + Wave generation disabled + 0 + + + Noise + Noise wave generation enabled + 1 + + + Triangle + Triangle wave generation enabled + 2 + + + + + TSEL2 + DAC channel2 trigger selection + 19 + 3 + + TSEL2 + read-write + + TIM6_TRGO + Timer 6 TRGO event + 0 + + + TIM8_TRGO + Timer 8 TRGO event + 1 + + + TIM7_TRGO + Timer 7 TRGO event + 2 + + + TIM5_TRGO + Timer 5 TRGO event + 3 + + + TIM2_TRGO + Timer 2 TRGO event + 4 + + + TIM4_TRGO + Timer 4 TRGO event + 5 + + + EXTI9 + EXTI line9 + 6 + + + SOFTWARE + Software trigger + 7 + + + + + TEN2 + DAC channel2 trigger enable + 18 + 1 + + + + BOFF2 + DAC channel2 output buffer disable + 17 + 1 + + + + EN2 + DAC channel2 enable + 16 + 1 + + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt enable + 13 + 1 + + DMAUDRIE1 + read-write + + Disabled + DAC channel X DMA Underrun Interrupt disabled + 0 + + + Enabled + DAC channel X DMA Underrun Interrupt enabled + 1 + + + + + DMAEN1 + DAC channel1 DMA enable + 12 + 1 + + DMAEN1 + read-write + + Disabled + DAC channel X DMA mode disabled + 0 + + + Enabled + DAC channel X DMA mode enabled + 1 + + + + + MAMP1 + DAC channel1 mask/amplitude selector + 8 + 4 + + + 0 + 15 + + + + + WAVE1 + DAC channel1 noise/triangle wave generation enable + 6 + 2 + + WAVE1 + read-write + + Disabled + Wave generation disabled + 0 + + + Noise + Noise wave generation enabled + 1 + + + Triangle + Triangle wave generation enabled + 2 + + + + + TSEL1 + DAC channel1 trigger selection + 3 + 3 + + TSEL1 + read-write + + TIM6_TRGO + Timer 6 TRGO event + 0 + + + TIM3_TRGO + Timer 3 TRGO event + 1 + + + TIM7_TRGO + Timer 7 TRGO event + 2 + + + TIM15_TRGO + Timer 15 TRGO event + 3 + + + TIM2_TRGO + Timer 2 TRGO event + 4 + + + EXTI9 + EXTI line9 + 6 + + + SOFTWARE + Software trigger + 7 + + + + + TEN1 + DAC channel1 trigger enable + 2 + 1 + + TEN1 + read-write + + Disabled + DAC channel X trigger disabled + 0 + + + Enabled + DAC channel X trigger enabled + 1 + + + + + BOFF1 + DAC channel1 output buffer disable + 1 + 1 + + BOFF1 + read-write + + Enabled + DAC channel X output buffer enabled + 0 + + + Disabled + DAC channel X output buffer disabled + 1 + + + + + EN1 + DAC channel1 enable + 0 + 1 + + EN1 + read-write + + Disabled + DAC channel X disabled + 0 + + + Enabled + DAC channel X enabled + 1 + + + + + + + SWTRIGR + SWTRIGR + software trigger register + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG2 + DAC channel2 software trigger + 1 + 1 + + + + SWTRIG1 + DAC channel1 software trigger + 0 + 1 + + SWTRIG1 + write + + Disabled + DAC channel X software trigger disabled + 0 + + + Enabled + DAC channel X software trigger enabled + 1 + + + + + + + DHR12R1 + DHR12R1 + channel1 12-bit right-aligned data holding register + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned data + 0 + 12 + + + 0 + 4095 + + + + + + + DHR12L1 + DHR12L1 + channel1 12-bit left aligned data holding register + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned data + 4 + 12 + + + 0 + 4095 + + + + + + + DHR8R1 + DHR8R1 + channel1 8-bit right aligned data holding register + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned data + 0 + 8 + + + 0 + 255 + + + + + + + DHR12R2 + DHR12R2 + channel2 12-bit right aligned data holding register + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned data + 0 + 12 + + + 0 + 4095 + + + + + + + DHR12L2 + DHR12L2 + channel2 12-bit left aligned data holding register + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned data + 4 + 12 + + + 0 + 4095 + + + + + + + DHR8R2 + DHR8R2 + channel2 8-bit right-aligned data holding register + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned data + 0 + 8 + + + 0 + 255 + + + + + + + DHR12RD + DHR12RD + Dual DAC 12-bit right-aligned data holding register + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned data + 16 + 12 + + + 0 + 4095 + + + + + DACC1DHR + DAC channel1 12-bit right-aligned data + 0 + 12 + + + 0 + 4095 + + + + + + + DHR12LD + DHR12LD + DUAL DAC 12-bit left aligned data holding register + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned data + 20 + 12 + + + 0 + 4095 + + + + + DACC1DHR + DAC channel1 12-bit left-aligned data + 4 + 12 + + + 0 + 4095 + + + + + + + DHR8RD + DHR8RD + DUAL DAC 8-bit right aligned data holding register + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned data + 8 + 8 + + + 0 + 255 + + + + + DACC1DHR + DAC channel1 8-bit right-aligned data + 0 + 8 + + + 0 + 255 + + + + + + + DOR1 + DOR1 + channel1 data output register + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output + 0 + 12 + + + + + DOR2 + DOR2 + channel2 data output register + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output + 0 + 12 + + + + + SR + SR + status register + 0x34 + 0x20 + read-write + 0x00000000 + + + DMAUDR2 + DAC channel2 DMA underrun flag + 29 + 1 + + + + DMAUDR1 + DAC channel1 DMA underrun flag + 13 + 1 + + DMAUDR1 + read-write + + NoUnderrun + No DMA underrun error condition occurred for DAC channel X + 0 + + + Underrun + DMA underrun error condition occurred for DAC channel X + 1 + + + + + + + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + PVD + PVD through EXTI line detection interrupt + 1 + + + + CR1 + CR1 + power control register + 0x0 + 0x20 + read-write + 0x0000C000 + + + LPDS + Low-power deep sleep + 0 + 1 + + + PDDS + Power down deepsleep + 1 + 1 + + PDDS + read-write + + STOP_MODE + Enter Stop mode when the CPU enters deepsleep + 0 + + + STANDBY_MODE + Enter Standby mode when the CPU enters deepsleep + 1 + + + + + CSBF + Clear standby flag + 3 + 1 + + + PVDE + Power voltage detector enable + 4 + 1 + + + PLS + PVD level selection + 5 + 3 + + + DBP + Disable backup domain write protection + 8 + 1 + + + FPDS + Flash power down in Stop mode + 9 + 1 + + + LPUDS + Low-power regulator in deepsleep under-drive mode + 10 + 1 + + + MRUDS + Main regulator in deepsleep under-drive mode + 11 + 1 + + + ADCDC1 + ADCDC1 + 13 + 1 + + + VOS + Regulator voltage scaling output selection + 14 + 2 + + VOS + read-write + + SCALE3 + Scale 3 mode + 1 + + + SCALE2 + Scale 2 mode + 2 + + + SCALE1 + Scale 1 mode (reset value) + 3 + + + + + ODEN + Over-drive enable + 16 + 1 + + + ODSWEN + Over-drive switching enabled + 17 + 1 + + + UDEN + Under-drive enable in stop mode + 18 + 2 + + + + + CSR1 + CSR1 + power control/status register + 0x4 + 0x20 + 0x00000000 + + + WUIF + Wakeup internal flag + 0 + 1 + read-only + + + SBF + Standby flag + 1 + 1 + read-only + + + PVDO + PVD output + 2 + 1 + read-only + + + BRR + Backup regulator ready + 3 + 1 + read-only + + + BRE + Backup regulator enable + 9 + 1 + read-write + + + VOSRDY + Regulator voltage scaling output selection ready bit + 14 + 1 + read-write + + + ODRDY + Over-drive mode ready + 16 + 1 + read-write + + + ODSWRDY + Over-drive mode switching ready + 17 + 1 + read-write + + + UDRDY + Under-drive ready flag + 18 + 2 + read-write + + + + + CR2 + CR2 + power control register + 0x8 + 0x20 + 0x00000000 + + + CWUPF1 + Clear Wakeup Pin flag for PA0 + 0 + 1 + read-only + + + CWUPF2 + Clear Wakeup Pin flag for PA2 + 1 + 1 + read-only + + + CWUPF3 + Clear Wakeup Pin flag for PC1 + 2 + 1 + read-only + + + CWUPF4 + Clear Wakeup Pin flag for PC13 + 3 + 1 + read-only + + + CWUPF5 + Clear Wakeup Pin flag for PI8 + 4 + 1 + read-only + + + CWUPF6 + Clear Wakeup Pin flag for PI11 + 5 + 1 + read-only + + + WUPP1 + Wakeup pin polarity bit for PA0 + 8 + 1 + read-write + + + WUPP2 + Wakeup pin polarity bit for PA2 + 9 + 1 + read-write + + + WUPP3 + Wakeup pin polarity bit for PC1 + 10 + 1 + read-write + + + WUPP4 + Wakeup pin polarity bit for PC13 + 11 + 1 + read-write + + + WUPP5 + Wakeup pin polarity bit for PI8 + 12 + 1 + read-write + + + WUPP6 + Wakeup pin polarity bit for PI11 + 13 + 1 + read-write + + + + + CSR2 + CSR2 + power control/status register + 0xC + 0x20 + 0x00000000 + + + WUPF1 + Wakeup Pin flag for PA0 + 0 + 1 + read-only + + + WUPF2 + Wakeup Pin flag for PA2 + 1 + 1 + read-only + + + WUPF3 + Wakeup Pin flag for PC1 + 2 + 1 + read-only + + + WUPF4 + Wakeup Pin flag for PC13 + 3 + 1 + read-only + + + WUPF5 + Wakeup Pin flag for PI8 + 4 + 1 + read-only + + + WUPF6 + Wakeup Pin flag for PI11 + 5 + 1 + read-only + + + EWUP1 + Enable Wakeup pin for PA0 + 8 + 1 + read-write + + + EWUP2 + Enable Wakeup pin for PA2 + 9 + 1 + read-write + + + EWUP3 + Enable Wakeup pin for PC1 + 10 + 1 + read-write + + + EWUP4 + Enable Wakeup pin for PC13 + 11 + 1 + read-write + + + EWUP5 + Enable Wakeup pin for PI8 + 12 + 1 + read-write + + + EWUP6 + Enable Wakeup pin for PI11 + 13 + 1 + read-write + + + + + + + IWDG + Independent watchdog + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value (write only, read 0000h) + 0 + 16 + + KEY + write + + Enable + Enable access to PR, RLR and WINR registers (0x5555) + 21845 + + + Reset + Reset the watchdog value (0xAAAA) + 43690 + + + Start + Start the watchdog (0xCCCC) + 52428 + + + + + + + PR + PR + Prescaler register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 3 + + PR + read-write + + DivideBy4 + Divider /4 + 0 + + + DivideBy8 + Divider /8 + 1 + + + DivideBy16 + Divider /16 + 2 + + + DivideBy32 + Divider /32 + 3 + + + DivideBy64 + Divider /64 + 4 + + + DivideBy128 + Divider /128 + 5 + + + DivideBy256 + Divider /256 + 6 + + + DivideBy256bis + Divider /256 + 7 + + + + + + + RLR + RLR + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload value + 0 + 12 + + + 0 + 4095 + + + + + + + SR + SR + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + RVU + Watchdog counter reload value update + 1 + 1 + + + PVU + Watchdog prescaler value update + 0 + 1 + + + + + WINR + WINR + Window register + 0x10 + 0x20 + read-write + 0x00000000 + + + WIN + Watchdog counter window value + 0 + 12 + + + 0 + 4095 + + + + + + + + + WWDG + Window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDG + Window Watchdog interrupt + 0 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + WDGA + Activation bit + 7 + 1 + + WDGA + read-write + + Disabled + Watchdog disabled + 0 + + + Enabled + Watchdog enabled + 1 + + + + + T + 7-bit counter (MSB to LSB) + 0 + 7 + + + 0 + 127 + + + + + + + CFR + CFR + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + EWI + Early wakeup interrupt + 9 + 1 + + EWIW + write + + Enable + interrupt occurs whenever the counter reaches the value 0x40 + 1 + + + + + W + 7-bit window value + 0 + 7 + + + 0 + 127 + + + + + WDGTB + Timer base + 7 + 2 + + WDGTB + read-write + + Div1 + Counter clock (PCLK1 div 4096) div 1 + 0 + + + Div2 + Counter clock (PCLK1 div 4096) div 2 + 1 + + + Div4 + Counter clock (PCLK1 div 4096) div 4 + 2 + + + Div8 + Counter clock (PCLK1 div 4096) div 8 + 3 + + + + + + + SR + SR + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + EWIF + Early wakeup interrupt flag + 0 + 1 + zeroToClear + + EWIFR + read + + Finished + The EWI Interrupt Service Routine has been serviced + 0 + + + Pending + The EWI Interrupt Service Routine has been triggered + 1 + + + + EWIFW + write + + Finished + The EWI Interrupt Service Routine has been serviced + 0 + + + + + + + + + ADC_Common + Common ADC registers + ADC_Common + 0x40012300 + + 0x0 + 0x400 + registers + + + + CSR + CSR + ADC Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + OVR3 + Overrun flag of ADC3 + 21 + 1 + + + + STRT3 + Regular channel Start flag of ADC 3 + 20 + 1 + + + + JSTRT3 + Injected channel Start flag of ADC 3 + 19 + 1 + + + + JEOC3 + Injected channel end of conversion of ADC 3 + 18 + 1 + + + + EOC3 + End of conversion of ADC 3 + 17 + 1 + + + + AWD3 + Analog watchdog flag of ADC 3 + 16 + 1 + + + + OVR2 + Overrun flag of ADC 2 + 13 + 1 + + + + STRT2 + Regular channel Start flag of ADC 2 + 12 + 1 + + + + JSTRT2 + Injected channel Start flag of ADC 2 + 11 + 1 + + + + JEOC2 + Injected channel end of conversion of ADC 2 + 10 + 1 + + + + EOC2 + End of conversion of ADC 2 + 9 + 1 + + + + AWD2 + Analog watchdog flag of ADC 2 + 8 + 1 + + + + OVR1 + Overrun flag of ADC 1 + 5 + 1 + + OVR1 + read + + NoOverrun + No overrun occurred + 0 + + + Overrun + Overrun occurred + 1 + + + + + STRT1 + Regular channel Start flag of ADC 1 + 4 + 1 + + STRT1 + read + + NotStarted + No regular channel conversion started + 0 + + + Started + Regular channel conversion has started + 1 + + + + + JSTRT1 + Injected channel Start flag of ADC 1 + 3 + 1 + + JSTRT1 + read + + NotStarted + No injected channel conversion started + 0 + + + Started + Injected channel conversion has started + 1 + + + + + JEOC1 + Injected channel end of conversion of ADC 1 + 2 + 1 + + JEOC1 + read + + NotComplete + Conversion is not complete + 0 + + + Complete + Conversion complete + 1 + + + + + EOC1 + End of conversion of ADC 1 + 1 + 1 + + EOC1 + read + + NotComplete + Conversion is not complete + 0 + + + Complete + Conversion complete + 1 + + + + + AWD1 + Analog watchdog flag of ADC 1 + 0 + 1 + + AWD1 + read + + NoEvent + No analog watchdog event occurred + 0 + + + Event + Analog watchdog event occurred + 1 + + + + + + + CCR + CCR + ADC common control register + 0x4 + 0x20 + read-write + 0x00000000 + + + TSVREFE + Temperature sensor and VREFINT enable + 23 + 1 + + TSVREFE + read-write + + Disabled + Temperature sensor and V_REFINT channel disabled + 0 + + + Enabled + Temperature sensor and V_REFINT channel enabled + 1 + + + + + VBATE + VBAT enable + 22 + 1 + + VBATE + read-write + + Disabled + V_BAT channel disabled + 0 + + + Enabled + V_BAT channel enabled + 1 + + + + + ADCPRE + ADC prescaler + 16 + 2 + + ADCPRE + read-write + + Div2 + PCLK2 divided by 2 + 0 + + + Div4 + PCLK2 divided by 4 + 1 + + + Div6 + PCLK2 divided by 6 + 2 + + + Div8 + PCLK2 divided by 8 + 3 + + + + + DMA + Direct memory access mode for multi ADC mode + 14 + 2 + + DMA + read-write + + Disabled + DMA mode disabled + 0 + + + Mode1 + DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3) + 1 + + + Mode2 + DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2) + 2 + + + Mode3 + DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2) + 3 + + + + + DDS + DMA disable selection for multi-ADC mode + 13 + 1 + + DDS + read-write + + Single + No new DMA request is issued after the last transfer + 0 + + + Continuous + DMA requests are issued as long as data are converted and DMA=01, 10 or 11 + 1 + + + + + DELAY + Delay between 2 sampling phases + 8 + 4 + + + 0 + 15 + + + + + MULTI + Multi ADC mode selection + 0 + 5 + + MULTI + read-write + + Independent + All the ADCs independent: independent mode + 0 + + + DualRJ + Dual ADC1 and ADC2, combined regular and injected simultaneous mode + 1 + + + DualRA + Dual ADC1 and ADC2, combined regular and alternate trigger mode + 2 + + + DualJ + Dual ADC1 and ADC2, injected simultaneous mode only + 5 + + + DualR + Dual ADC1 and ADC2, regular simultaneous mode only + 6 + + + DualI + Dual ADC1 and ADC2, interleaved mode only + 7 + + + DualA + Dual ADC1 and ADC2, alternate trigger mode only + 9 + + + TripleRJ + Triple ADC, regular and injected simultaneous mode + 17 + + + TripleRA + Triple ADC, regular and alternate trigger mode + 18 + + + TripleJ + Triple ADC, injected simultaneous mode only + 21 + + + TripleR + Triple ADC, regular simultaneous mode only + 22 + + + TripleI + Triple ADC, interleaved mode only + 23 + + + TripleA + Triple ADC, alternate trigger mode only + 24 + + + + + + + CDR + CDR + ADC common regular data register for dual and triple modes + 0x8 + 0x20 + read-only + 0x00000000 + + + DATA2 + 2nd data item of a pair of regular conversions + 16 + 16 + + + DATA1 + 1st data item of a pair of regular conversions + 0 + 16 + + + + + + + TIM1 + Advanced-timers + TIM + 0x40010000 + + 0x0 + 0x400 + registers + + + TIM1_BRK_TIM9 + TIM1 Break interrupt and TIM9 global + interrupt + 24 + + + TIM1_UP_TIM10 + TIM1 Update interrupt and TIM10 + 25 + + + TIM1_TRG_COM_TIM11 + TIM1 Trigger and Commutation interrupts and + TIM11 global interrupt + 26 + + + TIM1_CC + TIM1 Capture Compare interrupt + 27 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + CKD + Clock division + 8 + 2 + + CKD + read-write + + Div1 + t_DTS = t_CK_INT + 0 + + + Div2 + t_DTS = 2 × t_CK_INT + 1 + + + Div4 + t_DTS = 4 × t_CK_INT + 2 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + + ARPE + read-write + + Disabled + TIMx_APRR register is not buffered + 0 + + + Enabled + TIMx_APRR register is buffered + 1 + + + + + CMS + Center-aligned mode selection + 5 + 2 + + CMS + read-write + + EdgeAligned + The counter counts up or down depending on the direction bit + 0 + + + CenterAligned1 + The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. + 1 + + + CenterAligned2 + The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. + 2 + + + CenterAligned3 + The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. + 3 + + + + + DIR + Direction + 4 + 1 + + DIR + read-write + + Up + Counter used as upcounter + 0 + + + Down + Counter used as downcounter + 1 + + + + + OPM + One-pulse mode + 3 + 1 + + OPM + read-write + + Disabled + Counter is not stopped at update event + 0 + + + Enabled + Counter stops counting at the next update event (clearing the CEN bit) + 1 + + + + + URS + Update request source + 2 + 1 + + URS + read-write + + AnyEvent + Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + 0 + + + CounterOnly + Only counter overflow/underflow generates an update interrupt or DMA request + 1 + + + + + UDIS + Update disable + 1 + 1 + + UDIS + read-write + + Enabled + Update event enabled + 0 + + + Disabled + Update event disabled + 1 + + + + + CEN + Counter enable + 0 + 1 + + CEN + read-write + + Disabled + Counter disabled + 0 + + + Enabled + Counter enabled + 1 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + + OIS3N + Output Idle state 3 + 13 + 1 + + + + OIS3 + Output Idle state 3 + 12 + 1 + + + + OIS2N + Output Idle state 2 + 11 + 1 + + + + OIS2 + Output Idle state 2 + 10 + 1 + + + + OIS1N + Output Idle state 1 + 9 + 1 + + OIS1N + read-write + + Reset + OCxN=0 after a dead-time when MOE=0 + 0 + + + Set + OCxN=1 after a dead-time when MOE=0 + 1 + + + + + OIS1 + Output Idle state 1 + 8 + 1 + + OIS1 + read-write + + Reset + OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0 + 0 + + + Set + OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0 + 1 + + + + + TI1S + TI1 selection + 7 + 1 + + TI1S + read-write + + Normal + The TIMx_CH1 pin is connected to TI1 input + 0 + + + XOR + The TIMx_CH1, CH2, CH3 pins are connected to TI1 input + 1 + + + + + MMS + Master mode selection + 4 + 3 + + MMS + read-write + + Reset + The UG bit from the TIMx_EGR register is used as trigger output + 0 + + + Enable + The counter enable signal, CNT_EN, is used as trigger output + 1 + + + Update + The update event is selected as trigger output + 2 + + + ComparePulse + The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + 3 + + + CompareOC1 + OC1REF signal is used as trigger output + 4 + + + CompareOC2 + OC2REF signal is used as trigger output + 5 + + + CompareOC3 + OC3REF signal is used as trigger output + 6 + + + CompareOC4 + OC4REF signal is used as trigger output + 7 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + + CCDS + read-write + + OnCompare + CCx DMA request sent when CCx event occurs + 0 + + + OnUpdate + CCx DMA request sent when update event occurs + 1 + + + + + CCUS + Capture/compare control update selection + 2 + 1 + + + CCPC + Capture/compare preloaded control + 0 + 1 + + + OIS5 + Output Idle state 5 (OC5 output) + 16 + 1 + + + + OIS6 + Output Idle state 6 (OC6 output) + 18 + 1 + + + + MMS2 + Master mode selection 2 + 20 + 4 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + SMS_3 + Slave model selection - bit[3] + 16 + 1 + + + ETP + External trigger polarity + 15 + 1 + + ETP + read-write + + NotInverted + ETR is noninverted, active at high level or rising edge + 0 + + + Inverted + ETR is inverted, active at low level or falling edge + 1 + + + + + ECE + External clock enable + 14 + 1 + + ECE + read-write + + Disabled + External clock mode 2 disabled + 0 + + + Enabled + External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. + 1 + + + + + ETPS + External trigger prescaler + 12 + 2 + + ETPS + read-write + + Div1 + Prescaler OFF + 0 + + + Div2 + ETRP frequency divided by 2 + 1 + + + Div4 + ETRP frequency divided by 4 + 2 + + + Div8 + ETRP frequency divided by 8 + 3 + + + + + ETF + External trigger filter + 8 + 4 + + ETF + read-write + + NoFilter + No filter, sampling is done at fDTS + 0 + + + FCK_INT_N2 + fSAMPLING=fCK_INT, N=2 + 1 + + + FCK_INT_N4 + fSAMPLING=fCK_INT, N=4 + 2 + + + FCK_INT_N8 + fSAMPLING=fCK_INT, N=8 + 3 + + + FDTS_Div2_N6 + fSAMPLING=fDTS/2, N=6 + 4 + + + FDTS_Div2_N8 + fSAMPLING=fDTS/2, N=8 + 5 + + + FDTS_Div4_N6 + fSAMPLING=fDTS/4, N=6 + 6 + + + FDTS_Div4_N8 + fSAMPLING=fDTS/4, N=8 + 7 + + + FDTS_Div8_N6 + fSAMPLING=fDTS/8, N=6 + 8 + + + FDTS_Div8_N8 + fSAMPLING=fDTS/8, N=8 + 9 + + + FDTS_Div16_N5 + fSAMPLING=fDTS/16, N=5 + 10 + + + FDTS_Div16_N6 + fSAMPLING=fDTS/16, N=6 + 11 + + + FDTS_Div16_N8 + fSAMPLING=fDTS/16, N=8 + 12 + + + FDTS_Div32_N5 + fSAMPLING=fDTS/32, N=5 + 13 + + + FDTS_Div32_N6 + fSAMPLING=fDTS/32, N=6 + 14 + + + FDTS_Div32_N8 + fSAMPLING=fDTS/32, N=8 + 15 + + + + + MSM + Master/Slave mode + 7 + 1 + + MSM + read-write + + NoSync + No action + 0 + + + Sync + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + 1 + + + + + TS + Trigger selection + 4 + 3 + + TS + read-write + + ITR0 + Internal Trigger 0 (ITR0) + 0 + + + ITR1 + Internal Trigger 1 (ITR1) + 1 + + + ITR2 + Internal Trigger 2 (ITR2) + 2 + + + TI1F_ED + TI1 Edge Detector (TI1F_ED) + 4 + + + TI1FP1 + Filtered Timer Input 1 (TI1FP1) + 5 + + + TI2FP2 + Filtered Timer Input 2 (TI2FP2) + 6 + + + ETRF + External Trigger input (ETRF) + 7 + + + + + SMS + Slave mode selection - bit[2:0] + 0 + 3 + + SMS + read-write + + Disabled + Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. + 0 + + + Encoder_Mode_1 + Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. + 1 + + + Encoder_Mode_2 + Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. + 2 + + + Encoder_Mode_3 + Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + 3 + + + Reset_Mode + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 4 + + + Gated_Mode + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + 5 + + + Trigger_Mode + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + 6 + + + Ext_Clock_Mode + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 7 + + + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + TDE + Trigger DMA request enable + 14 + 1 + + TDE + read-write + + Disabled + Trigger DMA request disabled + 0 + + + Enabled + Trigger DMA request enabled + 1 + + + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + CC1DE + read-write + + Disabled + CCx DMA request disabled + 0 + + + Enabled + CCx DMA request enabled + 1 + + + + + UDE + Update DMA request enable + 8 + 1 + + UDE + read-write + + Disabled + Update DMA request disabled + 0 + + + Enabled + Update DMA request enabled + 1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + + TIE + read-write + + Disabled + Trigger interrupt disabled + 0 + + + Enabled + Trigger interrupt enabled + 1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + CC1IE + read-write + + Disabled + CCx interrupt disabled + 0 + + + Enabled + CCx interrupt enabled + 1 + + + + + UIE + Update interrupt enable + 0 + 1 + + UIE + read-write + + Disabled + Update interrupt disabled + 0 + + + Enabled + Update interrupt enabled + 1 + + + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + CC4OF + Capture/Compare 4 overcapture flag + 12 + 1 + zeroToClear + + read + + + write + + + + CC3OF + Capture/Compare 3 overcapture flag + 11 + 1 + zeroToClear + + read + + + write + + + + CC2OF + Capture/compare 2 overcapture flag + 10 + 1 + zeroToClear + + read + + + write + + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + zeroToClear + + CC1OFR + read + + Overcapture + The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set + 1 + + + + CC1OFW + write + + Clear + Clear flag + 0 + + + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + zeroToClear + + TIFR + read + + NoTrigger + No trigger event occurred + 0 + + + Trigger + Trigger interrupt pending + 1 + + + + TIFW + write + + Clear + Clear flag + 0 + + + + + COMIF + COM interrupt flag + 5 + 1 + + + CC4IF + Capture/Compare 4 interrupt flag + 4 + 1 + zeroToClear + + read + + + write + + + + CC3IF + Capture/Compare 3 interrupt flag + 3 + 1 + zeroToClear + + read + + + write + + + + CC2IF + Capture/Compare 2 interrupt flag + 2 + 1 + zeroToClear + + read + + + write + + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + zeroToClear + + CC1IFR + read + + Match + If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. + 1 + + + + CC1IFW + write + + Clear + Clear flag + 0 + + + + + UIF + Update interrupt flag + 0 + 1 + zeroToClear + + UIFR + read + + NoUpdateOccurred + No update occurred + 0 + + + UpdatePending + Update interrupt pending + 1 + + + + UIFW + write + + Clear + Clear flag + 0 + + + + + B2IF + Break 2 interrupt flag + 8 + 1 + + + CC5IF + Compare 5 interrupt flag + 16 + 1 + + + CC6IF + Compare 6 interrupt flag + 17 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + TGW + write + + Trigger + The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. + 1 + + + + + COMG + Capture/Compare control update generation + 5 + 1 + + + CC4G + Capture/compare 4 generation + 4 + 1 + + + + CC3G + Capture/compare 3 generation + 3 + 1 + + + + CC2G + Capture/compare 2 generation + 2 + 1 + + + + CC1G + Capture/compare 1 generation + 1 + 1 + + CC1GW + write + + Trigger + If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. + 1 + + + + + UG + Update generation + 0 + 1 + + UG + write + + Update + Re-initializes the timer counter and generates an update of the registers. + 1 + + + + + B2G + Break 2 generation + 8 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + Output Compare 2 clear enable + 15 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + + OC2PE + Output Compare 2 preload enable + 11 + 1 + + OC2PE + read-write + + Disabled + Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately + 0 + + + Enabled + Preload register on CCR2 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC2FE + Output Compare 2 fast enable + 10 + 1 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + CC2S + read-write + + Output + CC2 channel is configured as output + 0 + + + + + OC1CE + Output Compare 1 clear enable + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + OC1M + read-write + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive + 0 + + + ActiveOnMatch + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 + 1 + + + InactiveOnMatch + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved + 3 + + + ForceInactive + OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF + 4 + + + ForceActive + OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF + 5 + + + PwmMode1 + In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down + 6 + + + PwmMode2 + Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 + 7 + + + + + OC1PE + Output Compare 1 preload enable + 3 + 1 + + OC1PE + read-write + + Disabled + Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately + 0 + + + Enabled + Preload register on CCR1 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC1FE + Output Compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + CC1S + read-write + + Output + CC1 channel is configured as output + 0 + + + + + OC2M_3 + Output Compare 2 mode, bit 3 + 24 + 1 + + + + OC1M_3 + Output Compare 1 mode, bit 3 + 16 + 1 + + OC1M_3 + read-write + + Normal + Normal output compare mode (modes 0-7) + 0 + + + Extended + Extended output compare mode (modes 7-15) + 1 + + + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + 0 + 15 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + CC2S + read-write + + TI2 + CC2 channel is configured as input, IC2 is mapped on TI2 + 1 + + + TI1 + CC2 channel is configured as input, IC2 is mapped on TI1 + 2 + + + TRC + CC2 channel is configured as input, IC2 is mapped on TRC + 3 + + + + + IC1F + Input capture 1 filter + 4 + 4 + + IC1F + read-write + + NoFilter + No filter, sampling is done at fDTS + 0 + + + FCK_INT_N2 + fSAMPLING=fCK_INT, N=2 + 1 + + + FCK_INT_N4 + fSAMPLING=fCK_INT, N=4 + 2 + + + FCK_INT_N8 + fSAMPLING=fCK_INT, N=8 + 3 + + + FDTS_Div2_N6 + fSAMPLING=fDTS/2, N=6 + 4 + + + FDTS_Div2_N8 + fSAMPLING=fDTS/2, N=8 + 5 + + + FDTS_Div4_N6 + fSAMPLING=fDTS/4, N=6 + 6 + + + FDTS_Div4_N8 + fSAMPLING=fDTS/4, N=8 + 7 + + + FDTS_Div8_N6 + fSAMPLING=fDTS/8, N=6 + 8 + + + FDTS_Div8_N8 + fSAMPLING=fDTS/8, N=8 + 9 + + + FDTS_Div16_N5 + fSAMPLING=fDTS/16, N=5 + 10 + + + FDTS_Div16_N6 + fSAMPLING=fDTS/16, N=6 + 11 + + + FDTS_Div16_N8 + fSAMPLING=fDTS/16, N=8 + 12 + + + FDTS_Div32_N5 + fSAMPLING=fDTS/32, N=5 + 13 + + + FDTS_Div32_N6 + fSAMPLING=fDTS/32, N=6 + 14 + + + FDTS_Div32_N8 + fSAMPLING=fDTS/32, N=8 + 15 + + + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + CC1S + read-write + + TI1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 1 + + + TI2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 2 + + + TRC + CC1 channel is configured as input, IC1 is mapped on TRC + 3 + + + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + Output compare 4 clear enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + + OC4PE + Output compare 4 preload enable + 11 + 1 + + OC4PE + read-write + + Disabled + Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately + 0 + + + Enabled + Preload register on CCR4 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + CC4S + read-write + + Output + CC4 channel is configured as output + 0 + + + + + OC3CE + Output compare 3 clear enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + OC3M + read-write + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive + 0 + + + ActiveOnMatch + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 + 1 + + + InactiveOnMatch + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved + 3 + + + ForceInactive + OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF + 4 + + + ForceActive + OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF + 5 + + + PwmMode1 + In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down + 6 + + + PwmMode2 + Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 + 7 + + + + + OC3PE + Output compare 3 preload enable + 3 + 1 + + OC3PE + read-write + + Disabled + Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately + 0 + + + Enabled + Preload register on CCR3 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + + + CC3S + Capture/Compare 3 selection + 0 + 2 + + CC3S + read-write + + Output + CC3 channel is configured as output + 0 + + + + + OC3M_3 + Output Compare 3 mode, bit 3 + 16 + 1 + + OC3M_3 + read-write + + Normal + Normal output compare mode (modes 0-7) + 0 + + + Extended + Extended output compare mode (modes 7-15) + 1 + + + + + OC4M_3 + Output Compare 4 mode, bit 3 + 24 + 1 + + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + 0 + 15 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + 0 + 3 + + + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + CC4S + read-write + + TI4 + CC4 channel is configured as input, IC4 is mapped on TI4 + 1 + + + TI3 + CC4 channel is configured as input, IC4 is mapped on TI3 + 2 + + + TRC + CC4 channel is configured as input, IC4 is mapped on TRC + 3 + + + + + IC3F + Input capture 3 filter + 4 + 4 + + + 0 + 15 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + 0 + 3 + + + + + CC3S + Capture/compare 3 selection + 0 + 2 + + CC3S + read-write + + TI3 + CC3 channel is configured as input, IC3 is mapped on TI3 + 1 + + + TI4 + CC3 channel is configured as input, IC3 is mapped on TI4 + 2 + + + TRC + CC3 channel is configured as input, IC3 is mapped on TRC + 3 + + + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC4P + Capture/Compare 3 output Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output Polarity + 11 + 1 + + + CC3NE + Capture/Compare 3 complementary output enable + 10 + 1 + + + CC3P + Capture/Compare 3 output Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output Polarity + 7 + 1 + + + CC2NE + Capture/Compare 2 complementary output enable + 6 + 1 + + + CC2P + Capture/Compare 2 output Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + CC5E + Capture/Compare 5 output enable + 16 + 1 + + + CC5P + Capture/Compare 5 output polarity + 17 + 1 + + + CC6E + Capture/Compare 6 output enable + 20 + 1 + + + CC6P + Capture/Compare 6 output polarity + 21 + 1 + + + CC4NP + Capture/Compare 4 complementary output polarity + 15 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + 0 + 65535 + + + + + UIFCPY + UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0 + + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + 0 + 65535 + + + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + 0 + 65535 + + + + + + + 4 + 0x4 + 1-4 + CCR%s + CCR1 + capture/compare register + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR + Capture/Compare value + 0 + 16 + + + 0 + 65535 + + + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x00000000 + + + DBL + DMA burst length + 8 + 5 + + + 0 + 18 + + + + + DBA + DMA base address + 0 + 5 + + + 0 + 31 + + + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x00000000 + + + DMAB + DMA register for burst accesses + 0 + 32 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x00000000 + + + REP + Repetition counter value + 0 + 8 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + + + MOE + Main output enable + 15 + 1 + + MOE + read-write + + DisabledIdle + OC/OCN are disabled or forced idle depending on OSSI + 0 + + + Enabled + OC/OCN are enabled if CCxE/CCxNE are set + 1 + + + + + AOE + Automatic output enable + 14 + 1 + + AOE + read-write + + Manual + MOE can be set only by software + 0 + + + Automatic + MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) + 1 + + + + + BKP + Break polarity + 13 + 1 + + BKP + read-write + + ActiveLow + Break input BRKx is active low + 0 + + + ActiveHigh + Break input BRKx is active high + 1 + + + + + BKE + Break enable + 12 + 1 + + BKE + read-write + + Disabled + Break function x disabled + 0 + + + Enabled + Break function x disabled + 1 + + + + + OSSR + Off-state selection for Run mode + 11 + 1 + + OSSR + read-write + + Disabled + When inactive, OC/OCN outputs are disabled + 0 + + + IdleLevel + When inactive, OC/OCN outputs are enabled with their inactive level + 1 + + + + + OSSI + Off-state selection for Idle mode + 10 + 1 + + OSSI + read-write + + Disabled + When inactive, OC/OCN outputs are disabled + 0 + + + IdleLevel + When inactive, OC/OCN outputs are forced to idle level + 1 + + + + + LOCK + Lock configuration + 8 + 2 + + LOCK + read-write + + Off + No bit is write protected + 0 + + + Level1 + Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written + 1 + + + Level2 + LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written + 2 + + + Level3 + LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written + 3 + + + + + DTG + Dead-time generator setup + 0 + 8 + + + 0 + 255 + + + + + BKF + Break filter + 16 + 4 + + + BK2F + Break 2 filter + 20 + 4 + + + BK2E + Break 2 enable + 24 + 1 + + + + BK2P + Break 2 polarity + 25 + 1 + + + + + + CCMR3_Output + CCMR3_Output + capture/compare mode register 3 (output mode) + 0x54 + 0x20 + read-write + 0x00000000 + + + OC5FE + Output compare 5 fast enable + 2 + 1 + + + OC5PE + Output compare 5 preload enable + 3 + 1 + + + OC5M + Output compare 5 mode + 4 + 3 + + OC5M + read-write + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive + 0 + + + ActiveOnMatch + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 + 1 + + + InactiveOnMatch + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved + 3 + + + ForceInactive + OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF + 4 + + + ForceActive + OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF + 5 + + + PwmMode1 + In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down + 6 + + + PwmMode2 + Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 + 7 + + + + + OC5CE + Output compare 5 clear enable + 7 + 1 + + + OC6FE + Output compare 6 fast enable + 10 + 1 + + + OC6PE + Output compare 6 preload enable + 11 + 1 + + + OC6M + Output compare 6 mode + 12 + 3 + + + + OC6CE + Output compare 6 clear enable + 15 + 1 + + + OC5M_3 + Output Compare 5 mode + 16 + 1 + + OC5M_3 + read-write + + Normal + Normal output compare mode (modes 0-7) + 0 + + + Extended + Extended output compare mode (modes 7-15) + 1 + + + + + OC6M_3 + Output Compare 6 mode + 24 + 1 + + + + + + CCR5 + CCR5 + capture/compare register + 0x58 + 0x20 + read-write + 0x00000000 + + + CCR + Capture/Compare value + 0 + 16 + + + GC5C1 + Group Channel 5 and Channel 1 + 29 + 1 + + + GC5C2 + Group Channel 5 and Channel 2 + 30 + 1 + + + GC5C3 + Group Channel 5 and Channel 3 + 31 + 1 + + + + + CCR6 + CRR6 + capture/compare register + 0x5C + 0x20 + read-write + 0x00000000 + + + CCR + Capture/Compare value + 0 + 16 + + + + + AF1 + alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000001 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + BKDFBKE + BRK DFSDM_BREAK[0] enable + 8 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + + + AF2 + alternate function option register 2 + 0x64 + 0x20 + read-write + 0x00000001 + + + BK2INE + BRK2 BKIN input enable + 0 + 1 + + + BK2DFBKE + BRK2 DFSDM_BREAK[0] enable + 8 + 1 + + + BK2INP + BRK2 BKIN input polarity + 9 + 1 + + + + + + + TIM8 + TIM + 0x40010400 + + TIM8_BRK_TIM12 + TIM8 Break interrupt and TIM12 global + interrupt + 43 + + + TIM8_UP_TIM13 + TIM8 Update interrupt and TIM13 global + interrupt + 44 + + + TIM8_TRG_COM_TIM14 + TIM8 Trigger and Commutation interrupts and + TIM14 global interrupt + 45 + + + TIM8_CC + TIM8 Capture Compare interrupt + 46 + + + + TIM2 + General purpose timers + TIM + 0x40000000 + + 0x0 + 0x400 + registers + + + TIM2 + TIM2 global interrupt + 28 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + CKD + Clock division + 8 + 2 + + CKD + read-write + + Div1 + t_DTS = t_CK_INT + 0 + + + Div2 + t_DTS = 2 × t_CK_INT + 1 + + + Div4 + t_DTS = 4 × t_CK_INT + 2 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + + ARPE + read-write + + Disabled + TIMx_APRR register is not buffered + 0 + + + Enabled + TIMx_APRR register is buffered + 1 + + + + + CMS + Center-aligned mode selection + 5 + 2 + + CMS + read-write + + EdgeAligned + The counter counts up or down depending on the direction bit + 0 + + + CenterAligned1 + The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. + 1 + + + CenterAligned2 + The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. + 2 + + + CenterAligned3 + The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. + 3 + + + + + DIR + Direction + 4 + 1 + + DIR + read-write + + Up + Counter used as upcounter + 0 + + + Down + Counter used as downcounter + 1 + + + + + OPM + One-pulse mode + 3 + 1 + + OPM + read-write + + Disabled + Counter is not stopped at update event + 0 + + + Enabled + Counter stops counting at the next update event (clearing the CEN bit) + 1 + + + + + URS + Update request source + 2 + 1 + + URS + read-write + + AnyEvent + Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + 0 + + + CounterOnly + Only counter overflow/underflow generates an update interrupt or DMA request + 1 + + + + + UDIS + Update disable + 1 + 1 + + UDIS + read-write + + Enabled + Update event enabled + 0 + + + Disabled + Update event disabled + 1 + + + + + CEN + Counter enable + 0 + 1 + + CEN + read-write + + Disabled + Counter disabled + 0 + + + Enabled + Counter enabled + 1 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + TI1S + TI1 selection + 7 + 1 + + TI1S + read-write + + Normal + The TIMx_CH1 pin is connected to TI1 input + 0 + + + XOR + The TIMx_CH1, CH2, CH3 pins are connected to TI1 input + 1 + + + + + MMS + Master mode selection + 4 + 3 + + MMS + read-write + + Reset + The UG bit from the TIMx_EGR register is used as trigger output + 0 + + + Enable + The counter enable signal, CNT_EN, is used as trigger output + 1 + + + Update + The update event is selected as trigger output + 2 + + + ComparePulse + The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + 3 + + + CompareOC1 + OC1REF signal is used as trigger output + 4 + + + CompareOC2 + OC2REF signal is used as trigger output + 5 + + + CompareOC3 + OC3REF signal is used as trigger output + 6 + + + CompareOC4 + OC4REF signal is used as trigger output + 7 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + + CCDS + read-write + + OnCompare + CCx DMA request sent when CCx event occurs + 0 + + + OnUpdate + CCx DMA request sent when update event occurs + 1 + + + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + SMS + Slave mode selection + 0 + 3 + + SMS + read-write + + Disabled + Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. + 0 + + + Encoder_Mode_1 + Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. + 1 + + + Encoder_Mode_2 + Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. + 2 + + + Encoder_Mode_3 + Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + 3 + + + Reset_Mode + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 4 + + + Gated_Mode + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + 5 + + + Trigger_Mode + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + 6 + + + Ext_Clock_Mode + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 7 + + + + + TS + Trigger selection + 4 + 3 + + TS + read-write + + ITR0 + Internal Trigger 0 (ITR0) + 0 + + + ITR1 + Internal Trigger 1 (ITR1) + 1 + + + ITR2 + Internal Trigger 2 (ITR2) + 2 + + + TI1F_ED + TI1 Edge Detector (TI1F_ED) + 4 + + + TI1FP1 + Filtered Timer Input 1 (TI1FP1) + 5 + + + TI2FP2 + Filtered Timer Input 2 (TI2FP2) + 6 + + + ETRF + External Trigger input (ETRF) + 7 + + + + + MSM + Master/Slave mode + 7 + 1 + + MSM + read-write + + NoSync + No action + 0 + + + Sync + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + 1 + + + + + ETF + External trigger filter + 8 + 4 + + ETF + read-write + + NoFilter + No filter, sampling is done at fDTS + 0 + + + FCK_INT_N2 + fSAMPLING=fCK_INT, N=2 + 1 + + + FCK_INT_N4 + fSAMPLING=fCK_INT, N=4 + 2 + + + FCK_INT_N8 + fSAMPLING=fCK_INT, N=8 + 3 + + + FDTS_Div2_N6 + fSAMPLING=fDTS/2, N=6 + 4 + + + FDTS_Div2_N8 + fSAMPLING=fDTS/2, N=8 + 5 + + + FDTS_Div4_N6 + fSAMPLING=fDTS/4, N=6 + 6 + + + FDTS_Div4_N8 + fSAMPLING=fDTS/4, N=8 + 7 + + + FDTS_Div8_N6 + fSAMPLING=fDTS/8, N=6 + 8 + + + FDTS_Div8_N8 + fSAMPLING=fDTS/8, N=8 + 9 + + + FDTS_Div16_N5 + fSAMPLING=fDTS/16, N=5 + 10 + + + FDTS_Div16_N6 + fSAMPLING=fDTS/16, N=6 + 11 + + + FDTS_Div16_N8 + fSAMPLING=fDTS/16, N=8 + 12 + + + FDTS_Div32_N5 + fSAMPLING=fDTS/32, N=5 + 13 + + + FDTS_Div32_N6 + fSAMPLING=fDTS/32, N=6 + 14 + + + FDTS_Div32_N8 + fSAMPLING=fDTS/32, N=8 + 15 + + + + + ETPS + External trigger prescaler + 12 + 2 + + ETPS + read-write + + Div1 + Prescaler OFF + 0 + + + Div2 + ETRP frequency divided by 2 + 1 + + + Div4 + ETRP frequency divided by 4 + 2 + + + Div8 + ETRP frequency divided by 8 + 3 + + + + + ECE + External clock enable + 14 + 1 + + ECE + read-write + + Disabled + External clock mode 2 disabled + 0 + + + Enabled + External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. + 1 + + + + + ETP + External trigger polarity + 15 + 1 + + ETP + read-write + + NotInverted + ETR is noninverted, active at high level or rising edge + 0 + + + Inverted + ETR is inverted, active at low level or falling edge + 1 + + + + + SMS_3 + Slave model selection - bit[3] + 16 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + TDE + Trigger DMA request enable + 14 + 1 + + TDE + read-write + + Disabled + Trigger DMA request disabled + 0 + + + Enabled + Trigger DMA request enabled + 1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + CC1DE + read-write + + Disabled + CCx DMA request disabled + 0 + + + Enabled + CCx DMA request enabled + 1 + + + + + UDE + Update DMA request enable + 8 + 1 + + UDE + read-write + + Disabled + Update DMA request disabled + 0 + + + Enabled + Update DMA request enabled + 1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + + TIE + read-write + + Disabled + Trigger interrupt disabled + 0 + + + Enabled + Trigger interrupt enabled + 1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + CC1IE + read-write + + Disabled + CCx interrupt disabled + 0 + + + Enabled + CCx interrupt enabled + 1 + + + + + UIE + Update interrupt enable + 0 + 1 + + UIE + read-write + + Disabled + Update interrupt disabled + 0 + + + Enabled + Update interrupt enabled + 1 + + + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + CC4OF + Capture/Compare 4 overcapture flag + 12 + 1 + zeroToClear + + read + + + write + + + + CC3OF + Capture/Compare 3 overcapture flag + 11 + 1 + zeroToClear + + read + + + write + + + + CC2OF + Capture/compare 2 overcapture flag + 10 + 1 + zeroToClear + + read + + + write + + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + zeroToClear + + CC1OFR + read + + Overcapture + The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set + 1 + + + + CC1OFW + write + + Clear + Clear flag + 0 + + + + + TIF + Trigger interrupt flag + 6 + 1 + zeroToClear + + TIFR + read + + NoTrigger + No trigger event occurred + 0 + + + Trigger + Trigger interrupt pending + 1 + + + + TIFW + write + + Clear + Clear flag + 0 + + + + + CC4IF + Capture/Compare 4 interrupt flag + 4 + 1 + zeroToClear + + read + + + write + + + + CC3IF + Capture/Compare 3 interrupt flag + 3 + 1 + zeroToClear + + read + + + write + + + + CC2IF + Capture/Compare 2 interrupt flag + 2 + 1 + zeroToClear + + read + + + write + + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + zeroToClear + + CC1IFR + read + + Match + If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. + 1 + + + + CC1IFW + write + + Clear + Clear flag + 0 + + + + + UIF + Update interrupt flag + 0 + 1 + zeroToClear + + UIFR + read + + NoUpdateOccurred + No update occurred + 0 + + + UpdatePending + Update interrupt pending + 1 + + + + UIFW + write + + Clear + Clear flag + 0 + + + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + TG + Trigger generation + 6 + 1 + + TGW + write + + Trigger + The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. + 1 + + + + + CC4G + Capture/compare 4 generation + 4 + 1 + + + + CC3G + Capture/compare 3 generation + 3 + 1 + + + + CC2G + Capture/compare 2 generation + 2 + 1 + + + + CC1G + Capture/compare 1 generation + 1 + 1 + + CC1GW + write + + Trigger + If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. + 1 + + + + + UG + Update generation + 0 + 1 + + UG + write + + Update + Re-initializes the timer counter and generates an update of the registers. + 1 + + + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + OC2CE + 15 + 1 + + + OC2M + OC2M + 12 + 3 + + + + OC2PE + OC2PE + 11 + 1 + + OC2PE + read-write + + Disabled + Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately + 0 + + + Enabled + Preload register on CCR2 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC2FE + OC2FE + 10 + 1 + + + CC2S + CC2S + 8 + 2 + + CC2S + read-write + + Output + CC2 channel is configured as output + 0 + + + + + OC1CE + OC1CE + 7 + 1 + + + OC1M + OC1M + 4 + 3 + + OC1M + read-write + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive + 0 + + + ActiveOnMatch + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 + 1 + + + InactiveOnMatch + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved + 3 + + + ForceInactive + OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF + 4 + + + ForceActive + OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF + 5 + + + PwmMode1 + In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down + 6 + + + PwmMode2 + Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 + 7 + + + + + OC1PE + OC1PE + 3 + 1 + + OC1PE + read-write + + Disabled + Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately + 0 + + + Enabled + Preload register on CCR1 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC1FE + OC1FE + 2 + 1 + + + CC1S + CC1S + 0 + 2 + + CC1S + read-write + + Output + CC1 channel is configured as output + 0 + + + + + OC2M_3 + Output Compare 2 mode, bit 3 + 24 + 1 + + + + OC1M_3 + Output Compare 1 mode, bit 3 + 16 + 1 + + OC1M_3 + read-write + + Normal + Normal output compare mode (modes 0-7) + 0 + + + Extended + Extended output compare mode (modes 7-15) + 1 + + + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + 0 + 15 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + CC2S + read-write + + TI2 + CC2 channel is configured as input, IC2 is mapped on TI2 + 1 + + + TI1 + CC2 channel is configured as input, IC2 is mapped on TI1 + 2 + + + TRC + CC2 channel is configured as input, IC2 is mapped on TRC + 3 + + + + + IC1F + Input capture 1 filter + 4 + 4 + + IC1F + read-write + + NoFilter + No filter, sampling is done at fDTS + 0 + + + FCK_INT_N2 + fSAMPLING=fCK_INT, N=2 + 1 + + + FCK_INT_N4 + fSAMPLING=fCK_INT, N=4 + 2 + + + FCK_INT_N8 + fSAMPLING=fCK_INT, N=8 + 3 + + + FDTS_Div2_N6 + fSAMPLING=fDTS/2, N=6 + 4 + + + FDTS_Div2_N8 + fSAMPLING=fDTS/2, N=8 + 5 + + + FDTS_Div4_N6 + fSAMPLING=fDTS/4, N=6 + 6 + + + FDTS_Div4_N8 + fSAMPLING=fDTS/4, N=8 + 7 + + + FDTS_Div8_N6 + fSAMPLING=fDTS/8, N=6 + 8 + + + FDTS_Div8_N8 + fSAMPLING=fDTS/8, N=8 + 9 + + + FDTS_Div16_N5 + fSAMPLING=fDTS/16, N=5 + 10 + + + FDTS_Div16_N6 + fSAMPLING=fDTS/16, N=6 + 11 + + + FDTS_Div16_N8 + fSAMPLING=fDTS/16, N=8 + 12 + + + FDTS_Div32_N5 + fSAMPLING=fDTS/32, N=5 + 13 + + + FDTS_Div32_N6 + fSAMPLING=fDTS/32, N=6 + 14 + + + FDTS_Div32_N8 + fSAMPLING=fDTS/32, N=8 + 15 + + + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + CC1S + read-write + + TI1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 1 + + + TI2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 2 + + + TRC + CC1 channel is configured as input, IC1 is mapped on TRC + 3 + + + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + O24CE + 15 + 1 + + + OC4M + OC4M + 12 + 3 + + + + OC4PE + OC4PE + 11 + 1 + + OC4PE + read-write + + Disabled + Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately + 0 + + + Enabled + Preload register on CCR4 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC4FE + OC4FE + 10 + 1 + + + CC4S + CC4S + 8 + 2 + + CC4S + read-write + + Output + CC4 channel is configured as output + 0 + + + + + OC3CE + OC3CE + 7 + 1 + + + OC3M + OC3M + 4 + 3 + + OC3M + read-write + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive + 0 + + + ActiveOnMatch + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 + 1 + + + InactiveOnMatch + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved + 3 + + + ForceInactive + OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF + 4 + + + ForceActive + OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF + 5 + + + PwmMode1 + In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down + 6 + + + PwmMode2 + Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 + 7 + + + + + OC3PE + OC3PE + 3 + 1 + + OC3PE + read-write + + Disabled + Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately + 0 + + + Enabled + Preload register on CCR3 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC3FE + OC3FE + 2 + 1 + + + CC3S + CC3S + 0 + 2 + + CC3S + read-write + + Output + CC3 channel is configured as output + 0 + + + + + OC3M_3 + Output Compare 3 mode, bit 3 + 16 + 1 + + OC3M_3 + read-write + + Normal + Normal output compare mode (modes 0-7) + 0 + + + Extended + Extended output compare mode (modes 7-15) + 1 + + + + + OC4M_3 + Output Compare 4 mode, bit 3 + 24 + 1 + + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + 0 + 15 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + 0 + 3 + + + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + CC4S + read-write + + TI4 + CC4 channel is configured as input, IC4 is mapped on TI4 + 1 + + + TI3 + CC4 channel is configured as input, IC4 is mapped on TI3 + 2 + + + TRC + CC4 channel is configured as input, IC4 is mapped on TRC + 3 + + + + + IC3F + Input capture 3 filter + 4 + 4 + + + 0 + 15 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + 0 + 3 + + + + + CC3S + Capture/compare 3 selection + 0 + 2 + + CC3S + read-write + + TI3 + CC3 channel is configured as input, IC3 is mapped on TI3 + 1 + + + TI4 + CC3 channel is configured as input, IC3 is mapped on TI4 + 2 + + + TRC + CC3 channel is configured as input, IC3 is mapped on TRC + 3 + + + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC4NP + Capture/Compare 4 output Polarity + 15 + 1 + + + CC4P + Capture/Compare 3 output Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output Polarity + 11 + 1 + + + CC3P + Capture/Compare 3 output Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + Counter value + 0 + 32 + + + 0 + 4294967295 + + + + + UIFCPY + UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0 + + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + 0 + 65535 + + + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 32 + + + 0 + 4294967295 + + + + + + + 4 + 0x4 + 1-4 + CCR%s + CCR1 + capture/compare register + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR + Capture/Compare value + 0 + 32 + + + 0 + 4294967295 + + + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x00000000 + + + DBL + DMA burst length + 8 + 5 + + + 0 + 18 + + + + + DBA + DMA base address + 0 + 5 + + + 0 + 31 + + + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x00000000 + + + DMAB + DMA register for burst accesses + 0 + 32 + + + + + OR + OR1 + TIM2 option register 1 + 0x50 + 0x20 + read-write + 0x00000000 + + + ITR1_RMP + Internal trigger 1 remap + 10 + 2 + + + + + + + TIM3 + General purpose timers + TIM + 0x40000400 + + 0x0 + 0x400 + registers + + + TIM3 + TIM3 global interrupt + 29 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + CKD + Clock division + 8 + 2 + + CKD + read-write + + Div1 + t_DTS = t_CK_INT + 0 + + + Div2 + t_DTS = 2 × t_CK_INT + 1 + + + Div4 + t_DTS = 4 × t_CK_INT + 2 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + + ARPE + read-write + + Disabled + TIMx_APRR register is not buffered + 0 + + + Enabled + TIMx_APRR register is buffered + 1 + + + + + CMS + Center-aligned mode selection + 5 + 2 + + CMS + read-write + + EdgeAligned + The counter counts up or down depending on the direction bit + 0 + + + CenterAligned1 + The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. + 1 + + + CenterAligned2 + The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. + 2 + + + CenterAligned3 + The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. + 3 + + + + + DIR + Direction + 4 + 1 + + DIR + read-write + + Up + Counter used as upcounter + 0 + + + Down + Counter used as downcounter + 1 + + + + + OPM + One-pulse mode + 3 + 1 + + OPM + read-write + + Disabled + Counter is not stopped at update event + 0 + + + Enabled + Counter stops counting at the next update event (clearing the CEN bit) + 1 + + + + + URS + Update request source + 2 + 1 + + URS + read-write + + AnyEvent + Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + 0 + + + CounterOnly + Only counter overflow/underflow generates an update interrupt or DMA request + 1 + + + + + UDIS + Update disable + 1 + 1 + + UDIS + read-write + + Enabled + Update event enabled + 0 + + + Disabled + Update event disabled + 1 + + + + + CEN + Counter enable + 0 + 1 + + CEN + read-write + + Disabled + Counter disabled + 0 + + + Enabled + Counter enabled + 1 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + TI1S + TI1 selection + 7 + 1 + + TI1S + read-write + + Normal + The TIMx_CH1 pin is connected to TI1 input + 0 + + + XOR + The TIMx_CH1, CH2, CH3 pins are connected to TI1 input + 1 + + + + + MMS + Master mode selection + 4 + 3 + + MMS + read-write + + Reset + The UG bit from the TIMx_EGR register is used as trigger output + 0 + + + Enable + The counter enable signal, CNT_EN, is used as trigger output + 1 + + + Update + The update event is selected as trigger output + 2 + + + ComparePulse + The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + 3 + + + CompareOC1 + OC1REF signal is used as trigger output + 4 + + + CompareOC2 + OC2REF signal is used as trigger output + 5 + + + CompareOC3 + OC3REF signal is used as trigger output + 6 + + + CompareOC4 + OC4REF signal is used as trigger output + 7 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + + CCDS + read-write + + OnCompare + CCx DMA request sent when CCx event occurs + 0 + + + OnUpdate + CCx DMA request sent when update event occurs + 1 + + + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + SMS + Slave mode selection + 0 + 3 + + SMS + read-write + + Disabled + Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. + 0 + + + Encoder_Mode_1 + Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. + 1 + + + Encoder_Mode_2 + Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. + 2 + + + Encoder_Mode_3 + Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + 3 + + + Reset_Mode + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 4 + + + Gated_Mode + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + 5 + + + Trigger_Mode + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + 6 + + + Ext_Clock_Mode + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 7 + + + + + TS + Trigger selection + 4 + 3 + + TS + read-write + + ITR0 + Internal Trigger 0 (ITR0) + 0 + + + ITR1 + Internal Trigger 1 (ITR1) + 1 + + + ITR2 + Internal Trigger 2 (ITR2) + 2 + + + TI1F_ED + TI1 Edge Detector (TI1F_ED) + 4 + + + TI1FP1 + Filtered Timer Input 1 (TI1FP1) + 5 + + + TI2FP2 + Filtered Timer Input 2 (TI2FP2) + 6 + + + ETRF + External Trigger input (ETRF) + 7 + + + + + MSM + Master/Slave mode + 7 + 1 + + MSM + read-write + + NoSync + No action + 0 + + + Sync + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + 1 + + + + + ETF + External trigger filter + 8 + 4 + + ETF + read-write + + NoFilter + No filter, sampling is done at fDTS + 0 + + + FCK_INT_N2 + fSAMPLING=fCK_INT, N=2 + 1 + + + FCK_INT_N4 + fSAMPLING=fCK_INT, N=4 + 2 + + + FCK_INT_N8 + fSAMPLING=fCK_INT, N=8 + 3 + + + FDTS_Div2_N6 + fSAMPLING=fDTS/2, N=6 + 4 + + + FDTS_Div2_N8 + fSAMPLING=fDTS/2, N=8 + 5 + + + FDTS_Div4_N6 + fSAMPLING=fDTS/4, N=6 + 6 + + + FDTS_Div4_N8 + fSAMPLING=fDTS/4, N=8 + 7 + + + FDTS_Div8_N6 + fSAMPLING=fDTS/8, N=6 + 8 + + + FDTS_Div8_N8 + fSAMPLING=fDTS/8, N=8 + 9 + + + FDTS_Div16_N5 + fSAMPLING=fDTS/16, N=5 + 10 + + + FDTS_Div16_N6 + fSAMPLING=fDTS/16, N=6 + 11 + + + FDTS_Div16_N8 + fSAMPLING=fDTS/16, N=8 + 12 + + + FDTS_Div32_N5 + fSAMPLING=fDTS/32, N=5 + 13 + + + FDTS_Div32_N6 + fSAMPLING=fDTS/32, N=6 + 14 + + + FDTS_Div32_N8 + fSAMPLING=fDTS/32, N=8 + 15 + + + + + ETPS + External trigger prescaler + 12 + 2 + + ETPS + read-write + + Div1 + Prescaler OFF + 0 + + + Div2 + ETRP frequency divided by 2 + 1 + + + Div4 + ETRP frequency divided by 4 + 2 + + + Div8 + ETRP frequency divided by 8 + 3 + + + + + ECE + External clock enable + 14 + 1 + + ECE + read-write + + Disabled + External clock mode 2 disabled + 0 + + + Enabled + External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. + 1 + + + + + ETP + External trigger polarity + 15 + 1 + + ETP + read-write + + NotInverted + ETR is noninverted, active at high level or rising edge + 0 + + + Inverted + ETR is inverted, active at low level or falling edge + 1 + + + + + SMS_3 + Slave model selection - bit[3] + 16 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + TDE + Trigger DMA request enable + 14 + 1 + + TDE + read-write + + Disabled + Trigger DMA request disabled + 0 + + + Enabled + Trigger DMA request enabled + 1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + CC1DE + read-write + + Disabled + CCx DMA request disabled + 0 + + + Enabled + CCx DMA request enabled + 1 + + + + + UDE + Update DMA request enable + 8 + 1 + + UDE + read-write + + Disabled + Update DMA request disabled + 0 + + + Enabled + Update DMA request enabled + 1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + + TIE + read-write + + Disabled + Trigger interrupt disabled + 0 + + + Enabled + Trigger interrupt enabled + 1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + CC1IE + read-write + + Disabled + CCx interrupt disabled + 0 + + + Enabled + CCx interrupt enabled + 1 + + + + + UIE + Update interrupt enable + 0 + 1 + + UIE + read-write + + Disabled + Update interrupt disabled + 0 + + + Enabled + Update interrupt enabled + 1 + + + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + CC4OF + Capture/Compare 4 overcapture flag + 12 + 1 + zeroToClear + + read + + + write + + + + CC3OF + Capture/Compare 3 overcapture flag + 11 + 1 + zeroToClear + + read + + + write + + + + CC2OF + Capture/compare 2 overcapture flag + 10 + 1 + zeroToClear + + read + + + write + + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + zeroToClear + + CC1OFR + read + + Overcapture + The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set + 1 + + + + CC1OFW + write + + Clear + Clear flag + 0 + + + + + TIF + Trigger interrupt flag + 6 + 1 + zeroToClear + + TIFR + read + + NoTrigger + No trigger event occurred + 0 + + + Trigger + Trigger interrupt pending + 1 + + + + TIFW + write + + Clear + Clear flag + 0 + + + + + CC4IF + Capture/Compare 4 interrupt flag + 4 + 1 + zeroToClear + + read + + + write + + + + CC3IF + Capture/Compare 3 interrupt flag + 3 + 1 + zeroToClear + + read + + + write + + + + CC2IF + Capture/Compare 2 interrupt flag + 2 + 1 + zeroToClear + + read + + + write + + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + zeroToClear + + CC1IFR + read + + Match + If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. + 1 + + + + CC1IFW + write + + Clear + Clear flag + 0 + + + + + UIF + Update interrupt flag + 0 + 1 + zeroToClear + + UIFR + read + + NoUpdateOccurred + No update occurred + 0 + + + UpdatePending + Update interrupt pending + 1 + + + + UIFW + write + + Clear + Clear flag + 0 + + + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + TG + Trigger generation + 6 + 1 + + TGW + write + + Trigger + The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. + 1 + + + + + CC4G + Capture/compare 4 generation + 4 + 1 + + + + CC3G + Capture/compare 3 generation + 3 + 1 + + + + CC2G + Capture/compare 2 generation + 2 + 1 + + + + CC1G + Capture/compare 1 generation + 1 + 1 + + CC1GW + write + + Trigger + If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. + 1 + + + + + UG + Update generation + 0 + 1 + + UG + write + + Update + Re-initializes the timer counter and generates an update of the registers. + 1 + + + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + OC2CE + 15 + 1 + + + OC2M + OC2M + 12 + 3 + + + + OC2PE + OC2PE + 11 + 1 + + OC2PE + read-write + + Disabled + Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately + 0 + + + Enabled + Preload register on CCR2 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC2FE + OC2FE + 10 + 1 + + + CC2S + CC2S + 8 + 2 + + CC2S + read-write + + Output + CC2 channel is configured as output + 0 + + + + + OC1CE + OC1CE + 7 + 1 + + + OC1M + OC1M + 4 + 3 + + OC1M + read-write + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive + 0 + + + ActiveOnMatch + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 + 1 + + + InactiveOnMatch + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved + 3 + + + ForceInactive + OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF + 4 + + + ForceActive + OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF + 5 + + + PwmMode1 + In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down + 6 + + + PwmMode2 + Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 + 7 + + + + + OC1PE + OC1PE + 3 + 1 + + OC1PE + read-write + + Disabled + Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately + 0 + + + Enabled + Preload register on CCR1 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC1FE + OC1FE + 2 + 1 + + + CC1S + CC1S + 0 + 2 + + CC1S + read-write + + Output + CC1 channel is configured as output + 0 + + + + + OC2M_3 + Output Compare 2 mode, bit 3 + 24 + 1 + + + + OC1M_3 + Output Compare 1 mode, bit 3 + 16 + 1 + + OC1M_3 + read-write + + Normal + Normal output compare mode (modes 0-7) + 0 + + + Extended + Extended output compare mode (modes 7-15) + 1 + + + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + 0 + 15 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + CC2S + read-write + + TI2 + CC2 channel is configured as input, IC2 is mapped on TI2 + 1 + + + TI1 + CC2 channel is configured as input, IC2 is mapped on TI1 + 2 + + + TRC + CC2 channel is configured as input, IC2 is mapped on TRC + 3 + + + + + IC1F + Input capture 1 filter + 4 + 4 + + IC1F + read-write + + NoFilter + No filter, sampling is done at fDTS + 0 + + + FCK_INT_N2 + fSAMPLING=fCK_INT, N=2 + 1 + + + FCK_INT_N4 + fSAMPLING=fCK_INT, N=4 + 2 + + + FCK_INT_N8 + fSAMPLING=fCK_INT, N=8 + 3 + + + FDTS_Div2_N6 + fSAMPLING=fDTS/2, N=6 + 4 + + + FDTS_Div2_N8 + fSAMPLING=fDTS/2, N=8 + 5 + + + FDTS_Div4_N6 + fSAMPLING=fDTS/4, N=6 + 6 + + + FDTS_Div4_N8 + fSAMPLING=fDTS/4, N=8 + 7 + + + FDTS_Div8_N6 + fSAMPLING=fDTS/8, N=6 + 8 + + + FDTS_Div8_N8 + fSAMPLING=fDTS/8, N=8 + 9 + + + FDTS_Div16_N5 + fSAMPLING=fDTS/16, N=5 + 10 + + + FDTS_Div16_N6 + fSAMPLING=fDTS/16, N=6 + 11 + + + FDTS_Div16_N8 + fSAMPLING=fDTS/16, N=8 + 12 + + + FDTS_Div32_N5 + fSAMPLING=fDTS/32, N=5 + 13 + + + FDTS_Div32_N6 + fSAMPLING=fDTS/32, N=6 + 14 + + + FDTS_Div32_N8 + fSAMPLING=fDTS/32, N=8 + 15 + + + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + CC1S + read-write + + TI1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 1 + + + TI2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 2 + + + TRC + CC1 channel is configured as input, IC1 is mapped on TRC + 3 + + + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + O24CE + 15 + 1 + + + OC4M + OC4M + 12 + 3 + + + + OC4PE + OC4PE + 11 + 1 + + OC4PE + read-write + + Disabled + Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately + 0 + + + Enabled + Preload register on CCR4 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC4FE + OC4FE + 10 + 1 + + + CC4S + CC4S + 8 + 2 + + CC4S + read-write + + Output + CC4 channel is configured as output + 0 + + + + + OC3CE + OC3CE + 7 + 1 + + + OC3M + OC3M + 4 + 3 + + OC3M + read-write + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive + 0 + + + ActiveOnMatch + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 + 1 + + + InactiveOnMatch + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved + 3 + + + ForceInactive + OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF + 4 + + + ForceActive + OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF + 5 + + + PwmMode1 + In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down + 6 + + + PwmMode2 + Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 + 7 + + + + + OC3PE + OC3PE + 3 + 1 + + OC3PE + read-write + + Disabled + Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately + 0 + + + Enabled + Preload register on CCR3 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC3FE + OC3FE + 2 + 1 + + + CC3S + CC3S + 0 + 2 + + CC3S + read-write + + Output + CC3 channel is configured as output + 0 + + + + + OC3M_3 + Output Compare 3 mode, bit 3 + 16 + 1 + + OC3M_3 + read-write + + Normal + Normal output compare mode (modes 0-7) + 0 + + + Extended + Extended output compare mode (modes 7-15) + 1 + + + + + OC4M_3 + Output Compare 4 mode, bit 3 + 24 + 1 + + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + 0 + 15 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + 0 + 3 + + + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + CC4S + read-write + + TI4 + CC4 channel is configured as input, IC4 is mapped on TI4 + 1 + + + TI3 + CC4 channel is configured as input, IC4 is mapped on TI3 + 2 + + + TRC + CC4 channel is configured as input, IC4 is mapped on TRC + 3 + + + + + IC3F + Input capture 3 filter + 4 + 4 + + + 0 + 15 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + 0 + 3 + + + + + CC3S + Capture/compare 3 selection + 0 + 2 + + CC3S + read-write + + TI3 + CC3 channel is configured as input, IC3 is mapped on TI3 + 1 + + + TI4 + CC3 channel is configured as input, IC3 is mapped on TI4 + 2 + + + TRC + CC3 channel is configured as input, IC3 is mapped on TRC + 3 + + + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC4NP + Capture/Compare 4 output Polarity + 15 + 1 + + + CC4P + Capture/Compare 3 output Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output Polarity + 11 + 1 + + + CC3P + Capture/Compare 3 output Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + Counter value + 0 + 16 + + + 0 + 65535 + + + + + UIFCPY + UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0 + + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + 0 + 65535 + + + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + 0 + 65535 + + + + + + + 4 + 0x4 + 1-4 + CCR%s + CCR1 + capture/compare register + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR + Capture/Compare value + 0 + 16 + + + 0 + 65535 + + + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x00000000 + + + DBL + DMA burst length + 8 + 5 + + + 0 + 18 + + + + + DBA + DMA base address + 0 + 5 + + + 0 + 31 + + + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x00000000 + + + DMAB + DMA register for burst accesses + 0 + 32 + + + + + + + TIM4 + General purpose timers + TIM + 0x40000800 + + TIM4 + TIM4 global interrupt + 30 + + + + TIM5 + General purpose timers + TIM + 0x40000C00 + + 0x0 + 0x400 + registers + + + TIM5 + TIM5 global interrupt + 50 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + CKD + Clock division + 8 + 2 + + CKD + read-write + + Div1 + t_DTS = t_CK_INT + 0 + + + Div2 + t_DTS = 2 × t_CK_INT + 1 + + + Div4 + t_DTS = 4 × t_CK_INT + 2 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + + ARPE + read-write + + Disabled + TIMx_APRR register is not buffered + 0 + + + Enabled + TIMx_APRR register is buffered + 1 + + + + + CMS + Center-aligned mode selection + 5 + 2 + + CMS + read-write + + EdgeAligned + The counter counts up or down depending on the direction bit + 0 + + + CenterAligned1 + The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. + 1 + + + CenterAligned2 + The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. + 2 + + + CenterAligned3 + The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. + 3 + + + + + DIR + Direction + 4 + 1 + + DIR + read-write + + Up + Counter used as upcounter + 0 + + + Down + Counter used as downcounter + 1 + + + + + OPM + One-pulse mode + 3 + 1 + + OPM + read-write + + Disabled + Counter is not stopped at update event + 0 + + + Enabled + Counter stops counting at the next update event (clearing the CEN bit) + 1 + + + + + URS + Update request source + 2 + 1 + + URS + read-write + + AnyEvent + Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + 0 + + + CounterOnly + Only counter overflow/underflow generates an update interrupt or DMA request + 1 + + + + + UDIS + Update disable + 1 + 1 + + UDIS + read-write + + Enabled + Update event enabled + 0 + + + Disabled + Update event disabled + 1 + + + + + CEN + Counter enable + 0 + 1 + + CEN + read-write + + Disabled + Counter disabled + 0 + + + Enabled + Counter enabled + 1 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + TI1S + TI1 selection + 7 + 1 + + TI1S + read-write + + Normal + The TIMx_CH1 pin is connected to TI1 input + 0 + + + XOR + The TIMx_CH1, CH2, CH3 pins are connected to TI1 input + 1 + + + + + MMS + Master mode selection + 4 + 3 + + MMS + read-write + + Reset + The UG bit from the TIMx_EGR register is used as trigger output + 0 + + + Enable + The counter enable signal, CNT_EN, is used as trigger output + 1 + + + Update + The update event is selected as trigger output + 2 + + + ComparePulse + The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + 3 + + + CompareOC1 + OC1REF signal is used as trigger output + 4 + + + CompareOC2 + OC2REF signal is used as trigger output + 5 + + + CompareOC3 + OC3REF signal is used as trigger output + 6 + + + CompareOC4 + OC4REF signal is used as trigger output + 7 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + + CCDS + read-write + + OnCompare + CCx DMA request sent when CCx event occurs + 0 + + + OnUpdate + CCx DMA request sent when update event occurs + 1 + + + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + SMS + Slave mode selection + 0 + 3 + + SMS + read-write + + Disabled + Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. + 0 + + + Encoder_Mode_1 + Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. + 1 + + + Encoder_Mode_2 + Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. + 2 + + + Encoder_Mode_3 + Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + 3 + + + Reset_Mode + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 4 + + + Gated_Mode + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + 5 + + + Trigger_Mode + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + 6 + + + Ext_Clock_Mode + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 7 + + + + + TS + Trigger selection + 4 + 3 + + TS + read-write + + ITR0 + Internal Trigger 0 (ITR0) + 0 + + + ITR1 + Internal Trigger 1 (ITR1) + 1 + + + ITR2 + Internal Trigger 2 (ITR2) + 2 + + + TI1F_ED + TI1 Edge Detector (TI1F_ED) + 4 + + + TI1FP1 + Filtered Timer Input 1 (TI1FP1) + 5 + + + TI2FP2 + Filtered Timer Input 2 (TI2FP2) + 6 + + + ETRF + External Trigger input (ETRF) + 7 + + + + + MSM + Master/Slave mode + 7 + 1 + + MSM + read-write + + NoSync + No action + 0 + + + Sync + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + 1 + + + + + ETF + External trigger filter + 8 + 4 + + ETF + read-write + + NoFilter + No filter, sampling is done at fDTS + 0 + + + FCK_INT_N2 + fSAMPLING=fCK_INT, N=2 + 1 + + + FCK_INT_N4 + fSAMPLING=fCK_INT, N=4 + 2 + + + FCK_INT_N8 + fSAMPLING=fCK_INT, N=8 + 3 + + + FDTS_Div2_N6 + fSAMPLING=fDTS/2, N=6 + 4 + + + FDTS_Div2_N8 + fSAMPLING=fDTS/2, N=8 + 5 + + + FDTS_Div4_N6 + fSAMPLING=fDTS/4, N=6 + 6 + + + FDTS_Div4_N8 + fSAMPLING=fDTS/4, N=8 + 7 + + + FDTS_Div8_N6 + fSAMPLING=fDTS/8, N=6 + 8 + + + FDTS_Div8_N8 + fSAMPLING=fDTS/8, N=8 + 9 + + + FDTS_Div16_N5 + fSAMPLING=fDTS/16, N=5 + 10 + + + FDTS_Div16_N6 + fSAMPLING=fDTS/16, N=6 + 11 + + + FDTS_Div16_N8 + fSAMPLING=fDTS/16, N=8 + 12 + + + FDTS_Div32_N5 + fSAMPLING=fDTS/32, N=5 + 13 + + + FDTS_Div32_N6 + fSAMPLING=fDTS/32, N=6 + 14 + + + FDTS_Div32_N8 + fSAMPLING=fDTS/32, N=8 + 15 + + + + + ETPS + External trigger prescaler + 12 + 2 + + ETPS + read-write + + Div1 + Prescaler OFF + 0 + + + Div2 + ETRP frequency divided by 2 + 1 + + + Div4 + ETRP frequency divided by 4 + 2 + + + Div8 + ETRP frequency divided by 8 + 3 + + + + + ECE + External clock enable + 14 + 1 + + ECE + read-write + + Disabled + External clock mode 2 disabled + 0 + + + Enabled + External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. + 1 + + + + + ETP + External trigger polarity + 15 + 1 + + ETP + read-write + + NotInverted + ETR is noninverted, active at high level or rising edge + 0 + + + Inverted + ETR is inverted, active at low level or falling edge + 1 + + + + + SMS_3 + Slave model selection - bit[3] + 16 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + TDE + Trigger DMA request enable + 14 + 1 + + TDE + read-write + + Disabled + Trigger DMA request disabled + 0 + + + Enabled + Trigger DMA request enabled + 1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + CC1DE + read-write + + Disabled + CCx DMA request disabled + 0 + + + Enabled + CCx DMA request enabled + 1 + + + + + UDE + Update DMA request enable + 8 + 1 + + UDE + read-write + + Disabled + Update DMA request disabled + 0 + + + Enabled + Update DMA request enabled + 1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + + TIE + read-write + + Disabled + Trigger interrupt disabled + 0 + + + Enabled + Trigger interrupt enabled + 1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + CC1IE + read-write + + Disabled + CCx interrupt disabled + 0 + + + Enabled + CCx interrupt enabled + 1 + + + + + UIE + Update interrupt enable + 0 + 1 + + UIE + read-write + + Disabled + Update interrupt disabled + 0 + + + Enabled + Update interrupt enabled + 1 + + + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + CC4OF + Capture/Compare 4 overcapture flag + 12 + 1 + zeroToClear + + read + + + write + + + + CC3OF + Capture/Compare 3 overcapture flag + 11 + 1 + zeroToClear + + read + + + write + + + + CC2OF + Capture/compare 2 overcapture flag + 10 + 1 + zeroToClear + + read + + + write + + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + zeroToClear + + CC1OFR + read + + Overcapture + The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set + 1 + + + + CC1OFW + write + + Clear + Clear flag + 0 + + + + + TIF + Trigger interrupt flag + 6 + 1 + zeroToClear + + TIFR + read + + NoTrigger + No trigger event occurred + 0 + + + Trigger + Trigger interrupt pending + 1 + + + + TIFW + write + + Clear + Clear flag + 0 + + + + + CC4IF + Capture/Compare 4 interrupt flag + 4 + 1 + zeroToClear + + read + + + write + + + + CC3IF + Capture/Compare 3 interrupt flag + 3 + 1 + zeroToClear + + read + + + write + + + + CC2IF + Capture/Compare 2 interrupt flag + 2 + 1 + zeroToClear + + read + + + write + + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + zeroToClear + + CC1IFR + read + + Match + If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register. + 1 + + + + CC1IFW + write + + Clear + Clear flag + 0 + + + + + UIF + Update interrupt flag + 0 + 1 + zeroToClear + + UIFR + read + + NoUpdateOccurred + No update occurred + 0 + + + UpdatePending + Update interrupt pending + 1 + + + + UIFW + write + + Clear + Clear flag + 0 + + + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + TG + Trigger generation + 6 + 1 + + TGW + write + + Trigger + The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. + 1 + + + + + CC4G + Capture/compare 4 generation + 4 + 1 + + + + CC3G + Capture/compare 3 generation + 3 + 1 + + + + CC2G + Capture/compare 2 generation + 2 + 1 + + + + CC1G + Capture/compare 1 generation + 1 + 1 + + CC1GW + write + + Trigger + If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register. + 1 + + + + + UG + Update generation + 0 + 1 + + UG + write + + Update + Re-initializes the timer counter and generates an update of the registers. + 1 + + + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + OC2CE + 15 + 1 + + + OC2M + OC2M + 12 + 3 + + + + OC2PE + OC2PE + 11 + 1 + + OC2PE + read-write + + Disabled + Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately + 0 + + + Enabled + Preload register on CCR2 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC2FE + OC2FE + 10 + 1 + + + CC2S + CC2S + 8 + 2 + + CC2S + read-write + + Output + CC2 channel is configured as output + 0 + + + + + OC1CE + OC1CE + 7 + 1 + + + OC1M + OC1M + 4 + 3 + + OC1M + read-write + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive + 0 + + + ActiveOnMatch + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 + 1 + + + InactiveOnMatch + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved + 3 + + + ForceInactive + OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF + 4 + + + ForceActive + OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF + 5 + + + PwmMode1 + In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down + 6 + + + PwmMode2 + Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 + 7 + + + + + OC1PE + OC1PE + 3 + 1 + + OC1PE + read-write + + Disabled + Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately + 0 + + + Enabled + Preload register on CCR1 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC1FE + OC1FE + 2 + 1 + + + CC1S + CC1S + 0 + 2 + + CC1S + read-write + + Output + CC1 channel is configured as output + 0 + + + + + OC2M_3 + Output Compare 2 mode, bit 3 + 24 + 1 + + + + OC1M_3 + Output Compare 1 mode, bit 3 + 16 + 1 + + OC1M_3 + read-write + + Normal + Normal output compare mode (modes 0-7) + 0 + + + Extended + Extended output compare mode (modes 7-15) + 1 + + + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + 0 + 15 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + CC2S + read-write + + TI2 + CC2 channel is configured as input, IC2 is mapped on TI2 + 1 + + + TI1 + CC2 channel is configured as input, IC2 is mapped on TI1 + 2 + + + TRC + CC2 channel is configured as input, IC2 is mapped on TRC + 3 + + + + + IC1F + Input capture 1 filter + 4 + 4 + + IC1F + read-write + + NoFilter + No filter, sampling is done at fDTS + 0 + + + FCK_INT_N2 + fSAMPLING=fCK_INT, N=2 + 1 + + + FCK_INT_N4 + fSAMPLING=fCK_INT, N=4 + 2 + + + FCK_INT_N8 + fSAMPLING=fCK_INT, N=8 + 3 + + + FDTS_Div2_N6 + fSAMPLING=fDTS/2, N=6 + 4 + + + FDTS_Div2_N8 + fSAMPLING=fDTS/2, N=8 + 5 + + + FDTS_Div4_N6 + fSAMPLING=fDTS/4, N=6 + 6 + + + FDTS_Div4_N8 + fSAMPLING=fDTS/4, N=8 + 7 + + + FDTS_Div8_N6 + fSAMPLING=fDTS/8, N=6 + 8 + + + FDTS_Div8_N8 + fSAMPLING=fDTS/8, N=8 + 9 + + + FDTS_Div16_N5 + fSAMPLING=fDTS/16, N=5 + 10 + + + FDTS_Div16_N6 + fSAMPLING=fDTS/16, N=6 + 11 + + + FDTS_Div16_N8 + fSAMPLING=fDTS/16, N=8 + 12 + + + FDTS_Div32_N5 + fSAMPLING=fDTS/32, N=5 + 13 + + + FDTS_Div32_N6 + fSAMPLING=fDTS/32, N=6 + 14 + + + FDTS_Div32_N8 + fSAMPLING=fDTS/32, N=8 + 15 + + + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + CC1S + read-write + + TI1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 1 + + + TI2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 2 + + + TRC + CC1 channel is configured as input, IC1 is mapped on TRC + 3 + + + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + O24CE + 15 + 1 + + + OC4M + OC4M + 12 + 3 + + + + OC4PE + OC4PE + 11 + 1 + + OC4PE + read-write + + Disabled + Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately + 0 + + + Enabled + Preload register on CCR4 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC4FE + OC4FE + 10 + 1 + + + CC4S + CC4S + 8 + 2 + + CC4S + read-write + + Output + CC4 channel is configured as output + 0 + + + + + OC3CE + OC3CE + 7 + 1 + + + OC3M + OC3M + 4 + 3 + + OC3M + read-write + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive + 0 + + + ActiveOnMatch + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 + 1 + + + InactiveOnMatch + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved + 3 + + + ForceInactive + OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF + 4 + + + ForceActive + OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF + 5 + + + PwmMode1 + In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down + 6 + + + PwmMode2 + Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 + 7 + + + + + OC3PE + OC3PE + 3 + 1 + + OC3PE + read-write + + Disabled + Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately + 0 + + + Enabled + Preload register on CCR3 enabled. Preload value is loaded into active register on each update event + 1 + + + + + OC3FE + OC3FE + 2 + 1 + + + CC3S + CC3S + 0 + 2 + + CC3S + read-write + + Output + CC3 channel is configured as output + 0 + + + + + OC3M_3 + Output Compare 3 mode, bit 3 + 16 + 1 + + OC3M_3 + read-write + + Normal + Normal output compare mode (modes 0-7) + 0 + + + Extended + Extended output compare mode (modes 7-15) + 1 + + + + + OC4M_3 + Output Compare 4 mode, bit 3 + 24 + 1 + + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + 0 + 15 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + 0 + 3 + + + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + CC4S + read-write + + TI4 + CC4 channel is configured as input, IC4 is mapped on TI4 + 1 + + + TI3 + CC4 channel is configured as input, IC4 is mapped on TI3 + 2 + + + TRC + CC4 channel is configured as input, IC4 is mapped on TRC + 3 + + + + + IC3F + Input capture 3 filter + 4 + 4 + + + 0 + 15 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + 0 + 3 + + + + + CC3S + Capture/compare 3 selection + 0 + 2 + + CC3S + read-write + + TI3 + CC3 channel is configured as input, IC3 is mapped on TI3 + 1 + + + TI4 + CC3 channel is configured as input, IC3 is mapped on TI4 + 2 + + + TRC + CC3 channel is configured as input, IC3 is mapped on TRC + 3 + + + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC4NP + Capture/Compare 4 output Polarity + 15 + 1 + + + CC4P + Capture/Compare 3 output Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output Polarity + 11 + 1 + + + CC3P + Capture/Compare 3 output Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + Counter value + 0 + 32 + + + 0 + 4294967295 + + + + + UIFCPY + UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0 + + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + 0 + 65535 + + + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 32 + + + 0 + 4294967295 + + + + + + + 4 + 0x4 + 1-4 + CCR%s + CCR1 + capture/compare register + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR + Capture/Compare value + 0 + 32 + + + 0 + 4294967295 + + + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x00000000 + + + DBL + DMA burst length + 8 + 5 + + + 0 + 18 + + + + + DBA + DMA base address + 0 + 5 + + + 0 + 31 + + + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x00000000 + + + DMAB + DMA register for burst accesses + 0 + 32 + + + + + OR + OR1 + TIM2 option register 1 + 0x50 + 0x20 + read-write + 0x00000000 + + + TI4_RMP + Input Capture 4 remap + 6 + 2 + + + + + + + TIM9 + General purpose timers + TIM + 0x40014000 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + CKD + Clock division + 8 + 2 + + CKD + read-write + + Div1 + t_DTS = t_CK_INT + 0 + + + Div2 + t_DTS = 2 × t_CK_INT + 1 + + + Div4 + t_DTS = 4 × t_CK_INT + 2 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + + ARPE + read-write + + Disabled + TIMx_APRR register is not buffered + 0 + + + Enabled + TIMx_APRR register is buffered + 1 + + + + + OPM + One-pulse mode + 3 + 1 + + OPM + read-write + + Disabled + Counter is not stopped at update event + 0 + + + Enabled + Counter stops counting at the next update event (clearing the CEN bit) + 1 + + + + + URS + Update request source + 2 + 1 + + URS + read-write + + AnyEvent + Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + 0 + + + CounterOnly + Only counter overflow/underflow generates an update interrupt or DMA request + 1 + + + + + UDIS + Update disable + 1 + 1 + + UDIS + read-write + + Enabled + Update event enabled + 0 + + + Disabled + Update event disabled + 1 + + + + + CEN + Counter enable + 0 + 1 + + CEN + read-write + + Disabled + Counter disabled + 0 + + + Enabled + Counter enabled + 1 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + SMS_3 + Slave mode selection - bit 3 + 16 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + UIE + read-write + + Disabled + Update interrupt disabled + 0 + + + Enabled + Update interrupt enabled + 1 + + + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + CC2OF + Capture/compare 2 overcapture flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC2IF + Capture/Compare 2 interrupt flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + zeroToClear + + UIFR + read + + NoUpdateOccurred + No update occurred + 0 + + + UpdatePending + Update interrupt pending + 1 + + + + UIFW + write + + Clear + Clear flag + 0 + + + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + TG + Trigger generation + 6 + 1 + + + CC2G + Capture/compare 2 generation + 2 + 1 + + + CC1G + Capture/compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + UG + write + + Update + Re-initializes the timer counter and generates an update of the registers. + 1 + + + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + + OC2PE + Output Compare 2 preload enable + 11 + 1 + + + OC2FE + Output Compare 2 fast enable + 10 + 1 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + + OC1M + Output Compare 1 mode + 4 + 3 + + OC1M + read-write + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive + 0 + + + ActiveOnMatch + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 + 1 + + + InactiveOnMatch + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved + 3 + + + ForceInactive + OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF + 4 + + + ForceActive + OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF + 5 + + + PwmMode1 + In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved + 6 + + + PwmMode2 + Inversely to PwmMode1 / Reserved + 7 + + + + + OC1PE + Output Compare 1 preload enable + 3 + 1 + + + OC1FE + Output Compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + OC2M_3 + Output Compare 2 mode, bit 3 + 24 + 1 + + + + OC1M_3 + Output Compare 1 mode, bit 3 + 16 + 1 + + OC1M_3 + read-write + + Normal + Normal output compare mode (modes 0-7) + 0 + + + Extended + Extended output compare mode (modes 7-15) + 1 + + + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 3 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 3 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC2NP + Capture/Compare 2 output Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + 0 + 65535 + + + + + UIFCPY + UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0 + + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + 0 + 65535 + + + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + 0 + 65535 + + + + + + + 2 + 0x4 + 1-2 + CCR%s + CCR1 + capture/compare register + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR + Capture/Compare value + 0 + 16 + + + 0 + 65535 + + + + + + + + + TIM12 + TIM + 0x40001800 + + + TIM10 + General-purpose-timers + TIM + 0x40014400 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + CKD + Clock division + 8 + 2 + + CKD + read-write + + Div1 + t_DTS = t_CK_INT + 0 + + + Div2 + t_DTS = 2 × t_CK_INT + 1 + + + Div4 + t_DTS = 4 × t_CK_INT + 2 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + + ARPE + read-write + + Disabled + TIMx_APRR register is not buffered + 0 + + + Enabled + TIMx_APRR register is buffered + 1 + + + + + URS + Update request source + 2 + 1 + + URS + read-write + + AnyEvent + Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + 0 + + + CounterOnly + Only counter overflow/underflow generates an update interrupt or DMA request + 1 + + + + + UDIS + Update disable + 1 + 1 + + UDIS + read-write + + Enabled + Update event enabled + 0 + + + Disabled + Update event disabled + 1 + + + + + CEN + Counter enable + 0 + 1 + + CEN + read-write + + Disabled + Counter disabled + 0 + + + Enabled + Counter enabled + 1 + + + + + OPM + One-pulse mode + 3 + 1 + + OPM + read-write + + Disabled + Counter is not stopped at update event + 0 + + + Enabled + Counter stops counting at the next update event (clearing the CEN bit) + 1 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + UIE + read-write + + Disabled + Update interrupt disabled + 0 + + + Enabled + Update interrupt enabled + 1 + + + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + zeroToClear + + UIFR + read + + NoUpdateOccurred + No update occurred + 0 + + + UpdatePending + Update interrupt pending + 1 + + + + UIFW + write + + Clear + Clear flag + 0 + + + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + CC1G + Capture/compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + UG + write + + Update + Re-initializes the timer counter and generates an update of the registers. + 1 + + + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC1M + Output Compare 1 mode + 4 + 3 + + OC1M + read-write + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + 0 + + + ActiveOnMatch + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + 1 + + + InactiveOnMatch + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy + 3 + + + ForceInactive + OCyREF is forced low + 4 + + + ForceActive + OCyREF is forced high + 5 + + + PwmMode1 + In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active + 6 + + + PwmMode2 + Inversely to PwmMode1 + 7 + + + + + OC1PE + Output Compare 1 preload enable + 3 + 1 + + + OC1FE + Output Compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + OC1M_3 + Output Compare 1 mode, bit 3 + 16 + 1 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + 0 + 65535 + + + + + UIFCPY + UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0 + + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + 0 + 65535 + + + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + 0 + 65535 + + + + + + + 1 + 0x0 + 1-1 + CCR%s + CCR1 + capture/compare register + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR + Capture/Compare value + 0 + 16 + + + 0 + 65535 + + + + + + + OR + OR + option register + 0x50 + 0x20 + read-write + 0x00000000 + + + TI1_RMP + TIM11 Input 1 remapping capability + 0 + 2 + + + + + + + TIM11 + TIM + 0x40014800 + + + TIM13 + TIM + 0x40001C00 + + + TIM14 + TIM + 0x40002000 + + + TIM6 + Basic timers + TIM + 0x40001000 + + 0x0 + 0x400 + registers + + + TIM6_DAC + TIM6 global interrupt, DAC1 and DAC2 underrun + error interrupt + 54 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + ARPE + Auto-reload preload enable + 7 + 1 + + ARPE + read-write + + Disabled + TIMx_APRR register is not buffered + 0 + + + Enabled + TIMx_APRR register is buffered + 1 + + + + + OPM + One-pulse mode + 3 + 1 + + OPM + read-write + + Disabled + Counter is not stopped at update event + 0 + + + Enabled + Counter stops counting at the next update event (clearing the CEN bit) + 1 + + + + + URS + Update request source + 2 + 1 + + URS + read-write + + AnyEvent + Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + 0 + + + CounterOnly + Only counter overflow/underflow generates an update interrupt or DMA request + 1 + + + + + UDIS + Update disable + 1 + 1 + + UDIS + read-write + + Enabled + Update event enabled + 0 + + + Disabled + Update event disabled + 1 + + + + + CEN + Counter enable + 0 + 1 + + CEN + read-write + + Disabled + Counter disabled + 0 + + + Enabled + Counter enabled + 1 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + MMS + Master mode selection + 4 + 3 + + MMS + read-write + + Reset + Use UG bit from TIMx_EGR register + 0 + + + Enable + Use CNT bit from TIMx_CEN register + 1 + + + Update + Use the update event + 2 + + + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + UDE + Update DMA request enable + 8 + 1 + + UDE + read-write + + Disabled + Update DMA request disabled + 0 + + + Enabled + Update DMA request enabled + 1 + + + + + UIE + Update interrupt enable + 0 + 1 + + UIE + read-write + + Disabled + Update interrupt disabled + 0 + + + Enabled + Update interrupt enabled + 1 + + + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + UIF + Update interrupt flag + 0 + 1 + zeroToClear + + UIFR + read + + NoUpdateOccurred + No update occurred + 0 + + + UpdatePending + Update interrupt pending + 1 + + + + UIFW + write + + Clear + Clear flag + 0 + + + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + UG + Update generation + 0 + 1 + + UG + write + + Update + Re-initializes the timer counter and generates an update of the registers. + 1 + + + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + Low counter value + 0 + 16 + + + 0 + 65535 + + + + + UIFCPY + UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0 + + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + 0 + 65535 + + + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Low Auto-reload value + 0 + 16 + + + 0 + 65535 + + + + + + + + + TIM7 + TIM + 0x40001400 + + TIM7 + TIM7 global interrupt + 55 + + + + Ethernet_MAC + Ethernet: media access control (MAC) + Ethernet + 0x40028000 + + 0x0 + 0x100 + registers + + + + MACCR + MACCR + Ethernet MAC configuration register + 0x0 + 0x20 + read-write + 0x00008000 + + + RE + Receiver enable + 2 + 1 + + RE + read-write + + Disabled + MAC receive state machine is disabled after the completion of the reception of the current frame + 0 + + + Enabled + MAC receive state machine is enabled + 1 + + + + + TE + Transmitter enable + 3 + 1 + + TE + read-write + + Disabled + MAC transmit state machine is disabled after completion of the transmission of the current frame + 0 + + + Enabled + MAC transmit state machine is enabled + 1 + + + + + DC + Deferral check + 4 + 1 + + DC + read-write + + Disabled + MAC defers until CRS signal goes inactive + 0 + + + Enabled + Deferral check function enabled + 1 + + + + + BL + Back-off limit + 5 + 2 + + BL + read-write + + BL10 + For retransmission n, wait up to 2^min(n, 10) time slots + 0 + + + BL8 + For retransmission n, wait up to 2^min(n, 8) time slots + 1 + + + BL4 + For retransmission n, wait up to 2^min(n, 4) time slots + 2 + + + BL1 + For retransmission n, wait up to 2^min(n, 1) time slots + 3 + + + + + APCS + Automatic pad/CRC stripping + 7 + 1 + + APCS + read-write + + Disabled + MAC passes all incoming frames unmodified + 0 + + + Strip + MAC strips the Pad/FCS field on incoming frames only for lengths less than or equal to 1500 bytes + 1 + + + + + RD + Retry disable + 9 + 1 + + RD + read-write + + Enabled + MAC attempts retries based on the settings of BL + 0 + + + Disabled + MAC attempts only 1 transmission + 1 + + + + + IPCO + IPv4 checksum offload + 10 + 1 + + IPCO + read-write + + Disabled + IPv4 checksum offload disabled + 0 + + + Offload + IPv4 checksums are checked in received frames + 1 + + + + + DM + Duplex mode + 11 + 1 + + DM + read-write + + HalfDuplex + MAC operates in half-duplex mode + 0 + + + FullDuplex + MAC operates in full-duplex mode + 1 + + + + + LM + Loopback mode + 12 + 1 + + LM + read-write + + Normal + Normal mode + 0 + + + Loopback + MAC operates in loopback mode at the MII + 1 + + + + + ROD + Receive own disable + 13 + 1 + + ROD + read-write + + Enabled + MAC receives all packets from PHY while transmitting + 0 + + + Disabled + MAC disables reception of frames in half-duplex mode + 1 + + + + + FES + Fast Ethernet speed + 14 + 1 + + FES + read-write + + FES10 + 10 Mbit/s + 0 + + + FES100 + 100 Mbit/s + 1 + + + + + CSD + Carrier sense disable + 16 + 1 + + CSD + read-write + + Enabled + Errors generated due to loss of carrier + 0 + + + Disabled + No error generated due to loss of carrier + 1 + + + + + IFG + Interframe gap + 17 + 3 + + IFG + read-write + + IFG96 + 96 bit times + 0 + + + IFG88 + 88 bit times + 1 + + + IFG80 + 80 bit times + 2 + + + IFG72 + 72 bit times + 3 + + + IFG64 + 64 bit times + 4 + + + IFG56 + 56 bit times + 5 + + + IFG48 + 48 bit times + 6 + + + IFG40 + 40 bit times + 7 + + + + + JD + Jabber disable + 22 + 1 + + JD + read-write + + Enabled + Jabber enabled, transmit frames up to 2048 bytes + 0 + + + Disabled + Jabber disabled, transmit frames up to 16384 bytes + 1 + + + + + WD + Watchdog disable + 23 + 1 + + WD + read-write + + Enabled + Watchdog enabled, receive frames limited to 2048 bytes + 0 + + + Disabled + Watchdog disabled, receive frames may be up to to 16384 bytes + 1 + + + + + CSTF + CRC stripping for type frames + 25 + 1 + + CSTF + read-write + + Disabled + CRC not stripped + 0 + + + Enabled + CRC stripped + 1 + + + + + + + MACFFR + MACFFR + Ethernet MAC frame filter register + 0x4 + 0x20 + read-write + 0x00000000 + + + PM + Promiscuous mode + 0 + 1 + + PM + read-write + + Disabled + Normal address filtering + 0 + + + Enabled + Address filters pass all incoming frames regardless of their destination or source address + 1 + + + + + HU + Hash unicast + 1 + 1 + + HU + read-write + + Perfect + MAC performs a perfect destination address filtering for unicast frames + 0 + + + Hash + MAC performs destination address filtering of received unicast frames according to the hash table + 1 + + + + + HM + Hash multicast + 2 + 1 + + HM + read-write + + Perfect + MAC performs a perfect destination address filtering for multicast frames + 0 + + + Hash + MAC performs destination address filtering of received multicast frames according to the hash table + 1 + + + + + DAIF + Destination address unique filtering + 3 + 1 + + DAIF + read-write + + Normal + Normal filtering of frames + 0 + + + Invert + Address check block operates in inverse filtering mode for the DA address comparison + 1 + + + + + PAM + Pass all multicast + 4 + 1 + + PAM + read-write + + Disabled + Filtering of multicast frames depends on HM + 0 + + + Enabled + All received frames with a multicast destination address are passed + 1 + + + + + BFD + Broadcast frames disable + 5 + 1 + + BFD + read-write + + Enabled + Address filters pass all received broadcast frames + 0 + + + Disabled + Address filters filter all incoming broadcast frames + 1 + + + + + PCF + Pass control frames + 6 + 2 + + PCF + read-write + + PreventAll + MAC prevents all control frames from reaching the application + 0 + + + ForwardAllExceptPause + MAC forwards all control frames to application except Pause + 1 + + + ForwardAll + MAC forwards all control frames to application even if they fail the address filter + 2 + + + ForwardAllFiltered + MAC forwards control frames that pass the address filter + 3 + + + + + SAIF + Source address inverse filtering + 7 + 1 + + SAIF + read-write + + Normal + Source address filter operates normally + 0 + + + Invert + Source address filter operation inverted + 1 + + + + + SAF + Source address filter + 8 + 1 + + SAF + read-write + + Disabled + Source address ignored + 0 + + + Enabled + MAC drops frames that fail the source address filter + 1 + + + + + HPF + Hash or perfect filter + 9 + 1 + + HPF + read-write + + HashOnly + If HM or HU is set, only frames that match the Hash filter are passed + 0 + + + HashOrPerfect + If HM or HU is set, frames that match either the perfect filter or the hash filter are passed + 1 + + + + + RA + Receive all + 31 + 1 + + RA + read-write + + Disabled + MAC receiver passes on to the application only those frames that have passed the SA/DA address file + 0 + + + Enabled + MAC receiver passes oll received frames on to the application + 1 + + + + + + + MACHTHR + MACHTHR + Ethernet MAC hash table high register + 0x8 + 0x20 + read-write + 0x00000000 + + + HTH + Upper 32 bits of hash table + 0 + 32 + + + 0 + 4294967295 + + + + + + + MACHTLR + MACHTLR + Ethernet MAC hash table low register + 0xC + 0x20 + read-write + 0x00000000 + + + HTL + Lower 32 bits of hash table + 0 + 32 + + + 0 + 4294967295 + + + + + + + MACMIIAR + MACMIIAR + Ethernet MAC MII address register + 0x10 + 0x20 + read-write + 0x00000000 + + + MB + MII busy + 0 + 1 + + MB + read-write + + Busy + This bit is set to 1 by the application to indicate that a read or write access is in progress + 1 + + + + + MW + MII write + 1 + 1 + + MW + read-write + + Read + Read operation + 0 + + + Write + Write operation + 1 + + + + + CR + Clock range + 2 + 3 + + CR + read-write + + CR_60_100 + 60-100MHz HCLK/42 + 0 + + + CR_100_150 + 100-150 MHz HCLK/62 + 1 + + + CR_20_35 + 20-35MHz HCLK/16 + 2 + + + CR_35_60 + 35-60MHz HCLK/16 + 3 + + + CR_150_168 + 150-168MHz HCLK/102 + 4 + + + + + MR + MII register - select the desired MII register in the PHY device + 6 + 5 + + + 0 + 31 + + + + + PA + PHY address - select which of possible 32 PHYs is being accessed + 11 + 5 + + + 0 + 31 + + + + + + + MACMIIDR + MACMIIDR + Ethernet MAC MII data register + 0x14 + 0x20 + read-write + 0x00000000 + + + MD + MII data read from/written to the PHY + 0 + 16 + + + 0 + 65535 + + + + + + + MACFCR + MACFCR + Ethernet MAC flow control register + 0x18 + 0x20 + read-write + 0x00000000 + + + FCB + Flow control busy/back pressure activate + 0 + 1 + + FCB + read-write + + DisableBackPressure + In half duplex only, deasserts back pressure + 0 + + + PauseOrBackPressure + In full duplex, initiate a Pause control frame. In half duplex, assert back pressure + 1 + + + + + TFCE + Transmit flow control enable + 1 + 1 + + TFCE + read-write + + Disabled + In full duplex, flow control is disabled. In half duplex, back pressure is disabled + 0 + + + Enabled + In full duplex, flow control is enabled. In half duplex, back pressure is enabled + 1 + + + + + RFCE + Receive flow control enable + 2 + 1 + + RFCE + read-write + + Disabled + Pause frames are not decoded + 0 + + + Enabled + MAC decodes received Pause frames and disables its transmitted for a specified time + 1 + + + + + UPFD + Unicast pause frame detect + 3 + 1 + + UPFD + read-write + + Disabled + MAC detects only a Pause frame with the multicast address specified in the 802.3x standard + 0 + + + Enabled + MAC additionally detects Pause frames with the station's unicast address + 1 + + + + + PLT + Pause low threshold + 4 + 2 + + PLT + read-write + + PLT4 + Pause time minus 4 slot times + 0 + + + PLT28 + Pause time minus 28 slot times + 1 + + + PLT144 + Pause time minus 144 slot times + 2 + + + PLT256 + Pause time minus 256 slot times + 3 + + + + + ZQPD + Zero-quanta pause disable + 7 + 1 + + ZQPD + read-write + + Enabled + Normal operation with automatic zero-quanta pause control frame generation + 0 + + + Disabled + Automatic generation of zero-quanta pause control frames is disabled + 1 + + + + + PT + Pause time + 16 + 16 + + + 0 + 65535 + + + + + + + MACVLANTR + MACVLANTR + Ethernet MAC VLAN tag register + 0x1C + 0x20 + read-write + 0x00000000 + + + VLANTI + VLAN tag identifier (for receive frames) + 0 + 16 + + + 0 + 65535 + + + + + VLANTC + 12-bit VLAN tag comparison + 16 + 1 + + VLANTC + read-write + + VLANTC16 + Full 16 bit VLAN identifiers are used for comparison and filtering + 0 + + + VLANTC12 + 12 bit VLAN identifies are used for comparison and filtering + 1 + + + + + + + MACPMTCSR + MACPMTCSR + Ethernet MAC PMT control and status register + 0x2C + 0x20 + read-write + 0x00000000 + + + PD + Power down + 0 + 1 + + PD + read-write + + Enabled + All received frames will be dropped. Cleared automatically when a magic packet or wakeup frame is received + 1 + + + + + MPE + Magic packet enable + 1 + 1 + + MPE + read-write + + Disabled + No power management event generated due to Magic Packet reception + 0 + + + Enabled + Enable generation of a power management event due to Magic Packet reception + 1 + + + + + WFE + Wakeup frame enable + 2 + 1 + + WFE + read-write + + Disabled + No power management event generated due to wakeup frame reception + 0 + + + Enabled + Enable generation of a power management event due to wakeup frame reception + 1 + + + + + MPR + Magic packet received + 5 + 1 + + + WFR + Wakeup frame received + 6 + 1 + + + GU + Global unicast + 9 + 1 + + GU + read-write + + Disabled + Normal operation + 0 + + + Enabled + Any unicast packet filtered by the MAC address recognition may be a wakeup frame + 1 + + + + + WFFRPR + Wakeup frame filter register pointer reset + 31 + 1 + + WFFRPR + read-write + + Reset + Reset wakeup frame filter register point to 0b000. Automatically cleared + 1 + + + + + + + MACDBGR + MACDBGR + Ethernet MAC debug register + 0x34 + 0x20 + read-only + 0x00000000 + + + TFF + Tx FIFO full + 25 + 1 + + + TFNE + Tx FIFO not empty + 24 + 1 + + + TFWA + Tx FIFO write active + 22 + 1 + + + TFRS + Tx FIFO read status + 20 + 2 + + + MTP + MAC transmitter in pause + 19 + 1 + + + MTFCS + MAC transmit frame controller status + 17 + 2 + + + MMTEA + MAC MII transmit engine active + 16 + 1 + + + RFFL + Rx FIFO fill level + 8 + 2 + + + RFRCS + Rx FIFO read controller status + 5 + 2 + + + RFWRA + Rx FIFO write controller active + 4 + 1 + + + MSFRWCS + MAC small FIFO read/write controllers status + 1 + 2 + + + MMRPEA + MAC MII receive protocol engine active + 0 + 1 + + + + + MACSR + MACSR + Ethernet MAC interrupt status register + 0x38 + 0x20 + 0x00000000 + + + PMTS + PMT status + 3 + 1 + read-only + + + MMCS + MMC status + 4 + 1 + read-only + + + MMCRS + MMC receive status + 5 + 1 + read-only + + + MMCTS + MMC transmit status + 6 + 1 + read-only + + + TSTS + Time stamp trigger status + 9 + 1 + read-write + + + + + MACIMR + MACIMR + Ethernet MAC interrupt mask register + 0x3C + 0x20 + read-write + 0x00000000 + + + PMTIM + PMT interrupt mask + 3 + 1 + + PMTIM + read-write + + Unmasked + PMT Status interrupt generation enabled + 0 + + + Masked + PMT Status interrupt generation disabled + 1 + + + + + TSTIM + Time stamp trigger interrupt mask + 9 + 1 + + TSTIM + read-write + + Unmasked + Time stamp interrupt generation enabled + 0 + + + Masked + Time stamp interrupt generation disabled + 1 + + + + + + + MACA0HR + MACA0HR + Ethernet MAC address 0 high register + 0x40 + 0x20 + 0x0010FFFF + + + MACA0H + MAC address0 high + 0 + 16 + read-write + + + 0 + 65535 + + + + + MO + Always 1 + 31 + 1 + read-only + + + + + MACA0LR + MACA0LR + Ethernet MAC address 0 low register + 0x44 + 0x20 + read-write + 0xFFFFFFFF + + + MACA0L + 0 + 0 + 32 + + + 0 + 4294967295 + + + + + + + MACA1HR + MACA1HR + Ethernet MAC address 1 high register + 0x48 + 0x20 + read-write + 0x0000FFFF + + + MACA1H + MACA1H + 0 + 16 + + + 0 + 65535 + + + + + MBC + MBC + 24 + 6 + + + 0 + 63 + + + + + SA + SA + 30 + 1 + + SA + read-write + + Destination + This address is used for comparison with DA fields of the received frame + 0 + + + Source + This address is used for comparison with SA fields of received frames + 1 + + + + + AE + AE + 31 + 1 + + AE + read-write + + Disabled + Address filters ignore this address + 0 + + + Enabled + Address filters use this address + 1 + + + + + + + MACA1LR + MACA1LR + Ethernet MAC address1 low register + 0x4C + 0x20 + read-write + 0xFFFFFFFF + + + MACA1L + MACA1LR + 0 + 32 + + + 0 + 4294967295 + + + + + + + MACA2HR + MACA2HR + Ethernet MAC address 2 high register + 0x50 + 0x20 + read-write + 0x0000FFFF + + + MACA2H + MAC2AH + 0 + 16 + + + 0 + 65535 + + + + + MBC + MBC + 24 + 6 + + + 0 + 63 + + + + + SA + SA + 30 + 1 + + SA + read-write + + Destination + This address is used for comparison with DA fields of the received frame + 0 + + + Source + This address is used for comparison with SA fields of received frames + 1 + + + + + AE + AE + 31 + 1 + + AE + read-write + + Disabled + Address filters ignore this address + 0 + + + Enabled + Address filters use this address + 1 + + + + + + + MACA2LR + MACA2LR + Ethernet MAC address 2 low register + 0x54 + 0x20 + read-write + 0xFFFFFFFF + + + MACA2L + MACA2L + 0 + 32 + + + 0 + 4294967295 + + + + + + + MACA3HR + MACA3HR + Ethernet MAC address 3 high register + 0x58 + 0x20 + read-write + 0x0000FFFF + + + MACA3H + MACA3H + 0 + 16 + + + 0 + 65535 + + + + + MBC + MBC + 24 + 6 + + + 0 + 63 + + + + + SA + SA + 30 + 1 + + SA + read-write + + Destination + This address is used for comparison with DA fields of the received frame + 0 + + + Source + This address is used for comparison with SA fields of received frames + 1 + + + + + AE + AE + 31 + 1 + + AE + read-write + + Disabled + Address filters ignore this address + 0 + + + Enabled + Address filters use this address + 1 + + + + + + + MACA3LR + MACA3LR + Ethernet MAC address 3 low register + 0x5C + 0x20 + read-write + 0xFFFFFFFF + + + MACA3L + MBCA3L + 0 + 32 + + + 0 + 4294967295 + + + + + + + MACRWUFFER + MACRWUFFER + Ethernet MAC remote wakeup frame filter register + 0x60 + 0x20 + read-write + 0xFFFFFFFF + + + + + Ethernet_MMC + Ethernet: MAC management counters + Ethernet + 0x40028100 + + 0x0 + 0x400 + registers + + + + MMCCR + MMCCR + Ethernet MMC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + CR + Counter reset + 0 + 1 + + CR + read-write + + Reset + Reset all counters. Cleared automatically + 1 + + + + + CSR + Counter stop rollover + 1 + 1 + + CSR + read-write + + Disabled + Counters roll over to zero after reaching the maximum value + 0 + + + Enabled + Counters do not roll over to zero after reaching the maximum value + 1 + + + + + ROR + Reset on read + 2 + 1 + + ROR + read-write + + Disabled + MMC counters do not reset on read + 0 + + + Enabled + MMC counters reset to zero after read + 1 + + + + + MCF + MMC counter freeze + 3 + 1 + + MCF + read-write + + Unfrozen + All MMC counters update normally + 0 + + + Frozen + All MMC counters frozen to their current value + 1 + + + + + MCP + MMC counter preset + 4 + 1 + + MCP + read-write + + Preset + MMC counters will be preset to almost full or almost half. Cleared automatically + 1 + + + + + MCFHP + MMC counter Full-Half preset + 5 + 1 + + MCFHP + read-write + + AlmostHalf + When MCP is set, MMC counters are preset to almost-half value 0x7FFF_FFF0 + 0 + + + AlmostFull + When MCP is set, MMC counters are preset to almost-full value 0xFFFF_FFF0 + 1 + + + + + + + MMCRIR + MMCRIR + Ethernet MMC receive interrupt register + 0x4 + 0x20 + read-write + 0x00000000 + + + RFCES + Received frames CRC error status + 5 + 1 + + + RFAES + Received frames alignment error status + 6 + 1 + + + RGUFS + Received good Unicast frames status + 17 + 1 + + + + + MMCTIR + MMCTIR + Ethernet MMC transmit interrupt register + 0x8 + 0x20 + read-only + 0x00000000 + + + TGFSCS + Transmitted good frames single collision status + 14 + 1 + + + TGFMSCS + Transmitted good frames more than single collision status + 15 + 1 + + + TGFS + Transmitted good frames status + 21 + 1 + + + + + MMCRIMR + MMCRIMR + Ethernet MMC receive interrupt mask register + 0xC + 0x20 + read-write + 0x00000000 + + + RFCEM + Received frame CRC error mask + 5 + 1 + + RFCEM + read-write + + Unmasked + Received-crc-error counter half-full interrupt enabled + 0 + + + Masked + Received-crc-error counter half-full interrupt disabled + 1 + + + + + RFAEM + Received frames alignment error mask + 6 + 1 + + RFAEM + read-write + + Unmasked + Received-alignment-error counter half-full interrupt enabled + 0 + + + Masked + Received-alignment-error counter half-full interrupt disabled + 1 + + + + + RGUFM + Received good Unicast frames mask + 17 + 1 + + RGUFM + read-write + + Unmasked + Received-good-unicast counter half-full interrupt enabled + 0 + + + Masked + Received-good-unicast counter half-full interrupt disabled + 1 + + + + + + + MMCTIMR + MMCTIMR + Ethernet MMC transmit interrupt mask register + 0x10 + 0x20 + read-write + 0x00000000 + + + TGFSCM + Transmitted good frames single collision mask + 14 + 1 + + TGFSCM + read-write + + Unmasked + Transmitted-good-single-collision half-full interrupt enabled + 0 + + + Masked + Transmitted-good-single-collision half-full interrupt disabled + 1 + + + + + TGFMSCM + Transmitted good frames more than single collision mask + 15 + 1 + + TGFMSCM + read-write + + Unmasked + Transmitted-good-multiple-collision half-full interrupt enabled + 0 + + + Masked + Transmitted-good-multiple-collision half-full interrupt disabled + 1 + + + + + TGFM + Transmitted good frames mask + 21 + 1 + + TGFM + read-write + + Unmasked + Transmitted-good counter half-full interrupt enabled + 0 + + + Masked + Transmitted-good counter half-full interrupt disabled + 1 + + + + + + + MMCTGFSCCR + MMCTGFSCCR + Ethernet MMC transmitted good frames after a single collision counter + 0x4C + 0x20 + read-only + 0x00000000 + + + TGFSCC + Transmitted good frames single collision counter + 0 + 32 + + + + + MMCTGFMSCCR + MMCTGFMSCCR + Ethernet MMC transmitted good frames after more than a single collision + 0x50 + 0x20 + read-only + 0x00000000 + + + TGFMSCC + TGFMSCC + 0 + 32 + + + + + MMCTGFCR + MMCTGFCR + Ethernet MMC transmitted good frames counter register + 0x68 + 0x20 + read-only + 0x00000000 + + + TGFC + HTL + 0 + 32 + + + + + MMCRFCECR + MMCRFCECR + Ethernet MMC received frames with CRC error counter register + 0x94 + 0x20 + read-only + 0x00000000 + + + RFCFC + RFCFC + 0 + 32 + + + + + MMCRFAECR + MMCRFAECR + Ethernet MMC received frames with alignment error counter register + 0x98 + 0x20 + read-only + 0x00000000 + + + RFAEC + RFAEC + 0 + 32 + + + + + MMCRGUFCR + MMCRGUFCR + MMC received good unicast frames counter register + 0xC4 + 0x20 + read-only + 0x00000000 + + + RGUFC + RGUFC + 0 + 32 + + + + + + + Ethernet_PTP + Ethernet: Precision time protocol + Ethernet + 0x40028700 + + 0x0 + 0x400 + registers + + + + PTPTSCR + PTPTSCR + Ethernet PTP time stamp control register + 0x0 + 0x20 + read-write + 0x00002000 + + + TSE + TSE + 0 + 1 + + + TSFCU + TSFCU + 1 + 1 + + + TSPTPPSV2E + TSPTPPSV2E + 10 + 1 + + + TSSPTPOEFE + TSSPTPOEFE + 11 + 1 + + + TSSIPV6FE + TSSIPV6FE + 12 + 1 + + + TSSIPV4FE + TSSIPV4FE + 13 + 1 + + + TSSEME + TSSEME + 14 + 1 + + + TSSMRME + TSSMRME + 15 + 1 + + + TSCNT + TSCNT + 16 + 2 + + + TSPFFMAE + TSPFFMAE + 18 + 1 + + + TSSTI + TSSTI + 2 + 1 + + + TSSTU + TSSTU + 3 + 1 + + + TSITE + TSITE + 4 + 1 + + + TTSARU + TTSARU + 5 + 1 + + + TSSARFE + TSSARFE + 8 + 1 + + + TSSSR + TSSSR + 9 + 1 + + + + + PTPSSIR + PTPSSIR + Ethernet PTP subsecond increment register + 0x4 + 0x20 + read-write + 0x00000000 + + + STSSI + STSSI + 0 + 8 + + + + + PTPTSHR + PTPTSHR + Ethernet PTP time stamp high register + 0x8 + 0x20 + read-only + 0x00000000 + + + STS + STS + 0 + 32 + + + + + PTPTSLR + PTPTSLR + Ethernet PTP time stamp low register + 0xC + 0x20 + read-only + 0x00000000 + + + STSS + STSS + 0 + 31 + + + STPNS + STPNS + 31 + 1 + + + + + PTPTSHUR + PTPTSHUR + Ethernet PTP time stamp high update register + 0x10 + 0x20 + read-write + 0x00000000 + + + TSUS + TSUS + 0 + 32 + + + + + PTPTSLUR + PTPTSLUR + Ethernet PTP time stamp low update register + 0x14 + 0x20 + read-write + 0x00000000 + + + TSUSS + TSUSS + 0 + 31 + + + TSUPNS + TSUPNS + 31 + 1 + + + + + PTPTSAR + PTPTSAR + Ethernet PTP time stamp addend register + 0x18 + 0x20 + read-write + 0x00000000 + + + TSA + TSA + 0 + 32 + + + + + PTPTTHR + PTPTTHR + Ethernet PTP target time high register + 0x1C + 0x20 + read-write + 0x00000000 + + + TTSH + 0 + 0 + 32 + + + + + PTPTTLR + PTPTTLR + Ethernet PTP target time low register + 0x20 + 0x20 + read-write + 0x00000000 + + + TTSL + TTSL + 0 + 32 + + + + + PTPTSSR + PTPTSSR + Ethernet PTP time stamp status register + 0x28 + 0x20 + read-only + 0x00000000 + + + TSSO + TSSO + 0 + 1 + + + TSTTR + TSTTR + 1 + 1 + + + + + PTPPPSCR + PTPPPSCR + Ethernet PTP PPS control register + 0x2C + 0x20 + read-only + 0x00000000 + + + TSSO + TSSO + 0 + 1 + + + TSTTR + TSTTR + 1 + 1 + + + + + + + Ethernet_DMA + Ethernet: DMA controller operation + Ethernet + 0x40029000 + + 0x0 + 0x400 + registers + + + ETH + Ethernet global interrupt + 61 + + + ETH_WKUP + Ethernet Wakeup through EXTI line + interrupt + 62 + + + + DMABMR + DMABMR + Ethernet DMA bus mode register + 0x0 + 0x20 + read-write + 0x00002101 + + + SR + Software reset + 0 + 1 + + SR + read-write + + Reset + Reset all MAC subsystem internal registers and logic. Cleared automatically + 1 + + + + + DA + DMA arbitration + 1 + 1 + + DA + read-write + + RoundRobin + Round-robin with Rx:Tx priority given by PM + 0 + + + RxPriority + Rx has priority over Tx + 1 + + + + + DSL + Descriptor skip length + 2 + 5 + + + 0 + 31 + + + + + EDFE + Enhanced descriptor format enable + 7 + 1 + + EDFE + read-write + + Disabled + Normal descriptor format + 0 + + + Enabled + Enhanced 32-byte descriptor format, required for timestamping and IPv4 checksum offload + 1 + + + + + PBL + Programmable burst length + 8 + 6 + + PBL + read-write + + PBL1 + Maximum of 1 beat per DMA transaction + 1 + + + PBL2 + Maximum of 2 beats per DMA transaction + 2 + + + PBL4 + Maximum of 4 beats per DMA transaction + 4 + + + PBL8 + Maximum of 8 beats per DMA transaction + 8 + + + PBL16 + Maximum of 16 beats per DMA transaction + 16 + + + PBL32 + Maximum of 32 beats per DMA transaction + 32 + + + + + PM + Rx-Tx priority ratio + 14 + 2 + + PM + read-write + + OneToOne + RxDMA priority over TxDMA is 1:1 + 0 + + + TwoToOne + RxDMA priority over TxDMA is 2:1 + 1 + + + ThreeToOne + RxDMA priority over TxDMA is 3:1 + 2 + + + FourToOne + RxDMA priority over TxDMA is 4:1 + 3 + + + + + FB + Fixed burst + 16 + 1 + + FB + read-write + + Variable + AHB uses SINGLE and INCR burst transfers + 0 + + + Fixed + AHB uses only fixed burst transfers + 1 + + + + + RDP + Rx DMA PBL + 17 + 6 + + RDP + read-write + + RDP1 + 1 beat per RxDMA transaction + 1 + + + RDP2 + 2 beats per RxDMA transaction + 2 + + + RDP4 + 4 beats per RxDMA transaction + 4 + + + RDP8 + 8 beats per RxDMA transaction + 8 + + + RDP16 + 16 beats per RxDMA transaction + 16 + + + RDP32 + 32 beats per RxDMA transaction + 32 + + + + + USP + Use separate PBL + 23 + 1 + + USP + read-write + + Combined + PBL value used for both Rx and Tx DMA + 0 + + + Separate + RxDMA uses RDP value, TxDMA uses PBL value + 1 + + + + + FPM + 4xPBL mode + 24 + 1 + + FPM + read-write + + x1 + PBL values used as-is + 0 + + + x4 + PBL values multiplied by 4 + 1 + + + + + AAB + Address-aligned beats + 25 + 1 + + AAB + read-write + + Unaligned + Bursts are not aligned + 0 + + + Aligned + Align bursts to start address LS bits. First burst alignment depends on FB bit + 1 + + + + + MB + Mixed burst + 26 + 1 + + MB + read-write + + Normal + Fixed burst transfers (INCRx and SINGLE) for burst lengths of 16 and below + 0 + + + Mixed + If FB is low, start all bursts greater than 16 with INCR (undefined burst) + 1 + + + + + + + DMATPDR + DMATPDR + Ethernet DMA transmit poll demand register + 0x4 + 0x20 + read-write + 0x00000000 + + + TPD + Transmit poll demand + 0 + 32 + + TPD + read-write + + Poll + Poll the transmit descriptor list + 0 + + + + + + + DMARPDR + DMARPDR + EHERNET DMA receive poll demand register + 0x8 + 0x20 + read-write + 0x00000000 + + + RPD + Receive poll demand + 0 + 32 + + RPD + read-write + + Poll + Poll the receive descriptor list + 0 + + + + + + + DMARDLAR + DMARDLAR + Ethernet DMA receive descriptor list address register + 0xC + 0x20 + read-write + 0x00000000 + + + SRL + Start of receive list + 0 + 32 + + + + + DMATDLAR + DMATDLAR + Ethernet DMA transmit descriptor list address register + 0x10 + 0x20 + read-write + 0x00000000 + + + STL + Start of transmit list + 0 + 32 + + + + + DMASR + DMASR + Ethernet DMA status register + 0x14 + 0x20 + 0x00000000 + + + TS + Transmit status + 0 + 1 + read-write + + + TPSS + Transmit process stopped status + 1 + 1 + read-write + + + TBUS + Transmit buffer unavailable status + 2 + 1 + read-write + + + TJTS + Transmit jabber timeout status + 3 + 1 + read-write + + + ROS + Receive overflow status + 4 + 1 + read-write + + + TUS + Transmit underflow status + 5 + 1 + read-write + + + RS + Receive status + 6 + 1 + read-write + + + RBUS + Receive buffer unavailable status + 7 + 1 + read-write + + + RPSS + Receive process stopped status + 8 + 1 + read-write + + + PWTS + PWTS + 9 + 1 + read-write + + + ETS + Early transmit status + 10 + 1 + read-write + + + FBES + Fatal bus error status + 13 + 1 + read-write + + + ERS + Early receive status + 14 + 1 + read-write + + + AIS + Abnormal interrupt summary + 15 + 1 + read-write + + + NIS + Normal interrupt summary + 16 + 1 + read-write + + + RPS + Receive process state + 17 + 3 + read-only + + RPS + read + + Stopped + Stopped, reset or Stop Receive command issued + 0 + + + RunningFetching + Running, fetching receive transfer descriptor + 1 + + + RunningWaiting + Running, waiting for receive packet + 3 + + + Suspended + Suspended, receive descriptor unavailable + 4 + + + RunningWriting + Running, writing data to host memory buffer + 7 + + + + + TPS + Transmit process state + 20 + 3 + read-only + + TPS + read + + Stopped + Stopped, Reset or Stop Transmit command issued + 0 + + + RunningFetching + Running, fetching transmit transfer descriptor + 1 + + + RunningWaiting + Running, waiting for status + 2 + + + RunningReading + Running, reading data from host memory buffer + 3 + + + Suspended + Suspended, transmit descriptor unavailable or transmit buffer underflow + 6 + + + Running + Running, closing transmit descriptor + 7 + + + + + EBS + Error bits status + 23 + 3 + read-only + + + MMCS + MMC status + 27 + 1 + read-only + + + PMTS + PMT status + 28 + 1 + read-only + + + TSTS + Time stamp trigger status + 29 + 1 + read-only + + + + + DMAOMR + DMAOMR + Ethernet DMA operation mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + SR + Start/stop receive + 1 + 1 + + SR + read-write + + Stopped + Reception is stopped after transfer of the current frame + 0 + + + Started + Reception is placed in the Running state + 1 + + + + + OSF + Operate on second frame + 2 + 1 + + + RTC + Receive threshold control + 3 + 2 + + RTC + read-write + + RTC64 + 64 bytes + 0 + + + RTC32 + 32 bytes + 1 + + + RTC96 + 96 bytes + 2 + + + RTC128 + 128 bytes + 3 + + + + + FUGF + Forward undersized good frames + 6 + 1 + + FUGF + read-write + + Drop + Rx FIFO drops all frames of less than 64 bytes + 0 + + + Forward + Rx FIFO forwards undersized frames + 1 + + + + + FEF + Forward error frames + 7 + 1 + + FEF + read-write + + Drop + Rx FIFO drops frames with error status + 0 + + + Forward + All frames except runt error frames are forwarded to the DMA + 1 + + + + + ST + Start/stop transmission + 13 + 1 + + ST + read-write + + Stopped + Transmission is placed in the Stopped state + 0 + + + Started + Transmission is placed in Running state + 1 + + + + + TTC + Transmit threshold control + 14 + 3 + + TTC + read-write + + TTC64 + 64 bytes + 0 + + + TTC128 + 128 bytes + 1 + + + TTC192 + 192 bytes + 2 + + + TTC256 + 256 bytes + 3 + + + TTC40 + 40 bytes + 4 + + + TTC32 + 32 bytes + 5 + + + TTC24 + 24 bytes + 6 + + + TTC16 + 16 bytes + 7 + + + + + FTF + Flush transmit FIFO + 20 + 1 + + FTF + read-write + + Flush + Transmit FIFO controller logic is reset to its default values. Cleared automatically + 1 + + + + + TSF + Transmit store and forward + 21 + 1 + + TSF + read-write + + CutThrough + Transmission starts when the frame size in the Tx FIFO exceeds TTC threshold + 0 + + + StoreForward + Transmission starts when a full frame is in the Tx FIFO + 1 + + + + + DFRF + Disable flushing of received frames + 24 + 1 + + + RSF + Receive store and forward + 25 + 1 + + RSF + read-write + + CutThrough + Rx FIFO operates in cut-through mode, subject to RTC bits + 0 + + + StoreForward + Frames are read from Rx FIFO after complete frame has been written + 1 + + + + + DTCEFD + Dropping of TCP/IP checksum error frames disable + 26 + 1 + + DTCEFD + read-write + + Enabled + Drop frames with errors only in the receive checksum offload engine + 0 + + + Disabled + Do not drop frames that only have errors in the receive checksum offload engine + 1 + + + + + + + DMAIER + DMAIER + Ethernet DMA interrupt enable register + 0x1C + 0x20 + read-write + 0x00000000 + + + TIE + Transmit interrupt enable + 0 + 1 + + + TPSIE + Transmit process stopped interrupt enable + 1 + 1 + + + TBUIE + Transmit buffer unavailable interrupt enable + 2 + 1 + + + TJTIE + Transmit jabber timeout interrupt enable + 3 + 1 + + + ROIE + Receive overflow interrupt enable + 4 + 1 + + + TUIE + Transmit underflow interrupt enable + 5 + 1 + + + RIE + Receive interrupt enable + 6 + 1 + + + RBUIE + Receive buffer unavailable interrupt enable + 7 + 1 + + + RPSIE + Receive process stopped interrupt enable + 8 + 1 + + + RWTIE + Receive watchdog timeout interrupt enable + 9 + 1 + + + ETIE + Early transmit interrupt enable + 10 + 1 + + + FBEIE + Fatal bus error interrupt enable + 13 + 1 + + + ERIE + Early receive interrupt enable + 14 + 1 + + + AISE + Abnormal interrupt summary enable + 15 + 1 + + + NISE + Normal interrupt summary enable + 16 + 1 + + + + + DMAMFBOCR + DMAMFBOCR + Ethernet DMA missed frame and buffer overflow counter register + 0x20 + 0x20 + read-write + 0x00000000 + + + MFC + Missed frames by the controller + 0 + 16 + + + OMFC + Overflow bit for missed frame counter + 16 + 1 + + + MFA + Missed frames by the application + 17 + 11 + + + OFOC + Overflow bit for FIFO overflow counter + 28 + 1 + + + + + DMARSWTR + DMARSWTR + Ethernet DMA receive status watchdog timer register + 0x24 + 0x20 + read-write + 0x00000000 + + + RSWTC + Receive status watchdog timer count + 0 + 8 + + + 0 + 255 + + + + + + + DMACHTDR + DMACHTDR + Ethernet DMA current host transmit descriptor register + 0x48 + 0x20 + read-only + 0x00000000 + + + HTDAP + Host transmit descriptor address pointer + 0 + 32 + + + + + DMACHRDR + DMACHRDR + Ethernet DMA current host receive descriptor register + 0x4C + 0x20 + read-only + 0x00000000 + + + HRDAP + Host receive descriptor address pointer + 0 + 32 + + + + + DMACHTBAR + DMACHTBAR + Ethernet DMA current host transmit buffer address register + 0x50 + 0x20 + read-only + 0x00000000 + + + HTBAP + Host transmit buffer address pointer + 0 + 32 + + + + + DMACHRBAR + DMACHRBAR + Ethernet DMA current host receive buffer address register + 0x54 + 0x20 + read-only + 0x00000000 + + + HRBAP + Host receive buffer address pointer + 0 + 32 + + + + + + + CRC + Cryptographic processor + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + HDMI_CEC + HDMI-CEC global interrupt + 94 + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data Register + 0 + 32 + + + 0 + 4294967295 + + + + + + + IDR + IDR + Independent Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + Independent Data register + 0 + 8 + + + 0 + 255 + + + + + + + CR + CR + Control register + 0x8 + 0x20 + write-only + 0x00000000 + + + RESET + RESET bit + 0 + 1 + + RESETW + write + + Reset + Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF + 1 + + + + + REV_OUT + Reverse output data + 7 + 1 + read-write + + REV_OUT + read-write + + Normal + Bit order not affected + 0 + + + Reversed + Bit reversed output + 1 + + + + + REV_IN + Reverse input data + 5 + 2 + read-write + + REV_IN + read-write + + Normal + Bit order not affected + 0 + + + Byte + Bit reversal done by byte + 1 + + + HalfWord + Bit reversal done by half-word + 2 + + + Word + Bit reversal done by word + 3 + + + + + POLYSIZE + Polynomial size + 3 + 2 + read-write + + POLYSIZE + read-write + + Polysize32 + 32-bit polynomial + 0 + + + Polysize16 + 16-bit polynomial + 1 + + + Polysize8 + 8-bit polynomial + 2 + + + Polysize7 + 7-bit polynomial + 3 + + + + + + + INIT + INIT + Initial CRC value + 0x10 + 0x20 + read-write + 0x00000000 + + + INIT + Programmable initial CRC value + 0 + 32 + + + 0 + 4294967295 + + + + + + + POL + POL + CRC polynomial + 0x14 + 0x20 + read-write + 0x00000000 + + + POL + Programmable polynomial + 0 + 32 + + + 0 + 4294967295 + + + + + + + DR8 + Data register - byte sized + DR + 0x0 + 0x8 + read-write + 0x000000FF + + + DR8 + Data register bits + 0 + 8 + + + 0 + 255 + + + + + + + DR16 + Data register - half-word sized + DR + 0x0 + 0x10 + read-write + 0x0000FFFF + + + DR16 + Data register bits + 0 + 16 + + + 0 + 65535 + + + + + + + + + CAN1 + Controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + CAN1_TX + CAN1 TX interrupts + 19 + + + CAN1_RX0 + CAN1 RX0 interrupts + 20 + + + CAN1_RX1 + CAN1 RX1 interrupts + 21 + + + CAN1_SCE + CAN1 SCE interrupt + 22 + + + + MCR + MCR + master control register + 0x0 + 0x20 + read-write + 0x00010002 + + + DBF + DBF + 16 + 1 + + + RESET + RESET + 15 + 1 + + + TTCM + TTCM + 7 + 1 + + + ABOM + ABOM + 6 + 1 + + + AWUM + AWUM + 5 + 1 + + + NART + NART + 4 + 1 + + + RFLM + RFLM + 3 + 1 + + + TXFP + TXFP + 2 + 1 + + + SLEEP + SLEEP + 1 + 1 + + + INRQ + INRQ + 0 + 1 + + + + + MSR + MSR + master status register + 0x4 + 0x20 + 0x00000C02 + + + RX + RX + 11 + 1 + read-only + + + SAMP + SAMP + 10 + 1 + read-only + + + RXM + RXM + 9 + 1 + read-only + + + TXM + TXM + 8 + 1 + read-only + + + SLAKI + SLAKI + 4 + 1 + read-write + + + WKUI + WKUI + 3 + 1 + read-write + + + ERRI + ERRI + 2 + 1 + read-write + + + SLAK + SLAK + 1 + 1 + read-only + + + INAK + INAK + 0 + 1 + read-only + + + + + TSR + TSR + transmit status register + 0x8 + 0x20 + 0x1C000000 + + + LOW2 + Lowest priority flag for mailbox 2 + 31 + 1 + read-only + + + LOW1 + Lowest priority flag for mailbox 1 + 30 + 1 + read-only + + + LOW0 + Lowest priority flag for mailbox 0 + 29 + 1 + read-only + + + TME2 + Lowest priority flag for mailbox 2 + 28 + 1 + read-only + + + TME1 + Lowest priority flag for mailbox 1 + 27 + 1 + read-only + + + TME0 + Lowest priority flag for mailbox 0 + 26 + 1 + read-only + + + CODE + CODE + 24 + 2 + read-only + + + ABRQ2 + ABRQ2 + 23 + 1 + read-write + + + TERR2 + TERR2 + 19 + 1 + read-write + + + ALST2 + ALST2 + 18 + 1 + read-write + + + TXOK2 + TXOK2 + 17 + 1 + read-write + + + RQCP2 + RQCP2 + 16 + 1 + read-write + + + ABRQ1 + ABRQ1 + 15 + 1 + read-write + + + TERR1 + TERR1 + 11 + 1 + read-write + + + ALST1 + ALST1 + 10 + 1 + read-write + + + TXOK1 + TXOK1 + 9 + 1 + read-write + + + RQCP1 + RQCP1 + 8 + 1 + read-write + + + ABRQ0 + ABRQ0 + 7 + 1 + read-write + + + TERR0 + TERR0 + 3 + 1 + read-write + + + ALST0 + ALST0 + 2 + 1 + read-write + + + TXOK0 + TXOK0 + 1 + 1 + read-write + + + RQCP0 + RQCP0 + 0 + 1 + read-write + + + + + 2 + 0x4 + 0-1 + RF%sR + RF0R + receive FIFO %s register + 0xC + 0x20 + 0x00000000 + + + RFOM + RFOM0 + 5 + 1 + read-write + + RFOM0W + write + + Release + Set by software to release the output mailbox of the FIFO + 1 + + + + + FOVR + FOVR0 + 4 + 1 + read-write + + FOVR0R + read + + NoOverrun + No FIFO x overrun + 0 + + + Overrun + FIFO x overrun + 1 + + + + FOVR0W + write + + Clear + Clear flag + 1 + + + + + FULL + FULL0 + 3 + 1 + read-write + + FULL0R + read + + NotFull + FIFO x is not full + 0 + + + Full + FIFO x is full + 1 + + + + FULL0W + write + + Clear + Clear flag + 1 + + + + + FMP + FMP0 + 0 + 2 + read-only + + + + + IER + IER + interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + SLKIE + SLKIE + 17 + 1 + + SLKIE + read-write + + Disabled + No interrupt when SLAKI bit is set + 0 + + + Enabled + Interrupt generated when SLAKI bit is set + 1 + + + + + WKUIE + WKUIE + 16 + 1 + + WKUIE + read-write + + Disabled + No interrupt when WKUI is set + 0 + + + Enabled + Interrupt generated when WKUI bit is set + 1 + + + + + ERRIE + ERRIE + 15 + 1 + + ERRIE + read-write + + Disabled + No interrupt will be generated when an error condition is pending in the CAN_ESR + 0 + + + Enabled + An interrupt will be generation when an error condition is pending in the CAN_ESR + 1 + + + + + LECIE + LECIE + 11 + 1 + + LECIE + read-write + + Disabled + ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection + 0 + + + Enabled + ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection + 1 + + + + + BOFIE + BOFIE + 10 + 1 + + BOFIE + read-write + + Disabled + ERRI bit will not be set when BOFF is set + 0 + + + Enabled + ERRI bit will be set when BOFF is set + 1 + + + + + EPVIE + EPVIE + 9 + 1 + + EPVIE + read-write + + Disabled + ERRI bit will not be set when EPVF is set + 0 + + + Enabled + ERRI bit will be set when EPVF is set + 1 + + + + + EWGIE + EWGIE + 8 + 1 + + EWGIE + read-write + + Disabled + ERRI bit will not be set when EWGF is set + 0 + + + Enabled + ERRI bit will be set when EWGF is set + 1 + + + + + FOVIE1 + FOVIE1 + 6 + 1 + + FOVIE1 + read-write + + Disabled + No interrupt when FOVR is set + 0 + + + Enabled + Interrupt generation when FOVR is set + 1 + + + + + FFIE1 + FFIE1 + 5 + 1 + + FFIE1 + read-write + + Disabled + No interrupt when FULL bit is set + 0 + + + Enabled + Interrupt generated when FULL bit is set + 1 + + + + + FMPIE1 + FMPIE1 + 4 + 1 + + FMPIE1 + read-write + + Disabled + No interrupt generated when state of FMP[1:0] bits are not 00b + 0 + + + Enabled + Interrupt generated when state of FMP[1:0] bits are not 00b + 1 + + + + + FOVIE0 + FOVIE0 + 3 + 1 + + FOVIE0 + read-write + + Disabled + No interrupt when FOVR bit is set + 0 + + + Enabled + Interrupt generated when FOVR bit is set + 1 + + + + + FFIE0 + FFIE0 + 2 + 1 + + FFIE0 + read-write + + Disabled + No interrupt when FULL bit is set + 0 + + + Enabled + Interrupt generated when FULL bit is set + 1 + + + + + FMPIE0 + FMPIE0 + 1 + 1 + + FMPIE0 + read-write + + Disabled + No interrupt generated when state of FMP[1:0] bits are not 00 + 0 + + + Enabled + Interrupt generated when state of FMP[1:0] bits are not 00b + 1 + + + + + TMEIE + TMEIE + 0 + 1 + + TMEIE + read-write + + Disabled + No interrupt when RQCPx bit is set + 0 + + + Enabled + Interrupt generated when RQCPx bit is set + 1 + + + + + + + ESR + ESR + interrupt enable register + 0x18 + 0x20 + 0x00000000 + + + REC + REC + 24 + 8 + read-only + + + TEC + TEC + 16 + 8 + read-only + + + LEC + LEC + 4 + 3 + read-write + + LEC + read-write + + NoError + No Error + 0 + + + Stuff + Stuff Error + 1 + + + Form + Form Error + 2 + + + Ack + Acknowledgment Error + 3 + + + BitRecessive + Bit recessive Error + 4 + + + BitDominant + Bit dominant Error + 5 + + + Crc + CRC Error + 6 + + + Custom + Set by software + 7 + + + + + BOFF + BOFF + 2 + 1 + read-only + + + EPVF + EPVF + 1 + 1 + read-only + + + EWGF + EWGF + 0 + 1 + read-only + + + + + BTR + BTR + bit timing register + 0x1C + 0x20 + read-write + 0x00000000 + + + SILM + SILM + 31 + 1 + + SILM + read-write + + Normal + Normal operation + 0 + + + Silent + Silent Mode + 1 + + + + + LBKM + LBKM + 30 + 1 + + LBKM + read-write + + Disabled + Loop Back Mode disabled + 0 + + + Enabled + Loop Back Mode enabled + 1 + + + + + SJW + SJW + 24 + 2 + + + TS2 + TS2 + 20 + 3 + + + TS1 + TS1 + 16 + 4 + + + BRP + BRP + 0 + 10 + + + + + 3 + 0x10 + 0-2 + TX%s + CAN Transmit cluster + 0x180 + + TIR + TI0R + TX mailbox identifier register + 0x0 + 0x20 + read-write + 0x00000000 + + + STID + STID + 21 + 11 + + + EXID + EXID + 3 + 18 + + + IDE + IDE + 2 + 1 + + IDE + read-write + + Standard + Standard identifier + 0 + + + Extended + Extended identifier + 1 + + + + + RTR + RTR + 1 + 1 + + RTR + read-write + + Data + Data frame + 0 + + + Remote + Remote frame + 1 + + + + + TXRQ + TXRQ + 0 + 1 + + + + + TDTR + TDT0R + mailbox data length control and time stamp register + 0x4 + 0x20 + read-write + 0x00000000 + + + TIME + TIME + 16 + 16 + + + TGT + TGT + 8 + 1 + + + DLC + DLC + 0 + 4 + + + 0 + 8 + + + + + + + TDLR + TDL0R + mailbox data low register + 0x8 + 0x20 + read-write + 0x00000000 + + + DATA3 + DATA3 + 24 + 8 + + + DATA2 + DATA2 + 16 + 8 + + + DATA1 + DATA1 + 8 + 8 + + + DATA0 + DATA0 + 0 + 8 + + + + + TDHR + TDH0R + mailbox data high register + 0xC + 0x20 + read-write + 0x00000000 + + + DATA7 + DATA7 + 24 + 8 + + + DATA6 + DATA6 + 16 + 8 + + + DATA5 + DATA5 + 8 + 8 + + + DATA4 + DATA4 + 0 + 8 + + + + + + 2 + 0x10 + 0-1 + RX%s + CAN Receive cluster + 0x1B0 + + RIR + RI0R + receive FIFO mailbox identifier register + 0x0 + 0x20 + read-only + 0x00000000 + + + STID + STID + 21 + 11 + + + EXID + EXID + 3 + 18 + + + IDE + IDE + 2 + 1 + + IDE + read + + Standard + Standard identifier + 0 + + + Extended + Extended identifier + 1 + + + + + RTR + RTR + 1 + 1 + + RTR + read + + Data + Data frame + 0 + + + Remote + Remote frame + 1 + + + + + + + RDTR + RDT0R + mailbox data high register + 0x4 + 0x20 + read-only + 0x00000000 + + + TIME + TIME + 16 + 16 + + + FMI + FMI + 8 + 8 + + + DLC + DLC + 0 + 4 + + + 0 + 8 + + + + + + + RDLR + RDL0R + mailbox data high register + 0x8 + 0x20 + read-only + 0x00000000 + + + DATA3 + DATA3 + 24 + 8 + + + DATA2 + DATA2 + 16 + 8 + + + DATA1 + DATA1 + 8 + 8 + + + DATA0 + DATA0 + 0 + 8 + + + + + RDHR + RDH0R + receive FIFO mailbox data high register + 0xC + 0x20 + read-only + 0x00000000 + + + DATA7 + DATA7 + 24 + 8 + + + DATA6 + DATA6 + 16 + 8 + + + DATA5 + DATA5 + 8 + 8 + + + DATA4 + DATA4 + 0 + 8 + + + + + + FMR + FMR + filter master register + 0x200 + 0x20 + read-write + 0x2A1C0E01 + + + CAN2SB + CAN2SB + 8 + 6 + + + FINIT + FINIT + 0 + 1 + + + + + FM1R + FM1R + filter mode register + 0x204 + 0x20 + read-write + 0x00000000 + + + FBM0 + Filter mode + 0 + 1 + + + FBM1 + Filter mode + 1 + 1 + + + FBM2 + Filter mode + 2 + 1 + + + FBM3 + Filter mode + 3 + 1 + + + FBM4 + Filter mode + 4 + 1 + + + FBM5 + Filter mode + 5 + 1 + + + FBM6 + Filter mode + 6 + 1 + + + FBM7 + Filter mode + 7 + 1 + + + FBM8 + Filter mode + 8 + 1 + + + FBM9 + Filter mode + 9 + 1 + + + FBM10 + Filter mode + 10 + 1 + + + FBM11 + Filter mode + 11 + 1 + + + FBM12 + Filter mode + 12 + 1 + + + FBM13 + Filter mode + 13 + 1 + + + FBM14 + Filter mode + 14 + 1 + + + FBM15 + Filter mode + 15 + 1 + + + FBM16 + Filter mode + 16 + 1 + + + FBM17 + Filter mode + 17 + 1 + + + FBM18 + Filter mode + 18 + 1 + + + FBM19 + Filter mode + 19 + 1 + + + FBM20 + Filter mode + 20 + 1 + + + FBM21 + Filter mode + 21 + 1 + + + FBM22 + Filter mode + 22 + 1 + + + FBM23 + Filter mode + 23 + 1 + + + FBM24 + Filter mode + 24 + 1 + + + FBM25 + Filter mode + 25 + 1 + + + FBM26 + Filter mode + 26 + 1 + + + FBM27 + Filter mode + 27 + 1 + + + + + FS1R + FS1R + filter scale register + 0x20C + 0x20 + read-write + 0x00000000 + + + FSC0 + Filter scale configuration + 0 + 1 + + + FSC1 + Filter scale configuration + 1 + 1 + + + FSC2 + Filter scale configuration + 2 + 1 + + + FSC3 + Filter scale configuration + 3 + 1 + + + FSC4 + Filter scale configuration + 4 + 1 + + + FSC5 + Filter scale configuration + 5 + 1 + + + FSC6 + Filter scale configuration + 6 + 1 + + + FSC7 + Filter scale configuration + 7 + 1 + + + FSC8 + Filter scale configuration + 8 + 1 + + + FSC9 + Filter scale configuration + 9 + 1 + + + FSC10 + Filter scale configuration + 10 + 1 + + + FSC11 + Filter scale configuration + 11 + 1 + + + FSC12 + Filter scale configuration + 12 + 1 + + + FSC13 + Filter scale configuration + 13 + 1 + + + FSC14 + Filter scale configuration + 14 + 1 + + + FSC15 + Filter scale configuration + 15 + 1 + + + FSC16 + Filter scale configuration + 16 + 1 + + + FSC17 + Filter scale configuration + 17 + 1 + + + FSC18 + Filter scale configuration + 18 + 1 + + + FSC19 + Filter scale configuration + 19 + 1 + + + FSC20 + Filter scale configuration + 20 + 1 + + + FSC21 + Filter scale configuration + 21 + 1 + + + FSC22 + Filter scale configuration + 22 + 1 + + + FSC23 + Filter scale configuration + 23 + 1 + + + FSC24 + Filter scale configuration + 24 + 1 + + + FSC25 + Filter scale configuration + 25 + 1 + + + FSC26 + Filter scale configuration + 26 + 1 + + + FSC27 + Filter scale configuration + 27 + 1 + + + + + FFA1R + FFA1R + filter FIFO assignment register + 0x214 + 0x20 + read-write + 0x00000000 + + + FFA0 + Filter FIFO assignment for filter 0 + 0 + 1 + + + FFA1 + Filter FIFO assignment for filter 1 + 1 + 1 + + + FFA2 + Filter FIFO assignment for filter 2 + 2 + 1 + + + FFA3 + Filter FIFO assignment for filter 3 + 3 + 1 + + + FFA4 + Filter FIFO assignment for filter 4 + 4 + 1 + + + FFA5 + Filter FIFO assignment for filter 5 + 5 + 1 + + + FFA6 + Filter FIFO assignment for filter 6 + 6 + 1 + + + FFA7 + Filter FIFO assignment for filter 7 + 7 + 1 + + + FFA8 + Filter FIFO assignment for filter 8 + 8 + 1 + + + FFA9 + Filter FIFO assignment for filter 9 + 9 + 1 + + + FFA10 + Filter FIFO assignment for filter 10 + 10 + 1 + + + FFA11 + Filter FIFO assignment for filter 11 + 11 + 1 + + + FFA12 + Filter FIFO assignment for filter 12 + 12 + 1 + + + FFA13 + Filter FIFO assignment for filter 13 + 13 + 1 + + + FFA14 + Filter FIFO assignment for filter 14 + 14 + 1 + + + FFA15 + Filter FIFO assignment for filter 15 + 15 + 1 + + + FFA16 + Filter FIFO assignment for filter 16 + 16 + 1 + + + FFA17 + Filter FIFO assignment for filter 17 + 17 + 1 + + + FFA18 + Filter FIFO assignment for filter 18 + 18 + 1 + + + FFA19 + Filter FIFO assignment for filter 19 + 19 + 1 + + + FFA20 + Filter FIFO assignment for filter 20 + 20 + 1 + + + FFA21 + Filter FIFO assignment for filter 21 + 21 + 1 + + + FFA22 + Filter FIFO assignment for filter 22 + 22 + 1 + + + FFA23 + Filter FIFO assignment for filter 23 + 23 + 1 + + + FFA24 + Filter FIFO assignment for filter 24 + 24 + 1 + + + FFA25 + Filter FIFO assignment for filter 25 + 25 + 1 + + + FFA26 + Filter FIFO assignment for filter 26 + 26 + 1 + + + FFA27 + Filter FIFO assignment for filter 27 + 27 + 1 + + + + + FA1R + FA1R + filter activation register + 0x21C + 0x20 + read-write + 0x00000000 + + + FACT0 + Filter active + 0 + 1 + + + FACT1 + Filter active + 1 + 1 + + + FACT2 + Filter active + 2 + 1 + + + FACT3 + Filter active + 3 + 1 + + + FACT4 + Filter active + 4 + 1 + + + FACT5 + Filter active + 5 + 1 + + + FACT6 + Filter active + 6 + 1 + + + FACT7 + Filter active + 7 + 1 + + + FACT8 + Filter active + 8 + 1 + + + FACT9 + Filter active + 9 + 1 + + + FACT10 + Filter active + 10 + 1 + + + FACT11 + Filter active + 11 + 1 + + + FACT12 + Filter active + 12 + 1 + + + FACT13 + Filter active + 13 + 1 + + + FACT14 + Filter active + 14 + 1 + + + FACT15 + Filter active + 15 + 1 + + + FACT16 + Filter active + 16 + 1 + + + FACT17 + Filter active + 17 + 1 + + + FACT18 + Filter active + 18 + 1 + + + FACT19 + Filter active + 19 + 1 + + + FACT20 + Filter active + 20 + 1 + + + FACT21 + Filter active + 21 + 1 + + + FACT22 + Filter active + 22 + 1 + + + FACT23 + Filter active + 23 + 1 + + + FACT24 + Filter active + 24 + 1 + + + FACT25 + Filter active + 25 + 1 + + + FACT26 + Filter active + 26 + 1 + + + FACT27 + Filter active + 27 + 1 + + + + + 28 + 0x8 + 0-27 + FB%s + CAN Filter Bank cluster + 0x240 + + FR1 + F0R1 + Filter bank 0 register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + FB + Filter bits + 0 + 32 + + + + + FR2 + F0R2 + Filter bank 0 register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + FB + Filter bits + 0 + 32 + + + + + + + + CAN2 + 0x40006800 + + CAN2_TX + CAN2 TX interrupts + 63 + + + CAN2_RX0 + CAN2 RX0 interrupts + 64 + + + CAN2_RX1 + CAN2 RX1 interrupts + 65 + + + CAN2_SCE + CAN2 SCE interrupt + 66 + + + + FLASH + FLASH + FLASH + 0x40023C00 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 4 + + + + ACR + ACR + Flash access control register + 0x0 + 0x20 + read-write + 0x00000000 + + + LATENCY + Latency + 0 + 4 + + LATENCY + read-write + + WS0 + 0 wait states + 0 + + + WS1 + 1 wait states + 1 + + + WS2 + 2 wait states + 2 + + + WS3 + 3 wait states + 3 + + + WS4 + 4 wait states + 4 + + + WS5 + 5 wait states + 5 + + + WS6 + 6 wait states + 6 + + + WS7 + 7 wait states + 7 + + + WS8 + 8 wait states + 8 + + + WS9 + 9 wait states + 9 + + + WS10 + 10 wait states + 10 + + + WS11 + 11 wait states + 11 + + + WS12 + 12 wait states + 12 + + + WS13 + 13 wait states + 13 + + + WS14 + 14 wait states + 14 + + + WS15 + 15 wait states + 15 + + + + + PRFTEN + Prefetch enable + 8 + 1 + + PRFTEN + read-write + + Disabled + Prefetch is disabled + 0 + + + Enabled + Prefetch is enabled + 1 + + + + + ARTEN + ART Accelerator Enable + 9 + 1 + + ARTEN + read-write + + Disabled + ART Accelerator is disabled + 0 + + + Enabled + ART Accelerator is enabled + 1 + + + + + ARTRST + ART Accelerator reset + 11 + 1 + + ARTRST + read-write + + NotReset + Accelerator is not reset + 0 + + + Reset + Accelerator is reset + 1 + + + + + + + KEYR + KEYR + Flash key register + 0x4 + 0x20 + write-only + 0x00000000 + + + KEY + FPEC key + 0 + 32 + + + 0 + 4294967295 + + + + + + + OPTKEYR + OPTKEYR + Flash option key register + 0x8 + 0x20 + write-only + 0x00000000 + + + OPTKEYR + Option byte key + 0 + 32 + + + 0 + 4294967295 + + + + + + + SR + SR + Status register + 0xC + 0x20 + 0x00000000 + + + EOP + End of operation + 0 + 1 + read-write + oneToClear + + EOPW + write + + Clear + Clear error flag + 1 + + + + + OPERR + Operation error + 1 + 1 + read-write + oneToClear + + OPERRW + write + + Clear + Clear error flag + 1 + + + + + WRPERR + Write protection error + 4 + 1 + read-write + oneToClear + + WRPERRW + write + + Clear + Clear error flag + 1 + + + + + PGAERR + Programming alignment error + 5 + 1 + read-write + oneToClear + + PGAERRW + write + + Clear + Clear error flag + 1 + + + + + PGPERR + Programming parallelism error + 6 + 1 + read-write + oneToClear + + PGPERRW + write + + Clear + Clear error flag + 1 + + + + + ERSERR + Programming sequence error + 7 + 1 + read-write + oneToClear + + ERSERRW + write + + Clear + Clear error flag + 1 + + + + + BSY + Busy + 16 + 1 + read-only + + BSYR + read + + NotBusy + no Flash memory operation ongoing + 0 + + + Busy + Flash memory operation ongoing + 1 + + + + + + + CR + CR + Control register + 0x10 + 0x20 + read-write + 0x80000000 + + + PG + Programming + 0 + 1 + + PG + read-write + + Program + Flash programming activated + 1 + + + + + SER + Sector Erase + 1 + 1 + + SER + read-write + + SectorErase + Erase activated for selected sector + 1 + + + + + MER + Mass Erase of sectors 0 to 11 + 2 + 1 + + MER + read-write + + MassErase + Erase activated for all user sectors + 1 + + + + + SNB + Sector number + 3 + 4 + + + 0 + 11 + + + + + PSIZE + Program size + 8 + 2 + + PSIZE + read-write + + PSIZE8 + Program x8 + 0 + + + PSIZE16 + Program x16 + 1 + + + PSIZE32 + Program x32 + 2 + + + PSIZE64 + Program x64 + 3 + + + + + STRT + Start + 16 + 1 + + STRT + read-write + + Start + Trigger an erase operation + 1 + + + + + EOPIE + End of operation interrupt enable + 24 + 1 + + EOPIE + read-write + + Disabled + End of operation interrupt disabled + 0 + + + Enabled + End of operation interrupt enabled + 1 + + + + + ERRIE + Error interrupt enable + 25 + 1 + + ERRIE + read-write + + Disabled + Error interrupt generation disabled + 0 + + + Enabled + Error interrupt generation enabled + 1 + + + + + LOCK + Lock + 31 + 1 + + LOCK + read-write + + Unlocked + FLASH_CR register is unlocked + 0 + + + Locked + FLASH_CR register is locked + 1 + + + + + + + OPTCR + OPTCR + Flash option control register + 0x14 + 0x20 + read-write + 0x0FFFAAED + + + OPTLOCK + Option lock + 0 + 1 + + + OPTSTRT + Option start + 1 + 1 + + + BOR_LEV + BOR reset Level + 2 + 2 + + + WWDG_SW + User option bytes + 4 + 1 + + + IWDG_SW + User option bytes + 5 + 1 + + + nRST_STOP + User option bytes + 6 + 1 + + + nRST_STDBY + User option bytes + 7 + 1 + + + RDP + Read protect + 8 + 8 + + + nWRP + Not write protect + 16 + 8 + + + IWDG_STDBY + Independent watchdog counter freeze in standby mode + 30 + 1 + + + IWDG_STOP + Independent watchdog counter freeze in Stop mode + 31 + 1 + + + + + OPTCR1 + OPTCR1 + Flash option control register 1 + 0x18 + 0x20 + read-write + 0x0FFF0000 + + + BOOT_ADD0 + Boot base address when Boot pin =0 + 0 + 16 + + + BOOT_ADD1 + Boot base address when Boot pin =1 + 16 + 16 + + + + + + + EXTI + External interrupt/event controller + EXTI + 0x40013C00 + + 0x0 + 0x400 + registers + + + PVD + PVD through EXTI line detection INTERRUPT + 1 + + + TAMP_STAMP + Tamper and TimeStamp interrupts through the + EXTI line + 2 + + + EXTI0 + EXTI Line0 interrupt + 6 + + + EXTI1 + EXTI Line1 interrupt + 7 + + + EXTI2 + EXTI Line2 interrupt + 8 + + + EXTI3 + EXTI Line3 interrupt + 9 + + + EXTI4 + EXTI Line4 interrupt + 10 + + + EXTI9_5 + EXTI Line[9:5] interrupts + 23 + + + EXTI15_10 + EXTI Line[15:10] interrupts + 40 + + + + IMR + IMR + Interrupt mask register (EXTI_IMR) + 0x0 + 0x20 + read-write + 0x00000000 + + + MR0 + Interrupt Mask on line 0 + 0 + 1 + + MR0 + read-write + + Masked + Interrupt request line is masked + 0 + + + Unmasked + Interrupt request line is unmasked + 1 + + + + + MR1 + Interrupt Mask on line 1 + 1 + 1 + + + + MR2 + Interrupt Mask on line 2 + 2 + 1 + + + + MR3 + Interrupt Mask on line 3 + 3 + 1 + + + + MR4 + Interrupt Mask on line 4 + 4 + 1 + + + + MR5 + Interrupt Mask on line 5 + 5 + 1 + + + + MR6 + Interrupt Mask on line 6 + 6 + 1 + + + + MR7 + Interrupt Mask on line 7 + 7 + 1 + + + + MR8 + Interrupt Mask on line 8 + 8 + 1 + + + + MR9 + Interrupt Mask on line 9 + 9 + 1 + + + + MR10 + Interrupt Mask on line 10 + 10 + 1 + + + + MR11 + Interrupt Mask on line 11 + 11 + 1 + + + + MR12 + Interrupt Mask on line 12 + 12 + 1 + + + + MR13 + Interrupt Mask on line 13 + 13 + 1 + + + + MR14 + Interrupt Mask on line 14 + 14 + 1 + + + + MR15 + Interrupt Mask on line 15 + 15 + 1 + + + + MR16 + Interrupt Mask on line 16 + 16 + 1 + + + + MR17 + Interrupt Mask on line 17 + 17 + 1 + + + + MR18 + Interrupt Mask on line 18 + 18 + 1 + + + + MR19 + Interrupt Mask on line 19 + 19 + 1 + + + + MR20 + Interrupt Mask on line 20 + 20 + 1 + + + + MR21 + Interrupt Mask on line 21 + 21 + 1 + + + + MR22 + Interrupt Mask on line 22 + 22 + 1 + + + + + + EMR + EMR + Event mask register (EXTI_EMR) + 0x4 + 0x20 + read-write + 0x00000000 + + + MR0 + Event Mask on line 0 + 0 + 1 + + MR0 + read-write + + Masked + Interrupt request line is masked + 0 + + + Unmasked + Interrupt request line is unmasked + 1 + + + + + MR1 + Event Mask on line 1 + 1 + 1 + + + + MR2 + Event Mask on line 2 + 2 + 1 + + + + MR3 + Event Mask on line 3 + 3 + 1 + + + + MR4 + Event Mask on line 4 + 4 + 1 + + + + MR5 + Event Mask on line 5 + 5 + 1 + + + + MR6 + Event Mask on line 6 + 6 + 1 + + + + MR7 + Event Mask on line 7 + 7 + 1 + + + + MR8 + Event Mask on line 8 + 8 + 1 + + + + MR9 + Event Mask on line 9 + 9 + 1 + + + + MR10 + Event Mask on line 10 + 10 + 1 + + + + MR11 + Event Mask on line 11 + 11 + 1 + + + + MR12 + Event Mask on line 12 + 12 + 1 + + + + MR13 + Event Mask on line 13 + 13 + 1 + + + + MR14 + Event Mask on line 14 + 14 + 1 + + + + MR15 + Event Mask on line 15 + 15 + 1 + + + + MR16 + Event Mask on line 16 + 16 + 1 + + + + MR17 + Event Mask on line 17 + 17 + 1 + + + + MR18 + Event Mask on line 18 + 18 + 1 + + + + MR19 + Event Mask on line 19 + 19 + 1 + + + + MR20 + Event Mask on line 20 + 20 + 1 + + + + MR21 + Event Mask on line 21 + 21 + 1 + + + + MR22 + Event Mask on line 22 + 22 + 1 + + + + + + RTSR + RTSR + Rising Trigger selection register (EXTI_RTSR) + 0x8 + 0x20 + read-write + 0x00000000 + + + TR0 + Rising trigger event configuration of line 0 + 0 + 1 + + TR0 + read-write + + Disabled + Rising edge trigger is disabled + 0 + + + Enabled + Rising edge trigger is enabled + 1 + + + + + TR1 + Rising trigger event configuration of line 1 + 1 + 1 + + + + TR2 + Rising trigger event configuration of line 2 + 2 + 1 + + + + TR3 + Rising trigger event configuration of line 3 + 3 + 1 + + + + TR4 + Rising trigger event configuration of line 4 + 4 + 1 + + + + TR5 + Rising trigger event configuration of line 5 + 5 + 1 + + + + TR6 + Rising trigger event configuration of line 6 + 6 + 1 + + + + TR7 + Rising trigger event configuration of line 7 + 7 + 1 + + + + TR8 + Rising trigger event configuration of line 8 + 8 + 1 + + + + TR9 + Rising trigger event configuration of line 9 + 9 + 1 + + + + TR10 + Rising trigger event configuration of line 10 + 10 + 1 + + + + TR11 + Rising trigger event configuration of line 11 + 11 + 1 + + + + TR12 + Rising trigger event configuration of line 12 + 12 + 1 + + + + TR13 + Rising trigger event configuration of line 13 + 13 + 1 + + + + TR14 + Rising trigger event configuration of line 14 + 14 + 1 + + + + TR15 + Rising trigger event configuration of line 15 + 15 + 1 + + + + TR16 + Rising trigger event configuration of line 16 + 16 + 1 + + + + TR17 + Rising trigger event configuration of line 17 + 17 + 1 + + + + TR18 + Rising trigger event configuration of line 18 + 18 + 1 + + + + TR19 + Rising trigger event configuration of line 19 + 19 + 1 + + + + TR20 + Rising trigger event configuration of line 20 + 20 + 1 + + + + TR21 + Rising trigger event configuration of line 21 + 21 + 1 + + + + TR22 + Rising trigger event configuration of line 22 + 22 + 1 + + + + + + FTSR + FTSR + Falling Trigger selection register (EXTI_FTSR) + 0xC + 0x20 + read-write + 0x00000000 + + + TR0 + Falling trigger event configuration of line 0 + 0 + 1 + + TR0 + read-write + + Disabled + Falling edge trigger is disabled + 0 + + + Enabled + Falling edge trigger is enabled + 1 + + + + + TR1 + Falling trigger event configuration of line 1 + 1 + 1 + + + + TR2 + Falling trigger event configuration of line 2 + 2 + 1 + + + + TR3 + Falling trigger event configuration of line 3 + 3 + 1 + + + + TR4 + Falling trigger event configuration of line 4 + 4 + 1 + + + + TR5 + Falling trigger event configuration of line 5 + 5 + 1 + + + + TR6 + Falling trigger event configuration of line 6 + 6 + 1 + + + + TR7 + Falling trigger event configuration of line 7 + 7 + 1 + + + + TR8 + Falling trigger event configuration of line 8 + 8 + 1 + + + + TR9 + Falling trigger event configuration of line 9 + 9 + 1 + + + + TR10 + Falling trigger event configuration of line 10 + 10 + 1 + + + + TR11 + Falling trigger event configuration of line 11 + 11 + 1 + + + + TR12 + Falling trigger event configuration of line 12 + 12 + 1 + + + + TR13 + Falling trigger event configuration of line 13 + 13 + 1 + + + + TR14 + Falling trigger event configuration of line 14 + 14 + 1 + + + + TR15 + Falling trigger event configuration of line 15 + 15 + 1 + + + + TR16 + Falling trigger event configuration of line 16 + 16 + 1 + + + + TR17 + Falling trigger event configuration of line 17 + 17 + 1 + + + + TR18 + Falling trigger event configuration of line 18 + 18 + 1 + + + + TR19 + Falling trigger event configuration of line 19 + 19 + 1 + + + + TR20 + Falling trigger event configuration of line 20 + 20 + 1 + + + + TR21 + Falling trigger event configuration of line 21 + 21 + 1 + + + + TR22 + Falling trigger event configuration of line 22 + 22 + 1 + + + + + + SWIER + SWIER + Software interrupt event register (EXTI_SWIER) + 0x10 + 0x20 + read-write + 0x00000000 + + + SWIER0 + Software Interrupt on line 0 + 0 + 1 + + SWIER0W + write + + Pend + Generates an interrupt request + 1 + + + + + SWIER1 + Software Interrupt on line 1 + 1 + 1 + + + + SWIER2 + Software Interrupt on line 2 + 2 + 1 + + + + SWIER3 + Software Interrupt on line 3 + 3 + 1 + + + + SWIER4 + Software Interrupt on line 4 + 4 + 1 + + + + SWIER5 + Software Interrupt on line 5 + 5 + 1 + + + + SWIER6 + Software Interrupt on line 6 + 6 + 1 + + + + SWIER7 + Software Interrupt on line 7 + 7 + 1 + + + + SWIER8 + Software Interrupt on line 8 + 8 + 1 + + + + SWIER9 + Software Interrupt on line 9 + 9 + 1 + + + + SWIER10 + Software Interrupt on line 10 + 10 + 1 + + + + SWIER11 + Software Interrupt on line 11 + 11 + 1 + + + + SWIER12 + Software Interrupt on line 12 + 12 + 1 + + + + SWIER13 + Software Interrupt on line 13 + 13 + 1 + + + + SWIER14 + Software Interrupt on line 14 + 14 + 1 + + + + SWIER15 + Software Interrupt on line 15 + 15 + 1 + + + + SWIER16 + Software Interrupt on line 16 + 16 + 1 + + + + SWIER17 + Software Interrupt on line 17 + 17 + 1 + + + + SWIER18 + Software Interrupt on line 18 + 18 + 1 + + + + SWIER19 + Software Interrupt on line 19 + 19 + 1 + + + + SWIER20 + Software Interrupt on line 20 + 20 + 1 + + + + SWIER21 + Software Interrupt on line 21 + 21 + 1 + + + + SWIER22 + Software Interrupt on line 22 + 22 + 1 + + + + + + PR + PR + Pending register (EXTI_PR) + 0x14 + 0x20 + read-write + 0x00000000 + + + PR0 + Pending bit 0 + 0 + 1 + oneToClear + + PR0R + read + + NotPending + No trigger request occurred + 0 + + + Pending + Selected trigger request occurred + 1 + + + + PR0W + write + + Clear + Clears pending bit + 1 + + + + + PR1 + Pending bit 1 + 1 + 1 + oneToClear + + read + + + write + + + + PR2 + Pending bit 2 + 2 + 1 + oneToClear + + read + + + write + + + + PR3 + Pending bit 3 + 3 + 1 + oneToClear + + read + + + write + + + + PR4 + Pending bit 4 + 4 + 1 + oneToClear + + read + + + write + + + + PR5 + Pending bit 5 + 5 + 1 + oneToClear + + read + + + write + + + + PR6 + Pending bit 6 + 6 + 1 + oneToClear + + read + + + write + + + + PR7 + Pending bit 7 + 7 + 1 + oneToClear + + read + + + write + + + + PR8 + Pending bit 8 + 8 + 1 + oneToClear + + read + + + write + + + + PR9 + Pending bit 9 + 9 + 1 + oneToClear + + read + + + write + + + + PR10 + Pending bit 10 + 10 + 1 + oneToClear + + read + + + write + + + + PR11 + Pending bit 11 + 11 + 1 + oneToClear + + read + + + write + + + + PR12 + Pending bit 12 + 12 + 1 + oneToClear + + read + + + write + + + + PR13 + Pending bit 13 + 13 + 1 + oneToClear + + read + + + write + + + + PR14 + Pending bit 14 + 14 + 1 + oneToClear + + read + + + write + + + + PR15 + Pending bit 15 + 15 + 1 + oneToClear + + read + + + write + + + + PR16 + Pending bit 16 + 16 + 1 + oneToClear + + read + + + write + + + + PR17 + Pending bit 17 + 17 + 1 + oneToClear + + read + + + write + + + + PR18 + Pending bit 18 + 18 + 1 + oneToClear + + read + + + write + + + + PR19 + Pending bit 19 + 19 + 1 + oneToClear + + read + + + write + + + + PR20 + Pending bit 20 + 20 + 1 + oneToClear + + read + + + write + + + + PR21 + Pending bit 21 + 21 + 1 + oneToClear + + read + + + write + + + + PR22 + Pending bit 22 + 22 + 1 + oneToClear + + read + + + write + + + + + + + + LTDC + LCD-TFT Controller + LTDC + 0x40016800 + + 0x0 + 0x400 + registers + + + LTDC + LTDC global interrupt + 88 + + + LTDC_ER + LTDC global error interrupt + 89 + + + + SSCR + SSCR + Synchronization Size Configuration Register + 0x8 + 0x20 + read-write + 0x00000000 + + + HSW + Horizontal Synchronization Width (in units of pixel clock period) + 16 + 12 + + + 0 + 4095 + + + + + VSH + Vertical Synchronization Height (in units of horizontal scan line) + 0 + 11 + + + 0 + 2047 + + + + + + + BPCR + BPCR + Back Porch Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + AHBP + Accumulated Horizontal back porch (in units of pixel clock period) + 16 + 12 + + + 0 + 4095 + + + + + AVBP + Accumulated Vertical back porch (in units of horizontal scan line) + 0 + 11 + + + 0 + 2047 + + + + + + + AWCR + AWCR + Active Width Configuration Register + 0x10 + 0x20 + read-write + 0x00000000 + + + AAW + Accumulated Active Width (in units of pixel clock period) + 16 + 12 + + + 0 + 4095 + + + + + AAH + Accumulated Active Height (in units of horizontal scan line) + 0 + 11 + + + 0 + 2047 + + + + + + + TWCR + TWCR + Total Width Configuration Register + 0x14 + 0x20 + read-write + 0x00000000 + + + TOTALW + Total Width (in units of pixel clock period) + 16 + 12 + + + 0 + 4095 + + + + + TOTALH + Total Height (in units of horizontal scan line) + 0 + 11 + + + 0 + 2047 + + + + + + + GCR + GCR + Global Control Register + 0x18 + 0x20 + 0x00002220 + + + HSPOL + Horizontal Synchronization Polarity + 31 + 1 + read-write + + HSPOL + read-write + + ActiveLow + Horizontal synchronization polarity is active low + 0 + + + ActiveHigh + Horizontal synchronization polarity is active high + 1 + + + + + VSPOL + Vertical Synchronization Polarity + 30 + 1 + read-write + + VSPOL + read-write + + ActiveLow + Vertical synchronization polarity is active low + 0 + + + ActiveHigh + Vertical synchronization polarity is active high + 1 + + + + + DEPOL + Data Enable Polarity + 29 + 1 + read-write + + DEPOL + read-write + + ActiveLow + Data enable polarity is active low + 0 + + + ActiveHigh + Data enable polarity is active high + 1 + + + + + PCPOL + Pixel Clock Polarity + 28 + 1 + read-write + + PCPOL + read-write + + RisingEdge + Pixel clock on rising edge + 0 + + + FallingEdge + Pixel clock on falling edge + 1 + + + + + DEN + Dither Enable + 16 + 1 + read-write + + DEN + read-write + + Disabled + Dither disabled + 0 + + + Enabled + Dither enabled + 1 + + + + + DRW + Dither Red Width + 12 + 3 + read-only + + + DGW + Dither Green Width + 8 + 3 + read-only + + + DBW + Dither Blue Width + 4 + 3 + read-only + + + LTDCEN + LCD-TFT controller enable bit + 0 + 1 + read-write + + LTDCEN + read-write + + Disabled + LCD-TFT controller disabled + 0 + + + Enabled + LCD-TFT controller enabled + 1 + + + + + + + SRCR + SRCR + Shadow Reload Configuration Register + 0x24 + 0x20 + read-write + 0x00000000 + + + VBR + Vertical Blanking Reload + 1 + 1 + + VBR + read-write + + NoEffect + This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) + 0 + + + Reload + The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). + 1 + + + + + IMR + Immediate Reload + 0 + 1 + + IMR + read-write + + NoEffect + This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) + 0 + + + Reload + The shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload + 1 + + + + + + + BCCR + BCCR + Background Color Configuration Register + 0x2C + 0x20 + read-write + 0x00000000 + + + BCBLUE + Background color blue value + 0 + 8 + + + 0 + 255 + + + + + BCGREEN + Background color green value + 8 + 8 + + + 0 + 255 + + + + + BCRED + Background color red value + 16 + 8 + + + 0 + 255 + + + + + + + IER + IER + Interrupt Enable Register + 0x34 + 0x20 + read-write + 0x00000000 + + + RRIE + Register Reload interrupt enable + 3 + 1 + + RRIE + read-write + + Disabled + Register reload interrupt disabled + 0 + + + Enabled + Register reload interrupt enabled + 1 + + + + + TERRIE + Transfer Error Interrupt Enable + 2 + 1 + + TERRIE + read-write + + Disabled + Transfer error interrupt disabled + 0 + + + Enabled + Transfer error interrupt enabled + 1 + + + + + FUIE + FIFO Underrun Interrupt Enable + 1 + 1 + + FUIE + read-write + + Disabled + FIFO underrun interrupt disabled + 0 + + + Enabled + FIFO underrun interrupt enabled + 1 + + + + + LIE + Line Interrupt Enable + 0 + 1 + + LIE + read-write + + Disabled + Line interrupt disabled + 0 + + + Enabled + Line interrupt enabled + 1 + + + + + + + ISR + ISR + Interrupt Status Register + 0x38 + 0x20 + read-only + 0x00000000 + + + RRIF + Register Reload Interrupt Flag + 3 + 1 + + RRIF + read + + NoReload + No register reload + 0 + + + Reload + Register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) + 1 + + + + + TERRIF + Transfer Error interrupt flag + 2 + 1 + + TERRIF + read + + NoError + No transfer error + 0 + + + Error + Transfer error interrupt generated when a bus error occurs + 1 + + + + + FUIF + FIFO Underrun Interrupt flag + 1 + 1 + + FUIF + read + + NoUnderrun + No FIFO underrun + 0 + + + Underrun + FIFO underrun interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO + 1 + + + + + LIF + Line Interrupt flag + 0 + 1 + + LIF + read + + NotReached + Programmed line not reached + 0 + + + Reached + Line interrupt generated when a programmed line is reached + 1 + + + + + + + ICR + ICR + Interrupt Clear Register + 0x3C + 0x20 + write-only + 0x00000000 + + + CRRIF + Clears Register Reload Interrupt Flag + 3 + 1 + oneToClear + + CRRIFW + write + + Clear + Clears the RRIF flag in the ISR register + 1 + + + + + CTERRIF + Clears the Transfer Error Interrupt Flag + 2 + 1 + oneToClear + + CTERRIFW + write + + Clear + Clears the TERRIF flag in the ISR register + 1 + + + + + CFUIF + Clears the FIFO Underrun Interrupt flag + 1 + 1 + oneToClear + + CFUIFW + write + + Clear + Clears the FUIF flag in the ISR register + 1 + + + + + CLIF + Clears the Line Interrupt Flag + 0 + 1 + oneToClear + + CLIFW + write + + Clear + Clears the LIF flag in the ISR register + 1 + + + + + + + LIPCR + LIPCR + Line Interrupt Position Configuration Register + 0x40 + 0x20 + read-write + 0x00000000 + + + LIPOS + Line Interrupt Position + 0 + 11 + + + 0 + 2047 + + + + + + + CPSR + CPSR + Current Position Status Register + 0x44 + 0x20 + read-only + 0x00000000 + + + CXPOS + Current X Position + 16 + 16 + + + CYPOS + Current Y Position + 0 + 16 + + + + + CDSR + CDSR + Current Display Status Register + 0x48 + 0x20 + read-only + 0x0000000F + + + HSYNCS + Horizontal Synchronization display Status + 3 + 1 + + HSYNCS + read + + NotActive + Currently not in HSYNC phase + 0 + + + Active + Currently in HSYNC phase + 1 + + + + + VSYNCS + Vertical Synchronization display Status + 2 + 1 + + VSYNCS + read + + NotActive + Currently not in VSYNC phase + 0 + + + Active + Currently in VSYNC phase + 1 + + + + + HDES + Horizontal Data Enable display Status + 1 + 1 + + HDES + read + + NotActive + Currently not in horizontal Data Enable phase + 0 + + + Active + Currently in horizontal Data Enable phase + 1 + + + + + VDES + Vertical Data Enable display Status + 0 + 1 + + VDES + read + + NotActive + Currently not in vertical Data Enable phase + 0 + + + Active + Currently in vertical Data Enable phase + 1 + + + + + + + 2 + 0x80 + 1-2 + LAYER%s + Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR + 0x84 + + CR + L1CR + Layerx Control Register + 0x0 + 0x20 + read-write + 0x00000000 + + + CLUTEN + Color Look-Up Table Enable + 4 + 1 + + CLUTEN + read-write + + Disabled + Color look-up table disabled + 0 + + + Enabled + Color look-up table enabled + 1 + + + + + COLKEN + Color Keying Enable + 1 + 1 + + COLKEN + read-write + + Disabled + Color keying disabled + 0 + + + Enabled + Color keying enabled + 1 + + + + + LEN + Layer Enable + 0 + 1 + + LEN + read-write + + Disabled + Layer disabled + 0 + + + Enabled + Layer enabled + 1 + + + + + + + WHPCR + L1WHPCR + Layerx Window Horizontal Position Configuration Register + 0x4 + 0x20 + read-write + 0x00000000 + + + WHSPPOS + Window Horizontal Stop Position + 16 + 12 + + + 0 + 4095 + + + + + WHSTPOS + Window Horizontal Start Position + 0 + 12 + + + 0 + 4095 + + + + + + + WVPCR + L1WVPCR + Layerx Window Vertical Position Configuration Register + 0x8 + 0x20 + read-write + 0x00000000 + + + WVSPPOS + Window Vertical Stop Position + 16 + 11 + + + 0 + 2047 + + + + + WVSTPOS + Window Vertical Start Position + 0 + 11 + + + 0 + 2047 + + + + + + + CKCR + L1CKCR + Layerx Color Keying Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + CKRED + Color Key Red value + 16 + 8 + + + 0 + 255 + + + + + CKGREEN + Color Key Green value + 8 + 8 + + + 0 + 255 + + + + + CKBLUE + Color Key Blue value + 0 + 8 + + + 0 + 255 + + + + + + + PFCR + L1PFCR + Layerx Pixel Format Configuration Register + 0x10 + 0x20 + read-write + 0x00000000 + + + PF + Pixel Format + 0 + 3 + + PF + read-write + + ARGB8888 + ARGB8888 + 0 + + + RGB888 + RGB888 + 1 + + + RGB565 + RGB565 + 2 + + + ARGB1555 + ARGB1555 + 3 + + + ARGB4444 + ARGB4444 + 4 + + + L8 + L8 (8-bit luminance) + 5 + + + AL44 + AL44 (4-bit alpha, 4-bit luminance) + 6 + + + AL88 + AL88 (8-bit alpha, 8-bit luminance) + 7 + + + + + + + CACR + L1CACR + Layerx Constant Alpha Configuration Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CONSTA + Constant Alpha + 0 + 8 + + + 0 + 255 + + + + + + + DCCR + L1DCCR + Layerx Default Color Configuration Register + 0x18 + 0x20 + read-write + 0x00000000 + + + DCALPHA + Default Color Alpha + 24 + 8 + + + 0 + 255 + + + + + DCRED + Default Color Red + 16 + 8 + + + 0 + 255 + + + + + DCGREEN + Default Color Green + 8 + 8 + + + 0 + 255 + + + + + DCBLUE + Default Color Blue + 0 + 8 + + + 0 + 255 + + + + + + + BFCR + L1BFCR + Layerx Blending Factors Configuration Register + 0x1C + 0x20 + read-write + 0x00000607 + + + BF1 + Blending Factor 1 + 8 + 3 + + BF1 + read-write + + Constant + BF1 = constant alpha + 4 + + + Pixel + BF1 = pixel alpha * constant alpha + 6 + + + + + BF2 + Blending Factor 2 + 0 + 3 + + BF2 + read-write + + Constant + BF2 = 1 - constant alpha + 5 + + + Pixel + BF2 = 1 - pixel alpha * constant alpha + 7 + + + + + + + CFBAR + L1CFBAR + Layerx Color Frame Buffer Address Register + 0x28 + 0x20 + read-write + 0x00000000 + + + CFBADD + Color Frame Buffer Start Address + 0 + 32 + + + 0 + 4294967295 + + + + + + + CFBLR + L1CFBLR + Layerx Color Frame Buffer Length Register + 0x2C + 0x20 + read-write + 0x00000000 + + + CFBP + Color Frame Buffer Pitch in bytes + 16 + 13 + + + 0 + 8191 + + + + + CFBLL + Color Frame Buffer Line Length + 0 + 13 + + + 0 + 8191 + + + + + + + CFBLNR + L1CFBLNR + Layerx ColorFrame Buffer Line Number Register + 0x30 + 0x20 + read-write + 0x00000000 + + + CFBLNBR + Frame Buffer Line Number + 0 + 11 + + + 0 + 2047 + + + + + + + CLUTWR + L1CLUTWR + Layerx CLUT Write Register + 0x40 + 0x20 + write-only + 0x00000000 + + + CLUTADD + CLUT Address + 24 + 8 + + + 0 + 255 + + + + + RED + Red value + 16 + 8 + + + 0 + 255 + + + + + GREEN + Green value + 8 + 8 + + + 0 + 255 + + + + + BLUE + Blue value + 0 + 8 + + + 0 + 255 + + + + + + + + + + SAI1 + Serial audio interface + SAI + 0x40015800 + + 0x0 + 0x400 + registers + + + SAI1 + SAI1 global interrupt + 87 + + + SAI2 + SAI2 global interrupt + 91 + + + + 2 + 0x20 + A,B + CH%s + Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR + 0x4 + + CR1 + ACR1 + AConfiguration register 1 + 0x0 + 0x20 + read-write + 0x00000040 + + + MCKDIV + Master clock divider + 20 + 4 + + + NODIV + No divider + 19 + 1 + + NODIV + read-write + + MasterClock + MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value + 0 + + + NoDiv + MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. + 1 + + + + + DMAEN + DMA enable + 17 + 1 + + DMAEN + read-write + + Disabled + DMA disabled + 0 + + + Enabled + DMA enabled + 1 + + + + + SAIEN + Audio block A enable + 16 + 1 + + SAIEN + read-write + + Disabled + SAI audio block disabled + 0 + + + Enabled + SAI audio block enabled + 1 + + + + + OUTDRIV + Output drive + 13 + 1 + + OUTDRIV + read-write + + OnStart + Audio block output driven when SAIEN is set + 0 + + + Immediately + Audio block output driven immediately after the setting of this bit + 1 + + + + + MONO + Mono mode + 12 + 1 + + MONO + read-write + + Stereo + Stereo mode + 0 + + + Mono + Mono mode + 1 + + + + + SYNCEN + Synchronization enable + 10 + 2 + + SYNCEN + read-write + + Asynchronous + audio sub-block in asynchronous mode + 0 + + + Internal + audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode + 1 + + + External + audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode + 2 + + + + + CKSTR + Clock strobing edge + 9 + 1 + + CKSTR + read-write + + FallingEdge + Data strobing edge is falling edge of SCK + 0 + + + RisingEdge + Data strobing edge is rising edge of SCK + 1 + + + + + LSBFIRST + Least significant bit first + 8 + 1 + + LSBFIRST + read-write + + MsbFirst + Data are transferred with MSB first + 0 + + + LsbFirst + Data are transferred with LSB first + 1 + + + + + DS + Data size + 5 + 3 + + DS + read-write + + Bit8 + 8 bits + 2 + + + Bit10 + 10 bits + 3 + + + Bit16 + 16 bits + 4 + + + Bit20 + 20 bits + 5 + + + Bit24 + 24 bits + 6 + + + Bit32 + 32 bits + 7 + + + + + PRTCFG + Protocol configuration + 2 + 2 + + PRTCFG + read-write + + Free + Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol + 0 + + + Spdif + SPDIF protocol + 1 + + + Ac97 + AC’97 protocol + 2 + + + + + MODE + Audio block mode + 0 + 2 + + MODE + read-write + + MasterTx + Master transmitter + 0 + + + MasterRx + Master receiver + 1 + + + SlaveTx + Slave transmitter + 2 + + + SlaveRx + Slave receiver + 3 + + + + + + + CR2 + ACR2 + AConfiguration register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + COMP + Companding mode + 14 + 2 + read-write + + COMP + read-write + + NoCompanding + No companding algorithm + 0 + + + MuLaw + μ-Law algorithm + 2 + + + ALaw + A-Law algorithm + 3 + + + + + CPL + Complement bit + 13 + 1 + read-write + + CPL + read-write + + OnesComplement + 1’s complement representation + 0 + + + TwosComplement + 2’s complement representation + 1 + + + + + MUTECNT + Mute counter + 7 + 6 + read-write + + + MUTEVAL + Mute value + 6 + 1 + read-write + + MUTEVAL + read-write + + SendZero + Bit value 0 is sent during the mute mode + 0 + + + SendLast + Last values are sent during the mute mode + 1 + + + + + MUTE + Mute + 5 + 1 + read-write + + MUTE + read-write + + Disabled + No mute mode + 0 + + + Enabled + Mute mode enabled + 1 + + + + + TRIS + Tristate management on data line + 4 + 1 + read-write + + + FFLUSH + FIFO flush + 3 + 1 + + FFLUSH + read-write + + NoFlush + No FIFO flush + 0 + + + Flush + FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared + 1 + + + + + FTH + FIFO threshold + 0 + 3 + read-write + + FTH + read-write + + Empty + FIFO empty + 0 + + + Quarter1 + 1⁄4 FIFO + 1 + + + Quarter2 + 1⁄2 FIFO + 2 + + + Quarter3 + 3⁄4 FIFO + 3 + + + Full + FIFO full + 4 + + + + + + + FRCR + AFRCR + AFRCR + 0x8 + 0x20 + read-write + 0x00000007 + + + FSOFF + Frame synchronization offset + 18 + 1 + read-write + + FSOFF + read-write + + OnFirst + FS is asserted on the first bit of the slot 0 + 0 + + + BeforeFirst + FS is asserted one bit before the first bit of the slot 0 + 1 + + + + + FSPOL + Frame synchronization polarity + 17 + 1 + read-write + + FSPOL + read-write + + FallingEdge + FS is active low (falling edge) + 0 + + + RisingEdge + FS is active high (rising edge) + 1 + + + + + FSDEF + Frame synchronization definition + 16 + 1 + read-write + + + FSALL + Frame synchronization active level length + 8 + 7 + read-write + + + FRL + Frame length + 0 + 8 + read-write + + + + + SLOTR + ASLOTR + ASlot register + 0xC + 0x20 + read-write + 0x00000000 + + + SLOTEN + Slot enable + 16 + 16 + + SLOTEN + read-write + + Inactive + Inactive slot + 0 + + + Active + Active slot + 1 + + + + + NBSLOT + Number of slots in an audio frame + 8 + 4 + + + SLOTSZ + Slot size + 6 + 2 + + SLOTSZ + read-write + + DataSize + The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register) + 0 + + + Bit16 + 16-bit + 1 + + + Bit32 + 32-bit + 2 + + + + + FBOFF + First bit offset + 0 + 5 + + + + + IM + AIM + AInterrupt mask register2 + 0x10 + 0x20 + read-write + 0x00000000 + + + LFSDETIE + Late frame synchronization detection interrupt enable + 6 + 1 + + LFSDETIE + read-write + + Disabled + Interrupt is disabled + 0 + + + Enabled + Interrupt is enabled + 1 + + + + + AFSDETIE + Anticipated frame synchronization detection interrupt enable + 5 + 1 + + AFSDETIE + read-write + + Disabled + Interrupt is disabled + 0 + + + Enabled + Interrupt is enabled + 1 + + + + + CNRDYIE + Codec not ready interrupt enable + 4 + 1 + + CNRDYIE + read-write + + Disabled + Interrupt is disabled + 0 + + + Enabled + Interrupt is enabled + 1 + + + + + FREQIE + FIFO request interrupt enable + 3 + 1 + + FREQIE + read-write + + Disabled + Interrupt is disabled + 0 + + + Enabled + Interrupt is enabled + 1 + + + + + WCKCFGIE + Wrong clock configuration interrupt enable + 2 + 1 + + WCKCFGIE + read-write + + Disabled + Interrupt is disabled + 0 + + + Enabled + Interrupt is enabled + 1 + + + + + MUTEDETIE + Mute detection interrupt enable + 1 + 1 + + MUTEDETIE + read-write + + Disabled + Interrupt is disabled + 0 + + + Enabled + Interrupt is enabled + 1 + + + + + OVRUDRIE + Overrun/underrun interrupt enable + 0 + 1 + + OVRUDRIE + read-write + + Disabled + Interrupt is disabled + 0 + + + Enabled + Interrupt is enabled + 1 + + + + + + + SR + ASR + AStatus register + 0x14 + 0x20 + read-only + 0x00000008 + + + FLVL + FIFO level threshold + 16 + 3 + + FLVLR + read + + Empty + FIFO empty + 0 + + + Quarter1 + FIFO <= 1⁄4 but not empty + 1 + + + Quarter2 + 1⁄4 < FIFO <= 1⁄2 + 2 + + + Quarter3 + 1⁄2 < FIFO <= 3⁄4 + 3 + + + Quarter4 + 3⁄4 < FIFO but not full + 4 + + + Full + FIFO full + 5 + + + + + LFSDET + Late frame synchronization detection + 6 + 1 + + LFSDETR + read + + NoError + No error + 0 + + + NoSync + Frame synchronization signal is not present at the right time + 1 + + + + + AFSDET + Anticipated frame synchronization detection + 5 + 1 + + AFSDETR + read + + NoError + No error + 0 + + + EarlySync + Frame synchronization signal is detected earlier than expected + 1 + + + + + CNRDY + Codec not ready + 4 + 1 + + CNRDYR + read + + Ready + External AC’97 Codec is ready + 0 + + + NotReady + External AC’97 Codec is not ready + 1 + + + + + FREQ + FIFO request + 3 + 1 + + FREQR + read + + NoRequest + No FIFO request + 0 + + + Request + FIFO request to read or to write the SAI_xDR + 1 + + + + + WCKCFG + Wrong clock configuration flag. This bit is read only. + 2 + 1 + + WCKCFGR + read + + Correct + Clock configuration is correct + 0 + + + Wrong + Clock configuration does not respect the rule concerning the frame length specification + 1 + + + + + MUTEDET + Mute detection + 1 + 1 + + MUTEDETR + read + + NoMute + No MUTE detection on the SD input line + 0 + + + Mute + MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame + 1 + + + + + OVRUDR + Overrun / underrun + 0 + 1 + + OVRUDRR + read + + NoError + No overrun/underrun error + 0 + + + Overrun + Overrun/underrun error detection + 1 + + + + + + + CLRFR + ACLRFR + AClear flag register + 0x18 + 0x20 + write-only + 0x00000000 + + + CLFSDET + Clear late frame synchronization detection flag + 6 + 1 + + CLFSDETW + write + + Clear + Clears the LFSDET flag + 1 + + + + + CAFSDET + Clear anticipated frame synchronization detection flag. + 5 + 1 + + CAFSDETW + write + + Clear + Clears the AFSDET flag + 1 + + + + + CCNRDY + Clear codec not ready flag + 4 + 1 + + CCNRDYW + write + + Clear + Clears the CNRDY flag + 1 + + + + + CWCKCFG + Clear wrong clock configuration flag + 2 + 1 + + CWCKCFGW + write + + Clear + Clears the WCKCFG flag + 1 + + + + + CMUTEDET + Mute detection flag + 1 + 1 + + CMUTEDETW + write + + Clear + Clears the MUTEDET flag + 1 + + + + + COVRUDR + Clear overrun / underrun + 0 + 1 + + COVRUDRW + write + + Clear + Clears the OVRUDR flag + 1 + + + + + + + DR + ADR + AData register + 0x1C + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + + GCR + GCR + Global configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + SYNCIN + Synchronization inputs + 0 + 2 + + + SYNCOUT + Synchronization outputs + 4 + 2 + + + + + + + SAI2 + 0x40015C00 + + SAI2 + SAI2 global interrupt + 91 + + + + DMA2D + DMA2D controller + DMA2D + 0x4002B000 + + 0x0 + 0xC00 + registers + + + DMA2D + DMA2D global interrupt + 90 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + MODE + DMA2D mode + 16 + 2 + + MODE + read-write + + MemoryToMemory + Memory-to-memory (FG fetch only) + 0 + + + MemoryToMemoryPFC + Memory-to-memory with PFC (FG fetch only with FG PFC active) + 1 + + + MemoryToMemoryPFCBlending + Memory-to-memory with blending (FG and BG fetch with PFC and blending) + 2 + + + RegisterToMemory + Register-to-memory + 3 + + + + + CEIE + Configuration Error Interrupt Enable + 13 + 1 + + CEIE + read-write + + Disabled + CE interrupt disabled + 0 + + + Enabled + CE interrupt enabled + 1 + + + + + CTCIE + CLUT transfer complete interrupt enable + 12 + 1 + + CTCIE + read-write + + Disabled + CTC interrupt disabled + 0 + + + Enabled + CTC interrupt enabled + 1 + + + + + CAEIE + CLUT access error interrupt enable + 11 + 1 + + CAEIE + read-write + + Disabled + CAE interrupt disabled + 0 + + + Enabled + CAE interrupt enabled + 1 + + + + + TWIE + Transfer watermark interrupt enable + 10 + 1 + + TWIE + read-write + + Disabled + TW interrupt disabled + 0 + + + Enabled + TW interrupt enabled + 1 + + + + + TCIE + Transfer complete interrupt enable + 9 + 1 + + TCIE + read-write + + Disabled + TC interrupt disabled + 0 + + + Enabled + TC interrupt enabled + 1 + + + + + TEIE + Transfer error interrupt enable + 8 + 1 + + TEIE + read-write + + Disabled + TE interrupt disabled + 0 + + + Enabled + TE interrupt enabled + 1 + + + + + ABORT + Abort + 2 + 1 + + ABORT + read-write + + AbortRequest + Transfer abort requested + 1 + + + + + SUSP + Suspend + 1 + 1 + + SUSP + read-write + + NotSuspended + Transfer not suspended + 0 + + + Suspended + Transfer suspended + 1 + + + + + START + Start + 0 + 1 + + START + read-write + + Start + Launch the DMA2D + 1 + + + + + + + ISR + ISR + Interrupt Status Register + 0x4 + 0x20 + read-only + 0x00000000 + + + CEIF + Configuration error interrupt flag + 5 + 1 + + + CTCIF + CLUT transfer complete interrupt flag + 4 + 1 + + + CAEIF + CLUT access error interrupt flag + 3 + 1 + + + TWIF + Transfer watermark interrupt flag + 2 + 1 + + + TCIF + Transfer complete interrupt flag + 1 + 1 + + + TEIF + Transfer error interrupt flag + 0 + 1 + + + + + IFCR + IFCR + interrupt flag clear register + 0x8 + 0x20 + read-write + 0x00000000 + + + CCEIF + Clear configuration error interrupt flag + 5 + 1 + + CCEIF + read-write + + Clear + Clear the CEIF flag in the ISR register + 1 + + + + + CCTCIF + Clear CLUT transfer complete interrupt flag + 4 + 1 + + CCTCIF + read-write + + Clear + Clear the CTCIF flag in the ISR register + 1 + + + + + CAECIF + Clear CLUT access error interrupt flag + 3 + 1 + + CAECIF + read-write + + Clear + Clear the CAEIF flag in the ISR register + 1 + + + + + CTWIF + Clear transfer watermark interrupt flag + 2 + 1 + + CTWIF + read-write + + Clear + Clear the TWIF flag in the ISR register + 1 + + + + + CTCIF + Clear transfer complete interrupt flag + 1 + 1 + + CTCIF + read-write + + Clear + Clear the TCIF flag in the ISR register + 1 + + + + + CTEIF + Clear Transfer error interrupt flag + 0 + 1 + + CTEIF + read-write + + Clear + Clear the TEIF flag in the ISR register + 1 + + + + + + + FGMAR + FGMAR + foreground memory address register + 0xC + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + FGOR + FGOR + foreground offset register + 0x10 + 0x20 + read-write + 0x00000000 + + + LO + Line offset + 0 + 14 + + + 0 + 16383 + + + + + + + BGMAR + BGMAR + background memory address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + BGOR + BGOR + background offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + LO + Line offset + 0 + 14 + + + 0 + 16383 + + + + + + + FGPFCCR + FGPFCCR + foreground PFC control register + 0x1C + 0x20 + read-write + 0x00000000 + + + ALPHA + Alpha value + 24 + 8 + + + 0 + 255 + + + + + AM + Alpha mode + 16 + 2 + + AM + read-write + + NoModify + No modification of alpha channel + 0 + + + Replace + Replace with value in ALPHA[7:0] + 1 + + + Multiply + Multiply with value in ALPHA[7:0] + 2 + + + + + CS + CLUT size + 8 + 8 + + + 0 + 255 + + + + + START + Start + 5 + 1 + + START + read-write + + Start + Start the automatic loading of the CLUT + 1 + + + + + CCM + CLUT color mode + 4 + 1 + + CCM + read-write + + ARGB8888 + CLUT color format ARGB8888 + 0 + + + RGB888 + CLUT color format RGB888 + 1 + + + + + CM + Color mode + 0 + 4 + + CM + read-write + + ARGB8888 + Color mode ARGB8888 + 0 + + + RGB888 + Color mode RGB888 + 1 + + + RGB565 + Color mode RGB565 + 2 + + + ARGB1555 + Color mode ARGB1555 + 3 + + + ARGB4444 + Color mode ARGB4444 + 4 + + + L8 + Color mode L8 + 5 + + + AL44 + Color mode AL44 + 6 + + + AL88 + Color mode AL88 + 7 + + + L4 + Color mode L4 + 8 + + + A8 + Color mode A8 + 9 + + + A4 + Color mode A4 + 10 + + + + + + + FGCOLR + FGCOLR + foreground color register + 0x20 + 0x20 + read-write + 0x00000000 + + + RED + Red Value + 16 + 8 + + + 0 + 255 + + + + + GREEN + Green Value + 8 + 8 + + + 0 + 255 + + + + + BLUE + Blue Value + 0 + 8 + + + 0 + 255 + + + + + + + BGPFCCR + BGPFCCR + background PFC control register + 0x24 + 0x20 + read-write + 0x00000000 + + + ALPHA + Alpha value + 24 + 8 + + + 0 + 255 + + + + + AM + Alpha mode + 16 + 2 + + AM + read-write + + NoModify + No modification of alpha channel + 0 + + + Replace + Replace with value in ALPHA[7:0] + 1 + + + Multiply + Multiply with value in ALPHA[7:0] + 2 + + + + + CS + CLUT size + 8 + 8 + + + 0 + 255 + + + + + START + Start + 5 + 1 + + START + read-write + + Start + Start the automatic loading of the CLUT + 1 + + + + + CCM + CLUT Color mode + 4 + 1 + + CCM + read-write + + ARGB8888 + CLUT color format ARGB8888 + 0 + + + RGB888 + CLUT color format RGB888 + 1 + + + + + CM + Color mode + 0 + 4 + + CM + read-write + + ARGB8888 + Color mode ARGB8888 + 0 + + + RGB888 + Color mode RGB888 + 1 + + + RGB565 + Color mode RGB565 + 2 + + + ARGB1555 + Color mode ARGB1555 + 3 + + + ARGB4444 + Color mode ARGB4444 + 4 + + + L8 + Color mode L8 + 5 + + + AL44 + Color mode AL44 + 6 + + + AL88 + Color mode AL88 + 7 + + + L4 + Color mode L4 + 8 + + + A8 + Color mode A8 + 9 + + + A4 + Color mode A4 + 10 + + + + + + + BGCOLR + BGCOLR + background color register + 0x28 + 0x20 + read-write + 0x00000000 + + + RED + Red Value + 16 + 8 + + + 0 + 255 + + + + + GREEN + Green Value + 8 + 8 + + + 0 + 255 + + + + + BLUE + Blue Value + 0 + 8 + + + 0 + 255 + + + + + + + FGCMAR + FGCMAR + foreground CLUT memory address register + 0x2C + 0x20 + read-write + 0x00000000 + + + MA + Memory Address + 0 + 32 + + + + + BGCMAR + BGCMAR + background CLUT memory address register + 0x30 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + OPFCCR + OPFCCR + output PFC control register + 0x34 + 0x20 + read-write + 0x00000000 + + + CM + Color mode + 0 + 3 + + CM + read-write + + ARGB8888 + ARGB8888 + 0 + + + RGB888 + RGB888 + 1 + + + RGB565 + RGB565 + 2 + + + ARGB1555 + ARGB1555 + 3 + + + ARGB4444 + ARGB4444 + 4 + + + + + + + OCOLR + OCOLR + output color register + 0x38 + 0x20 + read-write + 0x00000000 + + + APLHA + Alpha Channel Value + 24 + 8 + + + RED + Red Value + 16 + 8 + + + GREEN + Green Value + 8 + 8 + + + BLUE + Blue Value + 0 + 8 + + + + + OMAR + OMAR + output memory address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory Address + 0 + 32 + + + + + OOR + OOR + output offset register + 0x40 + 0x20 + read-write + 0x00000000 + + + LO + Line Offset + 0 + 14 + + + 0 + 16383 + + + + + + + NLR + NLR + number of line register + 0x44 + 0x20 + read-write + 0x00000000 + + + PL + Pixel per lines + 16 + 14 + + + 0 + 16383 + + + + + NL + Number of lines + 0 + 16 + + + 0 + 65535 + + + + + + + LWR + LWR + line watermark register + 0x48 + 0x20 + read-write + 0x00000000 + + + LW + Line watermark + 0 + 16 + + + + + AMTCR + AMTCR + AHB master timer configuration register + 0x4C + 0x20 + read-write + 0x00000000 + + + DT + Dead Time + 8 + 8 + + + 0 + 255 + + + + + EN + Enable + 0 + 1 + + EN + read-write + + Disabled + Disabled AHB/AXI dead-time functionality + 0 + + + Enabled + Enabled AHB/AXI dead-time functionality + 1 + + + + + + + FGCLUT + FGCLUT + FGCLUT + 0x400 + 0x20 + read-write + 0x00000000 + + + APLHA + APLHA + 24 + 8 + + + RED + RED + 16 + 8 + + + GREEN + GREEN + 8 + 8 + + + BLUE + BLUE + 0 + 8 + + + + + BGCLUT + BGCLUT + BGCLUT + 0x800 + 0x20 + read-write + 0x00000000 + + + APLHA + APLHA + 24 + 8 + + + RED + RED + 16 + 8 + + + GREEN + GREEN + 8 + 8 + + + BLUE + BLUE + 0 + 8 + + + + + + + QUADSPI + QuadSPI interface + QUADSPI + 0xA0001000 + + 0x0 + 0x1000 + registers + + + QuadSPI + QuadSPI global interrupt + 92 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + PRESCALER + Clock prescaler + 24 + 8 + + + PMM + Polling match mode + 23 + 1 + + + APMS + Automatic poll mode stop + 22 + 1 + + + TOIE + TimeOut interrupt enable + 20 + 1 + + + SMIE + Status match interrupt enable + 19 + 1 + + + FTIE + FIFO threshold interrupt enable + 18 + 1 + + + TCIE + Transfer complete interrupt enable + 17 + 1 + + + TEIE + Transfer error interrupt enable + 16 + 1 + + + FTHRES + IFO threshold level + 8 + 5 + + + FSEL + FLASH memory selection + 7 + 1 + + + DFM + Dual-flash mode + 6 + 1 + + + SSHIFT + Sample shift + 4 + 1 + + + TCEN + Timeout counter enable + 3 + 1 + + + DMAEN + DMA enable + 2 + 1 + + + ABORT + Abort request + 1 + 1 + + + EN + Enable + 0 + 1 + + + + + DCR + DCR + device configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + FSIZE + FLASH memory size + 16 + 5 + + + CSHT + Chip select high time + 8 + 3 + + + CKMODE + Mode 0 / mode 3 + 0 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + read-only + 0x00000000 + + + FLEVEL + FIFO level + 8 + 7 + + + BUSY + Busy + 5 + 1 + + + TOF + Timeout flag + 4 + 1 + + + SMF + Status match flag + 3 + 1 + + + FTF + FIFO threshold flag + 2 + 1 + + + TCF + Transfer complete flag + 1 + 1 + + + TEF + Transfer error flag + 0 + 1 + + + + + FCR + FCR + flag clear register + 0xC + 0x20 + read-write + 0x00000000 + + + CTOF + Clear timeout flag + 4 + 1 + + + CSMF + Clear status match flag + 3 + 1 + + + CTCF + Clear transfer complete flag + 1 + 1 + + + CTEF + Clear transfer error flag + 0 + 1 + + + + + DLR + DLR + data length register + 0x10 + 0x20 + read-write + 0x00000000 + + + DL + Data length + 0 + 32 + + + + + CCR + CCR + communication configuration register + 0x14 + 0x20 + read-write + 0x00000000 + + + DDRM + Double data rate mode + 31 + 1 + + + DHHC + DDR hold half cycle + 30 + 1 + + + SIOO + Send instruction only once mode + 28 + 1 + + + FMODE + Functional mode + 26 + 2 + + + DMODE + Data mode + 24 + 2 + + + DCYC + Number of dummy cycles + 18 + 5 + + + ABSIZE + Alternate bytes size + 16 + 2 + + + ABMODE + Alternate bytes mode + 14 + 2 + + + ADSIZE + Address size + 12 + 2 + + + ADMODE + Address mode + 10 + 2 + + + IMODE + Instruction mode + 8 + 2 + + + INSTRUCTION + Instruction + 0 + 8 + + + + + AR + AR + address register + 0x18 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Address + 0 + 32 + + + + + ABR + ABR + ABR + 0x1C + 0x20 + read-write + 0x00000000 + + + ALTERNATE + ALTERNATE + 0 + 32 + + + + + DR + DR + data register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + PSMKR + PSMKR + polling status mask register + 0x24 + 0x20 + read-write + 0x00000000 + + + MASK + Status mask + 0 + 32 + + + + + PSMAR + PSMAR + polling status match register + 0x28 + 0x20 + read-write + 0x00000000 + + + MATCH + Status match + 0 + 32 + + + + + PIR + PIR + polling interval register + 0x2C + 0x20 + read-write + 0x00000000 + + + INTERVAL + Polling interval + 0 + 16 + + + + + LPTR + LPTR + low-power timeout register + 0x30 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Timeout period + 0 + 16 + + + + + + + CEC + HDMI-CEC controller + CEC + 0x40006C00 + + 0x0 + 0x400 + registers + + + HDMI_CEC + HDMI-CEC global interrupt + 94 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + TXEOM + Tx End Of Message + 2 + 1 + + + TXSOM + Tx start of message + 1 + 1 + + + CECEN + CEC Enable + 0 + 1 + + + + + CFGR + CFGR + configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + SFT + Signal Free Time + 0 + 3 + + + RXTOL + Rx-Tolerance + 3 + 1 + + + BRESTP + Rx-stop on bit rising error + 4 + 1 + + + BREGEN + Generate error-bit on bit rising error + 5 + 1 + + + LBPEGEN + Generate Error-Bit on Long Bit Period Error + 6 + 1 + + + BRDNOGEN + Avoid Error-Bit Generation in Broadcast + 7 + 1 + + + SFTOP + SFT Option Bit + 8 + 1 + + + OAR + Own addresses configuration + 16 + 15 + + + LSTN + Listen mode + 31 + 1 + + + + + TXDR + TXDR + Tx data register + 0x8 + 0x20 + write-only + 0x00000000 + + + TXD + Tx Data register + 0 + 8 + + + + + RXDR + RXDR + Rx Data Register + 0xC + 0x20 + read-only + 0x00000000 + + + RXDR + CEC Rx Data Register + 0 + 8 + + + + + ISR + ISR + Interrupt and Status Register + 0x10 + 0x20 + read-write + 0x00000000 + + + TXACKE + Tx-Missing acknowledge error + 12 + 1 + + + TXERR + Tx-Error + 11 + 1 + + + TXUDR + Tx-Buffer Underrun + 10 + 1 + + + TXEND + End of Transmission + 9 + 1 + + + TXBR + Tx-Byte Request + 8 + 1 + + + ARBLST + Arbitration Lost + 7 + 1 + + + RXACKE + Rx-Missing Acknowledge + 6 + 1 + + + LBPE + Rx-Long Bit Period Error + 5 + 1 + + + SBPE + Rx-Short Bit period error + 4 + 1 + + + BRE + Rx-Bit rising error + 3 + 1 + + + RXOVR + Rx-Overrun + 2 + 1 + + + RXEND + End Of Reception + 1 + 1 + + + RXBR + Rx-Byte Received + 0 + 1 + + + + + IER + IER + interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + TXACKIE + Tx-Missing Acknowledge Error Interrupt Enable + 12 + 1 + + + TXERRIE + Tx-Error Interrupt Enable + 11 + 1 + + + TXUDRIE + Tx-Underrun interrupt enable + 10 + 1 + + + TXENDIE + Tx-End of message interrupt enable + 9 + 1 + + + TXBRIE + Tx-Byte Request Interrupt Enable + 8 + 1 + + + ARBLSTIE + Arbitration Lost Interrupt Enable + 7 + 1 + + + RXACKIE + Rx-Missing Acknowledge Error Interrupt Enable + 6 + 1 + + + LBPEIE + Long Bit Period Error Interrupt Enable + 5 + 1 + + + SBPEIE + Short Bit Period Error Interrupt Enable + 4 + 1 + + + BREIE + Bit Rising Error Interrupt Enable + 3 + 1 + + + RXOVRIE + Rx-Buffer Overrun Interrupt Enable + 2 + 1 + + + RXENDIE + End Of Reception Interrupt Enable + 1 + 1 + + + RXBRIE + Rx-Byte Received Interrupt Enable + 0 + 1 + + + + + + + SPDIFRX + Receiver Interface + SPDIF_RX + 0x40004000 + + 0x0 + 0x400 + registers + + + SPDIFRX + SPDIFRX global interrupt + 97 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x00000000 + + + SPDIFEN + Peripheral Block Enable + 0 + 2 + + + RXDMAEN + Receiver DMA ENable for data flow + 2 + 1 + + + RXSTEO + STerEO Mode + 3 + 1 + + + DRFMT + RX Data format + 4 + 2 + + + PMSK + Mask Parity error bit + 6 + 1 + + + VMSK + Mask of Validity bit + 7 + 1 + + + CUMSK + Mask of channel status and user bits + 8 + 1 + + + PTMSK + Mask of Preamble Type bits + 9 + 1 + + + CBDMAEN + Control Buffer DMA ENable for control flow + 10 + 1 + + + CHSEL + Channel Selection + 11 + 1 + + + NBTR + Maximum allowed re-tries during synchronization phase + 12 + 2 + + + WFA + Wait For Activity + 14 + 1 + + + INSEL + input selection + 16 + 3 + + + + + IMR + IMR + Interrupt mask register + 0x4 + 0x20 + read-write + 0x00000000 + + + RXNEIE + RXNE interrupt enable + 0 + 1 + + + CSRNEIE + Control Buffer Ready Interrupt Enable + 1 + 1 + + + PERRIE + Parity error interrupt enable + 2 + 1 + + + OVRIE + Overrun error Interrupt Enable + 3 + 1 + + + SBLKIE + Synchronization Block Detected Interrupt Enable + 4 + 1 + + + SYNCDIE + Synchronization Done + 5 + 1 + + + IFEIE + Serial Interface Error Interrupt Enable + 6 + 1 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-only + 0x00000000 + + + RXNE + Read data register not empty + 0 + 1 + + + CSRNE + Control Buffer register is not empty + 1 + 1 + + + PERR + Parity error + 2 + 1 + + + OVR + Overrun error + 3 + 1 + + + SBD + Synchronization Block Detected + 4 + 1 + + + SYNCD + Synchronization Done + 5 + 1 + + + FERR + Framing error + 6 + 1 + + + SERR + Synchronization error + 7 + 1 + + + TERR + Time-out error + 8 + 1 + + + WIDTH5 + Duration of 5 symbols counted with SPDIF_CLK + 16 + 15 + + + + + IFCR + IFCR + Interrupt Flag Clear register + 0xC + 0x20 + write-only + 0x00000000 + + + PERRCF + Clears the Parity error flag + 2 + 1 + + + OVRCF + Clears the Overrun error flag + 3 + 1 + + + SBDCF + Clears the Synchronization Block Detected flag + 4 + 1 + + + SYNCDCF + Clears the Synchronization Done flag + 5 + 1 + + + + + DR + DR + Data input register + 0x10 + 0x20 + read-only + 0x00000000 + + + DR + Parity Error bit + 0 + 24 + + + PE + Parity Error bit + 24 + 1 + + + V + Validity bit + 25 + 1 + + + U + User bit + 26 + 1 + + + C + Channel Status bit + 27 + 1 + + + PT + Preamble Type + 28 + 2 + + + + + CSR + CSR + Channel Status register + 0x14 + 0x20 + read-only + 0x00000000 + + + USR + User data information + 0 + 16 + + + CS + Channel A status information + 16 + 8 + + + SOB + Start Of Block + 24 + 1 + + + + + DIR + DIR + Debug Information register + 0x18 + 0x20 + read-only + 0x00000000 + + + THI + Threshold HIGH + 0 + 13 + + + TLO + Threshold LOW + 16 + 13 + + + + + + + SDMMC1 + Secure digital input/output interface + SDMMC + 0x40012C00 + + 0x0 + 0x400 + registers + + + SDMMC1 + SDMMC1 global interrupt + 49 + + + + POWER + POWER + power control register + 0x0 + 0x20 + read-write + 0x00000000 + + + PWRCTRL + PWRCTRL + 0 + 2 + + + + + CLKCR + CLKCR + SDI clock control register + 0x4 + 0x20 + read-write + 0x00000000 + + + HWFC_EN + HW Flow Control enable + 14 + 1 + + + NEGEDGE + SDIO_CK dephasing selection bit + 13 + 1 + + + WIDBUS + Wide bus mode enable bit + 11 + 2 + + + BYPASS + Clock divider bypass enable bit + 10 + 1 + + + PWRSAV + Power saving configuration bit + 9 + 1 + + + CLKEN + Clock enable bit + 8 + 1 + + + CLKDIV + Clock divide factor + 0 + 8 + + + + + ARG + ARG + argument register + 0x8 + 0x20 + read-write + 0x00000000 + + + CMDARG + Command argument + 0 + 32 + + + + + CMD + CMD + command register + 0xC + 0x20 + read-write + 0x00000000 + + + SDIOSuspend + SD I/O suspend command + 11 + 1 + + + CPSMEN + Command path state machine (CPSM) Enable bit + 10 + 1 + + + WAITPEND + CPSM Waits for ends of data transfer (CmdPend internal signal) + 9 + 1 + + + WAITINT + CPSM waits for interrupt request + 8 + 1 + + + WAITRESP + Wait for response bits + 6 + 2 + + + CMDINDEX + Command index + 0 + 6 + + + + + RESPCMD + RESPCMD + command response register + 0x10 + 0x20 + read-only + 0x00000000 + + + RESPCMD + Response command index + 0 + 6 + + + + + RESP1 + RESP1 + response 1..4 register + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS1 + see Table 132 + 0 + 32 + + + + + RESP2 + RESP2 + response 1..4 register + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS2 + see Table 132 + 0 + 32 + + + + + RESP3 + RESP3 + response 1..4 register + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTATUS3 + see Table 132 + 0 + 32 + + + + + RESP4 + RESP4 + response 1..4 register + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS4 + see Table 132 + 0 + 32 + + + + + DTIMER + DTIMER + data timer register + 0x24 + 0x20 + read-write + 0x00000000 + + + DATATIME + Data timeout period + 0 + 32 + + + + + DLEN + DLEN + data length register + 0x28 + 0x20 + read-write + 0x00000000 + + + DATALENGTH + Data length value + 0 + 25 + + + + + DCTRL + DCTRL + data control register + 0x2C + 0x20 + read-write + 0x00000000 + + + SDIOEN + SD I/O enable functions + 11 + 1 + + + RWMOD + Read wait mode + 10 + 1 + + + RWSTOP + Read wait stop + 9 + 1 + + + RWSTART + Read wait start + 8 + 1 + + + DBLOCKSIZE + Data block size + 4 + 4 + + + DMAEN + DMA enable bit + 3 + 1 + + + DTMODE + Data transfer mode selection 1: Stream or SDIO multibyte data transfer + 2 + 1 + + + DTDIR + Data transfer direction selection + 1 + 1 + + + DTEN + DTEN + 0 + 1 + + + + + DCOUNT + DCOUNT + data counter register + 0x30 + 0x20 + read-only + 0x00000000 + + + DATACOUNT + Data count value + 0 + 25 + + + + + STA + STA + status register + 0x34 + 0x20 + read-only + 0x00000000 + + + SDIOIT + SDIO interrupt received + 22 + 1 + + + RXDAVL + Data available in receive FIFO + 21 + 1 + + + TXDAVL + Data available in transmit FIFO + 20 + 1 + + + RXFIFOE + Receive FIFO empty + 19 + 1 + + + TXFIFOE + Transmit FIFO empty + 18 + 1 + + + RXFIFOF + Receive FIFO full + 17 + 1 + + + TXFIFOF + Transmit FIFO full + 16 + 1 + + + RXFIFOHF + Receive FIFO half full: there are at least 8 words in the FIFO + 15 + 1 + + + TXFIFOHE + Transmit FIFO half empty: at least 8 words can be written into the FIFO + 14 + 1 + + + RXACT + Data receive in progress + 13 + 1 + + + TXACT + Data transmit in progress + 12 + 1 + + + CMDACT + Command transfer in progress + 11 + 1 + + + DBCKEND + Data block sent/received (CRC check passed) + 10 + 1 + + + DATAEND + Data end (data counter, SDIDCOUNT, is zero) + 8 + 1 + + + CMDSENT + Command sent (no response required) + 7 + 1 + + + CMDREND + Command response received (CRC check passed) + 6 + 1 + + + RXOVERR + Received FIFO overrun error + 5 + 1 + + + TXUNDERR + Transmit FIFO underrun error + 4 + 1 + + + DTIMEOUT + Data timeout + 3 + 1 + + + CTIMEOUT + Command response timeout + 2 + 1 + + + DCRCFAIL + Data block sent/received (CRC check failed) + 1 + 1 + + + CCRCFAIL + Command response received (CRC check failed) + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x38 + 0x20 + read-write + 0x00000000 + + + SDIOITC + SDIOIT flag clear bit + 22 + 1 + + + DBCKENDC + DBCKEND flag clear bit + 10 + 1 + + + DATAENDC + DATAEND flag clear bit + 8 + 1 + + + CMDSENTC + CMDSENT flag clear bit + 7 + 1 + + + CMDRENDC + CMDREND flag clear bit + 6 + 1 + + + RXOVERRC + RXOVERR flag clear bit + 5 + 1 + + + TXUNDERRC + TXUNDERR flag clear bit + 4 + 1 + + + DTIMEOUTC + DTIMEOUT flag clear bit + 3 + 1 + + + CTIMEOUTC + CTIMEOUT flag clear bit + 2 + 1 + + + DCRCFAILC + DCRCFAIL flag clear bit + 1 + 1 + + + CCRCFAILC + CCRCFAIL flag clear bit + 0 + 1 + + + + + MASK + MASK + mask register + 0x3C + 0x20 + read-write + 0x00000000 + + + SDIOITIE + SDIO mode interrupt received interrupt enable + 22 + 1 + + + RXDAVLIE + Data available in Rx FIFO interrupt enable + 21 + 1 + + + TXDAVLIE + Data available in Tx FIFO interrupt enable + 20 + 1 + + + RXFIFOEIE + Rx FIFO empty interrupt enable + 19 + 1 + + + TXFIFOEIE + Tx FIFO empty interrupt enable + 18 + 1 + + + RXFIFOFIE + Rx FIFO full interrupt enable + 17 + 1 + + + TXFIFOFIE + Tx FIFO full interrupt enable + 16 + 1 + + + RXFIFOHFIE + Rx FIFO half full interrupt enable + 15 + 1 + + + TXFIFOHEIE + Tx FIFO half empty interrupt enable + 14 + 1 + + + RXACTIE + Data receive acting interrupt enable + 13 + 1 + + + TXACTIE + Data transmit acting interrupt enable + 12 + 1 + + + CMDACTIE + Command acting interrupt enable + 11 + 1 + + + DBCKENDIE + Data block end interrupt enable + 10 + 1 + + + DATAENDIE + Data end interrupt enable + 8 + 1 + + + CMDSENTIE + Command sent interrupt enable + 7 + 1 + + + CMDRENDIE + Command response received interrupt enable + 6 + 1 + + + RXOVERRIE + Rx FIFO overrun error interrupt enable + 5 + 1 + + + TXUNDERRIE + Tx FIFO underrun error interrupt enable + 4 + 1 + + + DTIMEOUTIE + Data timeout interrupt enable + 3 + 1 + + + CTIMEOUTIE + Command timeout interrupt enable + 2 + 1 + + + DCRCFAILIE + Data CRC fail interrupt enable + 1 + 1 + + + CCRCFAILIE + Command CRC fail interrupt enable + 0 + 1 + + + + + FIFOCNT + FIFOCNT + FIFO counter register + 0x48 + 0x20 + read-only + 0x00000000 + + + FIFOCOUNT + Remaining number of words to be written to or read from the FIFO + 0 + 24 + + + + + FIFO + FIFO + data FIFO register + 0x80 + 0x20 + read-write + 0x00000000 + + + FIFOData + Receive and transmit FIFO data + 0 + 32 + + + + + + + LPTIM1 + Low power timer + LPTIM + 0x40002400 + + 0x0 + 0x400 + registers + + + LPTimer1 + LP Timer1 global interrupt + 93 + + + LP_Timer1 + LP Timer1 global interrupt + 93 + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + DOWN + Counter direction change up to down + 6 + 1 + + + UP + Counter direction change down to up + 5 + 1 + + + ARROK + Autoreload register update OK + 4 + 1 + + + CMPOK + Compare register update OK + 3 + 1 + + + EXTTRIG + External trigger edge event + 2 + 1 + + + ARRM + Autoreload match + 1 + 1 + + + CMPM + Compare match + 0 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + DOWNCF + Direction change to down Clear Flag + 6 + 1 + + + UPCF + Direction change to UP Clear Flag + 5 + 1 + + + ARROKCF + Autoreload register update OK Clear Flag + 4 + 1 + + + CMPOKCF + Compare register update OK Clear Flag + 3 + 1 + + + EXTTRIGCF + External trigger valid edge Clear Flag + 2 + 1 + + + ARRMCF + Autoreload match Clear Flag + 1 + 1 + + + CMPMCF + compare match Clear Flag + 0 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + DOWNIE + Direction change to down Interrupt Enable + 6 + 1 + + + UPIE + Direction change to UP Interrupt Enable + 5 + 1 + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + + + CMPOKIE + Compare register update OK Interrupt Enable + 3 + 1 + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + + + CMPMIE + Compare match Interrupt Enable + 0 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + ENC + Encoder mode enable + 24 + 1 + + + COUNTMODE + counter mode enabled + 23 + 1 + + + PRELOAD + Registers update mode + 22 + 1 + + + WAVPOL + Waveform shape polarity + 21 + 1 + + + WAVE + Waveform shape + 20 + 1 + + + TIMOUT + Timeout enable + 19 + 1 + + + TRIGEN + Trigger enable and polarity + 17 + 2 + + + TRIGSEL + Trigger selector + 13 + 3 + + + PRESC + Clock prescaler + 9 + 3 + + + TRGFLT + Configurable digital filter for trigger + 6 + 2 + + + CKFLT + Configurable digital filter for external clock + 3 + 2 + + + CKPOL + Clock Polarity + 1 + 2 + + + CKSEL + Clock selector + 0 + 1 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + CNTSTRT + Timer start in continuous mode + 2 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + ENABLE + LPTIM Enable + 0 + 1 + + + + + CMP + CMP + Compare Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CMP + Compare value + 0 + 16 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 16 + + + + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EV + I2C1 event interrupt + 31 + + + I2C1_ER + I2C1 error interrupt + 32 + + + I2C2_EV + I2C2 event interrupt + 33 + + + I2C2_ER + I2C2 error interrupt + 34 + + + I2C3_EV + I2C3 event interrupt + 72 + + + I2C3_ER + I2C3 error interrupt + 73 + + + I2C4_EV + I2C4 event interrupt + 95 + + + I2C4_ER + I2C4 error interrupt + 96 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + PE + Peripheral enable + 0 + 1 + + PE + read-write + + Disabled + Peripheral disabled + 0 + + + Enabled + Peripheral enabled + 1 + + + + + TXIE + TX Interrupt enable + 1 + 1 + + TXIE + read-write + + Disabled + Transmit (TXIS) interrupt disabled + 0 + + + Enabled + Transmit (TXIS) interrupt enabled + 1 + + + + + RXIE + RX Interrupt enable + 2 + 1 + + RXIE + read-write + + Disabled + Receive (RXNE) interrupt disabled + 0 + + + Enabled + Receive (RXNE) interrupt enabled + 1 + + + + + ADDRIE + Address match interrupt enable (slave only) + 3 + 1 + + ADDRIE + read-write + + Disabled + Address match (ADDR) interrupts disabled + 0 + + + Enabled + Address match (ADDR) interrupts enabled + 1 + + + + + NACKIE + Not acknowledge received interrupt enable + 4 + 1 + + NACKIE + read-write + + Disabled + Not acknowledge (NACKF) received interrupts disabled + 0 + + + Enabled + Not acknowledge (NACKF) received interrupts enabled + 1 + + + + + STOPIE + STOP detection Interrupt enable + 5 + 1 + + STOPIE + read-write + + Disabled + Stop detection (STOPF) interrupt disabled + 0 + + + Enabled + Stop detection (STOPF) interrupt enabled + 1 + + + + + TCIE + Transfer Complete interrupt enable + 6 + 1 + + TCIE + read-write + + Disabled + Transfer Complete interrupt disabled + 0 + + + Enabled + Transfer Complete interrupt enabled + 1 + + + + + ERRIE + Error interrupts enable + 7 + 1 + + ERRIE + read-write + + Disabled + Error detection interrupts disabled + 0 + + + Enabled + Error detection interrupts enabled + 1 + + + + + DNF + Digital noise filter + 8 + 4 + + DNF + read-write + + NoFilter + Digital filter disabled + 0 + + + Filter1 + Digital filter enabled and filtering capability up to 1 tI2CCLK + 1 + + + Filter2 + Digital filter enabled and filtering capability up to 2 tI2CCLK + 2 + + + Filter3 + Digital filter enabled and filtering capability up to 3 tI2CCLK + 3 + + + Filter4 + Digital filter enabled and filtering capability up to 4 tI2CCLK + 4 + + + Filter5 + Digital filter enabled and filtering capability up to 5 tI2CCLK + 5 + + + Filter6 + Digital filter enabled and filtering capability up to 6 tI2CCLK + 6 + + + Filter7 + Digital filter enabled and filtering capability up to 7 tI2CCLK + 7 + + + Filter8 + Digital filter enabled and filtering capability up to 8 tI2CCLK + 8 + + + Filter9 + Digital filter enabled and filtering capability up to 9 tI2CCLK + 9 + + + Filter10 + Digital filter enabled and filtering capability up to 10 tI2CCLK + 10 + + + Filter11 + Digital filter enabled and filtering capability up to 11 tI2CCLK + 11 + + + Filter12 + Digital filter enabled and filtering capability up to 12 tI2CCLK + 12 + + + Filter13 + Digital filter enabled and filtering capability up to 13 tI2CCLK + 13 + + + Filter14 + Digital filter enabled and filtering capability up to 14 tI2CCLK + 14 + + + Filter15 + Digital filter enabled and filtering capability up to 15 tI2CCLK + 15 + + + + + ANFOFF + Analog noise filter OFF + 12 + 1 + + ANFOFF + read-write + + Enabled + Analog noise filter enabled + 0 + + + Disabled + Analog noise filter disabled + 1 + + + + + TXDMAEN + DMA transmission requests enable + 14 + 1 + + TXDMAEN + read-write + + Disabled + DMA mode disabled for transmission + 0 + + + Enabled + DMA mode enabled for transmission + 1 + + + + + RXDMAEN + DMA reception requests enable + 15 + 1 + + RXDMAEN + read-write + + Disabled + DMA mode disabled for reception + 0 + + + Enabled + DMA mode enabled for reception + 1 + + + + + SBC + Slave byte control + 16 + 1 + + SBC + read-write + + Disabled + Slave byte control disabled + 0 + + + Enabled + Slave byte control enabled + 1 + + + + + NOSTRETCH + Clock stretching disable + 17 + 1 + + NOSTRETCH + read-write + + Enabled + Clock stretching enabled + 0 + + + Disabled + Clock stretching disabled + 1 + + + + + WUPEN + Wakeup from STOP enable + 18 + 1 + + WUPEN + read-write + + Disabled + Wakeup from Stop mode disabled + 0 + + + Enabled + Wakeup from Stop mode enabled + 1 + + + + + GCEN + General call enable + 19 + 1 + + GCEN + read-write + + Disabled + General call disabled. Address 0b00000000 is NACKed + 0 + + + Enabled + General call enabled. Address 0b00000000 is ACKed + 1 + + + + + SMBHEN + SMBus Host address enable + 20 + 1 + + SMBHEN + read-write + + Disabled + Host address disabled. Address 0b0001000x is NACKed + 0 + + + Enabled + Host address enabled. Address 0b0001000x is ACKed + 1 + + + + + SMBDEN + SMBus Device Default address enable + 21 + 1 + + SMBDEN + read-write + + Disabled + Device default address disabled. Address 0b1100001x is NACKed + 0 + + + Enabled + Device default address enabled. Address 0b1100001x is ACKed + 1 + + + + + ALERTEN + SMBUS alert enable + 22 + 1 + + ALERTEN + read-write + + Disabled + In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported + 0 + + + Enabled + In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported + 1 + + + + + PECEN + PEC enable + 23 + 1 + + PECEN + read-write + + Disabled + PEC calculation disabled + 0 + + + Enabled + PEC calculation enabled + 1 + + + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECBYTE + Packet error checking byte + 26 + 1 + oneToSet + + PECBYTER + read + + NoPec + No PEC transfer + 0 + + + Pec + PEC transmission/reception is requested + 1 + + + + PECBYTEW + write + + Pec + PEC transmission/reception is requested + 1 + + + + + AUTOEND + Automatic end mode (master mode) + 25 + 1 + + AUTOEND + read-write + + Software + Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low + 0 + + + Automatic + Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred + 1 + + + + + RELOAD + NBYTES reload mode + 24 + 1 + + RELOAD + read-write + + Completed + The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) + 0 + + + NotCompleted + The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) + 1 + + + + + NBYTES + Number of bytes + 16 + 8 + + + 0 + 255 + + + + + NACK + NACK generation (slave mode) + 15 + 1 + oneToSet + + NACKR + read + + Ack + an ACK is sent after current received byte + 0 + + + Nack + a NACK is sent after current received byte + 1 + + + + NACKW + write + + Nack + a NACK is sent after current received byte + 1 + + + + + STOP + Stop generation (master mode) + 14 + 1 + oneToSet + + STOPR + read + + NoStop + No Stop generation + 0 + + + Stop + Stop generation after current byte transfer + 1 + + + + STOPW + write + + Stop + Stop generation after current byte transfer + 1 + + + + + START + Start generation + 13 + 1 + oneToSet + + STARTR + read + + NoStart + No Start generation + 0 + + + Start + Restart/Start generation + 1 + + + + STARTW + write + + Start + Restart/Start generation + 1 + + + + + HEAD10R + 10-bit address header only read direction (master receiver mode) + 12 + 1 + + HEAD10R + read-write + + Complete + The master sends the complete 10 bit slave address read sequence + 0 + + + Partial + The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction + 1 + + + + + ADD10 + 10-bit addressing mode (master mode) + 11 + 1 + + ADD10 + read-write + + Bit7 + The master operates in 7-bit addressing mode + 0 + + + Bit10 + The master operates in 10-bit addressing mode + 1 + + + + + RD_WRN + Transfer direction (master mode) + 10 + 1 + + RD_WRN + read-write + + Write + Master requests a write transfer + 0 + + + Read + Master requests a read transfer + 1 + + + + + SADD + Slave address bit (master mode) + 0 + 10 + + + 0 + 1023 + + + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + OA1 + Interface address + 0 + 10 + + + 0 + 1023 + + + + + OA1MODE + Own Address 1 10-bit mode + 10 + 1 + + OA1MODE + read-write + + Bit7 + Own address 1 is a 7-bit address + 0 + + + Bit10 + Own address 1 is a 10-bit address + 1 + + + + + OA1EN + Own Address 1 enable + 15 + 1 + + OA1EN + read-write + + Disabled + Own address 1 disabled. The received slave address OA1 is NACKed + 0 + + + Enabled + Own address 1 enabled. The received slave address OA1 is ACKed + 1 + + + + + + + OAR2 + OAR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + OA2 + Interface address + 1 + 7 + + + 0 + 127 + + + + + OA2MSK + Own Address 2 masks + 8 + 3 + + OA2MSK + read-write + + NoMask + No mask + 0 + + + Mask1 + OA2[1] is masked and don’t care. Only OA2[7:2] are compared + 1 + + + Mask2 + OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared + 2 + + + Mask3 + OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared + 3 + + + Mask4 + OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared + 4 + + + Mask5 + OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared + 5 + + + Mask6 + OA2[6:1] are masked and don’t care. Only OA2[7] is compared. + 6 + + + Mask7 + OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged + 7 + + + + + OA2EN + Own Address 2 enable + 15 + 1 + + OA2EN + read-write + + Disabled + Own address 2 disabled. The received slave address OA2 is NACKed + 0 + + + Enabled + Own address 2 enabled. The received slave address OA2 is ACKed + 1 + + + + + + + TIMINGR + TIMINGR + Timing register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low period (master mode) + 0 + 8 + + + 0 + 255 + + + + + SCLH + SCL high period (master mode) + 8 + 8 + + + 0 + 255 + + + + + SDADEL + Data hold time + 16 + 4 + + + 0 + 15 + + + + + SCLDEL + Data setup time + 20 + 4 + + + 0 + 15 + + + + + PRESC + Timing prescaler + 28 + 4 + + + 0 + 15 + + + + + + + TIMEOUTR + TIMEOUTR + Status register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + TIMEOUTA + Bus timeout A + 0 + 12 + + + 0 + 4095 + + + + + TIDLE + Idle clock timeout detection + 12 + 1 + + TIDLE + read-write + + Disabled + TIMEOUTA is used to detect SCL low timeout + 0 + + + Enabled + TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) + 1 + + + + + TIMOUTEN + Clock timeout enable + 15 + 1 + + TIMOUTEN + read-write + + Disabled + SCL timeout detection is disabled + 0 + + + Enabled + SCL timeout detection is enabled + 1 + + + + + TIMEOUTB + Bus timeout B + 16 + 12 + + + 0 + 4095 + + + + + TEXTEN + Extended clock timeout enable + 31 + 1 + + TEXTEN + read-write + + Disabled + Extended clock timeout detection is disabled + 0 + + + Enabled + Extended clock timeout detection is enabled + 1 + + + + + + + ISR + ISR + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDCODE + Address match code (Slave mode) + 17 + 7 + read-only + + + 0 + 127 + + + + + DIR + Transfer direction (Slave mode) + 16 + 1 + read-only + + DIR + read + + Write + Write transfer, slave enters receiver mode + 0 + + + Read + Read transfer, slave enters transmitter mode + 1 + + + + + BUSY + Bus busy + 15 + 1 + read-only + + BUSY + read + + NotBusy + No communication is in progress on the bus + 0 + + + Busy + A communication is in progress on the bus + 1 + + + + + ALERT + SMBus alert + 13 + 1 + read-only + + ALERT + read + + NoAlert + SMBA alert is not detected + 0 + + + Alert + SMBA alert event is detected on SMBA pin + 1 + + + + + TIMEOUT + Timeout or t_low detection flag + 12 + 1 + read-only + + TIMEOUT + read + + NoTimeout + No timeout occured + 0 + + + Timeout + Timeout occured + 1 + + + + + PECERR + PEC Error in reception + 11 + 1 + read-only + + PECERR + read + + Match + Received PEC does match with PEC register + 0 + + + NoMatch + Received PEC does not match with PEC register + 1 + + + + + OVR + Overrun/Underrun (slave mode) + 10 + 1 + read-only + + OVR + read + + NoOverrun + No overrun/underrun error occurs + 0 + + + Overrun + slave mode with NOSTRETCH=1, when an overrun/underrun error occurs + 1 + + + + + ARLO + Arbitration lost + 9 + 1 + read-only + + ARLO + read + + NotLost + No arbitration lost + 0 + + + Lost + Arbitration lost + 1 + + + + + BERR + Bus error + 8 + 1 + read-only + + BERR + read + + NoError + No bus error + 0 + + + Error + Misplaced Start and Stop condition is detected + 1 + + + + + TCR + Transfer Complete Reload + 7 + 1 + read-only + + TCR + read + + NotComplete + Transfer is not complete + 0 + + + Complete + NBYTES has been transfered + 1 + + + + + TC + Transfer Complete (master mode) + 6 + 1 + read-only + + TC + read + + NotComplete + Transfer is not complete + 0 + + + Complete + NBYTES has been transfered + 1 + + + + + STOPF + Stop detection flag + 5 + 1 + read-only + + STOPF + read + + NoStop + No Stop condition detected + 0 + + + Stop + Stop condition detected + 1 + + + + + NACKF + Not acknowledge received flag + 4 + 1 + read-only + + NACKF + read + + NoNack + No NACK has been received + 0 + + + Nack + NACK has been received + 1 + + + + + ADDR + Address matched (slave mode) + 3 + 1 + read-only + + ADDR + read + + NotMatch + Adress mismatched or not received + 0 + + + Match + Received slave address matched with one of the enabled slave addresses + 1 + + + + + RXNE + Receive data register not empty (receivers) + 2 + 1 + read-only + + RXNE + read + + Empty + The RXDR register is empty + 0 + + + NotEmpty + Received data is copied into the RXDR register, and is ready to be read + 1 + + + + + TXIS + Transmit interrupt status (transmitters) + 1 + 1 + read-write + oneToSet + + TXISR + read + + NotEmpty + The TXDR register is not empty + 0 + + + Empty + The TXDR register is empty and the data to be transmitted must be written in the TXDR register + 1 + + + + TXISW + write + + Trigger + Generate a TXIS event + 1 + + + + + TXE + Transmit data register empty (transmitters) + 0 + 1 + read-write + oneToSet + + TXER + read + + NotEmpty + TXDR register not empty + 0 + + + Empty + TXDR register empty + 1 + + + + TXEW + write + + Flush + Flush the transmit data register + 1 + + + + + + + ICR + ICR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTCF + Alert flag clear + 13 + 1 + + ALERTCF + write + + Clear + Clears the ALERT flag in ISR register + 1 + + + + + TIMOUTCF + Timeout detection flag clear + 12 + 1 + + TIMOUTCF + write + + Clear + Clears the TIMOUT flag in ISR register + 1 + + + + + PECCF + PEC Error flag clear + 11 + 1 + + PECCF + write + + Clear + Clears the PEC flag in ISR register + 1 + + + + + OVRCF + Overrun/Underrun flag clear + 10 + 1 + + OVRCF + write + + Clear + Clears the OVR flag in ISR register + 1 + + + + + ARLOCF + Arbitration lost flag clear + 9 + 1 + + ARLOCF + write + + Clear + Clears the ARLO flag in ISR register + 1 + + + + + BERRCF + Bus error flag clear + 8 + 1 + + BERRCF + write + + Clear + Clears the BERR flag in ISR register + 1 + + + + + STOPCF + Stop detection flag clear + 5 + 1 + + STOPCF + write + + Clear + Clears the STOP flag in ISR register + 1 + + + + + NACKCF + Not Acknowledge flag clear + 4 + 1 + + NACKCF + write + + Clear + Clears the NACK flag in ISR register + 1 + + + + + ADDRCF + Address Matched flag clear + 3 + 1 + + ADDRCF + write + + Clear + Clears the ADDR flag in ISR register + 1 + + + + + + + PECR + PECR + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PEC + Packet error checking register + 0 + 8 + + + 0 + 255 + + + + + + + RXDR + RXDR + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RXDATA + 8-bit receive data + 0 + 8 + + + 0 + 255 + + + + + + + TXDR + TXDR + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TXDATA + 8-bit transmit data + 0 + 8 + + + 0 + 255 + + + + + + + + + I2C2 + 0x40005800 + + I2C2_EV + I2C2 event interrupt + 33 + + + I2C2_ER + I2C2 error interrupt + 34 + + + + I2C3 + 0x40005C00 + + I2C3_EV + I2C3 event interrupt + 72 + + + I2C3_ER + I2C3 error interrupt + 73 + + + + I2C4 + 0x40006000 + + I2C4_EV + I2C4 event interrupt + 95 + + + I2C4_ER + I2C4 Error interrupt + 96 + + + + RTC + Real-time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC_WKUP + RTC Tamper or TimeStamp /CSS on LSE through + EXTI line 19 interrupts + 3 + + + RTC_ALARM + RTC alarms through EXTI line 18 + interrupts + 41 + + + + TR + TR + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + PM + AM/PM notation + 22 + 1 + + PM + read-write + + AM + AM or 24-hour format + 0 + + + PM + PM + 1 + + + + + HT + Hour tens in BCD format + 20 + 2 + + + 0 + 3 + + + + + HU + Hour units in BCD format + 16 + 4 + + + 0 + 15 + + + + + MNT + Minute tens in BCD format + 12 + 3 + + + 0 + 7 + + + + + MNU + Minute units in BCD format + 8 + 4 + + + 0 + 15 + + + + + ST + Second tens in BCD format + 4 + 3 + + + 0 + 7 + + + + + SU + Second units in BCD format + 0 + 4 + + + 0 + 15 + + + + + + + DR + DR + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens in BCD format + 20 + 4 + + + 0 + 15 + + + + + YU + Year units in BCD format + 16 + 4 + + + 0 + 15 + + + + + WDU + Week day units + 13 + 3 + + + 1 + 7 + + + + + MT + Month tens in BCD format + 12 + 1 + + MT + read-write + + Zero + Month tens is 0 + 0 + + + One + Month tens is 1 + 1 + + + + + MU + Month units in BCD format + 8 + 4 + + + 0 + 15 + + + + + DT + Date tens in BCD format + 4 + 2 + + + 0 + 3 + + + + + DU + Date units in BCD format + 0 + 4 + + + 0 + 15 + + + + + + + CR + CR + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + WUCKSEL + Wakeup clock selection + 0 + 3 + + WUCKSEL + read-write + + Div16 + RTC/16 clock is selected + 0 + + + Div8 + RTC/8 clock is selected + 1 + + + Div4 + RTC/4 clock is selected + 2 + + + Div2 + RTC/2 clock is selected + 3 + + + ClockSpare + ck_spre (usually 1 Hz) clock is selected + 4 + + + ClockSpareWithOffset + ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + 6 + + + + + TSEDGE + Time-stamp event active edge + 3 + 1 + + TSEDGE + read-write + + RisingEdge + RTC_TS input rising edge generates a time-stamp event + 0 + + + FallingEdge + RTC_TS input falling edge generates a time-stamp event + 1 + + + + + REFCKON + Reference clock detection enable (50 or 60 Hz) + 4 + 1 + + REFCKON + read-write + + Disabled + RTC_REFIN detection disabled + 0 + + + Enabled + RTC_REFIN detection enabled + 1 + + + + + BYPSHAD + Bypass the shadow registers + 5 + 1 + + BYPSHAD + read-write + + ShadowReg + Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles + 0 + + + BypassShadowReg + Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters + 1 + + + + + FMT + Hour format + 6 + 1 + + FMT + read-write + + Twenty_Four_Hour + 24 hour/day format + 0 + + + AM_PM + AM/PM hour format + 1 + + + + + ALRAE + Alarm A enable + 8 + 1 + + ALRAE + read-write + + Disabled + Alarm A disabled + 0 + + + Enabled + Alarm A enabled + 1 + + + + + ALRBE + Alarm B enable + 9 + 1 + + ALRBE + read-write + + Disabled + Alarm B disabled + 0 + + + Enabled + Alarm B enabled + 1 + + + + + WUTE + Wakeup timer enable + 10 + 1 + + WUTE + read-write + + Disabled + Wakeup timer disabled + 0 + + + Enabled + Wakeup timer enabled + 1 + + + + + TSE + Time stamp enable + 11 + 1 + + TSE + read-write + + Disabled + Timestamp disabled + 0 + + + Enabled + Timestamp enabled + 1 + + + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + + ALRAIE + read-write + + Disabled + Alarm A interrupt disabled + 0 + + + Enabled + Alarm A interrupt enabled + 1 + + + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + + ALRBIE + read-write + + Disabled + Alarm B Interrupt disabled + 0 + + + Enabled + Alarm B Interrupt enabled + 1 + + + + + WUTIE + Wakeup timer interrupt enable + 14 + 1 + + WUTIE + read-write + + Disabled + Wakeup timer interrupt disabled + 0 + + + Enabled + Wakeup timer interrupt enabled + 1 + + + + + TSIE + Time-stamp interrupt enable + 15 + 1 + + TSIE + read-write + + Disabled + Time-stamp Interrupt disabled + 0 + + + Enabled + Time-stamp Interrupt enabled + 1 + + + + + ADD1H + Add 1 hour (summer time change) + 16 + 1 + + ADD1HW + write + + Add1 + Adds 1 hour to the current time. This can be used for summer time change outside initialization mode + 1 + + + + + SUB1H + Subtract 1 hour (winter time change) + 17 + 1 + + SUB1HW + write + + Sub1 + Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode + 1 + + + + + BKP + Backup + 18 + 1 + + BKP + read-write + + DST_Not_Changed + Daylight Saving Time change has not been performed + 0 + + + DST_Changed + Daylight Saving Time change has been performed + 1 + + + + + COSEL + Calibration output selection + 19 + 1 + + COSEL + read-write + + CalFreq_512Hz + Calibration output is 512 Hz (with default prescaler setting) + 0 + + + CalFreq_1Hz + Calibration output is 1 Hz (with default prescaler setting) + 1 + + + + + POL + Output polarity + 20 + 1 + + POL + read-write + + High + The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + 0 + + + Low + The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + 1 + + + + + OSEL + Output selection + 21 + 2 + + OSEL + read-write + + Disabled + Output disabled + 0 + + + AlarmA + Alarm A output enabled + 1 + + + AlarmB + Alarm B output enabled + 2 + + + Wakeup + Wakeup output enabled + 3 + + + + + COE + Calibration output enable + 23 + 1 + + COE + read-write + + Disabled + Calibration output disabled + 0 + + + Enabled + Calibration output enabled + 1 + + + + + ITSE + timestamp on internal event enable + 24 + 1 + + + + + ISR + ISR + initialization and status register + 0xC + 0x20 + 0x00000007 + + + ALRAWF + Alarm A write flag + 0 + 1 + read-only + + ALRAWFR + read + + UpdateNotAllowed + Alarm update not allowed + 0 + + + UpdateAllowed + Alarm update allowed + 1 + + + + + ALRBWF + Alarm B write flag + 1 + 1 + read-only + + + + WUTWF + Wakeup timer write flag + 2 + 1 + read-only + + WUTWFR + read + + UpdateNotAllowed + Wakeup timer configuration update not allowed + 0 + + + UpdateAllowed + Wakeup timer configuration update allowed + 1 + + + + + SHPF + Shift operation pending + 3 + 1 + read-write + + SHPFR + read + + NoShiftPending + No shift operation is pending + 0 + + + ShiftPending + A shift operation is pending + 1 + + + + + INITS + Initialization status flag + 4 + 1 + read-only + + INITSR + read + + NotInitalized + Calendar has not been initialized + 0 + + + Initalized + Calendar has been initialized + 1 + + + + + RSF + Registers synchronization flag + 5 + 1 + read-write + zeroToClear + + RSFR + read + + NotSynced + Calendar shadow registers not yet synchronized + 0 + + + Synced + Calendar shadow registers synchronized + 1 + + + + RSFW + write + + Clear + This flag is cleared by software by writing 0 + 0 + + + + + INITF + Initialization flag + 6 + 1 + read-only + + INITFR + read + + NotAllowed + Calendar registers update is not allowed + 0 + + + Allowed + Calendar registers update is allowed + 1 + + + + + INIT + Initialization mode + 7 + 1 + read-write + + INIT + read-write + + FreeRunningMode + Free running mode + 0 + + + InitMode + Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + 1 + + + + + ALRAF + Alarm A flag + 8 + 1 + read-write + zeroToClear + + ALRAFR + read + + Match + This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + 1 + + + + ALRAFW + write + + Clear + This flag is cleared by software by writing 0 + 0 + + + + + ALRBF + Alarm B flag + 9 + 1 + read-write + zeroToClear + + ALRBFR + read + + Match + This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR) + 1 + + + + ALRBFW + write + + Clear + This flag is cleared by software by writing 0 + 0 + + + + + WUTF + Wakeup timer flag + 10 + 1 + read-write + zeroToClear + + WUTFR + read + + Zero + This flag is set by hardware when the wakeup auto-reload counter reaches 0 + 1 + + + + WUTFW + write + + Clear + This flag is cleared by software by writing 0 + 0 + + + + + TSF + Time-stamp flag + 11 + 1 + read-write + zeroToClear + + TSFR + read + + TimestampEvent + This flag is set by hardware when a time-stamp event occurs + 1 + + + + TSFW + write + + Clear + This flag is cleared by software by writing 0 + 0 + + + + + TSOVF + Time-stamp overflow flag + 12 + 1 + read-write + zeroToClear + + TSOVFR + read + + Overflow + This flag is set by hardware when a time-stamp event occurs while TSF is already set + 1 + + + + TSOVFW + write + + Clear + This flag is cleared by software by writing 0 + 0 + + + + + TAMP1F + Tamper detection flag + 13 + 1 + read-write + zeroToClear + + TAMP1FR + read + + Tampered + This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input + 1 + + + + TAMP1FW + write + + Clear + Flag cleared by software writing 0 + 0 + + + + + TAMP2F + RTC_TAMP2 detection flag + 14 + 1 + read-write + zeroToClear + + read + + + write + + + + TAMP3F + RTC_TAMP3 detection flag + 15 + 1 + read-write + zeroToClear + + read + + + write + + + + RECALPF + Recalibration pending Flag + 16 + 1 + read-only + + RECALPFR + read + + Pending + The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + 1 + + + + + + + PRER + PRER + prescaler register + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_A + Asynchronous prescaler factor + 16 + 7 + + + 0 + 127 + + + + + PREDIV_S + Synchronous prescaler factor + 0 + 15 + + + 0 + 32767 + + + + + + + WUTR + WUTR + wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value bits + 0 + 16 + + + 0 + 65535 + + + + + + + 2 + 0x4 + A,B + ALRM%sR + ALRMAR + Alarm register + 0x1C + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm date mask + 31 + 1 + + + + WDSEL + Week day selection + 30 + 1 + + WDSEL + read-write + + DateUnits + DU[3:0] represents the date units + 0 + + + WeekDay + DU[3:0] represents the week day. DT[1:0] is don’t care. + 1 + + + + + DT + Date tens in BCD format + 28 + 2 + + + 0 + 3 + + + + + DU + Date units or day in BCD format + 24 + 4 + + + 0 + 15 + + + + + MSK3 + Alarm hours mask + 23 + 1 + + + + PM + AM/PM notation + 22 + 1 + + PM + read-write + + AM + AM or 24-hour format + 0 + + + PM + PM + 1 + + + + + HT + Hour tens in BCD format + 20 + 2 + + + 0 + 3 + + + + + HU + Hour units in BCD format + 16 + 4 + + + 0 + 15 + + + + + MSK2 + Alarm minutes mask + 15 + 1 + + + + MNT + Minute tens in BCD format + 12 + 3 + + + 0 + 7 + + + + + MNU + Minute units in BCD format + 8 + 4 + + + 0 + 15 + + + + + MSK1 + Alarm seconds mask + 7 + 1 + + MSK1 + read-write + + Mask + Alarm set if the date/day match + 0 + + + NotMask + Date/day don’t care in Alarm comparison + 1 + + + + + ST + Second tens in BCD format + 4 + 3 + + + 0 + 7 + + + + + SU + Second units in BCD format + 0 + 4 + + + 0 + 15 + + + + + + + WPR + WPR + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + Write protection key + 0 + 8 + + + 0 + 255 + + + + + + + SSR + SSR + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + 0 + 65535 + + + + + + + SHIFTR + SHIFTR + shift control register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add one second + 31 + 1 + + ADD1SW + write + + Add1 + Add one second to the clock/calendar + 1 + + + + + SUBFS + Subtract a fraction of a second + 0 + 15 + + + 0 + 32767 + + + + + + + TSTR + TSTR + time stamp time register + 0x30 + + + TSDR + TSDR + time stamp date register + 0x34 + + + TSSSR + TSSSR + timestamp sub second register + 0x38 + + + CALR + CALR + calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + CALP + Increase frequency of RTC by 488.5 ppm + 15 + 1 + + CALP + read-write + + NoChange + No RTCCLK pulses are added + 0 + + + IncreaseFreq + One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + 1 + + + + + CALW8 + Use an 8-second calibration cycle period + 14 + 1 + + CALW8 + read-write + + Eight_Second + When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + 1 + + + + + CALW16 + Use a 16-second calibration cycle period + 13 + 1 + + CALW16 + read-write + + Sixteen_Second + When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + 1 + + + + + CALM + Calibration minus + 0 + 9 + + + 0 + 511 + + + + + + + TAMPCR + TAMPCR + tamper configuration register + 0x40 + 0x20 + read-write + 0x00000000 + + + TAMP1E + Tamper 1 detection enable + 0 + 1 + + + TAMP1TRG + Active level for tamper 1 + 1 + 1 + + + TAMPIE + Tamper interrupt enable + 2 + 1 + + + TAMP2E + Tamper 2 detection enable + 3 + 1 + + + TAMP2TRG + Active level for tamper 2 + 4 + 1 + + + TAMP3E + Tamper 3 detection enable + 5 + 1 + + + TAMP3TRG + Active level for tamper 3 + 6 + 1 + + + TAMPTS + Activate timestamp on tamper detection event + 7 + 1 + + + TAMPFREQ + Tamper sampling frequency + 8 + 3 + + + TAMPFLT + Tamper filter count + 11 + 2 + + + TAMPPRCH + Tamper precharge duration + 13 + 2 + + + TAMPPUDIS + TAMPER pull-up disable + 15 + 1 + + + TAMP1IE + Tamper 1 interrupt enable + 16 + 1 + + + TAMP1NOERASE + Tamper 1 no erase + 17 + 1 + + + TAMP1MF + Tamper 1 mask flag + 18 + 1 + + + TAMP2IE + Tamper 2 interrupt enable + 19 + 1 + + + TAMP2NOERASE + Tamper 2 no erase + 20 + 1 + + + TAMP2MF + Tamper 2 mask flag + 21 + 1 + + + TAMP3IE + Tamper 3 interrupt enable + 22 + 1 + + + TAMP3NOERASE + Tamper 3 no erase + 23 + 1 + + + TAMP3MF + Tamper 3 mask flag + 24 + 1 + + + + + 2 + 0x4 + A,B + ALRM%sSSR + ALRMASSR + Alarm sub-second register + 0x44 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting at this bit + 24 + 4 + + + 0 + 15 + + + + + SS + Sub seconds value + 0 + 15 + + + 0 + 32767 + + + + + + + OR + OR + option register + 0x4C + 0x20 + read-write + 0x00000000 + + + RTC_ALARM_TYPE + RTC_ALARM on PC13 output type + 0 + 1 + + + RTC_OUT_RMP + RTC_OUT remap + 1 + 1 + + + + + 32 + 0x4 + 0-31 + BKP%sR + BKP0R + backup register + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + 0 + 4294967295 + + + + + + + + + USART6 + 0x40011400 + + USART6 + USART6 global interrupt + 71 + + + + USART1 + Universal synchronous asynchronous receiver transmitter + USART + 0x40011000 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 37 + + + USART6 + USART6 global interrupt + 71 + + + UART4 + UART4 global interrupt + 52 + + + UART7 + UART7 global interrupt + 82 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + M1 + Word length + 28 + 1 + + M1 + read-write + + M0 + Use M0 to set the data bits + 0 + + + Bit7 + 1 start bit, 7 data bits, n stop bits + 1 + + + + + EOBIE + End of Block interrupt enable + 27 + 1 + + EOBIE + read-write + + Disabled + Interrupt is inhibited + 0 + + + Enabled + A USART interrupt is generated when the EOBF flag is set in the ISR register + 1 + + + + + RTOIE + Receiver timeout interrupt enable + 26 + 1 + + RTOIE + read-write + + Disabled + Interrupt is inhibited + 0 + + + Enabled + An USART interrupt is generated when the RTOF bit is set in the ISR register + 1 + + + + + OVER8 + Oversampling mode + 15 + 1 + + OVER8 + read-write + + Oversampling16 + Oversampling by 16 + 0 + + + Oversampling8 + Oversampling by 8 + 1 + + + + + CMIE + Character match interrupt enable + 14 + 1 + + CMIE + read-write + + Disabled + Interrupt is disabled + 0 + + + Enabled + Interrupt is generated when the CMF bit is set in the ISR register + 1 + + + + + MME + Mute mode enable + 13 + 1 + + MME + read-write + + Disabled + Receiver in active mode permanently + 0 + + + Enabled + Receiver can switch between mute mode and active mode + 1 + + + + + M0 + Word length + 12 + 1 + + M0 + read-write + + Bit8 + 1 start bit, 8 data bits, n stop bits + 0 + + + Bit9 + 1 start bit, 9 data bits, n stop bits + 1 + + + + + WAKE + Receiver wakeup method + 11 + 1 + + WAKE + read-write + + Idle + Idle line + 0 + + + Address + Address mask + 1 + + + + + PCE + Parity control enable + 10 + 1 + + PCE + read-write + + Disabled + Parity control disabled + 0 + + + Enabled + Parity control enabled + 1 + + + + + PS + Parity selection + 9 + 1 + + PS + read-write + + Even + Even parity + 0 + + + Odd + Odd parity + 1 + + + + + PEIE + PE interrupt enable + 8 + 1 + + PEIE + read-write + + Disabled + Interrupt is disabled + 0 + + + Enabled + Interrupt is generated whenever PE=1 in the ISR register + 1 + + + + + TXEIE + interrupt enable + 7 + 1 + + TXEIE + read-write + + Disabled + Interrupt is disabled + 0 + + + Enabled + Interrupt is generated whenever TXE=1 in the ISR register + 1 + + + + + TCIE + Transmission complete interrupt enable + 6 + 1 + + TCIE + read-write + + Disabled + Interrupt is disabled + 0 + + + Enabled + Interrupt is generated whenever TC=1 in the ISR register + 1 + + + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + RXNEIE + read-write + + Disabled + Interrupt is disabled + 0 + + + Enabled + Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register + 1 + + + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + IDLEIE + read-write + + Disabled + Interrupt is disabled + 0 + + + Enabled + Interrupt is generated whenever IDLE=1 in the ISR register + 1 + + + + + TE + Transmitter enable + 3 + 1 + + TE + read-write + + Disabled + Transmitter is disabled + 0 + + + Enabled + Transmitter is enabled + 1 + + + + + RE + Receiver enable + 2 + 1 + + RE + read-write + + Disabled + Receiver is disabled + 0 + + + Enabled + Receiver is enabled + 1 + + + + + UESM + USART enable in Stop mode + 1 + 1 + + UESM + read-write + + Disabled + USART not able to wake up the MCU from Stop mode + 0 + + + Enabled + USART able to wake up the MCU from Stop mode + 1 + + + + + UE + USART enable + 0 + 1 + + UE + read-write + + Disabled + UART is disabled + 0 + + + Enabled + UART is enabled + 1 + + + + + DEAT + Driver Enable assertion time + 21 + 5 + + + 0 + 31 + + + + + DEDT + Driver Enable de-assertion time + 16 + 5 + + + 0 + 31 + + + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + RTOEN + Receiver timeout enable + 23 + 1 + + RTOEN + read-write + + Disabled + Receiver timeout feature disabled + 0 + + + Enabled + Receiver timeout feature enabled + 1 + + + + + ABREN + Auto baud rate enable + 20 + 1 + + ABREN + read-write + + Disabled + Auto baud rate detection is disabled + 0 + + + Enabled + Auto baud rate detection is enabled + 1 + + + + + MSBFIRST + Most significant bit first + 19 + 1 + + MSBFIRST + read-write + + LSB + data is transmitted/received with data bit 0 first, following the start bit + 0 + + + MSB + data is transmitted/received with MSB (bit 7/8/9) first, following the start bit + 1 + + + + + DATAINV + Binary data inversion + 18 + 1 + + DATAINV + read-write + + Positive + Logical data from the data register are send/received in positive/direct logic + 0 + + + Negative + Logical data from the data register are send/received in negative/inverse logic + 1 + + + + + TXINV + TX pin active level inversion + 17 + 1 + + TXINV + read-write + + Standard + TX pin signal works using the standard logic levels + 0 + + + Inverted + TX pin signal values are inverted + 1 + + + + + RXINV + RX pin active level inversion + 16 + 1 + + RXINV + read-write + + Standard + RX pin signal works using the standard logic levels + 0 + + + Inverted + RX pin signal values are inverted + 1 + + + + + SWAP + Swap TX/RX pins + 15 + 1 + + SWAP + read-write + + Standard + TX/RX pins are used as defined in standard pinout + 0 + + + Swapped + The TX and RX pins functions are swapped + 1 + + + + + LINEN + LIN mode enable + 14 + 1 + + LINEN + read-write + + Disabled + LIN mode disabled + 0 + + + Enabled + LIN mode enabled + 1 + + + + + STOP + STOP bits + 12 + 2 + + STOP + read-write + + Stop1 + 1 stop bit + 0 + + + Stop0p5 + 0.5 stop bit + 1 + + + Stop2 + 2 stop bit + 2 + + + Stop1p5 + 1.5 stop bit + 3 + + + + + CLKEN + Clock enable + 11 + 1 + + CLKEN + read-write + + Disabled + CK pin disabled + 0 + + + Enabled + CK pin enabled + 1 + + + + + CPOL + Clock polarity + 10 + 1 + + CPOL + read-write + + Low + Steady low value on CK pin outside transmission window + 0 + + + High + Steady high value on CK pin outside transmission window + 1 + + + + + CPHA + Clock phase + 9 + 1 + + CPHA + read-write + + First + The first clock transition is the first data capture edge + 0 + + + Second + The second clock transition is the first data capture edge + 1 + + + + + LBCL + Last bit clock pulse + 8 + 1 + + LBCL + read-write + + NotOutput + The clock pulse of the last data bit is not output to the CK pin + 0 + + + Output + The clock pulse of the last data bit is output to the CK pin + 1 + + + + + LBDIE + LIN break detection interrupt enable + 6 + 1 + + LBDIE + read-write + + Disabled + Interrupt is inhibited + 0 + + + Enabled + An interrupt is generated whenever LBDF=1 in the ISR register + 1 + + + + + LBDL + LIN break detection length + 5 + 1 + + LBDL + read-write + + Bit10 + 10-bit break detection + 0 + + + Bit11 + 11-bit break detection + 1 + + + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection + 4 + 1 + + ADDM7 + read-write + + Bit4 + 4-bit address detection + 0 + + + Bit7 + 7-bit address detection + 1 + + + + + ABRMOD + Auto baud rate mode + 21 + 2 + + ABRMOD + read-write + + Start + Measurement of the start bit is used to detect the baud rate + 0 + + + Edge + Falling edge to falling edge measurement + 1 + + + Frame7F + 0x7F frame detection + 2 + + + Frame55 + 0x55 frame detection + 3 + + + + + ADD + Address of the USART node + 24 + 8 + + + 0 + 255 + + + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x00000000 + + + WUFIE + Wakeup from Stop mode interrupt enable + 22 + 1 + + WUFIE + read-write + + Disabled + Interrupt is inhibited + 0 + + + Enabled + An USART interrupt is generated whenever WUF=1 in the ISR register + 1 + + + + + WUS + Wakeup from Stop mode interrupt flag selection + 20 + 2 + + WUS + read-write + + Address + WUF active on address match + 0 + + + Start + WuF active on Start bit detection + 2 + + + RXNE + WUF active on RXNE + 3 + + + + + SCARCNT + Smartcard auto-retry count + 17 + 3 + + + 0 + 7 + + + + + DEP + Driver enable polarity selection + 15 + 1 + + DEP + read-write + + High + DE signal is active high + 0 + + + Low + DE signal is active low + 1 + + + + + DEM + Driver enable mode + 14 + 1 + + DEM + read-write + + Disabled + DE function is disabled + 0 + + + Enabled + The DE signal is output on the RTS pin + 1 + + + + + DDRE + DMA Disable on Reception Error + 13 + 1 + + DDRE + read-write + + NotDisabled + DMA is not disabled in case of reception error + 0 + + + Disabled + DMA is disabled following a reception error + 1 + + + + + OVRDIS + Overrun Disable + 12 + 1 + + OVRDIS + read-write + + Enabled + Overrun Error Flag, ORE, is set when received data is not read before receiving new data + 0 + + + Disabled + Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register + 1 + + + + + ONEBIT + One sample bit method enable + 11 + 1 + + ONEBIT + read-write + + Sample3 + Three sample bit method + 0 + + + Sample1 + One sample bit method + 1 + + + + + CTSIE + CTS interrupt enable + 10 + 1 + + CTSIE + read-write + + Disabled + Interrupt is inhibited + 0 + + + Enabled + An interrupt is generated whenever CTSIF=1 in the ISR register + 1 + + + + + CTSE + CTS enable + 9 + 1 + + CTSE + read-write + + Disabled + CTS hardware flow control disabled + 0 + + + Enabled + CTS mode enabled, data is only transmitted when the CTS input is asserted + 1 + + + + + RTSE + RTS enable + 8 + 1 + + RTSE + read-write + + Disabled + RTS hardware flow control disabled + 0 + + + Enabled + RTS output enabled, data is only requested when there is space in the receive buffer + 1 + + + + + DMAT + DMA enable transmitter + 7 + 1 + + DMAT + read-write + + Disabled + DMA mode is disabled for transmission + 0 + + + Enabled + DMA mode is enabled for transmission + 1 + + + + + DMAR + DMA enable receiver + 6 + 1 + + DMAR + read-write + + Disabled + DMA mode is disabled for reception + 0 + + + Enabled + DMA mode is enabled for reception + 1 + + + + + SCEN + Smartcard mode enable + 5 + 1 + + SCEN + read-write + + Disabled + Smartcard Mode disabled + 0 + + + Enabled + Smartcard Mode enabled + 1 + + + + + NACK + Smartcard NACK enable + 4 + 1 + + NACK + read-write + + Disabled + NACK transmission in case of parity error is disabled + 0 + + + Enabled + NACK transmission during parity error is enabled + 1 + + + + + HDSEL + Half-duplex selection + 3 + 1 + + HDSEL + read-write + + NotSelected + Half duplex mode is not selected + 0 + + + Selected + Half duplex mode is selected + 1 + + + + + IRLP + Ir low-power + 2 + 1 + + IRLP + read-write + + Normal + Normal mode + 0 + + + LowPower + Low-power mode + 1 + + + + + IREN + Ir mode enable + 1 + 1 + + IREN + read-write + + Disabled + IrDA disabled + 0 + + + Enabled + IrDA enabled + 1 + + + + + EIE + Error interrupt enable + 0 + 1 + + EIE + read-write + + Disabled + Interrupt is inhibited + 0 + + + Enabled + An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register + 1 + + + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x00000000 + + + BRR + DIV_Mantissa + 0 + 16 + + + 0 + 65535 + + + + + + + GTPR + GTPR + Guard time and prescaler register + 0x10 + 0x20 + read-write + 0x00000000 + + + GT + Guard time value + 8 + 8 + + + 0 + 255 + + + + + PSC + Prescaler value + 0 + 8 + + + 0 + 255 + + + + + + + RTOR + RTOR + Receiver timeout register + 0x14 + 0x20 + read-write + 0x00000000 + + + BLEN + Block Length + 24 + 8 + + + 0 + 255 + + + + + RTO + Receiver timeout value + 0 + 24 + + + 0 + 16777215 + + + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x00000000 + + + TXFRQ + Transmit data flush request + 4 + 1 + + TXFRQ + write + + Discard + Set the TXE flags. This allows to discard the transmit data + 1 + + + + + RXFRQ + Receive data flush request + 3 + 1 + + RXFRQ + write + + Discard + clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition + 1 + + + + + MMRQ + Mute mode request + 2 + 1 + + MMRQ + write + + Mute + Puts the USART in mute mode and sets the RWU flag + 1 + + + + + SBKRQ + Send break request + 1 + 1 + + SBKRQ + write + + Break + sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available + 1 + + + + + ABRRQ + Auto baud rate request + 0 + 1 + + ABRRQ + write + + Request + resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame + 1 + + + + + + + ISR + ISR + Interrupt & status register + 0x1C + 0x20 + read-only + 0x000000C0 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + ABRF + ABRF + 15 + 1 + + + ABRE + ABRE + 14 + 1 + + + EOBF + EOBF + 12 + 1 + + + RTOF + RTOF + 11 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + LBDF + LBDF + 8 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x00000000 + + + WUCF + Wakeup from Stop mode clear flag + 20 + 1 + + WUCF + write + + Clear + Clears the WUF flag in the ISR register + 1 + + + + + CMCF + Character match clear flag + 17 + 1 + + CMCF + write + + Clear + Clears the CMF flag in the ISR register + 1 + + + + + EOBCF + End of block clear flag + 12 + 1 + + EOBCF + write + + Clear + Clears the EOBF flag in the ISR register + 1 + + + + + RTOCF + Receiver timeout clear flag + 11 + 1 + + RTOCF + write + + Clear + Clears the RTOF flag in the ISR register + 1 + + + + + CTSCF + CTS clear flag + 9 + 1 + + CTSCF + write + + Clear + Clears the CTSIF flag in the ISR register + 1 + + + + + LBDCF + LIN break detection clear flag + 8 + 1 + + LBDCF + write + + Clear + Clears the LBDF flag in the ISR register + 1 + + + + + TCCF + Transmission complete clear flag + 6 + 1 + + TCCF + write + + Clear + Clears the TC flag in the ISR register + 1 + + + + + IDLECF + Idle line detected clear flag + 4 + 1 + + IDLECF + write + + Clear + Clears the IDLE flag in the ISR register + 1 + + + + + ORECF + Overrun error clear flag + 3 + 1 + + ORECF + write + + Clear + Clears the ORE flag in the ISR register + 1 + + + + + NCF + Noise detected clear flag + 2 + 1 + + NCF + write + + Clear + Clears the NF flag in the ISR register + 1 + + + + + FECF + Framing error clear flag + 1 + 1 + + FECF + write + + Clear + Clears the FE flag in the ISR register + 1 + + + + + PECF + Parity error clear flag + 0 + 1 + + PECF + write + + Clear + Clears the PE flag in the ISR register + 1 + + + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RDR + Receive data value + 0 + 9 + + + 0 + 511 + + + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TDR + Transmit data value + 0 + 9 + + + 0 + 511 + + + + + + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + UART5 + 0x40005000 + + UART5 + UART5 global interrupt + 53 + + + + UART4 + 0x40004C00 + + UART4 + UART4 global interrupt + 52 + + + + UART8 + 0x40007C00 + + UART8 + UART 8 global interrupt + 83 + + + + UART7 + 0x40007800 + + UART7 + UART7 global interrupt + 82 + + + + OTG_FS_GLOBAL + USB on the go full speed + USB_OTG_FS + 0x50000000 + + 0x0 + 0x400 + registers + + + + GOTGCTL + GOTGCTL + OTG_FS control and status register (OTG_FS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + SRQSCS + Session request success + 0 + 1 + read-only + + + SRQ + Session request + 1 + 1 + read-write + + + HNGSCS + Host negotiation success + 8 + 1 + read-only + + + HNPRQ + HNP request + 9 + 1 + read-write + + + HSHNPEN + Host set HNP enable + 10 + 1 + read-write + + + DHNPEN + Device HNP enabled + 11 + 1 + read-write + + + CIDSTS + Connector ID status + 16 + 1 + read-only + + + DBCT + Long/short debounce time + 17 + 1 + read-only + + + ASVLD + A-session valid + 18 + 1 + read-only + + + BSVLD + B-session valid + 19 + 1 + read-only + + + VBVALOEN + VBUS valid override enable + 2 + 1 + read-write + + + VBVALOVAL + VBUS valid override value + 3 + 1 + read-write + + + AVALOEN + A-peripheral session valid override enable + 4 + 1 + read-write + + + AVALOVAL + A-peripheral session valid override value + 5 + 1 + read-write + + + BVALOEN + B-peripheral session valid override enable + 6 + 1 + read-write + + + BVALOVAL + B-peripheral session valid override value + 7 + 1 + read-write + + + EHEN + Embedded host enable + 12 + 1 + read-write + + + OTGVER + OTG version + 20 + 1 + read-write + + + CURMOD + Current mode of operation + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTG_FS interrupt register (OTG_FS_GOTGINT) + 0x4 + 0x20 + read-write + 0x00000000 + + + SEDET + Session end detected + 2 + 1 + + + SRSSCHG + Session request success status change + 8 + 1 + + + HNSSCHG + Host negotiation success status change + 9 + 1 + + + HNGDET + Host negotiation detected + 17 + 1 + + + ADTOCHG + A-device timeout change + 18 + 1 + + + DBCDNE + Debounce done + 19 + 1 + + + IDCHNG + ID input pin changed + 20 + 1 + + + + + GAHBCFG + GAHBCFG + OTG_FS AHB configuration register (OTG_FS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GINT + Global interrupt mask + 0 + 1 + + + TXFELVL + TxFIFO empty level + 7 + 1 + + + PTXFELVL + Periodic TxFIFO empty level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + OTG_FS USB configuration register (OTG_FS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOCAL + FS timeout calibration + 0 + 3 + read-write + + + PHYSEL + Full Speed serial transceiver select + 6 + 1 + write-only + + + SRPCAP + SRP-capable + 8 + 1 + read-write + + + HNPCAP + HNP-capable + 9 + 1 + read-write + + + TRDT + USB turnaround time + 10 + 4 + read-write + + + FHMOD + Force host mode + 29 + 1 + read-write + + + FDMOD + Force device mode + 30 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTG_FS reset register (OTG_FS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSRST + Core soft reset + 0 + 1 + read-write + + + HSRST + HCLK soft reset + 1 + 1 + read-write + + + FCRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDL + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTG_FS core interrupt register (OTG_FS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CMOD + Current mode of operation + 0 + 1 + read-only + + + MMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFE + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINAKEFF + Global IN non-periodic NAK effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ESUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDNE + Enumeration done + 13 + 1 + read-write + + + ISOODRP + Isochronous OUT packet dropped interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame interrupt + 15 + 1 + read-write + + + IEPINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPINT + OUT endpoint interrupt + 19 + 1 + read-only + + + IISOIXFR + Incomplete isochronous IN transfer + 20 + 1 + read-write + + + IPXFR_INCOMPISOOUT + Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode) + 21 + 1 + read-write + + + HPRTINT + Host port interrupt + 24 + 1 + read-only + + + HCINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFE + Periodic TxFIFO empty + 26 + 1 + read-only + + + CIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCINT + Disconnect detected interrupt + 29 + 1 + read-write + + + SRQINT + Session request/new session detected interrupt + 30 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected interrupt + 31 + 1 + read-write + + + RSTDET + Reset detected interrupt + 23 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTG_FS interrupt mask register (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MMISM + Mode mismatch interrupt mask + 1 + 1 + read-write + + + OTGINT + OTG interrupt mask + 2 + 1 + read-write + + + SOFM + Start of frame mask + 3 + 1 + read-write + + + RXFLVLM + Receive FIFO non-empty mask + 4 + 1 + read-write + + + NPTXFEM + Non-periodic TxFIFO empty mask + 5 + 1 + read-write + + + GINAKEFFM + Global non-periodic IN NAK effective mask + 6 + 1 + read-write + + + GONAKEFFM + Global OUT NAK effective mask + 7 + 1 + read-write + + + ESUSPM + Early suspend mask + 10 + 1 + read-write + + + USBSUSPM + USB suspend mask + 11 + 1 + read-write + + + USBRST + USB reset mask + 12 + 1 + read-write + + + ENUMDNEM + Enumeration done mask + 13 + 1 + read-write + + + ISOODRPM + Isochronous OUT packet dropped interrupt mask + 14 + 1 + read-write + + + EOPFM + End of periodic frame interrupt mask + 15 + 1 + read-write + + + IEPINT + IN endpoints interrupt mask + 18 + 1 + read-write + + + OEPINT + OUT endpoints interrupt mask + 19 + 1 + read-write + + + IISOIXFRM + Incomplete isochronous IN transfer mask + 20 + 1 + read-write + + + IPXFRM_IISOOXFRM + Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode) + 21 + 1 + read-write + + + PRTIM + Host port interrupt mask + 24 + 1 + read-write + + + HCIM + Host channels interrupt mask + 25 + 1 + read-write + + + PTXFEM + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CIDSCHGM + Connector ID status change mask + 28 + 1 + read-write + + + DISCINT + Disconnect detected interrupt mask + 29 + 1 + read-write + + + SRQIM + Session request/new session detected interrupt mask + 30 + 1 + read-write + + + WUIM + Resume/remote wakeup detected interrupt mask + 31 + 1 + read-write + + + RSTDETM + Reset detected interrupt mask + 23 + 1 + read-write + + + LPMIN + LPM interrupt mask + 27 + 1 + read-write + + + + + GRXSTSR_Device + GRXSTSR_Device + OTG_FS Receive status debug read(Device mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + GRXSTSR_Host + GRXSTSR_Host + OTG_FS Receive status debug read(Host mode) + GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + STSPHST + Status phase start + 27 + 1 + + + + + GRXFSIZ + GRXFSIZ + OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFD + RxFIFO depth + 0 + 16 + + + + + DIEPTXF0 + DIEPTXF0_Device + OTG_FS Endpoint 0 Transmit FIFO size + 0x28 + 0x20 + read-write + 0x00000200 + + + TX0FSA + Endpoint 0 transmit RAM start address + 0 + 16 + + + TX0FD + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + HNPTXFSIZ_Host + HNPTXFSIZ_Host + OTG_FS Host non-periodic transmit FIFO size register + DIEPTXF0 + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSA + Non-periodic transmit RAM start address + 0 + 16 + + + NPTXFD + Non-periodic TxFIFO depth + 16 + 16 + + + + + HNPTXSTS + HNPTXSTS + OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSAV + Non-periodic TxFIFO space available + 0 + 16 + + + NPTQXSAV + Non-periodic transmit request queue space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request queue + 24 + 7 + + + + + GCCFG + GCCFG + OTG_FS general core configuration register (OTG_FS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDWN + Power down + 16 + 1 + + + BCDEN + Battery charging detector (BCD) enable + 17 + 1 + + + DCDEN + Data contact detection (DCD) mode enable + 18 + 1 + + + PDEN + Primary detection (PD) mode enable + 19 + 1 + + + SDEN + Secondary detection (SD) mode enable + 20 + 1 + + + VBDEN + USB VBUS detection enable + 21 + 1 + + + DCDET + Data contact detection (DCD) status + 0 + 1 + + + PDET + Primary detection (PD) status + 1 + 1 + + + SDET + Secondary detection (SD) status + 2 + 1 + + + PS2DET + DM pull-up detection status + 3 + 1 + + + + + CID + CID + core ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + PRODUCT_ID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXSA + Host periodic TxFIFO start address + 0 + 16 + + + PTXFSIZ + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF1) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFO2 transmit RAM start address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFO3 transmit RAM start address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFO4 transmit RAM start address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + GRXSTSP_Device + GRXSTSP_Device + OTG status read and pop register (Device mode) + 0x20 + 0x20 + read-only + 0x02000400 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + GRXSTSP_Host + GRXSTSP_Host + OTG status read and pop register (Host mode) + GRXSTSP_Device + 0x20 + 0x20 + read-only + 0x02000400 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + STSPHST + Status phase start + 27 + 1 + + + + + GI2CCTL + GI2CCTL + OTG I2C access register + 0x30 + 0x20 + read-write + 0x02000400 + + + RWDATA + I2C Read/Write Data + 0 + 8 + + + REGADDR + I2C Register Address + 8 + 8 + + + ADDR + I2C Address + 16 + 7 + + + I2CEN + I2C Enable + 23 + 1 + + + ACK + I2C ACK + 24 + 1 + + + I2CDEVADR + I2C Device Address + 26 + 2 + + + I2CDATSE0 + I2C DatSe0 USB mode + 28 + 1 + + + RW + Read/Write Indicator + 30 + 1 + + + BSYDNE + I2C Busy/Done + 31 + 1 + + + + + GPWRDN + GPWRDN + OTG power down register + 0x58 + 0x20 + read-write + 0x02000400 + + + ADPMEN + ADP module enable + 0 + 1 + + + ADPIF + ADP interrupt flag + 23 + 1 + + + + + GADPCTL + GADPCTL + OTG ADP timer, control and status register + 0x60 + 0x20 + 0x02000400 + + + PRBDSCHG + Probe discharge + 0 + 2 + read-write + + + PRBDELTA + Probe delta + 2 + 2 + read-write + + + PRBPER + Probe period + 4 + 2 + read-write + + + RTIM + Ramp time + 6 + 11 + read-only + + + ENAPRB + Enable probe + 17 + 1 + read-write + + + ENASNS + Enable sense + 18 + 1 + read-write + + + ADPRST + ADP reset + 19 + 1 + read-only + + + ADPEN + ADP enable + 20 + 1 + read-write + + + ADPPRBIF + ADP probe interrupt flag + 21 + 1 + read-write + + + ADPSNSIF + ADP sense interrupt flag + 22 + 1 + read-write + + + ADPTOIF + ADP timeout interrupt flag + 23 + 1 + read-write + + + ADPPRBIM + ADP probe interrupt mask + 24 + 1 + read-write + + + ADPSNSIM + ADP sense interrupt mask + 25 + 1 + read-write + + + ADPTOIM + ADP timeout interrupt mask + 26 + 1 + read-write + + + AR + Access request + 27 + 2 + read-write + + + + + DIEPTXF4 + DIEPTXF4 + OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4) + 0x110 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start address + 0 + 16 + + + INEPTXFD + IN endpoint Tx FIFO depth + 16 + 16 + + + + + DIEPTXF5 + DIEPTXF5 + OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF5) + 0x114 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start address + 0 + 16 + + + INEPTXFD + IN endpoint Tx FIFO depth + 16 + 16 + + + + + GLPMCFG + GLPMCFG + OTG core LPM configuration register + 0x54 + 0x20 + 0x00000000 + + + LPMEN + LPM support enable + 0 + 1 + read-write + + + LPMACK + LPM token acknowledge enable + 1 + 1 + read-write + + + BESL + Best effort service latency + 2 + 4 + read-write + + + REMWAKE + bRemoteWake value + 6 + 1 + read-write + + + L1SSEN + L1 Shallow Sleep enable + 7 + 1 + read-write + + + BESLTHRS + BESL threshold + 8 + 4 + read-write + + + L1DSEN + L1 deep sleep enable + 12 + 1 + read-write + + + LPMRST + LPM response + 13 + 2 + read-only + + + SLPSTS + Port sleep status + 15 + 1 + read-only + + + L1RSMOK + Sleep State Resume OK + 16 + 1 + read-only + + + LPMCHIDX + LPM Channel Index + 17 + 4 + read-write + + + LPMRCNT + LPM retry count + 21 + 3 + read-write + + + SNDLPM + Send LPM transaction + 24 + 1 + read-write + + + LPMRCNTSTS + LPM retry count status + 25 + 3 + read-only + + + ENBESL + Enable best effort service latency + 28 + 1 + read-write + + + + + + + OTG_FS_HOST + USB on the go full speed + USB_OTG_FS + 0x50000400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTG_FS host configuration register (OTG_FS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCS + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSS + FS- and LS-only support + 2 + 1 + read-write + + + + + HFIR + HFIR + OTG_FS Host frame interval register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRIVL + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSAVL + Periodic transmit data FIFO space available + 0 + 16 + read-write + + + PTXQSAV + Periodic transmit request queue space available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTG_FS Host all channels interrupt register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTG_FS host all channels interrupt mask register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTM + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTG_FS host port control and status register (OTG_FS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PCSTS + Port connect status + 0 + 1 + read-only + + + PCDET + Port connect detected + 1 + 1 + read-write + + + PENA + Port enable + 2 + 1 + read-write + + + PENCHNG + Port enable/disable change + 3 + 1 + read-write + + + POCA + Port overcurrent active + 4 + 1 + read-only + + + POCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRES + Port resume + 6 + 1 + read-write + + + PSUSP + Port suspend + 7 + 1 + read-write + + + PRST + Port reset + 8 + 1 + read-write + + + PLSTS + Port line status + 10 + 2 + read-only + + + PPWR + Port power + 12 + 1 + read-write + + + PTCTL + Port test control + 13 + 4 + read-write + + + PSPD + Port speed + 17 + 2 + read-only + + + + + 12 + 0x20 + 0-11 + HC%s + Host channel + 0x100 + + CHAR + HCCHAR0 + OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) + 0x0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + INT + HCINT0 + OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) + 0x8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received interrupt + 3 + 1 + + + NAK + NAK response received interrupt + 4 + 1 + + + ACK + ACK response received/transmitted interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + INTMSK + HCINTMSK0 + OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) + 0xC + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt mask + 3 + 1 + + + NAKM + NAK response received interrupt mask + 4 + 1 + + + ACKM + ACK response received/transmitted interrupt mask + 5 + 1 + + + NYET + response received interrupt mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + TSIZ + HCTSIZ0 + OTG_FS host channel-0 transfer size register + 0x10 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + + + + OTG_FS_DEVICE + USB on the go full speed + USB_OTG_FS + 0x50000800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTG_FS device configuration register (OTG_FS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DSPD + Device speed + 0 + 2 + + + NZLSOHSK + Non-zero-length status OUT handshake + 2 + 1 + + + DAD + Device address + 4 + 7 + + + PFIVL + Periodic frame interval + 11 + 2 + + + + + DCTL + DCTL + OTG_FS device control register (OTG_FS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWUSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SDIS + Soft disconnect + 1 + 1 + read-write + + + GINSTS + Global IN NAK status + 2 + 1 + read-only + + + GONSTS + Global OUT NAK status + 3 + 1 + read-only + + + TCTL + Test control + 4 + 3 + read-write + + + SGINAK + Set global IN NAK + 7 + 1 + read-write + + + CGINAK + Clear global IN NAK + 8 + 1 + read-write + + + SGONAK + Set global OUT NAK + 9 + 1 + read-write + + + CGONAK + Clear global OUT NAK + 10 + 1 + read-write + + + POPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTG_FS device status register (OTG_FS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + EERR + Erratic error + 3 + 1 + + + FNSOF + Frame number of the received SOF + 8 + 14 + + + + + DIEPMSK + DIEPMSK + OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt mask + 1 + 1 + + + TOM + Timeout condition mask (Non-isochronous endpoints) + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective mask + 6 + 1 + + + + + DOEPMSK + DOEPMSK + OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt mask + 1 + 1 + + + STUPM + SETUP phase done mask + 3 + 1 + + + OTEPDM + OUT token received when endpoint disabled mask + 4 + 1 + + + + + DAINT + DAINT + OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + IEPINT + IN endpoint interrupt bits + 0 + 16 + + + OEPINT + OUT endpoint interrupt bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + IEPM + IN EP interrupt mask bits + 0 + 16 + + + OEPM + OUT EP interrupt mask bits + 16 + 16 + + + + + DVBUSDIS + DVBUSDIS + OTG_FS device VBUS discharge time register + 0x28 + 0x20 + read-write + 0x000017D7 + + + VBUSDT + Device VBUS discharge time + 0 + 16 + + + + + DVBUSPULSE + DVBUSPULSE + OTG_FS device VBUS pulsing time register + 0x2C + 0x20 + read-write + 0x000005B8 + + + DVBUSP + Device VBUS pulsing time + 0 + 12 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTG_FS device IN endpoint FIFO empty interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEM + IN EP Tx FIFO empty interrupt mask bits + 0 + 16 + + + + + DIEP0 + Device IN endpoint 0 + 0x100 + + CTL + DIEPCTL0 + OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0) + 0x0 + 0x20 + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 2 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-only + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + INT + DIEPINT0 + device endpoint-x interrupt register + 0x8 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + TSIZ + DIEPTSIZ0 + device endpoint-0 transfer size register + 0x10 + 0x20 + read-write + 0x00000000 + + + PKTCNT + Packet count + 19 + 2 + + + XFRSIZ + Transfer size + 0 + 7 + + + + + TXFSTS + DTXFSTS0 + OTG_FS device IN endpoint transmit FIFO status register + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space available + 0 + 16 + + + + + + 5 + 0x20 + 1-5 + DIEP%s + Device IN endpoint X + 0x120 + + CTL + DIEPCTL1 + OTG device endpoint-1 control register + 0x0 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM_SD1PID + SODDFRM/SD1PID + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + INT + DIEPINT1 + device endpoint-1 interrupt register + 0x8 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + TSIZ + DIEPTSIZ1 + device endpoint-1 transfer size register + 0x10 + 0x20 + read-write + 0x00000000 + + + MCNT + Multi count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + TXFSTS + DTXFSTS1 + OTG_FS device IN endpoint transmit FIFO status register + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space available + 0 + 16 + + + + + + DOEP0 + Device OUT endpoint 0 + 0x300 + + CTL + DOEPCTL0 + device endpoint-0 control register + 0x0 + 0x20 + 0x00008000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-only + + + MPSIZ + MPSIZ + 0 + 2 + read-only + + + + + INT + DOEPINT0 + device endpoint-0 interrupt register + 0x8 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + TSIZ + DOEPTSIZ0 + device OUT endpoint-0 transfer size register + 0x10 + 0x20 + read-write + 0x00000000 + + + STUPCNT + SETUP packet count + 29 + 2 + + + PKTCNT + Packet count + 19 + 1 + + + XFRSIZ + Transfer size + 0 + 7 + + + + + + 5 + 0x20 + 1-5 + DOEP%s + Device IN endpoint X + 0x320 + + CTL + DOEPCTL1 + device endpoint-1 control register + 0x0 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + INT + DOEPINT1 + device endpoint-1 interrupt register + 0x8 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + TSIZ + DOEPTSIZ1 + device OUT endpoint-1 transfer size register + 0x10 + 0x20 + read-write + 0x00000000 + + + RXDPID_STUPCNT + Received data PID/SETUP packet count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + + + + OTG_FS_PWRCLK + USB on the go full speed + USB_OTG_FS + 0x50000E00 + + 0x0 + 0x400 + registers + + + OTG_FS_WKUP + USB On-The-Go FS Wakeup through EXTI line + interrupt + 42 + + + OTG_FS + USB On The Go FS global + interrupt + 67 + + + + PCGCCTL + PCGCCTL + OTG_FS power and clock gating control register (OTG_FS_PCGCCTL) + 0x0 + 0x20 + read-write + 0x00000000 + + + STPPCLK + Stop PHY clock + 0 + 1 + + + GATEHCLK + Gate HCLK + 1 + 1 + + + PHYSUSP + PHY Suspended + 4 + 1 + + + + + + + OTG_HS_GLOBAL + USB on the go high speed + USB_OTG_HS + 0x40040000 + + 0x0 + 0x400 + registers + + + + GOTGCTL + GOTGCTL + OTG_HS control and status register + 0x0 + 0x20 + 0x00000800 + + + SRQSCS + Session request success + 0 + 1 + read-only + + + SRQ + Session request + 1 + 1 + read-write + + + HNGSCS + Host negotiation success + 8 + 1 + read-only + + + HNPRQ + HNP request + 9 + 1 + read-write + + + HSHNPEN + Host set HNP enable + 10 + 1 + read-write + + + DHNPEN + Device HNP enabled + 11 + 1 + read-write + + + CIDSTS + Connector ID status + 16 + 1 + read-only + + + DBCT + Long/short debounce time + 17 + 1 + read-only + + + ASVLD + A-session valid + 18 + 1 + read-only + + + BSVLD + B-session valid + 19 + 1 + read-only + + + EHEN + Embedded host enable + 12 + 1 + read-write + + + VBVALOEN + V_BUS valid override enable + 2 + 1 + read-write + + + VBVALOVAL + V_BUS valid override value + 3 + 1 + read-write + + + AVALOEN + A-peripheral session valid override enable + 4 + 1 + read-write + + + AVALOVAL + A-peripheral session valid override value + 5 + 1 + read-write + + + BVALOEN + B-peripheral session valid override enable + 6 + 1 + read-write + + + BVALOVAL + B-peripheral session valid override value + 7 + 1 + read-write + + + OTGVER + OTG version + 20 + 1 + read-write + + + CURMOD + Current mode of operation + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTG_HS interrupt register + 0x4 + 0x20 + read-write + 0x00000000 + + + SEDET + Session end detected + 2 + 1 + + + SRSSCHG + Session request success status change + 8 + 1 + + + HNSSCHG + Host negotiation success status change + 9 + 1 + + + HNGDET + Host negotiation detected + 17 + 1 + + + ADTOCHG + A-device timeout change + 18 + 1 + + + DBCDNE + Debounce done + 19 + 1 + + + IDCHNG + ID input pin changed + 20 + 1 + + + + + GAHBCFG + GAHBCFG + OTG_HS AHB configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + GINT + Global interrupt mask + 0 + 1 + + + HBSTLEN + Burst length/type + 1 + 4 + + + DMAEN + DMA enable + 5 + 1 + + + TXFELVL + TxFIFO empty level + 7 + 1 + + + PTXFELVL + Periodic TxFIFO empty level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + OTG_HS USB configuration register + 0xC + 0x20 + 0x00000A00 + + + TOCAL + FS timeout calibration + 0 + 3 + read-write + + + PHYSEL + USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select + 6 + 1 + write-only + + + SRPCAP + SRP-capable + 8 + 1 + read-write + + + HNPCAP + HNP-capable + 9 + 1 + read-write + + + TRDT + USB turnaround time + 10 + 4 + read-write + + + PHYLPCS + PHY Low-power clock select + 15 + 1 + read-write + + + ULPIFSLS + ULPI FS/LS select + 17 + 1 + read-write + + + ULPIAR + ULPI Auto-resume + 18 + 1 + read-write + + + ULPICSM + ULPI Clock SuspendM + 19 + 1 + read-write + + + ULPIEVBUSD + ULPI External VBUS Drive + 20 + 1 + read-write + + + ULPIEVBUSI + ULPI external VBUS indicator + 21 + 1 + read-write + + + TSDPS + TermSel DLine pulsing selection + 22 + 1 + read-write + + + PCCI + Indicator complement + 23 + 1 + read-write + + + PTCI + Indicator pass through + 24 + 1 + read-write + + + ULPIIPD + ULPI interface protect disable + 25 + 1 + read-write + + + FHMOD + Forced host mode + 29 + 1 + read-write + + + FDMOD + Forced peripheral mode + 30 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTG_HS reset register + 0x10 + 0x20 + 0x20000000 + + + CSRST + Core soft reset + 0 + 1 + read-write + + + HSRST + HCLK soft reset + 1 + 1 + read-write + + + FCRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDL + AHB master idle + 31 + 1 + read-only + + + DMAREQ + DMA request signal enabled for USB OTG HS + 30 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTG_HS core interrupt register + 0x14 + 0x20 + 0x04000020 + + + CMOD + Current mode of operation + 0 + 1 + read-only + + + MMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO nonempty + 4 + 1 + read-only + + + NPTXFE + Nonperiodic TxFIFO empty + 5 + 1 + read-only + + + GINAKEFF + Global IN nonperiodic NAK effective + 6 + 1 + read-only + + + BOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ESUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDNE + Enumeration done + 13 + 1 + read-write + + + ISOODRP + Isochronous OUT packet dropped interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame interrupt + 15 + 1 + read-write + + + IEPINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPINT + OUT endpoint interrupt + 19 + 1 + read-only + + + IISOIXFR + Incomplete isochronous IN transfer + 20 + 1 + read-write + + + PXFR_INCOMPISOOUT + Incomplete periodic transfer + 21 + 1 + read-write + + + DATAFSUSP + Data fetch suspended + 22 + 1 + read-write + + + HPRTINT + Host port interrupt + 24 + 1 + read-only + + + HCINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFE + Periodic TxFIFO empty + 26 + 1 + read-only + + + CIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCINT + Disconnect detected interrupt + 29 + 1 + read-write + + + SRQINT + Session request/new session detected interrupt + 30 + 1 + read-write + + + WKUINT + Resume/remote wakeup detected interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTG_HS interrupt mask register + 0x18 + 0x20 + 0x00000000 + + + MMISM + Mode mismatch interrupt mask + 1 + 1 + read-write + + + OTGINT + OTG interrupt mask + 2 + 1 + read-write + + + SOFM + Start of frame mask + 3 + 1 + read-write + + + RXFLVLM + Receive FIFO nonempty mask + 4 + 1 + read-write + + + NPTXFEM + Nonperiodic TxFIFO empty mask + 5 + 1 + read-write + + + GINAKEFFM + Global nonperiodic IN NAK effective mask + 6 + 1 + read-write + + + GONAKEFFM + Global OUT NAK effective mask + 7 + 1 + read-write + + + ESUSPM + Early suspend mask + 10 + 1 + read-write + + + USBSUSPM + USB suspend mask + 11 + 1 + read-write + + + USBRST + USB reset mask + 12 + 1 + read-write + + + ENUMDNEM + Enumeration done mask + 13 + 1 + read-write + + + ISOODRPM + Isochronous OUT packet dropped interrupt mask + 14 + 1 + read-write + + + EOPFM + End of periodic frame interrupt mask + 15 + 1 + read-write + + + IEPINT + IN endpoints interrupt mask + 18 + 1 + read-write + + + OEPINT + OUT endpoints interrupt mask + 19 + 1 + read-write + + + IISOIXFRM + Incomplete isochronous IN transfer mask + 20 + 1 + read-write + + + PXFRM_IISOOXFRM + Incomplete periodic transfer mask + 21 + 1 + read-write + + + FSUSPM + Data fetch suspended mask + 22 + 1 + read-write + + + PRTIM + Host port interrupt mask + 24 + 1 + read-only + + + HCIM + Host channels interrupt mask + 25 + 1 + read-write + + + PTXFEM + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CIDSCHGM + Connector ID status change mask + 28 + 1 + read-write + + + DISCINT + Disconnect detected interrupt mask + 29 + 1 + read-write + + + SRQIM + Session request/new session detected interrupt mask + 30 + 1 + read-write + + + WUIM + Resume/remote wakeup detected interrupt mask + 31 + 1 + read-write + + + RSTDE + Reset detected interrupt mask + 23 + 1 + read-write + + + LPMINTM + LPM interrupt mask + 27 + 1 + read-write + + + + + GRXSTSR_Host + GRXSTSR_Host + OTG_HS Receive status debug read register (host mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXSTSP_Host + GRXSTSP_Host + OTG_HS status read and pop register (host mode) + 0x20 + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTG_HS Receive FIFO size register + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFD + RxFIFO depth + 0 + 16 + + + + + HNPTXFSIZ + HNPTXFSIZ_Host + OTG_HS nonperiodic transmit FIFO size register (host mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSA + Nonperiodic transmit RAM start address + 0 + 16 + + + NPTXFD + Nonperiodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF0 + DIEPTXF0_Device + Endpoint 0 transmit FIFO size (peripheral mode) + HNPTXFSIZ + 0x28 + 0x20 + read-write + 0x00000200 + + + TX0FSA + Endpoint 0 transmit RAM start address + 0 + 16 + + + TX0FD + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + HNPTXSTS + GNPTXSTS + OTG_HS nonperiodic transmit FIFO/queue status register + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSAV + Nonperiodic TxFIFO space available + 0 + 16 + + + NPTQXSAV + Nonperiodic transmit request queue space available + 16 + 8 + + + NPTXQTOP + Top of the nonperiodic transmit request queue + 24 + 7 + + + + + GCCFG + GCCFG + OTG_HS general core configuration register + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDWN + Power down + 16 + 1 + + + BCDEN + Battery charging detector (BCD) enable + 17 + 1 + + + DCDEN + Data contact detection (DCD) mode enable + 18 + 1 + + + PDEN + Primary detection (PD) mode enable + 19 + 1 + + + SDEN + Secondary detection (SD) mode enable + 20 + 1 + + + VBDEN + USB VBUS detection enable + 21 + 1 + + + DCDET + Data contact detection (DCD) status + 0 + 1 + + + PDET + Primary detection (PD) status + 1 + 1 + + + SDET + Secondary detection (SD) status + 2 + 1 + + + PS2DET + DM pull-up detection status + 3 + 1 + + + + + CID + CID + OTG_HS core ID register + 0x3C + 0x20 + read-write + 0x00001200 + + + PRODUCT_ID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTG_HS Host periodic transmit FIFO size register + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXSA + Host periodic TxFIFO start address + 0 + 16 + + + PTXFD + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTG_HS device IN endpoint transmit FIFO size register + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTG_HS device IN endpoint transmit FIFO size register + 0x108 + 0x20 + read-write + 0x02000600 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTG_HS device IN endpoint transmit FIFO size register + 0x10C + 0x20 + read-write + 0x02000800 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF4 + DIEPTXF4 + OTG_HS device IN endpoint transmit FIFO size register + 0x110 + 0x20 + read-write + 0x02000A00 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF5 + DIEPTXF5 + OTG_HS device IN endpoint transmit FIFO size register + 0x114 + 0x20 + read-write + 0x02000C00 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF6 + DIEPTXF6 + OTG_HS device IN endpoint transmit FIFO size register + 0x118 + 0x20 + read-write + 0x02000E00 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF7 + DIEPTXF7 + OTG_HS device IN endpoint transmit FIFO size register + 0x11C + 0x20 + read-write + 0x02001000 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + GRXSTSR_Device + GRXSTSR_Device + OTG_HS Receive status debug read register (peripheral mode mode) + GRXSTSR_Host + 0x1C + 0x20 + read-only + 0x00000000 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + GRXSTSP_Device + GRXSTSP_Device + OTG_HS status read and pop register (peripheral mode) + GRXSTSP_Host + 0x20 + 0x20 + read-only + 0x00000000 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + GLPMCFG + GLPMCFG + OTG core LPM configuration register + 0x54 + 0x20 + 0x00000000 + + + LPMEN + LPM support enable + 0 + 1 + read-write + + + LPMACK + LPM token acknowledge enable + 1 + 1 + read-write + + + BESL + Best effort service latency + 2 + 4 + read-only + + + REMWAKE + bRemoteWake value + 6 + 1 + read-only + + + L1SSEN + L1 Shallow Sleep enable + 7 + 1 + read-write + + + BESLTHRS + BESL threshold + 8 + 4 + read-write + + + L1DSEN + L1 deep sleep enable + 12 + 1 + read-write + + + LPMRST + LPM response + 13 + 2 + read-only + + + SLPSTS + Port sleep status + 15 + 1 + read-only + + + L1RSMOK + Sleep State Resume OK + 16 + 1 + read-only + + + LPMCHIDX + LPM Channel Index + 17 + 4 + read-write + + + LPMRCNT + LPM retry count + 21 + 3 + read-write + + + SNDLPM + Send LPM transaction + 24 + 1 + read-write + + + LPMRCNTSTS + LPM retry count status + 25 + 3 + read-only + + + ENBESL + Enable best effort service latency + 28 + 1 + read-write + + + + + DIEPTXF8 + OTG_HS device IN endpoint transmit FIFO size register + 0x120 + 0x20 + read-write + 0x02001200 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + OTG_HS_HOST + USB on the go high speed + USB_OTG_HS + 0x40040400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTG_HS host configuration register + 0x0 + 0x20 + 0x00000000 + + + FSLSPCS + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSS + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTG_HS Host frame interval register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRIVL + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTG_HS host frame number/frame time remaining register + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTG_HS_Host periodic transmit FIFO/queue status register + 0x10 + 0x20 + 0x00080100 + + + PTXFSAVL + Periodic transmit data FIFO space available + 0 + 16 + read-write + + + PTXQSAV + Periodic transmit request queue space available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTG_HS Host all channels interrupt register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTG_HS host all channels interrupt mask register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTM + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTG_HS host port control and status register + 0x40 + 0x20 + 0x00000000 + + + PCSTS + Port connect status + 0 + 1 + read-only + + + PCDET + Port connect detected + 1 + 1 + read-write + + + PENA + Port enable + 2 + 1 + read-write + + + PENCHNG + Port enable/disable change + 3 + 1 + read-write + + + POCA + Port overcurrent active + 4 + 1 + read-only + + + POCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRES + Port resume + 6 + 1 + read-write + + + PSUSP + Port suspend + 7 + 1 + read-write + + + PRST + Port reset + 8 + 1 + read-write + + + PLSTS + Port line status + 10 + 2 + read-only + + + PPWR + Port power + 12 + 1 + read-write + + + PTCTL + Port test control + 13 + 4 + read-write + + + PSPD + Port speed + 17 + 2 + read-only + + + + + 16 + 0x20 + 0-15 + HC%s + Host channel + 0x100 + + CHAR + HCCHAR0 + OTG_HS host channel-0 characteristics register + 0x0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + SPLT + HCSPLT0 + OTG_HS host channel-0 split control register + 0x4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + INT + HCINT0 + OTG_HS host channel-11 interrupt register + 0x8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received interrupt + 3 + 1 + + + NAK + NAK response received interrupt + 4 + 1 + + + ACK + ACK response received/transmitted interrupt + 5 + 1 + + + NYET + Response received interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + INTMSK + HCINTMSK0 + OTG_HS host channel-11 interrupt mask register + 0xC + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt mask + 3 + 1 + + + NAKM + NAK response received interrupt mask + 4 + 1 + + + ACKM + ACK response received/transmitted interrupt mask + 5 + 1 + + + NYET + response received interrupt mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + TSIZ + HCTSIZ0 + OTG_HS host channel-11 transfer size register + 0x10 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + DMA + HCDMA0 + OTG_HS host channel-0 DMA address register + 0x14 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + 0 + 32 + + + + + + + + OTG_HS_DEVICE + USB on the go high speed + USB_OTG_HS + 0x40040800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTG_HS device configuration register + 0x0 + 0x20 + read-write + 0x02200000 + + + DSPD + Device speed + 0 + 2 + + + NZLSOHSK + Nonzero-length status OUT handshake + 2 + 1 + + + DAD + Device address + 4 + 7 + + + PFIVL + Periodic (micro)frame interval + 11 + 2 + + + PERSCHIVL + Periodic scheduling interval + 24 + 2 + + + + + DCTL + DCTL + OTG_HS device control register + 0x4 + 0x20 + 0x00000000 + + + RWUSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SDIS + Soft disconnect + 1 + 1 + read-write + + + GINSTS + Global IN NAK status + 2 + 1 + read-only + + + GONSTS + Global OUT NAK status + 3 + 1 + read-only + + + TCTL + Test control + 4 + 3 + read-write + + + SGINAK + Set global IN NAK + 7 + 1 + write-only + + + CGINAK + Clear global IN NAK + 8 + 1 + write-only + + + SGONAK + Set global OUT NAK + 9 + 1 + write-only + + + CGONAK + Clear global OUT NAK + 10 + 1 + write-only + + + POPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTG_HS device status register + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + EERR + Erratic error + 3 + 1 + + + FNSOF + Frame number of the received SOF + 8 + 14 + + + + + DIEPMSK + DIEPMSK + OTG_HS device IN endpoint common interrupt mask register + 0x10 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt mask + 1 + 1 + + + TOM + Timeout condition mask (nonisochronous endpoints) + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective mask + 6 + 1 + + + TXFURM + FIFO underrun mask + 8 + 1 + + + BIM + BNA interrupt mask + 9 + 1 + + + + + DOEPMSK + DOEPMSK + OTG_HS device OUT endpoint common interrupt mask register + 0x14 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt mask + 1 + 1 + + + STUPM + SETUP phase done mask + 3 + 1 + + + OTEPDM + OUT token received when endpoint disabled mask + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets received mask + 6 + 1 + + + OPEM + OUT packet error mask + 8 + 1 + + + BOIM + BNA interrupt mask + 9 + 1 + + + + + DAINT + DAINT + OTG_HS device all endpoints interrupt register + 0x18 + 0x20 + read-only + 0x00000000 + + + IEPINT + IN endpoint interrupt bits + 0 + 16 + + + OEPINT + OUT endpoint interrupt bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTG_HS all endpoints interrupt mask register + 0x1C + 0x20 + read-write + 0x00000000 + + + IEPM + IN EP interrupt mask bits + 0 + 16 + + + OEPM + OUT EP interrupt mask bits + 16 + 16 + + + + + DVBUSDIS + DVBUSDIS + OTG_HS device VBUS discharge time register + 0x28 + 0x20 + read-write + 0x000017D7 + + + VBUSDT + Device VBUS discharge time + 0 + 16 + + + + + DVBUSPULSE + DVBUSPULSE + OTG_HS device VBUS pulsing time register + 0x2C + 0x20 + read-write + 0x000005B8 + + + DVBUSP + Device VBUS pulsing time + 0 + 12 + + + + + DTHRCTL + DTHRCTL + OTG_HS Device threshold control register + 0x30 + 0x20 + read-write + 0x00000000 + + + NONISOTHREN + Nonisochronous IN endpoints threshold enable + 0 + 1 + + + ISOTHREN + ISO IN endpoint threshold enable + 1 + 1 + + + TXTHRLEN + Transmit threshold length + 2 + 9 + + + RXTHREN + Receive threshold enable + 16 + 1 + + + RXTHRLEN + Receive threshold length + 17 + 9 + + + ARPEN + Arbiter parking enable + 27 + 1 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTG_HS device IN endpoint FIFO empty interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEM + IN EP Tx FIFO empty interrupt mask bits + 0 + 16 + + + + + DEACHINT + DEACHINT + OTG_HS device each endpoint interrupt register + 0x38 + 0x20 + read-write + 0x00000000 + + + IEP1INT + IN endpoint 1interrupt bit + 1 + 1 + + + OEP1INT + OUT endpoint 1 interrupt bit + 17 + 1 + + + + + DEACHINTMSK + DEACHINTMSK + OTG_HS device each endpoint interrupt register mask + 0x3C + 0x20 + read-write + 0x00000000 + + + IEP1INTM + IN Endpoint 1 interrupt mask bit + 1 + 1 + + + OEP1INTM + OUT Endpoint 1 interrupt mask bit + 17 + 1 + + + + + DIEP0 + Device IN endpoint 0 + 0x100 + + CTL + DIEPCTL0 + OTG device endpoint-0 control register + 0x0 + 0x20 + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + INT + DIEPINT0 + OTG device endpoint-0 interrupt register + 0x8 + 0x20 + 0x00000080 + + + XFRC + Transfer completed interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + TSIZ + DIEPTSIZ0 + OTG_HS device IN endpoint 0 transfer size register + 0x10 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + DMA + OTG_HS device endpoint-0 DMA address register + 0x14 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + 0 + 32 + + + + + TXFSTS + DTXFSTS0 + OTG_HS device IN endpoint transmit FIFO status register + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space avail + 0 + 16 + + + + + + 8 + 0x20 + 1-8 + DIEP%s + Device IN endpoint X + 0x120 + + CTL + DIEPCTL1 + OTG device endpoint-1 control register + 0x0 + 0x20 + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + INT + DIEPINT1 + OTG device endpoint-1 interrupt register + 0x8 + 0x20 + 0x00000000 + + + XFRC + Transfer completed interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + TSIZ + DIEPTSIZ1 + OTG_HS device endpoint transfer size register + 0x10 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + DMA + DIEPDMA1 + OTG_HS device endpoint-1 DMA address register + 0x14 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + 0 + 32 + + + + + TXFSTS + DTXFSTS1 + OTG_HS device IN endpoint transmit FIFO status register + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space avail + 0 + 16 + + + + + + DOEP0 + Device OUT endpoint 0 + 0x300 + + CTL + DOEPCTL0 + OTG_HS device control OUT endpoint 0 control register + 0x0 + 0x20 + 0x00008000 + + + MPSIZ + Maximum packet size + 0 + 2 + read-only + + + USBAEP + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-only + + + SNPM + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-only + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + INT + DOEPINT0 + OTG_HS device endpoint-0 interrupt register + 0x8 + 0x20 + read-write + 0x00000080 + + + XFRC + Transfer completed interrupt + 0 + 1 + + + EPDISD + Endpoint disabled interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + TSIZ + DOEPTSIZ0 + OTG_HS device endpoint-0 transfer size register + 0x10 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + STUPCNT + SETUP packet count + 29 + 2 + + + + + DMA + OTG_HS device endpoint-0 DMA address register + 0x14 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + 0 + 32 + + + + + + 8 + 0x20 + 1-8 + DOEP%s + Device IN endpoint X + 0x320 + + CTL + DOEPCTL1 + OTG device endpoint-1 control register + 0x0 + 0x20 + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + INT + DOEPINT1 + OTG_HS device endpoint-1 interrupt register + 0x8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed interrupt + 0 + 1 + + + EPDISD + Endpoint disabled interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + DMA + OTG_HS device endpoint-1 DMA address register + 0x14 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA address + 0 + 32 + + + + + TSIZ + DOEPTSIZ1 + OTG_HS device endpoint-1 transfer size register + 0x10 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet count + 29 + 2 + + + + + + DIEPEACHMSK1 + 0x44 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt mask + 1 + 1 + + + AHBERRM + AHB error mask + 2 + 1 + + + TOM + Timeout condition mask (Non-isochronous endpoints) + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty mask + 4 + 1 + + + INEPNEM + IN endpoint NAK effective mask + 6 + 1 + + + TXFURM + FIFO underrun mask + 8 + 1 + + + BNAM + BNA interrupt mask + 9 + 1 + + + NAKM + NAK interrupt mask + 13 + 1 + + + + + DOEPEACHMSK1 + 0x84 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt mask + 1 + 1 + + + AHBERRM + AHB error mask + 2 + 1 + + + STUPM + SETUP phase done mask + 3 + 1 + + + OTEPDM + OUT token received when endpoint disabled mask + 4 + 1 + + + B2BSTUPM + Back-to-back SETUP packets received mask + 6 + 1 + + + OUTPKTERRM + Out packet error mask + 8 + 1 + + + BNAM + BNA interrupt mask + 9 + 1 + + + BERRM + Babble error interrupt mask + 12 + 1 + + + NAKMSK + NAK interrupt mask + 13 + 1 + + + NYETMSK + NYET interrupt mask + 14 + 1 + + + + + + + OTG_HS_PWRCLK + USB on the go high speed + USB_OTG_HS + 0x40040E00 + + 0x0 + 0x3F200 + registers + + + OTG_HS_EP1_OUT + USB On The Go HS End Point 1 Out global + interrupt + 74 + + + OTG_HS_EP1_IN + USB On The Go HS End Point 1 In global + interrupt + 75 + + + OTG_HS_WKUP + USB On The Go HS Wakeup through EXTI + interrupt + 76 + + + OTG_HS + USB On The Go HS global + interrupt + 77 + + + + PCGCR + PCGCR + Power and clock gating control register + 0x0 + 0x20 + read-write + 0x00000000 + + + STPPCLK + Stop PHY clock + 0 + 1 + + + GATEHCLK + Gate HCLK + 1 + 1 + + + PHYSUSP + PHY suspended + 4 + 1 + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + 0xE000E100 + + 0x0 + 0x369 + registers + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x0 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x4 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER2 + ISER2 + Interrupt Set-Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable Register + 0x80 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable Register + 0x84 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER2 + ICER2 + Interrupt Clear-Enable Register + 0x88 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR2 + ISPR2 + Interrupt Set-Pending Register + 0x108 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR2 + ICPR2 + Interrupt Clear-Pending Register + 0x188 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x200 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x204 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR2 + IABR2 + Interrupt Active Bit Register + 0x208 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x300 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x304 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x308 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x30C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x310 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x314 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x318 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x31C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x320 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x324 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x328 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x32C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x330 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x334 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x338 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR15 + IPR15 + Interrupt Priority Register + 0x33C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR16 + IPR16 + Interrupt Priority Register + 0x340 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR17 + IPR17 + Interrupt Priority Register + 0x344 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR18 + IPR18 + Interrupt Priority Register + 0x348 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR19 + IPR19 + Interrupt Priority Register + 0x34C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR20 + IPR20 + Interrupt Priority Register + 0x350 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR21 + IPR21 + Interrupt Priority Register + 0x354 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR22 + IPR22 + Interrupt Priority Register + 0x358 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR23 + IPR23 + Interrupt Priority Register + 0x35C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR24 + IPR24 + Interrupt Priority Register + 0x360 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR25 + IPR25 + Interrupt Priority Register + 0x364 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + MPU + Memory protection unit + MPU + 0xE000ED90 + + 0x0 + 0x15 + registers + + + + TYPER + TYPER + MPU type register + 0x0 + 0x20 + read-only + 0x00000800 + + + SEPARATE + Separate flag + 0 + 1 + + + DREGION + Number of MPU data regions + 8 + 8 + + + IREGION + Number of MPU instruction regions + 16 + 8 + + + + + CTRL + CTRL + MPU control register + 0x4 + 0x20 + read-only + 0x00000000 + + + ENABLE + Enables the MPU + 0 + 1 + + + HFNMIENA + Enables the operation of MPU during hard fault + 1 + 1 + + + PRIVDEFENA + Enable priviliged software access to default memory map + 2 + 1 + + + + + RNR + RNR + MPU region number register + 0x8 + 0x20 + read-write + 0x00000000 + + + REGION + MPU region + 0 + 8 + + + + + RBAR + RBAR + MPU region base address register + 0xC + 0x20 + read-write + 0x00000000 + + + REGION + MPU region field + 0 + 4 + + + VALID + MPU region number valid + 4 + 1 + + + ADDR + Region base address field + 5 + 27 + + + + + RASR + RASR + MPU region attribute and size register + 0x10 + 0x20 + read-write + 0x00000000 + + + ENABLE + Region enable bit. + 0 + 1 + + + SIZE + Size of the MPU protection region + 1 + 5 + + + SRD + Subregion disable bits + 8 + 8 + + + B + memory attribute + 16 + 1 + + + C + memory attribute + 17 + 1 + + + S + Shareable memory attribute + 18 + 1 + + + TEX + memory attribute + 19 + 3 + + + AP + Access permission + 24 + 3 + + + XN + Instruction access disable bit + 28 + 1 + + + + + + + STK + SysTick timer + STK + 0xE000E010 + + 0x0 + 0x11 + registers + + + + CSR + CSR + SysTick control and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + ENABLE + Counter enable + 0 + 1 + + + TICKINT + SysTick exception request enable + 1 + 1 + + + CLKSOURCE + Clock source selection + 2 + 1 + + + COUNTFLAG + COUNTFLAG + 16 + 1 + + + + + RVR + RVR + SysTick reload value register + 0x4 + 0x20 + read-write + 0x00000000 + + + RELOAD + RELOAD value + 0 + 24 + + + + + CVR + CVR + SysTick current value register + 0x8 + 0x20 + read-write + 0x00000000 + + + CURRENT + Current counter value + 0 + 24 + + + + + CALIB + CALIB + SysTick calibration value register + 0xC + 0x20 + read-write + 0x00000000 + + + TENMS + Calibration value + 0 + 24 + + + SKEW + SKEW flag: Indicates whether the TENMS value is exact + 30 + 1 + + + NOREF + NOREF flag. Reads as zero + 31 + 1 + + + + + + + NVIC_STIR + Nested vectored interrupt controller + NVIC + 0xE000EF00 + + 0x0 + 0x5 + registers + + + + STIR + STIR + Software trigger interrupt register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTID + Software generated interrupt ID + 0 + 9 + + + + + + + FPU_CPACR + Floating point unit CPACR + FPU + 0xE000ED88 + + 0x0 + 0x5 + registers + + + + CPACR + CPACR + Coprocessor access control register + 0x0 + 0x20 + read-write + 0x00000000 + + + CP + CP + 20 + 4 + + + + + + + SCB_ACTRL + System control block ACTLR + SCB + 0xE000E008 + + 0x0 + 0x5 + registers + + + + ACTRL + ACTRL + Auxiliary control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DISFOLD + DISFOLD + 2 + 1 + + + FPEXCODIS + FPEXCODIS + 10 + 1 + + + DISRAMODE + DISRAMODE + 11 + 1 + + + DISITMATBFLUSH + DISITMATBFLUSH + 12 + 1 + + + + + + + FPU + Floting point unit + FPU + 0xE000EF34 + + 0x0 + 0xD + registers + + + FPU + Floating point unit interrupt + 81 + + + + FPCCR + FPCCR + Floating-point context control register + 0x0 + 0x20 + read-write + 0x00000000 + + + LSPACT + LSPACT + 0 + 1 + + + USER + USER + 1 + 1 + + + THREAD + THREAD + 3 + 1 + + + HFRDY + HFRDY + 4 + 1 + + + MMRDY + MMRDY + 5 + 1 + + + BFRDY + BFRDY + 6 + 1 + + + MONRDY + MONRDY + 8 + 1 + + + LSPEN + LSPEN + 30 + 1 + + + ASPEN + ASPEN + 31 + 1 + + + + + FPCAR + FPCAR + Floating-point context address register + 0x4 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Location of unpopulated floating-point + 3 + 29 + + + + + FPSCR + FPSCR + Floating-point status control register + 0x8 + 0x20 + read-write + 0x00000000 + + + IOC + Invalid operation cumulative exception bit + 0 + 1 + + + DZC + Division by zero cumulative exception bit. + 1 + 1 + + + OFC + Overflow cumulative exception bit + 2 + 1 + + + UFC + Underflow cumulative exception bit + 3 + 1 + + + IXC + Inexact cumulative exception bit + 4 + 1 + + + IDC + Input denormal cumulative exception bit. + 7 + 1 + + + RMode + Rounding Mode control field + 22 + 2 + + + FZ + Flush-to-zero mode control bit: + 24 + 1 + + + DN + Default NaN mode control bit + 25 + 1 + + + AHP + Alternative half-precision control bit + 26 + 1 + + + V + Overflow condition code flag + 28 + 1 + + + C + Carry condition code flag + 29 + 1 + + + Z + Zero condition code flag + 30 + 1 + + + N + Negative condition code flag + 31 + 1 + + + + + + + SCB + System control block + SCB + 0xE000ED00 + + 0x0 + 0x41 + registers + + + + CPUID + CPUID + CPUID base register + 0x0 + 0x20 + read-only + 0x410FC241 + + + Revision + Revision number + 0 + 4 + + + PartNo + Part number of the processor + 4 + 12 + + + Constant + Reads as 0xF + 16 + 4 + + + Variant + Variant number + 20 + 4 + + + Implementer + Implementer code + 24 + 8 + + + + + ICSR + ICSR + Interrupt control and state register + 0x4 + 0x20 + read-write + 0x00000000 + + + VECTACTIVE + Active vector + 0 + 9 + + + RETTOBASE + Return to base level + 11 + 1 + + + VECTPENDING + Pending vector + 12 + 7 + + + ISRPENDING + Interrupt pending flag + 22 + 1 + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + + NMIPENDSET + NMI set-pending bit. + 31 + 1 + + + + + VTOR + VTOR + Vector table offset register + 0x8 + 0x20 + read-write + 0x00000000 + + + TBLOFF + Vector table base offset field + 9 + 21 + + + + + AIRCR + AIRCR + Application interrupt and reset control register + 0xC + 0x20 + read-write + 0x00000000 + + + VECTRESET + VECTRESET + 0 + 1 + + + VECTCLRACTIVE + VECTCLRACTIVE + 1 + 1 + + + SYSRESETREQ + SYSRESETREQ + 2 + 1 + + + PRIGROUP + PRIGROUP + 8 + 3 + + + ENDIANESS + ENDIANESS + 15 + 1 + + + VECTKEYSTAT + Register key + 16 + 16 + + + + + SCR + SCR + System control register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLEEPONEXIT + SLEEPONEXIT + 1 + 1 + + + SLEEPDEEP + SLEEPDEEP + 2 + 1 + + + SEVEONPEND + Send Event on Pending bit + 4 + 1 + + + + + CCR + CCR + Configuration and control register + 0x14 + 0x20 + read-write + 0x00000000 + + + NONBASETHRDENA + Configures how the processor enters Thread mode + 0 + 1 + + + USERSETMPEND + USERSETMPEND + 1 + 1 + + + UNALIGN__TRP + UNALIGN_ TRP + 3 + 1 + + + DIV_0_TRP + DIV_0_TRP + 4 + 1 + + + BFHFNMIGN + BFHFNMIGN + 8 + 1 + + + STKALIGN + STKALIGN + 9 + 1 + + + DC + DC + 16 + 1 + + + IC + IC + 17 + 1 + + + BP + BP + 18 + 1 + + + + + SHPR1 + SHPR1 + System handler priority registers + 0x18 + 0x20 + read-write + 0x00000000 + + + PRI_4 + Priority of system handler 4 + 0 + 8 + + + PRI_5 + Priority of system handler 5 + 8 + 8 + + + PRI_6 + Priority of system handler 6 + 16 + 8 + + + + + SHPR2 + SHPR2 + System handler priority registers + 0x1C + 0x20 + read-write + 0x00000000 + + + PRI_11 + Priority of system handler 11 + 24 + 8 + + + + + SHPR3 + SHPR3 + System handler priority registers + 0x20 + 0x20 + read-write + 0x00000000 + + + PRI_14 + Priority of system handler 14 + 16 + 8 + + + PRI_15 + Priority of system handler 15 + 24 + 8 + + + + + SHCRS + SHCRS + System handler control and state register + 0x24 + 0x20 + read-write + 0x00000000 + + + MEMFAULTACT + Memory management fault exception active bit + 0 + 1 + + + BUSFAULTACT + Bus fault exception active bit + 1 + 1 + + + USGFAULTACT + Usage fault exception active bit + 3 + 1 + + + SVCALLACT + SVC call active bit + 7 + 1 + + + MONITORACT + Debug monitor active bit + 8 + 1 + + + PENDSVACT + PendSV exception active bit + 10 + 1 + + + SYSTICKACT + SysTick exception active bit + 11 + 1 + + + USGFAULTPENDED + Usage fault exception pending bit + 12 + 1 + + + MEMFAULTPENDED + Memory management fault exception pending bit + 13 + 1 + + + BUSFAULTPENDED + Bus fault exception pending bit + 14 + 1 + + + SVCALLPENDED + SVC call pending bit + 15 + 1 + + + MEMFAULTENA + Memory management fault enable bit + 16 + 1 + + + BUSFAULTENA + Bus fault enable bit + 17 + 1 + + + USGFAULTENA + Usage fault enable bit + 18 + 1 + + + + + CFSR_UFSR_BFSR_MMFSR + CFSR_UFSR_BFSR_MMFSR + Configurable fault status register + 0x28 + 0x20 + read-write + 0x00000000 + + + IACCVIOL + IACCVIOL + 0 + 1 + + + DACCVIOL + DACCVIOL + 1 + 1 + + + MUNSTKERR + MUNSTKERR + 3 + 1 + + + MSTKERR + MSTKERR + 4 + 1 + + + MLSPERR + MLSPERR + 5 + 1 + + + MMARVALID + MMARVALID + 7 + 1 + + + IBUSERR + Instruction bus error + 8 + 1 + + + PRECISERR + Precise data bus error + 9 + 1 + + + IMPRECISERR + Imprecise data bus error + 10 + 1 + + + UNSTKERR + Bus fault on unstacking for a return from exception + 11 + 1 + + + STKERR + Bus fault on stacking for exception entry + 12 + 1 + + + LSPERR + Bus fault on floating-point lazy state preservation + 13 + 1 + + + BFARVALID + Bus Fault Address Register (BFAR) valid flag + 15 + 1 + + + UNDEFINSTR + Undefined instruction usage fault + 16 + 1 + + + INVSTATE + Invalid state usage fault + 17 + 1 + + + INVPC + Invalid PC load usage fault + 18 + 1 + + + NOCP + No coprocessor usage fault. + 19 + 1 + + + UNALIGNED + Unaligned access usage fault + 24 + 1 + + + DIVBYZERO + Divide by zero usage fault + 25 + 1 + + + + + HFSR + HFSR + Hard fault status register + 0x2C + 0x20 + read-write + 0x00000000 + + + VECTTBL + Vector table hard fault + 1 + 1 + + + FORCED + Forced hard fault + 30 + 1 + + + DEBUG_VT + Reserved for Debug use + 31 + 1 + + + + + MMFAR + MMFAR + Memory management fault address register + 0x34 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Memory management fault address + 0 + 32 + + + + + BFAR + BFAR + Bus fault address register + 0x38 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Bus fault address + 0 + 32 + + + + + + + PF + Processor features + PF + 0xE000ED78 + + 0x0 + 0xD + registers + + + + CLIDR + CLIDR + Cache Level ID register + 0x0 + 0x20 + read-only + 0x09000003 + + + CL1 + CL1 + 0 + 3 + + + CL2 + CL2 + 3 + 3 + + + CL3 + CL3 + 6 + 3 + + + CL4 + CL4 + 9 + 3 + + + CL5 + CL5 + 12 + 3 + + + CL6 + CL6 + 15 + 3 + + + CL7 + CL7 + 18 + 3 + + + LoUIS + LoUIS + 21 + 3 + + + LoC + LoC + 24 + 3 + + + LoU + LoU + 27 + 3 + + + + + CTR + CTR + Cache Type register + 0x4 + 0x20 + read-only + 0x8303C003 + + + _IminLine + IminLine + 0 + 4 + + + DMinLine + DMinLine + 16 + 4 + + + ERG + ERG + 20 + 4 + + + CWG + CWG + 24 + 4 + + + Format + Format + 29 + 3 + + + + + CCSIDR + CCSIDR + Cache Size ID register + 0x8 + 0x20 + read-only + 0x00000000 + + + LineSize + LineSize + 0 + 3 + + + Associativity + Associativity + 3 + 10 + + + NumSets + NumSets + 13 + 15 + + + WA + WA + 28 + 1 + + + RA + RA + 29 + 1 + + + WB + WB + 30 + 1 + + + WT + WT + 31 + 1 + + + + + + + AC + Access control + AC + 0xE000EF90 + + 0x0 + 0x1D + registers + + + + ITCMCR + ITCMCR + Instruction and Data Tightly-Coupled Memory Control Registers + 0x0 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 1 + + + RMW + RMW + 1 + 1 + + + RETEN + RETEN + 2 + 1 + + + SZ + SZ + 3 + 4 + + + + + DTCMCR + DTCMCR + Instruction and Data Tightly-Coupled Memory Control Registers + 0x4 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 1 + + + RMW + RMW + 1 + 1 + + + RETEN + RETEN + 2 + 1 + + + SZ + SZ + 3 + 4 + + + + + AHBPCR + AHBPCR + AHBP Control register + 0x8 + 0x20 + read-write + 0x00000000 + + + EN + EN + 0 + 1 + + + SZ + SZ + 1 + 3 + + + + + CACR + CACR + Auxiliary Cache Control register + 0xC + 0x20 + read-write + 0x00000000 + + + SIWT + SIWT + 0 + 1 + + + ECCEN + ECCEN + 1 + 1 + + + FORCEWT + FORCEWT + 2 + 1 + + + + + AHBSCR + AHBSCR + AHB Slave Control register + 0x10 + 0x20 + read-write + 0x00000000 + + + CTL + CTL + 0 + 2 + + + TPRI + TPRI + 2 + 9 + + + INITCOUNT + INITCOUNT + 11 + 5 + + + + + ABFSR + ABFSR + Auxiliary Bus Fault Status register + 0x18 + 0x20 + read-write + 0x00000000 + + + ITCM + ITCM + 0 + 1 + + + DTCM + DTCM + 1 + 1 + + + AHBP + AHBP + 2 + 1 + + + AXIM + AXIM + 3 + 1 + + + EPPB + EPPB + 4 + 1 + + + AXIMTYPE + AXIMTYPE + 8 + 2 + + + + + + + \ No newline at end of file diff --git a/Tools/Toolsets/stm32f74x.json b/Tools/Toolsets/stm32f74x.json new file mode 100644 index 00000000..1dc368ac --- /dev/null +++ b/Tools/Toolsets/stm32f74x.json @@ -0,0 +1,25 @@ +{ + "schemaVersion": "1.0", + "swiftCompiler": { + "extraCLIOptions": [ + "-Xcc", "-D__APPLE__", + "-Xcc", "-D__MACH__", + "-Xfrontend", "-disable-stack-protector", + "-enable-experimental-feature", "Embedded" + ] + }, + "linker": { + "extraCLIOptions": [ + "-arch", "armv7em", + "-dead_strip", + "-static", + "-e", "_reset", + "-no_zero_fill_sections", + "-segalign", "4", + "-segaddr", "__VECTORS", "0x20010000", + "-seg1addr", "0x20010200", + "-pagezero_size", "0", + "-allow_dead_duplicates" + ] + } +} diff --git a/stm32-neopixel/Makefile b/stm32-neopixel/Makefile index 60845a91..51885ce5 100755 --- a/stm32-neopixel/Makefile +++ b/stm32-neopixel/Makefile @@ -9,42 +9,30 @@ ## ##===----------------------------------------------------------------------===## -# Determine file paths -REPOROOT := $(shell git rev-parse --show-toplevel) -TOOLSROOT := $(REPOROOT)/Tools -SRCROOT := $(REPOROOT)/stm32-neopixel -BUILDROOT := $(SRCROOT)/.build/release - -# Setup tools and build flags -ARCH := armv7em -TARGET := $(ARCH)-apple-none-macho -VECTORS_ADDRESS=-0x00200000 - -SWIFT_BUILD := $(shell xcrun -f swift-build) -MACHO2BIN := $(SRCROOT)/../Tools/macho2bin.py +# Paths +REPOROOT := $(shell git rev-parse --show-toplevel) +TOOLSROOT := $(REPOROOT)/Tools +TOOLSET := $(TOOLSROOT)/Toolsets/stm32f74x.json +MACHO2BIN := $(TOOLSROOT)/macho2bin.py +SWIFT_BUILD := swift build + +# Flags +ARCH := armv7em +TARGET := $(ARCH)-apple-none-macho +SWIFT_BUILD_ARGS := \ + --configuration release \ + --triple $(TARGET) \ + --toolset $(TOOLSET) \ + --disable-local-rpath +BUILDROOT := $(shell $(SWIFT_BUILD) $(SWIFT_BUILD_ARGS) --show-bin-path) .PHONY: build build: - @echo "compiling..." + @echo "building..." $(SWIFT_BUILD) \ - --configuration release \ - --verbose \ - --triple $(TARGET) \ - -Xcc -D__APPLE__ -Xcc -D__MACH__ \ - -Xswiftc -Xfrontend -Xswiftc -disable-stack-protector - - @echo "linking..." - clang .build/release/libApplication.a -o .build/release/Application \ - -arch $(ARCH) \ - -dead_strip \ - -static \ - -Wl,-e,_reset \ - -Wl,-map,$(BUILDROOT)/Application.mangled.map \ - -Wl,-no_zero_fill_sections \ - -Wl,-segalign,4 \ - -Wl,-segaddr,__VECTORS,0x20010000 \ - -Wl,-seg1addr,0x20010200 \ - -Wl,-pagezero_size,0 + $(SWIFT_BUILD_ARGS) \ + -Xlinker -map -Xlinker $(BUILDROOT)/Application.mangled.map \ + --verbose @echo "demangling linker map..." cat $(BUILDROOT)/Application.mangled.map \ diff --git a/stm32-neopixel/Package.resolved b/stm32-neopixel/Package.resolved index aa9ec369..d7e51efb 100644 --- a/stm32-neopixel/Package.resolved +++ b/stm32-neopixel/Package.resolved @@ -1,13 +1,13 @@ { - "originHash" : "c23a233e350eb87b64e1d6f65aeedeb84fdc86c7edd481dd3dae915017d8ac6f", + "originHash" : "1e5ddc29279ed8df40c89e2aa6c1b16483a597824c05a9e88d3e1b8e4607db39", "pins" : [ { "identity" : "swift-argument-parser", "kind" : "remoteSourceControl", "location" : "https://github.com/apple/swift-argument-parser.git", "state" : { - "revision" : "0fbc8848e389af3bb55c182bc19ca9d5dc2f255b", - "version" : "1.4.0" + "revision" : "41982a3656a71c768319979febd796c6fd111d5c", + "version" : "1.5.0" } }, { @@ -15,8 +15,8 @@ "kind" : "remoteSourceControl", "location" : "https://github.com/apple/swift-mmio", "state" : { - "branch" : "swift-embedded-examples", - "revision" : "06d96ed4916739f2edafde87f3951b2d2a04df65" + "branch" : "main", + "revision" : "daf25ecacc0d9b71036c6af32cb7786a01802799" } }, { diff --git a/stm32-neopixel/Package.swift b/stm32-neopixel/Package.swift index 77236624..e909758e 100644 --- a/stm32-neopixel/Package.swift +++ b/stm32-neopixel/Package.swift @@ -1,4 +1,4 @@ -// swift-tools-version: 5.10 +// swift-tools-version: 6.2 import PackageDescription @@ -8,22 +8,22 @@ let package = Package( .macOS(.v10_15) ], products: [ - .library(name: "Application", type: .static, targets: ["Application"]) + .executable(name: "Application", targets: ["Application"]) ], dependencies: [ - .package( - url: "https://github.com/apple/swift-mmio", - branch: "swift-embedded-examples") + .package(url: "https://github.com/apple/swift-mmio", branch: "main") ], targets: [ - .target( + // SVD2Swift \ + // -i ../Tools/SVDs/stm32f7x6.patched.svd \ + // -o Sources/Application/Registers \ + // --indentation-width 2 \ + // -p DMA1 DMA2 GPIOA GPIOB GPIOI RCC SPI1 SPI2 USART1 + .executableTarget( name: "Application", dependencies: [ .product(name: "MMIO", package: "swift-mmio"), "Support", - ], - swiftSettings: [ - .enableExperimentalFeature("Embedded") ]), .target(name: "Support"), ]) diff --git a/stm32-neopixel/Sources/Application/Application.swift b/stm32-neopixel/Sources/Application/Application.swift index 3a554ac7..93ea5a40 100644 --- a/stm32-neopixel/Sources/Application/Application.swift +++ b/stm32-neopixel/Sources/Application/Application.swift @@ -24,23 +24,23 @@ public struct Application { rcc.cr.modify { $1.raw.pllon = 0 } // Configure UART to always use HSI. - rcc.dkcfgr2.modify { $0.raw.usart1sel = 0b10 } + rcc.dckcfgr2.modify { $0.usart1sel = .HSI } // Configure PLL to convert the 16MHz HSI to a 12.8MHz SYSCLK. // HSI is measured to be closer to 16.6Mhz on my device. // The SPI bus must run at 6.4MHz which is achieved with a /2 prescalar. - let pllM: UInt8 = 10 - let pllN: UInt8 = 64 - let pllP: UInt8 = 0b11 // maps to 8 - // ((16MHz / M) * N) / P = 12.8MHz + // M = 10 + // N = 64 + // P = 8 + // ((16MHz / M ) * N) / P = 12.8MHz rcc.pllcfgr.modify { rw in // Clear all non-reserved registers. rw.raw.storage &= 0b1111_0000_1011_1100__1000_0000_0000_0000 - rw.raw.storage |= UInt32(pllM) << 0 // Set M constant - rw.raw.storage |= UInt32(pllN) << 6 // Set N constant - rw.raw.storage |= UInt32(pllP) << 16 // Set P constant - rw.raw.storage |= UInt32(0) << 22 // Select HSI PLL Source + rw.raw.pllm = 10 // Set M constant + rw.raw.plln = 64 // Set N constant + rw.pllp = .Div8 // Set P constant + rw.pllsrc = .HSI // Select HSI PLL Source } // Enable the PLL clock and wait for ready. @@ -48,18 +48,13 @@ public struct Application { while rcc.cr.read().raw.pllrdy != 1 {} // Change the SYSCLK mux to select the PLL clock and wait for ready. - rcc.cfgr.modify { _, w in - w.raw.sw0 = 0 // Select PLL clock low. - w.raw.sw1 = 1 // Select PLL clock high. - w.raw.hpre = 0 // system clock not divided - w.raw.ppre1 = 0 // AHB clock not divided - w.raw.ppre2 = 0 // AHB clock not divided - } - - while true { - let cfgr = rcc.cfgr.read().raw - if cfgr.sws0 == 0 && cfgr.sws1 == 1 { break } + rcc.cfgr.modify { rw in + rw.raw.sw = 0b10 // Select PLL clock. + rw.raw.hpre = 0 // system clock not divided + rw.raw.ppre1 = 0 // AHB clock not divided + rw.raw.ppre2 = 0 // AHB clock not divided } + while rcc.cfgr.read().raw.sws != 0b10 {} // DMA rcc.ahb1enr.modify { $0.raw.dma1en = 1 } @@ -112,11 +107,11 @@ public struct Application { alternateFunction: 7)) // UART configuration - usart1.brr.modify { $0.raw.storage = 16_000_000 / 115200 } + usart1.brr.modify { $0.raw.brr_field = 16_000_000 / 115200 } usart1.cr1.modify { rw in - rw.raw.ue = 1 - rw.raw.re = 1 - rw.raw.te = 1 + rw.ue = .Enabled + rw.re = .Enabled + rw.te = .Enabled } // MARK: Main loop diff --git a/stm32-neopixel/Sources/Application/Neopixel/SPINeoPixel.swift b/stm32-neopixel/Sources/Application/Neopixel/SPINeoPixel.swift index 8901d64d..98eee592 100644 --- a/stm32-neopixel/Sources/Application/Neopixel/SPINeoPixel.swift +++ b/stm32-neopixel/Sources/Application/Neopixel/SPINeoPixel.swift @@ -70,66 +70,71 @@ extension SPINeoPixel { let count = UInt32( self.pixels.buffer.count * MemoryLayout.size) - self.dma.s4cr.modify { rw in + let index = 4 + self.dma.st[index].cr.modify { rw in rw.raw.chsel = 0 // Set the DMA channel to 0 (spi tx). - rw.raw.pfctrl = 0 // Set the DMA as the flow controller. - rw.raw.pl = 0b11 // Set the stream priority to Very High. - rw.raw.dir = 0b01 // Set memory to peripheral transfer direction. - rw.raw.pinc = 0 // Set peripheral to fixed (no-increment) mode. - rw.raw.minc = 1 // Set memory to incremented mode. - rw.raw.pburst = 0b00 // Set peripheral to single transaction mode. rw.raw.mburst = 0b00 // Set memory to single transaction mode. - rw.raw.psize = 0b00 // Set peripheral data width to 8 bit. + rw.pburst = .Single // Set peripheral to single transaction mode. + // ct + rw.dbm = .Disabled // Disable double buffer mode. + rw.pl = .VeryHigh // Set the stream priority to very high. + // pincos rw.raw.msize = 0b00 // Set memory data width to 8 bit. - rw.raw.circ = 0 // Disable circular mode. - rw.raw.dbm = 0 // Disable double buffer mode. - rw.raw.tcie = 1 // Enable transfer complete interrupt. - rw.raw.htie = 1 // Enable half transfer interrupt. - rw.raw.teie = 1 // Enable transfer error interrupt. - rw.raw.dmeie = 1 // Enable direct mode error interrupt. + rw.psize = .Bits8 // Set peripheral data width to 8 bit. + rw.raw.minc = 1 // Set memory to incremented mode. + rw.pinc = .Fixed // Set peripheral to fixed (no-increment) mode. + rw.circ = .Disabled // Disable circular mode. + rw.dir = .MemoryToPeripheral // Set transfer direction. + rw.pfctrl = .DMA // Set the DMA as the flow controller. + rw.tcie = .Enabled // Enable transfer complete interrupt. + rw.htie = .Enabled // Enable half transfer interrupt. + rw.teie = .Enabled // Enable transfer error interrupt. + rw.dmeie = .Enabled // Enable direct mode error interrupt. } // Set the total number of data items to the buffer size. - self.dma.s4ndtr.modify { $0.raw.ndt = UInt32(count) } + self.dma.st[index].ndtr.modify { $0.raw.ndt = UInt32(count) } // Set the destination peripheral port address to the spi data port. - self.dma.s4par.modify { $0.raw.pa = peripheral } + self.dma.st[index].par.modify { $0.raw.pa = peripheral } // Set the source memory address to the buffer's base. - self.dma.s4m0ar.modify { $0.raw.m0a = memory } + self.dma.st[index].m0ar.modify { $0.raw.m0a = memory } // Clear the second memory address as double buffering mode is disabled. - self.dma.s4m1ar.modify { $0.raw.m1a = 0 } + self.dma.st[index].m1ar.modify { $0.raw.m1a = 0 } - self.dma.s4fcr.modify { _, w in - w.raw.feie = 1 // Enable FIFO error interrupt. - w.raw.dmdis = 0 // Enable direct mode (double negative). - w.raw.fth = 0b00 // Reset FIFO threshold (no effect in direct mode). + self.dma.st[index].fcr.modify { _, w in + w.feie = .Enabled // Enable FIFO error interrupt. + w.dmdis = .Disabled // Enable direct mode (double negative). + w.fth = .Quarter // Reset FIFO threshold (no effect in direct mode). } - self.dma.hifcr.modify { rw in - rw.raw.ctcif4 = 1 // Clear transfer complete interrupt flag. - rw.raw.chtif4 = 1 // Clear half transfer interrupt flag. - rw.raw.cteif4 = 1 // Clear transfer error interrupt flag. - rw.raw.cdmeif4 = 1 // Clear direct mode error interrupt flag. - rw.raw.cfeif4 = 1 // Clear FIFO error interrupt flag. + self.dma.hifcr.modify { _, w in + w.raw.ctcif4 = 1 // Clear transfer complete interrupt flag. + w.raw.chtif4 = 1 // Clear half transfer interrupt flag. + w.raw.cteif4 = 1 // Clear transfer error interrupt flag. + w.raw.cdmeif4 = 1 // Clear direct mode error interrupt flag. + w.raw.cfeif4 = 1 // Clear FIFO error interrupt flag. } self.spi.cr1.modify { rw in - rw.raw.bidimode = 0 // Set full duplex. - rw.raw.bidioe = 0 - rw.raw.crcen = 0 // Disable hardware crc. - rw.raw.crcnext = 0 - rw.raw.crcl = 0 - rw.raw.rxonly = 0 // Set full duplex. + rw.bidimode = .Unidirectional // Set full duplex. + rw.bidioe = .OutputDisabled + rw.crcen = .Disabled // Disable hardware crc. + rw.crcnext = .TxBuffer + rw.crcl = .EightBit + rw.rxonly = .FullDuplex // Set full duplex. // FIXME: understand this Disable software slave management and select. - rw.raw.ssm = 1 - rw.raw.ssi = 1 - rw.raw.lsbfirst = 0 // Set data MSB first. - rw.raw.br = 0b000 // Set Baud Rate as Fpclk/2. - rw.raw.mstr = 1 // Set Master mode. - rw.raw.cpol = 0 // Set active high logic. - rw.raw.cpha = 1 // FIXME: understand this Set trailing edge logic. + rw.ssm = .Enabled + rw.ssi = .SlaveNotSelected + rw.lsbfirst = .MSBFirst // Set data MSB first. + // spe + rw.br = .Div2 // Set Baud Rate as Fpclk/2. + rw.mstr = .Master // Set Master mode. + rw.cpol = .IdleLow // Set active high logic. + // FIXME: understand this Set trailing edge logic. + rw.cpha = .SecondEdge } // Write to SPI_CR2 register: @@ -144,25 +149,27 @@ extension SPINeoPixel { // f) Initialize LDMA_TX and LDMA_RX bits if DMA is used in packed mode. self.spi.cr2.modify { rw in - rw.raw.ldma_tx = 0 // Reset dma transmission length. - rw.raw.ldma_rx = 0 // Reset dma reception length. - rw.raw.frxth = 1 // Set RXNE if FIFO <8 bits. - rw.raw.ds = 0b0111 // Set Data size to 8 bit. - rw.raw.txeie = 1 // Enable tx buffer empty interrupt. - rw.raw.rxneie = 1 // Enable rx not buffer empty interrupt. - rw.raw.errie = 1 // Enable error interrupt. - rw.raw.frf = 0 // Reset frame format (i2s). - // rw.raw.nssp = 0 // FIXME: understand this Disable NSS pulse management. - // rw.raw.ssoe = 0 // FIXME: understand this Disable slave select. - rw.raw.txdmaen = 1 // Enable tx dma. - rw.raw.rxdmaen = 0 // Disable rx dma. + rw.rxdmaen = .Disabled // Disable rx dma. + rw.txdmaen = .Enabled // Enable tx dma. + // FIXME: understand this Disable slave select. + // rw.ssoe = 0 + // FIXME: understand this Disable NSS pulse management. + // rw.nssp = 0 + rw.frf = .Motorola // Reset frame format (i2s). + rw.errie = .NotMasked // Enable error interrupt. + rw.rxneie = .NotMasked // Enable rx not buffer empty interrupt. + rw.txeie = .NotMasked // Enable tx buffer empty interrupt. + rw.ds = .EightBit // Set Data size to 8 bit. + rw.frxth = .Quarter // Set RXNE if FIFO <8 bits. + rw.ldma_rx = .Even // Reset dma reception length. + rw.ldma_tx = .Even // Reset dma transmission length. } // Activate the stream. - self.dma.s4cr.modify { $0.raw.en = 1 } + self.dma.st[index].cr.modify { $0.en = .Enabled } // Activate the SPI peripheral - self.spi.cr1.modify { $0.raw.spe = 1 } + self.spi.cr1.modify { $0.spe = .Enabled } func wait() -> Bool { while true { @@ -181,15 +188,15 @@ extension SPINeoPixel { // Wait until the last data frame is processed. while self.spi.sr.read().raw.bsy != 0 {} // Disable the SPI peripheral. - self.spi.cr1.modify { $0.raw.spe = 0 } + self.spi.cr1.modify { $0.spe = .Disabled } // Don't wait until the read data is received since the NeoPixel is not // a real SPI device. This will lead to overrun errors but they can be // safely ignored. // while self.spi.sr.read().raw.frlvl != 0b00 { } // Disable any existing DMA transfer on stream 0. - self.dma.s4cr.modify { $0.raw.en = 0 } + self.dma.st[index].cr.modify { $0.en = .Disabled } // Wait for the DMA stream to actually shutdown. - while self.dma.s4cr.read().raw.en != 0 {} + while self.dma.st[index].cr.read().en != .Disabled {} } } diff --git a/stm32-neopixel/Sources/Application/Registers/DMA1.swift b/stm32-neopixel/Sources/Application/Registers/DMA1.swift index be118f86..13ca8e33 100644 --- a/stm32-neopixel/Sources/Application/Registers/DMA1.swift +++ b/stm32-neopixel/Sources/Application/Registers/DMA1.swift @@ -3,1635 +3,5 @@ import MMIO /// DMA controller -@RegisterBlock -struct DMA1 { - /// low interrupt status register - @RegisterBlock(offset: 0x0) - var lisr: Register +typealias DMA1 = DMA2 - /// high interrupt status register - @RegisterBlock(offset: 0x4) - var hisr: Register - - /// low interrupt flag clear register - @RegisterBlock(offset: 0x8) - var lifcr: Register - - /// high interrupt flag clear register - @RegisterBlock(offset: 0xc) - var hifcr: Register - - /// stream x configuration register - @RegisterBlock(offset: 0x10) - var s0cr: Register - - /// stream x number of data register - @RegisterBlock(offset: 0x14) - var s0ndtr: Register - - /// stream x peripheral address register - @RegisterBlock(offset: 0x18) - var s0par: Register - - /// stream x memory 0 address register - @RegisterBlock(offset: 0x1c) - var s0m0ar: Register - - /// stream x memory 1 address register - @RegisterBlock(offset: 0x20) - var s0m1ar: Register - - /// stream x FIFO control register - @RegisterBlock(offset: 0x24) - var s0fcr: Register - - /// stream x configuration register - @RegisterBlock(offset: 0x28) - var s1cr: Register - - /// stream x number of data register - @RegisterBlock(offset: 0x2c) - var s1ndtr: Register - - /// stream x peripheral address register - @RegisterBlock(offset: 0x30) - var s1par: Register - - /// stream x memory 0 address register - @RegisterBlock(offset: 0x34) - var s1m0ar: Register - - /// stream x memory 1 address register - @RegisterBlock(offset: 0x38) - var s1m1ar: Register - - /// stream x FIFO control register - @RegisterBlock(offset: 0x3c) - var s1fcr: Register - - /// stream x configuration register - @RegisterBlock(offset: 0x40) - var s2cr: Register - - /// stream x number of data register - @RegisterBlock(offset: 0x44) - var s2ndtr: Register - - /// stream x peripheral address register - @RegisterBlock(offset: 0x48) - var s2par: Register - - /// stream x memory 0 address register - @RegisterBlock(offset: 0x4c) - var s2m0ar: Register - - /// stream x memory 1 address register - @RegisterBlock(offset: 0x50) - var s2m1ar: Register - - /// stream x FIFO control register - @RegisterBlock(offset: 0x54) - var s2fcr: Register - - /// stream x configuration register - @RegisterBlock(offset: 0x58) - var s3cr: Register - - /// stream x number of data register - @RegisterBlock(offset: 0x5c) - var s3ndtr: Register - - /// stream x peripheral address register - @RegisterBlock(offset: 0x60) - var s3par: Register - - /// stream x memory 0 address register - @RegisterBlock(offset: 0x64) - var s3m0ar: Register - - /// stream x memory 1 address register - @RegisterBlock(offset: 0x68) - var s3m1ar: Register - - /// stream x FIFO control register - @RegisterBlock(offset: 0x6c) - var s3fcr: Register - - /// stream x configuration register - @RegisterBlock(offset: 0x70) - var s4cr: Register - - /// stream x number of data register - @RegisterBlock(offset: 0x74) - var s4ndtr: Register - - /// stream x peripheral address register - @RegisterBlock(offset: 0x78) - var s4par: Register - - /// stream x memory 0 address register - @RegisterBlock(offset: 0x7c) - var s4m0ar: Register - - /// stream x memory 1 address register - @RegisterBlock(offset: 0x80) - var s4m1ar: Register - - /// stream x FIFO control register - @RegisterBlock(offset: 0x84) - var s4fcr: Register - - /// stream x configuration register - @RegisterBlock(offset: 0x88) - var s5cr: Register - - /// stream x number of data register - @RegisterBlock(offset: 0x8c) - var s5ndtr: Register - - /// stream x peripheral address register - @RegisterBlock(offset: 0x90) - var s5par: Register - - /// stream x memory 0 address register - @RegisterBlock(offset: 0x94) - var s5m0ar: Register - - /// stream x memory 1 address register - @RegisterBlock(offset: 0x98) - var s5m1ar: Register - - /// stream x FIFO control register - @RegisterBlock(offset: 0x9c) - var s5fcr: Register - - /// stream x configuration register - @RegisterBlock(offset: 0xa0) - var s6cr: Register - - /// stream x number of data register - @RegisterBlock(offset: 0xa4) - var s6ndtr: Register - - /// stream x peripheral address register - @RegisterBlock(offset: 0xa8) - var s6par: Register - - /// stream x memory 0 address register - @RegisterBlock(offset: 0xac) - var s6m0ar: Register - - /// stream x memory 1 address register - @RegisterBlock(offset: 0xb0) - var s6m1ar: Register - - /// stream x FIFO control register - @RegisterBlock(offset: 0xb4) - var s6fcr: Register - - /// stream x configuration register - @RegisterBlock(offset: 0xb8) - var s7cr: Register - - /// stream x number of data register - @RegisterBlock(offset: 0xbc) - var s7ndtr: Register - - /// stream x peripheral address register - @RegisterBlock(offset: 0xc0) - var s7par: Register - - /// stream x memory 0 address register - @RegisterBlock(offset: 0xc4) - var s7m0ar: Register - - /// stream x memory 1 address register - @RegisterBlock(offset: 0xc8) - var s7m1ar: Register - - /// stream x FIFO control register - @RegisterBlock(offset: 0xcc) - var s7fcr: Register -} - -extension DMA1 { - /// low interrupt status register - @Register(bitWidth: 32) - struct LISR { - /// Stream x transfer complete interrupt flag (x = 3..0) - @ReadOnly(bits: 27..<28) - var tcif3: TCIF3 - - /// Stream x half transfer interrupt flag (x=3..0) - @ReadOnly(bits: 26..<27) - var htif3: HTIF3 - - /// Stream x transfer error interrupt flag (x=3..0) - @ReadOnly(bits: 25..<26) - var teif3: TEIF3 - - /// Stream x direct mode error interrupt flag (x=3..0) - @ReadOnly(bits: 24..<25) - var dmeif3: DMEIF3 - - /// Stream x FIFO error interrupt flag (x=3..0) - @ReadOnly(bits: 22..<23) - var feif3: FEIF3 - - /// Stream x transfer complete interrupt flag (x = 3..0) - @ReadOnly(bits: 21..<22) - var tcif2: TCIF2 - - /// Stream x half transfer interrupt flag (x=3..0) - @ReadOnly(bits: 20..<21) - var htif2: HTIF2 - - /// Stream x transfer error interrupt flag (x=3..0) - @ReadOnly(bits: 19..<20) - var teif2: TEIF2 - - /// Stream x direct mode error interrupt flag (x=3..0) - @ReadOnly(bits: 18..<19) - var dmeif2: DMEIF2 - - /// Stream x FIFO error interrupt flag (x=3..0) - @ReadOnly(bits: 16..<17) - var feif2: FEIF2 - - /// Stream x transfer complete interrupt flag (x = 3..0) - @ReadOnly(bits: 11..<12) - var tcif1: TCIF1 - - /// Stream x half transfer interrupt flag (x=3..0) - @ReadOnly(bits: 10..<11) - var htif1: HTIF1 - - /// Stream x transfer error interrupt flag (x=3..0) - @ReadOnly(bits: 9..<10) - var teif1: TEIF1 - - /// Stream x direct mode error interrupt flag (x=3..0) - @ReadOnly(bits: 8..<9) - var dmeif1: DMEIF1 - - /// Stream x FIFO error interrupt flag (x=3..0) - @ReadOnly(bits: 6..<7) - var feif1: FEIF1 - - /// Stream x transfer complete interrupt flag (x = 3..0) - @ReadOnly(bits: 5..<6) - var tcif0: TCIF0 - - /// Stream x half transfer interrupt flag (x=3..0) - @ReadOnly(bits: 4..<5) - var htif0: HTIF0 - - /// Stream x transfer error interrupt flag (x=3..0) - @ReadOnly(bits: 3..<4) - var teif0: TEIF0 - - /// Stream x direct mode error interrupt flag (x=3..0) - @ReadOnly(bits: 2..<3) - var dmeif0: DMEIF0 - - /// Stream x FIFO error interrupt flag (x=3..0) - @ReadOnly(bits: 0..<1) - var feif0: FEIF0 - } - - /// high interrupt status register - @Register(bitWidth: 32) - struct HISR { - /// Stream x transfer complete interrupt flag (x=7..4) - @ReadOnly(bits: 27..<28) - var tcif7: TCIF7 - - /// Stream x half transfer interrupt flag (x=7..4) - @ReadOnly(bits: 26..<27) - var htif7: HTIF7 - - /// Stream x transfer error interrupt flag (x=7..4) - @ReadOnly(bits: 25..<26) - var teif7: TEIF7 - - /// Stream x direct mode error interrupt flag (x=7..4) - @ReadOnly(bits: 24..<25) - var dmeif7: DMEIF7 - - /// Stream x FIFO error interrupt flag (x=7..4) - @ReadOnly(bits: 22..<23) - var feif7: FEIF7 - - /// Stream x transfer complete interrupt flag (x=7..4) - @ReadOnly(bits: 21..<22) - var tcif6: TCIF6 - - /// Stream x half transfer interrupt flag (x=7..4) - @ReadOnly(bits: 20..<21) - var htif6: HTIF6 - - /// Stream x transfer error interrupt flag (x=7..4) - @ReadOnly(bits: 19..<20) - var teif6: TEIF6 - - /// Stream x direct mode error interrupt flag (x=7..4) - @ReadOnly(bits: 18..<19) - var dmeif6: DMEIF6 - - /// Stream x FIFO error interrupt flag (x=7..4) - @ReadOnly(bits: 16..<17) - var feif6: FEIF6 - - /// Stream x transfer complete interrupt flag (x=7..4) - @ReadOnly(bits: 11..<12) - var tcif5: TCIF5 - - /// Stream x half transfer interrupt flag (x=7..4) - @ReadOnly(bits: 10..<11) - var htif5: HTIF5 - - /// Stream x transfer error interrupt flag (x=7..4) - @ReadOnly(bits: 9..<10) - var teif5: TEIF5 - - /// Stream x direct mode error interrupt flag (x=7..4) - @ReadOnly(bits: 8..<9) - var dmeif5: DMEIF5 - - /// Stream x FIFO error interrupt flag (x=7..4) - @ReadOnly(bits: 6..<7) - var feif5: FEIF5 - - /// Stream x transfer complete interrupt flag (x=7..4) - @ReadOnly(bits: 5..<6) - var tcif4: TCIF4 - - /// Stream x half transfer interrupt flag (x=7..4) - @ReadOnly(bits: 4..<5) - var htif4: HTIF4 - - /// Stream x transfer error interrupt flag (x=7..4) - @ReadOnly(bits: 3..<4) - var teif4: TEIF4 - - /// Stream x direct mode error interrupt flag (x=7..4) - @ReadOnly(bits: 2..<3) - var dmeif4: DMEIF4 - - /// Stream x FIFO error interrupt flag (x=7..4) - @ReadOnly(bits: 0..<1) - var feif4: FEIF4 - } - - /// low interrupt flag clear register - @Register(bitWidth: 32) - struct LIFCR { - /// Stream x clear transfer complete interrupt flag (x = 3..0) - @ReadWrite(bits: 27..<28) - var ctcif3: CTCIF3 - - /// Stream x clear half transfer interrupt flag (x = 3..0) - @ReadWrite(bits: 26..<27) - var chtif3: CHTIF3 - - /// Stream x clear transfer error interrupt flag (x = 3..0) - @ReadWrite(bits: 25..<26) - var cteif3: CTEIF3 - - /// Stream x clear direct mode error interrupt flag (x = 3..0) - @ReadWrite(bits: 24..<25) - var cdmeif3: CDMEIF3 - - /// Stream x clear FIFO error interrupt flag (x = 3..0) - @ReadWrite(bits: 22..<23) - var cfeif3: CFEIF3 - - /// Stream x clear transfer complete interrupt flag (x = 3..0) - @ReadWrite(bits: 21..<22) - var ctcif2: CTCIF2 - - /// Stream x clear half transfer interrupt flag (x = 3..0) - @ReadWrite(bits: 20..<21) - var chtif2: CHTIF2 - - /// Stream x clear transfer error interrupt flag (x = 3..0) - @ReadWrite(bits: 19..<20) - var cteif2: CTEIF2 - - /// Stream x clear direct mode error interrupt flag (x = 3..0) - @ReadWrite(bits: 18..<19) - var cdmeif2: CDMEIF2 - - /// Stream x clear FIFO error interrupt flag (x = 3..0) - @ReadWrite(bits: 16..<17) - var cfeif2: CFEIF2 - - /// Stream x clear transfer complete interrupt flag (x = 3..0) - @ReadWrite(bits: 11..<12) - var ctcif1: CTCIF1 - - /// Stream x clear half transfer interrupt flag (x = 3..0) - @ReadWrite(bits: 10..<11) - var chtif1: CHTIF1 - - /// Stream x clear transfer error interrupt flag (x = 3..0) - @ReadWrite(bits: 9..<10) - var cteif1: CTEIF1 - - /// Stream x clear direct mode error interrupt flag (x = 3..0) - @ReadWrite(bits: 8..<9) - var cdmeif1: CDMEIF1 - - /// Stream x clear FIFO error interrupt flag (x = 3..0) - @ReadWrite(bits: 6..<7) - var cfeif1: CFEIF1 - - /// Stream x clear transfer complete interrupt flag (x = 3..0) - @ReadWrite(bits: 5..<6) - var ctcif0: CTCIF0 - - /// Stream x clear half transfer interrupt flag (x = 3..0) - @ReadWrite(bits: 4..<5) - var chtif0: CHTIF0 - - /// Stream x clear transfer error interrupt flag (x = 3..0) - @ReadWrite(bits: 3..<4) - var cteif0: CTEIF0 - - /// Stream x clear direct mode error interrupt flag (x = 3..0) - @ReadWrite(bits: 2..<3) - var cdmeif0: CDMEIF0 - - /// Stream x clear FIFO error interrupt flag (x = 3..0) - @ReadWrite(bits: 0..<1) - var cfeif0: CFEIF0 - } - - /// high interrupt flag clear register - @Register(bitWidth: 32) - struct HIFCR { - /// Stream x clear transfer complete interrupt flag (x = 7..4) - @ReadWrite(bits: 27..<28) - var ctcif7: CTCIF7 - - /// Stream x clear half transfer interrupt flag (x = 7..4) - @ReadWrite(bits: 26..<27) - var chtif7: CHTIF7 - - /// Stream x clear transfer error interrupt flag (x = 7..4) - @ReadWrite(bits: 25..<26) - var cteif7: CTEIF7 - - /// Stream x clear direct mode error interrupt flag (x = 7..4) - @ReadWrite(bits: 24..<25) - var cdmeif7: CDMEIF7 - - /// Stream x clear FIFO error interrupt flag (x = 7..4) - @ReadWrite(bits: 22..<23) - var cfeif7: CFEIF7 - - /// Stream x clear transfer complete interrupt flag (x = 7..4) - @ReadWrite(bits: 21..<22) - var ctcif6: CTCIF6 - - /// Stream x clear half transfer interrupt flag (x = 7..4) - @ReadWrite(bits: 20..<21) - var chtif6: CHTIF6 - - /// Stream x clear transfer error interrupt flag (x = 7..4) - @ReadWrite(bits: 19..<20) - var cteif6: CTEIF6 - - /// Stream x clear direct mode error interrupt flag (x = 7..4) - @ReadWrite(bits: 18..<19) - var cdmeif6: CDMEIF6 - - /// Stream x clear FIFO error interrupt flag (x = 7..4) - @ReadWrite(bits: 16..<17) - var cfeif6: CFEIF6 - - /// Stream x clear transfer complete interrupt flag (x = 7..4) - @ReadWrite(bits: 11..<12) - var ctcif5: CTCIF5 - - /// Stream x clear half transfer interrupt flag (x = 7..4) - @ReadWrite(bits: 10..<11) - var chtif5: CHTIF5 - - /// Stream x clear transfer error interrupt flag (x = 7..4) - @ReadWrite(bits: 9..<10) - var cteif5: CTEIF5 - - /// Stream x clear direct mode error interrupt flag (x = 7..4) - @ReadWrite(bits: 8..<9) - var cdmeif5: CDMEIF5 - - /// Stream x clear FIFO error interrupt flag (x = 7..4) - @ReadWrite(bits: 6..<7) - var cfeif5: CFEIF5 - - /// Stream x clear transfer complete interrupt flag (x = 7..4) - @ReadWrite(bits: 5..<6) - var ctcif4: CTCIF4 - - /// Stream x clear half transfer interrupt flag (x = 7..4) - @ReadWrite(bits: 4..<5) - var chtif4: CHTIF4 - - /// Stream x clear transfer error interrupt flag (x = 7..4) - @ReadWrite(bits: 3..<4) - var cteif4: CTEIF4 - - /// Stream x clear direct mode error interrupt flag (x = 7..4) - @ReadWrite(bits: 2..<3) - var cdmeif4: CDMEIF4 - - /// Stream x clear FIFO error interrupt flag (x = 7..4) - @ReadWrite(bits: 0..<1) - var cfeif4: CFEIF4 - } - - /// stream x configuration register - @Register(bitWidth: 32) - struct S0CR { - /// Channel selection - @ReadWrite(bits: 25..<28) - var chsel: CHSEL - - /// Memory burst transfer configuration - @ReadWrite(bits: 23..<25) - var mburst: MBURST - - /// Peripheral burst transfer configuration - @ReadWrite(bits: 21..<23) - var pburst: PBURST - - /// Current target (only in double buffer mode) - @ReadWrite(bits: 19..<20) - var ct: CT - - /// Double buffer mode - @ReadWrite(bits: 18..<19) - var dbm: DBM - - /// Priority level - @ReadWrite(bits: 16..<18) - var pl: PL - - /// Peripheral increment offset size - @ReadWrite(bits: 15..<16) - var pincos: PINCOS - - /// Memory data size - @ReadWrite(bits: 13..<15) - var msize: MSIZE - - /// Peripheral data size - @ReadWrite(bits: 11..<13) - var psize: PSIZE - - /// Memory increment mode - @ReadWrite(bits: 10..<11) - var minc: MINC - - /// Peripheral increment mode - @ReadWrite(bits: 9..<10) - var pinc: PINC - - /// Circular mode - @ReadWrite(bits: 8..<9) - var circ: CIRC - - /// Data transfer direction - @ReadWrite(bits: 6..<8) - var dir: DIR - - /// Peripheral flow controller - @ReadWrite(bits: 5..<6) - var pfctrl: PFCTRL - - /// Transfer complete interrupt enable - @ReadWrite(bits: 4..<5) - var tcie: TCIE - - /// Half transfer interrupt enable - @ReadWrite(bits: 3..<4) - var htie: HTIE - - /// Transfer error interrupt enable - @ReadWrite(bits: 2..<3) - var teie: TEIE - - /// Direct mode error interrupt enable - @ReadWrite(bits: 1..<2) - var dmeie: DMEIE - - /// Stream enable / flag stream ready when read low - @ReadWrite(bits: 0..<1) - var en: EN - } - - /// stream x number of data register - @Register(bitWidth: 32) - struct S0NDTR { - /// Number of data items to transfer - @ReadWrite(bits: 0..<16) - var ndt: NDT - } - - /// stream x peripheral address register - @Register(bitWidth: 32) - struct S0PAR { - /// Peripheral address - @ReadWrite(bits: 0..<32) - var pa: PA - } - - /// stream x memory 0 address register - @Register(bitWidth: 32) - struct S0M0AR { - /// Memory 0 address - @ReadWrite(bits: 0..<32) - var m0a: M0A - } - - /// stream x memory 1 address register - @Register(bitWidth: 32) - struct S0M1AR { - /// Memory 1 address (used in case of Double buffer mode) - @ReadWrite(bits: 0..<32) - var m1a: M1A - } - - /// stream x FIFO control register - @Register(bitWidth: 32) - struct S0FCR { - /// FIFO error interrupt enable - @ReadWrite(bits: 7..<8) - var feie: FEIE - - /// FIFO status - @ReadOnly(bits: 3..<6) - var fs: FS - - /// Direct mode disable - @ReadWrite(bits: 2..<3) - var dmdis: DMDIS - - /// FIFO threshold selection - @ReadWrite(bits: 0..<2) - var fth: FTH - } - - /// stream x configuration register - @Register(bitWidth: 32) - struct S1CR { - /// Channel selection - @ReadWrite(bits: 25..<28) - var chsel: CHSEL - - /// Memory burst transfer configuration - @ReadWrite(bits: 23..<25) - var mburst: MBURST - - /// Peripheral burst transfer configuration - @ReadWrite(bits: 21..<23) - var pburst: PBURST - - /// ACK - @ReadWrite(bits: 20..<21) - var ack: ACK - - /// Current target (only in double buffer mode) - @ReadWrite(bits: 19..<20) - var ct: CT - - /// Double buffer mode - @ReadWrite(bits: 18..<19) - var dbm: DBM - - /// Priority level - @ReadWrite(bits: 16..<18) - var pl: PL - - /// Peripheral increment offset size - @ReadWrite(bits: 15..<16) - var pincos: PINCOS - - /// Memory data size - @ReadWrite(bits: 13..<15) - var msize: MSIZE - - /// Peripheral data size - @ReadWrite(bits: 11..<13) - var psize: PSIZE - - /// Memory increment mode - @ReadWrite(bits: 10..<11) - var minc: MINC - - /// Peripheral increment mode - @ReadWrite(bits: 9..<10) - var pinc: PINC - - /// Circular mode - @ReadWrite(bits: 8..<9) - var circ: CIRC - - /// Data transfer direction - @ReadWrite(bits: 6..<8) - var dir: DIR - - /// Peripheral flow controller - @ReadWrite(bits: 5..<6) - var pfctrl: PFCTRL - - /// Transfer complete interrupt enable - @ReadWrite(bits: 4..<5) - var tcie: TCIE - - /// Half transfer interrupt enable - @ReadWrite(bits: 3..<4) - var htie: HTIE - - /// Transfer error interrupt enable - @ReadWrite(bits: 2..<3) - var teie: TEIE - - /// Direct mode error interrupt enable - @ReadWrite(bits: 1..<2) - var dmeie: DMEIE - - /// Stream enable / flag stream ready when read low - @ReadWrite(bits: 0..<1) - var en: EN - } - - /// stream x number of data register - @Register(bitWidth: 32) - struct S1NDTR { - /// Number of data items to transfer - @ReadWrite(bits: 0..<16) - var ndt: NDT - } - - /// stream x peripheral address register - @Register(bitWidth: 32) - struct S1PAR { - /// Peripheral address - @ReadWrite(bits: 0..<32) - var pa: PA - } - - /// stream x memory 0 address register - @Register(bitWidth: 32) - struct S1M0AR { - /// Memory 0 address - @ReadWrite(bits: 0..<32) - var m0a: M0A - } - - /// stream x memory 1 address register - @Register(bitWidth: 32) - struct S1M1AR { - /// Memory 1 address (used in case of Double buffer mode) - @ReadWrite(bits: 0..<32) - var m1a: M1A - } - - /// stream x FIFO control register - @Register(bitWidth: 32) - struct S1FCR { - /// FIFO error interrupt enable - @ReadWrite(bits: 7..<8) - var feie: FEIE - - /// FIFO status - @ReadOnly(bits: 3..<6) - var fs: FS - - /// Direct mode disable - @ReadWrite(bits: 2..<3) - var dmdis: DMDIS - - /// FIFO threshold selection - @ReadWrite(bits: 0..<2) - var fth: FTH - } - - /// stream x configuration register - @Register(bitWidth: 32) - struct S2CR { - /// Channel selection - @ReadWrite(bits: 25..<28) - var chsel: CHSEL - - /// Memory burst transfer configuration - @ReadWrite(bits: 23..<25) - var mburst: MBURST - - /// Peripheral burst transfer configuration - @ReadWrite(bits: 21..<23) - var pburst: PBURST - - /// ACK - @ReadWrite(bits: 20..<21) - var ack: ACK - - /// Current target (only in double buffer mode) - @ReadWrite(bits: 19..<20) - var ct: CT - - /// Double buffer mode - @ReadWrite(bits: 18..<19) - var dbm: DBM - - /// Priority level - @ReadWrite(bits: 16..<18) - var pl: PL - - /// Peripheral increment offset size - @ReadWrite(bits: 15..<16) - var pincos: PINCOS - - /// Memory data size - @ReadWrite(bits: 13..<15) - var msize: MSIZE - - /// Peripheral data size - @ReadWrite(bits: 11..<13) - var psize: PSIZE - - /// Memory increment mode - @ReadWrite(bits: 10..<11) - var minc: MINC - - /// Peripheral increment mode - @ReadWrite(bits: 9..<10) - var pinc: PINC - - /// Circular mode - @ReadWrite(bits: 8..<9) - var circ: CIRC - - /// Data transfer direction - @ReadWrite(bits: 6..<8) - var dir: DIR - - /// Peripheral flow controller - @ReadWrite(bits: 5..<6) - var pfctrl: PFCTRL - - /// Transfer complete interrupt enable - @ReadWrite(bits: 4..<5) - var tcie: TCIE - - /// Half transfer interrupt enable - @ReadWrite(bits: 3..<4) - var htie: HTIE - - /// Transfer error interrupt enable - @ReadWrite(bits: 2..<3) - var teie: TEIE - - /// Direct mode error interrupt enable - @ReadWrite(bits: 1..<2) - var dmeie: DMEIE - - /// Stream enable / flag stream ready when read low - @ReadWrite(bits: 0..<1) - var en: EN - } - - /// stream x number of data register - @Register(bitWidth: 32) - struct S2NDTR { - /// Number of data items to transfer - @ReadWrite(bits: 0..<16) - var ndt: NDT - } - - /// stream x peripheral address register - @Register(bitWidth: 32) - struct S2PAR { - /// Peripheral address - @ReadWrite(bits: 0..<32) - var pa: PA - } - - /// stream x memory 0 address register - @Register(bitWidth: 32) - struct S2M0AR { - /// Memory 0 address - @ReadWrite(bits: 0..<32) - var m0a: M0A - } - - /// stream x memory 1 address register - @Register(bitWidth: 32) - struct S2M1AR { - /// Memory 1 address (used in case of Double buffer mode) - @ReadWrite(bits: 0..<32) - var m1a: M1A - } - - /// stream x FIFO control register - @Register(bitWidth: 32) - struct S2FCR { - /// FIFO error interrupt enable - @ReadWrite(bits: 7..<8) - var feie: FEIE - - /// FIFO status - @ReadOnly(bits: 3..<6) - var fs: FS - - /// Direct mode disable - @ReadWrite(bits: 2..<3) - var dmdis: DMDIS - - /// FIFO threshold selection - @ReadWrite(bits: 0..<2) - var fth: FTH - } - - /// stream x configuration register - @Register(bitWidth: 32) - struct S3CR { - /// Channel selection - @ReadWrite(bits: 25..<28) - var chsel: CHSEL - - /// Memory burst transfer configuration - @ReadWrite(bits: 23..<25) - var mburst: MBURST - - /// Peripheral burst transfer configuration - @ReadWrite(bits: 21..<23) - var pburst: PBURST - - /// ACK - @ReadWrite(bits: 20..<21) - var ack: ACK - - /// Current target (only in double buffer mode) - @ReadWrite(bits: 19..<20) - var ct: CT - - /// Double buffer mode - @ReadWrite(bits: 18..<19) - var dbm: DBM - - /// Priority level - @ReadWrite(bits: 16..<18) - var pl: PL - - /// Peripheral increment offset size - @ReadWrite(bits: 15..<16) - var pincos: PINCOS - - /// Memory data size - @ReadWrite(bits: 13..<15) - var msize: MSIZE - - /// Peripheral data size - @ReadWrite(bits: 11..<13) - var psize: PSIZE - - /// Memory increment mode - @ReadWrite(bits: 10..<11) - var minc: MINC - - /// Peripheral increment mode - @ReadWrite(bits: 9..<10) - var pinc: PINC - - /// Circular mode - @ReadWrite(bits: 8..<9) - var circ: CIRC - - /// Data transfer direction - @ReadWrite(bits: 6..<8) - var dir: DIR - - /// Peripheral flow controller - @ReadWrite(bits: 5..<6) - var pfctrl: PFCTRL - - /// Transfer complete interrupt enable - @ReadWrite(bits: 4..<5) - var tcie: TCIE - - /// Half transfer interrupt enable - @ReadWrite(bits: 3..<4) - var htie: HTIE - - /// Transfer error interrupt enable - @ReadWrite(bits: 2..<3) - var teie: TEIE - - /// Direct mode error interrupt enable - @ReadWrite(bits: 1..<2) - var dmeie: DMEIE - - /// Stream enable / flag stream ready when read low - @ReadWrite(bits: 0..<1) - var en: EN - } - - /// stream x number of data register - @Register(bitWidth: 32) - struct S3NDTR { - /// Number of data items to transfer - @ReadWrite(bits: 0..<16) - var ndt: NDT - } - - /// stream x peripheral address register - @Register(bitWidth: 32) - struct S3PAR { - /// Peripheral address - @ReadWrite(bits: 0..<32) - var pa: PA - } - - /// stream x memory 0 address register - @Register(bitWidth: 32) - struct S3M0AR { - /// Memory 0 address - @ReadWrite(bits: 0..<32) - var m0a: M0A - } - - /// stream x memory 1 address register - @Register(bitWidth: 32) - struct S3M1AR { - /// Memory 1 address (used in case of Double buffer mode) - @ReadWrite(bits: 0..<32) - var m1a: M1A - } - - /// stream x FIFO control register - @Register(bitWidth: 32) - struct S3FCR { - /// FIFO error interrupt enable - @ReadWrite(bits: 7..<8) - var feie: FEIE - - /// FIFO status - @ReadOnly(bits: 3..<6) - var fs: FS - - /// Direct mode disable - @ReadWrite(bits: 2..<3) - var dmdis: DMDIS - - /// FIFO threshold selection - @ReadWrite(bits: 0..<2) - var fth: FTH - } - - /// stream x configuration register - @Register(bitWidth: 32) - struct S4CR { - /// Channel selection - @ReadWrite(bits: 25..<28) - var chsel: CHSEL - - /// Memory burst transfer configuration - @ReadWrite(bits: 23..<25) - var mburst: MBURST - - /// Peripheral burst transfer configuration - @ReadWrite(bits: 21..<23) - var pburst: PBURST - - /// ACK - @ReadWrite(bits: 20..<21) - var ack: ACK - - /// Current target (only in double buffer mode) - @ReadWrite(bits: 19..<20) - var ct: CT - - /// Double buffer mode - @ReadWrite(bits: 18..<19) - var dbm: DBM - - /// Priority level - @ReadWrite(bits: 16..<18) - var pl: PL - - /// Peripheral increment offset size - @ReadWrite(bits: 15..<16) - var pincos: PINCOS - - /// Memory data size - @ReadWrite(bits: 13..<15) - var msize: MSIZE - - /// Peripheral data size - @ReadWrite(bits: 11..<13) - var psize: PSIZE - - /// Memory increment mode - @ReadWrite(bits: 10..<11) - var minc: MINC - - /// Peripheral increment mode - @ReadWrite(bits: 9..<10) - var pinc: PINC - - /// Circular mode - @ReadWrite(bits: 8..<9) - var circ: CIRC - - /// Data transfer direction - @ReadWrite(bits: 6..<8) - var dir: DIR - - /// Peripheral flow controller - @ReadWrite(bits: 5..<6) - var pfctrl: PFCTRL - - /// Transfer complete interrupt enable - @ReadWrite(bits: 4..<5) - var tcie: TCIE - - /// Half transfer interrupt enable - @ReadWrite(bits: 3..<4) - var htie: HTIE - - /// Transfer error interrupt enable - @ReadWrite(bits: 2..<3) - var teie: TEIE - - /// Direct mode error interrupt enable - @ReadWrite(bits: 1..<2) - var dmeie: DMEIE - - /// Stream enable / flag stream ready when read low - @ReadWrite(bits: 0..<1) - var en: EN - } - - /// stream x number of data register - @Register(bitWidth: 32) - struct S4NDTR { - /// Number of data items to transfer - @ReadWrite(bits: 0..<16) - var ndt: NDT - } - - /// stream x peripheral address register - @Register(bitWidth: 32) - struct S4PAR { - /// Peripheral address - @ReadWrite(bits: 0..<32) - var pa: PA - } - - /// stream x memory 0 address register - @Register(bitWidth: 32) - struct S4M0AR { - /// Memory 0 address - @ReadWrite(bits: 0..<32) - var m0a: M0A - } - - /// stream x memory 1 address register - @Register(bitWidth: 32) - struct S4M1AR { - /// Memory 1 address (used in case of Double buffer mode) - @ReadWrite(bits: 0..<32) - var m1a: M1A - } - - /// stream x FIFO control register - @Register(bitWidth: 32) - struct S4FCR { - /// FIFO error interrupt enable - @ReadWrite(bits: 7..<8) - var feie: FEIE - - /// FIFO status - @ReadOnly(bits: 3..<6) - var fs: FS - - /// Direct mode disable - @ReadWrite(bits: 2..<3) - var dmdis: DMDIS - - /// FIFO threshold selection - @ReadWrite(bits: 0..<2) - var fth: FTH - } - - /// stream x configuration register - @Register(bitWidth: 32) - struct S5CR { - /// Channel selection - @ReadWrite(bits: 25..<28) - var chsel: CHSEL - - /// Memory burst transfer configuration - @ReadWrite(bits: 23..<25) - var mburst: MBURST - - /// Peripheral burst transfer configuration - @ReadWrite(bits: 21..<23) - var pburst: PBURST - - /// ACK - @ReadWrite(bits: 20..<21) - var ack: ACK - - /// Current target (only in double buffer mode) - @ReadWrite(bits: 19..<20) - var ct: CT - - /// Double buffer mode - @ReadWrite(bits: 18..<19) - var dbm: DBM - - /// Priority level - @ReadWrite(bits: 16..<18) - var pl: PL - - /// Peripheral increment offset size - @ReadWrite(bits: 15..<16) - var pincos: PINCOS - - /// Memory data size - @ReadWrite(bits: 13..<15) - var msize: MSIZE - - /// Peripheral data size - @ReadWrite(bits: 11..<13) - var psize: PSIZE - - /// Memory increment mode - @ReadWrite(bits: 10..<11) - var minc: MINC - - /// Peripheral increment mode - @ReadWrite(bits: 9..<10) - var pinc: PINC - - /// Circular mode - @ReadWrite(bits: 8..<9) - var circ: CIRC - - /// Data transfer direction - @ReadWrite(bits: 6..<8) - var dir: DIR - - /// Peripheral flow controller - @ReadWrite(bits: 5..<6) - var pfctrl: PFCTRL - - /// Transfer complete interrupt enable - @ReadWrite(bits: 4..<5) - var tcie: TCIE - - /// Half transfer interrupt enable - @ReadWrite(bits: 3..<4) - var htie: HTIE - - /// Transfer error interrupt enable - @ReadWrite(bits: 2..<3) - var teie: TEIE - - /// Direct mode error interrupt enable - @ReadWrite(bits: 1..<2) - var dmeie: DMEIE - - /// Stream enable / flag stream ready when read low - @ReadWrite(bits: 0..<1) - var en: EN - } - - /// stream x number of data register - @Register(bitWidth: 32) - struct S5NDTR { - /// Number of data items to transfer - @ReadWrite(bits: 0..<16) - var ndt: NDT - } - - /// stream x peripheral address register - @Register(bitWidth: 32) - struct S5PAR { - /// Peripheral address - @ReadWrite(bits: 0..<32) - var pa: PA - } - - /// stream x memory 0 address register - @Register(bitWidth: 32) - struct S5M0AR { - /// Memory 0 address - @ReadWrite(bits: 0..<32) - var m0a: M0A - } - - /// stream x memory 1 address register - @Register(bitWidth: 32) - struct S5M1AR { - /// Memory 1 address (used in case of Double buffer mode) - @ReadWrite(bits: 0..<32) - var m1a: M1A - } - - /// stream x FIFO control register - @Register(bitWidth: 32) - struct S5FCR { - /// FIFO error interrupt enable - @ReadWrite(bits: 7..<8) - var feie: FEIE - - /// FIFO status - @ReadOnly(bits: 3..<6) - var fs: FS - - /// Direct mode disable - @ReadWrite(bits: 2..<3) - var dmdis: DMDIS - - /// FIFO threshold selection - @ReadWrite(bits: 0..<2) - var fth: FTH - } - - /// stream x configuration register - @Register(bitWidth: 32) - struct S6CR { - /// Channel selection - @ReadWrite(bits: 25..<28) - var chsel: CHSEL - - /// Memory burst transfer configuration - @ReadWrite(bits: 23..<25) - var mburst: MBURST - - /// Peripheral burst transfer configuration - @ReadWrite(bits: 21..<23) - var pburst: PBURST - - /// ACK - @ReadWrite(bits: 20..<21) - var ack: ACK - - /// Current target (only in double buffer mode) - @ReadWrite(bits: 19..<20) - var ct: CT - - /// Double buffer mode - @ReadWrite(bits: 18..<19) - var dbm: DBM - - /// Priority level - @ReadWrite(bits: 16..<18) - var pl: PL - - /// Peripheral increment offset size - @ReadWrite(bits: 15..<16) - var pincos: PINCOS - - /// Memory data size - @ReadWrite(bits: 13..<15) - var msize: MSIZE - - /// Peripheral data size - @ReadWrite(bits: 11..<13) - var psize: PSIZE - - /// Memory increment mode - @ReadWrite(bits: 10..<11) - var minc: MINC - - /// Peripheral increment mode - @ReadWrite(bits: 9..<10) - var pinc: PINC - - /// Circular mode - @ReadWrite(bits: 8..<9) - var circ: CIRC - - /// Data transfer direction - @ReadWrite(bits: 6..<8) - var dir: DIR - - /// Peripheral flow controller - @ReadWrite(bits: 5..<6) - var pfctrl: PFCTRL - - /// Transfer complete interrupt enable - @ReadWrite(bits: 4..<5) - var tcie: TCIE - - /// Half transfer interrupt enable - @ReadWrite(bits: 3..<4) - var htie: HTIE - - /// Transfer error interrupt enable - @ReadWrite(bits: 2..<3) - var teie: TEIE - - /// Direct mode error interrupt enable - @ReadWrite(bits: 1..<2) - var dmeie: DMEIE - - /// Stream enable / flag stream ready when read low - @ReadWrite(bits: 0..<1) - var en: EN - } - - /// stream x number of data register - @Register(bitWidth: 32) - struct S6NDTR { - /// Number of data items to transfer - @ReadWrite(bits: 0..<16) - var ndt: NDT - } - - /// stream x peripheral address register - @Register(bitWidth: 32) - struct S6PAR { - /// Peripheral address - @ReadWrite(bits: 0..<32) - var pa: PA - } - - /// stream x memory 0 address register - @Register(bitWidth: 32) - struct S6M0AR { - /// Memory 0 address - @ReadWrite(bits: 0..<32) - var m0a: M0A - } - - /// stream x memory 1 address register - @Register(bitWidth: 32) - struct S6M1AR { - /// Memory 1 address (used in case of Double buffer mode) - @ReadWrite(bits: 0..<32) - var m1a: M1A - } - - /// stream x FIFO control register - @Register(bitWidth: 32) - struct S6FCR { - /// FIFO error interrupt enable - @ReadWrite(bits: 7..<8) - var feie: FEIE - - /// FIFO status - @ReadOnly(bits: 3..<6) - var fs: FS - - /// Direct mode disable - @ReadWrite(bits: 2..<3) - var dmdis: DMDIS - - /// FIFO threshold selection - @ReadWrite(bits: 0..<2) - var fth: FTH - } - - /// stream x configuration register - @Register(bitWidth: 32) - struct S7CR { - /// Channel selection - @ReadWrite(bits: 25..<28) - var chsel: CHSEL - - /// Memory burst transfer configuration - @ReadWrite(bits: 23..<25) - var mburst: MBURST - - /// Peripheral burst transfer configuration - @ReadWrite(bits: 21..<23) - var pburst: PBURST - - /// ACK - @ReadWrite(bits: 20..<21) - var ack: ACK - - /// Current target (only in double buffer mode) - @ReadWrite(bits: 19..<20) - var ct: CT - - /// Double buffer mode - @ReadWrite(bits: 18..<19) - var dbm: DBM - - /// Priority level - @ReadWrite(bits: 16..<18) - var pl: PL - - /// Peripheral increment offset size - @ReadWrite(bits: 15..<16) - var pincos: PINCOS - - /// Memory data size - @ReadWrite(bits: 13..<15) - var msize: MSIZE - - /// Peripheral data size - @ReadWrite(bits: 11..<13) - var psize: PSIZE - - /// Memory increment mode - @ReadWrite(bits: 10..<11) - var minc: MINC - - /// Peripheral increment mode - @ReadWrite(bits: 9..<10) - var pinc: PINC - - /// Circular mode - @ReadWrite(bits: 8..<9) - var circ: CIRC - - /// Data transfer direction - @ReadWrite(bits: 6..<8) - var dir: DIR - - /// Peripheral flow controller - @ReadWrite(bits: 5..<6) - var pfctrl: PFCTRL - - /// Transfer complete interrupt enable - @ReadWrite(bits: 4..<5) - var tcie: TCIE - - /// Half transfer interrupt enable - @ReadWrite(bits: 3..<4) - var htie: HTIE - - /// Transfer error interrupt enable - @ReadWrite(bits: 2..<3) - var teie: TEIE - - /// Direct mode error interrupt enable - @ReadWrite(bits: 1..<2) - var dmeie: DMEIE - - /// Stream enable / flag stream ready when read low - @ReadWrite(bits: 0..<1) - var en: EN - } - - /// stream x number of data register - @Register(bitWidth: 32) - struct S7NDTR { - /// Number of data items to transfer - @ReadWrite(bits: 0..<16) - var ndt: NDT - } - - /// stream x peripheral address register - @Register(bitWidth: 32) - struct S7PAR { - /// Peripheral address - @ReadWrite(bits: 0..<32) - var pa: PA - } - - /// stream x memory 0 address register - @Register(bitWidth: 32) - struct S7M0AR { - /// Memory 0 address - @ReadWrite(bits: 0..<32) - var m0a: M0A - } - - /// stream x memory 1 address register - @Register(bitWidth: 32) - struct S7M1AR { - /// Memory 1 address (used in case of Double buffer mode) - @ReadWrite(bits: 0..<32) - var m1a: M1A - } - - /// stream x FIFO control register - @Register(bitWidth: 32) - struct S7FCR { - /// FIFO error interrupt enable - @ReadWrite(bits: 7..<8) - var feie: FEIE - - /// FIFO status - @ReadOnly(bits: 3..<6) - var fs: FS - - /// Direct mode disable - @ReadWrite(bits: 2..<3) - var dmdis: DMDIS - - /// FIFO threshold selection - @ReadWrite(bits: 0..<2) - var fth: FTH - } -} diff --git a/stm32-neopixel/Sources/Application/Registers/DMA2.swift b/stm32-neopixel/Sources/Application/Registers/DMA2.swift new file mode 100644 index 00000000..e6b7a6bb --- /dev/null +++ b/stm32-neopixel/Sources/Application/Registers/DMA2.swift @@ -0,0 +1,893 @@ +// Generated by svd2swift. + +import MMIO + +/// DMA controller +@RegisterBlock +struct DMA2 { + /// low interrupt status register + @RegisterBlock(offset: 0x0) + var lisr: Register + + /// high interrupt status register + @RegisterBlock(offset: 0x4) + var hisr: Register + + /// low interrupt flag clear register + @RegisterBlock(offset: 0x8) + var lifcr: Register + + /// high interrupt flag clear register + @RegisterBlock(offset: 0xc) + var hifcr: Register + + /// Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers + @RegisterBlock(offset: 0x10, stride: 0x18, count: 8) + var st: RegisterArray +} + +extension DMA2 { + /// low interrupt status register + @Register(bitWidth: 32) + struct LISR { + /// Stream x transfer complete interrupt flag (x = 3..0) + @ReadOnly(bits: 27..<28) + var tcif3: TCIF3 + + /// Stream x half transfer interrupt flag (x=3..0) + @ReadOnly(bits: 26..<27) + var htif3: HTIF3 + + /// Stream x transfer error interrupt flag (x=3..0) + @ReadOnly(bits: 25..<26) + var teif3: TEIF3 + + /// Stream x direct mode error interrupt flag (x=3..0) + @ReadOnly(bits: 24..<25) + var dmeif3: DMEIF3 + + /// Stream x FIFO error interrupt flag (x=3..0) + @ReadOnly(bits: 22..<23) + var feif3: FEIF3 + + /// Stream x transfer complete interrupt flag (x = 3..0) + @ReadOnly(bits: 21..<22) + var tcif2: TCIF2 + + /// Stream x half transfer interrupt flag (x=3..0) + @ReadOnly(bits: 20..<21) + var htif2: HTIF2 + + /// Stream x transfer error interrupt flag (x=3..0) + @ReadOnly(bits: 19..<20) + var teif2: TEIF2 + + /// Stream x direct mode error interrupt flag (x=3..0) + @ReadOnly(bits: 18..<19) + var dmeif2: DMEIF2 + + /// Stream x FIFO error interrupt flag (x=3..0) + @ReadOnly(bits: 16..<17) + var feif2: FEIF2 + + /// Stream x transfer complete interrupt flag (x = 3..0) + @ReadOnly(bits: 11..<12) + var tcif1: TCIF1 + + /// Stream x half transfer interrupt flag (x=3..0) + @ReadOnly(bits: 10..<11) + var htif1: HTIF1 + + /// Stream x transfer error interrupt flag (x=3..0) + @ReadOnly(bits: 9..<10) + var teif1: TEIF1 + + /// Stream x direct mode error interrupt flag (x=3..0) + @ReadOnly(bits: 8..<9) + var dmeif1: DMEIF1 + + /// Stream x FIFO error interrupt flag (x=3..0) + @ReadOnly(bits: 6..<7) + var feif1: FEIF1 + + /// Stream x transfer complete interrupt flag (x = 3..0) + @ReadOnly(bits: 5..<6) + var tcif0: TCIF0 + + /// Stream x half transfer interrupt flag (x=3..0) + @ReadOnly(bits: 4..<5) + var htif0: HTIF0 + + /// Stream x transfer error interrupt flag (x=3..0) + @ReadOnly(bits: 3..<4) + var teif0: TEIF0 + + /// Stream x direct mode error interrupt flag (x=3..0) + @ReadOnly(bits: 2..<3) + var dmeif0: DMEIF0 + + /// Stream x FIFO error interrupt flag (x=3..0) + @ReadOnly(bits: 0..<1) + var feif0: FEIF0 + } + + /// high interrupt status register + @Register(bitWidth: 32) + struct HISR { + /// Stream x transfer complete interrupt flag (x=7..4) + @ReadOnly(bits: 27..<28) + var tcif7: TCIF7 + + /// Stream x half transfer interrupt flag (x=7..4) + @ReadOnly(bits: 26..<27) + var htif7: HTIF7 + + /// Stream x transfer error interrupt flag (x=7..4) + @ReadOnly(bits: 25..<26) + var teif7: TEIF7 + + /// Stream x direct mode error interrupt flag (x=7..4) + @ReadOnly(bits: 24..<25) + var dmeif7: DMEIF7 + + /// Stream x FIFO error interrupt flag (x=7..4) + @ReadOnly(bits: 22..<23) + var feif7: FEIF7 + + /// Stream x transfer complete interrupt flag (x=7..4) + @ReadOnly(bits: 21..<22) + var tcif6: TCIF6 + + /// Stream x half transfer interrupt flag (x=7..4) + @ReadOnly(bits: 20..<21) + var htif6: HTIF6 + + /// Stream x transfer error interrupt flag (x=7..4) + @ReadOnly(bits: 19..<20) + var teif6: TEIF6 + + /// Stream x direct mode error interrupt flag (x=7..4) + @ReadOnly(bits: 18..<19) + var dmeif6: DMEIF6 + + /// Stream x FIFO error interrupt flag (x=7..4) + @ReadOnly(bits: 16..<17) + var feif6: FEIF6 + + /// Stream x transfer complete interrupt flag (x=7..4) + @ReadOnly(bits: 11..<12) + var tcif5: TCIF5 + + /// Stream x half transfer interrupt flag (x=7..4) + @ReadOnly(bits: 10..<11) + var htif5: HTIF5 + + /// Stream x transfer error interrupt flag (x=7..4) + @ReadOnly(bits: 9..<10) + var teif5: TEIF5 + + /// Stream x direct mode error interrupt flag (x=7..4) + @ReadOnly(bits: 8..<9) + var dmeif5: DMEIF5 + + /// Stream x FIFO error interrupt flag (x=7..4) + @ReadOnly(bits: 6..<7) + var feif5: FEIF5 + + /// Stream x transfer complete interrupt flag (x=7..4) + @ReadOnly(bits: 5..<6) + var tcif4: TCIF4 + + /// Stream x half transfer interrupt flag (x=7..4) + @ReadOnly(bits: 4..<5) + var htif4: HTIF4 + + /// Stream x transfer error interrupt flag (x=7..4) + @ReadOnly(bits: 3..<4) + var teif4: TEIF4 + + /// Stream x direct mode error interrupt flag (x=7..4) + @ReadOnly(bits: 2..<3) + var dmeif4: DMEIF4 + + /// Stream x FIFO error interrupt flag (x=7..4) + @ReadOnly(bits: 0..<1) + var feif4: FEIF4 + } + + /// low interrupt flag clear register + @Register(bitWidth: 32) + struct LIFCR { + /// Stream x clear transfer complete interrupt flag (x = 3..0) + @WriteOnly(bits: 27..<28) + var ctcif3: CTCIF3 + + /// Stream x clear half transfer interrupt flag (x = 3..0) + @WriteOnly(bits: 26..<27) + var chtif3: CHTIF3 + + /// Stream x clear transfer error interrupt flag (x = 3..0) + @WriteOnly(bits: 25..<26) + var cteif3: CTEIF3 + + /// Stream x clear direct mode error interrupt flag (x = 3..0) + @WriteOnly(bits: 24..<25) + var cdmeif3: CDMEIF3 + + /// Stream x clear FIFO error interrupt flag (x = 3..0) + @WriteOnly(bits: 22..<23) + var cfeif3: CFEIF3 + + /// Stream x clear transfer complete interrupt flag (x = 3..0) + @WriteOnly(bits: 21..<22) + var ctcif2: CTCIF2 + + /// Stream x clear half transfer interrupt flag (x = 3..0) + @WriteOnly(bits: 20..<21) + var chtif2: CHTIF2 + + /// Stream x clear transfer error interrupt flag (x = 3..0) + @WriteOnly(bits: 19..<20) + var cteif2: CTEIF2 + + /// Stream x clear direct mode error interrupt flag (x = 3..0) + @WriteOnly(bits: 18..<19) + var cdmeif2: CDMEIF2 + + /// Stream x clear FIFO error interrupt flag (x = 3..0) + @WriteOnly(bits: 16..<17) + var cfeif2: CFEIF2 + + /// Stream x clear transfer complete interrupt flag (x = 3..0) + @WriteOnly(bits: 11..<12) + var ctcif1: CTCIF1 + + /// Stream x clear half transfer interrupt flag (x = 3..0) + @WriteOnly(bits: 10..<11) + var chtif1: CHTIF1 + + /// Stream x clear transfer error interrupt flag (x = 3..0) + @WriteOnly(bits: 9..<10) + var cteif1: CTEIF1 + + /// Stream x clear direct mode error interrupt flag (x = 3..0) + @WriteOnly(bits: 8..<9) + var cdmeif1: CDMEIF1 + + /// Stream x clear FIFO error interrupt flag (x = 3..0) + @WriteOnly(bits: 6..<7) + var cfeif1: CFEIF1 + + /// Stream x clear transfer complete interrupt flag (x = 3..0) + @WriteOnly(bits: 5..<6) + var ctcif0: CTCIF0 + + /// Stream x clear half transfer interrupt flag (x = 3..0) + @WriteOnly(bits: 4..<5) + var chtif0: CHTIF0 + + /// Stream x clear transfer error interrupt flag (x = 3..0) + @WriteOnly(bits: 3..<4) + var cteif0: CTEIF0 + + /// Stream x clear direct mode error interrupt flag (x = 3..0) + @WriteOnly(bits: 2..<3) + var cdmeif0: CDMEIF0 + + /// Stream x clear FIFO error interrupt flag (x = 3..0) + @WriteOnly(bits: 0..<1) + var cfeif0: CFEIF0 + } + + /// high interrupt flag clear register + @Register(bitWidth: 32) + struct HIFCR { + /// Stream x clear transfer complete interrupt flag (x = 7..4) + @WriteOnly(bits: 27..<28) + var ctcif7: CTCIF7 + + /// Stream x clear half transfer interrupt flag (x = 7..4) + @WriteOnly(bits: 26..<27) + var chtif7: CHTIF7 + + /// Stream x clear transfer error interrupt flag (x = 7..4) + @WriteOnly(bits: 25..<26) + var cteif7: CTEIF7 + + /// Stream x clear direct mode error interrupt flag (x = 7..4) + @WriteOnly(bits: 24..<25) + var cdmeif7: CDMEIF7 + + /// Stream x clear FIFO error interrupt flag (x = 7..4) + @WriteOnly(bits: 22..<23) + var cfeif7: CFEIF7 + + /// Stream x clear transfer complete interrupt flag (x = 7..4) + @WriteOnly(bits: 21..<22) + var ctcif6: CTCIF6 + + /// Stream x clear half transfer interrupt flag (x = 7..4) + @WriteOnly(bits: 20..<21) + var chtif6: CHTIF6 + + /// Stream x clear transfer error interrupt flag (x = 7..4) + @WriteOnly(bits: 19..<20) + var cteif6: CTEIF6 + + /// Stream x clear direct mode error interrupt flag (x = 7..4) + @WriteOnly(bits: 18..<19) + var cdmeif6: CDMEIF6 + + /// Stream x clear FIFO error interrupt flag (x = 7..4) + @WriteOnly(bits: 16..<17) + var cfeif6: CFEIF6 + + /// Stream x clear transfer complete interrupt flag (x = 7..4) + @WriteOnly(bits: 11..<12) + var ctcif5: CTCIF5 + + /// Stream x clear half transfer interrupt flag (x = 7..4) + @WriteOnly(bits: 10..<11) + var chtif5: CHTIF5 + + /// Stream x clear transfer error interrupt flag (x = 7..4) + @WriteOnly(bits: 9..<10) + var cteif5: CTEIF5 + + /// Stream x clear direct mode error interrupt flag (x = 7..4) + @WriteOnly(bits: 8..<9) + var cdmeif5: CDMEIF5 + + /// Stream x clear FIFO error interrupt flag (x = 7..4) + @WriteOnly(bits: 6..<7) + var cfeif5: CFEIF5 + + /// Stream x clear transfer complete interrupt flag (x = 7..4) + @WriteOnly(bits: 5..<6) + var ctcif4: CTCIF4 + + /// Stream x clear half transfer interrupt flag (x = 7..4) + @WriteOnly(bits: 4..<5) + var chtif4: CHTIF4 + + /// Stream x clear transfer error interrupt flag (x = 7..4) + @WriteOnly(bits: 3..<4) + var cteif4: CTEIF4 + + /// Stream x clear direct mode error interrupt flag (x = 7..4) + @WriteOnly(bits: 2..<3) + var cdmeif4: CDMEIF4 + + /// Stream x clear FIFO error interrupt flag (x = 7..4) + @WriteOnly(bits: 0..<1) + var cfeif4: CFEIF4 + } + + /// Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers + @RegisterBlock + struct ST { + /// stream x configuration register + @RegisterBlock(offset: 0x0) + var cr: Register + + /// stream x number of data register + @RegisterBlock(offset: 0x4) + var ndtr: Register + + /// stream x peripheral address register + @RegisterBlock(offset: 0x8) + var par: Register + + /// stream x memory 0 address register + @RegisterBlock(offset: 0xc) + var m0ar: Register + + /// stream x memory 1 address register + @RegisterBlock(offset: 0x10) + var m1ar: Register + + /// stream x FIFO control register + @RegisterBlock(offset: 0x14) + var fcr: Register + } +} + +extension DMA2.ST { + /// stream x configuration register + @Register(bitWidth: 32) + struct CR { + /// Channel selection + @ReadWrite(bits: 25..<28) + var chsel: CHSEL + + /// Memory burst transfer configuration + @ReadWrite(bits: 23..<25) + var mburst: MBURST + + /// Peripheral burst transfer configuration + @ReadWrite(bits: 21..<23, as: PBURSTValues.self) + var pburst: PBURST + + /// Current target (only in double buffer mode) + @ReadWrite(bits: 19..<20, as: CTValues.self) + var ct: CT + + /// Double buffer mode + @ReadWrite(bits: 18..<19, as: DBMValues.self) + var dbm: DBM + + /// Priority level + @ReadWrite(bits: 16..<18, as: PLValues.self) + var pl: PL + + /// Peripheral increment offset size + @ReadWrite(bits: 15..<16, as: PINCOSValues.self) + var pincos: PINCOS + + /// Memory data size + @ReadWrite(bits: 13..<15) + var msize: MSIZE + + /// Peripheral data size + @ReadWrite(bits: 11..<13, as: PSIZEValues.self) + var psize: PSIZE + + /// Memory increment mode + @ReadWrite(bits: 10..<11) + var minc: MINC + + /// Peripheral increment mode + @ReadWrite(bits: 9..<10, as: PINCValues.self) + var pinc: PINC + + /// Circular mode + @ReadWrite(bits: 8..<9, as: CIRCValues.self) + var circ: CIRC + + /// Data transfer direction + @ReadWrite(bits: 6..<8, as: DIRValues.self) + var dir: DIR + + /// Peripheral flow controller + @ReadWrite(bits: 5..<6, as: PFCTRLValues.self) + var pfctrl: PFCTRL + + /// Transfer complete interrupt enable + @ReadWrite(bits: 4..<5, as: TCIEValues.self) + var tcie: TCIE + + /// Half transfer interrupt enable + @ReadWrite(bits: 3..<4, as: HTIEValues.self) + var htie: HTIE + + /// Transfer error interrupt enable + @ReadWrite(bits: 2..<3, as: TEIEValues.self) + var teie: TEIE + + /// Direct mode error interrupt enable + @ReadWrite(bits: 1..<2, as: DMEIEValues.self) + var dmeie: DMEIE + + /// Stream enable / flag stream ready when read low + @ReadWrite(bits: 0..<1, as: ENValues.self) + var en: EN + } + + /// stream x number of data register + @Register(bitWidth: 32) + struct NDTR { + /// Number of data items to transfer + @ReadWrite(bits: 0..<16) + var ndt: NDT + } + + /// stream x peripheral address register + @Register(bitWidth: 32) + struct PAR { + /// Peripheral address + @ReadWrite(bits: 0..<32) + var pa: PA + } + + /// stream x memory 0 address register + @Register(bitWidth: 32) + struct M0AR { + /// Memory 0 address + @ReadWrite(bits: 0..<32) + var m0a: M0A + } + + /// stream x memory 1 address register + @Register(bitWidth: 32) + struct M1AR { + /// Memory 1 address (used in case of Double buffer mode) + @ReadWrite(bits: 0..<32) + var m1a: M1A + } + + /// stream x FIFO control register + @Register(bitWidth: 32) + struct FCR { + /// FIFO error interrupt enable + @ReadWrite(bits: 7..<8, as: FEIEValues.self) + var feie: FEIE + + /// FIFO status + @ReadOnly(bits: 3..<6) + var fs: FS + + /// Direct mode disable + @ReadWrite(bits: 2..<3, as: DMDISValues.self) + var dmdis: DMDIS + + /// FIFO threshold selection + @ReadWrite(bits: 0..<2, as: FTHValues.self) + var fth: FTH + } +} + +extension DMA2.ST.CR { + struct PBURSTValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// Single transfer + static let Single = Self(rawValue: 0x0) + + /// Incremental burst of 4 beats + static let INCR4 = Self(rawValue: 0x1) + + /// Incremental burst of 8 beats + static let INCR8 = Self(rawValue: 0x2) + + /// Incremental burst of 16 beats + static let INCR16 = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension DMA2.ST.CR { + struct CTValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// The current target memory is Memory 0 + static let Memory0 = Self(rawValue: 0x0) + + /// The current target memory is Memory 1 + static let Memory1 = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension DMA2.ST.CR { + struct DBMValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// No buffer switching at the end of transfer + static let Disabled = Self(rawValue: 0x0) + + /// Memory target switched at the end of the DMA transfer + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension DMA2.ST.CR { + struct PLValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// Low + static let Low = Self(rawValue: 0x0) + + /// Medium + static let Medium = Self(rawValue: 0x1) + + /// High + static let High = Self(rawValue: 0x2) + + /// Very high + static let VeryHigh = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension DMA2.ST.CR { + struct PINCOSValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// The offset size for the peripheral address calculation is linked to the PSIZE + static let PSIZE = Self(rawValue: 0x0) + + /// The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment) + static let Fixed4 = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension DMA2.ST.CR { + struct PSIZEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// Byte (8-bit) + static let Bits8 = Self(rawValue: 0x0) + + /// Half-word (16-bit) + static let Bits16 = Self(rawValue: 0x1) + + /// Word (32-bit) + static let Bits32 = Self(rawValue: 0x2) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension DMA2.ST.CR { + struct PINCValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Address pointer is fixed + static let Fixed = Self(rawValue: 0x0) + + /// Address pointer is incremented after each data transfer + static let Incremented = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension DMA2.ST.CR { + struct CIRCValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Circular mode disabled + static let Disabled = Self(rawValue: 0x0) + + /// Circular mode enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension DMA2.ST.CR { + struct DIRValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// Peripheral-to-memory + static let PeripheralToMemory = Self(rawValue: 0x0) + + /// Memory-to-peripheral + static let MemoryToPeripheral = Self(rawValue: 0x1) + + /// Memory-to-memory + static let MemoryToMemory = Self(rawValue: 0x2) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension DMA2.ST.CR { + struct PFCTRLValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// The DMA is the flow controller + static let DMA = Self(rawValue: 0x0) + + /// The peripheral is the flow controller + static let Peripheral = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension DMA2.ST.CR { + struct TCIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// TC interrupt disabled + static let Disabled = Self(rawValue: 0x0) + + /// TC interrupt enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension DMA2.ST.CR { + struct HTIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// HT interrupt disabled + static let Disabled = Self(rawValue: 0x0) + + /// HT interrupt enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension DMA2.ST.CR { + struct TEIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// TE interrupt disabled + static let Disabled = Self(rawValue: 0x0) + + /// TE interrupt enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension DMA2.ST.CR { + struct DMEIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// DME interrupt disabled + static let Disabled = Self(rawValue: 0x0) + + /// DME interrupt enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension DMA2.ST.CR { + struct ENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Stream disabled + static let Disabled = Self(rawValue: 0x0) + + /// Stream enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension DMA2.ST.FCR { + struct FEIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// FE interrupt disabled + static let Disabled = Self(rawValue: 0x0) + + /// FE interrupt enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension DMA2.ST.FCR { + struct DMDISValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Direct mode is enabled + static let Enabled = Self(rawValue: 0x0) + + /// Direct mode is disabled + static let Disabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension DMA2.ST.FCR { + struct FTHValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// 1/4 full FIFO + static let Quarter = Self(rawValue: 0x0) + + /// 1/2 full FIFO + static let Half = Self(rawValue: 0x1) + + /// 3/4 full FIFO + static let ThreeQuarters = Self(rawValue: 0x2) + + /// Full FIFO + static let Full = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} diff --git a/stm32-neopixel/Sources/Application/Registers/Device.swift b/stm32-neopixel/Sources/Application/Registers/Device.swift index e1d72549..3d315391 100644 --- a/stm32-neopixel/Sources/Application/Registers/Device.swift +++ b/stm32-neopixel/Sources/Application/Registers/Device.swift @@ -3,22 +3,28 @@ import MMIO /// DMA controller -let dma1 = DMA1(unsafeAddress: 0x4002_6000) +let dma1 = DMA1(unsafeAddress: 0x40026000) + +/// DMA controller +let dma2 = DMA2(unsafeAddress: 0x40026400) /// General-purpose I/Os -let gpioa = GPIOA(unsafeAddress: 0x4002_0000) +let gpioa = GPIOA(unsafeAddress: 0x40020000) /// General-purpose I/Os -let gpiob = GPIOB(unsafeAddress: 0x4002_0400) +let gpiob = GPIOB(unsafeAddress: 0x40020400) /// General-purpose I/Os -let gpioi = GPIOI(unsafeAddress: 0x4002_2000) +let gpioi = GPIOI(unsafeAddress: 0x40022000) /// Reset and clock control -let rcc = RCC(unsafeAddress: 0x4002_3800) +let rcc = RCC(unsafeAddress: 0x40023800) + +/// Serial peripheral interface +let spi1 = SPI1(unsafeAddress: 0x40013000) /// Serial peripheral interface -let spi2 = SPI2(unsafeAddress: 0x4000_3800) +let spi2 = SPI2(unsafeAddress: 0x40003800) /// Universal synchronous asynchronous receiver transmitter -let usart1 = USART1(unsafeAddress: 0x4001_1000) +let usart1 = USART1(unsafeAddress: 0x40011000) diff --git a/stm32-neopixel/Sources/Application/Registers/GPIOA.swift b/stm32-neopixel/Sources/Application/Registers/GPIOA.swift index 1bc077bf..3bc4d2ff 100644 --- a/stm32-neopixel/Sources/Application/Registers/GPIOA.swift +++ b/stm32-neopixel/Sources/Application/Registers/GPIOA.swift @@ -115,7 +115,7 @@ extension GPIOA { var moder1: MODER1 /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<2) + @ReadWrite(bits: 0..<2, as: MODER0Values.self) var moder0: MODER0 } @@ -183,7 +183,7 @@ extension GPIOA { var ot1: OT1 /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: OT0Values.self) var ot0: OT0 } @@ -251,7 +251,7 @@ extension GPIOA { var ospeedr1: OSPEEDR1 /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<2) + @ReadWrite(bits: 0..<2, as: OSPEEDR0Values.self) var ospeedr0: OSPEEDR0 } @@ -319,7 +319,7 @@ extension GPIOA { var pupdr1: PUPDR1 /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<2) + @ReadWrite(bits: 0..<2, as: PUPDR0Values.self) var pupdr0: PUPDR0 } @@ -455,7 +455,7 @@ extension GPIOA { var odr1: ODR1 /// Port output data (y = 0..15) - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: ODR0Values.self) var odr0: ODR0 } @@ -595,7 +595,7 @@ extension GPIOA { @Register(bitWidth: 32) struct LCKR { /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 16..<17) + @ReadWrite(bits: 16..<17, as: LCKKValues.self) var lckk: LCKK /// Port x lock bit y (y= 0..15) @@ -659,7 +659,7 @@ extension GPIOA { var lck1: LCK1 /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: LCK0Values.self) var lck0: LCK0 } @@ -695,7 +695,7 @@ extension GPIOA { var afrl1: AFRL1 /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 0..<4) + @ReadWrite(bits: 0..<4, as: AFRL0Values.self) var afrl0: AFRL0 } @@ -731,7 +731,7 @@ extension GPIOA { var afrh9: AFRH9 /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 0..<4) + @ReadWrite(bits: 0..<4, as: AFRH8Values.self) var afrh8: AFRH8 } @@ -803,3 +803,273 @@ extension GPIOA { var br15: BR15 } } + +extension GPIOA.MODER { + struct MODER0Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// Input mode (reset state) + static let Input = Self(rawValue: 0x0) + + /// General purpose output mode + static let Output = Self(rawValue: 0x1) + + /// Alternate function mode + static let Alternate = Self(rawValue: 0x2) + + /// Analog mode + static let Analog = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.OTYPER { + struct OT0Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Output push-pull (reset state) + static let PushPull = Self(rawValue: 0x0) + + /// Output open-drain + static let OpenDrain = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.OSPEEDR { + struct OSPEEDR0Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// Low speed + static let LowSpeed = Self(rawValue: 0x0) + + /// Medium speed + static let MediumSpeed = Self(rawValue: 0x1) + + /// High speed + static let HighSpeed = Self(rawValue: 0x2) + + /// Very high speed + static let VeryHighSpeed = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.PUPDR { + struct PUPDR0Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// No pull-up, pull-down + static let Floating = Self(rawValue: 0x0) + + /// Pull-up + static let PullUp = Self(rawValue: 0x1) + + /// Pull-down + static let PullDown = Self(rawValue: 0x2) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.ODR { + struct ODR0Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Set output to logic low + static let Low = Self(rawValue: 0x0) + + /// Set output to logic high + static let High = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.LCKR { + struct LCKKValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Port configuration lock key not active + static let NotActive = Self(rawValue: 0x0) + + /// Port configuration lock key active + static let Active = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.LCKR { + struct LCK0Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Port configuration not locked + static let Unlocked = Self(rawValue: 0x0) + + /// Port configuration locked + static let Locked = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.AFRL { + struct AFRL0Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 4 + + /// AF0 + static let AF0 = Self(rawValue: 0x0) + + /// AF1 + static let AF1 = Self(rawValue: 0x1) + + /// AF2 + static let AF2 = Self(rawValue: 0x2) + + /// AF3 + static let AF3 = Self(rawValue: 0x3) + + /// AF4 + static let AF4 = Self(rawValue: 0x4) + + /// AF5 + static let AF5 = Self(rawValue: 0x5) + + /// AF6 + static let AF6 = Self(rawValue: 0x6) + + /// AF7 + static let AF7 = Self(rawValue: 0x7) + + /// AF8 + static let AF8 = Self(rawValue: 0x8) + + /// AF9 + static let AF9 = Self(rawValue: 0x9) + + /// AF10 + static let AF10 = Self(rawValue: 0xa) + + /// AF11 + static let AF11 = Self(rawValue: 0xb) + + /// AF12 + static let AF12 = Self(rawValue: 0xc) + + /// AF13 + static let AF13 = Self(rawValue: 0xd) + + /// AF14 + static let AF14 = Self(rawValue: 0xe) + + /// AF15 + static let AF15 = Self(rawValue: 0xf) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.AFRH { + struct AFRH8Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 4 + + /// AF0 + static let AF0 = Self(rawValue: 0x0) + + /// AF1 + static let AF1 = Self(rawValue: 0x1) + + /// AF2 + static let AF2 = Self(rawValue: 0x2) + + /// AF3 + static let AF3 = Self(rawValue: 0x3) + + /// AF4 + static let AF4 = Self(rawValue: 0x4) + + /// AF5 + static let AF5 = Self(rawValue: 0x5) + + /// AF6 + static let AF6 = Self(rawValue: 0x6) + + /// AF7 + static let AF7 = Self(rawValue: 0x7) + + /// AF8 + static let AF8 = Self(rawValue: 0x8) + + /// AF9 + static let AF9 = Self(rawValue: 0x9) + + /// AF10 + static let AF10 = Self(rawValue: 0xa) + + /// AF11 + static let AF11 = Self(rawValue: 0xb) + + /// AF12 + static let AF12 = Self(rawValue: 0xc) + + /// AF13 + static let AF13 = Self(rawValue: 0xd) + + /// AF14 + static let AF14 = Self(rawValue: 0xe) + + /// AF15 + static let AF15 = Self(rawValue: 0xf) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} diff --git a/stm32-neopixel/Sources/Application/Registers/GPIOB.swift b/stm32-neopixel/Sources/Application/Registers/GPIOB.swift index 9988779e..c820355f 100644 --- a/stm32-neopixel/Sources/Application/Registers/GPIOB.swift +++ b/stm32-neopixel/Sources/Application/Registers/GPIOB.swift @@ -2,4 +2,6 @@ import MMIO +/// General-purpose I/Os typealias GPIOB = GPIOA + diff --git a/stm32-neopixel/Sources/Application/Registers/GPIOI.swift b/stm32-neopixel/Sources/Application/Registers/GPIOI.swift index dbdaf85b..f7e28cc8 100644 --- a/stm32-neopixel/Sources/Application/Registers/GPIOI.swift +++ b/stm32-neopixel/Sources/Application/Registers/GPIOI.swift @@ -2,4 +2,6 @@ import MMIO +/// General-purpose I/Os typealias GPIOI = GPIOA + diff --git a/stm32-neopixel/Sources/Application/Registers/RCC.swift b/stm32-neopixel/Sources/Application/Registers/RCC.swift index a06ea27b..4f5842ef 100644 --- a/stm32-neopixel/Sources/Application/Registers/RCC.swift +++ b/stm32-neopixel/Sources/Application/Registers/RCC.swift @@ -103,11 +103,11 @@ struct RCC { /// dedicated clocks configuration register @RegisterBlock(offset: 0x8c) - var dkcfgr1: Register + var dckcfgr1: Register /// dedicated clocks configuration register @RegisterBlock(offset: 0x90) - var dkcfgr2: Register + var dckcfgr2: Register } extension RCC { @@ -131,11 +131,11 @@ extension RCC { var pllon: PLLON /// Clock security system enable - @ReadWrite(bits: 19..<20) + @ReadWrite(bits: 19..<20, as: CSSONValues.self) var csson: CSSON /// HSE clock bypass - @ReadWrite(bits: 18..<19) + @ReadWrite(bits: 18..<19, as: HSEBYPValues.self) var hsebyp: HSEBYP /// HSE clock ready flag @@ -159,107 +159,47 @@ extension RCC { var hsirdy: HSIRDY /// Internal high-speed clock enable - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: HSIONValues.self) var hsion: HSION + + /// PLLSAI clock ready flag + @ReadOnly(bits: 29..<30) + var pllsairdy: PLLSAIRDY + + /// PLLSAI enable + @ReadWrite(bits: 28..<29) + var pllsaion: PLLSAION } /// PLL configuration register @Register(bitWidth: 32) struct PLLCFGR { - /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks - @ReadWrite(bits: 27..<28) - var pllq3: PLLQ3 - - /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks - @ReadWrite(bits: 26..<27) - var pllq2: PLLQ2 - - /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks - @ReadWrite(bits: 25..<26) - var pllq1: PLLQ1 - - /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks - @ReadWrite(bits: 24..<25) - var pllq0: PLLQ0 - /// Main PLL(PLL) and audio PLL (PLLI2S) entry clock source - @ReadWrite(bits: 22..<23) + @ReadWrite(bits: 22..<23, as: PLLSRCValues.self) var pllsrc: PLLSRC - /// Main PLL (PLL) division factor for main system clock - @ReadWrite(bits: 17..<18) - var pllp1: PLLP1 - - /// Main PLL (PLL) division factor for main system clock - @ReadWrite(bits: 16..<17) - var pllp0: PLLP0 - - /// Main PLL (PLL) multiplication factor for VCO - @ReadWrite(bits: 14..<15) - var plln8: PLLN8 - - /// Main PLL (PLL) multiplication factor for VCO - @ReadWrite(bits: 13..<14) - var plln7: PLLN7 - - /// Main PLL (PLL) multiplication factor for VCO - @ReadWrite(bits: 12..<13) - var plln6: PLLN6 - - /// Main PLL (PLL) multiplication factor for VCO - @ReadWrite(bits: 11..<12) - var plln5: PLLN5 - - /// Main PLL (PLL) multiplication factor for VCO - @ReadWrite(bits: 10..<11) - var plln4: PLLN4 - - /// Main PLL (PLL) multiplication factor for VCO - @ReadWrite(bits: 9..<10) - var plln3: PLLN3 - - /// Main PLL (PLL) multiplication factor for VCO - @ReadWrite(bits: 8..<9) - var plln2: PLLN2 - - /// Main PLL (PLL) multiplication factor for VCO - @ReadWrite(bits: 7..<8) - var plln1: PLLN1 - - /// Main PLL (PLL) multiplication factor for VCO - @ReadWrite(bits: 6..<7) - var plln0: PLLN0 - - /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - @ReadWrite(bits: 5..<6) - var pllm5: PLLM5 - - /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - @ReadWrite(bits: 4..<5) - var pllm4: PLLM4 - /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - @ReadWrite(bits: 3..<4) - var pllm3: PLLM3 + @ReadWrite(bits: 0..<6) + var pllm: PLLM - /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - @ReadWrite(bits: 2..<3) - var pllm2: PLLM2 + /// Main PLL (PLL) multiplication factor for VCO + @ReadWrite(bits: 6..<15) + var plln: PLLN - /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - @ReadWrite(bits: 1..<2) - var pllm1: PLLM1 + /// Main PLL (PLL) division factor for main system clock + @ReadWrite(bits: 16..<18, as: PLLPValues.self) + var pllp: PLLP - /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - @ReadWrite(bits: 0..<1) - var pllm0: PLLM0 + /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + @ReadWrite(bits: 24..<28) + var pllq: PLLQ } /// clock configuration register @Register(bitWidth: 32) struct CFGR { /// Microcontroller clock output 2 - @ReadWrite(bits: 30..<32) + @ReadWrite(bits: 30..<32, as: MCO2Values.self) var mco2: MCO2 /// MCO2 prescaler @@ -267,15 +207,15 @@ extension RCC { var mco2pre: MCO2PRE /// MCO1 prescaler - @ReadWrite(bits: 24..<27) + @ReadWrite(bits: 24..<27, as: MCO1PREValues.self) var mco1pre: MCO1PRE /// I2S clock selection - @ReadWrite(bits: 23..<24) + @ReadWrite(bits: 23..<24, as: I2SSRCValues.self) var i2ssrc: I2SSRC /// Microcontroller clock output 1 - @ReadWrite(bits: 21..<23) + @ReadWrite(bits: 21..<23, as: MCO1Values.self) var mco1: MCO1 /// HSE division factor for RTC clock @@ -287,28 +227,20 @@ extension RCC { var ppre2: PPRE2 /// APB Low speed prescaler (APB1) - @ReadWrite(bits: 10..<13) + @ReadWrite(bits: 10..<13, as: PPRE1Values.self) var ppre1: PPRE1 /// AHB prescaler - @ReadWrite(bits: 4..<8) + @ReadWrite(bits: 4..<8, as: HPREValues.self) var hpre: HPRE - /// System clock switch status - @ReadOnly(bits: 3..<4) - var sws1: SWS1 - - /// System clock switch status - @ReadOnly(bits: 2..<3) - var sws0: SWS0 - /// System clock switch - @ReadWrite(bits: 1..<2) - var sw1: SW1 + @Reserved(bits: 0..<2, as: SWValues.self) + var sw: SW - /// System clock switch - @ReadWrite(bits: 0..<1) - var sw0: SW0 + /// System clock switch status + @Reserved(bits: 2..<4) + var sws: SWS } /// clock interrupt register @@ -371,7 +303,7 @@ extension RCC { var lserdyie: LSERDYIE /// LSI ready interrupt enable - @ReadWrite(bits: 8..<9) + @ReadWrite(bits: 8..<9, as: LSIRDYIEValues.self) var lsirdyie: LSIRDYIE /// Clock security system interrupt flag @@ -475,7 +407,7 @@ extension RCC { var gpiobrst: GPIOBRST /// IO port A reset - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: GPIOARSTValues.self) var gpioarst: GPIOARST } @@ -499,7 +431,7 @@ extension RCC { var cryprst: CRYPRST /// Camera interface reset - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: DCMIRSTValues.self) var dcmirst: DCMIRST } @@ -507,7 +439,7 @@ extension RCC { @Register(bitWidth: 32) struct AHB3RSTR { /// Flexible memory controller module reset - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: FMCRSTValues.self) var fmcrst: FMCRST /// Quad SPI memory controller reset @@ -519,7 +451,7 @@ extension RCC { @Register(bitWidth: 32) struct APB1RSTR { /// TIM2 reset - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: TIM2RSTValues.self) var tim2rst: TIM2RST /// TIM3 reset @@ -568,11 +500,11 @@ extension RCC { /// USART 2 reset @ReadWrite(bits: 17..<18) - var uart2rst: UART2RST + var usart2rst: USART2RST /// USART 3 reset @ReadWrite(bits: 18..<19) - var uart3rst: UART3RST + var usart3rst: USART3RST /// USART 4 reset @ReadWrite(bits: 19..<20) @@ -639,7 +571,7 @@ extension RCC { @Register(bitWidth: 32) struct APB2RSTR { /// TIM1 reset - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: TIM1RSTValues.self) var tim1rst: TIM1RST /// TIM8 reset @@ -748,7 +680,7 @@ extension RCC { /// CCM data RAM clock enable @ReadWrite(bits: 20..<21) - var ccmdataramen: CCMDATARAMEN + var dtcmramen: DTCMRAMEN /// Backup SRAM interface clock enable @ReadWrite(bits: 18..<19) @@ -799,7 +731,7 @@ extension RCC { var gpioben: GPIOBEN /// IO port A clock enable - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: GPIOAENValues.self) var gpioaen: GPIOAEN } @@ -823,7 +755,7 @@ extension RCC { var crypen: CRYPEN /// Camera interface enable - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: DCMIENValues.self) var dcmien: DCMIEN } @@ -831,7 +763,7 @@ extension RCC { @Register(bitWidth: 32) struct AHB3ENR { /// Flexible memory controller module clock enable - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: FMCENValues.self) var fmcen: FMCEN /// Quad SPI memory controller clock enable @@ -843,7 +775,7 @@ extension RCC { @Register(bitWidth: 32) struct APB1ENR { /// TIM2 clock enable - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: TIM2ENValues.self) var tim2en: TIM2EN /// TIM3 clock enable @@ -936,11 +868,11 @@ extension RCC { /// UART7 clock enable @ReadWrite(bits: 30..<31) - var uart7enr: UART7ENR + var uart7en: UART7EN /// UART8 clock enable @ReadWrite(bits: 31..<32) - var uart8enr: UART8ENR + var uart8en: UART8EN /// SPDIF-RX clock enable @ReadWrite(bits: 16..<17) @@ -952,7 +884,7 @@ extension RCC { /// Low power timer 1 clock enable @ReadWrite(bits: 9..<10) - var lptmi1en: LPTMI1EN + var lptim1en: LPTIM1EN /// I2C4 clock enable @ReadWrite(bits: 24..<25) @@ -963,7 +895,7 @@ extension RCC { @Register(bitWidth: 32) struct APB2ENR { /// TIM1 clock enable - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: TIM1ENValues.self) var tim1en: TIM1EN /// TIM8 clock enable @@ -996,7 +928,7 @@ extension RCC { /// SPI4 clock enable @ReadWrite(bits: 13..<14) - var spi4enr: SPI4ENR + var spi4en: SPI4EN /// System configuration controller clock enable @ReadWrite(bits: 14..<15) @@ -1016,11 +948,11 @@ extension RCC { /// SPI5 clock enable @ReadWrite(bits: 20..<21) - var spi5enr: SPI5ENR + var spi5en: SPI5EN /// SPI6 clock enable @ReadWrite(bits: 21..<22) - var spi6enr: SPI6ENR + var spi6en: SPI6EN /// SAI1 clock enable @ReadWrite(bits: 22..<23) @@ -1043,7 +975,7 @@ extension RCC { @Register(bitWidth: 32) struct AHB1LPENR { /// IO port A clock enable during sleep mode - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: GPIOALPENValues.self) var gpioalpen: GPIOALPEN /// IO port B clock enable during Sleep mode @@ -1145,6 +1077,14 @@ extension RCC { /// USB OTG HS ULPI clock enable during Sleep mode @ReadWrite(bits: 30..<31) var otghsulpilpen: OTGHSULPILPEN + + /// AXI to AHB bridge clock enable during Sleep mode + @ReadWrite(bits: 13..<14) + var axilpen: AXILPEN + + /// DTCM RAM interface clock enable during Sleep mode + @ReadWrite(bits: 20..<21) + var dtcmlpen: DTCMLPEN } /// AHB2 peripheral clock enable in low power mode register @@ -1167,7 +1107,7 @@ extension RCC { var cryplpen: CRYPLPEN /// Camera interface enable during Sleep mode - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: DCMILPENValues.self) var dcmilpen: DCMILPEN } @@ -1175,7 +1115,7 @@ extension RCC { @Register(bitWidth: 32) struct AHB3LPENR { /// Flexible memory controller module clock enable during Sleep mode - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: FMCLPENValues.self) var fmclpen: FMCLPEN /// Quand SPI memory controller clock enable during Sleep mode @@ -1187,7 +1127,7 @@ extension RCC { @Register(bitWidth: 32) struct APB1LPENR { /// TIM2 clock enable during Sleep mode - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: TIM2LPENValues.self) var tim2lpen: TIM2LPEN /// TIM3 clock enable during Sleep mode @@ -1307,7 +1247,7 @@ extension RCC { @Register(bitWidth: 32) struct APB2LPENR { /// TIM1 clock enable during Sleep mode - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: TIM1LPENValues.self) var tim1lpen: TIM1LPEN /// TIM8 clock enable during Sleep mode @@ -1387,23 +1327,15 @@ extension RCC { @Register(bitWidth: 32) struct BDCR { /// Backup domain software reset - @ReadWrite(bits: 16..<17) + @ReadWrite(bits: 16..<17, as: BDRSTValues.self) var bdrst: BDRST /// RTC clock enable - @ReadWrite(bits: 15..<16) + @ReadWrite(bits: 15..<16, as: RTCENValues.self) var rtcen: RTCEN - /// RTC clock source selection - @ReadWrite(bits: 9..<10) - var rtcsel1: RTCSEL1 - - /// RTC clock source selection - @ReadWrite(bits: 8..<9) - var rtcsel0: RTCSEL0 - /// External low-speed oscillator bypass - @ReadWrite(bits: 2..<3) + @ReadWrite(bits: 2..<3, as: LSEBYPValues.self) var lsebyp: LSEBYP /// External low-speed oscillator ready @@ -1411,8 +1343,16 @@ extension RCC { var lserdy: LSERDY /// External low-speed oscillator enable - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: LSEONValues.self) var lseon: LSEON + + /// LSE oscillator drive capability + @ReadWrite(bits: 3..<5, as: LSEDRVValues.self) + var lsedrv: LSEDRV + + /// RTC clock source selection + @Reserved(bits: 8..<10, as: RTCSELValues.self) + var rtcsel: RTCSEL } /// clock control & status register @@ -1455,7 +1395,7 @@ extension RCC { var lsirdy: LSIRDY /// Internal low-speed oscillator enable - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: LSIONValues.self) var lsion: LSION } @@ -1463,11 +1403,11 @@ extension RCC { @Register(bitWidth: 32) struct SSCGR { /// Spread spectrum modulation enable - @ReadWrite(bits: 31..<32) + @ReadWrite(bits: 31..<32, as: SSCGENValues.self) var sscgen: SSCGEN /// Spread Select - @ReadWrite(bits: 30..<31) + @ReadWrite(bits: 30..<31, as: SPREADSELValues.self) var spreadsel: SPREADSEL /// Incrementation step @@ -1493,6 +1433,10 @@ extension RCC { /// PLLI2S multiplication factor for VCO @ReadWrite(bits: 6..<15) var plli2sn: PLLI2SN + + /// PLLI2S division factor for SPDIFRX clock + @ReadWrite(bits: 16..<18, as: PLLI2SPValues.self) + var plli2sp: PLLI2SP } /// PLL configuration register @@ -1503,7 +1447,7 @@ extension RCC { var pllsain: PLLSAIN /// PLLSAI division factor for 48MHz clock - @ReadWrite(bits: 16..<18) + @ReadWrite(bits: 16..<18, as: PLLSAIPValues.self) var pllsaip: PLLSAIP /// PLLSAI division factor for SAI clock @@ -1517,41 +1461,41 @@ extension RCC { /// dedicated clocks configuration register @Register(bitWidth: 32) - struct DKCFGR1 { + struct DCKCFGR1 { /// PLLI2S division factor for SAI1 clock - @ReadWrite(bits: 0..<5) - var plli2sdiv: PLLI2SDIV + @ReadWrite(bits: 0..<5, as: PLLI2SDIVQValues.self) + var plli2sdivq: PLLI2SDIVQ /// PLLSAI division factor for SAI1 clock - @ReadWrite(bits: 8..<13) + @ReadWrite(bits: 8..<13, as: PLLSAIDIVQValues.self) var pllsaidivq: PLLSAIDIVQ /// division factor for LCD_CLK - @ReadWrite(bits: 16..<18) + @ReadWrite(bits: 16..<18, as: PLLSAIDIVRValues.self) var pllsaidivr: PLLSAIDIVR /// SAI1 clock source selection - @ReadWrite(bits: 20..<22) + @ReadWrite(bits: 20..<22, as: SAI1SELValues.self) var sai1sel: SAI1SEL /// SAI2 clock source selection - @ReadWrite(bits: 22..<24) + @ReadWrite(bits: 22..<24, as: SAI2SELValues.self) var sai2sel: SAI2SEL /// Timers clocks prescalers selection - @ReadWrite(bits: 24..<25) + @ReadWrite(bits: 24..<25, as: TIMPREValues.self) var timpre: TIMPRE } /// dedicated clocks configuration register @Register(bitWidth: 32) - struct DKCFGR2 { + struct DCKCFGR2 { /// USART 1 clock source selection - @ReadWrite(bits: 0..<2) + @ReadWrite(bits: 0..<2, as: USART1SELValues.self) var usart1sel: USART1SEL /// USART 2 clock source selection - @ReadWrite(bits: 2..<4) + @ReadWrite(bits: 2..<4, as: USART2SELValues.self) var usart2sel: USART2SEL /// USART 3 clock source selection @@ -1579,7 +1523,7 @@ extension RCC { var uart8sel: UART8SEL /// I2C1 clock source selection - @ReadWrite(bits: 16..<18) + @ReadWrite(bits: 16..<18, as: I2C1SELValues.self) var i2c1sel: I2C1SEL /// I2C2 clock source selection @@ -1595,19 +1539,1295 @@ extension RCC { var i2c4sel: I2C4SEL /// Low power timer 1 clock source selection - @ReadWrite(bits: 24..<26) + @ReadWrite(bits: 24..<26, as: LPTIM1SELValues.self) var lptim1sel: LPTIM1SEL /// HDMI-CEC clock source selection - @ReadWrite(bits: 26..<27) + @ReadWrite(bits: 26..<27, as: CECSELValues.self) var cecsel: CECSEL /// 48MHz clock source selection - @ReadWrite(bits: 27..<28) + @ReadWrite(bits: 27..<28, as: CK48MSELValues.self) var ck48msel: CK48MSEL /// SDMMC clock source selection - @ReadWrite(bits: 28..<29) - var sdmmcsel: SDMMCSEL + @ReadWrite(bits: 28..<29, as: SDMMC1SELValues.self) + var sdmmc1sel: SDMMC1SEL + } +} + +extension RCC.CR { + struct CSSONValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Clock security system disabled (clock detector OFF) + static let Off = Self(rawValue: 0x0) + + /// Clock security system enable (clock detector ON if the HSE is ready, OFF if not) + static let On = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CR { + struct HSEBYPValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// HSE crystal oscillator not bypassed + static let NotBypassed = Self(rawValue: 0x0) + + /// HSE crystal oscillator bypassed with external clock + static let Bypassed = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CR { + struct HSIONValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Clock Off + static let Off = Self(rawValue: 0x0) + + /// Clock On + static let On = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.PLLCFGR { + struct PLLSRCValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// HSI clock selected as PLL and PLLI2S clock entry + static let HSI = Self(rawValue: 0x0) + + /// HSE oscillator clock selected as PLL and PLLI2S clock entry + static let HSE = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.PLLCFGR { + struct PLLPValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// PLLP=2 + static let Div2 = Self(rawValue: 0x0) + + /// PLLP=4 + static let Div4 = Self(rawValue: 0x1) + + /// PLLP=6 + static let Div6 = Self(rawValue: 0x2) + + /// PLLP=8 + static let Div8 = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + struct MCO2Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// System clock (SYSCLK) selected + static let SYSCLK = Self(rawValue: 0x0) + + /// PLLI2S clock selected + static let PLLI2S = Self(rawValue: 0x1) + + /// HSE oscillator clock selected + static let HSE = Self(rawValue: 0x2) + + /// PLL clock selected + static let PLL = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + struct MCO1PREValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 3 + + /// No division + static let Div1 = Self(rawValue: 0x0) + + /// Division by 2 + static let Div2 = Self(rawValue: 0x4) + + /// Division by 3 + static let Div3 = Self(rawValue: 0x5) + + /// Division by 4 + static let Div4 = Self(rawValue: 0x6) + + /// Division by 5 + static let Div5 = Self(rawValue: 0x7) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + struct I2SSRCValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// PLLI2S clock used as I2S clock source + static let PLLI2S = Self(rawValue: 0x0) + + /// External clock mapped on the I2S_CKIN pin used as I2S clock source + static let CKIN = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + struct MCO1Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// HSI clock selected + static let HSI = Self(rawValue: 0x0) + + /// LSE oscillator selected + static let LSE = Self(rawValue: 0x1) + + /// HSE oscillator clock selected + static let HSE = Self(rawValue: 0x2) + + /// PLL clock selected + static let PLL = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + struct PPRE1Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 3 + + /// HCLK not divided + static let Div1 = Self(rawValue: 0x0) + + /// HCLK divided by 2 + static let Div2 = Self(rawValue: 0x4) + + /// HCLK divided by 4 + static let Div4 = Self(rawValue: 0x5) + + /// HCLK divided by 8 + static let Div8 = Self(rawValue: 0x6) + + /// HCLK divided by 16 + static let Div16 = Self(rawValue: 0x7) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + struct HPREValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 4 + + /// SYSCLK not divided + static let Div1 = Self(rawValue: 0x0) + + /// SYSCLK divided by 2 + static let Div2 = Self(rawValue: 0x8) + + /// SYSCLK divided by 4 + static let Div4 = Self(rawValue: 0x9) + + /// SYSCLK divided by 8 + static let Div8 = Self(rawValue: 0xa) + + /// SYSCLK divided by 16 + static let Div16 = Self(rawValue: 0xb) + + /// SYSCLK divided by 64 + static let Div64 = Self(rawValue: 0xc) + + /// SYSCLK divided by 128 + static let Div128 = Self(rawValue: 0xd) + + /// SYSCLK divided by 256 + static let Div256 = Self(rawValue: 0xe) + + /// SYSCLK divided by 512 + static let Div512 = Self(rawValue: 0xf) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + struct SWValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// HSI selected as system clock + static let HSI = Self(rawValue: 0x0) + + /// HSE selected as system clock + static let HSE = Self(rawValue: 0x1) + + /// PLL selected as system clock + static let PLL = Self(rawValue: 0x2) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CIR { + struct LSIRDYIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt disabled + static let Disabled = Self(rawValue: 0x0) + + /// Interrupt enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB1RSTR { + struct GPIOARSTValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Reset the selected module + static let Reset = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB2RSTR { + struct DCMIRSTValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Reset the selected module + static let Reset = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB3RSTR { + struct FMCRSTValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Reset the selected module + static let Reset = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB1RSTR { + struct TIM2RSTValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Reset the selected module + static let Reset = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB2RSTR { + struct TIM1RSTValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Reset the selected module + static let Reset = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB1ENR { + struct GPIOAENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// The selected clock is disabled + static let Disabled = Self(rawValue: 0x0) + + /// The selected clock is enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB2ENR { + struct DCMIENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// The selected clock is disabled + static let Disabled = Self(rawValue: 0x0) + + /// The selected clock is enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB3ENR { + struct FMCENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// The selected clock is disabled + static let Disabled = Self(rawValue: 0x0) + + /// The selected clock is enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB1ENR { + struct TIM2ENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// The selected clock is disabled + static let Disabled = Self(rawValue: 0x0) + + /// The selected clock is enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB2ENR { + struct TIM1ENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// The selected clock is disabled + static let Disabled = Self(rawValue: 0x0) + + /// The selected clock is enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB1LPENR { + struct GPIOALPENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Selected module is disabled during Sleep mode + static let DisabledInSleep = Self(rawValue: 0x0) + + /// Selected module is enabled during Sleep mode + static let EnabledInSleep = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB2LPENR { + struct DCMILPENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Selected module is disabled during Sleep mode + static let DisabledInSleep = Self(rawValue: 0x0) + + /// Selected module is enabled during Sleep mode + static let EnabledInSleep = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB3LPENR { + struct FMCLPENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Selected module is disabled during Sleep mode + static let DisabledInSleep = Self(rawValue: 0x0) + + /// Selected module is enabled during Sleep mode + static let EnabledInSleep = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB1LPENR { + struct TIM2LPENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Selected module is disabled during Sleep mode + static let DisabledInSleep = Self(rawValue: 0x0) + + /// Selected module is enabled during Sleep mode + static let EnabledInSleep = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB2LPENR { + struct TIM1LPENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Selected module is disabled during Sleep mode + static let DisabledInSleep = Self(rawValue: 0x0) + + /// Selected module is enabled during Sleep mode + static let EnabledInSleep = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + struct BDRSTValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Reset not activated + static let Disabled = Self(rawValue: 0x0) + + /// Reset the entire RTC domain + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + struct RTCENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// RTC clock disabled + static let Disabled = Self(rawValue: 0x0) + + /// RTC clock enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + struct LSEBYPValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// LSE crystal oscillator not bypassed + static let NotBypassed = Self(rawValue: 0x0) + + /// LSE crystal oscillator bypassed with external clock + static let Bypassed = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + struct LSEONValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// LSE oscillator Off + static let Off = Self(rawValue: 0x0) + + /// LSE oscillator On + static let On = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + struct LSEDRVValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// Low drive capacity + static let Low = Self(rawValue: 0x0) + + /// Medium-high drive capacity + static let MediumHigh = Self(rawValue: 0x1) + + /// Medium-low drive capacity + static let MediumLow = Self(rawValue: 0x2) + + /// High drive capacity + static let High = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + struct RTCSELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// No clock + static let NoClock = Self(rawValue: 0x0) + + /// LSE oscillator clock used as RTC clock + static let LSE = Self(rawValue: 0x1) + + /// LSI oscillator clock used as RTC clock + static let LSI = Self(rawValue: 0x2) + + /// HSE oscillator clock divided by a prescaler used as RTC clock + static let HSE = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CSR { + struct LSIONValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// LSI oscillator Off + static let Off = Self(rawValue: 0x0) + + /// LSI oscillator On + static let On = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.SSCGR { + struct SSCGENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Spread spectrum modulation disabled + static let Disabled = Self(rawValue: 0x0) + + /// Spread spectrum modulation enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.SSCGR { + struct SPREADSELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Center spread + static let Center = Self(rawValue: 0x0) + + /// Down spread + static let Down = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.PLLI2SCFGR { + struct PLLI2SPValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// PLL*P=2 + static let Div2 = Self(rawValue: 0x0) + + /// PLL*P=4 + static let Div4 = Self(rawValue: 0x1) + + /// PLL*P=6 + static let Div6 = Self(rawValue: 0x2) + + /// PLL*P=8 + static let Div8 = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.PLLSAICFGR { + struct PLLSAIPValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// PLL*P=2 + static let Div2 = Self(rawValue: 0x0) + + /// PLL*P=4 + static let Div4 = Self(rawValue: 0x1) + + /// PLL*P=6 + static let Div6 = Self(rawValue: 0x2) + + /// PLL*P=8 + static let Div8 = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + struct PLLI2SDIVQValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 5 + + /// PLLI2SDIVQ = /1 + static let Div1 = Self(rawValue: 0x0) + + /// PLLI2SDIVQ = /2 + static let Div2 = Self(rawValue: 0x1) + + /// PLLI2SDIVQ = /3 + static let Div3 = Self(rawValue: 0x2) + + /// PLLI2SDIVQ = /4 + static let Div4 = Self(rawValue: 0x3) + + /// PLLI2SDIVQ = /5 + static let Div5 = Self(rawValue: 0x4) + + /// PLLI2SDIVQ = /6 + static let Div6 = Self(rawValue: 0x5) + + /// PLLI2SDIVQ = /7 + static let Div7 = Self(rawValue: 0x6) + + /// PLLI2SDIVQ = /8 + static let Div8 = Self(rawValue: 0x7) + + /// PLLI2SDIVQ = /9 + static let Div9 = Self(rawValue: 0x8) + + /// PLLI2SDIVQ = /10 + static let Div10 = Self(rawValue: 0x9) + + /// PLLI2SDIVQ = /11 + static let Div11 = Self(rawValue: 0xa) + + /// PLLI2SDIVQ = /12 + static let Div12 = Self(rawValue: 0xb) + + /// PLLI2SDIVQ = /13 + static let Div13 = Self(rawValue: 0xc) + + /// PLLI2SDIVQ = /14 + static let Div14 = Self(rawValue: 0xd) + + /// PLLI2SDIVQ = /15 + static let Div15 = Self(rawValue: 0xe) + + /// PLLI2SDIVQ = /16 + static let Div16 = Self(rawValue: 0xf) + + /// PLLI2SDIVQ = /17 + static let Div17 = Self(rawValue: 0x10) + + /// PLLI2SDIVQ = /18 + static let Div18 = Self(rawValue: 0x11) + + /// PLLI2SDIVQ = /19 + static let Div19 = Self(rawValue: 0x12) + + /// PLLI2SDIVQ = /20 + static let Div20 = Self(rawValue: 0x13) + + /// PLLI2SDIVQ = /21 + static let Div21 = Self(rawValue: 0x14) + + /// PLLI2SDIVQ = /22 + static let Div22 = Self(rawValue: 0x15) + + /// PLLI2SDIVQ = /23 + static let Div23 = Self(rawValue: 0x16) + + /// PLLI2SDIVQ = /24 + static let Div24 = Self(rawValue: 0x17) + + /// PLLI2SDIVQ = /25 + static let Div25 = Self(rawValue: 0x18) + + /// PLLI2SDIVQ = /26 + static let Div26 = Self(rawValue: 0x19) + + /// PLLI2SDIVQ = /27 + static let Div27 = Self(rawValue: 0x1a) + + /// PLLI2SDIVQ = /28 + static let Div28 = Self(rawValue: 0x1b) + + /// PLLI2SDIVQ = /29 + static let Div29 = Self(rawValue: 0x1c) + + /// PLLI2SDIVQ = /30 + static let Div30 = Self(rawValue: 0x1d) + + /// PLLI2SDIVQ = /31 + static let Div31 = Self(rawValue: 0x1e) + + /// PLLI2SDIVQ = /32 + static let Div32 = Self(rawValue: 0x1f) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + struct PLLSAIDIVQValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 5 + + /// PLLSAIDIVQ = /1 + static let Div1 = Self(rawValue: 0x0) + + /// PLLSAIDIVQ = /2 + static let Div2 = Self(rawValue: 0x1) + + /// PLLSAIDIVQ = /3 + static let Div3 = Self(rawValue: 0x2) + + /// PLLSAIDIVQ = /4 + static let Div4 = Self(rawValue: 0x3) + + /// PLLSAIDIVQ = /5 + static let Div5 = Self(rawValue: 0x4) + + /// PLLSAIDIVQ = /6 + static let Div6 = Self(rawValue: 0x5) + + /// PLLSAIDIVQ = /7 + static let Div7 = Self(rawValue: 0x6) + + /// PLLSAIDIVQ = /8 + static let Div8 = Self(rawValue: 0x7) + + /// PLLSAIDIVQ = /9 + static let Div9 = Self(rawValue: 0x8) + + /// PLLSAIDIVQ = /10 + static let Div10 = Self(rawValue: 0x9) + + /// PLLSAIDIVQ = /11 + static let Div11 = Self(rawValue: 0xa) + + /// PLLSAIDIVQ = /12 + static let Div12 = Self(rawValue: 0xb) + + /// PLLSAIDIVQ = /13 + static let Div13 = Self(rawValue: 0xc) + + /// PLLSAIDIVQ = /14 + static let Div14 = Self(rawValue: 0xd) + + /// PLLSAIDIVQ = /15 + static let Div15 = Self(rawValue: 0xe) + + /// PLLSAIDIVQ = /16 + static let Div16 = Self(rawValue: 0xf) + + /// PLLSAIDIVQ = /17 + static let Div17 = Self(rawValue: 0x10) + + /// PLLSAIDIVQ = /18 + static let Div18 = Self(rawValue: 0x11) + + /// PLLSAIDIVQ = /19 + static let Div19 = Self(rawValue: 0x12) + + /// PLLSAIDIVQ = /20 + static let Div20 = Self(rawValue: 0x13) + + /// PLLSAIDIVQ = /21 + static let Div21 = Self(rawValue: 0x14) + + /// PLLSAIDIVQ = /22 + static let Div22 = Self(rawValue: 0x15) + + /// PLLSAIDIVQ = /23 + static let Div23 = Self(rawValue: 0x16) + + /// PLLSAIDIVQ = /24 + static let Div24 = Self(rawValue: 0x17) + + /// PLLSAIDIVQ = /25 + static let Div25 = Self(rawValue: 0x18) + + /// PLLSAIDIVQ = /26 + static let Div26 = Self(rawValue: 0x19) + + /// PLLSAIDIVQ = /27 + static let Div27 = Self(rawValue: 0x1a) + + /// PLLSAIDIVQ = /28 + static let Div28 = Self(rawValue: 0x1b) + + /// PLLSAIDIVQ = /29 + static let Div29 = Self(rawValue: 0x1c) + + /// PLLSAIDIVQ = /30 + static let Div30 = Self(rawValue: 0x1d) + + /// PLLSAIDIVQ = /31 + static let Div31 = Self(rawValue: 0x1e) + + /// PLLSAIDIVQ = /32 + static let Div32 = Self(rawValue: 0x1f) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + struct PLLSAIDIVRValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// PLLSAIDIVR = /2 + static let Div2 = Self(rawValue: 0x0) + + /// PLLSAIDIVR = /4 + static let Div4 = Self(rawValue: 0x1) + + /// PLLSAIDIVR = /8 + static let Div8 = Self(rawValue: 0x2) + + /// PLLSAIDIVR = /16 + static let Div16 = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + struct SAI1SELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + static let PLLSAI = Self(rawValue: 0x0) + + /// SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + static let PLLI2S = Self(rawValue: 0x1) + + /// SAI1 clock frequency = Alternate function input frequency + static let AFIF = Self(rawValue: 0x2) + + /// SAI1 clock frequency = HSI or HSE + static let HSI_HSE = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + struct SAI2SELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + static let PLLSAI = Self(rawValue: 0x0) + + /// SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + static let PLLI2S = Self(rawValue: 0x1) + + /// SAI2 clock frequency = Alternate function input frequency + static let AFIF = Self(rawValue: 0x2) + + /// SAI2 clock frequency = HSI or HSE + static let HSI_HSE = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + struct TIMPREValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx + static let Mul1Or2 = Self(rawValue: 0x0) + + /// If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx + static let Mul1Or4 = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + struct USART1SELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// APB2 clock (PCLK2) is selected as USART clock + static let APB2 = Self(rawValue: 0x0) + + /// System clock is selected as USART clock + static let SYSCLK = Self(rawValue: 0x1) + + /// HSI clock is selected as USART clock + static let HSI = Self(rawValue: 0x2) + + /// LSE clock is selected as USART clock + static let LSE = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + struct USART2SELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// APB1 clock (PCLK1) is selected as USART clock + static let APB1 = Self(rawValue: 0x0) + + /// System clock is selected as USART clock + static let SYSCLK = Self(rawValue: 0x1) + + /// HSI clock is selected as USART clock + static let HSI = Self(rawValue: 0x2) + + /// LSE clock is selected as USART clock + static let LSE = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + struct I2C1SELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// APB clock selected as I2C clock + static let APB = Self(rawValue: 0x0) + + /// System clock selected as I2C clock + static let SYSCLK = Self(rawValue: 0x1) + + /// HSI clock selected as I2C clock + static let HSI = Self(rawValue: 0x2) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + struct LPTIM1SELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// APB1 clock (PCLK1) selected as LPTILM1 clock + static let APB1 = Self(rawValue: 0x0) + + /// LSI clock is selected as LPTILM1 clock + static let LSI = Self(rawValue: 0x1) + + /// HSI clock is selected as LPTILM1 clock + static let HSI = Self(rawValue: 0x2) + + /// LSE clock is selected as LPTILM1 clock + static let LSE = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + struct CECSELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// LSE clock is selected as HDMI-CEC clock + static let LSE = Self(rawValue: 0x0) + + /// HSI divided by 488 clock is selected as HDMI-CEC clock + static let HSI_Div488 = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + struct CK48MSELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// 48MHz clock from PLL is selected + static let PLL = Self(rawValue: 0x0) + + /// 48MHz clock from PLLSAI is selected + static let PLLSAI = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + struct SDMMC1SELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// 48 MHz clock is selected as SD clock + static let CK48M = Self(rawValue: 0x0) + + /// System clock is selected as SD clock + static let SYSCLK = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } } } diff --git a/stm32-neopixel/Sources/Application/Registers/SPI1.swift b/stm32-neopixel/Sources/Application/Registers/SPI1.swift new file mode 100644 index 00000000..d182ff40 --- /dev/null +++ b/stm32-neopixel/Sources/Application/Registers/SPI1.swift @@ -0,0 +1,1043 @@ +// Generated by svd2swift. + +import MMIO + +/// Serial peripheral interface +@RegisterBlock +struct SPI1 { + /// control register 1 + @RegisterBlock(offset: 0x0) + var cr1: Register + + /// control register 2 + @RegisterBlock(offset: 0x4) + var cr2: Register + + /// status register + @RegisterBlock(offset: 0x8) + var sr: Register + + /// data register + @RegisterBlock(offset: 0xc) + var dr: Register + + /// CRC polynomial register + @RegisterBlock(offset: 0x10) + var crcpr: Register + + /// RX CRC register + @RegisterBlock(offset: 0x14) + var rxcrcr: Register + + /// TX CRC register + @RegisterBlock(offset: 0x18) + var txcrcr: Register + + /// I2S configuration register + @RegisterBlock(offset: 0x1c) + var i2scfgr: Register + + /// I2S prescaler register + @RegisterBlock(offset: 0x20) + var i2spr: Register +} + +extension SPI1 { + /// control register 1 + @Register(bitWidth: 32) + struct CR1 { + /// Bidirectional data mode enable + @ReadWrite(bits: 15..<16, as: BIDIMODEValues.self) + var bidimode: BIDIMODE + + /// Output enable in bidirectional mode + @ReadWrite(bits: 14..<15, as: BIDIOEValues.self) + var bidioe: BIDIOE + + /// Hardware CRC calculation enable + @ReadWrite(bits: 13..<14, as: CRCENValues.self) + var crcen: CRCEN + + /// CRC transfer next + @ReadWrite(bits: 12..<13, as: CRCNEXTValues.self) + var crcnext: CRCNEXT + + /// CRC length + @ReadWrite(bits: 11..<12, as: CRCLValues.self) + var crcl: CRCL + + /// Receive only + @ReadWrite(bits: 10..<11, as: RXONLYValues.self) + var rxonly: RXONLY + + /// Software slave management + @ReadWrite(bits: 9..<10, as: SSMValues.self) + var ssm: SSM + + /// Internal slave select + @ReadWrite(bits: 8..<9, as: SSIValues.self) + var ssi: SSI + + /// Frame format + @ReadWrite(bits: 7..<8, as: LSBFIRSTValues.self) + var lsbfirst: LSBFIRST + + /// SPI enable + @ReadWrite(bits: 6..<7, as: SPEValues.self) + var spe: SPE + + /// Baud rate control + @ReadWrite(bits: 3..<6, as: BRValues.self) + var br: BR + + /// Master selection + @ReadWrite(bits: 2..<3, as: MSTRValues.self) + var mstr: MSTR + + /// Clock polarity + @ReadWrite(bits: 1..<2, as: CPOLValues.self) + var cpol: CPOL + + /// Clock phase + @ReadWrite(bits: 0..<1, as: CPHAValues.self) + var cpha: CPHA + } + + /// control register 2 + @Register(bitWidth: 32) + struct CR2 { + /// Rx buffer DMA enable + @ReadWrite(bits: 0..<1, as: RXDMAENValues.self) + var rxdmaen: RXDMAEN + + /// Tx buffer DMA enable + @ReadWrite(bits: 1..<2, as: TXDMAENValues.self) + var txdmaen: TXDMAEN + + /// SS output enable + @ReadWrite(bits: 2..<3, as: SSOEValues.self) + var ssoe: SSOE + + /// NSS pulse management + @ReadWrite(bits: 3..<4, as: NSSPValues.self) + var nssp: NSSP + + /// Frame format + @ReadWrite(bits: 4..<5, as: FRFValues.self) + var frf: FRF + + /// Error interrupt enable + @ReadWrite(bits: 5..<6, as: ERRIEValues.self) + var errie: ERRIE + + /// RX buffer not empty interrupt enable + @ReadWrite(bits: 6..<7, as: RXNEIEValues.self) + var rxneie: RXNEIE + + /// Tx buffer empty interrupt enable + @ReadWrite(bits: 7..<8, as: TXEIEValues.self) + var txeie: TXEIE + + /// Data size + @ReadWrite(bits: 8..<12, as: DSValues.self) + var ds: DS + + /// FIFO reception threshold + @ReadWrite(bits: 12..<13, as: FRXTHValues.self) + var frxth: FRXTH + + /// Last DMA transfer for reception + @ReadWrite(bits: 13..<14, as: LDMA_RXValues.self) + var ldma_rx: LDMA_RX + + /// Last DMA transfer for transmission + @ReadWrite(bits: 14..<15, as: LDMA_TXValues.self) + var ldma_tx: LDMA_TX + } + + /// status register + @Register(bitWidth: 32) + struct SR { + /// Frame format error + @ReadOnly(bits: 8..<9) + var fre: FRE + + /// Busy flag + @ReadOnly(bits: 7..<8) + var bsy: BSY + + /// Overrun flag + @ReadOnly(bits: 6..<7) + var ovr: OVR + + /// Mode fault + @ReadOnly(bits: 5..<6) + var modf: MODF + + /// CRC error flag + @ReadWrite(bits: 4..<5) + var crcerr: CRCERR + + /// Underrun flag + @ReadOnly(bits: 3..<4) + var udr: UDR + + /// Channel side + @ReadOnly(bits: 2..<3) + var chside: CHSIDE + + /// Transmit buffer empty + @ReadOnly(bits: 1..<2) + var txe: TXE + + /// Receive buffer not empty + @ReadOnly(bits: 0..<1) + var rxne: RXNE + + /// FIFO reception level + @ReadOnly(bits: 9..<11) + var frlvl: FRLVL + + /// FIFO Transmission Level + @ReadOnly(bits: 11..<13) + var ftlvl: FTLVL + } + + /// data register + @Register(bitWidth: 32) + struct DR { + /// Data register + @ReadWrite(bits: 0..<16) + var dr_field: DR_FIELD + } + + /// CRC polynomial register + @Register(bitWidth: 32) + struct CRCPR { + /// CRC polynomial register + @ReadWrite(bits: 0..<16) + var crcpoly: CRCPOLY + } + + /// RX CRC register + @Register(bitWidth: 32) + struct RXCRCR { + /// Rx CRC register + @ReadOnly(bits: 0..<16) + var rxcrc: RxCRC + } + + /// TX CRC register + @Register(bitWidth: 32) + struct TXCRCR { + /// Tx CRC register + @ReadOnly(bits: 0..<16) + var txcrc: TxCRC + } + + /// I2S configuration register + @Register(bitWidth: 32) + struct I2SCFGR { + /// I2S mode selection + @ReadWrite(bits: 11..<12, as: I2SMODValues.self) + var i2smod: I2SMOD + + /// I2S Enable + @ReadWrite(bits: 10..<11, as: I2SEValues.self) + var i2se: I2SE + + /// I2S configuration mode + @ReadWrite(bits: 8..<10, as: I2SCFGValues.self) + var i2scfg: I2SCFG + + /// PCM frame synchronization + @ReadWrite(bits: 7..<8, as: PCMSYNCValues.self) + var pcmsync: PCMSYNC + + /// I2S standard selection + @ReadWrite(bits: 4..<6, as: I2SSTDValues.self) + var i2sstd: I2SSTD + + /// Steady state clock polarity + @ReadWrite(bits: 3..<4, as: CKPOLValues.self) + var ckpol: CKPOL + + /// Data length to be transferred + @ReadWrite(bits: 1..<3, as: DATLENValues.self) + var datlen: DATLEN + + /// Channel length (number of bits per audio channel) + @ReadWrite(bits: 0..<1, as: CHLENValues.self) + var chlen: CHLEN + + /// Asynchronous start enable + @ReadWrite(bits: 12..<13) + var astrten: ASTRTEN + } + + /// I2S prescaler register + @Register(bitWidth: 32) + struct I2SPR { + /// Master clock output enable + @ReadWrite(bits: 9..<10, as: MCKOEValues.self) + var mckoe: MCKOE + + /// Odd factor for the prescaler + @ReadWrite(bits: 8..<9, as: ODDValues.self) + var odd: ODD + + /// I2S Linear prescaler + @ReadWrite(bits: 0..<8) + var i2sdiv: I2SDIV + } +} + +extension SPI1.CR1 { + struct BIDIMODEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// 2-line unidirectional data mode selected + static let Unidirectional = Self(rawValue: 0x0) + + /// 1-line bidirectional data mode selected + static let Bidirectional = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + struct BIDIOEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Output disabled (receive-only mode) + static let OutputDisabled = Self(rawValue: 0x0) + + /// Output enabled (transmit-only mode) + static let OutputEnabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + struct CRCENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// CRC calculation disabled + static let Disabled = Self(rawValue: 0x0) + + /// CRC calculation enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + struct CRCNEXTValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Next transmit value is from Tx buffer + static let TxBuffer = Self(rawValue: 0x0) + + /// Next transmit value is from Tx CRC register + static let CRC = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + struct CRCLValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// 8-bit CRC length + static let EightBit = Self(rawValue: 0x0) + + /// 16-bit CRC length + static let SixteenBit = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + struct RXONLYValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Full duplex (Transmit and receive) + static let FullDuplex = Self(rawValue: 0x0) + + /// Output disabled (Receive-only mode) + static let OutputDisabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + struct SSMValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Software slave management disabled + static let Disabled = Self(rawValue: 0x0) + + /// Software slave management enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + struct SSIValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored + static let SlaveSelected = Self(rawValue: 0x0) + + /// 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored + static let SlaveNotSelected = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + struct LSBFIRSTValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Data is transmitted/received with the MSB first + static let MSBFirst = Self(rawValue: 0x0) + + /// Data is transmitted/received with the LSB first + static let LSBFirst = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + struct SPEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Peripheral disabled + static let Disabled = Self(rawValue: 0x0) + + /// Peripheral enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + struct BRValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 3 + + /// f_PCLK / 2 + static let Div2 = Self(rawValue: 0x0) + + /// f_PCLK / 4 + static let Div4 = Self(rawValue: 0x1) + + /// f_PCLK / 8 + static let Div8 = Self(rawValue: 0x2) + + /// f_PCLK / 16 + static let Div16 = Self(rawValue: 0x3) + + /// f_PCLK / 32 + static let Div32 = Self(rawValue: 0x4) + + /// f_PCLK / 64 + static let Div64 = Self(rawValue: 0x5) + + /// f_PCLK / 128 + static let Div128 = Self(rawValue: 0x6) + + /// f_PCLK / 256 + static let Div256 = Self(rawValue: 0x7) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + struct MSTRValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Slave configuration + static let Slave = Self(rawValue: 0x0) + + /// Master configuration + static let Master = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + struct CPOLValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// CK to 0 when idle + static let IdleLow = Self(rawValue: 0x0) + + /// CK to 1 when idle + static let IdleHigh = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + struct CPHAValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// The first clock transition is the first data capture edge + static let FirstEdge = Self(rawValue: 0x0) + + /// The second clock transition is the first data capture edge + static let SecondEdge = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + struct RXDMAENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Rx buffer DMA disabled + static let Disabled = Self(rawValue: 0x0) + + /// Rx buffer DMA enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + struct TXDMAENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Tx buffer DMA disabled + static let Disabled = Self(rawValue: 0x0) + + /// Tx buffer DMA enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + struct SSOEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// SS output is disabled in master mode + static let Disabled = Self(rawValue: 0x0) + + /// SS output is enabled in master mode + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + struct NSSPValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// No NSS pulse + static let NoPulse = Self(rawValue: 0x0) + + /// NSS pulse generated + static let PulseGenerated = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + struct FRFValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// SPI Motorola mode + static let Motorola = Self(rawValue: 0x0) + + /// SPI TI mode + static let TI = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + struct ERRIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Error interrupt masked + static let Masked = Self(rawValue: 0x0) + + /// Error interrupt not masked + static let NotMasked = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + struct RXNEIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// RXE interrupt masked + static let Masked = Self(rawValue: 0x0) + + /// RXE interrupt not masked + static let NotMasked = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + struct TXEIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// TXE interrupt masked + static let Masked = Self(rawValue: 0x0) + + /// TXE interrupt not masked + static let NotMasked = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + struct DSValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 4 + + /// 4-bit + static let FourBit = Self(rawValue: 0x3) + + /// 5-bit + static let FiveBit = Self(rawValue: 0x4) + + /// 6-bit + static let SixBit = Self(rawValue: 0x5) + + /// 7-bit + static let SevenBit = Self(rawValue: 0x6) + + /// 8-bit + static let EightBit = Self(rawValue: 0x7) + + /// 9-bit + static let NineBit = Self(rawValue: 0x8) + + /// 10-bit + static let TenBit = Self(rawValue: 0x9) + + /// 11-bit + static let ElevenBit = Self(rawValue: 0xa) + + /// 12-bit + static let TwelveBit = Self(rawValue: 0xb) + + /// 13-bit + static let ThirteenBit = Self(rawValue: 0xc) + + /// 14-bit + static let FourteenBit = Self(rawValue: 0xd) + + /// 15-bit + static let FifteenBit = Self(rawValue: 0xe) + + /// 16-bit + static let SixteenBit = Self(rawValue: 0xf) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + struct FRXTHValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) + static let Half = Self(rawValue: 0x0) + + /// RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + static let Quarter = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + struct LDMA_RXValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Number of data to transfer for receive is even + static let Even = Self(rawValue: 0x0) + + /// Number of data to transfer for receive is odd + static let Odd = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + struct LDMA_TXValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Number of data to transfer for transmit is even + static let Even = Self(rawValue: 0x0) + + /// Number of data to transfer for transmit is odd + static let Odd = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.I2SCFGR { + struct I2SMODValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// SPI mode is selected + static let SPIMode = Self(rawValue: 0x0) + + /// I2S mode is selected + static let I2SMode = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.I2SCFGR { + struct I2SEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// I2S peripheral is disabled + static let Disabled = Self(rawValue: 0x0) + + /// I2S peripheral is enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.I2SCFGR { + struct I2SCFGValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// Slave - transmit + static let SlaveTx = Self(rawValue: 0x0) + + /// Slave - receive + static let SlaveRx = Self(rawValue: 0x1) + + /// Master - transmit + static let MasterTx = Self(rawValue: 0x2) + + /// Master - receive + static let MasterRx = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.I2SCFGR { + struct PCMSYNCValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Short frame synchronisation + static let Short = Self(rawValue: 0x0) + + /// Long frame synchronisation + static let Long = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.I2SCFGR { + struct I2SSTDValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// I2S Philips standard + static let Philips = Self(rawValue: 0x0) + + /// MSB justified standard + static let MSB = Self(rawValue: 0x1) + + /// LSB justified standard + static let LSB = Self(rawValue: 0x2) + + /// PCM standard + static let PCM = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.I2SCFGR { + struct CKPOLValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// I2S clock inactive state is low level + static let IdleLow = Self(rawValue: 0x0) + + /// I2S clock inactive state is high level + static let IdleHigh = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.I2SCFGR { + struct DATLENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// 16-bit data length + static let SixteenBit = Self(rawValue: 0x0) + + /// 24-bit data length + static let TwentyFourBit = Self(rawValue: 0x1) + + /// 32-bit data length + static let ThirtyTwoBit = Self(rawValue: 0x2) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.I2SCFGR { + struct CHLENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// 16-bit wide + static let SixteenBit = Self(rawValue: 0x0) + + /// 32-bit wide + static let ThirtyTwoBit = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.I2SPR { + struct MCKOEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Master clock output is disabled + static let Disabled = Self(rawValue: 0x0) + + /// Master clock output is enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.I2SPR { + struct ODDValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Real divider value is I2SDIV * 2 + static let Even = Self(rawValue: 0x0) + + /// Real divider value is (I2SDIV * 2) + 1 + static let Odd = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} diff --git a/stm32-neopixel/Sources/Application/Registers/SPI2.swift b/stm32-neopixel/Sources/Application/Registers/SPI2.swift index 5bb2e7b0..2e66bcc9 100644 --- a/stm32-neopixel/Sources/Application/Registers/SPI2.swift +++ b/stm32-neopixel/Sources/Application/Registers/SPI2.swift @@ -1,295 +1,7 @@ // Generated by svd2swift. -// swift-format-ignore-file - import MMIO /// Serial peripheral interface -@RegisterBlock -struct SPI2 { - /// control register 1 - @RegisterBlock(offset: 0x0) - var cr1: Register - - /// control register 2 - @RegisterBlock(offset: 0x4) - var cr2: Register - - /// status register - @RegisterBlock(offset: 0x8) - var sr: Register - - /// data register - @RegisterBlock(offset: 0xc) - var dr: Register - - /// CRC polynomial register - @RegisterBlock(offset: 0x10) - var crcpr: Register - - /// RX CRC register - @RegisterBlock(offset: 0x14) - var rxcrcr: Register - - /// TX CRC register - @RegisterBlock(offset: 0x18) - var txcrcr: Register - - /// I2S configuration register - @RegisterBlock(offset: 0x1c) - var i2scfgr: Register - - /// I2S prescaler register - @RegisterBlock(offset: 0x20) - var i2spr: Register -} - -extension SPI2 { - /// control register 1 - @Register(bitWidth: 32) - struct CR1 { - /// Bidirectional data mode enable - @ReadWrite(bits: 15..<16) - var bidimode: BIDIMODE - - /// Output enable in bidirectional mode - @ReadWrite(bits: 14..<15) - var bidioe: BIDIOE - - /// Hardware CRC calculation enable - @ReadWrite(bits: 13..<14) - var crcen: CRCEN - - /// CRC transfer next - @ReadWrite(bits: 12..<13) - var crcnext: CRCNEXT - - /// CRC length - @ReadWrite(bits: 11..<12) - var crcl: CRCL - - /// Receive only - @ReadWrite(bits: 10..<11) - var rxonly: RXONLY - - /// Software slave management - @ReadWrite(bits: 9..<10) - var ssm: SSM - - /// Internal slave select - @ReadWrite(bits: 8..<9) - var ssi: SSI - - /// Frame format - @ReadWrite(bits: 7..<8) - var lsbfirst: LSBFIRST - - /// SPI enable - @ReadWrite(bits: 6..<7) - var spe: SPE - - /// Baud rate control - @ReadWrite(bits: 3..<6) - var br: BR - - /// Master selection - @ReadWrite(bits: 2..<3) - var mstr: MSTR - - /// Clock polarity - @ReadWrite(bits: 1..<2) - var cpol: CPOL - - /// Clock phase - @ReadWrite(bits: 0..<1) - var cpha: CPHA - } - - /// control register 2 - @Register(bitWidth: 32) - struct CR2 { - /// Rx buffer DMA enable - @ReadWrite(bits: 0..<1) - var rxdmaen: RXDMAEN - - /// Tx buffer DMA enable - @ReadWrite(bits: 1..<2) - var txdmaen: TXDMAEN - - /// SS output enable - @ReadWrite(bits: 2..<3) - var ssoe: SSOE - - /// NSS pulse management - @ReadWrite(bits: 3..<4) - var nssp: NSSP - - /// Frame format - @ReadWrite(bits: 4..<5) - var frf: FRF - - /// Error interrupt enable - @ReadWrite(bits: 5..<6) - var errie: ERRIE - - /// RX buffer not empty interrupt enable - @ReadWrite(bits: 6..<7) - var rxneie: RXNEIE - - /// Tx buffer empty interrupt enable - @ReadWrite(bits: 7..<8) - var txeie: TXEIE - - /// Data size - @ReadWrite(bits: 8..<12) - var ds: DS - - /// FIFO reception threshold - @ReadWrite(bits: 12..<13) - var frxth: FRXTH - - /// Last DMA transfer for reception - @ReadWrite(bits: 13..<14) - var ldma_rx: LDMA_RX - - /// Last DMA transfer for transmission - @ReadWrite(bits: 14..<15) - var ldma_tx: LDMA_TX - } - - /// status register - @Register(bitWidth: 32) - struct SR { - /// Busy flag - @ReadOnly(bits: 7..<8) - var bsy: BSY - - /// Overrun flag - @ReadOnly(bits: 6..<7) - var ovr: OVR - - /// Mode fault - @ReadOnly(bits: 5..<6) - var modf: MODF - - /// CRC error flag - @ReadWrite(bits: 4..<5) - var crcerr: CRCERR - - /// Underrun flag - @ReadOnly(bits: 3..<4) - var udr: UDR - - /// Channel side - @ReadOnly(bits: 2..<3) - var chside: CHSIDE - - /// Transmit buffer empty - @ReadOnly(bits: 1..<2) - var txe: TXE - - /// Receive buffer not empty - @ReadOnly(bits: 0..<1) - var rxne: RXNE - - /// Frame format error - @ReadOnly(bits: 8..<9) - var fre: FRE - - /// FIFO reception level - @ReadOnly(bits: 9..<11) - var frlvl: FRLVL - - /// FIFO Transmission Level - @ReadOnly(bits: 11..<13) - var ftlvl: FTLVL - } - - /// data register - @Register(bitWidth: 32) - struct DR { - /// Data register - @ReadWrite(bits: 0..<16) - var dr_field: DR_FIELD - } - - /// CRC polynomial register - @Register(bitWidth: 32) - struct CRCPR { - /// CRC polynomial register - @ReadWrite(bits: 0..<16) - var crcpoly: CRCPOLY - } - - /// RX CRC register - @Register(bitWidth: 32) - struct RXCRCR { - /// Rx CRC register - @ReadOnly(bits: 0..<16) - var rxcrc: RxCRC - } - - /// TX CRC register - @Register(bitWidth: 32) - struct TXCRCR { - /// Tx CRC register - @ReadOnly(bits: 0..<16) - var txcrc: TxCRC - } - - /// I2S configuration register - @Register(bitWidth: 32) - struct I2SCFGR { - /// I2S mode selection - @ReadWrite(bits: 11..<12) - var i2smod: I2SMOD - - /// I2S Enable - @ReadWrite(bits: 10..<11) - var i2se: I2SE - - /// I2S configuration mode - @ReadWrite(bits: 8..<10) - var i2scfg: I2SCFG - - /// PCM frame synchronization - @ReadWrite(bits: 7..<8) - var pcmsync: PCMSYNC - - /// I2S standard selection - @ReadWrite(bits: 4..<6) - var i2sstd: I2SSTD - - /// Steady state clock polarity - @ReadWrite(bits: 3..<4) - var ckpol: CKPOL - - /// Data length to be transferred - @ReadWrite(bits: 1..<3) - var datlen: DATLEN - - /// Channel length (number of bits per audio channel) - @ReadWrite(bits: 0..<1) - var chlen: CHLEN - - /// Asynchronous start enable - @ReadWrite(bits: 12..<13) - var astrten: ASTRTEN - } - - /// I2S prescaler register - @Register(bitWidth: 32) - struct I2SPR { - /// Master clock output enable - @ReadWrite(bits: 9..<10) - var mckoe: MCKOE - - /// Odd factor for the prescaler - @ReadWrite(bits: 8..<9) - var odd: ODD +typealias SPI2 = SPI1 - /// I2S Linear prescaler - @ReadWrite(bits: 0..<8) - var i2sdiv: I2SDIV - } -} diff --git a/stm32-neopixel/Sources/Application/Registers/USART1.swift b/stm32-neopixel/Sources/Application/Registers/USART1.swift index 19cc4ee3..6230310f 100644 --- a/stm32-neopixel/Sources/Application/Registers/USART1.swift +++ b/stm32-neopixel/Sources/Application/Registers/USART1.swift @@ -1,7 +1,5 @@ // Generated by svd2swift. -// swift-format-ignore-file - import MMIO /// Universal synchronous asynchronous receiver transmitter @@ -57,215 +55,175 @@ extension USART1 { @Register(bitWidth: 32) struct CR1 { /// Word length - @ReadWrite(bits: 28..<29) + @ReadWrite(bits: 28..<29, as: M1Values.self) var m1: M1 /// End of Block interrupt enable - @ReadWrite(bits: 27..<28) + @ReadWrite(bits: 27..<28, as: EOBIEValues.self) var eobie: EOBIE /// Receiver timeout interrupt enable - @ReadWrite(bits: 26..<27) + @ReadWrite(bits: 26..<27, as: RTOIEValues.self) var rtoie: RTOIE - /// Driver Enable assertion time - @ReadWrite(bits: 25..<26) - var deat4: DEAT4 - - /// DEAT3 - @ReadWrite(bits: 24..<25) - var deat3: DEAT3 - - /// DEAT2 - @ReadWrite(bits: 23..<24) - var deat2: DEAT2 - - /// DEAT1 - @ReadWrite(bits: 22..<23) - var deat1: DEAT1 - - /// DEAT0 - @ReadWrite(bits: 21..<22) - var deat0: DEAT0 - - /// Driver Enable de-assertion time - @ReadWrite(bits: 20..<21) - var dedt4: DEDT4 - - /// DEDT3 - @ReadWrite(bits: 19..<20) - var dedt3: DEDT3 - - /// DEDT2 - @ReadWrite(bits: 18..<19) - var dedt2: DEDT2 - - /// DEDT1 - @ReadWrite(bits: 17..<18) - var dedt1: DEDT1 - - /// DEDT0 - @ReadWrite(bits: 16..<17) - var dedt0: DEDT0 - /// Oversampling mode - @ReadWrite(bits: 15..<16) + @ReadWrite(bits: 15..<16, as: OVER8Values.self) var over8: OVER8 /// Character match interrupt enable - @ReadWrite(bits: 14..<15) + @ReadWrite(bits: 14..<15, as: CMIEValues.self) var cmie: CMIE /// Mute mode enable - @ReadWrite(bits: 13..<14) + @ReadWrite(bits: 13..<14, as: MMEValues.self) var mme: MME /// Word length - @ReadWrite(bits: 12..<13) + @ReadWrite(bits: 12..<13, as: M0Values.self) var m0: M0 /// Receiver wakeup method - @ReadWrite(bits: 11..<12) + @ReadWrite(bits: 11..<12, as: WAKEValues.self) var wake: WAKE /// Parity control enable - @ReadWrite(bits: 10..<11) + @ReadWrite(bits: 10..<11, as: PCEValues.self) var pce: PCE /// Parity selection - @ReadWrite(bits: 9..<10) + @ReadWrite(bits: 9..<10, as: PSValues.self) var ps: PS /// PE interrupt enable - @ReadWrite(bits: 8..<9) + @ReadWrite(bits: 8..<9, as: PEIEValues.self) var peie: PEIE /// interrupt enable - @ReadWrite(bits: 7..<8) + @ReadWrite(bits: 7..<8, as: TXEIEValues.self) var txeie: TXEIE /// Transmission complete interrupt enable - @ReadWrite(bits: 6..<7) + @ReadWrite(bits: 6..<7, as: TCIEValues.self) var tcie: TCIE /// RXNE interrupt enable - @ReadWrite(bits: 5..<6) + @ReadWrite(bits: 5..<6, as: RXNEIEValues.self) var rxneie: RXNEIE /// IDLE interrupt enable - @ReadWrite(bits: 4..<5) + @ReadWrite(bits: 4..<5, as: IDLEIEValues.self) var idleie: IDLEIE /// Transmitter enable - @ReadWrite(bits: 3..<4) + @ReadWrite(bits: 3..<4, as: TEValues.self) var te: TE /// Receiver enable - @ReadWrite(bits: 2..<3) + @ReadWrite(bits: 2..<3, as: REValues.self) var re: RE /// USART enable in Stop mode - @ReadWrite(bits: 1..<2) + @ReadWrite(bits: 1..<2, as: UESMValues.self) var uesm: UESM /// USART enable - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: UEValues.self) var ue: UE + + /// Driver Enable assertion time + @ReadWrite(bits: 21..<26) + var deat: DEAT + + /// Driver Enable de-assertion time + @ReadWrite(bits: 16..<21) + var dedt: DEDT } /// Control register 2 @Register(bitWidth: 32) struct CR2 { - /// Address of the USART node - @ReadWrite(bits: 28..<32) - var add4_7: ADD4_7 - - /// Address of the USART node - @ReadWrite(bits: 24..<28) - var add0_3: ADD0_3 - /// Receiver timeout enable - @ReadWrite(bits: 23..<24) + @ReadWrite(bits: 23..<24, as: RTOENValues.self) var rtoen: RTOEN - /// Auto baud rate mode - @ReadWrite(bits: 22..<23) - var abrmod1: ABRMOD1 - - /// ABRMOD0 - @ReadWrite(bits: 21..<22) - var abrmod0: ABRMOD0 - /// Auto baud rate enable - @ReadWrite(bits: 20..<21) + @ReadWrite(bits: 20..<21, as: ABRENValues.self) var abren: ABREN /// Most significant bit first - @ReadWrite(bits: 19..<20) + @ReadWrite(bits: 19..<20, as: MSBFIRSTValues.self) var msbfirst: MSBFIRST /// Binary data inversion - @ReadWrite(bits: 18..<19) - var tainv: TAINV + @ReadWrite(bits: 18..<19, as: DATAINVValues.self) + var datainv: DATAINV /// TX pin active level inversion - @ReadWrite(bits: 17..<18) + @ReadWrite(bits: 17..<18, as: TXINVValues.self) var txinv: TXINV /// RX pin active level inversion - @ReadWrite(bits: 16..<17) + @ReadWrite(bits: 16..<17, as: RXINVValues.self) var rxinv: RXINV /// Swap TX/RX pins - @ReadWrite(bits: 15..<16) + @ReadWrite(bits: 15..<16, as: SWAPValues.self) var swap: SWAP /// LIN mode enable - @ReadWrite(bits: 14..<15) + @ReadWrite(bits: 14..<15, as: LINENValues.self) var linen: LINEN /// STOP bits - @ReadWrite(bits: 12..<14) + @ReadWrite(bits: 12..<14, as: STOPValues.self) var stop: STOP /// Clock enable - @ReadWrite(bits: 11..<12) + @ReadWrite(bits: 11..<12, as: CLKENValues.self) var clken: CLKEN /// Clock polarity - @ReadWrite(bits: 10..<11) + @ReadWrite(bits: 10..<11, as: CPOLValues.self) var cpol: CPOL /// Clock phase - @ReadWrite(bits: 9..<10) + @ReadWrite(bits: 9..<10, as: CPHAValues.self) var cpha: CPHA /// Last bit clock pulse - @ReadWrite(bits: 8..<9) + @ReadWrite(bits: 8..<9, as: LBCLValues.self) var lbcl: LBCL /// LIN break detection interrupt enable - @ReadWrite(bits: 6..<7) + @ReadWrite(bits: 6..<7, as: LBDIEValues.self) var lbdie: LBDIE /// LIN break detection length - @ReadWrite(bits: 5..<6) + @ReadWrite(bits: 5..<6, as: LBDLValues.self) var lbdl: LBDL /// 7-bit Address Detection/4-bit Address Detection - @ReadWrite(bits: 4..<5) + @ReadWrite(bits: 4..<5, as: ADDM7Values.self) var addm7: ADDM7 + + /// Auto baud rate mode + @ReadWrite(bits: 21..<23, as: ABRMODValues.self) + var abrmod: ABRMOD + + /// Address of the USART node + @ReadWrite(bits: 24..<32) + var add: ADD } /// Control register 3 @Register(bitWidth: 32) struct CR3 { /// Wakeup from Stop mode interrupt enable - @ReadWrite(bits: 22..<23) + @ReadWrite(bits: 22..<23, as: WUFIEValues.self) var wufie: WUFIE /// Wakeup from Stop mode interrupt flag selection - @ReadWrite(bits: 20..<22) + @ReadWrite(bits: 20..<22, as: WUSValues.self) var wus: WUS /// Smartcard auto-retry count @@ -273,67 +231,67 @@ extension USART1 { var scarcnt: SCARCNT /// Driver enable polarity selection - @ReadWrite(bits: 15..<16) + @ReadWrite(bits: 15..<16, as: DEPValues.self) var dep: DEP /// Driver enable mode - @ReadWrite(bits: 14..<15) + @ReadWrite(bits: 14..<15, as: DEMValues.self) var dem: DEM /// DMA Disable on Reception Error - @ReadWrite(bits: 13..<14) + @ReadWrite(bits: 13..<14, as: DDREValues.self) var ddre: DDRE /// Overrun Disable - @ReadWrite(bits: 12..<13) + @ReadWrite(bits: 12..<13, as: OVRDISValues.self) var ovrdis: OVRDIS /// One sample bit method enable - @ReadWrite(bits: 11..<12) + @ReadWrite(bits: 11..<12, as: ONEBITValues.self) var onebit: ONEBIT /// CTS interrupt enable - @ReadWrite(bits: 10..<11) + @ReadWrite(bits: 10..<11, as: CTSIEValues.self) var ctsie: CTSIE /// CTS enable - @ReadWrite(bits: 9..<10) + @ReadWrite(bits: 9..<10, as: CTSEValues.self) var ctse: CTSE /// RTS enable - @ReadWrite(bits: 8..<9) + @ReadWrite(bits: 8..<9, as: RTSEValues.self) var rtse: RTSE /// DMA enable transmitter - @ReadWrite(bits: 7..<8) + @ReadWrite(bits: 7..<8, as: DMATValues.self) var dmat: DMAT /// DMA enable receiver - @ReadWrite(bits: 6..<7) + @ReadWrite(bits: 6..<7, as: DMARValues.self) var dmar: DMAR /// Smartcard mode enable - @ReadWrite(bits: 5..<6) + @ReadWrite(bits: 5..<6, as: SCENValues.self) var scen: SCEN /// Smartcard NACK enable - @ReadWrite(bits: 4..<5) + @ReadWrite(bits: 4..<5, as: NACKValues.self) var nack: NACK /// Half-duplex selection - @ReadWrite(bits: 3..<4) + @ReadWrite(bits: 3..<4, as: HDSELValues.self) var hdsel: HDSEL /// Ir low-power - @ReadWrite(bits: 2..<3) + @ReadWrite(bits: 2..<3, as: IRLPValues.self) var irlp: IRLP /// Ir mode enable - @ReadWrite(bits: 1..<2) + @ReadWrite(bits: 1..<2, as: IRENValues.self) var iren: IREN /// Error interrupt enable - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: EIEValues.self) var eie: EIE } @@ -341,12 +299,8 @@ extension USART1 { @Register(bitWidth: 32) struct BRR { /// DIV_Mantissa - @ReadWrite(bits: 4..<16) - var div_mantissa: DIV_Mantissa - - /// DIV_Fraction - @ReadWrite(bits: 0..<4) - var div_fraction: DIV_Fraction + @ReadWrite(bits: 0..<16) + var brr_field: BRR_FIELD } /// Guard time and prescaler register @@ -557,3 +511,1044 @@ extension USART1 { var tdr_field: TDR_FIELD } } + +extension USART1.CR1 { + struct M1Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Use M0 to set the data bits + static let M0 = Self(rawValue: 0x0) + + /// 1 start bit, 7 data bits, n stop bits + static let Bit7 = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct EOBIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is inhibited + static let Disabled = Self(rawValue: 0x0) + + /// A USART interrupt is generated when the EOBF flag is set in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct RTOIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is inhibited + static let Disabled = Self(rawValue: 0x0) + + /// An USART interrupt is generated when the RTOF bit is set in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct OVER8Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Oversampling by 16 + static let Oversampling16 = Self(rawValue: 0x0) + + /// Oversampling by 8 + static let Oversampling8 = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct CMIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is disabled + static let Disabled = Self(rawValue: 0x0) + + /// Interrupt is generated when the CMF bit is set in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct MMEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Receiver in active mode permanently + static let Disabled = Self(rawValue: 0x0) + + /// Receiver can switch between mute mode and active mode + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct M0Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// 1 start bit, 8 data bits, n stop bits + static let Bit8 = Self(rawValue: 0x0) + + /// 1 start bit, 9 data bits, n stop bits + static let Bit9 = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct WAKEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Idle line + static let Idle = Self(rawValue: 0x0) + + /// Address mask + static let Address = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct PCEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Parity control disabled + static let Disabled = Self(rawValue: 0x0) + + /// Parity control enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct PSValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Even parity + static let Even = Self(rawValue: 0x0) + + /// Odd parity + static let Odd = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct PEIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is disabled + static let Disabled = Self(rawValue: 0x0) + + /// Interrupt is generated whenever PE=1 in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct TXEIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is disabled + static let Disabled = Self(rawValue: 0x0) + + /// Interrupt is generated whenever TXE=1 in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct TCIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is disabled + static let Disabled = Self(rawValue: 0x0) + + /// Interrupt is generated whenever TC=1 in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct RXNEIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is disabled + static let Disabled = Self(rawValue: 0x0) + + /// Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct IDLEIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is disabled + static let Disabled = Self(rawValue: 0x0) + + /// Interrupt is generated whenever IDLE=1 in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct TEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Transmitter is disabled + static let Disabled = Self(rawValue: 0x0) + + /// Transmitter is enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct REValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Receiver is disabled + static let Disabled = Self(rawValue: 0x0) + + /// Receiver is enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct UESMValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// USART not able to wake up the MCU from Stop mode + static let Disabled = Self(rawValue: 0x0) + + /// USART able to wake up the MCU from Stop mode + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct UEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// UART is disabled + static let Disabled = Self(rawValue: 0x0) + + /// UART is enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct RTOENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Receiver timeout feature disabled + static let Disabled = Self(rawValue: 0x0) + + /// Receiver timeout feature enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct ABRENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Auto baud rate detection is disabled + static let Disabled = Self(rawValue: 0x0) + + /// Auto baud rate detection is enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct MSBFIRSTValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// data is transmitted/received with data bit 0 first, following the start bit + static let LSB = Self(rawValue: 0x0) + + /// data is transmitted/received with MSB (bit 7/8/9) first, following the start bit + static let MSB = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct DATAINVValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Logical data from the data register are send/received in positive/direct logic + static let Positive = Self(rawValue: 0x0) + + /// Logical data from the data register are send/received in negative/inverse logic + static let Negative = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct TXINVValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// TX pin signal works using the standard logic levels + static let Standard = Self(rawValue: 0x0) + + /// TX pin signal values are inverted + static let Inverted = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct RXINVValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// RX pin signal works using the standard logic levels + static let Standard = Self(rawValue: 0x0) + + /// RX pin signal values are inverted + static let Inverted = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct SWAPValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// TX/RX pins are used as defined in standard pinout + static let Standard = Self(rawValue: 0x0) + + /// The TX and RX pins functions are swapped + static let Swapped = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct LINENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// LIN mode disabled + static let Disabled = Self(rawValue: 0x0) + + /// LIN mode enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct STOPValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// 1 stop bit + static let Stop1 = Self(rawValue: 0x0) + + /// 0.5 stop bit + static let Stop0p5 = Self(rawValue: 0x1) + + /// 2 stop bit + static let Stop2 = Self(rawValue: 0x2) + + /// 1.5 stop bit + static let Stop1p5 = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct CLKENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// CK pin disabled + static let Disabled = Self(rawValue: 0x0) + + /// CK pin enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct CPOLValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Steady low value on CK pin outside transmission window + static let Low = Self(rawValue: 0x0) + + /// Steady high value on CK pin outside transmission window + static let High = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct CPHAValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// The first clock transition is the first data capture edge + static let First = Self(rawValue: 0x0) + + /// The second clock transition is the first data capture edge + static let Second = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct LBCLValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// The clock pulse of the last data bit is not output to the CK pin + static let NotOutput = Self(rawValue: 0x0) + + /// The clock pulse of the last data bit is output to the CK pin + static let Output = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct LBDIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is inhibited + static let Disabled = Self(rawValue: 0x0) + + /// An interrupt is generated whenever LBDF=1 in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct LBDLValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// 10-bit break detection + static let Bit10 = Self(rawValue: 0x0) + + /// 11-bit break detection + static let Bit11 = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct ADDM7Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// 4-bit address detection + static let Bit4 = Self(rawValue: 0x0) + + /// 7-bit address detection + static let Bit7 = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct ABRMODValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// Measurement of the start bit is used to detect the baud rate + static let Start = Self(rawValue: 0x0) + + /// Falling edge to falling edge measurement + static let Edge = Self(rawValue: 0x1) + + /// 0x7F frame detection + static let Frame7F = Self(rawValue: 0x2) + + /// 0x55 frame detection + static let Frame55 = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct WUFIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is inhibited + static let Disabled = Self(rawValue: 0x0) + + /// An USART interrupt is generated whenever WUF=1 in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct WUSValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// WUF active on address match + static let Address = Self(rawValue: 0x0) + + /// WuF active on Start bit detection + static let Start = Self(rawValue: 0x2) + + /// WUF active on RXNE + static let RXNE = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct DEPValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// DE signal is active high + static let High = Self(rawValue: 0x0) + + /// DE signal is active low + static let Low = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct DEMValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// DE function is disabled + static let Disabled = Self(rawValue: 0x0) + + /// The DE signal is output on the RTS pin + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct DDREValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// DMA is not disabled in case of reception error + static let NotDisabled = Self(rawValue: 0x0) + + /// DMA is disabled following a reception error + static let Disabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct OVRDISValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Overrun Error Flag, ORE, is set when received data is not read before receiving new data + static let Enabled = Self(rawValue: 0x0) + + /// Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register + static let Disabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct ONEBITValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Three sample bit method + static let Sample3 = Self(rawValue: 0x0) + + /// One sample bit method + static let Sample1 = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct CTSIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is inhibited + static let Disabled = Self(rawValue: 0x0) + + /// An interrupt is generated whenever CTSIF=1 in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct CTSEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// CTS hardware flow control disabled + static let Disabled = Self(rawValue: 0x0) + + /// CTS mode enabled, data is only transmitted when the CTS input is asserted + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct RTSEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// RTS hardware flow control disabled + static let Disabled = Self(rawValue: 0x0) + + /// RTS output enabled, data is only requested when there is space in the receive buffer + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct DMATValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// DMA mode is disabled for transmission + static let Disabled = Self(rawValue: 0x0) + + /// DMA mode is enabled for transmission + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct DMARValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// DMA mode is disabled for reception + static let Disabled = Self(rawValue: 0x0) + + /// DMA mode is enabled for reception + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct SCENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Smartcard Mode disabled + static let Disabled = Self(rawValue: 0x0) + + /// Smartcard Mode enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct NACKValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// NACK transmission in case of parity error is disabled + static let Disabled = Self(rawValue: 0x0) + + /// NACK transmission during parity error is enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct HDSELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Half duplex mode is not selected + static let NotSelected = Self(rawValue: 0x0) + + /// Half duplex mode is selected + static let Selected = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct IRLPValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Normal mode + static let Normal = Self(rawValue: 0x0) + + /// Low-power mode + static let LowPower = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct IRENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// IrDA disabled + static let Disabled = Self(rawValue: 0x0) + + /// IrDA enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct EIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is inhibited + static let Disabled = Self(rawValue: 0x0) + + /// An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} diff --git a/stm32-uart-echo/.sourcekit-lsp/config.json b/stm32-uart-echo/.sourcekit-lsp/config.json deleted file mode 100644 index b1647f54..00000000 --- a/stm32-uart-echo/.sourcekit-lsp/config.json +++ /dev/null @@ -1,8 +0,0 @@ -{ - "swiftPM": { - "configuration": "release", - "triple": "armv7em-apple-none-macho", - "swiftCompilerFlags": ["-Xfrontend", "-disable-stack-protector"], - "cCompilerFlags": ["-D__APPLE__", "-D__MACH__"] - } -} diff --git a/stm32-uart-echo/Makefile b/stm32-uart-echo/Makefile index 92b2dfe4..51885ce5 100755 --- a/stm32-uart-echo/Makefile +++ b/stm32-uart-echo/Makefile @@ -9,42 +9,30 @@ ## ##===----------------------------------------------------------------------===## -# Determine file paths -REPOROOT := $(shell git rev-parse --show-toplevel) -TOOLSROOT := $(REPOROOT)/Tools -SRCROOT := $(REPOROOT)/stm32-uart-echo -BUILDROOT := $(SRCROOT)/.build/release - -# Setup tools and build flags -ARCH := armv7em -TARGET := $(ARCH)-apple-none-macho -VECTORS_ADDRESS=-0x00200000 - -SWIFT_BUILD := $(shell xcrun -f swift-build) -MACHO2BIN := $(SRCROOT)/../Tools/macho2bin.py +# Paths +REPOROOT := $(shell git rev-parse --show-toplevel) +TOOLSROOT := $(REPOROOT)/Tools +TOOLSET := $(TOOLSROOT)/Toolsets/stm32f74x.json +MACHO2BIN := $(TOOLSROOT)/macho2bin.py +SWIFT_BUILD := swift build + +# Flags +ARCH := armv7em +TARGET := $(ARCH)-apple-none-macho +SWIFT_BUILD_ARGS := \ + --configuration release \ + --triple $(TARGET) \ + --toolset $(TOOLSET) \ + --disable-local-rpath +BUILDROOT := $(shell $(SWIFT_BUILD) $(SWIFT_BUILD_ARGS) --show-bin-path) .PHONY: build build: - @echo "compiling..." + @echo "building..." $(SWIFT_BUILD) \ - --configuration release \ - --verbose \ - --triple $(TARGET) \ - -Xcc -D__APPLE__ -Xcc -D__MACH__ \ - -Xswiftc -Xfrontend -Xswiftc -disable-stack-protector - - @echo "linking..." - clang .build/release/libApplication.a -o .build/release/Application \ - -arch $(ARCH) \ - -dead_strip \ - -static \ - -Wl,-e,_reset \ - -Wl,-map,$(BUILDROOT)/Application.mangled.map \ - -Wl,-no_zero_fill_sections \ - -Wl,-segalign,4 \ - -Wl,-segaddr,__VECTORS,0x20010000 \ - -Wl,-seg1addr,0x20010200 \ - -Wl,-pagezero_size,0 + $(SWIFT_BUILD_ARGS) \ + -Xlinker -map -Xlinker $(BUILDROOT)/Application.mangled.map \ + --verbose @echo "demangling linker map..." cat $(BUILDROOT)/Application.mangled.map \ diff --git a/stm32-uart-echo/Package.resolved b/stm32-uart-echo/Package.resolved index dc3e17d1..25097fb2 100644 --- a/stm32-uart-echo/Package.resolved +++ b/stm32-uart-echo/Package.resolved @@ -1,13 +1,13 @@ { - "originHash" : "a341db4bc8f11a7dc810c323c7d37f2f9a1322e9633ccbec6a8d88de8c055685", + "originHash" : "50d5562e902c0a987f43e9c891a6d559c9d71bc593aa215e096917fdd28b5c6c", "pins" : [ { "identity" : "swift-argument-parser", "kind" : "remoteSourceControl", "location" : "https://github.com/apple/swift-argument-parser.git", "state" : { - "revision" : "0fbc8848e389af3bb55c182bc19ca9d5dc2f255b", - "version" : "1.4.0" + "revision" : "41982a3656a71c768319979febd796c6fd111d5c", + "version" : "1.5.0" } }, { @@ -15,8 +15,8 @@ "kind" : "remoteSourceControl", "location" : "https://github.com/apple/swift-mmio", "state" : { - "branch" : "swift-embedded-examples", - "revision" : "06d96ed4916739f2edafde87f3951b2d2a04df65" + "branch" : "main", + "revision" : "daf25ecacc0d9b71036c6af32cb7786a01802799" } }, { diff --git a/stm32-uart-echo/Package.swift b/stm32-uart-echo/Package.swift index dd406bed..1b031181 100644 --- a/stm32-uart-echo/Package.swift +++ b/stm32-uart-echo/Package.swift @@ -1,4 +1,4 @@ -// swift-tools-version: 5.10 +// swift-tools-version: 6.2 import PackageDescription @@ -8,22 +8,22 @@ let package = Package( .macOS(.v10_15) ], products: [ - .library(name: "Application", type: .static, targets: ["Application"]) + .executable(name: "Application", targets: ["Application"]) ], dependencies: [ - .package( - url: "https://github.com/apple/swift-mmio", - branch: "swift-embedded-examples") + .package(url: "https://github.com/apple/swift-mmio", branch: "main") ], targets: [ - .target( + // SVD2Swift \ + // --input ../Tools/SVDs/stm32f7x6.patched.svd \ + // --output Sources/Application/Registers \ + // --indentation-width 2 \ + // --peripherals GPIOA GPIOB RCC USART1 + .executableTarget( name: "Application", dependencies: [ .product(name: "MMIO", package: "swift-mmio"), "Support", - ], - swiftSettings: [ - .enableExperimentalFeature("Embedded") ]), .target(name: "Support"), ]) diff --git a/stm32-uart-echo/Sources/Application/Registers/Device.swift b/stm32-uart-echo/Sources/Application/Registers/Device.swift index 75fd7daf..8788410d 100644 --- a/stm32-uart-echo/Sources/Application/Registers/Device.swift +++ b/stm32-uart-echo/Sources/Application/Registers/Device.swift @@ -3,13 +3,13 @@ import MMIO /// General-purpose I/Os -let gpioa = GPIOA(unsafeAddress: 0x4002_0000) +let gpioa = GPIOA(unsafeAddress: 0x40020000) /// General-purpose I/Os -let gpiob = GPIOB(unsafeAddress: 0x4002_0400) +let gpiob = GPIOB(unsafeAddress: 0x40020400) /// Reset and clock control -let rcc = RCC(unsafeAddress: 0x4002_3800) +let rcc = RCC(unsafeAddress: 0x40023800) /// Universal synchronous asynchronous receiver transmitter -let usart1 = USART1(unsafeAddress: 0x4001_1000) +let usart1 = USART1(unsafeAddress: 0x40011000) diff --git a/stm32-uart-echo/Sources/Application/Registers/GPIOA.swift b/stm32-uart-echo/Sources/Application/Registers/GPIOA.swift index 1bc077bf..3bc4d2ff 100644 --- a/stm32-uart-echo/Sources/Application/Registers/GPIOA.swift +++ b/stm32-uart-echo/Sources/Application/Registers/GPIOA.swift @@ -115,7 +115,7 @@ extension GPIOA { var moder1: MODER1 /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<2) + @ReadWrite(bits: 0..<2, as: MODER0Values.self) var moder0: MODER0 } @@ -183,7 +183,7 @@ extension GPIOA { var ot1: OT1 /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: OT0Values.self) var ot0: OT0 } @@ -251,7 +251,7 @@ extension GPIOA { var ospeedr1: OSPEEDR1 /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<2) + @ReadWrite(bits: 0..<2, as: OSPEEDR0Values.self) var ospeedr0: OSPEEDR0 } @@ -319,7 +319,7 @@ extension GPIOA { var pupdr1: PUPDR1 /// Port x configuration bits (y = 0..15) - @ReadWrite(bits: 0..<2) + @ReadWrite(bits: 0..<2, as: PUPDR0Values.self) var pupdr0: PUPDR0 } @@ -455,7 +455,7 @@ extension GPIOA { var odr1: ODR1 /// Port output data (y = 0..15) - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: ODR0Values.self) var odr0: ODR0 } @@ -595,7 +595,7 @@ extension GPIOA { @Register(bitWidth: 32) struct LCKR { /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 16..<17) + @ReadWrite(bits: 16..<17, as: LCKKValues.self) var lckk: LCKK /// Port x lock bit y (y= 0..15) @@ -659,7 +659,7 @@ extension GPIOA { var lck1: LCK1 /// Port x lock bit y (y= 0..15) - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: LCK0Values.self) var lck0: LCK0 } @@ -695,7 +695,7 @@ extension GPIOA { var afrl1: AFRL1 /// Alternate function selection for port x bit y (y = 0..7) - @ReadWrite(bits: 0..<4) + @ReadWrite(bits: 0..<4, as: AFRL0Values.self) var afrl0: AFRL0 } @@ -731,7 +731,7 @@ extension GPIOA { var afrh9: AFRH9 /// Alternate function selection for port x bit y (y = 8..15) - @ReadWrite(bits: 0..<4) + @ReadWrite(bits: 0..<4, as: AFRH8Values.self) var afrh8: AFRH8 } @@ -803,3 +803,273 @@ extension GPIOA { var br15: BR15 } } + +extension GPIOA.MODER { + struct MODER0Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// Input mode (reset state) + static let Input = Self(rawValue: 0x0) + + /// General purpose output mode + static let Output = Self(rawValue: 0x1) + + /// Alternate function mode + static let Alternate = Self(rawValue: 0x2) + + /// Analog mode + static let Analog = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.OTYPER { + struct OT0Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Output push-pull (reset state) + static let PushPull = Self(rawValue: 0x0) + + /// Output open-drain + static let OpenDrain = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.OSPEEDR { + struct OSPEEDR0Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// Low speed + static let LowSpeed = Self(rawValue: 0x0) + + /// Medium speed + static let MediumSpeed = Self(rawValue: 0x1) + + /// High speed + static let HighSpeed = Self(rawValue: 0x2) + + /// Very high speed + static let VeryHighSpeed = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.PUPDR { + struct PUPDR0Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// No pull-up, pull-down + static let Floating = Self(rawValue: 0x0) + + /// Pull-up + static let PullUp = Self(rawValue: 0x1) + + /// Pull-down + static let PullDown = Self(rawValue: 0x2) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.ODR { + struct ODR0Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Set output to logic low + static let Low = Self(rawValue: 0x0) + + /// Set output to logic high + static let High = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.LCKR { + struct LCKKValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Port configuration lock key not active + static let NotActive = Self(rawValue: 0x0) + + /// Port configuration lock key active + static let Active = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.LCKR { + struct LCK0Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Port configuration not locked + static let Unlocked = Self(rawValue: 0x0) + + /// Port configuration locked + static let Locked = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.AFRL { + struct AFRL0Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 4 + + /// AF0 + static let AF0 = Self(rawValue: 0x0) + + /// AF1 + static let AF1 = Self(rawValue: 0x1) + + /// AF2 + static let AF2 = Self(rawValue: 0x2) + + /// AF3 + static let AF3 = Self(rawValue: 0x3) + + /// AF4 + static let AF4 = Self(rawValue: 0x4) + + /// AF5 + static let AF5 = Self(rawValue: 0x5) + + /// AF6 + static let AF6 = Self(rawValue: 0x6) + + /// AF7 + static let AF7 = Self(rawValue: 0x7) + + /// AF8 + static let AF8 = Self(rawValue: 0x8) + + /// AF9 + static let AF9 = Self(rawValue: 0x9) + + /// AF10 + static let AF10 = Self(rawValue: 0xa) + + /// AF11 + static let AF11 = Self(rawValue: 0xb) + + /// AF12 + static let AF12 = Self(rawValue: 0xc) + + /// AF13 + static let AF13 = Self(rawValue: 0xd) + + /// AF14 + static let AF14 = Self(rawValue: 0xe) + + /// AF15 + static let AF15 = Self(rawValue: 0xf) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.AFRH { + struct AFRH8Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 4 + + /// AF0 + static let AF0 = Self(rawValue: 0x0) + + /// AF1 + static let AF1 = Self(rawValue: 0x1) + + /// AF2 + static let AF2 = Self(rawValue: 0x2) + + /// AF3 + static let AF3 = Self(rawValue: 0x3) + + /// AF4 + static let AF4 = Self(rawValue: 0x4) + + /// AF5 + static let AF5 = Self(rawValue: 0x5) + + /// AF6 + static let AF6 = Self(rawValue: 0x6) + + /// AF7 + static let AF7 = Self(rawValue: 0x7) + + /// AF8 + static let AF8 = Self(rawValue: 0x8) + + /// AF9 + static let AF9 = Self(rawValue: 0x9) + + /// AF10 + static let AF10 = Self(rawValue: 0xa) + + /// AF11 + static let AF11 = Self(rawValue: 0xb) + + /// AF12 + static let AF12 = Self(rawValue: 0xc) + + /// AF13 + static let AF13 = Self(rawValue: 0xd) + + /// AF14 + static let AF14 = Self(rawValue: 0xe) + + /// AF15 + static let AF15 = Self(rawValue: 0xf) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} diff --git a/stm32-uart-echo/Sources/Application/Registers/GPIOB.swift b/stm32-uart-echo/Sources/Application/Registers/GPIOB.swift index 9988779e..c820355f 100644 --- a/stm32-uart-echo/Sources/Application/Registers/GPIOB.swift +++ b/stm32-uart-echo/Sources/Application/Registers/GPIOB.swift @@ -2,4 +2,6 @@ import MMIO +/// General-purpose I/Os typealias GPIOB = GPIOA + diff --git a/stm32-uart-echo/Sources/Application/Registers/RCC.swift b/stm32-uart-echo/Sources/Application/Registers/RCC.swift index a06ea27b..4f5842ef 100644 --- a/stm32-uart-echo/Sources/Application/Registers/RCC.swift +++ b/stm32-uart-echo/Sources/Application/Registers/RCC.swift @@ -103,11 +103,11 @@ struct RCC { /// dedicated clocks configuration register @RegisterBlock(offset: 0x8c) - var dkcfgr1: Register + var dckcfgr1: Register /// dedicated clocks configuration register @RegisterBlock(offset: 0x90) - var dkcfgr2: Register + var dckcfgr2: Register } extension RCC { @@ -131,11 +131,11 @@ extension RCC { var pllon: PLLON /// Clock security system enable - @ReadWrite(bits: 19..<20) + @ReadWrite(bits: 19..<20, as: CSSONValues.self) var csson: CSSON /// HSE clock bypass - @ReadWrite(bits: 18..<19) + @ReadWrite(bits: 18..<19, as: HSEBYPValues.self) var hsebyp: HSEBYP /// HSE clock ready flag @@ -159,107 +159,47 @@ extension RCC { var hsirdy: HSIRDY /// Internal high-speed clock enable - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: HSIONValues.self) var hsion: HSION + + /// PLLSAI clock ready flag + @ReadOnly(bits: 29..<30) + var pllsairdy: PLLSAIRDY + + /// PLLSAI enable + @ReadWrite(bits: 28..<29) + var pllsaion: PLLSAION } /// PLL configuration register @Register(bitWidth: 32) struct PLLCFGR { - /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks - @ReadWrite(bits: 27..<28) - var pllq3: PLLQ3 - - /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks - @ReadWrite(bits: 26..<27) - var pllq2: PLLQ2 - - /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks - @ReadWrite(bits: 25..<26) - var pllq1: PLLQ1 - - /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks - @ReadWrite(bits: 24..<25) - var pllq0: PLLQ0 - /// Main PLL(PLL) and audio PLL (PLLI2S) entry clock source - @ReadWrite(bits: 22..<23) + @ReadWrite(bits: 22..<23, as: PLLSRCValues.self) var pllsrc: PLLSRC - /// Main PLL (PLL) division factor for main system clock - @ReadWrite(bits: 17..<18) - var pllp1: PLLP1 - - /// Main PLL (PLL) division factor for main system clock - @ReadWrite(bits: 16..<17) - var pllp0: PLLP0 - - /// Main PLL (PLL) multiplication factor for VCO - @ReadWrite(bits: 14..<15) - var plln8: PLLN8 - - /// Main PLL (PLL) multiplication factor for VCO - @ReadWrite(bits: 13..<14) - var plln7: PLLN7 - - /// Main PLL (PLL) multiplication factor for VCO - @ReadWrite(bits: 12..<13) - var plln6: PLLN6 - - /// Main PLL (PLL) multiplication factor for VCO - @ReadWrite(bits: 11..<12) - var plln5: PLLN5 - - /// Main PLL (PLL) multiplication factor for VCO - @ReadWrite(bits: 10..<11) - var plln4: PLLN4 - - /// Main PLL (PLL) multiplication factor for VCO - @ReadWrite(bits: 9..<10) - var plln3: PLLN3 - - /// Main PLL (PLL) multiplication factor for VCO - @ReadWrite(bits: 8..<9) - var plln2: PLLN2 - - /// Main PLL (PLL) multiplication factor for VCO - @ReadWrite(bits: 7..<8) - var plln1: PLLN1 - - /// Main PLL (PLL) multiplication factor for VCO - @ReadWrite(bits: 6..<7) - var plln0: PLLN0 - - /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - @ReadWrite(bits: 5..<6) - var pllm5: PLLM5 - - /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - @ReadWrite(bits: 4..<5) - var pllm4: PLLM4 - /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - @ReadWrite(bits: 3..<4) - var pllm3: PLLM3 + @ReadWrite(bits: 0..<6) + var pllm: PLLM - /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - @ReadWrite(bits: 2..<3) - var pllm2: PLLM2 + /// Main PLL (PLL) multiplication factor for VCO + @ReadWrite(bits: 6..<15) + var plln: PLLN - /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - @ReadWrite(bits: 1..<2) - var pllm1: PLLM1 + /// Main PLL (PLL) division factor for main system clock + @ReadWrite(bits: 16..<18, as: PLLPValues.self) + var pllp: PLLP - /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - @ReadWrite(bits: 0..<1) - var pllm0: PLLM0 + /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + @ReadWrite(bits: 24..<28) + var pllq: PLLQ } /// clock configuration register @Register(bitWidth: 32) struct CFGR { /// Microcontroller clock output 2 - @ReadWrite(bits: 30..<32) + @ReadWrite(bits: 30..<32, as: MCO2Values.self) var mco2: MCO2 /// MCO2 prescaler @@ -267,15 +207,15 @@ extension RCC { var mco2pre: MCO2PRE /// MCO1 prescaler - @ReadWrite(bits: 24..<27) + @ReadWrite(bits: 24..<27, as: MCO1PREValues.self) var mco1pre: MCO1PRE /// I2S clock selection - @ReadWrite(bits: 23..<24) + @ReadWrite(bits: 23..<24, as: I2SSRCValues.self) var i2ssrc: I2SSRC /// Microcontroller clock output 1 - @ReadWrite(bits: 21..<23) + @ReadWrite(bits: 21..<23, as: MCO1Values.self) var mco1: MCO1 /// HSE division factor for RTC clock @@ -287,28 +227,20 @@ extension RCC { var ppre2: PPRE2 /// APB Low speed prescaler (APB1) - @ReadWrite(bits: 10..<13) + @ReadWrite(bits: 10..<13, as: PPRE1Values.self) var ppre1: PPRE1 /// AHB prescaler - @ReadWrite(bits: 4..<8) + @ReadWrite(bits: 4..<8, as: HPREValues.self) var hpre: HPRE - /// System clock switch status - @ReadOnly(bits: 3..<4) - var sws1: SWS1 - - /// System clock switch status - @ReadOnly(bits: 2..<3) - var sws0: SWS0 - /// System clock switch - @ReadWrite(bits: 1..<2) - var sw1: SW1 + @Reserved(bits: 0..<2, as: SWValues.self) + var sw: SW - /// System clock switch - @ReadWrite(bits: 0..<1) - var sw0: SW0 + /// System clock switch status + @Reserved(bits: 2..<4) + var sws: SWS } /// clock interrupt register @@ -371,7 +303,7 @@ extension RCC { var lserdyie: LSERDYIE /// LSI ready interrupt enable - @ReadWrite(bits: 8..<9) + @ReadWrite(bits: 8..<9, as: LSIRDYIEValues.self) var lsirdyie: LSIRDYIE /// Clock security system interrupt flag @@ -475,7 +407,7 @@ extension RCC { var gpiobrst: GPIOBRST /// IO port A reset - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: GPIOARSTValues.self) var gpioarst: GPIOARST } @@ -499,7 +431,7 @@ extension RCC { var cryprst: CRYPRST /// Camera interface reset - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: DCMIRSTValues.self) var dcmirst: DCMIRST } @@ -507,7 +439,7 @@ extension RCC { @Register(bitWidth: 32) struct AHB3RSTR { /// Flexible memory controller module reset - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: FMCRSTValues.self) var fmcrst: FMCRST /// Quad SPI memory controller reset @@ -519,7 +451,7 @@ extension RCC { @Register(bitWidth: 32) struct APB1RSTR { /// TIM2 reset - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: TIM2RSTValues.self) var tim2rst: TIM2RST /// TIM3 reset @@ -568,11 +500,11 @@ extension RCC { /// USART 2 reset @ReadWrite(bits: 17..<18) - var uart2rst: UART2RST + var usart2rst: USART2RST /// USART 3 reset @ReadWrite(bits: 18..<19) - var uart3rst: UART3RST + var usart3rst: USART3RST /// USART 4 reset @ReadWrite(bits: 19..<20) @@ -639,7 +571,7 @@ extension RCC { @Register(bitWidth: 32) struct APB2RSTR { /// TIM1 reset - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: TIM1RSTValues.self) var tim1rst: TIM1RST /// TIM8 reset @@ -748,7 +680,7 @@ extension RCC { /// CCM data RAM clock enable @ReadWrite(bits: 20..<21) - var ccmdataramen: CCMDATARAMEN + var dtcmramen: DTCMRAMEN /// Backup SRAM interface clock enable @ReadWrite(bits: 18..<19) @@ -799,7 +731,7 @@ extension RCC { var gpioben: GPIOBEN /// IO port A clock enable - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: GPIOAENValues.self) var gpioaen: GPIOAEN } @@ -823,7 +755,7 @@ extension RCC { var crypen: CRYPEN /// Camera interface enable - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: DCMIENValues.self) var dcmien: DCMIEN } @@ -831,7 +763,7 @@ extension RCC { @Register(bitWidth: 32) struct AHB3ENR { /// Flexible memory controller module clock enable - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: FMCENValues.self) var fmcen: FMCEN /// Quad SPI memory controller clock enable @@ -843,7 +775,7 @@ extension RCC { @Register(bitWidth: 32) struct APB1ENR { /// TIM2 clock enable - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: TIM2ENValues.self) var tim2en: TIM2EN /// TIM3 clock enable @@ -936,11 +868,11 @@ extension RCC { /// UART7 clock enable @ReadWrite(bits: 30..<31) - var uart7enr: UART7ENR + var uart7en: UART7EN /// UART8 clock enable @ReadWrite(bits: 31..<32) - var uart8enr: UART8ENR + var uart8en: UART8EN /// SPDIF-RX clock enable @ReadWrite(bits: 16..<17) @@ -952,7 +884,7 @@ extension RCC { /// Low power timer 1 clock enable @ReadWrite(bits: 9..<10) - var lptmi1en: LPTMI1EN + var lptim1en: LPTIM1EN /// I2C4 clock enable @ReadWrite(bits: 24..<25) @@ -963,7 +895,7 @@ extension RCC { @Register(bitWidth: 32) struct APB2ENR { /// TIM1 clock enable - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: TIM1ENValues.self) var tim1en: TIM1EN /// TIM8 clock enable @@ -996,7 +928,7 @@ extension RCC { /// SPI4 clock enable @ReadWrite(bits: 13..<14) - var spi4enr: SPI4ENR + var spi4en: SPI4EN /// System configuration controller clock enable @ReadWrite(bits: 14..<15) @@ -1016,11 +948,11 @@ extension RCC { /// SPI5 clock enable @ReadWrite(bits: 20..<21) - var spi5enr: SPI5ENR + var spi5en: SPI5EN /// SPI6 clock enable @ReadWrite(bits: 21..<22) - var spi6enr: SPI6ENR + var spi6en: SPI6EN /// SAI1 clock enable @ReadWrite(bits: 22..<23) @@ -1043,7 +975,7 @@ extension RCC { @Register(bitWidth: 32) struct AHB1LPENR { /// IO port A clock enable during sleep mode - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: GPIOALPENValues.self) var gpioalpen: GPIOALPEN /// IO port B clock enable during Sleep mode @@ -1145,6 +1077,14 @@ extension RCC { /// USB OTG HS ULPI clock enable during Sleep mode @ReadWrite(bits: 30..<31) var otghsulpilpen: OTGHSULPILPEN + + /// AXI to AHB bridge clock enable during Sleep mode + @ReadWrite(bits: 13..<14) + var axilpen: AXILPEN + + /// DTCM RAM interface clock enable during Sleep mode + @ReadWrite(bits: 20..<21) + var dtcmlpen: DTCMLPEN } /// AHB2 peripheral clock enable in low power mode register @@ -1167,7 +1107,7 @@ extension RCC { var cryplpen: CRYPLPEN /// Camera interface enable during Sleep mode - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: DCMILPENValues.self) var dcmilpen: DCMILPEN } @@ -1175,7 +1115,7 @@ extension RCC { @Register(bitWidth: 32) struct AHB3LPENR { /// Flexible memory controller module clock enable during Sleep mode - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: FMCLPENValues.self) var fmclpen: FMCLPEN /// Quand SPI memory controller clock enable during Sleep mode @@ -1187,7 +1127,7 @@ extension RCC { @Register(bitWidth: 32) struct APB1LPENR { /// TIM2 clock enable during Sleep mode - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: TIM2LPENValues.self) var tim2lpen: TIM2LPEN /// TIM3 clock enable during Sleep mode @@ -1307,7 +1247,7 @@ extension RCC { @Register(bitWidth: 32) struct APB2LPENR { /// TIM1 clock enable during Sleep mode - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: TIM1LPENValues.self) var tim1lpen: TIM1LPEN /// TIM8 clock enable during Sleep mode @@ -1387,23 +1327,15 @@ extension RCC { @Register(bitWidth: 32) struct BDCR { /// Backup domain software reset - @ReadWrite(bits: 16..<17) + @ReadWrite(bits: 16..<17, as: BDRSTValues.self) var bdrst: BDRST /// RTC clock enable - @ReadWrite(bits: 15..<16) + @ReadWrite(bits: 15..<16, as: RTCENValues.self) var rtcen: RTCEN - /// RTC clock source selection - @ReadWrite(bits: 9..<10) - var rtcsel1: RTCSEL1 - - /// RTC clock source selection - @ReadWrite(bits: 8..<9) - var rtcsel0: RTCSEL0 - /// External low-speed oscillator bypass - @ReadWrite(bits: 2..<3) + @ReadWrite(bits: 2..<3, as: LSEBYPValues.self) var lsebyp: LSEBYP /// External low-speed oscillator ready @@ -1411,8 +1343,16 @@ extension RCC { var lserdy: LSERDY /// External low-speed oscillator enable - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: LSEONValues.self) var lseon: LSEON + + /// LSE oscillator drive capability + @ReadWrite(bits: 3..<5, as: LSEDRVValues.self) + var lsedrv: LSEDRV + + /// RTC clock source selection + @Reserved(bits: 8..<10, as: RTCSELValues.self) + var rtcsel: RTCSEL } /// clock control & status register @@ -1455,7 +1395,7 @@ extension RCC { var lsirdy: LSIRDY /// Internal low-speed oscillator enable - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: LSIONValues.self) var lsion: LSION } @@ -1463,11 +1403,11 @@ extension RCC { @Register(bitWidth: 32) struct SSCGR { /// Spread spectrum modulation enable - @ReadWrite(bits: 31..<32) + @ReadWrite(bits: 31..<32, as: SSCGENValues.self) var sscgen: SSCGEN /// Spread Select - @ReadWrite(bits: 30..<31) + @ReadWrite(bits: 30..<31, as: SPREADSELValues.self) var spreadsel: SPREADSEL /// Incrementation step @@ -1493,6 +1433,10 @@ extension RCC { /// PLLI2S multiplication factor for VCO @ReadWrite(bits: 6..<15) var plli2sn: PLLI2SN + + /// PLLI2S division factor for SPDIFRX clock + @ReadWrite(bits: 16..<18, as: PLLI2SPValues.self) + var plli2sp: PLLI2SP } /// PLL configuration register @@ -1503,7 +1447,7 @@ extension RCC { var pllsain: PLLSAIN /// PLLSAI division factor for 48MHz clock - @ReadWrite(bits: 16..<18) + @ReadWrite(bits: 16..<18, as: PLLSAIPValues.self) var pllsaip: PLLSAIP /// PLLSAI division factor for SAI clock @@ -1517,41 +1461,41 @@ extension RCC { /// dedicated clocks configuration register @Register(bitWidth: 32) - struct DKCFGR1 { + struct DCKCFGR1 { /// PLLI2S division factor for SAI1 clock - @ReadWrite(bits: 0..<5) - var plli2sdiv: PLLI2SDIV + @ReadWrite(bits: 0..<5, as: PLLI2SDIVQValues.self) + var plli2sdivq: PLLI2SDIVQ /// PLLSAI division factor for SAI1 clock - @ReadWrite(bits: 8..<13) + @ReadWrite(bits: 8..<13, as: PLLSAIDIVQValues.self) var pllsaidivq: PLLSAIDIVQ /// division factor for LCD_CLK - @ReadWrite(bits: 16..<18) + @ReadWrite(bits: 16..<18, as: PLLSAIDIVRValues.self) var pllsaidivr: PLLSAIDIVR /// SAI1 clock source selection - @ReadWrite(bits: 20..<22) + @ReadWrite(bits: 20..<22, as: SAI1SELValues.self) var sai1sel: SAI1SEL /// SAI2 clock source selection - @ReadWrite(bits: 22..<24) + @ReadWrite(bits: 22..<24, as: SAI2SELValues.self) var sai2sel: SAI2SEL /// Timers clocks prescalers selection - @ReadWrite(bits: 24..<25) + @ReadWrite(bits: 24..<25, as: TIMPREValues.self) var timpre: TIMPRE } /// dedicated clocks configuration register @Register(bitWidth: 32) - struct DKCFGR2 { + struct DCKCFGR2 { /// USART 1 clock source selection - @ReadWrite(bits: 0..<2) + @ReadWrite(bits: 0..<2, as: USART1SELValues.self) var usart1sel: USART1SEL /// USART 2 clock source selection - @ReadWrite(bits: 2..<4) + @ReadWrite(bits: 2..<4, as: USART2SELValues.self) var usart2sel: USART2SEL /// USART 3 clock source selection @@ -1579,7 +1523,7 @@ extension RCC { var uart8sel: UART8SEL /// I2C1 clock source selection - @ReadWrite(bits: 16..<18) + @ReadWrite(bits: 16..<18, as: I2C1SELValues.self) var i2c1sel: I2C1SEL /// I2C2 clock source selection @@ -1595,19 +1539,1295 @@ extension RCC { var i2c4sel: I2C4SEL /// Low power timer 1 clock source selection - @ReadWrite(bits: 24..<26) + @ReadWrite(bits: 24..<26, as: LPTIM1SELValues.self) var lptim1sel: LPTIM1SEL /// HDMI-CEC clock source selection - @ReadWrite(bits: 26..<27) + @ReadWrite(bits: 26..<27, as: CECSELValues.self) var cecsel: CECSEL /// 48MHz clock source selection - @ReadWrite(bits: 27..<28) + @ReadWrite(bits: 27..<28, as: CK48MSELValues.self) var ck48msel: CK48MSEL /// SDMMC clock source selection - @ReadWrite(bits: 28..<29) - var sdmmcsel: SDMMCSEL + @ReadWrite(bits: 28..<29, as: SDMMC1SELValues.self) + var sdmmc1sel: SDMMC1SEL + } +} + +extension RCC.CR { + struct CSSONValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Clock security system disabled (clock detector OFF) + static let Off = Self(rawValue: 0x0) + + /// Clock security system enable (clock detector ON if the HSE is ready, OFF if not) + static let On = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CR { + struct HSEBYPValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// HSE crystal oscillator not bypassed + static let NotBypassed = Self(rawValue: 0x0) + + /// HSE crystal oscillator bypassed with external clock + static let Bypassed = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CR { + struct HSIONValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Clock Off + static let Off = Self(rawValue: 0x0) + + /// Clock On + static let On = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.PLLCFGR { + struct PLLSRCValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// HSI clock selected as PLL and PLLI2S clock entry + static let HSI = Self(rawValue: 0x0) + + /// HSE oscillator clock selected as PLL and PLLI2S clock entry + static let HSE = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.PLLCFGR { + struct PLLPValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// PLLP=2 + static let Div2 = Self(rawValue: 0x0) + + /// PLLP=4 + static let Div4 = Self(rawValue: 0x1) + + /// PLLP=6 + static let Div6 = Self(rawValue: 0x2) + + /// PLLP=8 + static let Div8 = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + struct MCO2Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// System clock (SYSCLK) selected + static let SYSCLK = Self(rawValue: 0x0) + + /// PLLI2S clock selected + static let PLLI2S = Self(rawValue: 0x1) + + /// HSE oscillator clock selected + static let HSE = Self(rawValue: 0x2) + + /// PLL clock selected + static let PLL = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + struct MCO1PREValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 3 + + /// No division + static let Div1 = Self(rawValue: 0x0) + + /// Division by 2 + static let Div2 = Self(rawValue: 0x4) + + /// Division by 3 + static let Div3 = Self(rawValue: 0x5) + + /// Division by 4 + static let Div4 = Self(rawValue: 0x6) + + /// Division by 5 + static let Div5 = Self(rawValue: 0x7) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + struct I2SSRCValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// PLLI2S clock used as I2S clock source + static let PLLI2S = Self(rawValue: 0x0) + + /// External clock mapped on the I2S_CKIN pin used as I2S clock source + static let CKIN = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + struct MCO1Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// HSI clock selected + static let HSI = Self(rawValue: 0x0) + + /// LSE oscillator selected + static let LSE = Self(rawValue: 0x1) + + /// HSE oscillator clock selected + static let HSE = Self(rawValue: 0x2) + + /// PLL clock selected + static let PLL = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + struct PPRE1Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 3 + + /// HCLK not divided + static let Div1 = Self(rawValue: 0x0) + + /// HCLK divided by 2 + static let Div2 = Self(rawValue: 0x4) + + /// HCLK divided by 4 + static let Div4 = Self(rawValue: 0x5) + + /// HCLK divided by 8 + static let Div8 = Self(rawValue: 0x6) + + /// HCLK divided by 16 + static let Div16 = Self(rawValue: 0x7) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + struct HPREValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 4 + + /// SYSCLK not divided + static let Div1 = Self(rawValue: 0x0) + + /// SYSCLK divided by 2 + static let Div2 = Self(rawValue: 0x8) + + /// SYSCLK divided by 4 + static let Div4 = Self(rawValue: 0x9) + + /// SYSCLK divided by 8 + static let Div8 = Self(rawValue: 0xa) + + /// SYSCLK divided by 16 + static let Div16 = Self(rawValue: 0xb) + + /// SYSCLK divided by 64 + static let Div64 = Self(rawValue: 0xc) + + /// SYSCLK divided by 128 + static let Div128 = Self(rawValue: 0xd) + + /// SYSCLK divided by 256 + static let Div256 = Self(rawValue: 0xe) + + /// SYSCLK divided by 512 + static let Div512 = Self(rawValue: 0xf) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + struct SWValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// HSI selected as system clock + static let HSI = Self(rawValue: 0x0) + + /// HSE selected as system clock + static let HSE = Self(rawValue: 0x1) + + /// PLL selected as system clock + static let PLL = Self(rawValue: 0x2) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CIR { + struct LSIRDYIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt disabled + static let Disabled = Self(rawValue: 0x0) + + /// Interrupt enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB1RSTR { + struct GPIOARSTValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Reset the selected module + static let Reset = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB2RSTR { + struct DCMIRSTValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Reset the selected module + static let Reset = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB3RSTR { + struct FMCRSTValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Reset the selected module + static let Reset = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB1RSTR { + struct TIM2RSTValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Reset the selected module + static let Reset = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB2RSTR { + struct TIM1RSTValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Reset the selected module + static let Reset = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB1ENR { + struct GPIOAENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// The selected clock is disabled + static let Disabled = Self(rawValue: 0x0) + + /// The selected clock is enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB2ENR { + struct DCMIENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// The selected clock is disabled + static let Disabled = Self(rawValue: 0x0) + + /// The selected clock is enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB3ENR { + struct FMCENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// The selected clock is disabled + static let Disabled = Self(rawValue: 0x0) + + /// The selected clock is enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB1ENR { + struct TIM2ENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// The selected clock is disabled + static let Disabled = Self(rawValue: 0x0) + + /// The selected clock is enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB2ENR { + struct TIM1ENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// The selected clock is disabled + static let Disabled = Self(rawValue: 0x0) + + /// The selected clock is enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB1LPENR { + struct GPIOALPENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Selected module is disabled during Sleep mode + static let DisabledInSleep = Self(rawValue: 0x0) + + /// Selected module is enabled during Sleep mode + static let EnabledInSleep = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB2LPENR { + struct DCMILPENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Selected module is disabled during Sleep mode + static let DisabledInSleep = Self(rawValue: 0x0) + + /// Selected module is enabled during Sleep mode + static let EnabledInSleep = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB3LPENR { + struct FMCLPENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Selected module is disabled during Sleep mode + static let DisabledInSleep = Self(rawValue: 0x0) + + /// Selected module is enabled during Sleep mode + static let EnabledInSleep = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB1LPENR { + struct TIM2LPENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Selected module is disabled during Sleep mode + static let DisabledInSleep = Self(rawValue: 0x0) + + /// Selected module is enabled during Sleep mode + static let EnabledInSleep = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB2LPENR { + struct TIM1LPENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Selected module is disabled during Sleep mode + static let DisabledInSleep = Self(rawValue: 0x0) + + /// Selected module is enabled during Sleep mode + static let EnabledInSleep = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + struct BDRSTValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Reset not activated + static let Disabled = Self(rawValue: 0x0) + + /// Reset the entire RTC domain + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + struct RTCENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// RTC clock disabled + static let Disabled = Self(rawValue: 0x0) + + /// RTC clock enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + struct LSEBYPValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// LSE crystal oscillator not bypassed + static let NotBypassed = Self(rawValue: 0x0) + + /// LSE crystal oscillator bypassed with external clock + static let Bypassed = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + struct LSEONValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// LSE oscillator Off + static let Off = Self(rawValue: 0x0) + + /// LSE oscillator On + static let On = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + struct LSEDRVValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// Low drive capacity + static let Low = Self(rawValue: 0x0) + + /// Medium-high drive capacity + static let MediumHigh = Self(rawValue: 0x1) + + /// Medium-low drive capacity + static let MediumLow = Self(rawValue: 0x2) + + /// High drive capacity + static let High = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + struct RTCSELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// No clock + static let NoClock = Self(rawValue: 0x0) + + /// LSE oscillator clock used as RTC clock + static let LSE = Self(rawValue: 0x1) + + /// LSI oscillator clock used as RTC clock + static let LSI = Self(rawValue: 0x2) + + /// HSE oscillator clock divided by a prescaler used as RTC clock + static let HSE = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CSR { + struct LSIONValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// LSI oscillator Off + static let Off = Self(rawValue: 0x0) + + /// LSI oscillator On + static let On = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.SSCGR { + struct SSCGENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Spread spectrum modulation disabled + static let Disabled = Self(rawValue: 0x0) + + /// Spread spectrum modulation enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.SSCGR { + struct SPREADSELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Center spread + static let Center = Self(rawValue: 0x0) + + /// Down spread + static let Down = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.PLLI2SCFGR { + struct PLLI2SPValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// PLL*P=2 + static let Div2 = Self(rawValue: 0x0) + + /// PLL*P=4 + static let Div4 = Self(rawValue: 0x1) + + /// PLL*P=6 + static let Div6 = Self(rawValue: 0x2) + + /// PLL*P=8 + static let Div8 = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.PLLSAICFGR { + struct PLLSAIPValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// PLL*P=2 + static let Div2 = Self(rawValue: 0x0) + + /// PLL*P=4 + static let Div4 = Self(rawValue: 0x1) + + /// PLL*P=6 + static let Div6 = Self(rawValue: 0x2) + + /// PLL*P=8 + static let Div8 = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + struct PLLI2SDIVQValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 5 + + /// PLLI2SDIVQ = /1 + static let Div1 = Self(rawValue: 0x0) + + /// PLLI2SDIVQ = /2 + static let Div2 = Self(rawValue: 0x1) + + /// PLLI2SDIVQ = /3 + static let Div3 = Self(rawValue: 0x2) + + /// PLLI2SDIVQ = /4 + static let Div4 = Self(rawValue: 0x3) + + /// PLLI2SDIVQ = /5 + static let Div5 = Self(rawValue: 0x4) + + /// PLLI2SDIVQ = /6 + static let Div6 = Self(rawValue: 0x5) + + /// PLLI2SDIVQ = /7 + static let Div7 = Self(rawValue: 0x6) + + /// PLLI2SDIVQ = /8 + static let Div8 = Self(rawValue: 0x7) + + /// PLLI2SDIVQ = /9 + static let Div9 = Self(rawValue: 0x8) + + /// PLLI2SDIVQ = /10 + static let Div10 = Self(rawValue: 0x9) + + /// PLLI2SDIVQ = /11 + static let Div11 = Self(rawValue: 0xa) + + /// PLLI2SDIVQ = /12 + static let Div12 = Self(rawValue: 0xb) + + /// PLLI2SDIVQ = /13 + static let Div13 = Self(rawValue: 0xc) + + /// PLLI2SDIVQ = /14 + static let Div14 = Self(rawValue: 0xd) + + /// PLLI2SDIVQ = /15 + static let Div15 = Self(rawValue: 0xe) + + /// PLLI2SDIVQ = /16 + static let Div16 = Self(rawValue: 0xf) + + /// PLLI2SDIVQ = /17 + static let Div17 = Self(rawValue: 0x10) + + /// PLLI2SDIVQ = /18 + static let Div18 = Self(rawValue: 0x11) + + /// PLLI2SDIVQ = /19 + static let Div19 = Self(rawValue: 0x12) + + /// PLLI2SDIVQ = /20 + static let Div20 = Self(rawValue: 0x13) + + /// PLLI2SDIVQ = /21 + static let Div21 = Self(rawValue: 0x14) + + /// PLLI2SDIVQ = /22 + static let Div22 = Self(rawValue: 0x15) + + /// PLLI2SDIVQ = /23 + static let Div23 = Self(rawValue: 0x16) + + /// PLLI2SDIVQ = /24 + static let Div24 = Self(rawValue: 0x17) + + /// PLLI2SDIVQ = /25 + static let Div25 = Self(rawValue: 0x18) + + /// PLLI2SDIVQ = /26 + static let Div26 = Self(rawValue: 0x19) + + /// PLLI2SDIVQ = /27 + static let Div27 = Self(rawValue: 0x1a) + + /// PLLI2SDIVQ = /28 + static let Div28 = Self(rawValue: 0x1b) + + /// PLLI2SDIVQ = /29 + static let Div29 = Self(rawValue: 0x1c) + + /// PLLI2SDIVQ = /30 + static let Div30 = Self(rawValue: 0x1d) + + /// PLLI2SDIVQ = /31 + static let Div31 = Self(rawValue: 0x1e) + + /// PLLI2SDIVQ = /32 + static let Div32 = Self(rawValue: 0x1f) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + struct PLLSAIDIVQValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 5 + + /// PLLSAIDIVQ = /1 + static let Div1 = Self(rawValue: 0x0) + + /// PLLSAIDIVQ = /2 + static let Div2 = Self(rawValue: 0x1) + + /// PLLSAIDIVQ = /3 + static let Div3 = Self(rawValue: 0x2) + + /// PLLSAIDIVQ = /4 + static let Div4 = Self(rawValue: 0x3) + + /// PLLSAIDIVQ = /5 + static let Div5 = Self(rawValue: 0x4) + + /// PLLSAIDIVQ = /6 + static let Div6 = Self(rawValue: 0x5) + + /// PLLSAIDIVQ = /7 + static let Div7 = Self(rawValue: 0x6) + + /// PLLSAIDIVQ = /8 + static let Div8 = Self(rawValue: 0x7) + + /// PLLSAIDIVQ = /9 + static let Div9 = Self(rawValue: 0x8) + + /// PLLSAIDIVQ = /10 + static let Div10 = Self(rawValue: 0x9) + + /// PLLSAIDIVQ = /11 + static let Div11 = Self(rawValue: 0xa) + + /// PLLSAIDIVQ = /12 + static let Div12 = Self(rawValue: 0xb) + + /// PLLSAIDIVQ = /13 + static let Div13 = Self(rawValue: 0xc) + + /// PLLSAIDIVQ = /14 + static let Div14 = Self(rawValue: 0xd) + + /// PLLSAIDIVQ = /15 + static let Div15 = Self(rawValue: 0xe) + + /// PLLSAIDIVQ = /16 + static let Div16 = Self(rawValue: 0xf) + + /// PLLSAIDIVQ = /17 + static let Div17 = Self(rawValue: 0x10) + + /// PLLSAIDIVQ = /18 + static let Div18 = Self(rawValue: 0x11) + + /// PLLSAIDIVQ = /19 + static let Div19 = Self(rawValue: 0x12) + + /// PLLSAIDIVQ = /20 + static let Div20 = Self(rawValue: 0x13) + + /// PLLSAIDIVQ = /21 + static let Div21 = Self(rawValue: 0x14) + + /// PLLSAIDIVQ = /22 + static let Div22 = Self(rawValue: 0x15) + + /// PLLSAIDIVQ = /23 + static let Div23 = Self(rawValue: 0x16) + + /// PLLSAIDIVQ = /24 + static let Div24 = Self(rawValue: 0x17) + + /// PLLSAIDIVQ = /25 + static let Div25 = Self(rawValue: 0x18) + + /// PLLSAIDIVQ = /26 + static let Div26 = Self(rawValue: 0x19) + + /// PLLSAIDIVQ = /27 + static let Div27 = Self(rawValue: 0x1a) + + /// PLLSAIDIVQ = /28 + static let Div28 = Self(rawValue: 0x1b) + + /// PLLSAIDIVQ = /29 + static let Div29 = Self(rawValue: 0x1c) + + /// PLLSAIDIVQ = /30 + static let Div30 = Self(rawValue: 0x1d) + + /// PLLSAIDIVQ = /31 + static let Div31 = Self(rawValue: 0x1e) + + /// PLLSAIDIVQ = /32 + static let Div32 = Self(rawValue: 0x1f) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + struct PLLSAIDIVRValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// PLLSAIDIVR = /2 + static let Div2 = Self(rawValue: 0x0) + + /// PLLSAIDIVR = /4 + static let Div4 = Self(rawValue: 0x1) + + /// PLLSAIDIVR = /8 + static let Div8 = Self(rawValue: 0x2) + + /// PLLSAIDIVR = /16 + static let Div16 = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + struct SAI1SELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + static let PLLSAI = Self(rawValue: 0x0) + + /// SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + static let PLLI2S = Self(rawValue: 0x1) + + /// SAI1 clock frequency = Alternate function input frequency + static let AFIF = Self(rawValue: 0x2) + + /// SAI1 clock frequency = HSI or HSE + static let HSI_HSE = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + struct SAI2SELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + static let PLLSAI = Self(rawValue: 0x0) + + /// SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + static let PLLI2S = Self(rawValue: 0x1) + + /// SAI2 clock frequency = Alternate function input frequency + static let AFIF = Self(rawValue: 0x2) + + /// SAI2 clock frequency = HSI or HSE + static let HSI_HSE = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + struct TIMPREValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx + static let Mul1Or2 = Self(rawValue: 0x0) + + /// If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx + static let Mul1Or4 = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + struct USART1SELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// APB2 clock (PCLK2) is selected as USART clock + static let APB2 = Self(rawValue: 0x0) + + /// System clock is selected as USART clock + static let SYSCLK = Self(rawValue: 0x1) + + /// HSI clock is selected as USART clock + static let HSI = Self(rawValue: 0x2) + + /// LSE clock is selected as USART clock + static let LSE = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + struct USART2SELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// APB1 clock (PCLK1) is selected as USART clock + static let APB1 = Self(rawValue: 0x0) + + /// System clock is selected as USART clock + static let SYSCLK = Self(rawValue: 0x1) + + /// HSI clock is selected as USART clock + static let HSI = Self(rawValue: 0x2) + + /// LSE clock is selected as USART clock + static let LSE = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + struct I2C1SELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// APB clock selected as I2C clock + static let APB = Self(rawValue: 0x0) + + /// System clock selected as I2C clock + static let SYSCLK = Self(rawValue: 0x1) + + /// HSI clock selected as I2C clock + static let HSI = Self(rawValue: 0x2) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + struct LPTIM1SELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// APB1 clock (PCLK1) selected as LPTILM1 clock + static let APB1 = Self(rawValue: 0x0) + + /// LSI clock is selected as LPTILM1 clock + static let LSI = Self(rawValue: 0x1) + + /// HSI clock is selected as LPTILM1 clock + static let HSI = Self(rawValue: 0x2) + + /// LSE clock is selected as LPTILM1 clock + static let LSE = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + struct CECSELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// LSE clock is selected as HDMI-CEC clock + static let LSE = Self(rawValue: 0x0) + + /// HSI divided by 488 clock is selected as HDMI-CEC clock + static let HSI_Div488 = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + struct CK48MSELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// 48MHz clock from PLL is selected + static let PLL = Self(rawValue: 0x0) + + /// 48MHz clock from PLLSAI is selected + static let PLLSAI = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + struct SDMMC1SELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// 48 MHz clock is selected as SD clock + static let CK48M = Self(rawValue: 0x0) + + /// System clock is selected as SD clock + static let SYSCLK = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } } } diff --git a/stm32-uart-echo/Sources/Application/Registers/USART1.swift b/stm32-uart-echo/Sources/Application/Registers/USART1.swift index 19cc4ee3..6230310f 100644 --- a/stm32-uart-echo/Sources/Application/Registers/USART1.swift +++ b/stm32-uart-echo/Sources/Application/Registers/USART1.swift @@ -1,7 +1,5 @@ // Generated by svd2swift. -// swift-format-ignore-file - import MMIO /// Universal synchronous asynchronous receiver transmitter @@ -57,215 +55,175 @@ extension USART1 { @Register(bitWidth: 32) struct CR1 { /// Word length - @ReadWrite(bits: 28..<29) + @ReadWrite(bits: 28..<29, as: M1Values.self) var m1: M1 /// End of Block interrupt enable - @ReadWrite(bits: 27..<28) + @ReadWrite(bits: 27..<28, as: EOBIEValues.self) var eobie: EOBIE /// Receiver timeout interrupt enable - @ReadWrite(bits: 26..<27) + @ReadWrite(bits: 26..<27, as: RTOIEValues.self) var rtoie: RTOIE - /// Driver Enable assertion time - @ReadWrite(bits: 25..<26) - var deat4: DEAT4 - - /// DEAT3 - @ReadWrite(bits: 24..<25) - var deat3: DEAT3 - - /// DEAT2 - @ReadWrite(bits: 23..<24) - var deat2: DEAT2 - - /// DEAT1 - @ReadWrite(bits: 22..<23) - var deat1: DEAT1 - - /// DEAT0 - @ReadWrite(bits: 21..<22) - var deat0: DEAT0 - - /// Driver Enable de-assertion time - @ReadWrite(bits: 20..<21) - var dedt4: DEDT4 - - /// DEDT3 - @ReadWrite(bits: 19..<20) - var dedt3: DEDT3 - - /// DEDT2 - @ReadWrite(bits: 18..<19) - var dedt2: DEDT2 - - /// DEDT1 - @ReadWrite(bits: 17..<18) - var dedt1: DEDT1 - - /// DEDT0 - @ReadWrite(bits: 16..<17) - var dedt0: DEDT0 - /// Oversampling mode - @ReadWrite(bits: 15..<16) + @ReadWrite(bits: 15..<16, as: OVER8Values.self) var over8: OVER8 /// Character match interrupt enable - @ReadWrite(bits: 14..<15) + @ReadWrite(bits: 14..<15, as: CMIEValues.self) var cmie: CMIE /// Mute mode enable - @ReadWrite(bits: 13..<14) + @ReadWrite(bits: 13..<14, as: MMEValues.self) var mme: MME /// Word length - @ReadWrite(bits: 12..<13) + @ReadWrite(bits: 12..<13, as: M0Values.self) var m0: M0 /// Receiver wakeup method - @ReadWrite(bits: 11..<12) + @ReadWrite(bits: 11..<12, as: WAKEValues.self) var wake: WAKE /// Parity control enable - @ReadWrite(bits: 10..<11) + @ReadWrite(bits: 10..<11, as: PCEValues.self) var pce: PCE /// Parity selection - @ReadWrite(bits: 9..<10) + @ReadWrite(bits: 9..<10, as: PSValues.self) var ps: PS /// PE interrupt enable - @ReadWrite(bits: 8..<9) + @ReadWrite(bits: 8..<9, as: PEIEValues.self) var peie: PEIE /// interrupt enable - @ReadWrite(bits: 7..<8) + @ReadWrite(bits: 7..<8, as: TXEIEValues.self) var txeie: TXEIE /// Transmission complete interrupt enable - @ReadWrite(bits: 6..<7) + @ReadWrite(bits: 6..<7, as: TCIEValues.self) var tcie: TCIE /// RXNE interrupt enable - @ReadWrite(bits: 5..<6) + @ReadWrite(bits: 5..<6, as: RXNEIEValues.self) var rxneie: RXNEIE /// IDLE interrupt enable - @ReadWrite(bits: 4..<5) + @ReadWrite(bits: 4..<5, as: IDLEIEValues.self) var idleie: IDLEIE /// Transmitter enable - @ReadWrite(bits: 3..<4) + @ReadWrite(bits: 3..<4, as: TEValues.self) var te: TE /// Receiver enable - @ReadWrite(bits: 2..<3) + @ReadWrite(bits: 2..<3, as: REValues.self) var re: RE /// USART enable in Stop mode - @ReadWrite(bits: 1..<2) + @ReadWrite(bits: 1..<2, as: UESMValues.self) var uesm: UESM /// USART enable - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: UEValues.self) var ue: UE + + /// Driver Enable assertion time + @ReadWrite(bits: 21..<26) + var deat: DEAT + + /// Driver Enable de-assertion time + @ReadWrite(bits: 16..<21) + var dedt: DEDT } /// Control register 2 @Register(bitWidth: 32) struct CR2 { - /// Address of the USART node - @ReadWrite(bits: 28..<32) - var add4_7: ADD4_7 - - /// Address of the USART node - @ReadWrite(bits: 24..<28) - var add0_3: ADD0_3 - /// Receiver timeout enable - @ReadWrite(bits: 23..<24) + @ReadWrite(bits: 23..<24, as: RTOENValues.self) var rtoen: RTOEN - /// Auto baud rate mode - @ReadWrite(bits: 22..<23) - var abrmod1: ABRMOD1 - - /// ABRMOD0 - @ReadWrite(bits: 21..<22) - var abrmod0: ABRMOD0 - /// Auto baud rate enable - @ReadWrite(bits: 20..<21) + @ReadWrite(bits: 20..<21, as: ABRENValues.self) var abren: ABREN /// Most significant bit first - @ReadWrite(bits: 19..<20) + @ReadWrite(bits: 19..<20, as: MSBFIRSTValues.self) var msbfirst: MSBFIRST /// Binary data inversion - @ReadWrite(bits: 18..<19) - var tainv: TAINV + @ReadWrite(bits: 18..<19, as: DATAINVValues.self) + var datainv: DATAINV /// TX pin active level inversion - @ReadWrite(bits: 17..<18) + @ReadWrite(bits: 17..<18, as: TXINVValues.self) var txinv: TXINV /// RX pin active level inversion - @ReadWrite(bits: 16..<17) + @ReadWrite(bits: 16..<17, as: RXINVValues.self) var rxinv: RXINV /// Swap TX/RX pins - @ReadWrite(bits: 15..<16) + @ReadWrite(bits: 15..<16, as: SWAPValues.self) var swap: SWAP /// LIN mode enable - @ReadWrite(bits: 14..<15) + @ReadWrite(bits: 14..<15, as: LINENValues.self) var linen: LINEN /// STOP bits - @ReadWrite(bits: 12..<14) + @ReadWrite(bits: 12..<14, as: STOPValues.self) var stop: STOP /// Clock enable - @ReadWrite(bits: 11..<12) + @ReadWrite(bits: 11..<12, as: CLKENValues.self) var clken: CLKEN /// Clock polarity - @ReadWrite(bits: 10..<11) + @ReadWrite(bits: 10..<11, as: CPOLValues.self) var cpol: CPOL /// Clock phase - @ReadWrite(bits: 9..<10) + @ReadWrite(bits: 9..<10, as: CPHAValues.self) var cpha: CPHA /// Last bit clock pulse - @ReadWrite(bits: 8..<9) + @ReadWrite(bits: 8..<9, as: LBCLValues.self) var lbcl: LBCL /// LIN break detection interrupt enable - @ReadWrite(bits: 6..<7) + @ReadWrite(bits: 6..<7, as: LBDIEValues.self) var lbdie: LBDIE /// LIN break detection length - @ReadWrite(bits: 5..<6) + @ReadWrite(bits: 5..<6, as: LBDLValues.self) var lbdl: LBDL /// 7-bit Address Detection/4-bit Address Detection - @ReadWrite(bits: 4..<5) + @ReadWrite(bits: 4..<5, as: ADDM7Values.self) var addm7: ADDM7 + + /// Auto baud rate mode + @ReadWrite(bits: 21..<23, as: ABRMODValues.self) + var abrmod: ABRMOD + + /// Address of the USART node + @ReadWrite(bits: 24..<32) + var add: ADD } /// Control register 3 @Register(bitWidth: 32) struct CR3 { /// Wakeup from Stop mode interrupt enable - @ReadWrite(bits: 22..<23) + @ReadWrite(bits: 22..<23, as: WUFIEValues.self) var wufie: WUFIE /// Wakeup from Stop mode interrupt flag selection - @ReadWrite(bits: 20..<22) + @ReadWrite(bits: 20..<22, as: WUSValues.self) var wus: WUS /// Smartcard auto-retry count @@ -273,67 +231,67 @@ extension USART1 { var scarcnt: SCARCNT /// Driver enable polarity selection - @ReadWrite(bits: 15..<16) + @ReadWrite(bits: 15..<16, as: DEPValues.self) var dep: DEP /// Driver enable mode - @ReadWrite(bits: 14..<15) + @ReadWrite(bits: 14..<15, as: DEMValues.self) var dem: DEM /// DMA Disable on Reception Error - @ReadWrite(bits: 13..<14) + @ReadWrite(bits: 13..<14, as: DDREValues.self) var ddre: DDRE /// Overrun Disable - @ReadWrite(bits: 12..<13) + @ReadWrite(bits: 12..<13, as: OVRDISValues.self) var ovrdis: OVRDIS /// One sample bit method enable - @ReadWrite(bits: 11..<12) + @ReadWrite(bits: 11..<12, as: ONEBITValues.self) var onebit: ONEBIT /// CTS interrupt enable - @ReadWrite(bits: 10..<11) + @ReadWrite(bits: 10..<11, as: CTSIEValues.self) var ctsie: CTSIE /// CTS enable - @ReadWrite(bits: 9..<10) + @ReadWrite(bits: 9..<10, as: CTSEValues.self) var ctse: CTSE /// RTS enable - @ReadWrite(bits: 8..<9) + @ReadWrite(bits: 8..<9, as: RTSEValues.self) var rtse: RTSE /// DMA enable transmitter - @ReadWrite(bits: 7..<8) + @ReadWrite(bits: 7..<8, as: DMATValues.self) var dmat: DMAT /// DMA enable receiver - @ReadWrite(bits: 6..<7) + @ReadWrite(bits: 6..<7, as: DMARValues.self) var dmar: DMAR /// Smartcard mode enable - @ReadWrite(bits: 5..<6) + @ReadWrite(bits: 5..<6, as: SCENValues.self) var scen: SCEN /// Smartcard NACK enable - @ReadWrite(bits: 4..<5) + @ReadWrite(bits: 4..<5, as: NACKValues.self) var nack: NACK /// Half-duplex selection - @ReadWrite(bits: 3..<4) + @ReadWrite(bits: 3..<4, as: HDSELValues.self) var hdsel: HDSEL /// Ir low-power - @ReadWrite(bits: 2..<3) + @ReadWrite(bits: 2..<3, as: IRLPValues.self) var irlp: IRLP /// Ir mode enable - @ReadWrite(bits: 1..<2) + @ReadWrite(bits: 1..<2, as: IRENValues.self) var iren: IREN /// Error interrupt enable - @ReadWrite(bits: 0..<1) + @ReadWrite(bits: 0..<1, as: EIEValues.self) var eie: EIE } @@ -341,12 +299,8 @@ extension USART1 { @Register(bitWidth: 32) struct BRR { /// DIV_Mantissa - @ReadWrite(bits: 4..<16) - var div_mantissa: DIV_Mantissa - - /// DIV_Fraction - @ReadWrite(bits: 0..<4) - var div_fraction: DIV_Fraction + @ReadWrite(bits: 0..<16) + var brr_field: BRR_FIELD } /// Guard time and prescaler register @@ -557,3 +511,1044 @@ extension USART1 { var tdr_field: TDR_FIELD } } + +extension USART1.CR1 { + struct M1Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Use M0 to set the data bits + static let M0 = Self(rawValue: 0x0) + + /// 1 start bit, 7 data bits, n stop bits + static let Bit7 = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct EOBIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is inhibited + static let Disabled = Self(rawValue: 0x0) + + /// A USART interrupt is generated when the EOBF flag is set in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct RTOIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is inhibited + static let Disabled = Self(rawValue: 0x0) + + /// An USART interrupt is generated when the RTOF bit is set in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct OVER8Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Oversampling by 16 + static let Oversampling16 = Self(rawValue: 0x0) + + /// Oversampling by 8 + static let Oversampling8 = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct CMIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is disabled + static let Disabled = Self(rawValue: 0x0) + + /// Interrupt is generated when the CMF bit is set in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct MMEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Receiver in active mode permanently + static let Disabled = Self(rawValue: 0x0) + + /// Receiver can switch between mute mode and active mode + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct M0Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// 1 start bit, 8 data bits, n stop bits + static let Bit8 = Self(rawValue: 0x0) + + /// 1 start bit, 9 data bits, n stop bits + static let Bit9 = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct WAKEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Idle line + static let Idle = Self(rawValue: 0x0) + + /// Address mask + static let Address = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct PCEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Parity control disabled + static let Disabled = Self(rawValue: 0x0) + + /// Parity control enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct PSValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Even parity + static let Even = Self(rawValue: 0x0) + + /// Odd parity + static let Odd = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct PEIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is disabled + static let Disabled = Self(rawValue: 0x0) + + /// Interrupt is generated whenever PE=1 in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct TXEIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is disabled + static let Disabled = Self(rawValue: 0x0) + + /// Interrupt is generated whenever TXE=1 in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct TCIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is disabled + static let Disabled = Self(rawValue: 0x0) + + /// Interrupt is generated whenever TC=1 in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct RXNEIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is disabled + static let Disabled = Self(rawValue: 0x0) + + /// Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct IDLEIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is disabled + static let Disabled = Self(rawValue: 0x0) + + /// Interrupt is generated whenever IDLE=1 in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct TEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Transmitter is disabled + static let Disabled = Self(rawValue: 0x0) + + /// Transmitter is enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct REValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Receiver is disabled + static let Disabled = Self(rawValue: 0x0) + + /// Receiver is enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct UESMValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// USART not able to wake up the MCU from Stop mode + static let Disabled = Self(rawValue: 0x0) + + /// USART able to wake up the MCU from Stop mode + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + struct UEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// UART is disabled + static let Disabled = Self(rawValue: 0x0) + + /// UART is enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct RTOENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Receiver timeout feature disabled + static let Disabled = Self(rawValue: 0x0) + + /// Receiver timeout feature enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct ABRENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Auto baud rate detection is disabled + static let Disabled = Self(rawValue: 0x0) + + /// Auto baud rate detection is enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct MSBFIRSTValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// data is transmitted/received with data bit 0 first, following the start bit + static let LSB = Self(rawValue: 0x0) + + /// data is transmitted/received with MSB (bit 7/8/9) first, following the start bit + static let MSB = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct DATAINVValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Logical data from the data register are send/received in positive/direct logic + static let Positive = Self(rawValue: 0x0) + + /// Logical data from the data register are send/received in negative/inverse logic + static let Negative = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct TXINVValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// TX pin signal works using the standard logic levels + static let Standard = Self(rawValue: 0x0) + + /// TX pin signal values are inverted + static let Inverted = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct RXINVValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// RX pin signal works using the standard logic levels + static let Standard = Self(rawValue: 0x0) + + /// RX pin signal values are inverted + static let Inverted = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct SWAPValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// TX/RX pins are used as defined in standard pinout + static let Standard = Self(rawValue: 0x0) + + /// The TX and RX pins functions are swapped + static let Swapped = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct LINENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// LIN mode disabled + static let Disabled = Self(rawValue: 0x0) + + /// LIN mode enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct STOPValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// 1 stop bit + static let Stop1 = Self(rawValue: 0x0) + + /// 0.5 stop bit + static let Stop0p5 = Self(rawValue: 0x1) + + /// 2 stop bit + static let Stop2 = Self(rawValue: 0x2) + + /// 1.5 stop bit + static let Stop1p5 = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct CLKENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// CK pin disabled + static let Disabled = Self(rawValue: 0x0) + + /// CK pin enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct CPOLValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Steady low value on CK pin outside transmission window + static let Low = Self(rawValue: 0x0) + + /// Steady high value on CK pin outside transmission window + static let High = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct CPHAValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// The first clock transition is the first data capture edge + static let First = Self(rawValue: 0x0) + + /// The second clock transition is the first data capture edge + static let Second = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct LBCLValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// The clock pulse of the last data bit is not output to the CK pin + static let NotOutput = Self(rawValue: 0x0) + + /// The clock pulse of the last data bit is output to the CK pin + static let Output = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct LBDIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is inhibited + static let Disabled = Self(rawValue: 0x0) + + /// An interrupt is generated whenever LBDF=1 in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct LBDLValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// 10-bit break detection + static let Bit10 = Self(rawValue: 0x0) + + /// 11-bit break detection + static let Bit11 = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct ADDM7Values: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// 4-bit address detection + static let Bit4 = Self(rawValue: 0x0) + + /// 7-bit address detection + static let Bit7 = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + struct ABRMODValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// Measurement of the start bit is used to detect the baud rate + static let Start = Self(rawValue: 0x0) + + /// Falling edge to falling edge measurement + static let Edge = Self(rawValue: 0x1) + + /// 0x7F frame detection + static let Frame7F = Self(rawValue: 0x2) + + /// 0x55 frame detection + static let Frame55 = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct WUFIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is inhibited + static let Disabled = Self(rawValue: 0x0) + + /// An USART interrupt is generated whenever WUF=1 in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct WUSValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 2 + + /// WUF active on address match + static let Address = Self(rawValue: 0x0) + + /// WuF active on Start bit detection + static let Start = Self(rawValue: 0x2) + + /// WUF active on RXNE + static let RXNE = Self(rawValue: 0x3) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct DEPValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// DE signal is active high + static let High = Self(rawValue: 0x0) + + /// DE signal is active low + static let Low = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct DEMValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// DE function is disabled + static let Disabled = Self(rawValue: 0x0) + + /// The DE signal is output on the RTS pin + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct DDREValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// DMA is not disabled in case of reception error + static let NotDisabled = Self(rawValue: 0x0) + + /// DMA is disabled following a reception error + static let Disabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct OVRDISValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Overrun Error Flag, ORE, is set when received data is not read before receiving new data + static let Enabled = Self(rawValue: 0x0) + + /// Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register + static let Disabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct ONEBITValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Three sample bit method + static let Sample3 = Self(rawValue: 0x0) + + /// One sample bit method + static let Sample1 = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct CTSIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is inhibited + static let Disabled = Self(rawValue: 0x0) + + /// An interrupt is generated whenever CTSIF=1 in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct CTSEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// CTS hardware flow control disabled + static let Disabled = Self(rawValue: 0x0) + + /// CTS mode enabled, data is only transmitted when the CTS input is asserted + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct RTSEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// RTS hardware flow control disabled + static let Disabled = Self(rawValue: 0x0) + + /// RTS output enabled, data is only requested when there is space in the receive buffer + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct DMATValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// DMA mode is disabled for transmission + static let Disabled = Self(rawValue: 0x0) + + /// DMA mode is enabled for transmission + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct DMARValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// DMA mode is disabled for reception + static let Disabled = Self(rawValue: 0x0) + + /// DMA mode is enabled for reception + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct SCENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Smartcard Mode disabled + static let Disabled = Self(rawValue: 0x0) + + /// Smartcard Mode enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct NACKValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// NACK transmission in case of parity error is disabled + static let Disabled = Self(rawValue: 0x0) + + /// NACK transmission during parity error is enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct HDSELValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Half duplex mode is not selected + static let NotSelected = Self(rawValue: 0x0) + + /// Half duplex mode is selected + static let Selected = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct IRLPValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Normal mode + static let Normal = Self(rawValue: 0x0) + + /// Low-power mode + static let LowPower = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct IRENValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// IrDA disabled + static let Disabled = Self(rawValue: 0x0) + + /// IrDA enabled + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + struct EIEValues: BitFieldProjectable, RawRepresentable { + static let bitWidth = 1 + + /// Interrupt is inhibited + static let Disabled = Self(rawValue: 0x0) + + /// An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register + static let Enabled = Self(rawValue: 0x1) + + var rawValue: UInt8 + + @inlinable @inline(__always) + init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +}