diff --git a/.swiftformatignore b/.swiftformatignore index d4dc651b..3dd7359f 100644 --- a/.swiftformatignore +++ b/.swiftformatignore @@ -1,4 +1,4 @@ ./harmony/* -./stm32-lcd-logo/Sources/Application/Registers/* -./stm32-neopixel/Sources/Application/Registers/* -./stm32-uart-echo/Sources/Application/Registers/* +./stm32-lcd-logo/Sources/STM32F7X6/* +./stm32-neopixel/Sources/STM32F7X6/* +./stm32-uart-echo/Sources/STM32F7X6/* diff --git a/stm32-lcd-logo/Package.resolved b/stm32-lcd-logo/Package.resolved index a1112472..f36366ea 100644 --- a/stm32-lcd-logo/Package.resolved +++ b/stm32-lcd-logo/Package.resolved @@ -1,5 +1,5 @@ { - "originHash" : "5728b1ec253c3300a921ee6ddc3c43ff685abaa7f6ca8d86433af91b7883bf79", + "originHash" : "0259de139c240d30a60426d7d7f2d119ccc92fffcb5377eccefe0c9a21e3ef9c", "pins" : [ { "identity" : "swift-argument-parser", @@ -16,7 +16,7 @@ "location" : "https://github.com/apple/swift-mmio", "state" : { "branch" : "main", - "revision" : "daf25ecacc0d9b71036c6af32cb7786a01802799" + "revision" : "5232c5129a8c70beafc3d6acfbae2716c1b6822a" } }, { diff --git a/stm32-lcd-logo/Package.swift b/stm32-lcd-logo/Package.swift index c95815fc..29041b56 100644 --- a/stm32-lcd-logo/Package.swift +++ b/stm32-lcd-logo/Package.swift @@ -11,19 +11,28 @@ let package = Package( .package(url: "https://github.com/apple/swift-mmio", branch: "main") ], targets: [ - // SVD2Swift \ - // --input Tools/SVDs/stm32f7x6.patched.svd \ - // --output stm32-lcd-logo/Sources/STM32F7x6 \ - // --peripherals FLASH GPIOA GPIOB GPIOC GPIOD GPIOE GPIOF GPIOG GPIOH GPIOI GPIOJ GPIOK LTDC RCC .executableTarget( name: "Application", - dependencies: [ - .product(name: "MMIO", package: "swift-mmio"), - "Support", - ], + dependencies: ["STM32F7X6", "Support"], swiftSettings: [ .enableExperimentalFeature("InlineArrayTypeSugar"), .enableExperimentalFeature("SymbolLinkageMarkers"), ]), + // SVD2Swift \ + // --input Sources/STM32F7X6/stm32f7x6.patched.svd \ + // --output Sources/STM32F7X6 \ + // --access-level public \ + // --indentation-width 2 \ + // --peripherals FLASH GPIOA GPIOB GPIOC GPIOD GPIOE GPIOF GPIOG GPIOH GPIOI GPIOJ GPIOK LTDC RCC + .target( + name: "STM32F7X6", + dependencies: [ + .product(name: "MMIO", package: "swift-mmio") + ], + plugins: [ + // Plugin disabled because SwiftPM is slow. + // .plugin(name: "SVD2SwiftPlugin", package: "swift-mmio") + ]), .target(name: "Support"), - ]) + ], + swiftLanguageModes: [.v5]) diff --git a/stm32-lcd-logo/Sources/Application/Application.swift b/stm32-lcd-logo/Sources/Application/Application.swift index ad93eb33..d6ab1f67 100644 --- a/stm32-lcd-logo/Sources/Application/Application.swift +++ b/stm32-lcd-logo/Sources/Application/Application.swift @@ -9,6 +9,7 @@ // //===----------------------------------------------------------------------===// +import STM32F7X6 import Support @main diff --git a/stm32-lcd-logo/Sources/Application/HAL/GPIOA+Helpers.swift b/stm32-lcd-logo/Sources/Application/HAL/GPIOA+Helpers.swift index 1348a90a..c6e978e1 100644 --- a/stm32-lcd-logo/Sources/Application/HAL/GPIOA+Helpers.swift +++ b/stm32-lcd-logo/Sources/Application/HAL/GPIOA+Helpers.swift @@ -9,6 +9,8 @@ // //===----------------------------------------------------------------------===// +import STM32F7X6 + extension GPIOA { public enum Port: Int { case a, b, c, d, e, f, g, h, i, j, k diff --git a/stm32-lcd-logo/Sources/Application/HAL/LTDC+Helpers.swift b/stm32-lcd-logo/Sources/Application/HAL/LTDC+Helpers.swift index ec21a7b9..22c400bd 100644 --- a/stm32-lcd-logo/Sources/Application/HAL/LTDC+Helpers.swift +++ b/stm32-lcd-logo/Sources/Application/HAL/LTDC+Helpers.swift @@ -9,6 +9,7 @@ // //===----------------------------------------------------------------------===// +import STM32F7X6 import Support extension LTDC { diff --git a/stm32-lcd-logo/Sources/Application/HAL/RCC+Helpers.swift b/stm32-lcd-logo/Sources/Application/HAL/RCC+Helpers.swift index 84488921..e7eb20c3 100644 --- a/stm32-lcd-logo/Sources/Application/HAL/RCC+Helpers.swift +++ b/stm32-lcd-logo/Sources/Application/HAL/RCC+Helpers.swift @@ -1,3 +1,16 @@ +//===----------------------------------------------------------------------===// +// +// This source file is part of the Swift open source project +// +// Copyright (c) 2024 Apple Inc. and the Swift project authors. +// Licensed under Apache License v2.0 with Runtime Library Exception +// +// See https://swift.org/LICENSE.txt for license information +// +//===----------------------------------------------------------------------===// + +import STM32F7X6 + extension RCC { func enableGPIOPortClock(_ port: GPIOA.Port) { switch port { diff --git a/stm32-lcd-logo/Sources/Application/Registers/Device.swift b/stm32-lcd-logo/Sources/Application/Registers/Device.swift deleted file mode 100644 index 992bf558..00000000 --- a/stm32-lcd-logo/Sources/Application/Registers/Device.swift +++ /dev/null @@ -1,45 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// FLASH -let flash = FLASH(unsafeAddress: 0x40023c00) - -/// General-purpose I/Os -let gpioa = GPIOA(unsafeAddress: 0x40020000) - -/// General-purpose I/Os -let gpiob = GPIOB(unsafeAddress: 0x40020400) - -/// General-purpose I/Os -let gpioc = GPIOC(unsafeAddress: 0x40020800) - -/// General-purpose I/Os -let gpiod = GPIOD(unsafeAddress: 0x40020c00) - -/// General-purpose I/Os -let gpioe = GPIOE(unsafeAddress: 0x40021000) - -/// General-purpose I/Os -let gpiof = GPIOF(unsafeAddress: 0x40021400) - -/// General-purpose I/Os -let gpiog = GPIOG(unsafeAddress: 0x40021800) - -/// General-purpose I/Os -let gpioh = GPIOH(unsafeAddress: 0x40021c00) - -/// General-purpose I/Os -let gpioi = GPIOI(unsafeAddress: 0x40022000) - -/// General-purpose I/Os -let gpioj = GPIOJ(unsafeAddress: 0x40022400) - -/// General-purpose I/Os -let gpiok = GPIOK(unsafeAddress: 0x40022800) - -/// LCD-TFT Controller -let ltdc = LTDC(unsafeAddress: 0x40016800) - -/// Reset and clock control -let rcc = RCC(unsafeAddress: 0x40023800) diff --git a/stm32-lcd-logo/Sources/STM32F7X6/Device.swift b/stm32-lcd-logo/Sources/STM32F7X6/Device.swift new file mode 100644 index 00000000..3166a664 --- /dev/null +++ b/stm32-lcd-logo/Sources/STM32F7X6/Device.swift @@ -0,0 +1,45 @@ +// Generated by svd2swift. + +import MMIO + +/// FLASH +public let flash = FLASH(unsafeAddress: 0x40023c00) + +/// General-purpose I/Os +public let gpioa = GPIOA(unsafeAddress: 0x40020000) + +/// General-purpose I/Os +public let gpiob = GPIOB(unsafeAddress: 0x40020400) + +/// General-purpose I/Os +public let gpioc = GPIOC(unsafeAddress: 0x40020800) + +/// General-purpose I/Os +public let gpiod = GPIOD(unsafeAddress: 0x40020c00) + +/// General-purpose I/Os +public let gpioe = GPIOE(unsafeAddress: 0x40021000) + +/// General-purpose I/Os +public let gpiof = GPIOF(unsafeAddress: 0x40021400) + +/// General-purpose I/Os +public let gpiog = GPIOG(unsafeAddress: 0x40021800) + +/// General-purpose I/Os +public let gpioh = GPIOH(unsafeAddress: 0x40021c00) + +/// General-purpose I/Os +public let gpioi = GPIOI(unsafeAddress: 0x40022000) + +/// General-purpose I/Os +public let gpioj = GPIOJ(unsafeAddress: 0x40022400) + +/// General-purpose I/Os +public let gpiok = GPIOK(unsafeAddress: 0x40022800) + +/// LCD-TFT Controller +public let ltdc = LTDC(unsafeAddress: 0x40016800) + +/// Reset and clock control +public let rcc = RCC(unsafeAddress: 0x40023800) diff --git a/stm32-lcd-logo/Sources/STM32F7X6/Empty.swift b/stm32-lcd-logo/Sources/STM32F7X6/Empty.swift new file mode 100644 index 00000000..934a795a --- /dev/null +++ b/stm32-lcd-logo/Sources/STM32F7X6/Empty.swift @@ -0,0 +1,13 @@ +//===----------------------------------------------------------------------===// +// +// This source file is part of the Swift open source project +// +// Copyright (c) 2024 Apple Inc. and the Swift project authors. +// Licensed under Apache License v2.0 with Runtime Library Exception +// +// See https://swift.org/LICENSE.txt for license information +// +//===----------------------------------------------------------------------===// + +// This file is intentionally left empty for SwiftPM to recognize the target as +// a Swift source module. diff --git a/stm32-lcd-logo/Sources/Application/Registers/FLASH.swift b/stm32-lcd-logo/Sources/STM32F7X6/FLASH.swift similarity index 50% rename from stm32-lcd-logo/Sources/Application/Registers/FLASH.swift rename to stm32-lcd-logo/Sources/STM32F7X6/FLASH.swift index ddca3de8..1903ed94 100644 --- a/stm32-lcd-logo/Sources/Application/Registers/FLASH.swift +++ b/stm32-lcd-logo/Sources/STM32F7X6/FLASH.swift @@ -4,465 +4,465 @@ import MMIO /// FLASH @RegisterBlock -struct FLASH { +public struct FLASH { /// Flash access control register @RegisterBlock(offset: 0x0) - var acr: Register + public var acr: Register /// Flash key register @RegisterBlock(offset: 0x4) - var keyr: Register + public var keyr: Register /// Flash option key register @RegisterBlock(offset: 0x8) - var optkeyr: Register + public var optkeyr: Register /// Status register @RegisterBlock(offset: 0xc) - var sr: Register + public var sr: Register /// Control register @RegisterBlock(offset: 0x10) - var cr: Register + public var cr: Register /// Flash option control register @RegisterBlock(offset: 0x14) - var optcr: Register + public var optcr: Register /// Flash option control register 1 @RegisterBlock(offset: 0x18) - var optcr1: Register + public var optcr1: Register } extension FLASH { /// Flash access control register @Register(bitWidth: 32) - struct ACR { + public struct ACR { /// Latency @ReadWrite(bits: 0..<4, as: LATENCYValues.self) - var latency: LATENCY + public var latency: LATENCY /// Prefetch enable @ReadWrite(bits: 8..<9, as: PRFTENValues.self) - var prften: PRFTEN + public var prften: PRFTEN /// ART Accelerator Enable @ReadWrite(bits: 9..<10, as: ARTENValues.self) - var arten: ARTEN + public var arten: ARTEN /// ART Accelerator reset @ReadWrite(bits: 11..<12, as: ARTRSTValues.self) - var artrst: ARTRST + public var artrst: ARTRST } /// Flash key register @Register(bitWidth: 32) - struct KEYR { + public struct KEYR { /// FPEC key @WriteOnly(bits: 0..<32) - var key: KEY + public var key: KEY } /// Flash option key register @Register(bitWidth: 32) - struct OPTKEYR { + public struct OPTKEYR { /// Option byte key @WriteOnly(bits: 0..<32) - var optkeyr_field: OPTKEYR_FIELD + public var optkeyr_field: OPTKEYR_FIELD } /// Status register @Register(bitWidth: 32) - struct SR { + public struct SR { /// End of operation @ReadWrite(bits: 0..<1) - var eop: EOP + public var eop: EOP /// Operation error @ReadWrite(bits: 1..<2) - var operr: OPERR + public var operr: OPERR /// Write protection error @ReadWrite(bits: 4..<5) - var wrperr: WRPERR + public var wrperr: WRPERR /// Programming alignment error @ReadWrite(bits: 5..<6) - var pgaerr: PGAERR + public var pgaerr: PGAERR /// Programming parallelism error @ReadWrite(bits: 6..<7) - var pgperr: PGPERR + public var pgperr: PGPERR /// Programming sequence error @ReadWrite(bits: 7..<8) - var erserr: ERSERR + public var erserr: ERSERR /// Busy @ReadOnly(bits: 16..<17) - var bsy: BSY + public var bsy: BSY } /// Control register @Register(bitWidth: 32) - struct CR { + public struct CR { /// Programming @ReadWrite(bits: 0..<1, as: PGValues.self) - var pg: PG + public var pg: PG /// Sector Erase @ReadWrite(bits: 1..<2, as: SERValues.self) - var ser: SER + public var ser: SER /// Mass Erase of sectors 0 to 11 @ReadWrite(bits: 2..<3, as: MERValues.self) - var mer: MER + public var mer: MER /// Sector number @ReadWrite(bits: 3..<7) - var snb: SNB + public var snb: SNB /// Program size @ReadWrite(bits: 8..<10, as: PSIZEValues.self) - var psize: PSIZE + public var psize: PSIZE /// Start @ReadWrite(bits: 16..<17, as: STRTValues.self) - var strt: STRT + public var strt: STRT /// End of operation interrupt enable @ReadWrite(bits: 24..<25, as: EOPIEValues.self) - var eopie: EOPIE + public var eopie: EOPIE /// Error interrupt enable @ReadWrite(bits: 25..<26, as: ERRIEValues.self) - var errie: ERRIE + public var errie: ERRIE /// Lock @ReadWrite(bits: 31..<32, as: LOCKValues.self) - var lock: LOCK + public var lock: LOCK } /// Flash option control register @Register(bitWidth: 32) - struct OPTCR { + public struct OPTCR { /// Option lock @ReadWrite(bits: 0..<1) - var optlock: OPTLOCK + public var optlock: OPTLOCK /// Option start @ReadWrite(bits: 1..<2) - var optstrt: OPTSTRT + public var optstrt: OPTSTRT /// BOR reset Level @ReadWrite(bits: 2..<4) - var bor_lev: BOR_LEV + public var bor_lev: BOR_LEV /// User option bytes @ReadWrite(bits: 4..<5) - var wwdg_sw: WWDG_SW + public var wwdg_sw: WWDG_SW /// User option bytes @ReadWrite(bits: 5..<6) - var iwdg_sw: IWDG_SW + public var iwdg_sw: IWDG_SW /// User option bytes @ReadWrite(bits: 6..<7) - var nrst_stop: nRST_STOP + public var nrst_stop: nRST_STOP /// User option bytes @ReadWrite(bits: 7..<8) - var nrst_stdby: nRST_STDBY + public var nrst_stdby: nRST_STDBY /// Read protect @ReadWrite(bits: 8..<16) - var rdp: RDP + public var rdp: RDP /// Not write protect @ReadWrite(bits: 16..<24) - var nwrp: nWRP + public var nwrp: nWRP /// Independent watchdog counter freeze in standby mode @ReadWrite(bits: 30..<31) - var iwdg_stdby: IWDG_STDBY + public var iwdg_stdby: IWDG_STDBY /// Independent watchdog counter freeze in Stop mode @ReadWrite(bits: 31..<32) - var iwdg_stop: IWDG_STOP + public var iwdg_stop: IWDG_STOP } /// Flash option control register 1 @Register(bitWidth: 32) - struct OPTCR1 { + public struct OPTCR1 { /// Boot base address when Boot pin =0 @ReadWrite(bits: 0..<16) - var boot_add0: BOOT_ADD0 + public var boot_add0: BOOT_ADD0 /// Boot base address when Boot pin =1 @ReadWrite(bits: 16..<32) - var boot_add1: BOOT_ADD1 + public var boot_add1: BOOT_ADD1 } } extension FLASH.ACR { - struct LATENCYValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 4 + public struct LATENCYValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 4 /// 0 wait states - static let WS0 = Self(rawValue: 0x0) + public static let WS0 = Self(rawValue: 0x0) /// 1 wait states - static let WS1 = Self(rawValue: 0x1) + public static let WS1 = Self(rawValue: 0x1) /// 2 wait states - static let WS2 = Self(rawValue: 0x2) + public static let WS2 = Self(rawValue: 0x2) /// 3 wait states - static let WS3 = Self(rawValue: 0x3) + public static let WS3 = Self(rawValue: 0x3) /// 4 wait states - static let WS4 = Self(rawValue: 0x4) + public static let WS4 = Self(rawValue: 0x4) /// 5 wait states - static let WS5 = Self(rawValue: 0x5) + public static let WS5 = Self(rawValue: 0x5) /// 6 wait states - static let WS6 = Self(rawValue: 0x6) + public static let WS6 = Self(rawValue: 0x6) /// 7 wait states - static let WS7 = Self(rawValue: 0x7) + public static let WS7 = Self(rawValue: 0x7) /// 8 wait states - static let WS8 = Self(rawValue: 0x8) + public static let WS8 = Self(rawValue: 0x8) /// 9 wait states - static let WS9 = Self(rawValue: 0x9) + public static let WS9 = Self(rawValue: 0x9) /// 10 wait states - static let WS10 = Self(rawValue: 0xa) + public static let WS10 = Self(rawValue: 0xa) /// 11 wait states - static let WS11 = Self(rawValue: 0xb) + public static let WS11 = Self(rawValue: 0xb) /// 12 wait states - static let WS12 = Self(rawValue: 0xc) + public static let WS12 = Self(rawValue: 0xc) /// 13 wait states - static let WS13 = Self(rawValue: 0xd) + public static let WS13 = Self(rawValue: 0xd) /// 14 wait states - static let WS14 = Self(rawValue: 0xe) + public static let WS14 = Self(rawValue: 0xe) /// 15 wait states - static let WS15 = Self(rawValue: 0xf) + public static let WS15 = Self(rawValue: 0xf) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension FLASH.ACR { - struct PRFTENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct PRFTENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Prefetch is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Prefetch is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension FLASH.ACR { - struct ARTENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct ARTENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// ART Accelerator is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// ART Accelerator is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension FLASH.ACR { - struct ARTRSTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct ARTRSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Accelerator is not reset - static let NotReset = Self(rawValue: 0x0) + public static let NotReset = Self(rawValue: 0x0) /// Accelerator is reset - static let Reset = Self(rawValue: 0x1) + public static let Reset = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension FLASH.CR { - struct PGValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct PGValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Flash programming activated - static let Program = Self(rawValue: 0x1) + public static let Program = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension FLASH.CR { - struct SERValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct SERValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Erase activated for selected sector - static let SectorErase = Self(rawValue: 0x1) + public static let SectorErase = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension FLASH.CR { - struct MERValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct MERValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Erase activated for all user sectors - static let MassErase = Self(rawValue: 0x1) + public static let MassErase = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension FLASH.CR { - struct PSIZEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct PSIZEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// Program x8 - static let PSIZE8 = Self(rawValue: 0x0) + public static let PSIZE8 = Self(rawValue: 0x0) /// Program x16 - static let PSIZE16 = Self(rawValue: 0x1) + public static let PSIZE16 = Self(rawValue: 0x1) /// Program x32 - static let PSIZE32 = Self(rawValue: 0x2) + public static let PSIZE32 = Self(rawValue: 0x2) /// Program x64 - static let PSIZE64 = Self(rawValue: 0x3) + public static let PSIZE64 = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension FLASH.CR { - struct STRTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct STRTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Trigger an erase operation - static let Start = Self(rawValue: 0x1) + public static let Start = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension FLASH.CR { - struct EOPIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct EOPIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// End of operation interrupt disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// End of operation interrupt enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension FLASH.CR { - struct ERRIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct ERRIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Error interrupt generation disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Error interrupt generation enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension FLASH.CR { - struct LOCKValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LOCKValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// FLASH_CR register is unlocked - static let Unlocked = Self(rawValue: 0x0) + public static let Unlocked = Self(rawValue: 0x0) /// FLASH_CR register is locked - static let Locked = Self(rawValue: 0x1) + public static let Locked = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } diff --git a/stm32-uart-echo/Sources/Application/Registers/GPIOA.swift b/stm32-lcd-logo/Sources/STM32F7X6/GPIOA.swift similarity index 62% rename from stm32-uart-echo/Sources/Application/Registers/GPIOA.swift rename to stm32-lcd-logo/Sources/STM32F7X6/GPIOA.swift index 3bc4d2ff..a70e68c7 100644 --- a/stm32-uart-echo/Sources/Application/Registers/GPIOA.swift +++ b/stm32-lcd-logo/Sources/STM32F7X6/GPIOA.swift @@ -4,1071 +4,1071 @@ import MMIO /// General-purpose I/Os @RegisterBlock -struct GPIOA { +public struct GPIOA { /// GPIO port mode register @RegisterBlock(offset: 0x0) - var moder: Register + public var moder: Register /// GPIO port output type register @RegisterBlock(offset: 0x4) - var otyper: Register + public var otyper: Register /// GPIO port output speed register @RegisterBlock(offset: 0x8) - var ospeedr: Register + public var ospeedr: Register /// GPIO port pull-up/pull-down register @RegisterBlock(offset: 0xc) - var pupdr: Register + public var pupdr: Register /// GPIO port input data register @RegisterBlock(offset: 0x10) - var idr: Register + public var idr: Register /// GPIO port output data register @RegisterBlock(offset: 0x14) - var odr: Register + public var odr: Register /// GPIO port bit set/reset register @RegisterBlock(offset: 0x18) - var bsrr: Register + public var bsrr: Register /// GPIO port configuration lock register @RegisterBlock(offset: 0x1c) - var lckr: Register + public var lckr: Register /// GPIO alternate function low register @RegisterBlock(offset: 0x20) - var afrl: Register + public var afrl: Register /// GPIO alternate function high register @RegisterBlock(offset: 0x24) - var afrh: Register + public var afrh: Register /// GPIO port bit reset register @RegisterBlock(offset: 0x28) - var brr: Register + public var brr: Register } extension GPIOA { /// GPIO port mode register @Register(bitWidth: 32) - struct MODER { + public struct MODER { /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 30..<32) - var moder15: MODER15 + public var moder15: MODER15 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 28..<30) - var moder14: MODER14 + public var moder14: MODER14 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 26..<28) - var moder13: MODER13 + public var moder13: MODER13 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 24..<26) - var moder12: MODER12 + public var moder12: MODER12 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 22..<24) - var moder11: MODER11 + public var moder11: MODER11 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 20..<22) - var moder10: MODER10 + public var moder10: MODER10 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 18..<20) - var moder9: MODER9 + public var moder9: MODER9 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 16..<18) - var moder8: MODER8 + public var moder8: MODER8 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 14..<16) - var moder7: MODER7 + public var moder7: MODER7 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 12..<14) - var moder6: MODER6 + public var moder6: MODER6 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 10..<12) - var moder5: MODER5 + public var moder5: MODER5 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 8..<10) - var moder4: MODER4 + public var moder4: MODER4 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 6..<8) - var moder3: MODER3 + public var moder3: MODER3 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 4..<6) - var moder2: MODER2 + public var moder2: MODER2 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 2..<4) - var moder1: MODER1 + public var moder1: MODER1 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 0..<2, as: MODER0Values.self) - var moder0: MODER0 + public var moder0: MODER0 } /// GPIO port output type register @Register(bitWidth: 32) - struct OTYPER { + public struct OTYPER { /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 15..<16) - var ot15: OT15 + public var ot15: OT15 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 14..<15) - var ot14: OT14 + public var ot14: OT14 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 13..<14) - var ot13: OT13 + public var ot13: OT13 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 12..<13) - var ot12: OT12 + public var ot12: OT12 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 11..<12) - var ot11: OT11 + public var ot11: OT11 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 10..<11) - var ot10: OT10 + public var ot10: OT10 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 9..<10) - var ot9: OT9 + public var ot9: OT9 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 8..<9) - var ot8: OT8 + public var ot8: OT8 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 7..<8) - var ot7: OT7 + public var ot7: OT7 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 6..<7) - var ot6: OT6 + public var ot6: OT6 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 5..<6) - var ot5: OT5 + public var ot5: OT5 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 4..<5) - var ot4: OT4 + public var ot4: OT4 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 3..<4) - var ot3: OT3 + public var ot3: OT3 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 2..<3) - var ot2: OT2 + public var ot2: OT2 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 1..<2) - var ot1: OT1 + public var ot1: OT1 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 0..<1, as: OT0Values.self) - var ot0: OT0 + public var ot0: OT0 } /// GPIO port output speed register @Register(bitWidth: 32) - struct OSPEEDR { + public struct OSPEEDR { /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 30..<32) - var ospeedr15: OSPEEDR15 + public var ospeedr15: OSPEEDR15 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 28..<30) - var ospeedr14: OSPEEDR14 + public var ospeedr14: OSPEEDR14 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 26..<28) - var ospeedr13: OSPEEDR13 + public var ospeedr13: OSPEEDR13 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 24..<26) - var ospeedr12: OSPEEDR12 + public var ospeedr12: OSPEEDR12 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 22..<24) - var ospeedr11: OSPEEDR11 + public var ospeedr11: OSPEEDR11 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 20..<22) - var ospeedr10: OSPEEDR10 + public var ospeedr10: OSPEEDR10 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 18..<20) - var ospeedr9: OSPEEDR9 + public var ospeedr9: OSPEEDR9 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 16..<18) - var ospeedr8: OSPEEDR8 + public var ospeedr8: OSPEEDR8 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 14..<16) - var ospeedr7: OSPEEDR7 + public var ospeedr7: OSPEEDR7 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 12..<14) - var ospeedr6: OSPEEDR6 + public var ospeedr6: OSPEEDR6 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 10..<12) - var ospeedr5: OSPEEDR5 + public var ospeedr5: OSPEEDR5 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 8..<10) - var ospeedr4: OSPEEDR4 + public var ospeedr4: OSPEEDR4 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 6..<8) - var ospeedr3: OSPEEDR3 + public var ospeedr3: OSPEEDR3 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 4..<6) - var ospeedr2: OSPEEDR2 + public var ospeedr2: OSPEEDR2 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 2..<4) - var ospeedr1: OSPEEDR1 + public var ospeedr1: OSPEEDR1 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 0..<2, as: OSPEEDR0Values.self) - var ospeedr0: OSPEEDR0 + public var ospeedr0: OSPEEDR0 } /// GPIO port pull-up/pull-down register @Register(bitWidth: 32) - struct PUPDR { + public struct PUPDR { /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 30..<32) - var pupdr15: PUPDR15 + public var pupdr15: PUPDR15 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 28..<30) - var pupdr14: PUPDR14 + public var pupdr14: PUPDR14 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 26..<28) - var pupdr13: PUPDR13 + public var pupdr13: PUPDR13 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 24..<26) - var pupdr12: PUPDR12 + public var pupdr12: PUPDR12 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 22..<24) - var pupdr11: PUPDR11 + public var pupdr11: PUPDR11 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 20..<22) - var pupdr10: PUPDR10 + public var pupdr10: PUPDR10 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 18..<20) - var pupdr9: PUPDR9 + public var pupdr9: PUPDR9 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 16..<18) - var pupdr8: PUPDR8 + public var pupdr8: PUPDR8 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 14..<16) - var pupdr7: PUPDR7 + public var pupdr7: PUPDR7 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 12..<14) - var pupdr6: PUPDR6 + public var pupdr6: PUPDR6 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 10..<12) - var pupdr5: PUPDR5 + public var pupdr5: PUPDR5 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 8..<10) - var pupdr4: PUPDR4 + public var pupdr4: PUPDR4 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 6..<8) - var pupdr3: PUPDR3 + public var pupdr3: PUPDR3 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 4..<6) - var pupdr2: PUPDR2 + public var pupdr2: PUPDR2 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 2..<4) - var pupdr1: PUPDR1 + public var pupdr1: PUPDR1 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 0..<2, as: PUPDR0Values.self) - var pupdr0: PUPDR0 + public var pupdr0: PUPDR0 } /// GPIO port input data register @Register(bitWidth: 32) - struct IDR { + public struct IDR { /// Port input data (y = 0..15) @ReadOnly(bits: 15..<16) - var idr15: IDR15 + public var idr15: IDR15 /// Port input data (y = 0..15) @ReadOnly(bits: 14..<15) - var idr14: IDR14 + public var idr14: IDR14 /// Port input data (y = 0..15) @ReadOnly(bits: 13..<14) - var idr13: IDR13 + public var idr13: IDR13 /// Port input data (y = 0..15) @ReadOnly(bits: 12..<13) - var idr12: IDR12 + public var idr12: IDR12 /// Port input data (y = 0..15) @ReadOnly(bits: 11..<12) - var idr11: IDR11 + public var idr11: IDR11 /// Port input data (y = 0..15) @ReadOnly(bits: 10..<11) - var idr10: IDR10 + public var idr10: IDR10 /// Port input data (y = 0..15) @ReadOnly(bits: 9..<10) - var idr9: IDR9 + public var idr9: IDR9 /// Port input data (y = 0..15) @ReadOnly(bits: 8..<9) - var idr8: IDR8 + public var idr8: IDR8 /// Port input data (y = 0..15) @ReadOnly(bits: 7..<8) - var idr7: IDR7 + public var idr7: IDR7 /// Port input data (y = 0..15) @ReadOnly(bits: 6..<7) - var idr6: IDR6 + public var idr6: IDR6 /// Port input data (y = 0..15) @ReadOnly(bits: 5..<6) - var idr5: IDR5 + public var idr5: IDR5 /// Port input data (y = 0..15) @ReadOnly(bits: 4..<5) - var idr4: IDR4 + public var idr4: IDR4 /// Port input data (y = 0..15) @ReadOnly(bits: 3..<4) - var idr3: IDR3 + public var idr3: IDR3 /// Port input data (y = 0..15) @ReadOnly(bits: 2..<3) - var idr2: IDR2 + public var idr2: IDR2 /// Port input data (y = 0..15) @ReadOnly(bits: 1..<2) - var idr1: IDR1 + public var idr1: IDR1 /// Port input data (y = 0..15) @ReadOnly(bits: 0..<1) - var idr0: IDR0 + public var idr0: IDR0 } /// GPIO port output data register @Register(bitWidth: 32) - struct ODR { + public struct ODR { /// Port output data (y = 0..15) @ReadWrite(bits: 15..<16) - var odr15: ODR15 + public var odr15: ODR15 /// Port output data (y = 0..15) @ReadWrite(bits: 14..<15) - var odr14: ODR14 + public var odr14: ODR14 /// Port output data (y = 0..15) @ReadWrite(bits: 13..<14) - var odr13: ODR13 + public var odr13: ODR13 /// Port output data (y = 0..15) @ReadWrite(bits: 12..<13) - var odr12: ODR12 + public var odr12: ODR12 /// Port output data (y = 0..15) @ReadWrite(bits: 11..<12) - var odr11: ODR11 + public var odr11: ODR11 /// Port output data (y = 0..15) @ReadWrite(bits: 10..<11) - var odr10: ODR10 + public var odr10: ODR10 /// Port output data (y = 0..15) @ReadWrite(bits: 9..<10) - var odr9: ODR9 + public var odr9: ODR9 /// Port output data (y = 0..15) @ReadWrite(bits: 8..<9) - var odr8: ODR8 + public var odr8: ODR8 /// Port output data (y = 0..15) @ReadWrite(bits: 7..<8) - var odr7: ODR7 + public var odr7: ODR7 /// Port output data (y = 0..15) @ReadWrite(bits: 6..<7) - var odr6: ODR6 + public var odr6: ODR6 /// Port output data (y = 0..15) @ReadWrite(bits: 5..<6) - var odr5: ODR5 + public var odr5: ODR5 /// Port output data (y = 0..15) @ReadWrite(bits: 4..<5) - var odr4: ODR4 + public var odr4: ODR4 /// Port output data (y = 0..15) @ReadWrite(bits: 3..<4) - var odr3: ODR3 + public var odr3: ODR3 /// Port output data (y = 0..15) @ReadWrite(bits: 2..<3) - var odr2: ODR2 + public var odr2: ODR2 /// Port output data (y = 0..15) @ReadWrite(bits: 1..<2) - var odr1: ODR1 + public var odr1: ODR1 /// Port output data (y = 0..15) @ReadWrite(bits: 0..<1, as: ODR0Values.self) - var odr0: ODR0 + public var odr0: ODR0 } /// GPIO port bit set/reset register @Register(bitWidth: 32) - struct BSRR { + public struct BSRR { /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 31..<32) - var br15: BR15 + public var br15: BR15 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 30..<31) - var br14: BR14 + public var br14: BR14 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 29..<30) - var br13: BR13 + public var br13: BR13 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 28..<29) - var br12: BR12 + public var br12: BR12 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 27..<28) - var br11: BR11 + public var br11: BR11 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 26..<27) - var br10: BR10 + public var br10: BR10 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 25..<26) - var br9: BR9 + public var br9: BR9 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 24..<25) - var br8: BR8 + public var br8: BR8 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 23..<24) - var br7: BR7 + public var br7: BR7 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 22..<23) - var br6: BR6 + public var br6: BR6 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 21..<22) - var br5: BR5 + public var br5: BR5 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 20..<21) - var br4: BR4 + public var br4: BR4 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 19..<20) - var br3: BR3 + public var br3: BR3 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 18..<19) - var br2: BR2 + public var br2: BR2 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 17..<18) - var br1: BR1 + public var br1: BR1 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 16..<17) - var br0: BR0 + public var br0: BR0 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 15..<16) - var bs15: BS15 + public var bs15: BS15 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 14..<15) - var bs14: BS14 + public var bs14: BS14 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 13..<14) - var bs13: BS13 + public var bs13: BS13 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 12..<13) - var bs12: BS12 + public var bs12: BS12 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 11..<12) - var bs11: BS11 + public var bs11: BS11 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 10..<11) - var bs10: BS10 + public var bs10: BS10 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 9..<10) - var bs9: BS9 + public var bs9: BS9 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 8..<9) - var bs8: BS8 + public var bs8: BS8 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 7..<8) - var bs7: BS7 + public var bs7: BS7 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 6..<7) - var bs6: BS6 + public var bs6: BS6 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 5..<6) - var bs5: BS5 + public var bs5: BS5 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 4..<5) - var bs4: BS4 + public var bs4: BS4 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 3..<4) - var bs3: BS3 + public var bs3: BS3 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 2..<3) - var bs2: BS2 + public var bs2: BS2 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 1..<2) - var bs1: BS1 + public var bs1: BS1 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 0..<1) - var bs0: BS0 + public var bs0: BS0 } /// GPIO port configuration lock register @Register(bitWidth: 32) - struct LCKR { + public struct LCKR { /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 16..<17, as: LCKKValues.self) - var lckk: LCKK + public var lckk: LCKK /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 15..<16) - var lck15: LCK15 + public var lck15: LCK15 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 14..<15) - var lck14: LCK14 + public var lck14: LCK14 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 13..<14) - var lck13: LCK13 + public var lck13: LCK13 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 12..<13) - var lck12: LCK12 + public var lck12: LCK12 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 11..<12) - var lck11: LCK11 + public var lck11: LCK11 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 10..<11) - var lck10: LCK10 + public var lck10: LCK10 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 9..<10) - var lck9: LCK9 + public var lck9: LCK9 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 8..<9) - var lck8: LCK8 + public var lck8: LCK8 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 7..<8) - var lck7: LCK7 + public var lck7: LCK7 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 6..<7) - var lck6: LCK6 + public var lck6: LCK6 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 5..<6) - var lck5: LCK5 + public var lck5: LCK5 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 4..<5) - var lck4: LCK4 + public var lck4: LCK4 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 3..<4) - var lck3: LCK3 + public var lck3: LCK3 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 2..<3) - var lck2: LCK2 + public var lck2: LCK2 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 1..<2) - var lck1: LCK1 + public var lck1: LCK1 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 0..<1, as: LCK0Values.self) - var lck0: LCK0 + public var lck0: LCK0 } /// GPIO alternate function low register @Register(bitWidth: 32) - struct AFRL { + public struct AFRL { /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 28..<32) - var afrl7: AFRL7 + public var afrl7: AFRL7 /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 24..<28) - var afrl6: AFRL6 + public var afrl6: AFRL6 /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 20..<24) - var afrl5: AFRL5 + public var afrl5: AFRL5 /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 16..<20) - var afrl4: AFRL4 + public var afrl4: AFRL4 /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 12..<16) - var afrl3: AFRL3 + public var afrl3: AFRL3 /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 8..<12) - var afrl2: AFRL2 + public var afrl2: AFRL2 /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 4..<8) - var afrl1: AFRL1 + public var afrl1: AFRL1 /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 0..<4, as: AFRL0Values.self) - var afrl0: AFRL0 + public var afrl0: AFRL0 } /// GPIO alternate function high register @Register(bitWidth: 32) - struct AFRH { + public struct AFRH { /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 28..<32) - var afrh15: AFRH15 + public var afrh15: AFRH15 /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 24..<28) - var afrh14: AFRH14 + public var afrh14: AFRH14 /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 20..<24) - var afrh13: AFRH13 + public var afrh13: AFRH13 /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 16..<20) - var afrh12: AFRH12 + public var afrh12: AFRH12 /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 12..<16) - var afrh11: AFRH11 + public var afrh11: AFRH11 /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 8..<12) - var afrh10: AFRH10 + public var afrh10: AFRH10 /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 4..<8) - var afrh9: AFRH9 + public var afrh9: AFRH9 /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 0..<4, as: AFRH8Values.self) - var afrh8: AFRH8 + public var afrh8: AFRH8 } /// GPIO port bit reset register @Register(bitWidth: 32) - struct BRR { + public struct BRR { /// Port A Reset bit 0 @ReadWrite(bits: 0..<1) - var br0: BR0 + public var br0: BR0 /// Port A Reset bit 1 @ReadWrite(bits: 1..<2) - var br1: BR1 + public var br1: BR1 /// Port A Reset bit 2 @ReadWrite(bits: 2..<3) - var br2: BR2 + public var br2: BR2 /// Port A Reset bit 3 @ReadWrite(bits: 3..<4) - var br3: BR3 + public var br3: BR3 /// Port A Reset bit 4 @ReadWrite(bits: 4..<5) - var br4: BR4 + public var br4: BR4 /// Port A Reset bit 5 @ReadWrite(bits: 5..<6) - var br5: BR5 + public var br5: BR5 /// Port A Reset bit 6 @ReadWrite(bits: 6..<7) - var br6: BR6 + public var br6: BR6 /// Port A Reset bit 7 @ReadWrite(bits: 7..<8) - var br7: BR7 + public var br7: BR7 /// Port A Reset bit 8 @ReadWrite(bits: 8..<9) - var br8: BR8 + public var br8: BR8 /// Port A Reset bit 9 @ReadWrite(bits: 9..<10) - var br9: BR9 + public var br9: BR9 /// Port A Reset bit 10 @ReadWrite(bits: 10..<11) - var br10: BR10 + public var br10: BR10 /// Port A Reset bit 11 @ReadWrite(bits: 11..<12) - var br11: BR11 + public var br11: BR11 /// Port A Reset bit 12 @ReadWrite(bits: 12..<13) - var br12: BR12 + public var br12: BR12 /// Port A Reset bit 13 @ReadWrite(bits: 13..<14) - var br13: BR13 + public var br13: BR13 /// Port A Reset bit 14 @ReadWrite(bits: 14..<15) - var br14: BR14 + public var br14: BR14 /// Port A Reset bit 15 @ReadWrite(bits: 15..<16) - var br15: BR15 + public var br15: BR15 } } extension GPIOA.MODER { - struct MODER0Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct MODER0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// Input mode (reset state) - static let Input = Self(rawValue: 0x0) + public static let Input = Self(rawValue: 0x0) /// General purpose output mode - static let Output = Self(rawValue: 0x1) + public static let Output = Self(rawValue: 0x1) /// Alternate function mode - static let Alternate = Self(rawValue: 0x2) + public static let Alternate = Self(rawValue: 0x2) /// Analog mode - static let Analog = Self(rawValue: 0x3) + public static let Analog = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.OTYPER { - struct OT0Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct OT0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Output push-pull (reset state) - static let PushPull = Self(rawValue: 0x0) + public static let PushPull = Self(rawValue: 0x0) /// Output open-drain - static let OpenDrain = Self(rawValue: 0x1) + public static let OpenDrain = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.OSPEEDR { - struct OSPEEDR0Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct OSPEEDR0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// Low speed - static let LowSpeed = Self(rawValue: 0x0) + public static let LowSpeed = Self(rawValue: 0x0) /// Medium speed - static let MediumSpeed = Self(rawValue: 0x1) + public static let MediumSpeed = Self(rawValue: 0x1) /// High speed - static let HighSpeed = Self(rawValue: 0x2) + public static let HighSpeed = Self(rawValue: 0x2) /// Very high speed - static let VeryHighSpeed = Self(rawValue: 0x3) + public static let VeryHighSpeed = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.PUPDR { - struct PUPDR0Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct PUPDR0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// No pull-up, pull-down - static let Floating = Self(rawValue: 0x0) + public static let Floating = Self(rawValue: 0x0) /// Pull-up - static let PullUp = Self(rawValue: 0x1) + public static let PullUp = Self(rawValue: 0x1) /// Pull-down - static let PullDown = Self(rawValue: 0x2) + public static let PullDown = Self(rawValue: 0x2) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.ODR { - struct ODR0Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct ODR0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Set output to logic low - static let Low = Self(rawValue: 0x0) + public static let Low = Self(rawValue: 0x0) /// Set output to logic high - static let High = Self(rawValue: 0x1) + public static let High = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.LCKR { - struct LCKKValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LCKKValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Port configuration lock key not active - static let NotActive = Self(rawValue: 0x0) + public static let NotActive = Self(rawValue: 0x0) /// Port configuration lock key active - static let Active = Self(rawValue: 0x1) + public static let Active = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.LCKR { - struct LCK0Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LCK0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Port configuration not locked - static let Unlocked = Self(rawValue: 0x0) + public static let Unlocked = Self(rawValue: 0x0) /// Port configuration locked - static let Locked = Self(rawValue: 0x1) + public static let Locked = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.AFRL { - struct AFRL0Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 4 + public struct AFRL0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 4 /// AF0 - static let AF0 = Self(rawValue: 0x0) + public static let AF0 = Self(rawValue: 0x0) /// AF1 - static let AF1 = Self(rawValue: 0x1) + public static let AF1 = Self(rawValue: 0x1) /// AF2 - static let AF2 = Self(rawValue: 0x2) + public static let AF2 = Self(rawValue: 0x2) /// AF3 - static let AF3 = Self(rawValue: 0x3) + public static let AF3 = Self(rawValue: 0x3) /// AF4 - static let AF4 = Self(rawValue: 0x4) + public static let AF4 = Self(rawValue: 0x4) /// AF5 - static let AF5 = Self(rawValue: 0x5) + public static let AF5 = Self(rawValue: 0x5) /// AF6 - static let AF6 = Self(rawValue: 0x6) + public static let AF6 = Self(rawValue: 0x6) /// AF7 - static let AF7 = Self(rawValue: 0x7) + public static let AF7 = Self(rawValue: 0x7) /// AF8 - static let AF8 = Self(rawValue: 0x8) + public static let AF8 = Self(rawValue: 0x8) /// AF9 - static let AF9 = Self(rawValue: 0x9) + public static let AF9 = Self(rawValue: 0x9) /// AF10 - static let AF10 = Self(rawValue: 0xa) + public static let AF10 = Self(rawValue: 0xa) /// AF11 - static let AF11 = Self(rawValue: 0xb) + public static let AF11 = Self(rawValue: 0xb) /// AF12 - static let AF12 = Self(rawValue: 0xc) + public static let AF12 = Self(rawValue: 0xc) /// AF13 - static let AF13 = Self(rawValue: 0xd) + public static let AF13 = Self(rawValue: 0xd) /// AF14 - static let AF14 = Self(rawValue: 0xe) + public static let AF14 = Self(rawValue: 0xe) /// AF15 - static let AF15 = Self(rawValue: 0xf) + public static let AF15 = Self(rawValue: 0xf) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.AFRH { - struct AFRH8Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 4 + public struct AFRH8Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 4 /// AF0 - static let AF0 = Self(rawValue: 0x0) + public static let AF0 = Self(rawValue: 0x0) /// AF1 - static let AF1 = Self(rawValue: 0x1) + public static let AF1 = Self(rawValue: 0x1) /// AF2 - static let AF2 = Self(rawValue: 0x2) + public static let AF2 = Self(rawValue: 0x2) /// AF3 - static let AF3 = Self(rawValue: 0x3) + public static let AF3 = Self(rawValue: 0x3) /// AF4 - static let AF4 = Self(rawValue: 0x4) + public static let AF4 = Self(rawValue: 0x4) /// AF5 - static let AF5 = Self(rawValue: 0x5) + public static let AF5 = Self(rawValue: 0x5) /// AF6 - static let AF6 = Self(rawValue: 0x6) + public static let AF6 = Self(rawValue: 0x6) /// AF7 - static let AF7 = Self(rawValue: 0x7) + public static let AF7 = Self(rawValue: 0x7) /// AF8 - static let AF8 = Self(rawValue: 0x8) + public static let AF8 = Self(rawValue: 0x8) /// AF9 - static let AF9 = Self(rawValue: 0x9) + public static let AF9 = Self(rawValue: 0x9) /// AF10 - static let AF10 = Self(rawValue: 0xa) + public static let AF10 = Self(rawValue: 0xa) /// AF11 - static let AF11 = Self(rawValue: 0xb) + public static let AF11 = Self(rawValue: 0xb) /// AF12 - static let AF12 = Self(rawValue: 0xc) + public static let AF12 = Self(rawValue: 0xc) /// AF13 - static let AF13 = Self(rawValue: 0xd) + public static let AF13 = Self(rawValue: 0xd) /// AF14 - static let AF14 = Self(rawValue: 0xe) + public static let AF14 = Self(rawValue: 0xe) /// AF15 - static let AF15 = Self(rawValue: 0xf) + public static let AF15 = Self(rawValue: 0xf) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } diff --git a/stm32-neopixel/Sources/Application/Registers/GPIOB.swift b/stm32-lcd-logo/Sources/STM32F7X6/GPIOB.swift similarity index 68% rename from stm32-neopixel/Sources/Application/Registers/GPIOB.swift rename to stm32-lcd-logo/Sources/STM32F7X6/GPIOB.swift index c820355f..bd0a35ba 100644 --- a/stm32-neopixel/Sources/Application/Registers/GPIOB.swift +++ b/stm32-lcd-logo/Sources/STM32F7X6/GPIOB.swift @@ -3,5 +3,5 @@ import MMIO /// General-purpose I/Os -typealias GPIOB = GPIOA +public typealias GPIOB = GPIOA diff --git a/stm32-lcd-logo/Sources/Application/Registers/GPIOC.swift b/stm32-lcd-logo/Sources/STM32F7X6/GPIOC.swift similarity index 68% rename from stm32-lcd-logo/Sources/Application/Registers/GPIOC.swift rename to stm32-lcd-logo/Sources/STM32F7X6/GPIOC.swift index 76543eca..c46e6690 100644 --- a/stm32-lcd-logo/Sources/Application/Registers/GPIOC.swift +++ b/stm32-lcd-logo/Sources/STM32F7X6/GPIOC.swift @@ -3,5 +3,5 @@ import MMIO /// General-purpose I/Os -typealias GPIOC = GPIOA +public typealias GPIOC = GPIOA diff --git a/stm32-lcd-logo/Sources/Application/Registers/GPIOD.swift b/stm32-lcd-logo/Sources/STM32F7X6/GPIOD.swift similarity index 68% rename from stm32-lcd-logo/Sources/Application/Registers/GPIOD.swift rename to stm32-lcd-logo/Sources/STM32F7X6/GPIOD.swift index d54a0d5b..d51ac802 100644 --- a/stm32-lcd-logo/Sources/Application/Registers/GPIOD.swift +++ b/stm32-lcd-logo/Sources/STM32F7X6/GPIOD.swift @@ -3,5 +3,5 @@ import MMIO /// General-purpose I/Os -typealias GPIOD = GPIOA +public typealias GPIOD = GPIOA diff --git a/stm32-lcd-logo/Sources/Application/Registers/GPIOE.swift b/stm32-lcd-logo/Sources/STM32F7X6/GPIOE.swift similarity index 68% rename from stm32-lcd-logo/Sources/Application/Registers/GPIOE.swift rename to stm32-lcd-logo/Sources/STM32F7X6/GPIOE.swift index 08b7facf..c78fa87f 100644 --- a/stm32-lcd-logo/Sources/Application/Registers/GPIOE.swift +++ b/stm32-lcd-logo/Sources/STM32F7X6/GPIOE.swift @@ -3,5 +3,5 @@ import MMIO /// General-purpose I/Os -typealias GPIOE = GPIOA +public typealias GPIOE = GPIOA diff --git a/stm32-lcd-logo/Sources/Application/Registers/GPIOF.swift b/stm32-lcd-logo/Sources/STM32F7X6/GPIOF.swift similarity index 68% rename from stm32-lcd-logo/Sources/Application/Registers/GPIOF.swift rename to stm32-lcd-logo/Sources/STM32F7X6/GPIOF.swift index a0502a12..f4dce7fb 100644 --- a/stm32-lcd-logo/Sources/Application/Registers/GPIOF.swift +++ b/stm32-lcd-logo/Sources/STM32F7X6/GPIOF.swift @@ -3,5 +3,5 @@ import MMIO /// General-purpose I/Os -typealias GPIOF = GPIOA +public typealias GPIOF = GPIOA diff --git a/stm32-lcd-logo/Sources/Application/Registers/GPIOG.swift b/stm32-lcd-logo/Sources/STM32F7X6/GPIOG.swift similarity index 68% rename from stm32-lcd-logo/Sources/Application/Registers/GPIOG.swift rename to stm32-lcd-logo/Sources/STM32F7X6/GPIOG.swift index 1bfc7fd8..88fb4c6a 100644 --- a/stm32-lcd-logo/Sources/Application/Registers/GPIOG.swift +++ b/stm32-lcd-logo/Sources/STM32F7X6/GPIOG.swift @@ -3,5 +3,5 @@ import MMIO /// General-purpose I/Os -typealias GPIOG = GPIOA +public typealias GPIOG = GPIOA diff --git a/stm32-lcd-logo/Sources/Application/Registers/GPIOH.swift b/stm32-lcd-logo/Sources/STM32F7X6/GPIOH.swift similarity index 68% rename from stm32-lcd-logo/Sources/Application/Registers/GPIOH.swift rename to stm32-lcd-logo/Sources/STM32F7X6/GPIOH.swift index 3384a586..5a558ef3 100644 --- a/stm32-lcd-logo/Sources/Application/Registers/GPIOH.swift +++ b/stm32-lcd-logo/Sources/STM32F7X6/GPIOH.swift @@ -3,5 +3,5 @@ import MMIO /// General-purpose I/Os -typealias GPIOH = GPIOA +public typealias GPIOH = GPIOA diff --git a/stm32-lcd-logo/Sources/Application/Registers/GPIOI.swift b/stm32-lcd-logo/Sources/STM32F7X6/GPIOI.swift similarity index 68% rename from stm32-lcd-logo/Sources/Application/Registers/GPIOI.swift rename to stm32-lcd-logo/Sources/STM32F7X6/GPIOI.swift index f7e28cc8..6b2b5182 100644 --- a/stm32-lcd-logo/Sources/Application/Registers/GPIOI.swift +++ b/stm32-lcd-logo/Sources/STM32F7X6/GPIOI.swift @@ -3,5 +3,5 @@ import MMIO /// General-purpose I/Os -typealias GPIOI = GPIOA +public typealias GPIOI = GPIOA diff --git a/stm32-lcd-logo/Sources/Application/Registers/GPIOJ.swift b/stm32-lcd-logo/Sources/STM32F7X6/GPIOJ.swift similarity index 68% rename from stm32-lcd-logo/Sources/Application/Registers/GPIOJ.swift rename to stm32-lcd-logo/Sources/STM32F7X6/GPIOJ.swift index 6e349edb..98b3c09a 100644 --- a/stm32-lcd-logo/Sources/Application/Registers/GPIOJ.swift +++ b/stm32-lcd-logo/Sources/STM32F7X6/GPIOJ.swift @@ -3,5 +3,5 @@ import MMIO /// General-purpose I/Os -typealias GPIOJ = GPIOA +public typealias GPIOJ = GPIOA diff --git a/stm32-lcd-logo/Sources/Application/Registers/GPIOK.swift b/stm32-lcd-logo/Sources/STM32F7X6/GPIOK.swift similarity index 68% rename from stm32-lcd-logo/Sources/Application/Registers/GPIOK.swift rename to stm32-lcd-logo/Sources/STM32F7X6/GPIOK.swift index ca28ed7e..c1f074b8 100644 --- a/stm32-lcd-logo/Sources/Application/Registers/GPIOK.swift +++ b/stm32-lcd-logo/Sources/STM32F7X6/GPIOK.swift @@ -3,5 +3,5 @@ import MMIO /// General-purpose I/Os -typealias GPIOK = GPIOA +public typealias GPIOK = GPIOA diff --git a/stm32-lcd-logo/Sources/Application/Registers/LTDC.swift b/stm32-lcd-logo/Sources/STM32F7X6/LTDC.swift similarity index 59% rename from stm32-lcd-logo/Sources/Application/Registers/LTDC.swift rename to stm32-lcd-logo/Sources/STM32F7X6/LTDC.swift index bbbe2dbe..7dd4bf0a 100644 --- a/stm32-lcd-logo/Sources/Application/Registers/LTDC.swift +++ b/stm32-lcd-logo/Sources/STM32F7X6/LTDC.swift @@ -4,843 +4,843 @@ import MMIO /// LCD-TFT Controller @RegisterBlock -struct LTDC { +public struct LTDC { /// Synchronization Size Configuration Register @RegisterBlock(offset: 0x8) - var sscr: Register + public var sscr: Register /// Back Porch Configuration Register @RegisterBlock(offset: 0xc) - var bpcr: Register + public var bpcr: Register /// Active Width Configuration Register @RegisterBlock(offset: 0x10) - var awcr: Register + public var awcr: Register /// Total Width Configuration Register @RegisterBlock(offset: 0x14) - var twcr: Register + public var twcr: Register /// Global Control Register @RegisterBlock(offset: 0x18) - var gcr: Register + public var gcr: Register /// Shadow Reload Configuration Register @RegisterBlock(offset: 0x24) - var srcr: Register + public var srcr: Register /// Background Color Configuration Register @RegisterBlock(offset: 0x2c) - var bccr: Register + public var bccr: Register /// Interrupt Enable Register @RegisterBlock(offset: 0x34) - var ier: Register + public var ier: Register /// Interrupt Status Register @RegisterBlock(offset: 0x38) - var isr: Register + public var isr: Register /// Interrupt Clear Register @RegisterBlock(offset: 0x3c) - var icr: Register + public var icr: Register /// Line Interrupt Position Configuration Register @RegisterBlock(offset: 0x40) - var lipcr: Register + public var lipcr: Register /// Current Position Status Register @RegisterBlock(offset: 0x44) - var cpsr: Register + public var cpsr: Register /// Current Display Status Register @RegisterBlock(offset: 0x48) - var cdsr: Register + public var cdsr: Register /// Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR @RegisterBlock(offset: 0x84, stride: 0x80, count: 2) - var layer: RegisterArray + public var layer: RegisterArray } extension LTDC { /// Synchronization Size Configuration Register @Register(bitWidth: 32) - struct SSCR { + public struct SSCR { /// Horizontal Synchronization Width (in units of pixel clock period) @ReadWrite(bits: 16..<28) - var hsw: HSW + public var hsw: HSW /// Vertical Synchronization Height (in units of horizontal scan line) @ReadWrite(bits: 0..<11) - var vsh: VSH + public var vsh: VSH } /// Back Porch Configuration Register @Register(bitWidth: 32) - struct BPCR { + public struct BPCR { /// Accumulated Horizontal back porch (in units of pixel clock period) @ReadWrite(bits: 16..<28) - var ahbp: AHBP + public var ahbp: AHBP /// Accumulated Vertical back porch (in units of horizontal scan line) @ReadWrite(bits: 0..<11) - var avbp: AVBP + public var avbp: AVBP } /// Active Width Configuration Register @Register(bitWidth: 32) - struct AWCR { + public struct AWCR { /// Accumulated Active Width (in units of pixel clock period) @ReadWrite(bits: 16..<28) - var aaw: AAW + public var aaw: AAW /// Accumulated Active Height (in units of horizontal scan line) @ReadWrite(bits: 0..<11) - var aah: AAH + public var aah: AAH } /// Total Width Configuration Register @Register(bitWidth: 32) - struct TWCR { + public struct TWCR { /// Total Width (in units of pixel clock period) @ReadWrite(bits: 16..<28) - var totalw: TOTALW + public var totalw: TOTALW /// Total Height (in units of horizontal scan line) @ReadWrite(bits: 0..<11) - var totalh: TOTALH + public var totalh: TOTALH } /// Global Control Register @Register(bitWidth: 32) - struct GCR { + public struct GCR { /// Horizontal Synchronization Polarity @ReadWrite(bits: 31..<32, as: HSPOLValues.self) - var hspol: HSPOL + public var hspol: HSPOL /// Vertical Synchronization Polarity @ReadWrite(bits: 30..<31, as: VSPOLValues.self) - var vspol: VSPOL + public var vspol: VSPOL /// Data Enable Polarity @ReadWrite(bits: 29..<30, as: DEPOLValues.self) - var depol: DEPOL + public var depol: DEPOL /// Pixel Clock Polarity @ReadWrite(bits: 28..<29, as: PCPOLValues.self) - var pcpol: PCPOL + public var pcpol: PCPOL /// Dither Enable @ReadWrite(bits: 16..<17, as: DENValues.self) - var den: DEN + public var den: DEN /// Dither Red Width @ReadOnly(bits: 12..<15) - var drw: DRW + public var drw: DRW /// Dither Green Width @ReadOnly(bits: 8..<11) - var dgw: DGW + public var dgw: DGW /// Dither Blue Width @ReadOnly(bits: 4..<7) - var dbw: DBW + public var dbw: DBW /// LCD-TFT controller enable bit @ReadWrite(bits: 0..<1, as: LTDCENValues.self) - var ltdcen: LTDCEN + public var ltdcen: LTDCEN } /// Shadow Reload Configuration Register @Register(bitWidth: 32) - struct SRCR { + public struct SRCR { /// Vertical Blanking Reload @ReadWrite(bits: 1..<2, as: VBRValues.self) - var vbr: VBR + public var vbr: VBR /// Immediate Reload @ReadWrite(bits: 0..<1, as: IMRValues.self) - var imr: IMR + public var imr: IMR } /// Background Color Configuration Register @Register(bitWidth: 32) - struct BCCR { + public struct BCCR { /// Background color blue value @ReadWrite(bits: 0..<8) - var bcblue: BCBLUE + public var bcblue: BCBLUE /// Background color green value @ReadWrite(bits: 8..<16) - var bcgreen: BCGREEN + public var bcgreen: BCGREEN /// Background color red value @ReadWrite(bits: 16..<24) - var bcred: BCRED + public var bcred: BCRED } /// Interrupt Enable Register @Register(bitWidth: 32) - struct IER { + public struct IER { /// Register Reload interrupt enable @ReadWrite(bits: 3..<4, as: RRIEValues.self) - var rrie: RRIE + public var rrie: RRIE /// Transfer Error Interrupt Enable @ReadWrite(bits: 2..<3, as: TERRIEValues.self) - var terrie: TERRIE + public var terrie: TERRIE /// FIFO Underrun Interrupt Enable @ReadWrite(bits: 1..<2, as: FUIEValues.self) - var fuie: FUIE + public var fuie: FUIE /// Line Interrupt Enable @ReadWrite(bits: 0..<1, as: LIEValues.self) - var lie: LIE + public var lie: LIE } /// Interrupt Status Register @Register(bitWidth: 32) - struct ISR { + public struct ISR { /// Register Reload Interrupt Flag @ReadOnly(bits: 3..<4) - var rrif: RRIF + public var rrif: RRIF /// Transfer Error interrupt flag @ReadOnly(bits: 2..<3) - var terrif: TERRIF + public var terrif: TERRIF /// FIFO Underrun Interrupt flag @ReadOnly(bits: 1..<2) - var fuif: FUIF + public var fuif: FUIF /// Line Interrupt flag @ReadOnly(bits: 0..<1) - var lif: LIF + public var lif: LIF } /// Interrupt Clear Register @Register(bitWidth: 32) - struct ICR { + public struct ICR { /// Clears Register Reload Interrupt Flag @WriteOnly(bits: 3..<4) - var crrif: CRRIF + public var crrif: CRRIF /// Clears the Transfer Error Interrupt Flag @WriteOnly(bits: 2..<3) - var cterrif: CTERRIF + public var cterrif: CTERRIF /// Clears the FIFO Underrun Interrupt flag @WriteOnly(bits: 1..<2) - var cfuif: CFUIF + public var cfuif: CFUIF /// Clears the Line Interrupt Flag @WriteOnly(bits: 0..<1) - var clif: CLIF + public var clif: CLIF } /// Line Interrupt Position Configuration Register @Register(bitWidth: 32) - struct LIPCR { + public struct LIPCR { /// Line Interrupt Position @ReadWrite(bits: 0..<11) - var lipos: LIPOS + public var lipos: LIPOS } /// Current Position Status Register @Register(bitWidth: 32) - struct CPSR { + public struct CPSR { /// Current X Position @ReadOnly(bits: 16..<32) - var cxpos: CXPOS + public var cxpos: CXPOS /// Current Y Position @ReadOnly(bits: 0..<16) - var cypos: CYPOS + public var cypos: CYPOS } /// Current Display Status Register @Register(bitWidth: 32) - struct CDSR { + public struct CDSR { /// Horizontal Synchronization display Status @ReadOnly(bits: 3..<4) - var hsyncs: HSYNCS + public var hsyncs: HSYNCS /// Vertical Synchronization display Status @ReadOnly(bits: 2..<3) - var vsyncs: VSYNCS + public var vsyncs: VSYNCS /// Horizontal Data Enable display Status @ReadOnly(bits: 1..<2) - var hdes: HDES + public var hdes: HDES /// Vertical Data Enable display Status @ReadOnly(bits: 0..<1) - var vdes: VDES + public var vdes: VDES } /// Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR @RegisterBlock - struct LAYER { + public struct LAYER { /// Layerx Control Register @RegisterBlock(offset: 0x0) - var cr: Register + public var cr: Register /// Layerx Window Horizontal Position Configuration Register @RegisterBlock(offset: 0x4) - var whpcr: Register + public var whpcr: Register /// Layerx Window Vertical Position Configuration Register @RegisterBlock(offset: 0x8) - var wvpcr: Register + public var wvpcr: Register /// Layerx Color Keying Configuration Register @RegisterBlock(offset: 0xc) - var ckcr: Register + public var ckcr: Register /// Layerx Pixel Format Configuration Register @RegisterBlock(offset: 0x10) - var pfcr: Register + public var pfcr: Register /// Layerx Constant Alpha Configuration Register @RegisterBlock(offset: 0x14) - var cacr: Register + public var cacr: Register /// Layerx Default Color Configuration Register @RegisterBlock(offset: 0x18) - var dccr: Register + public var dccr: Register /// Layerx Blending Factors Configuration Register @RegisterBlock(offset: 0x1c) - var bfcr: Register + public var bfcr: Register /// Layerx Color Frame Buffer Address Register @RegisterBlock(offset: 0x28) - var cfbar: Register + public var cfbar: Register /// Layerx Color Frame Buffer Length Register @RegisterBlock(offset: 0x2c) - var cfblr: Register + public var cfblr: Register /// Layerx ColorFrame Buffer Line Number Register @RegisterBlock(offset: 0x30) - var cfblnr: Register + public var cfblnr: Register /// Layerx CLUT Write Register @RegisterBlock(offset: 0x40) - var clutwr: Register + public var clutwr: Register } } extension LTDC.LAYER { /// Layerx Control Register @Register(bitWidth: 32) - struct CR { + public struct CR { /// Color Look-Up Table Enable @ReadWrite(bits: 4..<5, as: CLUTENValues.self) - var cluten: CLUTEN + public var cluten: CLUTEN /// Color Keying Enable @ReadWrite(bits: 1..<2, as: COLKENValues.self) - var colken: COLKEN + public var colken: COLKEN /// Layer Enable @ReadWrite(bits: 0..<1, as: LENValues.self) - var len: LEN + public var len: LEN } /// Layerx Window Horizontal Position Configuration Register @Register(bitWidth: 32) - struct WHPCR { + public struct WHPCR { /// Window Horizontal Stop Position @ReadWrite(bits: 16..<28) - var whsppos: WHSPPOS + public var whsppos: WHSPPOS /// Window Horizontal Start Position @ReadWrite(bits: 0..<12) - var whstpos: WHSTPOS + public var whstpos: WHSTPOS } /// Layerx Window Vertical Position Configuration Register @Register(bitWidth: 32) - struct WVPCR { + public struct WVPCR { /// Window Vertical Stop Position @ReadWrite(bits: 16..<27) - var wvsppos: WVSPPOS + public var wvsppos: WVSPPOS /// Window Vertical Start Position @ReadWrite(bits: 0..<11) - var wvstpos: WVSTPOS + public var wvstpos: WVSTPOS } /// Layerx Color Keying Configuration Register @Register(bitWidth: 32) - struct CKCR { + public struct CKCR { /// Color Key Red value @ReadWrite(bits: 16..<24) - var ckred: CKRED + public var ckred: CKRED /// Color Key Green value @ReadWrite(bits: 8..<16) - var ckgreen: CKGREEN + public var ckgreen: CKGREEN /// Color Key Blue value @ReadWrite(bits: 0..<8) - var ckblue: CKBLUE + public var ckblue: CKBLUE } /// Layerx Pixel Format Configuration Register @Register(bitWidth: 32) - struct PFCR { + public struct PFCR { /// Pixel Format @ReadWrite(bits: 0..<3, as: PFValues.self) - var pf: PF + public var pf: PF } /// Layerx Constant Alpha Configuration Register @Register(bitWidth: 32) - struct CACR { + public struct CACR { /// Constant Alpha @ReadWrite(bits: 0..<8) - var consta: CONSTA + public var consta: CONSTA } /// Layerx Default Color Configuration Register @Register(bitWidth: 32) - struct DCCR { + public struct DCCR { /// Default Color Alpha @ReadWrite(bits: 24..<32) - var dcalpha: DCALPHA + public var dcalpha: DCALPHA /// Default Color Red @ReadWrite(bits: 16..<24) - var dcred: DCRED + public var dcred: DCRED /// Default Color Green @ReadWrite(bits: 8..<16) - var dcgreen: DCGREEN + public var dcgreen: DCGREEN /// Default Color Blue @ReadWrite(bits: 0..<8) - var dcblue: DCBLUE + public var dcblue: DCBLUE } /// Layerx Blending Factors Configuration Register @Register(bitWidth: 32) - struct BFCR { + public struct BFCR { /// Blending Factor 1 @ReadWrite(bits: 8..<11, as: BF1Values.self) - var bf1: BF1 + public var bf1: BF1 /// Blending Factor 2 @ReadWrite(bits: 0..<3, as: BF2Values.self) - var bf2: BF2 + public var bf2: BF2 } /// Layerx Color Frame Buffer Address Register @Register(bitWidth: 32) - struct CFBAR { + public struct CFBAR { /// Color Frame Buffer Start Address @ReadWrite(bits: 0..<32) - var cfbadd: CFBADD + public var cfbadd: CFBADD } /// Layerx Color Frame Buffer Length Register @Register(bitWidth: 32) - struct CFBLR { + public struct CFBLR { /// Color Frame Buffer Pitch in bytes @ReadWrite(bits: 16..<29) - var cfbp: CFBP + public var cfbp: CFBP /// Color Frame Buffer Line Length @ReadWrite(bits: 0..<13) - var cfbll: CFBLL + public var cfbll: CFBLL } /// Layerx ColorFrame Buffer Line Number Register @Register(bitWidth: 32) - struct CFBLNR { + public struct CFBLNR { /// Frame Buffer Line Number @ReadWrite(bits: 0..<11) - var cfblnbr: CFBLNBR + public var cfblnbr: CFBLNBR } /// Layerx CLUT Write Register @Register(bitWidth: 32) - struct CLUTWR { + public struct CLUTWR { /// CLUT Address @WriteOnly(bits: 24..<32) - var clutadd: CLUTADD + public var clutadd: CLUTADD /// Red value @WriteOnly(bits: 16..<24) - var red: RED + public var red: RED /// Green value @WriteOnly(bits: 8..<16) - var green: GREEN + public var green: GREEN /// Blue value @WriteOnly(bits: 0..<8) - var blue: BLUE + public var blue: BLUE } } extension LTDC.GCR { - struct HSPOLValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct HSPOLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Horizontal synchronization polarity is active low - static let ActiveLow = Self(rawValue: 0x0) + public static let ActiveLow = Self(rawValue: 0x0) /// Horizontal synchronization polarity is active high - static let ActiveHigh = Self(rawValue: 0x1) + public static let ActiveHigh = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension LTDC.GCR { - struct VSPOLValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct VSPOLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Vertical synchronization polarity is active low - static let ActiveLow = Self(rawValue: 0x0) + public static let ActiveLow = Self(rawValue: 0x0) /// Vertical synchronization polarity is active high - static let ActiveHigh = Self(rawValue: 0x1) + public static let ActiveHigh = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension LTDC.GCR { - struct DEPOLValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DEPOLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Data enable polarity is active low - static let ActiveLow = Self(rawValue: 0x0) + public static let ActiveLow = Self(rawValue: 0x0) /// Data enable polarity is active high - static let ActiveHigh = Self(rawValue: 0x1) + public static let ActiveHigh = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension LTDC.GCR { - struct PCPOLValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct PCPOLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Pixel clock on rising edge - static let RisingEdge = Self(rawValue: 0x0) + public static let RisingEdge = Self(rawValue: 0x0) /// Pixel clock on falling edge - static let FallingEdge = Self(rawValue: 0x1) + public static let FallingEdge = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension LTDC.GCR { - struct DENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Dither disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Dither enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension LTDC.GCR { - struct LTDCENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LTDCENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// LCD-TFT controller disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// LCD-TFT controller enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension LTDC.SRCR { - struct VBRValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct VBRValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) - static let NoEffect = Self(rawValue: 0x0) + public static let NoEffect = Self(rawValue: 0x0) /// The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). - static let Reload = Self(rawValue: 0x1) + public static let Reload = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension LTDC.SRCR { - struct IMRValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct IMRValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) - static let NoEffect = Self(rawValue: 0x0) + public static let NoEffect = Self(rawValue: 0x0) /// The shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload - static let Reload = Self(rawValue: 0x1) + public static let Reload = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension LTDC.IER { - struct RRIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct RRIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Register reload interrupt disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Register reload interrupt enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension LTDC.IER { - struct TERRIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TERRIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Transfer error interrupt disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Transfer error interrupt enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension LTDC.IER { - struct FUIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct FUIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// FIFO underrun interrupt disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// FIFO underrun interrupt enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension LTDC.IER { - struct LIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Line interrupt disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Line interrupt enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension LTDC.LAYER.CR { - struct CLUTENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CLUTENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Color look-up table disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Color look-up table enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension LTDC.LAYER.CR { - struct COLKENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct COLKENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Color keying disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Color keying enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension LTDC.LAYER.CR { - struct LENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Layer disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Layer enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension LTDC.LAYER.PFCR { - struct PFValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 3 + public struct PFValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 3 /// ARGB8888 - static let ARGB8888 = Self(rawValue: 0x0) + public static let ARGB8888 = Self(rawValue: 0x0) /// RGB888 - static let RGB888 = Self(rawValue: 0x1) + public static let RGB888 = Self(rawValue: 0x1) /// RGB565 - static let RGB565 = Self(rawValue: 0x2) + public static let RGB565 = Self(rawValue: 0x2) /// ARGB1555 - static let ARGB1555 = Self(rawValue: 0x3) + public static let ARGB1555 = Self(rawValue: 0x3) /// ARGB4444 - static let ARGB4444 = Self(rawValue: 0x4) + public static let ARGB4444 = Self(rawValue: 0x4) /// L8 (8-bit luminance) - static let L8 = Self(rawValue: 0x5) + public static let L8 = Self(rawValue: 0x5) /// AL44 (4-bit alpha, 4-bit luminance) - static let AL44 = Self(rawValue: 0x6) + public static let AL44 = Self(rawValue: 0x6) /// AL88 (8-bit alpha, 8-bit luminance) - static let AL88 = Self(rawValue: 0x7) + public static let AL88 = Self(rawValue: 0x7) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension LTDC.LAYER.BFCR { - struct BF1Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 3 + public struct BF1Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 3 /// BF1 = constant alpha - static let Constant = Self(rawValue: 0x4) + public static let Constant = Self(rawValue: 0x4) /// BF1 = pixel alpha * constant alpha - static let Pixel = Self(rawValue: 0x6) + public static let Pixel = Self(rawValue: 0x6) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension LTDC.LAYER.BFCR { - struct BF2Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 3 + public struct BF2Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 3 /// BF2 = 1 - constant alpha - static let Constant = Self(rawValue: 0x5) + public static let Constant = Self(rawValue: 0x5) /// BF2 = 1 - pixel alpha * constant alpha - static let Pixel = Self(rawValue: 0x7) + public static let Pixel = Self(rawValue: 0x7) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } diff --git a/stm32-lcd-logo/Sources/Application/Registers/RCC.swift b/stm32-lcd-logo/Sources/STM32F7X6/RCC.swift similarity index 55% rename from stm32-lcd-logo/Sources/Application/Registers/RCC.swift rename to stm32-lcd-logo/Sources/STM32F7X6/RCC.swift index 4f5842ef..4a36aea8 100644 --- a/stm32-lcd-logo/Sources/Application/Registers/RCC.swift +++ b/stm32-lcd-logo/Sources/STM32F7X6/RCC.swift @@ -4,2829 +4,2829 @@ import MMIO /// Reset and clock control @RegisterBlock -struct RCC { +public struct RCC { /// clock control register @RegisterBlock(offset: 0x0) - var cr: Register + public var cr: Register /// PLL configuration register @RegisterBlock(offset: 0x4) - var pllcfgr: Register + public var pllcfgr: Register /// clock configuration register @RegisterBlock(offset: 0x8) - var cfgr: Register + public var cfgr: Register /// clock interrupt register @RegisterBlock(offset: 0xc) - var cir: Register + public var cir: Register /// AHB1 peripheral reset register @RegisterBlock(offset: 0x10) - var ahb1rstr: Register + public var ahb1rstr: Register /// AHB2 peripheral reset register @RegisterBlock(offset: 0x14) - var ahb2rstr: Register + public var ahb2rstr: Register /// AHB3 peripheral reset register @RegisterBlock(offset: 0x18) - var ahb3rstr: Register + public var ahb3rstr: Register /// APB1 peripheral reset register @RegisterBlock(offset: 0x20) - var apb1rstr: Register + public var apb1rstr: Register /// APB2 peripheral reset register @RegisterBlock(offset: 0x24) - var apb2rstr: Register + public var apb2rstr: Register /// AHB1 peripheral clock register @RegisterBlock(offset: 0x30) - var ahb1enr: Register + public var ahb1enr: Register /// AHB2 peripheral clock enable register @RegisterBlock(offset: 0x34) - var ahb2enr: Register + public var ahb2enr: Register /// AHB3 peripheral clock enable register @RegisterBlock(offset: 0x38) - var ahb3enr: Register + public var ahb3enr: Register /// APB1 peripheral clock enable register @RegisterBlock(offset: 0x40) - var apb1enr: Register + public var apb1enr: Register /// APB2 peripheral clock enable register @RegisterBlock(offset: 0x44) - var apb2enr: Register + public var apb2enr: Register /// AHB1 peripheral clock enable in low power mode register @RegisterBlock(offset: 0x50) - var ahb1lpenr: Register + public var ahb1lpenr: Register /// AHB2 peripheral clock enable in low power mode register @RegisterBlock(offset: 0x54) - var ahb2lpenr: Register + public var ahb2lpenr: Register /// AHB3 peripheral clock enable in low power mode register @RegisterBlock(offset: 0x58) - var ahb3lpenr: Register + public var ahb3lpenr: Register /// APB1 peripheral clock enable in low power mode register @RegisterBlock(offset: 0x60) - var apb1lpenr: Register + public var apb1lpenr: Register /// APB2 peripheral clock enabled in low power mode register @RegisterBlock(offset: 0x64) - var apb2lpenr: Register + public var apb2lpenr: Register /// Backup domain control register @RegisterBlock(offset: 0x70) - var bdcr: Register + public var bdcr: Register /// clock control & status register @RegisterBlock(offset: 0x74) - var csr: Register + public var csr: Register /// spread spectrum clock generation register @RegisterBlock(offset: 0x80) - var sscgr: Register + public var sscgr: Register /// PLLI2S configuration register @RegisterBlock(offset: 0x84) - var plli2scfgr: Register + public var plli2scfgr: Register /// PLL configuration register @RegisterBlock(offset: 0x88) - var pllsaicfgr: Register + public var pllsaicfgr: Register /// dedicated clocks configuration register @RegisterBlock(offset: 0x8c) - var dckcfgr1: Register + public var dckcfgr1: Register /// dedicated clocks configuration register @RegisterBlock(offset: 0x90) - var dckcfgr2: Register + public var dckcfgr2: Register } extension RCC { /// clock control register @Register(bitWidth: 32) - struct CR { + public struct CR { /// PLLI2S clock ready flag @ReadOnly(bits: 27..<28) - var plli2srdy: PLLI2SRDY + public var plli2srdy: PLLI2SRDY /// PLLI2S enable @ReadWrite(bits: 26..<27) - var plli2son: PLLI2SON + public var plli2son: PLLI2SON /// Main PLL (PLL) clock ready flag @ReadOnly(bits: 25..<26) - var pllrdy: PLLRDY + public var pllrdy: PLLRDY /// Main PLL (PLL) enable @ReadWrite(bits: 24..<25) - var pllon: PLLON + public var pllon: PLLON /// Clock security system enable @ReadWrite(bits: 19..<20, as: CSSONValues.self) - var csson: CSSON + public var csson: CSSON /// HSE clock bypass @ReadWrite(bits: 18..<19, as: HSEBYPValues.self) - var hsebyp: HSEBYP + public var hsebyp: HSEBYP /// HSE clock ready flag @ReadOnly(bits: 17..<18) - var hserdy: HSERDY + public var hserdy: HSERDY /// HSE clock enable @ReadWrite(bits: 16..<17) - var hseon: HSEON + public var hseon: HSEON /// Internal high-speed clock calibration @ReadOnly(bits: 8..<16) - var hsical: HSICAL + public var hsical: HSICAL /// Internal high-speed clock trimming @ReadWrite(bits: 3..<8) - var hsitrim: HSITRIM + public var hsitrim: HSITRIM /// Internal high-speed clock ready flag @ReadOnly(bits: 1..<2) - var hsirdy: HSIRDY + public var hsirdy: HSIRDY /// Internal high-speed clock enable @ReadWrite(bits: 0..<1, as: HSIONValues.self) - var hsion: HSION + public var hsion: HSION /// PLLSAI clock ready flag @ReadOnly(bits: 29..<30) - var pllsairdy: PLLSAIRDY + public var pllsairdy: PLLSAIRDY /// PLLSAI enable @ReadWrite(bits: 28..<29) - var pllsaion: PLLSAION + public var pllsaion: PLLSAION } /// PLL configuration register @Register(bitWidth: 32) - struct PLLCFGR { + public struct PLLCFGR { /// Main PLL(PLL) and audio PLL (PLLI2S) entry clock source @ReadWrite(bits: 22..<23, as: PLLSRCValues.self) - var pllsrc: PLLSRC + public var pllsrc: PLLSRC /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock @ReadWrite(bits: 0..<6) - var pllm: PLLM + public var pllm: PLLM /// Main PLL (PLL) multiplication factor for VCO @ReadWrite(bits: 6..<15) - var plln: PLLN + public var plln: PLLN /// Main PLL (PLL) division factor for main system clock @ReadWrite(bits: 16..<18, as: PLLPValues.self) - var pllp: PLLP + public var pllp: PLLP /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks @ReadWrite(bits: 24..<28) - var pllq: PLLQ + public var pllq: PLLQ } /// clock configuration register @Register(bitWidth: 32) - struct CFGR { + public struct CFGR { /// Microcontroller clock output 2 @ReadWrite(bits: 30..<32, as: MCO2Values.self) - var mco2: MCO2 + public var mco2: MCO2 /// MCO2 prescaler @ReadWrite(bits: 27..<30) - var mco2pre: MCO2PRE + public var mco2pre: MCO2PRE /// MCO1 prescaler @ReadWrite(bits: 24..<27, as: MCO1PREValues.self) - var mco1pre: MCO1PRE + public var mco1pre: MCO1PRE /// I2S clock selection @ReadWrite(bits: 23..<24, as: I2SSRCValues.self) - var i2ssrc: I2SSRC + public var i2ssrc: I2SSRC /// Microcontroller clock output 1 @ReadWrite(bits: 21..<23, as: MCO1Values.self) - var mco1: MCO1 + public var mco1: MCO1 /// HSE division factor for RTC clock @ReadWrite(bits: 16..<21) - var rtcpre: RTCPRE + public var rtcpre: RTCPRE /// APB high-speed prescaler (APB2) @ReadWrite(bits: 13..<16) - var ppre2: PPRE2 + public var ppre2: PPRE2 /// APB Low speed prescaler (APB1) @ReadWrite(bits: 10..<13, as: PPRE1Values.self) - var ppre1: PPRE1 + public var ppre1: PPRE1 /// AHB prescaler @ReadWrite(bits: 4..<8, as: HPREValues.self) - var hpre: HPRE + public var hpre: HPRE /// System clock switch @Reserved(bits: 0..<2, as: SWValues.self) - var sw: SW + public var sw: SW /// System clock switch status @Reserved(bits: 2..<4) - var sws: SWS + public var sws: SWS } /// clock interrupt register @Register(bitWidth: 32) - struct CIR { + public struct CIR { /// Clock security system interrupt clear @WriteOnly(bits: 23..<24) - var cssc: CSSC + public var cssc: CSSC /// PLLSAI Ready Interrupt Clear @WriteOnly(bits: 22..<23) - var pllsairdyc: PLLSAIRDYC + public var pllsairdyc: PLLSAIRDYC /// PLLI2S ready interrupt clear @WriteOnly(bits: 21..<22) - var plli2srdyc: PLLI2SRDYC + public var plli2srdyc: PLLI2SRDYC /// Main PLL(PLL) ready interrupt clear @WriteOnly(bits: 20..<21) - var pllrdyc: PLLRDYC + public var pllrdyc: PLLRDYC /// HSE ready interrupt clear @WriteOnly(bits: 19..<20) - var hserdyc: HSERDYC + public var hserdyc: HSERDYC /// HSI ready interrupt clear @WriteOnly(bits: 18..<19) - var hsirdyc: HSIRDYC + public var hsirdyc: HSIRDYC /// LSE ready interrupt clear @WriteOnly(bits: 17..<18) - var lserdyc: LSERDYC + public var lserdyc: LSERDYC /// LSI ready interrupt clear @WriteOnly(bits: 16..<17) - var lsirdyc: LSIRDYC + public var lsirdyc: LSIRDYC /// PLLSAI Ready Interrupt Enable @ReadWrite(bits: 14..<15) - var pllsairdyie: PLLSAIRDYIE + public var pllsairdyie: PLLSAIRDYIE /// PLLI2S ready interrupt enable @ReadWrite(bits: 13..<14) - var plli2srdyie: PLLI2SRDYIE + public var plli2srdyie: PLLI2SRDYIE /// Main PLL (PLL) ready interrupt enable @ReadWrite(bits: 12..<13) - var pllrdyie: PLLRDYIE + public var pllrdyie: PLLRDYIE /// HSE ready interrupt enable @ReadWrite(bits: 11..<12) - var hserdyie: HSERDYIE + public var hserdyie: HSERDYIE /// HSI ready interrupt enable @ReadWrite(bits: 10..<11) - var hsirdyie: HSIRDYIE + public var hsirdyie: HSIRDYIE /// LSE ready interrupt enable @ReadWrite(bits: 9..<10) - var lserdyie: LSERDYIE + public var lserdyie: LSERDYIE /// LSI ready interrupt enable @ReadWrite(bits: 8..<9, as: LSIRDYIEValues.self) - var lsirdyie: LSIRDYIE + public var lsirdyie: LSIRDYIE /// Clock security system interrupt flag @ReadOnly(bits: 7..<8) - var cssf: CSSF + public var cssf: CSSF /// PLLSAI ready interrupt flag @ReadOnly(bits: 6..<7) - var pllsairdyf: PLLSAIRDYF + public var pllsairdyf: PLLSAIRDYF /// PLLI2S ready interrupt flag @ReadOnly(bits: 5..<6) - var plli2srdyf: PLLI2SRDYF + public var plli2srdyf: PLLI2SRDYF /// Main PLL (PLL) ready interrupt flag @ReadOnly(bits: 4..<5) - var pllrdyf: PLLRDYF + public var pllrdyf: PLLRDYF /// HSE ready interrupt flag @ReadOnly(bits: 3..<4) - var hserdyf: HSERDYF + public var hserdyf: HSERDYF /// HSI ready interrupt flag @ReadOnly(bits: 2..<3) - var hsirdyf: HSIRDYF + public var hsirdyf: HSIRDYF /// LSE ready interrupt flag @ReadOnly(bits: 1..<2) - var lserdyf: LSERDYF + public var lserdyf: LSERDYF /// LSI ready interrupt flag @ReadOnly(bits: 0..<1) - var lsirdyf: LSIRDYF + public var lsirdyf: LSIRDYF } /// AHB1 peripheral reset register @Register(bitWidth: 32) - struct AHB1RSTR { + public struct AHB1RSTR { /// USB OTG HS module reset @ReadWrite(bits: 29..<30) - var otghsrst: OTGHSRST + public var otghsrst: OTGHSRST /// Ethernet MAC reset @ReadWrite(bits: 25..<26) - var ethmacrst: ETHMACRST + public var ethmacrst: ETHMACRST /// DMA2D reset @ReadWrite(bits: 23..<24) - var dma2drst: DMA2DRST + public var dma2drst: DMA2DRST /// DMA2 reset @ReadWrite(bits: 22..<23) - var dma2rst: DMA2RST + public var dma2rst: DMA2RST /// DMA2 reset @ReadWrite(bits: 21..<22) - var dma1rst: DMA1RST + public var dma1rst: DMA1RST /// CRC reset @ReadWrite(bits: 12..<13) - var crcrst: CRCRST + public var crcrst: CRCRST /// IO port K reset @ReadWrite(bits: 10..<11) - var gpiokrst: GPIOKRST + public var gpiokrst: GPIOKRST /// IO port J reset @ReadWrite(bits: 9..<10) - var gpiojrst: GPIOJRST + public var gpiojrst: GPIOJRST /// IO port I reset @ReadWrite(bits: 8..<9) - var gpioirst: GPIOIRST + public var gpioirst: GPIOIRST /// IO port H reset @ReadWrite(bits: 7..<8) - var gpiohrst: GPIOHRST + public var gpiohrst: GPIOHRST /// IO port G reset @ReadWrite(bits: 6..<7) - var gpiogrst: GPIOGRST + public var gpiogrst: GPIOGRST /// IO port F reset @ReadWrite(bits: 5..<6) - var gpiofrst: GPIOFRST + public var gpiofrst: GPIOFRST /// IO port E reset @ReadWrite(bits: 4..<5) - var gpioerst: GPIOERST + public var gpioerst: GPIOERST /// IO port D reset @ReadWrite(bits: 3..<4) - var gpiodrst: GPIODRST + public var gpiodrst: GPIODRST /// IO port C reset @ReadWrite(bits: 2..<3) - var gpiocrst: GPIOCRST + public var gpiocrst: GPIOCRST /// IO port B reset @ReadWrite(bits: 1..<2) - var gpiobrst: GPIOBRST + public var gpiobrst: GPIOBRST /// IO port A reset @ReadWrite(bits: 0..<1, as: GPIOARSTValues.self) - var gpioarst: GPIOARST + public var gpioarst: GPIOARST } /// AHB2 peripheral reset register @Register(bitWidth: 32) - struct AHB2RSTR { + public struct AHB2RSTR { /// USB OTG FS module reset @ReadWrite(bits: 7..<8) - var otgfsrst: OTGFSRST + public var otgfsrst: OTGFSRST /// Random number generator module reset @ReadWrite(bits: 6..<7) - var rngrst: RNGRST + public var rngrst: RNGRST /// Hash module reset @ReadWrite(bits: 5..<6) - var hsahrst: HSAHRST + public var hsahrst: HSAHRST /// Cryptographic module reset @ReadWrite(bits: 4..<5) - var cryprst: CRYPRST + public var cryprst: CRYPRST /// Camera interface reset @ReadWrite(bits: 0..<1, as: DCMIRSTValues.self) - var dcmirst: DCMIRST + public var dcmirst: DCMIRST } /// AHB3 peripheral reset register @Register(bitWidth: 32) - struct AHB3RSTR { + public struct AHB3RSTR { /// Flexible memory controller module reset @ReadWrite(bits: 0..<1, as: FMCRSTValues.self) - var fmcrst: FMCRST + public var fmcrst: FMCRST /// Quad SPI memory controller reset @ReadWrite(bits: 1..<2) - var qspirst: QSPIRST + public var qspirst: QSPIRST } /// APB1 peripheral reset register @Register(bitWidth: 32) - struct APB1RSTR { + public struct APB1RSTR { /// TIM2 reset @ReadWrite(bits: 0..<1, as: TIM2RSTValues.self) - var tim2rst: TIM2RST + public var tim2rst: TIM2RST /// TIM3 reset @ReadWrite(bits: 1..<2) - var tim3rst: TIM3RST + public var tim3rst: TIM3RST /// TIM4 reset @ReadWrite(bits: 2..<3) - var tim4rst: TIM4RST + public var tim4rst: TIM4RST /// TIM5 reset @ReadWrite(bits: 3..<4) - var tim5rst: TIM5RST + public var tim5rst: TIM5RST /// TIM6 reset @ReadWrite(bits: 4..<5) - var tim6rst: TIM6RST + public var tim6rst: TIM6RST /// TIM7 reset @ReadWrite(bits: 5..<6) - var tim7rst: TIM7RST + public var tim7rst: TIM7RST /// TIM12 reset @ReadWrite(bits: 6..<7) - var tim12rst: TIM12RST + public var tim12rst: TIM12RST /// TIM13 reset @ReadWrite(bits: 7..<8) - var tim13rst: TIM13RST + public var tim13rst: TIM13RST /// TIM14 reset @ReadWrite(bits: 8..<9) - var tim14rst: TIM14RST + public var tim14rst: TIM14RST /// Window watchdog reset @ReadWrite(bits: 11..<12) - var wwdgrst: WWDGRST + public var wwdgrst: WWDGRST /// SPI 2 reset @ReadWrite(bits: 14..<15) - var spi2rst: SPI2RST + public var spi2rst: SPI2RST /// SPI 3 reset @ReadWrite(bits: 15..<16) - var spi3rst: SPI3RST + public var spi3rst: SPI3RST /// USART 2 reset @ReadWrite(bits: 17..<18) - var usart2rst: USART2RST + public var usart2rst: USART2RST /// USART 3 reset @ReadWrite(bits: 18..<19) - var usart3rst: USART3RST + public var usart3rst: USART3RST /// USART 4 reset @ReadWrite(bits: 19..<20) - var uart4rst: UART4RST + public var uart4rst: UART4RST /// USART 5 reset @ReadWrite(bits: 20..<21) - var uart5rst: UART5RST + public var uart5rst: UART5RST /// I2C 1 reset @ReadWrite(bits: 21..<22) - var i2c1rst: I2C1RST + public var i2c1rst: I2C1RST /// I2C 2 reset @ReadWrite(bits: 22..<23) - var i2c2rst: I2C2RST + public var i2c2rst: I2C2RST /// I2C3 reset @ReadWrite(bits: 23..<24) - var i2c3rst: I2C3RST + public var i2c3rst: I2C3RST /// CAN1 reset @ReadWrite(bits: 25..<26) - var can1rst: CAN1RST + public var can1rst: CAN1RST /// CAN2 reset @ReadWrite(bits: 26..<27) - var can2rst: CAN2RST + public var can2rst: CAN2RST /// Power interface reset @ReadWrite(bits: 28..<29) - var pwrrst: PWRRST + public var pwrrst: PWRRST /// DAC reset @ReadWrite(bits: 29..<30) - var dacrst: DACRST + public var dacrst: DACRST /// UART7 reset @ReadWrite(bits: 30..<31) - var uart7rst: UART7RST + public var uart7rst: UART7RST /// UART8 reset @ReadWrite(bits: 31..<32) - var uart8rst: UART8RST + public var uart8rst: UART8RST /// SPDIF-RX reset @ReadWrite(bits: 16..<17) - var spdifrxrst: SPDIFRXRST + public var spdifrxrst: SPDIFRXRST /// HDMI-CEC reset @ReadWrite(bits: 27..<28) - var cecrst: CECRST + public var cecrst: CECRST /// Low power timer 1 reset @ReadWrite(bits: 9..<10) - var lptim1rst: LPTIM1RST + public var lptim1rst: LPTIM1RST /// I2C 4 reset @ReadWrite(bits: 24..<25) - var i2c4rst: I2C4RST + public var i2c4rst: I2C4RST } /// APB2 peripheral reset register @Register(bitWidth: 32) - struct APB2RSTR { + public struct APB2RSTR { /// TIM1 reset @ReadWrite(bits: 0..<1, as: TIM1RSTValues.self) - var tim1rst: TIM1RST + public var tim1rst: TIM1RST /// TIM8 reset @ReadWrite(bits: 1..<2) - var tim8rst: TIM8RST + public var tim8rst: TIM8RST /// USART1 reset @ReadWrite(bits: 4..<5) - var usart1rst: USART1RST + public var usart1rst: USART1RST /// USART6 reset @ReadWrite(bits: 5..<6) - var usart6rst: USART6RST + public var usart6rst: USART6RST /// ADC interface reset (common to all ADCs) @ReadWrite(bits: 8..<9) - var adcrst: ADCRST + public var adcrst: ADCRST /// SPI 1 reset @ReadWrite(bits: 12..<13) - var spi1rst: SPI1RST + public var spi1rst: SPI1RST /// SPI4 reset @ReadWrite(bits: 13..<14) - var spi4rst: SPI4RST + public var spi4rst: SPI4RST /// System configuration controller reset @ReadWrite(bits: 14..<15) - var syscfgrst: SYSCFGRST + public var syscfgrst: SYSCFGRST /// TIM9 reset @ReadWrite(bits: 16..<17) - var tim9rst: TIM9RST + public var tim9rst: TIM9RST /// TIM10 reset @ReadWrite(bits: 17..<18) - var tim10rst: TIM10RST + public var tim10rst: TIM10RST /// TIM11 reset @ReadWrite(bits: 18..<19) - var tim11rst: TIM11RST + public var tim11rst: TIM11RST /// SPI5 reset @ReadWrite(bits: 20..<21) - var spi5rst: SPI5RST + public var spi5rst: SPI5RST /// SPI6 reset @ReadWrite(bits: 21..<22) - var spi6rst: SPI6RST + public var spi6rst: SPI6RST /// SAI1 reset @ReadWrite(bits: 22..<23) - var sai1rst: SAI1RST + public var sai1rst: SAI1RST /// LTDC reset @ReadWrite(bits: 26..<27) - var ltdcrst: LTDCRST + public var ltdcrst: LTDCRST /// SAI2 reset @ReadWrite(bits: 23..<24) - var sai2rst: SAI2RST + public var sai2rst: SAI2RST /// SDMMC1 reset @ReadWrite(bits: 11..<12) - var sdmmc1rst: SDMMC1RST + public var sdmmc1rst: SDMMC1RST } /// AHB1 peripheral clock register @Register(bitWidth: 32) - struct AHB1ENR { + public struct AHB1ENR { /// USB OTG HSULPI clock enable @ReadWrite(bits: 30..<31) - var otghsulpien: OTGHSULPIEN + public var otghsulpien: OTGHSULPIEN /// USB OTG HS clock enable @ReadWrite(bits: 29..<30) - var otghsen: OTGHSEN + public var otghsen: OTGHSEN /// Ethernet PTP clock enable @ReadWrite(bits: 28..<29) - var ethmacptpen: ETHMACPTPEN + public var ethmacptpen: ETHMACPTPEN /// Ethernet Reception clock enable @ReadWrite(bits: 27..<28) - var ethmacrxen: ETHMACRXEN + public var ethmacrxen: ETHMACRXEN /// Ethernet Transmission clock enable @ReadWrite(bits: 26..<27) - var ethmactxen: ETHMACTXEN + public var ethmactxen: ETHMACTXEN /// Ethernet MAC clock enable @ReadWrite(bits: 25..<26) - var ethmacen: ETHMACEN + public var ethmacen: ETHMACEN /// DMA2D clock enable @ReadWrite(bits: 23..<24) - var dma2den: DMA2DEN + public var dma2den: DMA2DEN /// DMA2 clock enable @ReadWrite(bits: 22..<23) - var dma2en: DMA2EN + public var dma2en: DMA2EN /// DMA1 clock enable @ReadWrite(bits: 21..<22) - var dma1en: DMA1EN + public var dma1en: DMA1EN /// CCM data RAM clock enable @ReadWrite(bits: 20..<21) - var dtcmramen: DTCMRAMEN + public var dtcmramen: DTCMRAMEN /// Backup SRAM interface clock enable @ReadWrite(bits: 18..<19) - var bkpsramen: BKPSRAMEN + public var bkpsramen: BKPSRAMEN /// CRC clock enable @ReadWrite(bits: 12..<13) - var crcen: CRCEN + public var crcen: CRCEN /// IO port K clock enable @ReadWrite(bits: 10..<11) - var gpioken: GPIOKEN + public var gpioken: GPIOKEN /// IO port J clock enable @ReadWrite(bits: 9..<10) - var gpiojen: GPIOJEN + public var gpiojen: GPIOJEN /// IO port I clock enable @ReadWrite(bits: 8..<9) - var gpioien: GPIOIEN + public var gpioien: GPIOIEN /// IO port H clock enable @ReadWrite(bits: 7..<8) - var gpiohen: GPIOHEN + public var gpiohen: GPIOHEN /// IO port G clock enable @ReadWrite(bits: 6..<7) - var gpiogen: GPIOGEN + public var gpiogen: GPIOGEN /// IO port F clock enable @ReadWrite(bits: 5..<6) - var gpiofen: GPIOFEN + public var gpiofen: GPIOFEN /// IO port E clock enable @ReadWrite(bits: 4..<5) - var gpioeen: GPIOEEN + public var gpioeen: GPIOEEN /// IO port D clock enable @ReadWrite(bits: 3..<4) - var gpioden: GPIODEN + public var gpioden: GPIODEN /// IO port C clock enable @ReadWrite(bits: 2..<3) - var gpiocen: GPIOCEN + public var gpiocen: GPIOCEN /// IO port B clock enable @ReadWrite(bits: 1..<2) - var gpioben: GPIOBEN + public var gpioben: GPIOBEN /// IO port A clock enable @ReadWrite(bits: 0..<1, as: GPIOAENValues.self) - var gpioaen: GPIOAEN + public var gpioaen: GPIOAEN } /// AHB2 peripheral clock enable register @Register(bitWidth: 32) - struct AHB2ENR { + public struct AHB2ENR { /// USB OTG FS clock enable @ReadWrite(bits: 7..<8) - var otgfsen: OTGFSEN + public var otgfsen: OTGFSEN /// Random number generator clock enable @ReadWrite(bits: 6..<7) - var rngen: RNGEN + public var rngen: RNGEN /// Hash modules clock enable @ReadWrite(bits: 5..<6) - var hashen: HASHEN + public var hashen: HASHEN /// Cryptographic modules clock enable @ReadWrite(bits: 4..<5) - var crypen: CRYPEN + public var crypen: CRYPEN /// Camera interface enable @ReadWrite(bits: 0..<1, as: DCMIENValues.self) - var dcmien: DCMIEN + public var dcmien: DCMIEN } /// AHB3 peripheral clock enable register @Register(bitWidth: 32) - struct AHB3ENR { + public struct AHB3ENR { /// Flexible memory controller module clock enable @ReadWrite(bits: 0..<1, as: FMCENValues.self) - var fmcen: FMCEN + public var fmcen: FMCEN /// Quad SPI memory controller clock enable @ReadWrite(bits: 1..<2) - var qspien: QSPIEN + public var qspien: QSPIEN } /// APB1 peripheral clock enable register @Register(bitWidth: 32) - struct APB1ENR { + public struct APB1ENR { /// TIM2 clock enable @ReadWrite(bits: 0..<1, as: TIM2ENValues.self) - var tim2en: TIM2EN + public var tim2en: TIM2EN /// TIM3 clock enable @ReadWrite(bits: 1..<2) - var tim3en: TIM3EN + public var tim3en: TIM3EN /// TIM4 clock enable @ReadWrite(bits: 2..<3) - var tim4en: TIM4EN + public var tim4en: TIM4EN /// TIM5 clock enable @ReadWrite(bits: 3..<4) - var tim5en: TIM5EN + public var tim5en: TIM5EN /// TIM6 clock enable @ReadWrite(bits: 4..<5) - var tim6en: TIM6EN + public var tim6en: TIM6EN /// TIM7 clock enable @ReadWrite(bits: 5..<6) - var tim7en: TIM7EN + public var tim7en: TIM7EN /// TIM12 clock enable @ReadWrite(bits: 6..<7) - var tim12en: TIM12EN + public var tim12en: TIM12EN /// TIM13 clock enable @ReadWrite(bits: 7..<8) - var tim13en: TIM13EN + public var tim13en: TIM13EN /// TIM14 clock enable @ReadWrite(bits: 8..<9) - var tim14en: TIM14EN + public var tim14en: TIM14EN /// Window watchdog clock enable @ReadWrite(bits: 11..<12) - var wwdgen: WWDGEN + public var wwdgen: WWDGEN /// SPI2 clock enable @ReadWrite(bits: 14..<15) - var spi2en: SPI2EN + public var spi2en: SPI2EN /// SPI3 clock enable @ReadWrite(bits: 15..<16) - var spi3en: SPI3EN + public var spi3en: SPI3EN /// USART 2 clock enable @ReadWrite(bits: 17..<18) - var usart2en: USART2EN + public var usart2en: USART2EN /// USART3 clock enable @ReadWrite(bits: 18..<19) - var usart3en: USART3EN + public var usart3en: USART3EN /// UART4 clock enable @ReadWrite(bits: 19..<20) - var uart4en: UART4EN + public var uart4en: UART4EN /// UART5 clock enable @ReadWrite(bits: 20..<21) - var uart5en: UART5EN + public var uart5en: UART5EN /// I2C1 clock enable @ReadWrite(bits: 21..<22) - var i2c1en: I2C1EN + public var i2c1en: I2C1EN /// I2C2 clock enable @ReadWrite(bits: 22..<23) - var i2c2en: I2C2EN + public var i2c2en: I2C2EN /// I2C3 clock enable @ReadWrite(bits: 23..<24) - var i2c3en: I2C3EN + public var i2c3en: I2C3EN /// CAN 1 clock enable @ReadWrite(bits: 25..<26) - var can1en: CAN1EN + public var can1en: CAN1EN /// CAN 2 clock enable @ReadWrite(bits: 26..<27) - var can2en: CAN2EN + public var can2en: CAN2EN /// Power interface clock enable @ReadWrite(bits: 28..<29) - var pwren: PWREN + public var pwren: PWREN /// DAC interface clock enable @ReadWrite(bits: 29..<30) - var dacen: DACEN + public var dacen: DACEN /// UART7 clock enable @ReadWrite(bits: 30..<31) - var uart7en: UART7EN + public var uart7en: UART7EN /// UART8 clock enable @ReadWrite(bits: 31..<32) - var uart8en: UART8EN + public var uart8en: UART8EN /// SPDIF-RX clock enable @ReadWrite(bits: 16..<17) - var spdifrxen: SPDIFRXEN + public var spdifrxen: SPDIFRXEN /// HDMI-CEN clock enable @ReadWrite(bits: 27..<28) - var cecen: CECEN + public var cecen: CECEN /// Low power timer 1 clock enable @ReadWrite(bits: 9..<10) - var lptim1en: LPTIM1EN + public var lptim1en: LPTIM1EN /// I2C4 clock enable @ReadWrite(bits: 24..<25) - var i2c4en: I2C4EN + public var i2c4en: I2C4EN } /// APB2 peripheral clock enable register @Register(bitWidth: 32) - struct APB2ENR { + public struct APB2ENR { /// TIM1 clock enable @ReadWrite(bits: 0..<1, as: TIM1ENValues.self) - var tim1en: TIM1EN + public var tim1en: TIM1EN /// TIM8 clock enable @ReadWrite(bits: 1..<2) - var tim8en: TIM8EN + public var tim8en: TIM8EN /// USART1 clock enable @ReadWrite(bits: 4..<5) - var usart1en: USART1EN + public var usart1en: USART1EN /// USART6 clock enable @ReadWrite(bits: 5..<6) - var usart6en: USART6EN + public var usart6en: USART6EN /// ADC1 clock enable @ReadWrite(bits: 8..<9) - var adc1en: ADC1EN + public var adc1en: ADC1EN /// ADC2 clock enable @ReadWrite(bits: 9..<10) - var adc2en: ADC2EN + public var adc2en: ADC2EN /// ADC3 clock enable @ReadWrite(bits: 10..<11) - var adc3en: ADC3EN + public var adc3en: ADC3EN /// SPI1 clock enable @ReadWrite(bits: 12..<13) - var spi1en: SPI1EN + public var spi1en: SPI1EN /// SPI4 clock enable @ReadWrite(bits: 13..<14) - var spi4en: SPI4EN + public var spi4en: SPI4EN /// System configuration controller clock enable @ReadWrite(bits: 14..<15) - var syscfgen: SYSCFGEN + public var syscfgen: SYSCFGEN /// TIM9 clock enable @ReadWrite(bits: 16..<17) - var tim9en: TIM9EN + public var tim9en: TIM9EN /// TIM10 clock enable @ReadWrite(bits: 17..<18) - var tim10en: TIM10EN + public var tim10en: TIM10EN /// TIM11 clock enable @ReadWrite(bits: 18..<19) - var tim11en: TIM11EN + public var tim11en: TIM11EN /// SPI5 clock enable @ReadWrite(bits: 20..<21) - var spi5en: SPI5EN + public var spi5en: SPI5EN /// SPI6 clock enable @ReadWrite(bits: 21..<22) - var spi6en: SPI6EN + public var spi6en: SPI6EN /// SAI1 clock enable @ReadWrite(bits: 22..<23) - var sai1en: SAI1EN + public var sai1en: SAI1EN /// LTDC clock enable @ReadWrite(bits: 26..<27) - var ltdcen: LTDCEN + public var ltdcen: LTDCEN /// SAI2 clock enable @ReadWrite(bits: 23..<24) - var sai2en: SAI2EN + public var sai2en: SAI2EN /// SDMMC1 clock enable @ReadWrite(bits: 11..<12) - var sdmmc1en: SDMMC1EN + public var sdmmc1en: SDMMC1EN } /// AHB1 peripheral clock enable in low power mode register @Register(bitWidth: 32) - struct AHB1LPENR { + public struct AHB1LPENR { /// IO port A clock enable during sleep mode @ReadWrite(bits: 0..<1, as: GPIOALPENValues.self) - var gpioalpen: GPIOALPEN + public var gpioalpen: GPIOALPEN /// IO port B clock enable during Sleep mode @ReadWrite(bits: 1..<2) - var gpioblpen: GPIOBLPEN + public var gpioblpen: GPIOBLPEN /// IO port C clock enable during Sleep mode @ReadWrite(bits: 2..<3) - var gpioclpen: GPIOCLPEN + public var gpioclpen: GPIOCLPEN /// IO port D clock enable during Sleep mode @ReadWrite(bits: 3..<4) - var gpiodlpen: GPIODLPEN + public var gpiodlpen: GPIODLPEN /// IO port E clock enable during Sleep mode @ReadWrite(bits: 4..<5) - var gpioelpen: GPIOELPEN + public var gpioelpen: GPIOELPEN /// IO port F clock enable during Sleep mode @ReadWrite(bits: 5..<6) - var gpioflpen: GPIOFLPEN + public var gpioflpen: GPIOFLPEN /// IO port G clock enable during Sleep mode @ReadWrite(bits: 6..<7) - var gpioglpen: GPIOGLPEN + public var gpioglpen: GPIOGLPEN /// IO port H clock enable during Sleep mode @ReadWrite(bits: 7..<8) - var gpiohlpen: GPIOHLPEN + public var gpiohlpen: GPIOHLPEN /// IO port I clock enable during Sleep mode @ReadWrite(bits: 8..<9) - var gpioilpen: GPIOILPEN + public var gpioilpen: GPIOILPEN /// IO port J clock enable during Sleep mode @ReadWrite(bits: 9..<10) - var gpiojlpen: GPIOJLPEN + public var gpiojlpen: GPIOJLPEN /// IO port K clock enable during Sleep mode @ReadWrite(bits: 10..<11) - var gpioklpen: GPIOKLPEN + public var gpioklpen: GPIOKLPEN /// CRC clock enable during Sleep mode @ReadWrite(bits: 12..<13) - var crclpen: CRCLPEN + public var crclpen: CRCLPEN /// Flash interface clock enable during Sleep mode @ReadWrite(bits: 15..<16) - var flitflpen: FLITFLPEN + public var flitflpen: FLITFLPEN /// SRAM 1interface clock enable during Sleep mode @ReadWrite(bits: 16..<17) - var sram1lpen: SRAM1LPEN + public var sram1lpen: SRAM1LPEN /// SRAM 2 interface clock enable during Sleep mode @ReadWrite(bits: 17..<18) - var sram2lpen: SRAM2LPEN + public var sram2lpen: SRAM2LPEN /// Backup SRAM interface clock enable during Sleep mode @ReadWrite(bits: 18..<19) - var bkpsramlpen: BKPSRAMLPEN + public var bkpsramlpen: BKPSRAMLPEN /// SRAM 3 interface clock enable during Sleep mode @ReadWrite(bits: 19..<20) - var sram3lpen: SRAM3LPEN + public var sram3lpen: SRAM3LPEN /// DMA1 clock enable during Sleep mode @ReadWrite(bits: 21..<22) - var dma1lpen: DMA1LPEN + public var dma1lpen: DMA1LPEN /// DMA2 clock enable during Sleep mode @ReadWrite(bits: 22..<23) - var dma2lpen: DMA2LPEN + public var dma2lpen: DMA2LPEN /// DMA2D clock enable during Sleep mode @ReadWrite(bits: 23..<24) - var dma2dlpen: DMA2DLPEN + public var dma2dlpen: DMA2DLPEN /// Ethernet MAC clock enable during Sleep mode @ReadWrite(bits: 25..<26) - var ethmaclpen: ETHMACLPEN + public var ethmaclpen: ETHMACLPEN /// Ethernet transmission clock enable during Sleep mode @ReadWrite(bits: 26..<27) - var ethmactxlpen: ETHMACTXLPEN + public var ethmactxlpen: ETHMACTXLPEN /// Ethernet reception clock enable during Sleep mode @ReadWrite(bits: 27..<28) - var ethmacrxlpen: ETHMACRXLPEN + public var ethmacrxlpen: ETHMACRXLPEN /// Ethernet PTP clock enable during Sleep mode @ReadWrite(bits: 28..<29) - var ethmacptplpen: ETHMACPTPLPEN + public var ethmacptplpen: ETHMACPTPLPEN /// USB OTG HS clock enable during Sleep mode @ReadWrite(bits: 29..<30) - var otghslpen: OTGHSLPEN + public var otghslpen: OTGHSLPEN /// USB OTG HS ULPI clock enable during Sleep mode @ReadWrite(bits: 30..<31) - var otghsulpilpen: OTGHSULPILPEN + public var otghsulpilpen: OTGHSULPILPEN /// AXI to AHB bridge clock enable during Sleep mode @ReadWrite(bits: 13..<14) - var axilpen: AXILPEN + public var axilpen: AXILPEN /// DTCM RAM interface clock enable during Sleep mode @ReadWrite(bits: 20..<21) - var dtcmlpen: DTCMLPEN + public var dtcmlpen: DTCMLPEN } /// AHB2 peripheral clock enable in low power mode register @Register(bitWidth: 32) - struct AHB2LPENR { + public struct AHB2LPENR { /// USB OTG FS clock enable during Sleep mode @ReadWrite(bits: 7..<8) - var otgfslpen: OTGFSLPEN + public var otgfslpen: OTGFSLPEN /// Random number generator clock enable during Sleep mode @ReadWrite(bits: 6..<7) - var rnglpen: RNGLPEN + public var rnglpen: RNGLPEN /// Hash modules clock enable during Sleep mode @ReadWrite(bits: 5..<6) - var hashlpen: HASHLPEN + public var hashlpen: HASHLPEN /// Cryptography modules clock enable during Sleep mode @ReadWrite(bits: 4..<5) - var cryplpen: CRYPLPEN + public var cryplpen: CRYPLPEN /// Camera interface enable during Sleep mode @ReadWrite(bits: 0..<1, as: DCMILPENValues.self) - var dcmilpen: DCMILPEN + public var dcmilpen: DCMILPEN } /// AHB3 peripheral clock enable in low power mode register @Register(bitWidth: 32) - struct AHB3LPENR { + public struct AHB3LPENR { /// Flexible memory controller module clock enable during Sleep mode @ReadWrite(bits: 0..<1, as: FMCLPENValues.self) - var fmclpen: FMCLPEN + public var fmclpen: FMCLPEN /// Quand SPI memory controller clock enable during Sleep mode @ReadWrite(bits: 1..<2) - var qspilpen: QSPILPEN + public var qspilpen: QSPILPEN } /// APB1 peripheral clock enable in low power mode register @Register(bitWidth: 32) - struct APB1LPENR { + public struct APB1LPENR { /// TIM2 clock enable during Sleep mode @ReadWrite(bits: 0..<1, as: TIM2LPENValues.self) - var tim2lpen: TIM2LPEN + public var tim2lpen: TIM2LPEN /// TIM3 clock enable during Sleep mode @ReadWrite(bits: 1..<2) - var tim3lpen: TIM3LPEN + public var tim3lpen: TIM3LPEN /// TIM4 clock enable during Sleep mode @ReadWrite(bits: 2..<3) - var tim4lpen: TIM4LPEN + public var tim4lpen: TIM4LPEN /// TIM5 clock enable during Sleep mode @ReadWrite(bits: 3..<4) - var tim5lpen: TIM5LPEN + public var tim5lpen: TIM5LPEN /// TIM6 clock enable during Sleep mode @ReadWrite(bits: 4..<5) - var tim6lpen: TIM6LPEN + public var tim6lpen: TIM6LPEN /// TIM7 clock enable during Sleep mode @ReadWrite(bits: 5..<6) - var tim7lpen: TIM7LPEN + public var tim7lpen: TIM7LPEN /// TIM12 clock enable during Sleep mode @ReadWrite(bits: 6..<7) - var tim12lpen: TIM12LPEN + public var tim12lpen: TIM12LPEN /// TIM13 clock enable during Sleep mode @ReadWrite(bits: 7..<8) - var tim13lpen: TIM13LPEN + public var tim13lpen: TIM13LPEN /// TIM14 clock enable during Sleep mode @ReadWrite(bits: 8..<9) - var tim14lpen: TIM14LPEN + public var tim14lpen: TIM14LPEN /// Window watchdog clock enable during Sleep mode @ReadWrite(bits: 11..<12) - var wwdglpen: WWDGLPEN + public var wwdglpen: WWDGLPEN /// SPI2 clock enable during Sleep mode @ReadWrite(bits: 14..<15) - var spi2lpen: SPI2LPEN + public var spi2lpen: SPI2LPEN /// SPI3 clock enable during Sleep mode @ReadWrite(bits: 15..<16) - var spi3lpen: SPI3LPEN + public var spi3lpen: SPI3LPEN /// USART2 clock enable during Sleep mode @ReadWrite(bits: 17..<18) - var usart2lpen: USART2LPEN + public var usart2lpen: USART2LPEN /// USART3 clock enable during Sleep mode @ReadWrite(bits: 18..<19) - var usart3lpen: USART3LPEN + public var usart3lpen: USART3LPEN /// UART4 clock enable during Sleep mode @ReadWrite(bits: 19..<20) - var uart4lpen: UART4LPEN + public var uart4lpen: UART4LPEN /// UART5 clock enable during Sleep mode @ReadWrite(bits: 20..<21) - var uart5lpen: UART5LPEN + public var uart5lpen: UART5LPEN /// I2C1 clock enable during Sleep mode @ReadWrite(bits: 21..<22) - var i2c1lpen: I2C1LPEN + public var i2c1lpen: I2C1LPEN /// I2C2 clock enable during Sleep mode @ReadWrite(bits: 22..<23) - var i2c2lpen: I2C2LPEN + public var i2c2lpen: I2C2LPEN /// I2C3 clock enable during Sleep mode @ReadWrite(bits: 23..<24) - var i2c3lpen: I2C3LPEN + public var i2c3lpen: I2C3LPEN /// CAN 1 clock enable during Sleep mode @ReadWrite(bits: 25..<26) - var can1lpen: CAN1LPEN + public var can1lpen: CAN1LPEN /// CAN 2 clock enable during Sleep mode @ReadWrite(bits: 26..<27) - var can2lpen: CAN2LPEN + public var can2lpen: CAN2LPEN /// Power interface clock enable during Sleep mode @ReadWrite(bits: 28..<29) - var pwrlpen: PWRLPEN + public var pwrlpen: PWRLPEN /// DAC interface clock enable during Sleep mode @ReadWrite(bits: 29..<30) - var daclpen: DACLPEN + public var daclpen: DACLPEN /// UART7 clock enable during Sleep mode @ReadWrite(bits: 30..<31) - var uart7lpen: UART7LPEN + public var uart7lpen: UART7LPEN /// UART8 clock enable during Sleep mode @ReadWrite(bits: 31..<32) - var uart8lpen: UART8LPEN + public var uart8lpen: UART8LPEN /// SPDIF-RX clock enable during sleep mode @ReadWrite(bits: 16..<17) - var spdifrxlpen: SPDIFRXLPEN + public var spdifrxlpen: SPDIFRXLPEN /// HDMI-CEN clock enable during Sleep mode @ReadWrite(bits: 27..<28) - var ceclpen: CECLPEN + public var ceclpen: CECLPEN /// low power timer 1 clock enable during Sleep mode @ReadWrite(bits: 9..<10) - var lptim1lpen: LPTIM1LPEN + public var lptim1lpen: LPTIM1LPEN /// I2C4 clock enable during Sleep mode @ReadWrite(bits: 24..<25) - var i2c4lpen: I2C4LPEN + public var i2c4lpen: I2C4LPEN } /// APB2 peripheral clock enabled in low power mode register @Register(bitWidth: 32) - struct APB2LPENR { + public struct APB2LPENR { /// TIM1 clock enable during Sleep mode @ReadWrite(bits: 0..<1, as: TIM1LPENValues.self) - var tim1lpen: TIM1LPEN + public var tim1lpen: TIM1LPEN /// TIM8 clock enable during Sleep mode @ReadWrite(bits: 1..<2) - var tim8lpen: TIM8LPEN + public var tim8lpen: TIM8LPEN /// USART1 clock enable during Sleep mode @ReadWrite(bits: 4..<5) - var usart1lpen: USART1LPEN + public var usart1lpen: USART1LPEN /// USART6 clock enable during Sleep mode @ReadWrite(bits: 5..<6) - var usart6lpen: USART6LPEN + public var usart6lpen: USART6LPEN /// ADC1 clock enable during Sleep mode @ReadWrite(bits: 8..<9) - var adc1lpen: ADC1LPEN + public var adc1lpen: ADC1LPEN /// ADC2 clock enable during Sleep mode @ReadWrite(bits: 9..<10) - var adc2lpen: ADC2LPEN + public var adc2lpen: ADC2LPEN /// ADC 3 clock enable during Sleep mode @ReadWrite(bits: 10..<11) - var adc3lpen: ADC3LPEN + public var adc3lpen: ADC3LPEN /// SPI 1 clock enable during Sleep mode @ReadWrite(bits: 12..<13) - var spi1lpen: SPI1LPEN + public var spi1lpen: SPI1LPEN /// SPI 4 clock enable during Sleep mode @ReadWrite(bits: 13..<14) - var spi4lpen: SPI4LPEN + public var spi4lpen: SPI4LPEN /// System configuration controller clock enable during Sleep mode @ReadWrite(bits: 14..<15) - var syscfglpen: SYSCFGLPEN + public var syscfglpen: SYSCFGLPEN /// TIM9 clock enable during sleep mode @ReadWrite(bits: 16..<17) - var tim9lpen: TIM9LPEN + public var tim9lpen: TIM9LPEN /// TIM10 clock enable during Sleep mode @ReadWrite(bits: 17..<18) - var tim10lpen: TIM10LPEN + public var tim10lpen: TIM10LPEN /// TIM11 clock enable during Sleep mode @ReadWrite(bits: 18..<19) - var tim11lpen: TIM11LPEN + public var tim11lpen: TIM11LPEN /// SPI 5 clock enable during Sleep mode @ReadWrite(bits: 20..<21) - var spi5lpen: SPI5LPEN + public var spi5lpen: SPI5LPEN /// SPI 6 clock enable during Sleep mode @ReadWrite(bits: 21..<22) - var spi6lpen: SPI6LPEN + public var spi6lpen: SPI6LPEN /// SAI1 clock enable during sleep mode @ReadWrite(bits: 22..<23) - var sai1lpen: SAI1LPEN + public var sai1lpen: SAI1LPEN /// LTDC clock enable during sleep mode @ReadWrite(bits: 26..<27) - var ltdclpen: LTDCLPEN + public var ltdclpen: LTDCLPEN /// SAI2 clock enable during sleep mode @ReadWrite(bits: 23..<24) - var sai2lpen: SAI2LPEN + public var sai2lpen: SAI2LPEN /// SDMMC1 clock enable during Sleep mode @ReadWrite(bits: 11..<12) - var sdmmc1lpen: SDMMC1LPEN + public var sdmmc1lpen: SDMMC1LPEN } /// Backup domain control register @Register(bitWidth: 32) - struct BDCR { + public struct BDCR { /// Backup domain software reset @ReadWrite(bits: 16..<17, as: BDRSTValues.self) - var bdrst: BDRST + public var bdrst: BDRST /// RTC clock enable @ReadWrite(bits: 15..<16, as: RTCENValues.self) - var rtcen: RTCEN + public var rtcen: RTCEN /// External low-speed oscillator bypass @ReadWrite(bits: 2..<3, as: LSEBYPValues.self) - var lsebyp: LSEBYP + public var lsebyp: LSEBYP /// External low-speed oscillator ready @ReadOnly(bits: 1..<2) - var lserdy: LSERDY + public var lserdy: LSERDY /// External low-speed oscillator enable @ReadWrite(bits: 0..<1, as: LSEONValues.self) - var lseon: LSEON + public var lseon: LSEON /// LSE oscillator drive capability @ReadWrite(bits: 3..<5, as: LSEDRVValues.self) - var lsedrv: LSEDRV + public var lsedrv: LSEDRV /// RTC clock source selection @Reserved(bits: 8..<10, as: RTCSELValues.self) - var rtcsel: RTCSEL + public var rtcsel: RTCSEL } /// clock control & status register @Register(bitWidth: 32) - struct CSR { + public struct CSR { /// Low-power reset flag @ReadWrite(bits: 31..<32) - var lpwrrstf: LPWRRSTF + public var lpwrrstf: LPWRRSTF /// Window watchdog reset flag @ReadWrite(bits: 30..<31) - var wwdgrstf: WWDGRSTF + public var wwdgrstf: WWDGRSTF /// Independent watchdog reset flag @ReadWrite(bits: 29..<30) - var wdgrstf: WDGRSTF + public var wdgrstf: WDGRSTF /// Software reset flag @ReadWrite(bits: 28..<29) - var sftrstf: SFTRSTF + public var sftrstf: SFTRSTF /// POR/PDR reset flag @ReadWrite(bits: 27..<28) - var porrstf: PORRSTF + public var porrstf: PORRSTF /// PIN reset flag @ReadWrite(bits: 26..<27) - var padrstf: PADRSTF + public var padrstf: PADRSTF /// BOR reset flag @ReadWrite(bits: 25..<26) - var borrstf: BORRSTF + public var borrstf: BORRSTF /// Remove reset flag @ReadWrite(bits: 24..<25) - var rmvf: RMVF + public var rmvf: RMVF /// Internal low-speed oscillator ready @ReadOnly(bits: 1..<2) - var lsirdy: LSIRDY + public var lsirdy: LSIRDY /// Internal low-speed oscillator enable @ReadWrite(bits: 0..<1, as: LSIONValues.self) - var lsion: LSION + public var lsion: LSION } /// spread spectrum clock generation register @Register(bitWidth: 32) - struct SSCGR { + public struct SSCGR { /// Spread spectrum modulation enable @ReadWrite(bits: 31..<32, as: SSCGENValues.self) - var sscgen: SSCGEN + public var sscgen: SSCGEN /// Spread Select @ReadWrite(bits: 30..<31, as: SPREADSELValues.self) - var spreadsel: SPREADSEL + public var spreadsel: SPREADSEL /// Incrementation step @ReadWrite(bits: 13..<28) - var incstep: INCSTEP + public var incstep: INCSTEP /// Modulation period @ReadWrite(bits: 0..<13) - var modper: MODPER + public var modper: MODPER } /// PLLI2S configuration register @Register(bitWidth: 32) - struct PLLI2SCFGR { + public struct PLLI2SCFGR { /// PLLI2S division factor for I2S clocks @ReadWrite(bits: 28..<31) - var plli2sr: PLLI2SR + public var plli2sr: PLLI2SR /// PLLI2S division factor for SAI1 clock @ReadWrite(bits: 24..<28) - var plli2sq: PLLI2SQ + public var plli2sq: PLLI2SQ /// PLLI2S multiplication factor for VCO @ReadWrite(bits: 6..<15) - var plli2sn: PLLI2SN + public var plli2sn: PLLI2SN /// PLLI2S division factor for SPDIFRX clock @ReadWrite(bits: 16..<18, as: PLLI2SPValues.self) - var plli2sp: PLLI2SP + public var plli2sp: PLLI2SP } /// PLL configuration register @Register(bitWidth: 32) - struct PLLSAICFGR { + public struct PLLSAICFGR { /// PLLSAI division factor for VCO @ReadWrite(bits: 6..<15) - var pllsain: PLLSAIN + public var pllsain: PLLSAIN /// PLLSAI division factor for 48MHz clock @ReadWrite(bits: 16..<18, as: PLLSAIPValues.self) - var pllsaip: PLLSAIP + public var pllsaip: PLLSAIP /// PLLSAI division factor for SAI clock @ReadWrite(bits: 24..<28) - var pllsaiq: PLLSAIQ + public var pllsaiq: PLLSAIQ /// PLLSAI division factor for LCD clock @ReadWrite(bits: 28..<31) - var pllsair: PLLSAIR + public var pllsair: PLLSAIR } /// dedicated clocks configuration register @Register(bitWidth: 32) - struct DCKCFGR1 { + public struct DCKCFGR1 { /// PLLI2S division factor for SAI1 clock @ReadWrite(bits: 0..<5, as: PLLI2SDIVQValues.self) - var plli2sdivq: PLLI2SDIVQ + public var plli2sdivq: PLLI2SDIVQ /// PLLSAI division factor for SAI1 clock @ReadWrite(bits: 8..<13, as: PLLSAIDIVQValues.self) - var pllsaidivq: PLLSAIDIVQ + public var pllsaidivq: PLLSAIDIVQ /// division factor for LCD_CLK @ReadWrite(bits: 16..<18, as: PLLSAIDIVRValues.self) - var pllsaidivr: PLLSAIDIVR + public var pllsaidivr: PLLSAIDIVR /// SAI1 clock source selection @ReadWrite(bits: 20..<22, as: SAI1SELValues.self) - var sai1sel: SAI1SEL + public var sai1sel: SAI1SEL /// SAI2 clock source selection @ReadWrite(bits: 22..<24, as: SAI2SELValues.self) - var sai2sel: SAI2SEL + public var sai2sel: SAI2SEL /// Timers clocks prescalers selection @ReadWrite(bits: 24..<25, as: TIMPREValues.self) - var timpre: TIMPRE + public var timpre: TIMPRE } /// dedicated clocks configuration register @Register(bitWidth: 32) - struct DCKCFGR2 { + public struct DCKCFGR2 { /// USART 1 clock source selection @ReadWrite(bits: 0..<2, as: USART1SELValues.self) - var usart1sel: USART1SEL + public var usart1sel: USART1SEL /// USART 2 clock source selection @ReadWrite(bits: 2..<4, as: USART2SELValues.self) - var usart2sel: USART2SEL + public var usart2sel: USART2SEL /// USART 3 clock source selection @ReadWrite(bits: 4..<6) - var usart3sel: USART3SEL + public var usart3sel: USART3SEL /// UART 4 clock source selection @ReadWrite(bits: 6..<8) - var uart4sel: UART4SEL + public var uart4sel: UART4SEL /// UART 5 clock source selection @ReadWrite(bits: 8..<10) - var uart5sel: UART5SEL + public var uart5sel: UART5SEL /// USART 6 clock source selection @ReadWrite(bits: 10..<12) - var usart6sel: USART6SEL + public var usart6sel: USART6SEL /// UART 7 clock source selection @ReadWrite(bits: 12..<14) - var uart7sel: UART7SEL + public var uart7sel: UART7SEL /// UART 8 clock source selection @ReadWrite(bits: 14..<16) - var uart8sel: UART8SEL + public var uart8sel: UART8SEL /// I2C1 clock source selection @ReadWrite(bits: 16..<18, as: I2C1SELValues.self) - var i2c1sel: I2C1SEL + public var i2c1sel: I2C1SEL /// I2C2 clock source selection @ReadWrite(bits: 18..<20) - var i2c2sel: I2C2SEL + public var i2c2sel: I2C2SEL /// I2C3 clock source selection @ReadWrite(bits: 20..<22) - var i2c3sel: I2C3SEL + public var i2c3sel: I2C3SEL /// I2C4 clock source selection @ReadWrite(bits: 22..<24) - var i2c4sel: I2C4SEL + public var i2c4sel: I2C4SEL /// Low power timer 1 clock source selection @ReadWrite(bits: 24..<26, as: LPTIM1SELValues.self) - var lptim1sel: LPTIM1SEL + public var lptim1sel: LPTIM1SEL /// HDMI-CEC clock source selection @ReadWrite(bits: 26..<27, as: CECSELValues.self) - var cecsel: CECSEL + public var cecsel: CECSEL /// 48MHz clock source selection @ReadWrite(bits: 27..<28, as: CK48MSELValues.self) - var ck48msel: CK48MSEL + public var ck48msel: CK48MSEL /// SDMMC clock source selection @ReadWrite(bits: 28..<29, as: SDMMC1SELValues.self) - var sdmmc1sel: SDMMC1SEL + public var sdmmc1sel: SDMMC1SEL } } extension RCC.CR { - struct CSSONValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CSSONValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Clock security system disabled (clock detector OFF) - static let Off = Self(rawValue: 0x0) + public static let Off = Self(rawValue: 0x0) /// Clock security system enable (clock detector ON if the HSE is ready, OFF if not) - static let On = Self(rawValue: 0x1) + public static let On = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CR { - struct HSEBYPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct HSEBYPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// HSE crystal oscillator not bypassed - static let NotBypassed = Self(rawValue: 0x0) + public static let NotBypassed = Self(rawValue: 0x0) /// HSE crystal oscillator bypassed with external clock - static let Bypassed = Self(rawValue: 0x1) + public static let Bypassed = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CR { - struct HSIONValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct HSIONValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Clock Off - static let Off = Self(rawValue: 0x0) + public static let Off = Self(rawValue: 0x0) /// Clock On - static let On = Self(rawValue: 0x1) + public static let On = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.PLLCFGR { - struct PLLSRCValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct PLLSRCValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// HSI clock selected as PLL and PLLI2S clock entry - static let HSI = Self(rawValue: 0x0) + public static let HSI = Self(rawValue: 0x0) /// HSE oscillator clock selected as PLL and PLLI2S clock entry - static let HSE = Self(rawValue: 0x1) + public static let HSE = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.PLLCFGR { - struct PLLPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct PLLPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// PLLP=2 - static let Div2 = Self(rawValue: 0x0) + public static let Div2 = Self(rawValue: 0x0) /// PLLP=4 - static let Div4 = Self(rawValue: 0x1) + public static let Div4 = Self(rawValue: 0x1) /// PLLP=6 - static let Div6 = Self(rawValue: 0x2) + public static let Div6 = Self(rawValue: 0x2) /// PLLP=8 - static let Div8 = Self(rawValue: 0x3) + public static let Div8 = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CFGR { - struct MCO2Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct MCO2Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// System clock (SYSCLK) selected - static let SYSCLK = Self(rawValue: 0x0) + public static let SYSCLK = Self(rawValue: 0x0) /// PLLI2S clock selected - static let PLLI2S = Self(rawValue: 0x1) + public static let PLLI2S = Self(rawValue: 0x1) /// HSE oscillator clock selected - static let HSE = Self(rawValue: 0x2) + public static let HSE = Self(rawValue: 0x2) /// PLL clock selected - static let PLL = Self(rawValue: 0x3) + public static let PLL = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CFGR { - struct MCO1PREValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 3 + public struct MCO1PREValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 3 /// No division - static let Div1 = Self(rawValue: 0x0) + public static let Div1 = Self(rawValue: 0x0) /// Division by 2 - static let Div2 = Self(rawValue: 0x4) + public static let Div2 = Self(rawValue: 0x4) /// Division by 3 - static let Div3 = Self(rawValue: 0x5) + public static let Div3 = Self(rawValue: 0x5) /// Division by 4 - static let Div4 = Self(rawValue: 0x6) + public static let Div4 = Self(rawValue: 0x6) /// Division by 5 - static let Div5 = Self(rawValue: 0x7) + public static let Div5 = Self(rawValue: 0x7) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CFGR { - struct I2SSRCValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct I2SSRCValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// PLLI2S clock used as I2S clock source - static let PLLI2S = Self(rawValue: 0x0) + public static let PLLI2S = Self(rawValue: 0x0) /// External clock mapped on the I2S_CKIN pin used as I2S clock source - static let CKIN = Self(rawValue: 0x1) + public static let CKIN = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CFGR { - struct MCO1Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct MCO1Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// HSI clock selected - static let HSI = Self(rawValue: 0x0) + public static let HSI = Self(rawValue: 0x0) /// LSE oscillator selected - static let LSE = Self(rawValue: 0x1) + public static let LSE = Self(rawValue: 0x1) /// HSE oscillator clock selected - static let HSE = Self(rawValue: 0x2) + public static let HSE = Self(rawValue: 0x2) /// PLL clock selected - static let PLL = Self(rawValue: 0x3) + public static let PLL = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CFGR { - struct PPRE1Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 3 + public struct PPRE1Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 3 /// HCLK not divided - static let Div1 = Self(rawValue: 0x0) + public static let Div1 = Self(rawValue: 0x0) /// HCLK divided by 2 - static let Div2 = Self(rawValue: 0x4) + public static let Div2 = Self(rawValue: 0x4) /// HCLK divided by 4 - static let Div4 = Self(rawValue: 0x5) + public static let Div4 = Self(rawValue: 0x5) /// HCLK divided by 8 - static let Div8 = Self(rawValue: 0x6) + public static let Div8 = Self(rawValue: 0x6) /// HCLK divided by 16 - static let Div16 = Self(rawValue: 0x7) + public static let Div16 = Self(rawValue: 0x7) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CFGR { - struct HPREValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 4 + public struct HPREValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 4 /// SYSCLK not divided - static let Div1 = Self(rawValue: 0x0) + public static let Div1 = Self(rawValue: 0x0) /// SYSCLK divided by 2 - static let Div2 = Self(rawValue: 0x8) + public static let Div2 = Self(rawValue: 0x8) /// SYSCLK divided by 4 - static let Div4 = Self(rawValue: 0x9) + public static let Div4 = Self(rawValue: 0x9) /// SYSCLK divided by 8 - static let Div8 = Self(rawValue: 0xa) + public static let Div8 = Self(rawValue: 0xa) /// SYSCLK divided by 16 - static let Div16 = Self(rawValue: 0xb) + public static let Div16 = Self(rawValue: 0xb) /// SYSCLK divided by 64 - static let Div64 = Self(rawValue: 0xc) + public static let Div64 = Self(rawValue: 0xc) /// SYSCLK divided by 128 - static let Div128 = Self(rawValue: 0xd) + public static let Div128 = Self(rawValue: 0xd) /// SYSCLK divided by 256 - static let Div256 = Self(rawValue: 0xe) + public static let Div256 = Self(rawValue: 0xe) /// SYSCLK divided by 512 - static let Div512 = Self(rawValue: 0xf) + public static let Div512 = Self(rawValue: 0xf) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CFGR { - struct SWValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct SWValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// HSI selected as system clock - static let HSI = Self(rawValue: 0x0) + public static let HSI = Self(rawValue: 0x0) /// HSE selected as system clock - static let HSE = Self(rawValue: 0x1) + public static let HSE = Self(rawValue: 0x1) /// PLL selected as system clock - static let PLL = Self(rawValue: 0x2) + public static let PLL = Self(rawValue: 0x2) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CIR { - struct LSIRDYIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LSIRDYIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Interrupt enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB1RSTR { - struct GPIOARSTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct GPIOARSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Reset the selected module - static let Reset = Self(rawValue: 0x1) + public static let Reset = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB2RSTR { - struct DCMIRSTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DCMIRSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Reset the selected module - static let Reset = Self(rawValue: 0x1) + public static let Reset = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB3RSTR { - struct FMCRSTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct FMCRSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Reset the selected module - static let Reset = Self(rawValue: 0x1) + public static let Reset = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.APB1RSTR { - struct TIM2RSTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TIM2RSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Reset the selected module - static let Reset = Self(rawValue: 0x1) + public static let Reset = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.APB2RSTR { - struct TIM1RSTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TIM1RSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Reset the selected module - static let Reset = Self(rawValue: 0x1) + public static let Reset = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB1ENR { - struct GPIOAENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct GPIOAENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// The selected clock is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// The selected clock is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB2ENR { - struct DCMIENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DCMIENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// The selected clock is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// The selected clock is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB3ENR { - struct FMCENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct FMCENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// The selected clock is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// The selected clock is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.APB1ENR { - struct TIM2ENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TIM2ENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// The selected clock is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// The selected clock is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.APB2ENR { - struct TIM1ENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TIM1ENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// The selected clock is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// The selected clock is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB1LPENR { - struct GPIOALPENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct GPIOALPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Selected module is disabled during Sleep mode - static let DisabledInSleep = Self(rawValue: 0x0) + public static let DisabledInSleep = Self(rawValue: 0x0) /// Selected module is enabled during Sleep mode - static let EnabledInSleep = Self(rawValue: 0x1) + public static let EnabledInSleep = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB2LPENR { - struct DCMILPENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DCMILPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Selected module is disabled during Sleep mode - static let DisabledInSleep = Self(rawValue: 0x0) + public static let DisabledInSleep = Self(rawValue: 0x0) /// Selected module is enabled during Sleep mode - static let EnabledInSleep = Self(rawValue: 0x1) + public static let EnabledInSleep = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB3LPENR { - struct FMCLPENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct FMCLPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Selected module is disabled during Sleep mode - static let DisabledInSleep = Self(rawValue: 0x0) + public static let DisabledInSleep = Self(rawValue: 0x0) /// Selected module is enabled during Sleep mode - static let EnabledInSleep = Self(rawValue: 0x1) + public static let EnabledInSleep = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.APB1LPENR { - struct TIM2LPENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TIM2LPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Selected module is disabled during Sleep mode - static let DisabledInSleep = Self(rawValue: 0x0) + public static let DisabledInSleep = Self(rawValue: 0x0) /// Selected module is enabled during Sleep mode - static let EnabledInSleep = Self(rawValue: 0x1) + public static let EnabledInSleep = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.APB2LPENR { - struct TIM1LPENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TIM1LPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Selected module is disabled during Sleep mode - static let DisabledInSleep = Self(rawValue: 0x0) + public static let DisabledInSleep = Self(rawValue: 0x0) /// Selected module is enabled during Sleep mode - static let EnabledInSleep = Self(rawValue: 0x1) + public static let EnabledInSleep = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.BDCR { - struct BDRSTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct BDRSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Reset not activated - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Reset the entire RTC domain - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.BDCR { - struct RTCENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct RTCENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// RTC clock disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// RTC clock enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.BDCR { - struct LSEBYPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LSEBYPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// LSE crystal oscillator not bypassed - static let NotBypassed = Self(rawValue: 0x0) + public static let NotBypassed = Self(rawValue: 0x0) /// LSE crystal oscillator bypassed with external clock - static let Bypassed = Self(rawValue: 0x1) + public static let Bypassed = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.BDCR { - struct LSEONValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LSEONValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// LSE oscillator Off - static let Off = Self(rawValue: 0x0) + public static let Off = Self(rawValue: 0x0) /// LSE oscillator On - static let On = Self(rawValue: 0x1) + public static let On = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.BDCR { - struct LSEDRVValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct LSEDRVValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// Low drive capacity - static let Low = Self(rawValue: 0x0) + public static let Low = Self(rawValue: 0x0) /// Medium-high drive capacity - static let MediumHigh = Self(rawValue: 0x1) + public static let MediumHigh = Self(rawValue: 0x1) /// Medium-low drive capacity - static let MediumLow = Self(rawValue: 0x2) + public static let MediumLow = Self(rawValue: 0x2) /// High drive capacity - static let High = Self(rawValue: 0x3) + public static let High = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.BDCR { - struct RTCSELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct RTCSELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// No clock - static let NoClock = Self(rawValue: 0x0) + public static let NoClock = Self(rawValue: 0x0) /// LSE oscillator clock used as RTC clock - static let LSE = Self(rawValue: 0x1) + public static let LSE = Self(rawValue: 0x1) /// LSI oscillator clock used as RTC clock - static let LSI = Self(rawValue: 0x2) + public static let LSI = Self(rawValue: 0x2) /// HSE oscillator clock divided by a prescaler used as RTC clock - static let HSE = Self(rawValue: 0x3) + public static let HSE = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CSR { - struct LSIONValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LSIONValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// LSI oscillator Off - static let Off = Self(rawValue: 0x0) + public static let Off = Self(rawValue: 0x0) /// LSI oscillator On - static let On = Self(rawValue: 0x1) + public static let On = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.SSCGR { - struct SSCGENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct SSCGENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Spread spectrum modulation disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Spread spectrum modulation enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.SSCGR { - struct SPREADSELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct SPREADSELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Center spread - static let Center = Self(rawValue: 0x0) + public static let Center = Self(rawValue: 0x0) /// Down spread - static let Down = Self(rawValue: 0x1) + public static let Down = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.PLLI2SCFGR { - struct PLLI2SPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct PLLI2SPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// PLL*P=2 - static let Div2 = Self(rawValue: 0x0) + public static let Div2 = Self(rawValue: 0x0) /// PLL*P=4 - static let Div4 = Self(rawValue: 0x1) + public static let Div4 = Self(rawValue: 0x1) /// PLL*P=6 - static let Div6 = Self(rawValue: 0x2) + public static let Div6 = Self(rawValue: 0x2) /// PLL*P=8 - static let Div8 = Self(rawValue: 0x3) + public static let Div8 = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.PLLSAICFGR { - struct PLLSAIPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct PLLSAIPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// PLL*P=2 - static let Div2 = Self(rawValue: 0x0) + public static let Div2 = Self(rawValue: 0x0) /// PLL*P=4 - static let Div4 = Self(rawValue: 0x1) + public static let Div4 = Self(rawValue: 0x1) /// PLL*P=6 - static let Div6 = Self(rawValue: 0x2) + public static let Div6 = Self(rawValue: 0x2) /// PLL*P=8 - static let Div8 = Self(rawValue: 0x3) + public static let Div8 = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR1 { - struct PLLI2SDIVQValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 5 + public struct PLLI2SDIVQValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 5 /// PLLI2SDIVQ = /1 - static let Div1 = Self(rawValue: 0x0) + public static let Div1 = Self(rawValue: 0x0) /// PLLI2SDIVQ = /2 - static let Div2 = Self(rawValue: 0x1) + public static let Div2 = Self(rawValue: 0x1) /// PLLI2SDIVQ = /3 - static let Div3 = Self(rawValue: 0x2) + public static let Div3 = Self(rawValue: 0x2) /// PLLI2SDIVQ = /4 - static let Div4 = Self(rawValue: 0x3) + public static let Div4 = Self(rawValue: 0x3) /// PLLI2SDIVQ = /5 - static let Div5 = Self(rawValue: 0x4) + public static let Div5 = Self(rawValue: 0x4) /// PLLI2SDIVQ = /6 - static let Div6 = Self(rawValue: 0x5) + public static let Div6 = Self(rawValue: 0x5) /// PLLI2SDIVQ = /7 - static let Div7 = Self(rawValue: 0x6) + public static let Div7 = Self(rawValue: 0x6) /// PLLI2SDIVQ = /8 - static let Div8 = Self(rawValue: 0x7) + public static let Div8 = Self(rawValue: 0x7) /// PLLI2SDIVQ = /9 - static let Div9 = Self(rawValue: 0x8) + public static let Div9 = Self(rawValue: 0x8) /// PLLI2SDIVQ = /10 - static let Div10 = Self(rawValue: 0x9) + public static let Div10 = Self(rawValue: 0x9) /// PLLI2SDIVQ = /11 - static let Div11 = Self(rawValue: 0xa) + public static let Div11 = Self(rawValue: 0xa) /// PLLI2SDIVQ = /12 - static let Div12 = Self(rawValue: 0xb) + public static let Div12 = Self(rawValue: 0xb) /// PLLI2SDIVQ = /13 - static let Div13 = Self(rawValue: 0xc) + public static let Div13 = Self(rawValue: 0xc) /// PLLI2SDIVQ = /14 - static let Div14 = Self(rawValue: 0xd) + public static let Div14 = Self(rawValue: 0xd) /// PLLI2SDIVQ = /15 - static let Div15 = Self(rawValue: 0xe) + public static let Div15 = Self(rawValue: 0xe) /// PLLI2SDIVQ = /16 - static let Div16 = Self(rawValue: 0xf) + public static let Div16 = Self(rawValue: 0xf) /// PLLI2SDIVQ = /17 - static let Div17 = Self(rawValue: 0x10) + public static let Div17 = Self(rawValue: 0x10) /// PLLI2SDIVQ = /18 - static let Div18 = Self(rawValue: 0x11) + public static let Div18 = Self(rawValue: 0x11) /// PLLI2SDIVQ = /19 - static let Div19 = Self(rawValue: 0x12) + public static let Div19 = Self(rawValue: 0x12) /// PLLI2SDIVQ = /20 - static let Div20 = Self(rawValue: 0x13) + public static let Div20 = Self(rawValue: 0x13) /// PLLI2SDIVQ = /21 - static let Div21 = Self(rawValue: 0x14) + public static let Div21 = Self(rawValue: 0x14) /// PLLI2SDIVQ = /22 - static let Div22 = Self(rawValue: 0x15) + public static let Div22 = Self(rawValue: 0x15) /// PLLI2SDIVQ = /23 - static let Div23 = Self(rawValue: 0x16) + public static let Div23 = Self(rawValue: 0x16) /// PLLI2SDIVQ = /24 - static let Div24 = Self(rawValue: 0x17) + public static let Div24 = Self(rawValue: 0x17) /// PLLI2SDIVQ = /25 - static let Div25 = Self(rawValue: 0x18) + public static let Div25 = Self(rawValue: 0x18) /// PLLI2SDIVQ = /26 - static let Div26 = Self(rawValue: 0x19) + public static let Div26 = Self(rawValue: 0x19) /// PLLI2SDIVQ = /27 - static let Div27 = Self(rawValue: 0x1a) + public static let Div27 = Self(rawValue: 0x1a) /// PLLI2SDIVQ = /28 - static let Div28 = Self(rawValue: 0x1b) + public static let Div28 = Self(rawValue: 0x1b) /// PLLI2SDIVQ = /29 - static let Div29 = Self(rawValue: 0x1c) + public static let Div29 = Self(rawValue: 0x1c) /// PLLI2SDIVQ = /30 - static let Div30 = Self(rawValue: 0x1d) + public static let Div30 = Self(rawValue: 0x1d) /// PLLI2SDIVQ = /31 - static let Div31 = Self(rawValue: 0x1e) + public static let Div31 = Self(rawValue: 0x1e) /// PLLI2SDIVQ = /32 - static let Div32 = Self(rawValue: 0x1f) + public static let Div32 = Self(rawValue: 0x1f) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR1 { - struct PLLSAIDIVQValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 5 + public struct PLLSAIDIVQValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 5 /// PLLSAIDIVQ = /1 - static let Div1 = Self(rawValue: 0x0) + public static let Div1 = Self(rawValue: 0x0) /// PLLSAIDIVQ = /2 - static let Div2 = Self(rawValue: 0x1) + public static let Div2 = Self(rawValue: 0x1) /// PLLSAIDIVQ = /3 - static let Div3 = Self(rawValue: 0x2) + public static let Div3 = Self(rawValue: 0x2) /// PLLSAIDIVQ = /4 - static let Div4 = Self(rawValue: 0x3) + public static let Div4 = Self(rawValue: 0x3) /// PLLSAIDIVQ = /5 - static let Div5 = Self(rawValue: 0x4) + public static let Div5 = Self(rawValue: 0x4) /// PLLSAIDIVQ = /6 - static let Div6 = Self(rawValue: 0x5) + public static let Div6 = Self(rawValue: 0x5) /// PLLSAIDIVQ = /7 - static let Div7 = Self(rawValue: 0x6) + public static let Div7 = Self(rawValue: 0x6) /// PLLSAIDIVQ = /8 - static let Div8 = Self(rawValue: 0x7) + public static let Div8 = Self(rawValue: 0x7) /// PLLSAIDIVQ = /9 - static let Div9 = Self(rawValue: 0x8) + public static let Div9 = Self(rawValue: 0x8) /// PLLSAIDIVQ = /10 - static let Div10 = Self(rawValue: 0x9) + public static let Div10 = Self(rawValue: 0x9) /// PLLSAIDIVQ = /11 - static let Div11 = Self(rawValue: 0xa) + public static let Div11 = Self(rawValue: 0xa) /// PLLSAIDIVQ = /12 - static let Div12 = Self(rawValue: 0xb) + public static let Div12 = Self(rawValue: 0xb) /// PLLSAIDIVQ = /13 - static let Div13 = Self(rawValue: 0xc) + public static let Div13 = Self(rawValue: 0xc) /// PLLSAIDIVQ = /14 - static let Div14 = Self(rawValue: 0xd) + public static let Div14 = Self(rawValue: 0xd) /// PLLSAIDIVQ = /15 - static let Div15 = Self(rawValue: 0xe) + public static let Div15 = Self(rawValue: 0xe) /// PLLSAIDIVQ = /16 - static let Div16 = Self(rawValue: 0xf) + public static let Div16 = Self(rawValue: 0xf) /// PLLSAIDIVQ = /17 - static let Div17 = Self(rawValue: 0x10) + public static let Div17 = Self(rawValue: 0x10) /// PLLSAIDIVQ = /18 - static let Div18 = Self(rawValue: 0x11) + public static let Div18 = Self(rawValue: 0x11) /// PLLSAIDIVQ = /19 - static let Div19 = Self(rawValue: 0x12) + public static let Div19 = Self(rawValue: 0x12) /// PLLSAIDIVQ = /20 - static let Div20 = Self(rawValue: 0x13) + public static let Div20 = Self(rawValue: 0x13) /// PLLSAIDIVQ = /21 - static let Div21 = Self(rawValue: 0x14) + public static let Div21 = Self(rawValue: 0x14) /// PLLSAIDIVQ = /22 - static let Div22 = Self(rawValue: 0x15) + public static let Div22 = Self(rawValue: 0x15) /// PLLSAIDIVQ = /23 - static let Div23 = Self(rawValue: 0x16) + public static let Div23 = Self(rawValue: 0x16) /// PLLSAIDIVQ = /24 - static let Div24 = Self(rawValue: 0x17) + public static let Div24 = Self(rawValue: 0x17) /// PLLSAIDIVQ = /25 - static let Div25 = Self(rawValue: 0x18) + public static let Div25 = Self(rawValue: 0x18) /// PLLSAIDIVQ = /26 - static let Div26 = Self(rawValue: 0x19) + public static let Div26 = Self(rawValue: 0x19) /// PLLSAIDIVQ = /27 - static let Div27 = Self(rawValue: 0x1a) + public static let Div27 = Self(rawValue: 0x1a) /// PLLSAIDIVQ = /28 - static let Div28 = Self(rawValue: 0x1b) + public static let Div28 = Self(rawValue: 0x1b) /// PLLSAIDIVQ = /29 - static let Div29 = Self(rawValue: 0x1c) + public static let Div29 = Self(rawValue: 0x1c) /// PLLSAIDIVQ = /30 - static let Div30 = Self(rawValue: 0x1d) + public static let Div30 = Self(rawValue: 0x1d) /// PLLSAIDIVQ = /31 - static let Div31 = Self(rawValue: 0x1e) + public static let Div31 = Self(rawValue: 0x1e) /// PLLSAIDIVQ = /32 - static let Div32 = Self(rawValue: 0x1f) + public static let Div32 = Self(rawValue: 0x1f) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR1 { - struct PLLSAIDIVRValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct PLLSAIDIVRValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// PLLSAIDIVR = /2 - static let Div2 = Self(rawValue: 0x0) + public static let Div2 = Self(rawValue: 0x0) /// PLLSAIDIVR = /4 - static let Div4 = Self(rawValue: 0x1) + public static let Div4 = Self(rawValue: 0x1) /// PLLSAIDIVR = /8 - static let Div8 = Self(rawValue: 0x2) + public static let Div8 = Self(rawValue: 0x2) /// PLLSAIDIVR = /16 - static let Div16 = Self(rawValue: 0x3) + public static let Div16 = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR1 { - struct SAI1SELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct SAI1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - static let PLLSAI = Self(rawValue: 0x0) + public static let PLLSAI = Self(rawValue: 0x0) /// SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - static let PLLI2S = Self(rawValue: 0x1) + public static let PLLI2S = Self(rawValue: 0x1) /// SAI1 clock frequency = Alternate function input frequency - static let AFIF = Self(rawValue: 0x2) + public static let AFIF = Self(rawValue: 0x2) /// SAI1 clock frequency = HSI or HSE - static let HSI_HSE = Self(rawValue: 0x3) + public static let HSI_HSE = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR1 { - struct SAI2SELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct SAI2SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - static let PLLSAI = Self(rawValue: 0x0) + public static let PLLSAI = Self(rawValue: 0x0) /// SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - static let PLLI2S = Self(rawValue: 0x1) + public static let PLLI2S = Self(rawValue: 0x1) /// SAI2 clock frequency = Alternate function input frequency - static let AFIF = Self(rawValue: 0x2) + public static let AFIF = Self(rawValue: 0x2) /// SAI2 clock frequency = HSI or HSE - static let HSI_HSE = Self(rawValue: 0x3) + public static let HSI_HSE = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR1 { - struct TIMPREValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TIMPREValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx - static let Mul1Or2 = Self(rawValue: 0x0) + public static let Mul1Or2 = Self(rawValue: 0x0) /// If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx - static let Mul1Or4 = Self(rawValue: 0x1) + public static let Mul1Or4 = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR2 { - struct USART1SELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct USART1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// APB2 clock (PCLK2) is selected as USART clock - static let APB2 = Self(rawValue: 0x0) + public static let APB2 = Self(rawValue: 0x0) /// System clock is selected as USART clock - static let SYSCLK = Self(rawValue: 0x1) + public static let SYSCLK = Self(rawValue: 0x1) /// HSI clock is selected as USART clock - static let HSI = Self(rawValue: 0x2) + public static let HSI = Self(rawValue: 0x2) /// LSE clock is selected as USART clock - static let LSE = Self(rawValue: 0x3) + public static let LSE = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR2 { - struct USART2SELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct USART2SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// APB1 clock (PCLK1) is selected as USART clock - static let APB1 = Self(rawValue: 0x0) + public static let APB1 = Self(rawValue: 0x0) /// System clock is selected as USART clock - static let SYSCLK = Self(rawValue: 0x1) + public static let SYSCLK = Self(rawValue: 0x1) /// HSI clock is selected as USART clock - static let HSI = Self(rawValue: 0x2) + public static let HSI = Self(rawValue: 0x2) /// LSE clock is selected as USART clock - static let LSE = Self(rawValue: 0x3) + public static let LSE = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR2 { - struct I2C1SELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct I2C1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// APB clock selected as I2C clock - static let APB = Self(rawValue: 0x0) + public static let APB = Self(rawValue: 0x0) /// System clock selected as I2C clock - static let SYSCLK = Self(rawValue: 0x1) + public static let SYSCLK = Self(rawValue: 0x1) /// HSI clock selected as I2C clock - static let HSI = Self(rawValue: 0x2) + public static let HSI = Self(rawValue: 0x2) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR2 { - struct LPTIM1SELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct LPTIM1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// APB1 clock (PCLK1) selected as LPTILM1 clock - static let APB1 = Self(rawValue: 0x0) + public static let APB1 = Self(rawValue: 0x0) /// LSI clock is selected as LPTILM1 clock - static let LSI = Self(rawValue: 0x1) + public static let LSI = Self(rawValue: 0x1) /// HSI clock is selected as LPTILM1 clock - static let HSI = Self(rawValue: 0x2) + public static let HSI = Self(rawValue: 0x2) /// LSE clock is selected as LPTILM1 clock - static let LSE = Self(rawValue: 0x3) + public static let LSE = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR2 { - struct CECSELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CECSELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// LSE clock is selected as HDMI-CEC clock - static let LSE = Self(rawValue: 0x0) + public static let LSE = Self(rawValue: 0x0) /// HSI divided by 488 clock is selected as HDMI-CEC clock - static let HSI_Div488 = Self(rawValue: 0x1) + public static let HSI_Div488 = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR2 { - struct CK48MSELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CK48MSELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// 48MHz clock from PLL is selected - static let PLL = Self(rawValue: 0x0) + public static let PLL = Self(rawValue: 0x0) /// 48MHz clock from PLLSAI is selected - static let PLLSAI = Self(rawValue: 0x1) + public static let PLLSAI = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR2 { - struct SDMMC1SELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct SDMMC1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// 48 MHz clock is selected as SD clock - static let CK48M = Self(rawValue: 0x0) + public static let CK48M = Self(rawValue: 0x0) /// System clock is selected as SD clock - static let SYSCLK = Self(rawValue: 0x1) + public static let SYSCLK = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } diff --git a/stm32-lcd-logo/Sources/STM32F7X6/stm32f7x6.patched.svd b/stm32-lcd-logo/Sources/STM32F7X6/stm32f7x6.patched.svd new file mode 120000 index 00000000..a6442b50 --- /dev/null +++ b/stm32-lcd-logo/Sources/STM32F7X6/stm32f7x6.patched.svd @@ -0,0 +1 @@ +../../../Tools/SVDs/stm32f7x6.patched.svd \ No newline at end of file diff --git a/stm32-lcd-logo/Sources/STM32F7X6/svd2swift.json b/stm32-lcd-logo/Sources/STM32F7X6/svd2swift.json new file mode 100644 index 00000000..dd674df6 --- /dev/null +++ b/stm32-lcd-logo/Sources/STM32F7X6/svd2swift.json @@ -0,0 +1,19 @@ +{ + "peripherals": [ + "FLASH", + "GPIOA", + "GPIOB", + "GPIOC", + "GPIOD", + "GPIOE", + "GPIOF", + "GPIOG", + "GPIOH", + "GPIOI", + "GPIOJ", + "GPIOK", + "LTDC", + "RCC" + ], + "access-level": "public" +} diff --git a/stm32-neopixel/Makefile b/stm32-neopixel/Makefile index 8880d741..d66a5fc0 100755 --- a/stm32-neopixel/Makefile +++ b/stm32-neopixel/Makefile @@ -46,7 +46,10 @@ build: @echo "extracting binary..." $(MACHO2BIN) \ - $(BUILDROOT)/Application $(BUILDROOT)/Application.bin --base-address 0x20010000 --segments '__TEXT,__DATA,__VECTORS' + $(BUILDROOT)/Application \ + $(BUILDROOT)/Application.bin \ + --base-address 0x20010000 \ + --segments '__TEXT,__DATA,__VECTORS' .PHONY: clean clean: diff --git a/stm32-neopixel/Package.resolved b/stm32-neopixel/Package.resolved index d7e51efb..e9d315fa 100644 --- a/stm32-neopixel/Package.resolved +++ b/stm32-neopixel/Package.resolved @@ -1,5 +1,5 @@ { - "originHash" : "1e5ddc29279ed8df40c89e2aa6c1b16483a597824c05a9e88d3e1b8e4607db39", + "originHash" : "fec1335f7424378925c47a261a19ffe2160476fc1e6fd88c5e270ddff078da9d", "pins" : [ { "identity" : "swift-argument-parser", @@ -16,7 +16,7 @@ "location" : "https://github.com/apple/swift-mmio", "state" : { "branch" : "main", - "revision" : "daf25ecacc0d9b71036c6af32cb7786a01802799" + "revision" : "5232c5129a8c70beafc3d6acfbae2716c1b6822a" } }, { diff --git a/stm32-neopixel/Package.swift b/stm32-neopixel/Package.swift index 79803832..972f744c 100644 --- a/stm32-neopixel/Package.swift +++ b/stm32-neopixel/Package.swift @@ -4,9 +4,6 @@ import PackageDescription let package = Package( name: "stm32-neopixel", - platforms: [ - .macOS(.v10_15) - ], products: [ .executable(name: "Application", targets: ["Application"]) ], @@ -14,16 +11,24 @@ let package = Package( .package(url: "https://github.com/apple/swift-mmio", branch: "main") ], targets: [ - // SVD2Swift \ - // -i ../Tools/SVDs/stm32f7x6.patched.svd \ - // -o Sources/Application/Registers \ - // --indentation-width 2 \ - // -p DMA1 DMA2 GPIOA GPIOB GPIOI RCC SPI1 SPI2 USART1 .executableTarget( name: "Application", + dependencies: ["STM32F7X6", "Support"]), + // SVD2Swift \ + // --input Sources/STM32F7X6/stm32f7x6.patched.svd \ + // --output Sources/STM32F7X6 \ + // --access-level public \ + // --indentation-width 2 \ + // --peripherals DMA1 DMA2 GPIOA GPIOB GPIOI RCC SPI1 SPI2 USART1 + .target( + name: "STM32F7X6", dependencies: [ - .product(name: "MMIO", package: "swift-mmio"), - "Support", + .product(name: "MMIO", package: "swift-mmio") + ], + plugins: [ + // Plugin disabled because SwiftPM is slow. + // .plugin(name: "SVD2SwiftPlugin", package: "swift-mmio") ]), .target(name: "Support"), - ]) + ], + swiftLanguageModes: [.v5]) diff --git a/stm32-neopixel/Sources/Application/Application.swift b/stm32-neopixel/Sources/Application/Application.swift index 93ea5a40..2daab9a9 100644 --- a/stm32-neopixel/Sources/Application/Application.swift +++ b/stm32-neopixel/Sources/Application/Application.swift @@ -9,6 +9,7 @@ // //===----------------------------------------------------------------------===// +import STM32F7X6 import Support @main diff --git a/stm32-neopixel/Sources/Application/Registers/GPIO.swift b/stm32-neopixel/Sources/Application/GPIO.swift similarity index 99% rename from stm32-neopixel/Sources/Application/Registers/GPIO.swift rename to stm32-neopixel/Sources/Application/GPIO.swift index a90ecd4e..8e24b427 100644 --- a/stm32-neopixel/Sources/Application/Registers/GPIO.swift +++ b/stm32-neopixel/Sources/Application/GPIO.swift @@ -9,6 +9,8 @@ // //===----------------------------------------------------------------------===// +import STM32F7X6 + extension GPIOA { enum Mode: UInt32 { case input = 0x0 diff --git a/stm32-neopixel/Sources/Application/Neopixel/SPINeoPixel.swift b/stm32-neopixel/Sources/Application/Neopixel/SPINeoPixel.swift index 98eee592..c130ce5e 100644 --- a/stm32-neopixel/Sources/Application/Neopixel/SPINeoPixel.swift +++ b/stm32-neopixel/Sources/Application/Neopixel/SPINeoPixel.swift @@ -9,6 +9,8 @@ // //===----------------------------------------------------------------------===// +import STM32F7X6 + class PixelBuffer { let buffer: UnsafeMutableBufferPointer diff --git a/stm32-neopixel/Sources/Application/Registers/Device.swift b/stm32-neopixel/Sources/Application/Registers/Device.swift deleted file mode 100644 index 3d315391..00000000 --- a/stm32-neopixel/Sources/Application/Registers/Device.swift +++ /dev/null @@ -1,30 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// DMA controller -let dma1 = DMA1(unsafeAddress: 0x40026000) - -/// DMA controller -let dma2 = DMA2(unsafeAddress: 0x40026400) - -/// General-purpose I/Os -let gpioa = GPIOA(unsafeAddress: 0x40020000) - -/// General-purpose I/Os -let gpiob = GPIOB(unsafeAddress: 0x40020400) - -/// General-purpose I/Os -let gpioi = GPIOI(unsafeAddress: 0x40022000) - -/// Reset and clock control -let rcc = RCC(unsafeAddress: 0x40023800) - -/// Serial peripheral interface -let spi1 = SPI1(unsafeAddress: 0x40013000) - -/// Serial peripheral interface -let spi2 = SPI2(unsafeAddress: 0x40003800) - -/// Universal synchronous asynchronous receiver transmitter -let usart1 = USART1(unsafeAddress: 0x40011000) diff --git a/stm32-neopixel/Sources/Application/Registers/SPI1.swift b/stm32-neopixel/Sources/Application/Registers/SPI1.swift deleted file mode 100644 index d182ff40..00000000 --- a/stm32-neopixel/Sources/Application/Registers/SPI1.swift +++ /dev/null @@ -1,1043 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// Serial peripheral interface -@RegisterBlock -struct SPI1 { - /// control register 1 - @RegisterBlock(offset: 0x0) - var cr1: Register - - /// control register 2 - @RegisterBlock(offset: 0x4) - var cr2: Register - - /// status register - @RegisterBlock(offset: 0x8) - var sr: Register - - /// data register - @RegisterBlock(offset: 0xc) - var dr: Register - - /// CRC polynomial register - @RegisterBlock(offset: 0x10) - var crcpr: Register - - /// RX CRC register - @RegisterBlock(offset: 0x14) - var rxcrcr: Register - - /// TX CRC register - @RegisterBlock(offset: 0x18) - var txcrcr: Register - - /// I2S configuration register - @RegisterBlock(offset: 0x1c) - var i2scfgr: Register - - /// I2S prescaler register - @RegisterBlock(offset: 0x20) - var i2spr: Register -} - -extension SPI1 { - /// control register 1 - @Register(bitWidth: 32) - struct CR1 { - /// Bidirectional data mode enable - @ReadWrite(bits: 15..<16, as: BIDIMODEValues.self) - var bidimode: BIDIMODE - - /// Output enable in bidirectional mode - @ReadWrite(bits: 14..<15, as: BIDIOEValues.self) - var bidioe: BIDIOE - - /// Hardware CRC calculation enable - @ReadWrite(bits: 13..<14, as: CRCENValues.self) - var crcen: CRCEN - - /// CRC transfer next - @ReadWrite(bits: 12..<13, as: CRCNEXTValues.self) - var crcnext: CRCNEXT - - /// CRC length - @ReadWrite(bits: 11..<12, as: CRCLValues.self) - var crcl: CRCL - - /// Receive only - @ReadWrite(bits: 10..<11, as: RXONLYValues.self) - var rxonly: RXONLY - - /// Software slave management - @ReadWrite(bits: 9..<10, as: SSMValues.self) - var ssm: SSM - - /// Internal slave select - @ReadWrite(bits: 8..<9, as: SSIValues.self) - var ssi: SSI - - /// Frame format - @ReadWrite(bits: 7..<8, as: LSBFIRSTValues.self) - var lsbfirst: LSBFIRST - - /// SPI enable - @ReadWrite(bits: 6..<7, as: SPEValues.self) - var spe: SPE - - /// Baud rate control - @ReadWrite(bits: 3..<6, as: BRValues.self) - var br: BR - - /// Master selection - @ReadWrite(bits: 2..<3, as: MSTRValues.self) - var mstr: MSTR - - /// Clock polarity - @ReadWrite(bits: 1..<2, as: CPOLValues.self) - var cpol: CPOL - - /// Clock phase - @ReadWrite(bits: 0..<1, as: CPHAValues.self) - var cpha: CPHA - } - - /// control register 2 - @Register(bitWidth: 32) - struct CR2 { - /// Rx buffer DMA enable - @ReadWrite(bits: 0..<1, as: RXDMAENValues.self) - var rxdmaen: RXDMAEN - - /// Tx buffer DMA enable - @ReadWrite(bits: 1..<2, as: TXDMAENValues.self) - var txdmaen: TXDMAEN - - /// SS output enable - @ReadWrite(bits: 2..<3, as: SSOEValues.self) - var ssoe: SSOE - - /// NSS pulse management - @ReadWrite(bits: 3..<4, as: NSSPValues.self) - var nssp: NSSP - - /// Frame format - @ReadWrite(bits: 4..<5, as: FRFValues.self) - var frf: FRF - - /// Error interrupt enable - @ReadWrite(bits: 5..<6, as: ERRIEValues.self) - var errie: ERRIE - - /// RX buffer not empty interrupt enable - @ReadWrite(bits: 6..<7, as: RXNEIEValues.self) - var rxneie: RXNEIE - - /// Tx buffer empty interrupt enable - @ReadWrite(bits: 7..<8, as: TXEIEValues.self) - var txeie: TXEIE - - /// Data size - @ReadWrite(bits: 8..<12, as: DSValues.self) - var ds: DS - - /// FIFO reception threshold - @ReadWrite(bits: 12..<13, as: FRXTHValues.self) - var frxth: FRXTH - - /// Last DMA transfer for reception - @ReadWrite(bits: 13..<14, as: LDMA_RXValues.self) - var ldma_rx: LDMA_RX - - /// Last DMA transfer for transmission - @ReadWrite(bits: 14..<15, as: LDMA_TXValues.self) - var ldma_tx: LDMA_TX - } - - /// status register - @Register(bitWidth: 32) - struct SR { - /// Frame format error - @ReadOnly(bits: 8..<9) - var fre: FRE - - /// Busy flag - @ReadOnly(bits: 7..<8) - var bsy: BSY - - /// Overrun flag - @ReadOnly(bits: 6..<7) - var ovr: OVR - - /// Mode fault - @ReadOnly(bits: 5..<6) - var modf: MODF - - /// CRC error flag - @ReadWrite(bits: 4..<5) - var crcerr: CRCERR - - /// Underrun flag - @ReadOnly(bits: 3..<4) - var udr: UDR - - /// Channel side - @ReadOnly(bits: 2..<3) - var chside: CHSIDE - - /// Transmit buffer empty - @ReadOnly(bits: 1..<2) - var txe: TXE - - /// Receive buffer not empty - @ReadOnly(bits: 0..<1) - var rxne: RXNE - - /// FIFO reception level - @ReadOnly(bits: 9..<11) - var frlvl: FRLVL - - /// FIFO Transmission Level - @ReadOnly(bits: 11..<13) - var ftlvl: FTLVL - } - - /// data register - @Register(bitWidth: 32) - struct DR { - /// Data register - @ReadWrite(bits: 0..<16) - var dr_field: DR_FIELD - } - - /// CRC polynomial register - @Register(bitWidth: 32) - struct CRCPR { - /// CRC polynomial register - @ReadWrite(bits: 0..<16) - var crcpoly: CRCPOLY - } - - /// RX CRC register - @Register(bitWidth: 32) - struct RXCRCR { - /// Rx CRC register - @ReadOnly(bits: 0..<16) - var rxcrc: RxCRC - } - - /// TX CRC register - @Register(bitWidth: 32) - struct TXCRCR { - /// Tx CRC register - @ReadOnly(bits: 0..<16) - var txcrc: TxCRC - } - - /// I2S configuration register - @Register(bitWidth: 32) - struct I2SCFGR { - /// I2S mode selection - @ReadWrite(bits: 11..<12, as: I2SMODValues.self) - var i2smod: I2SMOD - - /// I2S Enable - @ReadWrite(bits: 10..<11, as: I2SEValues.self) - var i2se: I2SE - - /// I2S configuration mode - @ReadWrite(bits: 8..<10, as: I2SCFGValues.self) - var i2scfg: I2SCFG - - /// PCM frame synchronization - @ReadWrite(bits: 7..<8, as: PCMSYNCValues.self) - var pcmsync: PCMSYNC - - /// I2S standard selection - @ReadWrite(bits: 4..<6, as: I2SSTDValues.self) - var i2sstd: I2SSTD - - /// Steady state clock polarity - @ReadWrite(bits: 3..<4, as: CKPOLValues.self) - var ckpol: CKPOL - - /// Data length to be transferred - @ReadWrite(bits: 1..<3, as: DATLENValues.self) - var datlen: DATLEN - - /// Channel length (number of bits per audio channel) - @ReadWrite(bits: 0..<1, as: CHLENValues.self) - var chlen: CHLEN - - /// Asynchronous start enable - @ReadWrite(bits: 12..<13) - var astrten: ASTRTEN - } - - /// I2S prescaler register - @Register(bitWidth: 32) - struct I2SPR { - /// Master clock output enable - @ReadWrite(bits: 9..<10, as: MCKOEValues.self) - var mckoe: MCKOE - - /// Odd factor for the prescaler - @ReadWrite(bits: 8..<9, as: ODDValues.self) - var odd: ODD - - /// I2S Linear prescaler - @ReadWrite(bits: 0..<8) - var i2sdiv: I2SDIV - } -} - -extension SPI1.CR1 { - struct BIDIMODEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// 2-line unidirectional data mode selected - static let Unidirectional = Self(rawValue: 0x0) - - /// 1-line bidirectional data mode selected - static let Bidirectional = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - struct BIDIOEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// Output disabled (receive-only mode) - static let OutputDisabled = Self(rawValue: 0x0) - - /// Output enabled (transmit-only mode) - static let OutputEnabled = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - struct CRCENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// CRC calculation disabled - static let Disabled = Self(rawValue: 0x0) - - /// CRC calculation enabled - static let Enabled = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - struct CRCNEXTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// Next transmit value is from Tx buffer - static let TxBuffer = Self(rawValue: 0x0) - - /// Next transmit value is from Tx CRC register - static let CRC = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - struct CRCLValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// 8-bit CRC length - static let EightBit = Self(rawValue: 0x0) - - /// 16-bit CRC length - static let SixteenBit = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - struct RXONLYValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// Full duplex (Transmit and receive) - static let FullDuplex = Self(rawValue: 0x0) - - /// Output disabled (Receive-only mode) - static let OutputDisabled = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - struct SSMValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// Software slave management disabled - static let Disabled = Self(rawValue: 0x0) - - /// Software slave management enabled - static let Enabled = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - struct SSIValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored - static let SlaveSelected = Self(rawValue: 0x0) - - /// 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored - static let SlaveNotSelected = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - struct LSBFIRSTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// Data is transmitted/received with the MSB first - static let MSBFirst = Self(rawValue: 0x0) - - /// Data is transmitted/received with the LSB first - static let LSBFirst = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - struct SPEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// Peripheral disabled - static let Disabled = Self(rawValue: 0x0) - - /// Peripheral enabled - static let Enabled = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - struct BRValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 3 - - /// f_PCLK / 2 - static let Div2 = Self(rawValue: 0x0) - - /// f_PCLK / 4 - static let Div4 = Self(rawValue: 0x1) - - /// f_PCLK / 8 - static let Div8 = Self(rawValue: 0x2) - - /// f_PCLK / 16 - static let Div16 = Self(rawValue: 0x3) - - /// f_PCLK / 32 - static let Div32 = Self(rawValue: 0x4) - - /// f_PCLK / 64 - static let Div64 = Self(rawValue: 0x5) - - /// f_PCLK / 128 - static let Div128 = Self(rawValue: 0x6) - - /// f_PCLK / 256 - static let Div256 = Self(rawValue: 0x7) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - struct MSTRValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// Slave configuration - static let Slave = Self(rawValue: 0x0) - - /// Master configuration - static let Master = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - struct CPOLValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// CK to 0 when idle - static let IdleLow = Self(rawValue: 0x0) - - /// CK to 1 when idle - static let IdleHigh = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR1 { - struct CPHAValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// The first clock transition is the first data capture edge - static let FirstEdge = Self(rawValue: 0x0) - - /// The second clock transition is the first data capture edge - static let SecondEdge = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - struct RXDMAENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// Rx buffer DMA disabled - static let Disabled = Self(rawValue: 0x0) - - /// Rx buffer DMA enabled - static let Enabled = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - struct TXDMAENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// Tx buffer DMA disabled - static let Disabled = Self(rawValue: 0x0) - - /// Tx buffer DMA enabled - static let Enabled = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - struct SSOEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// SS output is disabled in master mode - static let Disabled = Self(rawValue: 0x0) - - /// SS output is enabled in master mode - static let Enabled = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - struct NSSPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// No NSS pulse - static let NoPulse = Self(rawValue: 0x0) - - /// NSS pulse generated - static let PulseGenerated = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - struct FRFValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// SPI Motorola mode - static let Motorola = Self(rawValue: 0x0) - - /// SPI TI mode - static let TI = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - struct ERRIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// Error interrupt masked - static let Masked = Self(rawValue: 0x0) - - /// Error interrupt not masked - static let NotMasked = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - struct RXNEIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// RXE interrupt masked - static let Masked = Self(rawValue: 0x0) - - /// RXE interrupt not masked - static let NotMasked = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - struct TXEIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// TXE interrupt masked - static let Masked = Self(rawValue: 0x0) - - /// TXE interrupt not masked - static let NotMasked = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - struct DSValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 4 - - /// 4-bit - static let FourBit = Self(rawValue: 0x3) - - /// 5-bit - static let FiveBit = Self(rawValue: 0x4) - - /// 6-bit - static let SixBit = Self(rawValue: 0x5) - - /// 7-bit - static let SevenBit = Self(rawValue: 0x6) - - /// 8-bit - static let EightBit = Self(rawValue: 0x7) - - /// 9-bit - static let NineBit = Self(rawValue: 0x8) - - /// 10-bit - static let TenBit = Self(rawValue: 0x9) - - /// 11-bit - static let ElevenBit = Self(rawValue: 0xa) - - /// 12-bit - static let TwelveBit = Self(rawValue: 0xb) - - /// 13-bit - static let ThirteenBit = Self(rawValue: 0xc) - - /// 14-bit - static let FourteenBit = Self(rawValue: 0xd) - - /// 15-bit - static let FifteenBit = Self(rawValue: 0xe) - - /// 16-bit - static let SixteenBit = Self(rawValue: 0xf) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - struct FRXTHValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) - static let Half = Self(rawValue: 0x0) - - /// RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) - static let Quarter = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - struct LDMA_RXValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// Number of data to transfer for receive is even - static let Even = Self(rawValue: 0x0) - - /// Number of data to transfer for receive is odd - static let Odd = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.CR2 { - struct LDMA_TXValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// Number of data to transfer for transmit is even - static let Even = Self(rawValue: 0x0) - - /// Number of data to transfer for transmit is odd - static let Odd = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.I2SCFGR { - struct I2SMODValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// SPI mode is selected - static let SPIMode = Self(rawValue: 0x0) - - /// I2S mode is selected - static let I2SMode = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.I2SCFGR { - struct I2SEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// I2S peripheral is disabled - static let Disabled = Self(rawValue: 0x0) - - /// I2S peripheral is enabled - static let Enabled = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.I2SCFGR { - struct I2SCFGValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 - - /// Slave - transmit - static let SlaveTx = Self(rawValue: 0x0) - - /// Slave - receive - static let SlaveRx = Self(rawValue: 0x1) - - /// Master - transmit - static let MasterTx = Self(rawValue: 0x2) - - /// Master - receive - static let MasterRx = Self(rawValue: 0x3) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.I2SCFGR { - struct PCMSYNCValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// Short frame synchronisation - static let Short = Self(rawValue: 0x0) - - /// Long frame synchronisation - static let Long = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.I2SCFGR { - struct I2SSTDValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 - - /// I2S Philips standard - static let Philips = Self(rawValue: 0x0) - - /// MSB justified standard - static let MSB = Self(rawValue: 0x1) - - /// LSB justified standard - static let LSB = Self(rawValue: 0x2) - - /// PCM standard - static let PCM = Self(rawValue: 0x3) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.I2SCFGR { - struct CKPOLValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// I2S clock inactive state is low level - static let IdleLow = Self(rawValue: 0x0) - - /// I2S clock inactive state is high level - static let IdleHigh = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.I2SCFGR { - struct DATLENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 - - /// 16-bit data length - static let SixteenBit = Self(rawValue: 0x0) - - /// 24-bit data length - static let TwentyFourBit = Self(rawValue: 0x1) - - /// 32-bit data length - static let ThirtyTwoBit = Self(rawValue: 0x2) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.I2SCFGR { - struct CHLENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// 16-bit wide - static let SixteenBit = Self(rawValue: 0x0) - - /// 32-bit wide - static let ThirtyTwoBit = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.I2SPR { - struct MCKOEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// Master clock output is disabled - static let Disabled = Self(rawValue: 0x0) - - /// Master clock output is enabled - static let Enabled = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} - -extension SPI1.I2SPR { - struct ODDValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 - - /// Real divider value is I2SDIV * 2 - static let Even = Self(rawValue: 0x0) - - /// Real divider value is (I2SDIV * 2) + 1 - static let Odd = Self(rawValue: 0x1) - - var rawValue: UInt8 - - @inlinable @inline(__always) - init(rawValue: Self.RawValue) { - self.rawValue = rawValue - } - } -} diff --git a/stm32-neopixel/Sources/Application/Registers/DMA1.swift b/stm32-neopixel/Sources/STM32F7X6/DMA1.swift similarity index 67% rename from stm32-neopixel/Sources/Application/Registers/DMA1.swift rename to stm32-neopixel/Sources/STM32F7X6/DMA1.swift index 13ca8e33..a8ad2dab 100644 --- a/stm32-neopixel/Sources/Application/Registers/DMA1.swift +++ b/stm32-neopixel/Sources/STM32F7X6/DMA1.swift @@ -3,5 +3,5 @@ import MMIO /// DMA controller -typealias DMA1 = DMA2 +public typealias DMA1 = DMA2 diff --git a/stm32-neopixel/Sources/Application/Registers/DMA2.swift b/stm32-neopixel/Sources/STM32F7X6/DMA2.swift similarity index 61% rename from stm32-neopixel/Sources/Application/Registers/DMA2.swift rename to stm32-neopixel/Sources/STM32F7X6/DMA2.swift index e6b7a6bb..8b61636f 100644 --- a/stm32-neopixel/Sources/Application/Registers/DMA2.swift +++ b/stm32-neopixel/Sources/STM32F7X6/DMA2.swift @@ -4,889 +4,889 @@ import MMIO /// DMA controller @RegisterBlock -struct DMA2 { +public struct DMA2 { /// low interrupt status register @RegisterBlock(offset: 0x0) - var lisr: Register + public var lisr: Register /// high interrupt status register @RegisterBlock(offset: 0x4) - var hisr: Register + public var hisr: Register /// low interrupt flag clear register @RegisterBlock(offset: 0x8) - var lifcr: Register + public var lifcr: Register /// high interrupt flag clear register @RegisterBlock(offset: 0xc) - var hifcr: Register + public var hifcr: Register /// Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers @RegisterBlock(offset: 0x10, stride: 0x18, count: 8) - var st: RegisterArray + public var st: RegisterArray } extension DMA2 { /// low interrupt status register @Register(bitWidth: 32) - struct LISR { + public struct LISR { /// Stream x transfer complete interrupt flag (x = 3..0) @ReadOnly(bits: 27..<28) - var tcif3: TCIF3 + public var tcif3: TCIF3 /// Stream x half transfer interrupt flag (x=3..0) @ReadOnly(bits: 26..<27) - var htif3: HTIF3 + public var htif3: HTIF3 /// Stream x transfer error interrupt flag (x=3..0) @ReadOnly(bits: 25..<26) - var teif3: TEIF3 + public var teif3: TEIF3 /// Stream x direct mode error interrupt flag (x=3..0) @ReadOnly(bits: 24..<25) - var dmeif3: DMEIF3 + public var dmeif3: DMEIF3 /// Stream x FIFO error interrupt flag (x=3..0) @ReadOnly(bits: 22..<23) - var feif3: FEIF3 + public var feif3: FEIF3 /// Stream x transfer complete interrupt flag (x = 3..0) @ReadOnly(bits: 21..<22) - var tcif2: TCIF2 + public var tcif2: TCIF2 /// Stream x half transfer interrupt flag (x=3..0) @ReadOnly(bits: 20..<21) - var htif2: HTIF2 + public var htif2: HTIF2 /// Stream x transfer error interrupt flag (x=3..0) @ReadOnly(bits: 19..<20) - var teif2: TEIF2 + public var teif2: TEIF2 /// Stream x direct mode error interrupt flag (x=3..0) @ReadOnly(bits: 18..<19) - var dmeif2: DMEIF2 + public var dmeif2: DMEIF2 /// Stream x FIFO error interrupt flag (x=3..0) @ReadOnly(bits: 16..<17) - var feif2: FEIF2 + public var feif2: FEIF2 /// Stream x transfer complete interrupt flag (x = 3..0) @ReadOnly(bits: 11..<12) - var tcif1: TCIF1 + public var tcif1: TCIF1 /// Stream x half transfer interrupt flag (x=3..0) @ReadOnly(bits: 10..<11) - var htif1: HTIF1 + public var htif1: HTIF1 /// Stream x transfer error interrupt flag (x=3..0) @ReadOnly(bits: 9..<10) - var teif1: TEIF1 + public var teif1: TEIF1 /// Stream x direct mode error interrupt flag (x=3..0) @ReadOnly(bits: 8..<9) - var dmeif1: DMEIF1 + public var dmeif1: DMEIF1 /// Stream x FIFO error interrupt flag (x=3..0) @ReadOnly(bits: 6..<7) - var feif1: FEIF1 + public var feif1: FEIF1 /// Stream x transfer complete interrupt flag (x = 3..0) @ReadOnly(bits: 5..<6) - var tcif0: TCIF0 + public var tcif0: TCIF0 /// Stream x half transfer interrupt flag (x=3..0) @ReadOnly(bits: 4..<5) - var htif0: HTIF0 + public var htif0: HTIF0 /// Stream x transfer error interrupt flag (x=3..0) @ReadOnly(bits: 3..<4) - var teif0: TEIF0 + public var teif0: TEIF0 /// Stream x direct mode error interrupt flag (x=3..0) @ReadOnly(bits: 2..<3) - var dmeif0: DMEIF0 + public var dmeif0: DMEIF0 /// Stream x FIFO error interrupt flag (x=3..0) @ReadOnly(bits: 0..<1) - var feif0: FEIF0 + public var feif0: FEIF0 } /// high interrupt status register @Register(bitWidth: 32) - struct HISR { + public struct HISR { /// Stream x transfer complete interrupt flag (x=7..4) @ReadOnly(bits: 27..<28) - var tcif7: TCIF7 + public var tcif7: TCIF7 /// Stream x half transfer interrupt flag (x=7..4) @ReadOnly(bits: 26..<27) - var htif7: HTIF7 + public var htif7: HTIF7 /// Stream x transfer error interrupt flag (x=7..4) @ReadOnly(bits: 25..<26) - var teif7: TEIF7 + public var teif7: TEIF7 /// Stream x direct mode error interrupt flag (x=7..4) @ReadOnly(bits: 24..<25) - var dmeif7: DMEIF7 + public var dmeif7: DMEIF7 /// Stream x FIFO error interrupt flag (x=7..4) @ReadOnly(bits: 22..<23) - var feif7: FEIF7 + public var feif7: FEIF7 /// Stream x transfer complete interrupt flag (x=7..4) @ReadOnly(bits: 21..<22) - var tcif6: TCIF6 + public var tcif6: TCIF6 /// Stream x half transfer interrupt flag (x=7..4) @ReadOnly(bits: 20..<21) - var htif6: HTIF6 + public var htif6: HTIF6 /// Stream x transfer error interrupt flag (x=7..4) @ReadOnly(bits: 19..<20) - var teif6: TEIF6 + public var teif6: TEIF6 /// Stream x direct mode error interrupt flag (x=7..4) @ReadOnly(bits: 18..<19) - var dmeif6: DMEIF6 + public var dmeif6: DMEIF6 /// Stream x FIFO error interrupt flag (x=7..4) @ReadOnly(bits: 16..<17) - var feif6: FEIF6 + public var feif6: FEIF6 /// Stream x transfer complete interrupt flag (x=7..4) @ReadOnly(bits: 11..<12) - var tcif5: TCIF5 + public var tcif5: TCIF5 /// Stream x half transfer interrupt flag (x=7..4) @ReadOnly(bits: 10..<11) - var htif5: HTIF5 + public var htif5: HTIF5 /// Stream x transfer error interrupt flag (x=7..4) @ReadOnly(bits: 9..<10) - var teif5: TEIF5 + public var teif5: TEIF5 /// Stream x direct mode error interrupt flag (x=7..4) @ReadOnly(bits: 8..<9) - var dmeif5: DMEIF5 + public var dmeif5: DMEIF5 /// Stream x FIFO error interrupt flag (x=7..4) @ReadOnly(bits: 6..<7) - var feif5: FEIF5 + public var feif5: FEIF5 /// Stream x transfer complete interrupt flag (x=7..4) @ReadOnly(bits: 5..<6) - var tcif4: TCIF4 + public var tcif4: TCIF4 /// Stream x half transfer interrupt flag (x=7..4) @ReadOnly(bits: 4..<5) - var htif4: HTIF4 + public var htif4: HTIF4 /// Stream x transfer error interrupt flag (x=7..4) @ReadOnly(bits: 3..<4) - var teif4: TEIF4 + public var teif4: TEIF4 /// Stream x direct mode error interrupt flag (x=7..4) @ReadOnly(bits: 2..<3) - var dmeif4: DMEIF4 + public var dmeif4: DMEIF4 /// Stream x FIFO error interrupt flag (x=7..4) @ReadOnly(bits: 0..<1) - var feif4: FEIF4 + public var feif4: FEIF4 } /// low interrupt flag clear register @Register(bitWidth: 32) - struct LIFCR { + public struct LIFCR { /// Stream x clear transfer complete interrupt flag (x = 3..0) @WriteOnly(bits: 27..<28) - var ctcif3: CTCIF3 + public var ctcif3: CTCIF3 /// Stream x clear half transfer interrupt flag (x = 3..0) @WriteOnly(bits: 26..<27) - var chtif3: CHTIF3 + public var chtif3: CHTIF3 /// Stream x clear transfer error interrupt flag (x = 3..0) @WriteOnly(bits: 25..<26) - var cteif3: CTEIF3 + public var cteif3: CTEIF3 /// Stream x clear direct mode error interrupt flag (x = 3..0) @WriteOnly(bits: 24..<25) - var cdmeif3: CDMEIF3 + public var cdmeif3: CDMEIF3 /// Stream x clear FIFO error interrupt flag (x = 3..0) @WriteOnly(bits: 22..<23) - var cfeif3: CFEIF3 + public var cfeif3: CFEIF3 /// Stream x clear transfer complete interrupt flag (x = 3..0) @WriteOnly(bits: 21..<22) - var ctcif2: CTCIF2 + public var ctcif2: CTCIF2 /// Stream x clear half transfer interrupt flag (x = 3..0) @WriteOnly(bits: 20..<21) - var chtif2: CHTIF2 + public var chtif2: CHTIF2 /// Stream x clear transfer error interrupt flag (x = 3..0) @WriteOnly(bits: 19..<20) - var cteif2: CTEIF2 + public var cteif2: CTEIF2 /// Stream x clear direct mode error interrupt flag (x = 3..0) @WriteOnly(bits: 18..<19) - var cdmeif2: CDMEIF2 + public var cdmeif2: CDMEIF2 /// Stream x clear FIFO error interrupt flag (x = 3..0) @WriteOnly(bits: 16..<17) - var cfeif2: CFEIF2 + public var cfeif2: CFEIF2 /// Stream x clear transfer complete interrupt flag (x = 3..0) @WriteOnly(bits: 11..<12) - var ctcif1: CTCIF1 + public var ctcif1: CTCIF1 /// Stream x clear half transfer interrupt flag (x = 3..0) @WriteOnly(bits: 10..<11) - var chtif1: CHTIF1 + public var chtif1: CHTIF1 /// Stream x clear transfer error interrupt flag (x = 3..0) @WriteOnly(bits: 9..<10) - var cteif1: CTEIF1 + public var cteif1: CTEIF1 /// Stream x clear direct mode error interrupt flag (x = 3..0) @WriteOnly(bits: 8..<9) - var cdmeif1: CDMEIF1 + public var cdmeif1: CDMEIF1 /// Stream x clear FIFO error interrupt flag (x = 3..0) @WriteOnly(bits: 6..<7) - var cfeif1: CFEIF1 + public var cfeif1: CFEIF1 /// Stream x clear transfer complete interrupt flag (x = 3..0) @WriteOnly(bits: 5..<6) - var ctcif0: CTCIF0 + public var ctcif0: CTCIF0 /// Stream x clear half transfer interrupt flag (x = 3..0) @WriteOnly(bits: 4..<5) - var chtif0: CHTIF0 + public var chtif0: CHTIF0 /// Stream x clear transfer error interrupt flag (x = 3..0) @WriteOnly(bits: 3..<4) - var cteif0: CTEIF0 + public var cteif0: CTEIF0 /// Stream x clear direct mode error interrupt flag (x = 3..0) @WriteOnly(bits: 2..<3) - var cdmeif0: CDMEIF0 + public var cdmeif0: CDMEIF0 /// Stream x clear FIFO error interrupt flag (x = 3..0) @WriteOnly(bits: 0..<1) - var cfeif0: CFEIF0 + public var cfeif0: CFEIF0 } /// high interrupt flag clear register @Register(bitWidth: 32) - struct HIFCR { + public struct HIFCR { /// Stream x clear transfer complete interrupt flag (x = 7..4) @WriteOnly(bits: 27..<28) - var ctcif7: CTCIF7 + public var ctcif7: CTCIF7 /// Stream x clear half transfer interrupt flag (x = 7..4) @WriteOnly(bits: 26..<27) - var chtif7: CHTIF7 + public var chtif7: CHTIF7 /// Stream x clear transfer error interrupt flag (x = 7..4) @WriteOnly(bits: 25..<26) - var cteif7: CTEIF7 + public var cteif7: CTEIF7 /// Stream x clear direct mode error interrupt flag (x = 7..4) @WriteOnly(bits: 24..<25) - var cdmeif7: CDMEIF7 + public var cdmeif7: CDMEIF7 /// Stream x clear FIFO error interrupt flag (x = 7..4) @WriteOnly(bits: 22..<23) - var cfeif7: CFEIF7 + public var cfeif7: CFEIF7 /// Stream x clear transfer complete interrupt flag (x = 7..4) @WriteOnly(bits: 21..<22) - var ctcif6: CTCIF6 + public var ctcif6: CTCIF6 /// Stream x clear half transfer interrupt flag (x = 7..4) @WriteOnly(bits: 20..<21) - var chtif6: CHTIF6 + public var chtif6: CHTIF6 /// Stream x clear transfer error interrupt flag (x = 7..4) @WriteOnly(bits: 19..<20) - var cteif6: CTEIF6 + public var cteif6: CTEIF6 /// Stream x clear direct mode error interrupt flag (x = 7..4) @WriteOnly(bits: 18..<19) - var cdmeif6: CDMEIF6 + public var cdmeif6: CDMEIF6 /// Stream x clear FIFO error interrupt flag (x = 7..4) @WriteOnly(bits: 16..<17) - var cfeif6: CFEIF6 + public var cfeif6: CFEIF6 /// Stream x clear transfer complete interrupt flag (x = 7..4) @WriteOnly(bits: 11..<12) - var ctcif5: CTCIF5 + public var ctcif5: CTCIF5 /// Stream x clear half transfer interrupt flag (x = 7..4) @WriteOnly(bits: 10..<11) - var chtif5: CHTIF5 + public var chtif5: CHTIF5 /// Stream x clear transfer error interrupt flag (x = 7..4) @WriteOnly(bits: 9..<10) - var cteif5: CTEIF5 + public var cteif5: CTEIF5 /// Stream x clear direct mode error interrupt flag (x = 7..4) @WriteOnly(bits: 8..<9) - var cdmeif5: CDMEIF5 + public var cdmeif5: CDMEIF5 /// Stream x clear FIFO error interrupt flag (x = 7..4) @WriteOnly(bits: 6..<7) - var cfeif5: CFEIF5 + public var cfeif5: CFEIF5 /// Stream x clear transfer complete interrupt flag (x = 7..4) @WriteOnly(bits: 5..<6) - var ctcif4: CTCIF4 + public var ctcif4: CTCIF4 /// Stream x clear half transfer interrupt flag (x = 7..4) @WriteOnly(bits: 4..<5) - var chtif4: CHTIF4 + public var chtif4: CHTIF4 /// Stream x clear transfer error interrupt flag (x = 7..4) @WriteOnly(bits: 3..<4) - var cteif4: CTEIF4 + public var cteif4: CTEIF4 /// Stream x clear direct mode error interrupt flag (x = 7..4) @WriteOnly(bits: 2..<3) - var cdmeif4: CDMEIF4 + public var cdmeif4: CDMEIF4 /// Stream x clear FIFO error interrupt flag (x = 7..4) @WriteOnly(bits: 0..<1) - var cfeif4: CFEIF4 + public var cfeif4: CFEIF4 } /// Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers @RegisterBlock - struct ST { + public struct ST { /// stream x configuration register @RegisterBlock(offset: 0x0) - var cr: Register + public var cr: Register /// stream x number of data register @RegisterBlock(offset: 0x4) - var ndtr: Register + public var ndtr: Register /// stream x peripheral address register @RegisterBlock(offset: 0x8) - var par: Register + public var par: Register /// stream x memory 0 address register @RegisterBlock(offset: 0xc) - var m0ar: Register + public var m0ar: Register /// stream x memory 1 address register @RegisterBlock(offset: 0x10) - var m1ar: Register + public var m1ar: Register /// stream x FIFO control register @RegisterBlock(offset: 0x14) - var fcr: Register + public var fcr: Register } } extension DMA2.ST { /// stream x configuration register @Register(bitWidth: 32) - struct CR { + public struct CR { /// Channel selection @ReadWrite(bits: 25..<28) - var chsel: CHSEL + public var chsel: CHSEL /// Memory burst transfer configuration @ReadWrite(bits: 23..<25) - var mburst: MBURST + public var mburst: MBURST /// Peripheral burst transfer configuration @ReadWrite(bits: 21..<23, as: PBURSTValues.self) - var pburst: PBURST + public var pburst: PBURST /// Current target (only in double buffer mode) @ReadWrite(bits: 19..<20, as: CTValues.self) - var ct: CT + public var ct: CT /// Double buffer mode @ReadWrite(bits: 18..<19, as: DBMValues.self) - var dbm: DBM + public var dbm: DBM /// Priority level @ReadWrite(bits: 16..<18, as: PLValues.self) - var pl: PL + public var pl: PL /// Peripheral increment offset size @ReadWrite(bits: 15..<16, as: PINCOSValues.self) - var pincos: PINCOS + public var pincos: PINCOS /// Memory data size @ReadWrite(bits: 13..<15) - var msize: MSIZE + public var msize: MSIZE /// Peripheral data size @ReadWrite(bits: 11..<13, as: PSIZEValues.self) - var psize: PSIZE + public var psize: PSIZE /// Memory increment mode @ReadWrite(bits: 10..<11) - var minc: MINC + public var minc: MINC /// Peripheral increment mode @ReadWrite(bits: 9..<10, as: PINCValues.self) - var pinc: PINC + public var pinc: PINC /// Circular mode @ReadWrite(bits: 8..<9, as: CIRCValues.self) - var circ: CIRC + public var circ: CIRC /// Data transfer direction @ReadWrite(bits: 6..<8, as: DIRValues.self) - var dir: DIR + public var dir: DIR /// Peripheral flow controller @ReadWrite(bits: 5..<6, as: PFCTRLValues.self) - var pfctrl: PFCTRL + public var pfctrl: PFCTRL /// Transfer complete interrupt enable @ReadWrite(bits: 4..<5, as: TCIEValues.self) - var tcie: TCIE + public var tcie: TCIE /// Half transfer interrupt enable @ReadWrite(bits: 3..<4, as: HTIEValues.self) - var htie: HTIE + public var htie: HTIE /// Transfer error interrupt enable @ReadWrite(bits: 2..<3, as: TEIEValues.self) - var teie: TEIE + public var teie: TEIE /// Direct mode error interrupt enable @ReadWrite(bits: 1..<2, as: DMEIEValues.self) - var dmeie: DMEIE + public var dmeie: DMEIE /// Stream enable / flag stream ready when read low @ReadWrite(bits: 0..<1, as: ENValues.self) - var en: EN + public var en: EN } /// stream x number of data register @Register(bitWidth: 32) - struct NDTR { + public struct NDTR { /// Number of data items to transfer @ReadWrite(bits: 0..<16) - var ndt: NDT + public var ndt: NDT } /// stream x peripheral address register @Register(bitWidth: 32) - struct PAR { + public struct PAR { /// Peripheral address @ReadWrite(bits: 0..<32) - var pa: PA + public var pa: PA } /// stream x memory 0 address register @Register(bitWidth: 32) - struct M0AR { + public struct M0AR { /// Memory 0 address @ReadWrite(bits: 0..<32) - var m0a: M0A + public var m0a: M0A } /// stream x memory 1 address register @Register(bitWidth: 32) - struct M1AR { + public struct M1AR { /// Memory 1 address (used in case of Double buffer mode) @ReadWrite(bits: 0..<32) - var m1a: M1A + public var m1a: M1A } /// stream x FIFO control register @Register(bitWidth: 32) - struct FCR { + public struct FCR { /// FIFO error interrupt enable @ReadWrite(bits: 7..<8, as: FEIEValues.self) - var feie: FEIE + public var feie: FEIE /// FIFO status @ReadOnly(bits: 3..<6) - var fs: FS + public var fs: FS /// Direct mode disable @ReadWrite(bits: 2..<3, as: DMDISValues.self) - var dmdis: DMDIS + public var dmdis: DMDIS /// FIFO threshold selection @ReadWrite(bits: 0..<2, as: FTHValues.self) - var fth: FTH + public var fth: FTH } } extension DMA2.ST.CR { - struct PBURSTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct PBURSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// Single transfer - static let Single = Self(rawValue: 0x0) + public static let Single = Self(rawValue: 0x0) /// Incremental burst of 4 beats - static let INCR4 = Self(rawValue: 0x1) + public static let INCR4 = Self(rawValue: 0x1) /// Incremental burst of 8 beats - static let INCR8 = Self(rawValue: 0x2) + public static let INCR8 = Self(rawValue: 0x2) /// Incremental burst of 16 beats - static let INCR16 = Self(rawValue: 0x3) + public static let INCR16 = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension DMA2.ST.CR { - struct CTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// The current target memory is Memory 0 - static let Memory0 = Self(rawValue: 0x0) + public static let Memory0 = Self(rawValue: 0x0) /// The current target memory is Memory 1 - static let Memory1 = Self(rawValue: 0x1) + public static let Memory1 = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension DMA2.ST.CR { - struct DBMValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DBMValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// No buffer switching at the end of transfer - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Memory target switched at the end of the DMA transfer - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension DMA2.ST.CR { - struct PLValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct PLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// Low - static let Low = Self(rawValue: 0x0) + public static let Low = Self(rawValue: 0x0) /// Medium - static let Medium = Self(rawValue: 0x1) + public static let Medium = Self(rawValue: 0x1) /// High - static let High = Self(rawValue: 0x2) + public static let High = Self(rawValue: 0x2) /// Very high - static let VeryHigh = Self(rawValue: 0x3) + public static let VeryHigh = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension DMA2.ST.CR { - struct PINCOSValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct PINCOSValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// The offset size for the peripheral address calculation is linked to the PSIZE - static let PSIZE = Self(rawValue: 0x0) + public static let PSIZE = Self(rawValue: 0x0) /// The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment) - static let Fixed4 = Self(rawValue: 0x1) + public static let Fixed4 = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension DMA2.ST.CR { - struct PSIZEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct PSIZEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// Byte (8-bit) - static let Bits8 = Self(rawValue: 0x0) + public static let Bits8 = Self(rawValue: 0x0) /// Half-word (16-bit) - static let Bits16 = Self(rawValue: 0x1) + public static let Bits16 = Self(rawValue: 0x1) /// Word (32-bit) - static let Bits32 = Self(rawValue: 0x2) + public static let Bits32 = Self(rawValue: 0x2) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension DMA2.ST.CR { - struct PINCValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct PINCValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Address pointer is fixed - static let Fixed = Self(rawValue: 0x0) + public static let Fixed = Self(rawValue: 0x0) /// Address pointer is incremented after each data transfer - static let Incremented = Self(rawValue: 0x1) + public static let Incremented = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension DMA2.ST.CR { - struct CIRCValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CIRCValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Circular mode disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Circular mode enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension DMA2.ST.CR { - struct DIRValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct DIRValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// Peripheral-to-memory - static let PeripheralToMemory = Self(rawValue: 0x0) + public static let PeripheralToMemory = Self(rawValue: 0x0) /// Memory-to-peripheral - static let MemoryToPeripheral = Self(rawValue: 0x1) + public static let MemoryToPeripheral = Self(rawValue: 0x1) /// Memory-to-memory - static let MemoryToMemory = Self(rawValue: 0x2) + public static let MemoryToMemory = Self(rawValue: 0x2) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension DMA2.ST.CR { - struct PFCTRLValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct PFCTRLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// The DMA is the flow controller - static let DMA = Self(rawValue: 0x0) + public static let DMA = Self(rawValue: 0x0) /// The peripheral is the flow controller - static let Peripheral = Self(rawValue: 0x1) + public static let Peripheral = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension DMA2.ST.CR { - struct TCIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TCIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// TC interrupt disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// TC interrupt enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension DMA2.ST.CR { - struct HTIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct HTIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// HT interrupt disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// HT interrupt enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension DMA2.ST.CR { - struct TEIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TEIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// TE interrupt disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// TE interrupt enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension DMA2.ST.CR { - struct DMEIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DMEIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// DME interrupt disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// DME interrupt enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension DMA2.ST.CR { - struct ENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct ENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Stream disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Stream enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension DMA2.ST.FCR { - struct FEIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct FEIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// FE interrupt disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// FE interrupt enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension DMA2.ST.FCR { - struct DMDISValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DMDISValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Direct mode is enabled - static let Enabled = Self(rawValue: 0x0) + public static let Enabled = Self(rawValue: 0x0) /// Direct mode is disabled - static let Disabled = Self(rawValue: 0x1) + public static let Disabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension DMA2.ST.FCR { - struct FTHValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct FTHValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// 1/4 full FIFO - static let Quarter = Self(rawValue: 0x0) + public static let Quarter = Self(rawValue: 0x0) /// 1/2 full FIFO - static let Half = Self(rawValue: 0x1) + public static let Half = Self(rawValue: 0x1) /// 3/4 full FIFO - static let ThreeQuarters = Self(rawValue: 0x2) + public static let ThreeQuarters = Self(rawValue: 0x2) /// Full FIFO - static let Full = Self(rawValue: 0x3) + public static let Full = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } diff --git a/stm32-neopixel/Sources/STM32F7X6/Device.swift b/stm32-neopixel/Sources/STM32F7X6/Device.swift new file mode 100644 index 00000000..58cb586c --- /dev/null +++ b/stm32-neopixel/Sources/STM32F7X6/Device.swift @@ -0,0 +1,30 @@ +// Generated by svd2swift. + +import MMIO + +/// DMA controller +public let dma1 = DMA1(unsafeAddress: 0x40026000) + +/// DMA controller +public let dma2 = DMA2(unsafeAddress: 0x40026400) + +/// General-purpose I/Os +public let gpioa = GPIOA(unsafeAddress: 0x40020000) + +/// General-purpose I/Os +public let gpiob = GPIOB(unsafeAddress: 0x40020400) + +/// General-purpose I/Os +public let gpioi = GPIOI(unsafeAddress: 0x40022000) + +/// Reset and clock control +public let rcc = RCC(unsafeAddress: 0x40023800) + +/// Serial peripheral interface +public let spi1 = SPI1(unsafeAddress: 0x40013000) + +/// Serial peripheral interface +public let spi2 = SPI2(unsafeAddress: 0x40003800) + +/// Universal synchronous asynchronous receiver transmitter +public let usart1 = USART1(unsafeAddress: 0x40011000) diff --git a/stm32-neopixel/Sources/STM32F7X6/Empty.swift b/stm32-neopixel/Sources/STM32F7X6/Empty.swift new file mode 100644 index 00000000..934a795a --- /dev/null +++ b/stm32-neopixel/Sources/STM32F7X6/Empty.swift @@ -0,0 +1,13 @@ +//===----------------------------------------------------------------------===// +// +// This source file is part of the Swift open source project +// +// Copyright (c) 2024 Apple Inc. and the Swift project authors. +// Licensed under Apache License v2.0 with Runtime Library Exception +// +// See https://swift.org/LICENSE.txt for license information +// +//===----------------------------------------------------------------------===// + +// This file is intentionally left empty for SwiftPM to recognize the target as +// a Swift source module. diff --git a/stm32-lcd-logo/Sources/Application/Registers/GPIOA.swift b/stm32-neopixel/Sources/STM32F7X6/GPIOA.swift similarity index 62% rename from stm32-lcd-logo/Sources/Application/Registers/GPIOA.swift rename to stm32-neopixel/Sources/STM32F7X6/GPIOA.swift index 3bc4d2ff..a70e68c7 100644 --- a/stm32-lcd-logo/Sources/Application/Registers/GPIOA.swift +++ b/stm32-neopixel/Sources/STM32F7X6/GPIOA.swift @@ -4,1071 +4,1071 @@ import MMIO /// General-purpose I/Os @RegisterBlock -struct GPIOA { +public struct GPIOA { /// GPIO port mode register @RegisterBlock(offset: 0x0) - var moder: Register + public var moder: Register /// GPIO port output type register @RegisterBlock(offset: 0x4) - var otyper: Register + public var otyper: Register /// GPIO port output speed register @RegisterBlock(offset: 0x8) - var ospeedr: Register + public var ospeedr: Register /// GPIO port pull-up/pull-down register @RegisterBlock(offset: 0xc) - var pupdr: Register + public var pupdr: Register /// GPIO port input data register @RegisterBlock(offset: 0x10) - var idr: Register + public var idr: Register /// GPIO port output data register @RegisterBlock(offset: 0x14) - var odr: Register + public var odr: Register /// GPIO port bit set/reset register @RegisterBlock(offset: 0x18) - var bsrr: Register + public var bsrr: Register /// GPIO port configuration lock register @RegisterBlock(offset: 0x1c) - var lckr: Register + public var lckr: Register /// GPIO alternate function low register @RegisterBlock(offset: 0x20) - var afrl: Register + public var afrl: Register /// GPIO alternate function high register @RegisterBlock(offset: 0x24) - var afrh: Register + public var afrh: Register /// GPIO port bit reset register @RegisterBlock(offset: 0x28) - var brr: Register + public var brr: Register } extension GPIOA { /// GPIO port mode register @Register(bitWidth: 32) - struct MODER { + public struct MODER { /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 30..<32) - var moder15: MODER15 + public var moder15: MODER15 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 28..<30) - var moder14: MODER14 + public var moder14: MODER14 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 26..<28) - var moder13: MODER13 + public var moder13: MODER13 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 24..<26) - var moder12: MODER12 + public var moder12: MODER12 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 22..<24) - var moder11: MODER11 + public var moder11: MODER11 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 20..<22) - var moder10: MODER10 + public var moder10: MODER10 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 18..<20) - var moder9: MODER9 + public var moder9: MODER9 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 16..<18) - var moder8: MODER8 + public var moder8: MODER8 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 14..<16) - var moder7: MODER7 + public var moder7: MODER7 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 12..<14) - var moder6: MODER6 + public var moder6: MODER6 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 10..<12) - var moder5: MODER5 + public var moder5: MODER5 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 8..<10) - var moder4: MODER4 + public var moder4: MODER4 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 6..<8) - var moder3: MODER3 + public var moder3: MODER3 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 4..<6) - var moder2: MODER2 + public var moder2: MODER2 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 2..<4) - var moder1: MODER1 + public var moder1: MODER1 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 0..<2, as: MODER0Values.self) - var moder0: MODER0 + public var moder0: MODER0 } /// GPIO port output type register @Register(bitWidth: 32) - struct OTYPER { + public struct OTYPER { /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 15..<16) - var ot15: OT15 + public var ot15: OT15 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 14..<15) - var ot14: OT14 + public var ot14: OT14 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 13..<14) - var ot13: OT13 + public var ot13: OT13 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 12..<13) - var ot12: OT12 + public var ot12: OT12 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 11..<12) - var ot11: OT11 + public var ot11: OT11 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 10..<11) - var ot10: OT10 + public var ot10: OT10 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 9..<10) - var ot9: OT9 + public var ot9: OT9 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 8..<9) - var ot8: OT8 + public var ot8: OT8 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 7..<8) - var ot7: OT7 + public var ot7: OT7 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 6..<7) - var ot6: OT6 + public var ot6: OT6 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 5..<6) - var ot5: OT5 + public var ot5: OT5 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 4..<5) - var ot4: OT4 + public var ot4: OT4 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 3..<4) - var ot3: OT3 + public var ot3: OT3 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 2..<3) - var ot2: OT2 + public var ot2: OT2 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 1..<2) - var ot1: OT1 + public var ot1: OT1 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 0..<1, as: OT0Values.self) - var ot0: OT0 + public var ot0: OT0 } /// GPIO port output speed register @Register(bitWidth: 32) - struct OSPEEDR { + public struct OSPEEDR { /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 30..<32) - var ospeedr15: OSPEEDR15 + public var ospeedr15: OSPEEDR15 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 28..<30) - var ospeedr14: OSPEEDR14 + public var ospeedr14: OSPEEDR14 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 26..<28) - var ospeedr13: OSPEEDR13 + public var ospeedr13: OSPEEDR13 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 24..<26) - var ospeedr12: OSPEEDR12 + public var ospeedr12: OSPEEDR12 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 22..<24) - var ospeedr11: OSPEEDR11 + public var ospeedr11: OSPEEDR11 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 20..<22) - var ospeedr10: OSPEEDR10 + public var ospeedr10: OSPEEDR10 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 18..<20) - var ospeedr9: OSPEEDR9 + public var ospeedr9: OSPEEDR9 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 16..<18) - var ospeedr8: OSPEEDR8 + public var ospeedr8: OSPEEDR8 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 14..<16) - var ospeedr7: OSPEEDR7 + public var ospeedr7: OSPEEDR7 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 12..<14) - var ospeedr6: OSPEEDR6 + public var ospeedr6: OSPEEDR6 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 10..<12) - var ospeedr5: OSPEEDR5 + public var ospeedr5: OSPEEDR5 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 8..<10) - var ospeedr4: OSPEEDR4 + public var ospeedr4: OSPEEDR4 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 6..<8) - var ospeedr3: OSPEEDR3 + public var ospeedr3: OSPEEDR3 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 4..<6) - var ospeedr2: OSPEEDR2 + public var ospeedr2: OSPEEDR2 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 2..<4) - var ospeedr1: OSPEEDR1 + public var ospeedr1: OSPEEDR1 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 0..<2, as: OSPEEDR0Values.self) - var ospeedr0: OSPEEDR0 + public var ospeedr0: OSPEEDR0 } /// GPIO port pull-up/pull-down register @Register(bitWidth: 32) - struct PUPDR { + public struct PUPDR { /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 30..<32) - var pupdr15: PUPDR15 + public var pupdr15: PUPDR15 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 28..<30) - var pupdr14: PUPDR14 + public var pupdr14: PUPDR14 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 26..<28) - var pupdr13: PUPDR13 + public var pupdr13: PUPDR13 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 24..<26) - var pupdr12: PUPDR12 + public var pupdr12: PUPDR12 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 22..<24) - var pupdr11: PUPDR11 + public var pupdr11: PUPDR11 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 20..<22) - var pupdr10: PUPDR10 + public var pupdr10: PUPDR10 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 18..<20) - var pupdr9: PUPDR9 + public var pupdr9: PUPDR9 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 16..<18) - var pupdr8: PUPDR8 + public var pupdr8: PUPDR8 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 14..<16) - var pupdr7: PUPDR7 + public var pupdr7: PUPDR7 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 12..<14) - var pupdr6: PUPDR6 + public var pupdr6: PUPDR6 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 10..<12) - var pupdr5: PUPDR5 + public var pupdr5: PUPDR5 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 8..<10) - var pupdr4: PUPDR4 + public var pupdr4: PUPDR4 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 6..<8) - var pupdr3: PUPDR3 + public var pupdr3: PUPDR3 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 4..<6) - var pupdr2: PUPDR2 + public var pupdr2: PUPDR2 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 2..<4) - var pupdr1: PUPDR1 + public var pupdr1: PUPDR1 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 0..<2, as: PUPDR0Values.self) - var pupdr0: PUPDR0 + public var pupdr0: PUPDR0 } /// GPIO port input data register @Register(bitWidth: 32) - struct IDR { + public struct IDR { /// Port input data (y = 0..15) @ReadOnly(bits: 15..<16) - var idr15: IDR15 + public var idr15: IDR15 /// Port input data (y = 0..15) @ReadOnly(bits: 14..<15) - var idr14: IDR14 + public var idr14: IDR14 /// Port input data (y = 0..15) @ReadOnly(bits: 13..<14) - var idr13: IDR13 + public var idr13: IDR13 /// Port input data (y = 0..15) @ReadOnly(bits: 12..<13) - var idr12: IDR12 + public var idr12: IDR12 /// Port input data (y = 0..15) @ReadOnly(bits: 11..<12) - var idr11: IDR11 + public var idr11: IDR11 /// Port input data (y = 0..15) @ReadOnly(bits: 10..<11) - var idr10: IDR10 + public var idr10: IDR10 /// Port input data (y = 0..15) @ReadOnly(bits: 9..<10) - var idr9: IDR9 + public var idr9: IDR9 /// Port input data (y = 0..15) @ReadOnly(bits: 8..<9) - var idr8: IDR8 + public var idr8: IDR8 /// Port input data (y = 0..15) @ReadOnly(bits: 7..<8) - var idr7: IDR7 + public var idr7: IDR7 /// Port input data (y = 0..15) @ReadOnly(bits: 6..<7) - var idr6: IDR6 + public var idr6: IDR6 /// Port input data (y = 0..15) @ReadOnly(bits: 5..<6) - var idr5: IDR5 + public var idr5: IDR5 /// Port input data (y = 0..15) @ReadOnly(bits: 4..<5) - var idr4: IDR4 + public var idr4: IDR4 /// Port input data (y = 0..15) @ReadOnly(bits: 3..<4) - var idr3: IDR3 + public var idr3: IDR3 /// Port input data (y = 0..15) @ReadOnly(bits: 2..<3) - var idr2: IDR2 + public var idr2: IDR2 /// Port input data (y = 0..15) @ReadOnly(bits: 1..<2) - var idr1: IDR1 + public var idr1: IDR1 /// Port input data (y = 0..15) @ReadOnly(bits: 0..<1) - var idr0: IDR0 + public var idr0: IDR0 } /// GPIO port output data register @Register(bitWidth: 32) - struct ODR { + public struct ODR { /// Port output data (y = 0..15) @ReadWrite(bits: 15..<16) - var odr15: ODR15 + public var odr15: ODR15 /// Port output data (y = 0..15) @ReadWrite(bits: 14..<15) - var odr14: ODR14 + public var odr14: ODR14 /// Port output data (y = 0..15) @ReadWrite(bits: 13..<14) - var odr13: ODR13 + public var odr13: ODR13 /// Port output data (y = 0..15) @ReadWrite(bits: 12..<13) - var odr12: ODR12 + public var odr12: ODR12 /// Port output data (y = 0..15) @ReadWrite(bits: 11..<12) - var odr11: ODR11 + public var odr11: ODR11 /// Port output data (y = 0..15) @ReadWrite(bits: 10..<11) - var odr10: ODR10 + public var odr10: ODR10 /// Port output data (y = 0..15) @ReadWrite(bits: 9..<10) - var odr9: ODR9 + public var odr9: ODR9 /// Port output data (y = 0..15) @ReadWrite(bits: 8..<9) - var odr8: ODR8 + public var odr8: ODR8 /// Port output data (y = 0..15) @ReadWrite(bits: 7..<8) - var odr7: ODR7 + public var odr7: ODR7 /// Port output data (y = 0..15) @ReadWrite(bits: 6..<7) - var odr6: ODR6 + public var odr6: ODR6 /// Port output data (y = 0..15) @ReadWrite(bits: 5..<6) - var odr5: ODR5 + public var odr5: ODR5 /// Port output data (y = 0..15) @ReadWrite(bits: 4..<5) - var odr4: ODR4 + public var odr4: ODR4 /// Port output data (y = 0..15) @ReadWrite(bits: 3..<4) - var odr3: ODR3 + public var odr3: ODR3 /// Port output data (y = 0..15) @ReadWrite(bits: 2..<3) - var odr2: ODR2 + public var odr2: ODR2 /// Port output data (y = 0..15) @ReadWrite(bits: 1..<2) - var odr1: ODR1 + public var odr1: ODR1 /// Port output data (y = 0..15) @ReadWrite(bits: 0..<1, as: ODR0Values.self) - var odr0: ODR0 + public var odr0: ODR0 } /// GPIO port bit set/reset register @Register(bitWidth: 32) - struct BSRR { + public struct BSRR { /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 31..<32) - var br15: BR15 + public var br15: BR15 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 30..<31) - var br14: BR14 + public var br14: BR14 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 29..<30) - var br13: BR13 + public var br13: BR13 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 28..<29) - var br12: BR12 + public var br12: BR12 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 27..<28) - var br11: BR11 + public var br11: BR11 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 26..<27) - var br10: BR10 + public var br10: BR10 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 25..<26) - var br9: BR9 + public var br9: BR9 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 24..<25) - var br8: BR8 + public var br8: BR8 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 23..<24) - var br7: BR7 + public var br7: BR7 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 22..<23) - var br6: BR6 + public var br6: BR6 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 21..<22) - var br5: BR5 + public var br5: BR5 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 20..<21) - var br4: BR4 + public var br4: BR4 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 19..<20) - var br3: BR3 + public var br3: BR3 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 18..<19) - var br2: BR2 + public var br2: BR2 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 17..<18) - var br1: BR1 + public var br1: BR1 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 16..<17) - var br0: BR0 + public var br0: BR0 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 15..<16) - var bs15: BS15 + public var bs15: BS15 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 14..<15) - var bs14: BS14 + public var bs14: BS14 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 13..<14) - var bs13: BS13 + public var bs13: BS13 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 12..<13) - var bs12: BS12 + public var bs12: BS12 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 11..<12) - var bs11: BS11 + public var bs11: BS11 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 10..<11) - var bs10: BS10 + public var bs10: BS10 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 9..<10) - var bs9: BS9 + public var bs9: BS9 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 8..<9) - var bs8: BS8 + public var bs8: BS8 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 7..<8) - var bs7: BS7 + public var bs7: BS7 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 6..<7) - var bs6: BS6 + public var bs6: BS6 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 5..<6) - var bs5: BS5 + public var bs5: BS5 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 4..<5) - var bs4: BS4 + public var bs4: BS4 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 3..<4) - var bs3: BS3 + public var bs3: BS3 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 2..<3) - var bs2: BS2 + public var bs2: BS2 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 1..<2) - var bs1: BS1 + public var bs1: BS1 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 0..<1) - var bs0: BS0 + public var bs0: BS0 } /// GPIO port configuration lock register @Register(bitWidth: 32) - struct LCKR { + public struct LCKR { /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 16..<17, as: LCKKValues.self) - var lckk: LCKK + public var lckk: LCKK /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 15..<16) - var lck15: LCK15 + public var lck15: LCK15 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 14..<15) - var lck14: LCK14 + public var lck14: LCK14 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 13..<14) - var lck13: LCK13 + public var lck13: LCK13 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 12..<13) - var lck12: LCK12 + public var lck12: LCK12 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 11..<12) - var lck11: LCK11 + public var lck11: LCK11 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 10..<11) - var lck10: LCK10 + public var lck10: LCK10 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 9..<10) - var lck9: LCK9 + public var lck9: LCK9 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 8..<9) - var lck8: LCK8 + public var lck8: LCK8 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 7..<8) - var lck7: LCK7 + public var lck7: LCK7 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 6..<7) - var lck6: LCK6 + public var lck6: LCK6 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 5..<6) - var lck5: LCK5 + public var lck5: LCK5 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 4..<5) - var lck4: LCK4 + public var lck4: LCK4 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 3..<4) - var lck3: LCK3 + public var lck3: LCK3 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 2..<3) - var lck2: LCK2 + public var lck2: LCK2 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 1..<2) - var lck1: LCK1 + public var lck1: LCK1 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 0..<1, as: LCK0Values.self) - var lck0: LCK0 + public var lck0: LCK0 } /// GPIO alternate function low register @Register(bitWidth: 32) - struct AFRL { + public struct AFRL { /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 28..<32) - var afrl7: AFRL7 + public var afrl7: AFRL7 /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 24..<28) - var afrl6: AFRL6 + public var afrl6: AFRL6 /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 20..<24) - var afrl5: AFRL5 + public var afrl5: AFRL5 /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 16..<20) - var afrl4: AFRL4 + public var afrl4: AFRL4 /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 12..<16) - var afrl3: AFRL3 + public var afrl3: AFRL3 /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 8..<12) - var afrl2: AFRL2 + public var afrl2: AFRL2 /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 4..<8) - var afrl1: AFRL1 + public var afrl1: AFRL1 /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 0..<4, as: AFRL0Values.self) - var afrl0: AFRL0 + public var afrl0: AFRL0 } /// GPIO alternate function high register @Register(bitWidth: 32) - struct AFRH { + public struct AFRH { /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 28..<32) - var afrh15: AFRH15 + public var afrh15: AFRH15 /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 24..<28) - var afrh14: AFRH14 + public var afrh14: AFRH14 /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 20..<24) - var afrh13: AFRH13 + public var afrh13: AFRH13 /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 16..<20) - var afrh12: AFRH12 + public var afrh12: AFRH12 /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 12..<16) - var afrh11: AFRH11 + public var afrh11: AFRH11 /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 8..<12) - var afrh10: AFRH10 + public var afrh10: AFRH10 /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 4..<8) - var afrh9: AFRH9 + public var afrh9: AFRH9 /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 0..<4, as: AFRH8Values.self) - var afrh8: AFRH8 + public var afrh8: AFRH8 } /// GPIO port bit reset register @Register(bitWidth: 32) - struct BRR { + public struct BRR { /// Port A Reset bit 0 @ReadWrite(bits: 0..<1) - var br0: BR0 + public var br0: BR0 /// Port A Reset bit 1 @ReadWrite(bits: 1..<2) - var br1: BR1 + public var br1: BR1 /// Port A Reset bit 2 @ReadWrite(bits: 2..<3) - var br2: BR2 + public var br2: BR2 /// Port A Reset bit 3 @ReadWrite(bits: 3..<4) - var br3: BR3 + public var br3: BR3 /// Port A Reset bit 4 @ReadWrite(bits: 4..<5) - var br4: BR4 + public var br4: BR4 /// Port A Reset bit 5 @ReadWrite(bits: 5..<6) - var br5: BR5 + public var br5: BR5 /// Port A Reset bit 6 @ReadWrite(bits: 6..<7) - var br6: BR6 + public var br6: BR6 /// Port A Reset bit 7 @ReadWrite(bits: 7..<8) - var br7: BR7 + public var br7: BR7 /// Port A Reset bit 8 @ReadWrite(bits: 8..<9) - var br8: BR8 + public var br8: BR8 /// Port A Reset bit 9 @ReadWrite(bits: 9..<10) - var br9: BR9 + public var br9: BR9 /// Port A Reset bit 10 @ReadWrite(bits: 10..<11) - var br10: BR10 + public var br10: BR10 /// Port A Reset bit 11 @ReadWrite(bits: 11..<12) - var br11: BR11 + public var br11: BR11 /// Port A Reset bit 12 @ReadWrite(bits: 12..<13) - var br12: BR12 + public var br12: BR12 /// Port A Reset bit 13 @ReadWrite(bits: 13..<14) - var br13: BR13 + public var br13: BR13 /// Port A Reset bit 14 @ReadWrite(bits: 14..<15) - var br14: BR14 + public var br14: BR14 /// Port A Reset bit 15 @ReadWrite(bits: 15..<16) - var br15: BR15 + public var br15: BR15 } } extension GPIOA.MODER { - struct MODER0Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct MODER0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// Input mode (reset state) - static let Input = Self(rawValue: 0x0) + public static let Input = Self(rawValue: 0x0) /// General purpose output mode - static let Output = Self(rawValue: 0x1) + public static let Output = Self(rawValue: 0x1) /// Alternate function mode - static let Alternate = Self(rawValue: 0x2) + public static let Alternate = Self(rawValue: 0x2) /// Analog mode - static let Analog = Self(rawValue: 0x3) + public static let Analog = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.OTYPER { - struct OT0Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct OT0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Output push-pull (reset state) - static let PushPull = Self(rawValue: 0x0) + public static let PushPull = Self(rawValue: 0x0) /// Output open-drain - static let OpenDrain = Self(rawValue: 0x1) + public static let OpenDrain = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.OSPEEDR { - struct OSPEEDR0Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct OSPEEDR0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// Low speed - static let LowSpeed = Self(rawValue: 0x0) + public static let LowSpeed = Self(rawValue: 0x0) /// Medium speed - static let MediumSpeed = Self(rawValue: 0x1) + public static let MediumSpeed = Self(rawValue: 0x1) /// High speed - static let HighSpeed = Self(rawValue: 0x2) + public static let HighSpeed = Self(rawValue: 0x2) /// Very high speed - static let VeryHighSpeed = Self(rawValue: 0x3) + public static let VeryHighSpeed = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.PUPDR { - struct PUPDR0Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct PUPDR0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// No pull-up, pull-down - static let Floating = Self(rawValue: 0x0) + public static let Floating = Self(rawValue: 0x0) /// Pull-up - static let PullUp = Self(rawValue: 0x1) + public static let PullUp = Self(rawValue: 0x1) /// Pull-down - static let PullDown = Self(rawValue: 0x2) + public static let PullDown = Self(rawValue: 0x2) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.ODR { - struct ODR0Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct ODR0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Set output to logic low - static let Low = Self(rawValue: 0x0) + public static let Low = Self(rawValue: 0x0) /// Set output to logic high - static let High = Self(rawValue: 0x1) + public static let High = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.LCKR { - struct LCKKValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LCKKValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Port configuration lock key not active - static let NotActive = Self(rawValue: 0x0) + public static let NotActive = Self(rawValue: 0x0) /// Port configuration lock key active - static let Active = Self(rawValue: 0x1) + public static let Active = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.LCKR { - struct LCK0Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LCK0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Port configuration not locked - static let Unlocked = Self(rawValue: 0x0) + public static let Unlocked = Self(rawValue: 0x0) /// Port configuration locked - static let Locked = Self(rawValue: 0x1) + public static let Locked = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.AFRL { - struct AFRL0Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 4 + public struct AFRL0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 4 /// AF0 - static let AF0 = Self(rawValue: 0x0) + public static let AF0 = Self(rawValue: 0x0) /// AF1 - static let AF1 = Self(rawValue: 0x1) + public static let AF1 = Self(rawValue: 0x1) /// AF2 - static let AF2 = Self(rawValue: 0x2) + public static let AF2 = Self(rawValue: 0x2) /// AF3 - static let AF3 = Self(rawValue: 0x3) + public static let AF3 = Self(rawValue: 0x3) /// AF4 - static let AF4 = Self(rawValue: 0x4) + public static let AF4 = Self(rawValue: 0x4) /// AF5 - static let AF5 = Self(rawValue: 0x5) + public static let AF5 = Self(rawValue: 0x5) /// AF6 - static let AF6 = Self(rawValue: 0x6) + public static let AF6 = Self(rawValue: 0x6) /// AF7 - static let AF7 = Self(rawValue: 0x7) + public static let AF7 = Self(rawValue: 0x7) /// AF8 - static let AF8 = Self(rawValue: 0x8) + public static let AF8 = Self(rawValue: 0x8) /// AF9 - static let AF9 = Self(rawValue: 0x9) + public static let AF9 = Self(rawValue: 0x9) /// AF10 - static let AF10 = Self(rawValue: 0xa) + public static let AF10 = Self(rawValue: 0xa) /// AF11 - static let AF11 = Self(rawValue: 0xb) + public static let AF11 = Self(rawValue: 0xb) /// AF12 - static let AF12 = Self(rawValue: 0xc) + public static let AF12 = Self(rawValue: 0xc) /// AF13 - static let AF13 = Self(rawValue: 0xd) + public static let AF13 = Self(rawValue: 0xd) /// AF14 - static let AF14 = Self(rawValue: 0xe) + public static let AF14 = Self(rawValue: 0xe) /// AF15 - static let AF15 = Self(rawValue: 0xf) + public static let AF15 = Self(rawValue: 0xf) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.AFRH { - struct AFRH8Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 4 + public struct AFRH8Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 4 /// AF0 - static let AF0 = Self(rawValue: 0x0) + public static let AF0 = Self(rawValue: 0x0) /// AF1 - static let AF1 = Self(rawValue: 0x1) + public static let AF1 = Self(rawValue: 0x1) /// AF2 - static let AF2 = Self(rawValue: 0x2) + public static let AF2 = Self(rawValue: 0x2) /// AF3 - static let AF3 = Self(rawValue: 0x3) + public static let AF3 = Self(rawValue: 0x3) /// AF4 - static let AF4 = Self(rawValue: 0x4) + public static let AF4 = Self(rawValue: 0x4) /// AF5 - static let AF5 = Self(rawValue: 0x5) + public static let AF5 = Self(rawValue: 0x5) /// AF6 - static let AF6 = Self(rawValue: 0x6) + public static let AF6 = Self(rawValue: 0x6) /// AF7 - static let AF7 = Self(rawValue: 0x7) + public static let AF7 = Self(rawValue: 0x7) /// AF8 - static let AF8 = Self(rawValue: 0x8) + public static let AF8 = Self(rawValue: 0x8) /// AF9 - static let AF9 = Self(rawValue: 0x9) + public static let AF9 = Self(rawValue: 0x9) /// AF10 - static let AF10 = Self(rawValue: 0xa) + public static let AF10 = Self(rawValue: 0xa) /// AF11 - static let AF11 = Self(rawValue: 0xb) + public static let AF11 = Self(rawValue: 0xb) /// AF12 - static let AF12 = Self(rawValue: 0xc) + public static let AF12 = Self(rawValue: 0xc) /// AF13 - static let AF13 = Self(rawValue: 0xd) + public static let AF13 = Self(rawValue: 0xd) /// AF14 - static let AF14 = Self(rawValue: 0xe) + public static let AF14 = Self(rawValue: 0xe) /// AF15 - static let AF15 = Self(rawValue: 0xf) + public static let AF15 = Self(rawValue: 0xf) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } diff --git a/stm32-uart-echo/Sources/Application/Registers/GPIOB.swift b/stm32-neopixel/Sources/STM32F7X6/GPIOB.swift similarity index 68% rename from stm32-uart-echo/Sources/Application/Registers/GPIOB.swift rename to stm32-neopixel/Sources/STM32F7X6/GPIOB.swift index c820355f..bd0a35ba 100644 --- a/stm32-uart-echo/Sources/Application/Registers/GPIOB.swift +++ b/stm32-neopixel/Sources/STM32F7X6/GPIOB.swift @@ -3,5 +3,5 @@ import MMIO /// General-purpose I/Os -typealias GPIOB = GPIOA +public typealias GPIOB = GPIOA diff --git a/stm32-neopixel/Sources/Application/Registers/GPIOI.swift b/stm32-neopixel/Sources/STM32F7X6/GPIOI.swift similarity index 68% rename from stm32-neopixel/Sources/Application/Registers/GPIOI.swift rename to stm32-neopixel/Sources/STM32F7X6/GPIOI.swift index f7e28cc8..6b2b5182 100644 --- a/stm32-neopixel/Sources/Application/Registers/GPIOI.swift +++ b/stm32-neopixel/Sources/STM32F7X6/GPIOI.swift @@ -3,5 +3,5 @@ import MMIO /// General-purpose I/Os -typealias GPIOI = GPIOA +public typealias GPIOI = GPIOA diff --git a/stm32-neopixel/Sources/Application/Registers/RCC.swift b/stm32-neopixel/Sources/STM32F7X6/RCC.swift similarity index 55% rename from stm32-neopixel/Sources/Application/Registers/RCC.swift rename to stm32-neopixel/Sources/STM32F7X6/RCC.swift index 4f5842ef..4a36aea8 100644 --- a/stm32-neopixel/Sources/Application/Registers/RCC.swift +++ b/stm32-neopixel/Sources/STM32F7X6/RCC.swift @@ -4,2829 +4,2829 @@ import MMIO /// Reset and clock control @RegisterBlock -struct RCC { +public struct RCC { /// clock control register @RegisterBlock(offset: 0x0) - var cr: Register + public var cr: Register /// PLL configuration register @RegisterBlock(offset: 0x4) - var pllcfgr: Register + public var pllcfgr: Register /// clock configuration register @RegisterBlock(offset: 0x8) - var cfgr: Register + public var cfgr: Register /// clock interrupt register @RegisterBlock(offset: 0xc) - var cir: Register + public var cir: Register /// AHB1 peripheral reset register @RegisterBlock(offset: 0x10) - var ahb1rstr: Register + public var ahb1rstr: Register /// AHB2 peripheral reset register @RegisterBlock(offset: 0x14) - var ahb2rstr: Register + public var ahb2rstr: Register /// AHB3 peripheral reset register @RegisterBlock(offset: 0x18) - var ahb3rstr: Register + public var ahb3rstr: Register /// APB1 peripheral reset register @RegisterBlock(offset: 0x20) - var apb1rstr: Register + public var apb1rstr: Register /// APB2 peripheral reset register @RegisterBlock(offset: 0x24) - var apb2rstr: Register + public var apb2rstr: Register /// AHB1 peripheral clock register @RegisterBlock(offset: 0x30) - var ahb1enr: Register + public var ahb1enr: Register /// AHB2 peripheral clock enable register @RegisterBlock(offset: 0x34) - var ahb2enr: Register + public var ahb2enr: Register /// AHB3 peripheral clock enable register @RegisterBlock(offset: 0x38) - var ahb3enr: Register + public var ahb3enr: Register /// APB1 peripheral clock enable register @RegisterBlock(offset: 0x40) - var apb1enr: Register + public var apb1enr: Register /// APB2 peripheral clock enable register @RegisterBlock(offset: 0x44) - var apb2enr: Register + public var apb2enr: Register /// AHB1 peripheral clock enable in low power mode register @RegisterBlock(offset: 0x50) - var ahb1lpenr: Register + public var ahb1lpenr: Register /// AHB2 peripheral clock enable in low power mode register @RegisterBlock(offset: 0x54) - var ahb2lpenr: Register + public var ahb2lpenr: Register /// AHB3 peripheral clock enable in low power mode register @RegisterBlock(offset: 0x58) - var ahb3lpenr: Register + public var ahb3lpenr: Register /// APB1 peripheral clock enable in low power mode register @RegisterBlock(offset: 0x60) - var apb1lpenr: Register + public var apb1lpenr: Register /// APB2 peripheral clock enabled in low power mode register @RegisterBlock(offset: 0x64) - var apb2lpenr: Register + public var apb2lpenr: Register /// Backup domain control register @RegisterBlock(offset: 0x70) - var bdcr: Register + public var bdcr: Register /// clock control & status register @RegisterBlock(offset: 0x74) - var csr: Register + public var csr: Register /// spread spectrum clock generation register @RegisterBlock(offset: 0x80) - var sscgr: Register + public var sscgr: Register /// PLLI2S configuration register @RegisterBlock(offset: 0x84) - var plli2scfgr: Register + public var plli2scfgr: Register /// PLL configuration register @RegisterBlock(offset: 0x88) - var pllsaicfgr: Register + public var pllsaicfgr: Register /// dedicated clocks configuration register @RegisterBlock(offset: 0x8c) - var dckcfgr1: Register + public var dckcfgr1: Register /// dedicated clocks configuration register @RegisterBlock(offset: 0x90) - var dckcfgr2: Register + public var dckcfgr2: Register } extension RCC { /// clock control register @Register(bitWidth: 32) - struct CR { + public struct CR { /// PLLI2S clock ready flag @ReadOnly(bits: 27..<28) - var plli2srdy: PLLI2SRDY + public var plli2srdy: PLLI2SRDY /// PLLI2S enable @ReadWrite(bits: 26..<27) - var plli2son: PLLI2SON + public var plli2son: PLLI2SON /// Main PLL (PLL) clock ready flag @ReadOnly(bits: 25..<26) - var pllrdy: PLLRDY + public var pllrdy: PLLRDY /// Main PLL (PLL) enable @ReadWrite(bits: 24..<25) - var pllon: PLLON + public var pllon: PLLON /// Clock security system enable @ReadWrite(bits: 19..<20, as: CSSONValues.self) - var csson: CSSON + public var csson: CSSON /// HSE clock bypass @ReadWrite(bits: 18..<19, as: HSEBYPValues.self) - var hsebyp: HSEBYP + public var hsebyp: HSEBYP /// HSE clock ready flag @ReadOnly(bits: 17..<18) - var hserdy: HSERDY + public var hserdy: HSERDY /// HSE clock enable @ReadWrite(bits: 16..<17) - var hseon: HSEON + public var hseon: HSEON /// Internal high-speed clock calibration @ReadOnly(bits: 8..<16) - var hsical: HSICAL + public var hsical: HSICAL /// Internal high-speed clock trimming @ReadWrite(bits: 3..<8) - var hsitrim: HSITRIM + public var hsitrim: HSITRIM /// Internal high-speed clock ready flag @ReadOnly(bits: 1..<2) - var hsirdy: HSIRDY + public var hsirdy: HSIRDY /// Internal high-speed clock enable @ReadWrite(bits: 0..<1, as: HSIONValues.self) - var hsion: HSION + public var hsion: HSION /// PLLSAI clock ready flag @ReadOnly(bits: 29..<30) - var pllsairdy: PLLSAIRDY + public var pllsairdy: PLLSAIRDY /// PLLSAI enable @ReadWrite(bits: 28..<29) - var pllsaion: PLLSAION + public var pllsaion: PLLSAION } /// PLL configuration register @Register(bitWidth: 32) - struct PLLCFGR { + public struct PLLCFGR { /// Main PLL(PLL) and audio PLL (PLLI2S) entry clock source @ReadWrite(bits: 22..<23, as: PLLSRCValues.self) - var pllsrc: PLLSRC + public var pllsrc: PLLSRC /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock @ReadWrite(bits: 0..<6) - var pllm: PLLM + public var pllm: PLLM /// Main PLL (PLL) multiplication factor for VCO @ReadWrite(bits: 6..<15) - var plln: PLLN + public var plln: PLLN /// Main PLL (PLL) division factor for main system clock @ReadWrite(bits: 16..<18, as: PLLPValues.self) - var pllp: PLLP + public var pllp: PLLP /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks @ReadWrite(bits: 24..<28) - var pllq: PLLQ + public var pllq: PLLQ } /// clock configuration register @Register(bitWidth: 32) - struct CFGR { + public struct CFGR { /// Microcontroller clock output 2 @ReadWrite(bits: 30..<32, as: MCO2Values.self) - var mco2: MCO2 + public var mco2: MCO2 /// MCO2 prescaler @ReadWrite(bits: 27..<30) - var mco2pre: MCO2PRE + public var mco2pre: MCO2PRE /// MCO1 prescaler @ReadWrite(bits: 24..<27, as: MCO1PREValues.self) - var mco1pre: MCO1PRE + public var mco1pre: MCO1PRE /// I2S clock selection @ReadWrite(bits: 23..<24, as: I2SSRCValues.self) - var i2ssrc: I2SSRC + public var i2ssrc: I2SSRC /// Microcontroller clock output 1 @ReadWrite(bits: 21..<23, as: MCO1Values.self) - var mco1: MCO1 + public var mco1: MCO1 /// HSE division factor for RTC clock @ReadWrite(bits: 16..<21) - var rtcpre: RTCPRE + public var rtcpre: RTCPRE /// APB high-speed prescaler (APB2) @ReadWrite(bits: 13..<16) - var ppre2: PPRE2 + public var ppre2: PPRE2 /// APB Low speed prescaler (APB1) @ReadWrite(bits: 10..<13, as: PPRE1Values.self) - var ppre1: PPRE1 + public var ppre1: PPRE1 /// AHB prescaler @ReadWrite(bits: 4..<8, as: HPREValues.self) - var hpre: HPRE + public var hpre: HPRE /// System clock switch @Reserved(bits: 0..<2, as: SWValues.self) - var sw: SW + public var sw: SW /// System clock switch status @Reserved(bits: 2..<4) - var sws: SWS + public var sws: SWS } /// clock interrupt register @Register(bitWidth: 32) - struct CIR { + public struct CIR { /// Clock security system interrupt clear @WriteOnly(bits: 23..<24) - var cssc: CSSC + public var cssc: CSSC /// PLLSAI Ready Interrupt Clear @WriteOnly(bits: 22..<23) - var pllsairdyc: PLLSAIRDYC + public var pllsairdyc: PLLSAIRDYC /// PLLI2S ready interrupt clear @WriteOnly(bits: 21..<22) - var plli2srdyc: PLLI2SRDYC + public var plli2srdyc: PLLI2SRDYC /// Main PLL(PLL) ready interrupt clear @WriteOnly(bits: 20..<21) - var pllrdyc: PLLRDYC + public var pllrdyc: PLLRDYC /// HSE ready interrupt clear @WriteOnly(bits: 19..<20) - var hserdyc: HSERDYC + public var hserdyc: HSERDYC /// HSI ready interrupt clear @WriteOnly(bits: 18..<19) - var hsirdyc: HSIRDYC + public var hsirdyc: HSIRDYC /// LSE ready interrupt clear @WriteOnly(bits: 17..<18) - var lserdyc: LSERDYC + public var lserdyc: LSERDYC /// LSI ready interrupt clear @WriteOnly(bits: 16..<17) - var lsirdyc: LSIRDYC + public var lsirdyc: LSIRDYC /// PLLSAI Ready Interrupt Enable @ReadWrite(bits: 14..<15) - var pllsairdyie: PLLSAIRDYIE + public var pllsairdyie: PLLSAIRDYIE /// PLLI2S ready interrupt enable @ReadWrite(bits: 13..<14) - var plli2srdyie: PLLI2SRDYIE + public var plli2srdyie: PLLI2SRDYIE /// Main PLL (PLL) ready interrupt enable @ReadWrite(bits: 12..<13) - var pllrdyie: PLLRDYIE + public var pllrdyie: PLLRDYIE /// HSE ready interrupt enable @ReadWrite(bits: 11..<12) - var hserdyie: HSERDYIE + public var hserdyie: HSERDYIE /// HSI ready interrupt enable @ReadWrite(bits: 10..<11) - var hsirdyie: HSIRDYIE + public var hsirdyie: HSIRDYIE /// LSE ready interrupt enable @ReadWrite(bits: 9..<10) - var lserdyie: LSERDYIE + public var lserdyie: LSERDYIE /// LSI ready interrupt enable @ReadWrite(bits: 8..<9, as: LSIRDYIEValues.self) - var lsirdyie: LSIRDYIE + public var lsirdyie: LSIRDYIE /// Clock security system interrupt flag @ReadOnly(bits: 7..<8) - var cssf: CSSF + public var cssf: CSSF /// PLLSAI ready interrupt flag @ReadOnly(bits: 6..<7) - var pllsairdyf: PLLSAIRDYF + public var pllsairdyf: PLLSAIRDYF /// PLLI2S ready interrupt flag @ReadOnly(bits: 5..<6) - var plli2srdyf: PLLI2SRDYF + public var plli2srdyf: PLLI2SRDYF /// Main PLL (PLL) ready interrupt flag @ReadOnly(bits: 4..<5) - var pllrdyf: PLLRDYF + public var pllrdyf: PLLRDYF /// HSE ready interrupt flag @ReadOnly(bits: 3..<4) - var hserdyf: HSERDYF + public var hserdyf: HSERDYF /// HSI ready interrupt flag @ReadOnly(bits: 2..<3) - var hsirdyf: HSIRDYF + public var hsirdyf: HSIRDYF /// LSE ready interrupt flag @ReadOnly(bits: 1..<2) - var lserdyf: LSERDYF + public var lserdyf: LSERDYF /// LSI ready interrupt flag @ReadOnly(bits: 0..<1) - var lsirdyf: LSIRDYF + public var lsirdyf: LSIRDYF } /// AHB1 peripheral reset register @Register(bitWidth: 32) - struct AHB1RSTR { + public struct AHB1RSTR { /// USB OTG HS module reset @ReadWrite(bits: 29..<30) - var otghsrst: OTGHSRST + public var otghsrst: OTGHSRST /// Ethernet MAC reset @ReadWrite(bits: 25..<26) - var ethmacrst: ETHMACRST + public var ethmacrst: ETHMACRST /// DMA2D reset @ReadWrite(bits: 23..<24) - var dma2drst: DMA2DRST + public var dma2drst: DMA2DRST /// DMA2 reset @ReadWrite(bits: 22..<23) - var dma2rst: DMA2RST + public var dma2rst: DMA2RST /// DMA2 reset @ReadWrite(bits: 21..<22) - var dma1rst: DMA1RST + public var dma1rst: DMA1RST /// CRC reset @ReadWrite(bits: 12..<13) - var crcrst: CRCRST + public var crcrst: CRCRST /// IO port K reset @ReadWrite(bits: 10..<11) - var gpiokrst: GPIOKRST + public var gpiokrst: GPIOKRST /// IO port J reset @ReadWrite(bits: 9..<10) - var gpiojrst: GPIOJRST + public var gpiojrst: GPIOJRST /// IO port I reset @ReadWrite(bits: 8..<9) - var gpioirst: GPIOIRST + public var gpioirst: GPIOIRST /// IO port H reset @ReadWrite(bits: 7..<8) - var gpiohrst: GPIOHRST + public var gpiohrst: GPIOHRST /// IO port G reset @ReadWrite(bits: 6..<7) - var gpiogrst: GPIOGRST + public var gpiogrst: GPIOGRST /// IO port F reset @ReadWrite(bits: 5..<6) - var gpiofrst: GPIOFRST + public var gpiofrst: GPIOFRST /// IO port E reset @ReadWrite(bits: 4..<5) - var gpioerst: GPIOERST + public var gpioerst: GPIOERST /// IO port D reset @ReadWrite(bits: 3..<4) - var gpiodrst: GPIODRST + public var gpiodrst: GPIODRST /// IO port C reset @ReadWrite(bits: 2..<3) - var gpiocrst: GPIOCRST + public var gpiocrst: GPIOCRST /// IO port B reset @ReadWrite(bits: 1..<2) - var gpiobrst: GPIOBRST + public var gpiobrst: GPIOBRST /// IO port A reset @ReadWrite(bits: 0..<1, as: GPIOARSTValues.self) - var gpioarst: GPIOARST + public var gpioarst: GPIOARST } /// AHB2 peripheral reset register @Register(bitWidth: 32) - struct AHB2RSTR { + public struct AHB2RSTR { /// USB OTG FS module reset @ReadWrite(bits: 7..<8) - var otgfsrst: OTGFSRST + public var otgfsrst: OTGFSRST /// Random number generator module reset @ReadWrite(bits: 6..<7) - var rngrst: RNGRST + public var rngrst: RNGRST /// Hash module reset @ReadWrite(bits: 5..<6) - var hsahrst: HSAHRST + public var hsahrst: HSAHRST /// Cryptographic module reset @ReadWrite(bits: 4..<5) - var cryprst: CRYPRST + public var cryprst: CRYPRST /// Camera interface reset @ReadWrite(bits: 0..<1, as: DCMIRSTValues.self) - var dcmirst: DCMIRST + public var dcmirst: DCMIRST } /// AHB3 peripheral reset register @Register(bitWidth: 32) - struct AHB3RSTR { + public struct AHB3RSTR { /// Flexible memory controller module reset @ReadWrite(bits: 0..<1, as: FMCRSTValues.self) - var fmcrst: FMCRST + public var fmcrst: FMCRST /// Quad SPI memory controller reset @ReadWrite(bits: 1..<2) - var qspirst: QSPIRST + public var qspirst: QSPIRST } /// APB1 peripheral reset register @Register(bitWidth: 32) - struct APB1RSTR { + public struct APB1RSTR { /// TIM2 reset @ReadWrite(bits: 0..<1, as: TIM2RSTValues.self) - var tim2rst: TIM2RST + public var tim2rst: TIM2RST /// TIM3 reset @ReadWrite(bits: 1..<2) - var tim3rst: TIM3RST + public var tim3rst: TIM3RST /// TIM4 reset @ReadWrite(bits: 2..<3) - var tim4rst: TIM4RST + public var tim4rst: TIM4RST /// TIM5 reset @ReadWrite(bits: 3..<4) - var tim5rst: TIM5RST + public var tim5rst: TIM5RST /// TIM6 reset @ReadWrite(bits: 4..<5) - var tim6rst: TIM6RST + public var tim6rst: TIM6RST /// TIM7 reset @ReadWrite(bits: 5..<6) - var tim7rst: TIM7RST + public var tim7rst: TIM7RST /// TIM12 reset @ReadWrite(bits: 6..<7) - var tim12rst: TIM12RST + public var tim12rst: TIM12RST /// TIM13 reset @ReadWrite(bits: 7..<8) - var tim13rst: TIM13RST + public var tim13rst: TIM13RST /// TIM14 reset @ReadWrite(bits: 8..<9) - var tim14rst: TIM14RST + public var tim14rst: TIM14RST /// Window watchdog reset @ReadWrite(bits: 11..<12) - var wwdgrst: WWDGRST + public var wwdgrst: WWDGRST /// SPI 2 reset @ReadWrite(bits: 14..<15) - var spi2rst: SPI2RST + public var spi2rst: SPI2RST /// SPI 3 reset @ReadWrite(bits: 15..<16) - var spi3rst: SPI3RST + public var spi3rst: SPI3RST /// USART 2 reset @ReadWrite(bits: 17..<18) - var usart2rst: USART2RST + public var usart2rst: USART2RST /// USART 3 reset @ReadWrite(bits: 18..<19) - var usart3rst: USART3RST + public var usart3rst: USART3RST /// USART 4 reset @ReadWrite(bits: 19..<20) - var uart4rst: UART4RST + public var uart4rst: UART4RST /// USART 5 reset @ReadWrite(bits: 20..<21) - var uart5rst: UART5RST + public var uart5rst: UART5RST /// I2C 1 reset @ReadWrite(bits: 21..<22) - var i2c1rst: I2C1RST + public var i2c1rst: I2C1RST /// I2C 2 reset @ReadWrite(bits: 22..<23) - var i2c2rst: I2C2RST + public var i2c2rst: I2C2RST /// I2C3 reset @ReadWrite(bits: 23..<24) - var i2c3rst: I2C3RST + public var i2c3rst: I2C3RST /// CAN1 reset @ReadWrite(bits: 25..<26) - var can1rst: CAN1RST + public var can1rst: CAN1RST /// CAN2 reset @ReadWrite(bits: 26..<27) - var can2rst: CAN2RST + public var can2rst: CAN2RST /// Power interface reset @ReadWrite(bits: 28..<29) - var pwrrst: PWRRST + public var pwrrst: PWRRST /// DAC reset @ReadWrite(bits: 29..<30) - var dacrst: DACRST + public var dacrst: DACRST /// UART7 reset @ReadWrite(bits: 30..<31) - var uart7rst: UART7RST + public var uart7rst: UART7RST /// UART8 reset @ReadWrite(bits: 31..<32) - var uart8rst: UART8RST + public var uart8rst: UART8RST /// SPDIF-RX reset @ReadWrite(bits: 16..<17) - var spdifrxrst: SPDIFRXRST + public var spdifrxrst: SPDIFRXRST /// HDMI-CEC reset @ReadWrite(bits: 27..<28) - var cecrst: CECRST + public var cecrst: CECRST /// Low power timer 1 reset @ReadWrite(bits: 9..<10) - var lptim1rst: LPTIM1RST + public var lptim1rst: LPTIM1RST /// I2C 4 reset @ReadWrite(bits: 24..<25) - var i2c4rst: I2C4RST + public var i2c4rst: I2C4RST } /// APB2 peripheral reset register @Register(bitWidth: 32) - struct APB2RSTR { + public struct APB2RSTR { /// TIM1 reset @ReadWrite(bits: 0..<1, as: TIM1RSTValues.self) - var tim1rst: TIM1RST + public var tim1rst: TIM1RST /// TIM8 reset @ReadWrite(bits: 1..<2) - var tim8rst: TIM8RST + public var tim8rst: TIM8RST /// USART1 reset @ReadWrite(bits: 4..<5) - var usart1rst: USART1RST + public var usart1rst: USART1RST /// USART6 reset @ReadWrite(bits: 5..<6) - var usart6rst: USART6RST + public var usart6rst: USART6RST /// ADC interface reset (common to all ADCs) @ReadWrite(bits: 8..<9) - var adcrst: ADCRST + public var adcrst: ADCRST /// SPI 1 reset @ReadWrite(bits: 12..<13) - var spi1rst: SPI1RST + public var spi1rst: SPI1RST /// SPI4 reset @ReadWrite(bits: 13..<14) - var spi4rst: SPI4RST + public var spi4rst: SPI4RST /// System configuration controller reset @ReadWrite(bits: 14..<15) - var syscfgrst: SYSCFGRST + public var syscfgrst: SYSCFGRST /// TIM9 reset @ReadWrite(bits: 16..<17) - var tim9rst: TIM9RST + public var tim9rst: TIM9RST /// TIM10 reset @ReadWrite(bits: 17..<18) - var tim10rst: TIM10RST + public var tim10rst: TIM10RST /// TIM11 reset @ReadWrite(bits: 18..<19) - var tim11rst: TIM11RST + public var tim11rst: TIM11RST /// SPI5 reset @ReadWrite(bits: 20..<21) - var spi5rst: SPI5RST + public var spi5rst: SPI5RST /// SPI6 reset @ReadWrite(bits: 21..<22) - var spi6rst: SPI6RST + public var spi6rst: SPI6RST /// SAI1 reset @ReadWrite(bits: 22..<23) - var sai1rst: SAI1RST + public var sai1rst: SAI1RST /// LTDC reset @ReadWrite(bits: 26..<27) - var ltdcrst: LTDCRST + public var ltdcrst: LTDCRST /// SAI2 reset @ReadWrite(bits: 23..<24) - var sai2rst: SAI2RST + public var sai2rst: SAI2RST /// SDMMC1 reset @ReadWrite(bits: 11..<12) - var sdmmc1rst: SDMMC1RST + public var sdmmc1rst: SDMMC1RST } /// AHB1 peripheral clock register @Register(bitWidth: 32) - struct AHB1ENR { + public struct AHB1ENR { /// USB OTG HSULPI clock enable @ReadWrite(bits: 30..<31) - var otghsulpien: OTGHSULPIEN + public var otghsulpien: OTGHSULPIEN /// USB OTG HS clock enable @ReadWrite(bits: 29..<30) - var otghsen: OTGHSEN + public var otghsen: OTGHSEN /// Ethernet PTP clock enable @ReadWrite(bits: 28..<29) - var ethmacptpen: ETHMACPTPEN + public var ethmacptpen: ETHMACPTPEN /// Ethernet Reception clock enable @ReadWrite(bits: 27..<28) - var ethmacrxen: ETHMACRXEN + public var ethmacrxen: ETHMACRXEN /// Ethernet Transmission clock enable @ReadWrite(bits: 26..<27) - var ethmactxen: ETHMACTXEN + public var ethmactxen: ETHMACTXEN /// Ethernet MAC clock enable @ReadWrite(bits: 25..<26) - var ethmacen: ETHMACEN + public var ethmacen: ETHMACEN /// DMA2D clock enable @ReadWrite(bits: 23..<24) - var dma2den: DMA2DEN + public var dma2den: DMA2DEN /// DMA2 clock enable @ReadWrite(bits: 22..<23) - var dma2en: DMA2EN + public var dma2en: DMA2EN /// DMA1 clock enable @ReadWrite(bits: 21..<22) - var dma1en: DMA1EN + public var dma1en: DMA1EN /// CCM data RAM clock enable @ReadWrite(bits: 20..<21) - var dtcmramen: DTCMRAMEN + public var dtcmramen: DTCMRAMEN /// Backup SRAM interface clock enable @ReadWrite(bits: 18..<19) - var bkpsramen: BKPSRAMEN + public var bkpsramen: BKPSRAMEN /// CRC clock enable @ReadWrite(bits: 12..<13) - var crcen: CRCEN + public var crcen: CRCEN /// IO port K clock enable @ReadWrite(bits: 10..<11) - var gpioken: GPIOKEN + public var gpioken: GPIOKEN /// IO port J clock enable @ReadWrite(bits: 9..<10) - var gpiojen: GPIOJEN + public var gpiojen: GPIOJEN /// IO port I clock enable @ReadWrite(bits: 8..<9) - var gpioien: GPIOIEN + public var gpioien: GPIOIEN /// IO port H clock enable @ReadWrite(bits: 7..<8) - var gpiohen: GPIOHEN + public var gpiohen: GPIOHEN /// IO port G clock enable @ReadWrite(bits: 6..<7) - var gpiogen: GPIOGEN + public var gpiogen: GPIOGEN /// IO port F clock enable @ReadWrite(bits: 5..<6) - var gpiofen: GPIOFEN + public var gpiofen: GPIOFEN /// IO port E clock enable @ReadWrite(bits: 4..<5) - var gpioeen: GPIOEEN + public var gpioeen: GPIOEEN /// IO port D clock enable @ReadWrite(bits: 3..<4) - var gpioden: GPIODEN + public var gpioden: GPIODEN /// IO port C clock enable @ReadWrite(bits: 2..<3) - var gpiocen: GPIOCEN + public var gpiocen: GPIOCEN /// IO port B clock enable @ReadWrite(bits: 1..<2) - var gpioben: GPIOBEN + public var gpioben: GPIOBEN /// IO port A clock enable @ReadWrite(bits: 0..<1, as: GPIOAENValues.self) - var gpioaen: GPIOAEN + public var gpioaen: GPIOAEN } /// AHB2 peripheral clock enable register @Register(bitWidth: 32) - struct AHB2ENR { + public struct AHB2ENR { /// USB OTG FS clock enable @ReadWrite(bits: 7..<8) - var otgfsen: OTGFSEN + public var otgfsen: OTGFSEN /// Random number generator clock enable @ReadWrite(bits: 6..<7) - var rngen: RNGEN + public var rngen: RNGEN /// Hash modules clock enable @ReadWrite(bits: 5..<6) - var hashen: HASHEN + public var hashen: HASHEN /// Cryptographic modules clock enable @ReadWrite(bits: 4..<5) - var crypen: CRYPEN + public var crypen: CRYPEN /// Camera interface enable @ReadWrite(bits: 0..<1, as: DCMIENValues.self) - var dcmien: DCMIEN + public var dcmien: DCMIEN } /// AHB3 peripheral clock enable register @Register(bitWidth: 32) - struct AHB3ENR { + public struct AHB3ENR { /// Flexible memory controller module clock enable @ReadWrite(bits: 0..<1, as: FMCENValues.self) - var fmcen: FMCEN + public var fmcen: FMCEN /// Quad SPI memory controller clock enable @ReadWrite(bits: 1..<2) - var qspien: QSPIEN + public var qspien: QSPIEN } /// APB1 peripheral clock enable register @Register(bitWidth: 32) - struct APB1ENR { + public struct APB1ENR { /// TIM2 clock enable @ReadWrite(bits: 0..<1, as: TIM2ENValues.self) - var tim2en: TIM2EN + public var tim2en: TIM2EN /// TIM3 clock enable @ReadWrite(bits: 1..<2) - var tim3en: TIM3EN + public var tim3en: TIM3EN /// TIM4 clock enable @ReadWrite(bits: 2..<3) - var tim4en: TIM4EN + public var tim4en: TIM4EN /// TIM5 clock enable @ReadWrite(bits: 3..<4) - var tim5en: TIM5EN + public var tim5en: TIM5EN /// TIM6 clock enable @ReadWrite(bits: 4..<5) - var tim6en: TIM6EN + public var tim6en: TIM6EN /// TIM7 clock enable @ReadWrite(bits: 5..<6) - var tim7en: TIM7EN + public var tim7en: TIM7EN /// TIM12 clock enable @ReadWrite(bits: 6..<7) - var tim12en: TIM12EN + public var tim12en: TIM12EN /// TIM13 clock enable @ReadWrite(bits: 7..<8) - var tim13en: TIM13EN + public var tim13en: TIM13EN /// TIM14 clock enable @ReadWrite(bits: 8..<9) - var tim14en: TIM14EN + public var tim14en: TIM14EN /// Window watchdog clock enable @ReadWrite(bits: 11..<12) - var wwdgen: WWDGEN + public var wwdgen: WWDGEN /// SPI2 clock enable @ReadWrite(bits: 14..<15) - var spi2en: SPI2EN + public var spi2en: SPI2EN /// SPI3 clock enable @ReadWrite(bits: 15..<16) - var spi3en: SPI3EN + public var spi3en: SPI3EN /// USART 2 clock enable @ReadWrite(bits: 17..<18) - var usart2en: USART2EN + public var usart2en: USART2EN /// USART3 clock enable @ReadWrite(bits: 18..<19) - var usart3en: USART3EN + public var usart3en: USART3EN /// UART4 clock enable @ReadWrite(bits: 19..<20) - var uart4en: UART4EN + public var uart4en: UART4EN /// UART5 clock enable @ReadWrite(bits: 20..<21) - var uart5en: UART5EN + public var uart5en: UART5EN /// I2C1 clock enable @ReadWrite(bits: 21..<22) - var i2c1en: I2C1EN + public var i2c1en: I2C1EN /// I2C2 clock enable @ReadWrite(bits: 22..<23) - var i2c2en: I2C2EN + public var i2c2en: I2C2EN /// I2C3 clock enable @ReadWrite(bits: 23..<24) - var i2c3en: I2C3EN + public var i2c3en: I2C3EN /// CAN 1 clock enable @ReadWrite(bits: 25..<26) - var can1en: CAN1EN + public var can1en: CAN1EN /// CAN 2 clock enable @ReadWrite(bits: 26..<27) - var can2en: CAN2EN + public var can2en: CAN2EN /// Power interface clock enable @ReadWrite(bits: 28..<29) - var pwren: PWREN + public var pwren: PWREN /// DAC interface clock enable @ReadWrite(bits: 29..<30) - var dacen: DACEN + public var dacen: DACEN /// UART7 clock enable @ReadWrite(bits: 30..<31) - var uart7en: UART7EN + public var uart7en: UART7EN /// UART8 clock enable @ReadWrite(bits: 31..<32) - var uart8en: UART8EN + public var uart8en: UART8EN /// SPDIF-RX clock enable @ReadWrite(bits: 16..<17) - var spdifrxen: SPDIFRXEN + public var spdifrxen: SPDIFRXEN /// HDMI-CEN clock enable @ReadWrite(bits: 27..<28) - var cecen: CECEN + public var cecen: CECEN /// Low power timer 1 clock enable @ReadWrite(bits: 9..<10) - var lptim1en: LPTIM1EN + public var lptim1en: LPTIM1EN /// I2C4 clock enable @ReadWrite(bits: 24..<25) - var i2c4en: I2C4EN + public var i2c4en: I2C4EN } /// APB2 peripheral clock enable register @Register(bitWidth: 32) - struct APB2ENR { + public struct APB2ENR { /// TIM1 clock enable @ReadWrite(bits: 0..<1, as: TIM1ENValues.self) - var tim1en: TIM1EN + public var tim1en: TIM1EN /// TIM8 clock enable @ReadWrite(bits: 1..<2) - var tim8en: TIM8EN + public var tim8en: TIM8EN /// USART1 clock enable @ReadWrite(bits: 4..<5) - var usart1en: USART1EN + public var usart1en: USART1EN /// USART6 clock enable @ReadWrite(bits: 5..<6) - var usart6en: USART6EN + public var usart6en: USART6EN /// ADC1 clock enable @ReadWrite(bits: 8..<9) - var adc1en: ADC1EN + public var adc1en: ADC1EN /// ADC2 clock enable @ReadWrite(bits: 9..<10) - var adc2en: ADC2EN + public var adc2en: ADC2EN /// ADC3 clock enable @ReadWrite(bits: 10..<11) - var adc3en: ADC3EN + public var adc3en: ADC3EN /// SPI1 clock enable @ReadWrite(bits: 12..<13) - var spi1en: SPI1EN + public var spi1en: SPI1EN /// SPI4 clock enable @ReadWrite(bits: 13..<14) - var spi4en: SPI4EN + public var spi4en: SPI4EN /// System configuration controller clock enable @ReadWrite(bits: 14..<15) - var syscfgen: SYSCFGEN + public var syscfgen: SYSCFGEN /// TIM9 clock enable @ReadWrite(bits: 16..<17) - var tim9en: TIM9EN + public var tim9en: TIM9EN /// TIM10 clock enable @ReadWrite(bits: 17..<18) - var tim10en: TIM10EN + public var tim10en: TIM10EN /// TIM11 clock enable @ReadWrite(bits: 18..<19) - var tim11en: TIM11EN + public var tim11en: TIM11EN /// SPI5 clock enable @ReadWrite(bits: 20..<21) - var spi5en: SPI5EN + public var spi5en: SPI5EN /// SPI6 clock enable @ReadWrite(bits: 21..<22) - var spi6en: SPI6EN + public var spi6en: SPI6EN /// SAI1 clock enable @ReadWrite(bits: 22..<23) - var sai1en: SAI1EN + public var sai1en: SAI1EN /// LTDC clock enable @ReadWrite(bits: 26..<27) - var ltdcen: LTDCEN + public var ltdcen: LTDCEN /// SAI2 clock enable @ReadWrite(bits: 23..<24) - var sai2en: SAI2EN + public var sai2en: SAI2EN /// SDMMC1 clock enable @ReadWrite(bits: 11..<12) - var sdmmc1en: SDMMC1EN + public var sdmmc1en: SDMMC1EN } /// AHB1 peripheral clock enable in low power mode register @Register(bitWidth: 32) - struct AHB1LPENR { + public struct AHB1LPENR { /// IO port A clock enable during sleep mode @ReadWrite(bits: 0..<1, as: GPIOALPENValues.self) - var gpioalpen: GPIOALPEN + public var gpioalpen: GPIOALPEN /// IO port B clock enable during Sleep mode @ReadWrite(bits: 1..<2) - var gpioblpen: GPIOBLPEN + public var gpioblpen: GPIOBLPEN /// IO port C clock enable during Sleep mode @ReadWrite(bits: 2..<3) - var gpioclpen: GPIOCLPEN + public var gpioclpen: GPIOCLPEN /// IO port D clock enable during Sleep mode @ReadWrite(bits: 3..<4) - var gpiodlpen: GPIODLPEN + public var gpiodlpen: GPIODLPEN /// IO port E clock enable during Sleep mode @ReadWrite(bits: 4..<5) - var gpioelpen: GPIOELPEN + public var gpioelpen: GPIOELPEN /// IO port F clock enable during Sleep mode @ReadWrite(bits: 5..<6) - var gpioflpen: GPIOFLPEN + public var gpioflpen: GPIOFLPEN /// IO port G clock enable during Sleep mode @ReadWrite(bits: 6..<7) - var gpioglpen: GPIOGLPEN + public var gpioglpen: GPIOGLPEN /// IO port H clock enable during Sleep mode @ReadWrite(bits: 7..<8) - var gpiohlpen: GPIOHLPEN + public var gpiohlpen: GPIOHLPEN /// IO port I clock enable during Sleep mode @ReadWrite(bits: 8..<9) - var gpioilpen: GPIOILPEN + public var gpioilpen: GPIOILPEN /// IO port J clock enable during Sleep mode @ReadWrite(bits: 9..<10) - var gpiojlpen: GPIOJLPEN + public var gpiojlpen: GPIOJLPEN /// IO port K clock enable during Sleep mode @ReadWrite(bits: 10..<11) - var gpioklpen: GPIOKLPEN + public var gpioklpen: GPIOKLPEN /// CRC clock enable during Sleep mode @ReadWrite(bits: 12..<13) - var crclpen: CRCLPEN + public var crclpen: CRCLPEN /// Flash interface clock enable during Sleep mode @ReadWrite(bits: 15..<16) - var flitflpen: FLITFLPEN + public var flitflpen: FLITFLPEN /// SRAM 1interface clock enable during Sleep mode @ReadWrite(bits: 16..<17) - var sram1lpen: SRAM1LPEN + public var sram1lpen: SRAM1LPEN /// SRAM 2 interface clock enable during Sleep mode @ReadWrite(bits: 17..<18) - var sram2lpen: SRAM2LPEN + public var sram2lpen: SRAM2LPEN /// Backup SRAM interface clock enable during Sleep mode @ReadWrite(bits: 18..<19) - var bkpsramlpen: BKPSRAMLPEN + public var bkpsramlpen: BKPSRAMLPEN /// SRAM 3 interface clock enable during Sleep mode @ReadWrite(bits: 19..<20) - var sram3lpen: SRAM3LPEN + public var sram3lpen: SRAM3LPEN /// DMA1 clock enable during Sleep mode @ReadWrite(bits: 21..<22) - var dma1lpen: DMA1LPEN + public var dma1lpen: DMA1LPEN /// DMA2 clock enable during Sleep mode @ReadWrite(bits: 22..<23) - var dma2lpen: DMA2LPEN + public var dma2lpen: DMA2LPEN /// DMA2D clock enable during Sleep mode @ReadWrite(bits: 23..<24) - var dma2dlpen: DMA2DLPEN + public var dma2dlpen: DMA2DLPEN /// Ethernet MAC clock enable during Sleep mode @ReadWrite(bits: 25..<26) - var ethmaclpen: ETHMACLPEN + public var ethmaclpen: ETHMACLPEN /// Ethernet transmission clock enable during Sleep mode @ReadWrite(bits: 26..<27) - var ethmactxlpen: ETHMACTXLPEN + public var ethmactxlpen: ETHMACTXLPEN /// Ethernet reception clock enable during Sleep mode @ReadWrite(bits: 27..<28) - var ethmacrxlpen: ETHMACRXLPEN + public var ethmacrxlpen: ETHMACRXLPEN /// Ethernet PTP clock enable during Sleep mode @ReadWrite(bits: 28..<29) - var ethmacptplpen: ETHMACPTPLPEN + public var ethmacptplpen: ETHMACPTPLPEN /// USB OTG HS clock enable during Sleep mode @ReadWrite(bits: 29..<30) - var otghslpen: OTGHSLPEN + public var otghslpen: OTGHSLPEN /// USB OTG HS ULPI clock enable during Sleep mode @ReadWrite(bits: 30..<31) - var otghsulpilpen: OTGHSULPILPEN + public var otghsulpilpen: OTGHSULPILPEN /// AXI to AHB bridge clock enable during Sleep mode @ReadWrite(bits: 13..<14) - var axilpen: AXILPEN + public var axilpen: AXILPEN /// DTCM RAM interface clock enable during Sleep mode @ReadWrite(bits: 20..<21) - var dtcmlpen: DTCMLPEN + public var dtcmlpen: DTCMLPEN } /// AHB2 peripheral clock enable in low power mode register @Register(bitWidth: 32) - struct AHB2LPENR { + public struct AHB2LPENR { /// USB OTG FS clock enable during Sleep mode @ReadWrite(bits: 7..<8) - var otgfslpen: OTGFSLPEN + public var otgfslpen: OTGFSLPEN /// Random number generator clock enable during Sleep mode @ReadWrite(bits: 6..<7) - var rnglpen: RNGLPEN + public var rnglpen: RNGLPEN /// Hash modules clock enable during Sleep mode @ReadWrite(bits: 5..<6) - var hashlpen: HASHLPEN + public var hashlpen: HASHLPEN /// Cryptography modules clock enable during Sleep mode @ReadWrite(bits: 4..<5) - var cryplpen: CRYPLPEN + public var cryplpen: CRYPLPEN /// Camera interface enable during Sleep mode @ReadWrite(bits: 0..<1, as: DCMILPENValues.self) - var dcmilpen: DCMILPEN + public var dcmilpen: DCMILPEN } /// AHB3 peripheral clock enable in low power mode register @Register(bitWidth: 32) - struct AHB3LPENR { + public struct AHB3LPENR { /// Flexible memory controller module clock enable during Sleep mode @ReadWrite(bits: 0..<1, as: FMCLPENValues.self) - var fmclpen: FMCLPEN + public var fmclpen: FMCLPEN /// Quand SPI memory controller clock enable during Sleep mode @ReadWrite(bits: 1..<2) - var qspilpen: QSPILPEN + public var qspilpen: QSPILPEN } /// APB1 peripheral clock enable in low power mode register @Register(bitWidth: 32) - struct APB1LPENR { + public struct APB1LPENR { /// TIM2 clock enable during Sleep mode @ReadWrite(bits: 0..<1, as: TIM2LPENValues.self) - var tim2lpen: TIM2LPEN + public var tim2lpen: TIM2LPEN /// TIM3 clock enable during Sleep mode @ReadWrite(bits: 1..<2) - var tim3lpen: TIM3LPEN + public var tim3lpen: TIM3LPEN /// TIM4 clock enable during Sleep mode @ReadWrite(bits: 2..<3) - var tim4lpen: TIM4LPEN + public var tim4lpen: TIM4LPEN /// TIM5 clock enable during Sleep mode @ReadWrite(bits: 3..<4) - var tim5lpen: TIM5LPEN + public var tim5lpen: TIM5LPEN /// TIM6 clock enable during Sleep mode @ReadWrite(bits: 4..<5) - var tim6lpen: TIM6LPEN + public var tim6lpen: TIM6LPEN /// TIM7 clock enable during Sleep mode @ReadWrite(bits: 5..<6) - var tim7lpen: TIM7LPEN + public var tim7lpen: TIM7LPEN /// TIM12 clock enable during Sleep mode @ReadWrite(bits: 6..<7) - var tim12lpen: TIM12LPEN + public var tim12lpen: TIM12LPEN /// TIM13 clock enable during Sleep mode @ReadWrite(bits: 7..<8) - var tim13lpen: TIM13LPEN + public var tim13lpen: TIM13LPEN /// TIM14 clock enable during Sleep mode @ReadWrite(bits: 8..<9) - var tim14lpen: TIM14LPEN + public var tim14lpen: TIM14LPEN /// Window watchdog clock enable during Sleep mode @ReadWrite(bits: 11..<12) - var wwdglpen: WWDGLPEN + public var wwdglpen: WWDGLPEN /// SPI2 clock enable during Sleep mode @ReadWrite(bits: 14..<15) - var spi2lpen: SPI2LPEN + public var spi2lpen: SPI2LPEN /// SPI3 clock enable during Sleep mode @ReadWrite(bits: 15..<16) - var spi3lpen: SPI3LPEN + public var spi3lpen: SPI3LPEN /// USART2 clock enable during Sleep mode @ReadWrite(bits: 17..<18) - var usart2lpen: USART2LPEN + public var usart2lpen: USART2LPEN /// USART3 clock enable during Sleep mode @ReadWrite(bits: 18..<19) - var usart3lpen: USART3LPEN + public var usart3lpen: USART3LPEN /// UART4 clock enable during Sleep mode @ReadWrite(bits: 19..<20) - var uart4lpen: UART4LPEN + public var uart4lpen: UART4LPEN /// UART5 clock enable during Sleep mode @ReadWrite(bits: 20..<21) - var uart5lpen: UART5LPEN + public var uart5lpen: UART5LPEN /// I2C1 clock enable during Sleep mode @ReadWrite(bits: 21..<22) - var i2c1lpen: I2C1LPEN + public var i2c1lpen: I2C1LPEN /// I2C2 clock enable during Sleep mode @ReadWrite(bits: 22..<23) - var i2c2lpen: I2C2LPEN + public var i2c2lpen: I2C2LPEN /// I2C3 clock enable during Sleep mode @ReadWrite(bits: 23..<24) - var i2c3lpen: I2C3LPEN + public var i2c3lpen: I2C3LPEN /// CAN 1 clock enable during Sleep mode @ReadWrite(bits: 25..<26) - var can1lpen: CAN1LPEN + public var can1lpen: CAN1LPEN /// CAN 2 clock enable during Sleep mode @ReadWrite(bits: 26..<27) - var can2lpen: CAN2LPEN + public var can2lpen: CAN2LPEN /// Power interface clock enable during Sleep mode @ReadWrite(bits: 28..<29) - var pwrlpen: PWRLPEN + public var pwrlpen: PWRLPEN /// DAC interface clock enable during Sleep mode @ReadWrite(bits: 29..<30) - var daclpen: DACLPEN + public var daclpen: DACLPEN /// UART7 clock enable during Sleep mode @ReadWrite(bits: 30..<31) - var uart7lpen: UART7LPEN + public var uart7lpen: UART7LPEN /// UART8 clock enable during Sleep mode @ReadWrite(bits: 31..<32) - var uart8lpen: UART8LPEN + public var uart8lpen: UART8LPEN /// SPDIF-RX clock enable during sleep mode @ReadWrite(bits: 16..<17) - var spdifrxlpen: SPDIFRXLPEN + public var spdifrxlpen: SPDIFRXLPEN /// HDMI-CEN clock enable during Sleep mode @ReadWrite(bits: 27..<28) - var ceclpen: CECLPEN + public var ceclpen: CECLPEN /// low power timer 1 clock enable during Sleep mode @ReadWrite(bits: 9..<10) - var lptim1lpen: LPTIM1LPEN + public var lptim1lpen: LPTIM1LPEN /// I2C4 clock enable during Sleep mode @ReadWrite(bits: 24..<25) - var i2c4lpen: I2C4LPEN + public var i2c4lpen: I2C4LPEN } /// APB2 peripheral clock enabled in low power mode register @Register(bitWidth: 32) - struct APB2LPENR { + public struct APB2LPENR { /// TIM1 clock enable during Sleep mode @ReadWrite(bits: 0..<1, as: TIM1LPENValues.self) - var tim1lpen: TIM1LPEN + public var tim1lpen: TIM1LPEN /// TIM8 clock enable during Sleep mode @ReadWrite(bits: 1..<2) - var tim8lpen: TIM8LPEN + public var tim8lpen: TIM8LPEN /// USART1 clock enable during Sleep mode @ReadWrite(bits: 4..<5) - var usart1lpen: USART1LPEN + public var usart1lpen: USART1LPEN /// USART6 clock enable during Sleep mode @ReadWrite(bits: 5..<6) - var usart6lpen: USART6LPEN + public var usart6lpen: USART6LPEN /// ADC1 clock enable during Sleep mode @ReadWrite(bits: 8..<9) - var adc1lpen: ADC1LPEN + public var adc1lpen: ADC1LPEN /// ADC2 clock enable during Sleep mode @ReadWrite(bits: 9..<10) - var adc2lpen: ADC2LPEN + public var adc2lpen: ADC2LPEN /// ADC 3 clock enable during Sleep mode @ReadWrite(bits: 10..<11) - var adc3lpen: ADC3LPEN + public var adc3lpen: ADC3LPEN /// SPI 1 clock enable during Sleep mode @ReadWrite(bits: 12..<13) - var spi1lpen: SPI1LPEN + public var spi1lpen: SPI1LPEN /// SPI 4 clock enable during Sleep mode @ReadWrite(bits: 13..<14) - var spi4lpen: SPI4LPEN + public var spi4lpen: SPI4LPEN /// System configuration controller clock enable during Sleep mode @ReadWrite(bits: 14..<15) - var syscfglpen: SYSCFGLPEN + public var syscfglpen: SYSCFGLPEN /// TIM9 clock enable during sleep mode @ReadWrite(bits: 16..<17) - var tim9lpen: TIM9LPEN + public var tim9lpen: TIM9LPEN /// TIM10 clock enable during Sleep mode @ReadWrite(bits: 17..<18) - var tim10lpen: TIM10LPEN + public var tim10lpen: TIM10LPEN /// TIM11 clock enable during Sleep mode @ReadWrite(bits: 18..<19) - var tim11lpen: TIM11LPEN + public var tim11lpen: TIM11LPEN /// SPI 5 clock enable during Sleep mode @ReadWrite(bits: 20..<21) - var spi5lpen: SPI5LPEN + public var spi5lpen: SPI5LPEN /// SPI 6 clock enable during Sleep mode @ReadWrite(bits: 21..<22) - var spi6lpen: SPI6LPEN + public var spi6lpen: SPI6LPEN /// SAI1 clock enable during sleep mode @ReadWrite(bits: 22..<23) - var sai1lpen: SAI1LPEN + public var sai1lpen: SAI1LPEN /// LTDC clock enable during sleep mode @ReadWrite(bits: 26..<27) - var ltdclpen: LTDCLPEN + public var ltdclpen: LTDCLPEN /// SAI2 clock enable during sleep mode @ReadWrite(bits: 23..<24) - var sai2lpen: SAI2LPEN + public var sai2lpen: SAI2LPEN /// SDMMC1 clock enable during Sleep mode @ReadWrite(bits: 11..<12) - var sdmmc1lpen: SDMMC1LPEN + public var sdmmc1lpen: SDMMC1LPEN } /// Backup domain control register @Register(bitWidth: 32) - struct BDCR { + public struct BDCR { /// Backup domain software reset @ReadWrite(bits: 16..<17, as: BDRSTValues.self) - var bdrst: BDRST + public var bdrst: BDRST /// RTC clock enable @ReadWrite(bits: 15..<16, as: RTCENValues.self) - var rtcen: RTCEN + public var rtcen: RTCEN /// External low-speed oscillator bypass @ReadWrite(bits: 2..<3, as: LSEBYPValues.self) - var lsebyp: LSEBYP + public var lsebyp: LSEBYP /// External low-speed oscillator ready @ReadOnly(bits: 1..<2) - var lserdy: LSERDY + public var lserdy: LSERDY /// External low-speed oscillator enable @ReadWrite(bits: 0..<1, as: LSEONValues.self) - var lseon: LSEON + public var lseon: LSEON /// LSE oscillator drive capability @ReadWrite(bits: 3..<5, as: LSEDRVValues.self) - var lsedrv: LSEDRV + public var lsedrv: LSEDRV /// RTC clock source selection @Reserved(bits: 8..<10, as: RTCSELValues.self) - var rtcsel: RTCSEL + public var rtcsel: RTCSEL } /// clock control & status register @Register(bitWidth: 32) - struct CSR { + public struct CSR { /// Low-power reset flag @ReadWrite(bits: 31..<32) - var lpwrrstf: LPWRRSTF + public var lpwrrstf: LPWRRSTF /// Window watchdog reset flag @ReadWrite(bits: 30..<31) - var wwdgrstf: WWDGRSTF + public var wwdgrstf: WWDGRSTF /// Independent watchdog reset flag @ReadWrite(bits: 29..<30) - var wdgrstf: WDGRSTF + public var wdgrstf: WDGRSTF /// Software reset flag @ReadWrite(bits: 28..<29) - var sftrstf: SFTRSTF + public var sftrstf: SFTRSTF /// POR/PDR reset flag @ReadWrite(bits: 27..<28) - var porrstf: PORRSTF + public var porrstf: PORRSTF /// PIN reset flag @ReadWrite(bits: 26..<27) - var padrstf: PADRSTF + public var padrstf: PADRSTF /// BOR reset flag @ReadWrite(bits: 25..<26) - var borrstf: BORRSTF + public var borrstf: BORRSTF /// Remove reset flag @ReadWrite(bits: 24..<25) - var rmvf: RMVF + public var rmvf: RMVF /// Internal low-speed oscillator ready @ReadOnly(bits: 1..<2) - var lsirdy: LSIRDY + public var lsirdy: LSIRDY /// Internal low-speed oscillator enable @ReadWrite(bits: 0..<1, as: LSIONValues.self) - var lsion: LSION + public var lsion: LSION } /// spread spectrum clock generation register @Register(bitWidth: 32) - struct SSCGR { + public struct SSCGR { /// Spread spectrum modulation enable @ReadWrite(bits: 31..<32, as: SSCGENValues.self) - var sscgen: SSCGEN + public var sscgen: SSCGEN /// Spread Select @ReadWrite(bits: 30..<31, as: SPREADSELValues.self) - var spreadsel: SPREADSEL + public var spreadsel: SPREADSEL /// Incrementation step @ReadWrite(bits: 13..<28) - var incstep: INCSTEP + public var incstep: INCSTEP /// Modulation period @ReadWrite(bits: 0..<13) - var modper: MODPER + public var modper: MODPER } /// PLLI2S configuration register @Register(bitWidth: 32) - struct PLLI2SCFGR { + public struct PLLI2SCFGR { /// PLLI2S division factor for I2S clocks @ReadWrite(bits: 28..<31) - var plli2sr: PLLI2SR + public var plli2sr: PLLI2SR /// PLLI2S division factor for SAI1 clock @ReadWrite(bits: 24..<28) - var plli2sq: PLLI2SQ + public var plli2sq: PLLI2SQ /// PLLI2S multiplication factor for VCO @ReadWrite(bits: 6..<15) - var plli2sn: PLLI2SN + public var plli2sn: PLLI2SN /// PLLI2S division factor for SPDIFRX clock @ReadWrite(bits: 16..<18, as: PLLI2SPValues.self) - var plli2sp: PLLI2SP + public var plli2sp: PLLI2SP } /// PLL configuration register @Register(bitWidth: 32) - struct PLLSAICFGR { + public struct PLLSAICFGR { /// PLLSAI division factor for VCO @ReadWrite(bits: 6..<15) - var pllsain: PLLSAIN + public var pllsain: PLLSAIN /// PLLSAI division factor for 48MHz clock @ReadWrite(bits: 16..<18, as: PLLSAIPValues.self) - var pllsaip: PLLSAIP + public var pllsaip: PLLSAIP /// PLLSAI division factor for SAI clock @ReadWrite(bits: 24..<28) - var pllsaiq: PLLSAIQ + public var pllsaiq: PLLSAIQ /// PLLSAI division factor for LCD clock @ReadWrite(bits: 28..<31) - var pllsair: PLLSAIR + public var pllsair: PLLSAIR } /// dedicated clocks configuration register @Register(bitWidth: 32) - struct DCKCFGR1 { + public struct DCKCFGR1 { /// PLLI2S division factor for SAI1 clock @ReadWrite(bits: 0..<5, as: PLLI2SDIVQValues.self) - var plli2sdivq: PLLI2SDIVQ + public var plli2sdivq: PLLI2SDIVQ /// PLLSAI division factor for SAI1 clock @ReadWrite(bits: 8..<13, as: PLLSAIDIVQValues.self) - var pllsaidivq: PLLSAIDIVQ + public var pllsaidivq: PLLSAIDIVQ /// division factor for LCD_CLK @ReadWrite(bits: 16..<18, as: PLLSAIDIVRValues.self) - var pllsaidivr: PLLSAIDIVR + public var pllsaidivr: PLLSAIDIVR /// SAI1 clock source selection @ReadWrite(bits: 20..<22, as: SAI1SELValues.self) - var sai1sel: SAI1SEL + public var sai1sel: SAI1SEL /// SAI2 clock source selection @ReadWrite(bits: 22..<24, as: SAI2SELValues.self) - var sai2sel: SAI2SEL + public var sai2sel: SAI2SEL /// Timers clocks prescalers selection @ReadWrite(bits: 24..<25, as: TIMPREValues.self) - var timpre: TIMPRE + public var timpre: TIMPRE } /// dedicated clocks configuration register @Register(bitWidth: 32) - struct DCKCFGR2 { + public struct DCKCFGR2 { /// USART 1 clock source selection @ReadWrite(bits: 0..<2, as: USART1SELValues.self) - var usart1sel: USART1SEL + public var usart1sel: USART1SEL /// USART 2 clock source selection @ReadWrite(bits: 2..<4, as: USART2SELValues.self) - var usart2sel: USART2SEL + public var usart2sel: USART2SEL /// USART 3 clock source selection @ReadWrite(bits: 4..<6) - var usart3sel: USART3SEL + public var usart3sel: USART3SEL /// UART 4 clock source selection @ReadWrite(bits: 6..<8) - var uart4sel: UART4SEL + public var uart4sel: UART4SEL /// UART 5 clock source selection @ReadWrite(bits: 8..<10) - var uart5sel: UART5SEL + public var uart5sel: UART5SEL /// USART 6 clock source selection @ReadWrite(bits: 10..<12) - var usart6sel: USART6SEL + public var usart6sel: USART6SEL /// UART 7 clock source selection @ReadWrite(bits: 12..<14) - var uart7sel: UART7SEL + public var uart7sel: UART7SEL /// UART 8 clock source selection @ReadWrite(bits: 14..<16) - var uart8sel: UART8SEL + public var uart8sel: UART8SEL /// I2C1 clock source selection @ReadWrite(bits: 16..<18, as: I2C1SELValues.self) - var i2c1sel: I2C1SEL + public var i2c1sel: I2C1SEL /// I2C2 clock source selection @ReadWrite(bits: 18..<20) - var i2c2sel: I2C2SEL + public var i2c2sel: I2C2SEL /// I2C3 clock source selection @ReadWrite(bits: 20..<22) - var i2c3sel: I2C3SEL + public var i2c3sel: I2C3SEL /// I2C4 clock source selection @ReadWrite(bits: 22..<24) - var i2c4sel: I2C4SEL + public var i2c4sel: I2C4SEL /// Low power timer 1 clock source selection @ReadWrite(bits: 24..<26, as: LPTIM1SELValues.self) - var lptim1sel: LPTIM1SEL + public var lptim1sel: LPTIM1SEL /// HDMI-CEC clock source selection @ReadWrite(bits: 26..<27, as: CECSELValues.self) - var cecsel: CECSEL + public var cecsel: CECSEL /// 48MHz clock source selection @ReadWrite(bits: 27..<28, as: CK48MSELValues.self) - var ck48msel: CK48MSEL + public var ck48msel: CK48MSEL /// SDMMC clock source selection @ReadWrite(bits: 28..<29, as: SDMMC1SELValues.self) - var sdmmc1sel: SDMMC1SEL + public var sdmmc1sel: SDMMC1SEL } } extension RCC.CR { - struct CSSONValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CSSONValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Clock security system disabled (clock detector OFF) - static let Off = Self(rawValue: 0x0) + public static let Off = Self(rawValue: 0x0) /// Clock security system enable (clock detector ON if the HSE is ready, OFF if not) - static let On = Self(rawValue: 0x1) + public static let On = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CR { - struct HSEBYPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct HSEBYPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// HSE crystal oscillator not bypassed - static let NotBypassed = Self(rawValue: 0x0) + public static let NotBypassed = Self(rawValue: 0x0) /// HSE crystal oscillator bypassed with external clock - static let Bypassed = Self(rawValue: 0x1) + public static let Bypassed = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CR { - struct HSIONValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct HSIONValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Clock Off - static let Off = Self(rawValue: 0x0) + public static let Off = Self(rawValue: 0x0) /// Clock On - static let On = Self(rawValue: 0x1) + public static let On = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.PLLCFGR { - struct PLLSRCValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct PLLSRCValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// HSI clock selected as PLL and PLLI2S clock entry - static let HSI = Self(rawValue: 0x0) + public static let HSI = Self(rawValue: 0x0) /// HSE oscillator clock selected as PLL and PLLI2S clock entry - static let HSE = Self(rawValue: 0x1) + public static let HSE = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.PLLCFGR { - struct PLLPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct PLLPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// PLLP=2 - static let Div2 = Self(rawValue: 0x0) + public static let Div2 = Self(rawValue: 0x0) /// PLLP=4 - static let Div4 = Self(rawValue: 0x1) + public static let Div4 = Self(rawValue: 0x1) /// PLLP=6 - static let Div6 = Self(rawValue: 0x2) + public static let Div6 = Self(rawValue: 0x2) /// PLLP=8 - static let Div8 = Self(rawValue: 0x3) + public static let Div8 = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CFGR { - struct MCO2Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct MCO2Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// System clock (SYSCLK) selected - static let SYSCLK = Self(rawValue: 0x0) + public static let SYSCLK = Self(rawValue: 0x0) /// PLLI2S clock selected - static let PLLI2S = Self(rawValue: 0x1) + public static let PLLI2S = Self(rawValue: 0x1) /// HSE oscillator clock selected - static let HSE = Self(rawValue: 0x2) + public static let HSE = Self(rawValue: 0x2) /// PLL clock selected - static let PLL = Self(rawValue: 0x3) + public static let PLL = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CFGR { - struct MCO1PREValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 3 + public struct MCO1PREValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 3 /// No division - static let Div1 = Self(rawValue: 0x0) + public static let Div1 = Self(rawValue: 0x0) /// Division by 2 - static let Div2 = Self(rawValue: 0x4) + public static let Div2 = Self(rawValue: 0x4) /// Division by 3 - static let Div3 = Self(rawValue: 0x5) + public static let Div3 = Self(rawValue: 0x5) /// Division by 4 - static let Div4 = Self(rawValue: 0x6) + public static let Div4 = Self(rawValue: 0x6) /// Division by 5 - static let Div5 = Self(rawValue: 0x7) + public static let Div5 = Self(rawValue: 0x7) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CFGR { - struct I2SSRCValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct I2SSRCValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// PLLI2S clock used as I2S clock source - static let PLLI2S = Self(rawValue: 0x0) + public static let PLLI2S = Self(rawValue: 0x0) /// External clock mapped on the I2S_CKIN pin used as I2S clock source - static let CKIN = Self(rawValue: 0x1) + public static let CKIN = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CFGR { - struct MCO1Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct MCO1Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// HSI clock selected - static let HSI = Self(rawValue: 0x0) + public static let HSI = Self(rawValue: 0x0) /// LSE oscillator selected - static let LSE = Self(rawValue: 0x1) + public static let LSE = Self(rawValue: 0x1) /// HSE oscillator clock selected - static let HSE = Self(rawValue: 0x2) + public static let HSE = Self(rawValue: 0x2) /// PLL clock selected - static let PLL = Self(rawValue: 0x3) + public static let PLL = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CFGR { - struct PPRE1Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 3 + public struct PPRE1Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 3 /// HCLK not divided - static let Div1 = Self(rawValue: 0x0) + public static let Div1 = Self(rawValue: 0x0) /// HCLK divided by 2 - static let Div2 = Self(rawValue: 0x4) + public static let Div2 = Self(rawValue: 0x4) /// HCLK divided by 4 - static let Div4 = Self(rawValue: 0x5) + public static let Div4 = Self(rawValue: 0x5) /// HCLK divided by 8 - static let Div8 = Self(rawValue: 0x6) + public static let Div8 = Self(rawValue: 0x6) /// HCLK divided by 16 - static let Div16 = Self(rawValue: 0x7) + public static let Div16 = Self(rawValue: 0x7) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CFGR { - struct HPREValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 4 + public struct HPREValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 4 /// SYSCLK not divided - static let Div1 = Self(rawValue: 0x0) + public static let Div1 = Self(rawValue: 0x0) /// SYSCLK divided by 2 - static let Div2 = Self(rawValue: 0x8) + public static let Div2 = Self(rawValue: 0x8) /// SYSCLK divided by 4 - static let Div4 = Self(rawValue: 0x9) + public static let Div4 = Self(rawValue: 0x9) /// SYSCLK divided by 8 - static let Div8 = Self(rawValue: 0xa) + public static let Div8 = Self(rawValue: 0xa) /// SYSCLK divided by 16 - static let Div16 = Self(rawValue: 0xb) + public static let Div16 = Self(rawValue: 0xb) /// SYSCLK divided by 64 - static let Div64 = Self(rawValue: 0xc) + public static let Div64 = Self(rawValue: 0xc) /// SYSCLK divided by 128 - static let Div128 = Self(rawValue: 0xd) + public static let Div128 = Self(rawValue: 0xd) /// SYSCLK divided by 256 - static let Div256 = Self(rawValue: 0xe) + public static let Div256 = Self(rawValue: 0xe) /// SYSCLK divided by 512 - static let Div512 = Self(rawValue: 0xf) + public static let Div512 = Self(rawValue: 0xf) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CFGR { - struct SWValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct SWValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// HSI selected as system clock - static let HSI = Self(rawValue: 0x0) + public static let HSI = Self(rawValue: 0x0) /// HSE selected as system clock - static let HSE = Self(rawValue: 0x1) + public static let HSE = Self(rawValue: 0x1) /// PLL selected as system clock - static let PLL = Self(rawValue: 0x2) + public static let PLL = Self(rawValue: 0x2) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CIR { - struct LSIRDYIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LSIRDYIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Interrupt enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB1RSTR { - struct GPIOARSTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct GPIOARSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Reset the selected module - static let Reset = Self(rawValue: 0x1) + public static let Reset = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB2RSTR { - struct DCMIRSTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DCMIRSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Reset the selected module - static let Reset = Self(rawValue: 0x1) + public static let Reset = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB3RSTR { - struct FMCRSTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct FMCRSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Reset the selected module - static let Reset = Self(rawValue: 0x1) + public static let Reset = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.APB1RSTR { - struct TIM2RSTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TIM2RSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Reset the selected module - static let Reset = Self(rawValue: 0x1) + public static let Reset = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.APB2RSTR { - struct TIM1RSTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TIM1RSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Reset the selected module - static let Reset = Self(rawValue: 0x1) + public static let Reset = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB1ENR { - struct GPIOAENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct GPIOAENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// The selected clock is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// The selected clock is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB2ENR { - struct DCMIENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DCMIENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// The selected clock is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// The selected clock is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB3ENR { - struct FMCENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct FMCENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// The selected clock is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// The selected clock is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.APB1ENR { - struct TIM2ENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TIM2ENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// The selected clock is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// The selected clock is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.APB2ENR { - struct TIM1ENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TIM1ENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// The selected clock is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// The selected clock is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB1LPENR { - struct GPIOALPENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct GPIOALPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Selected module is disabled during Sleep mode - static let DisabledInSleep = Self(rawValue: 0x0) + public static let DisabledInSleep = Self(rawValue: 0x0) /// Selected module is enabled during Sleep mode - static let EnabledInSleep = Self(rawValue: 0x1) + public static let EnabledInSleep = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB2LPENR { - struct DCMILPENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DCMILPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Selected module is disabled during Sleep mode - static let DisabledInSleep = Self(rawValue: 0x0) + public static let DisabledInSleep = Self(rawValue: 0x0) /// Selected module is enabled during Sleep mode - static let EnabledInSleep = Self(rawValue: 0x1) + public static let EnabledInSleep = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB3LPENR { - struct FMCLPENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct FMCLPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Selected module is disabled during Sleep mode - static let DisabledInSleep = Self(rawValue: 0x0) + public static let DisabledInSleep = Self(rawValue: 0x0) /// Selected module is enabled during Sleep mode - static let EnabledInSleep = Self(rawValue: 0x1) + public static let EnabledInSleep = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.APB1LPENR { - struct TIM2LPENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TIM2LPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Selected module is disabled during Sleep mode - static let DisabledInSleep = Self(rawValue: 0x0) + public static let DisabledInSleep = Self(rawValue: 0x0) /// Selected module is enabled during Sleep mode - static let EnabledInSleep = Self(rawValue: 0x1) + public static let EnabledInSleep = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.APB2LPENR { - struct TIM1LPENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TIM1LPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Selected module is disabled during Sleep mode - static let DisabledInSleep = Self(rawValue: 0x0) + public static let DisabledInSleep = Self(rawValue: 0x0) /// Selected module is enabled during Sleep mode - static let EnabledInSleep = Self(rawValue: 0x1) + public static let EnabledInSleep = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.BDCR { - struct BDRSTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct BDRSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Reset not activated - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Reset the entire RTC domain - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.BDCR { - struct RTCENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct RTCENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// RTC clock disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// RTC clock enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.BDCR { - struct LSEBYPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LSEBYPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// LSE crystal oscillator not bypassed - static let NotBypassed = Self(rawValue: 0x0) + public static let NotBypassed = Self(rawValue: 0x0) /// LSE crystal oscillator bypassed with external clock - static let Bypassed = Self(rawValue: 0x1) + public static let Bypassed = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.BDCR { - struct LSEONValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LSEONValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// LSE oscillator Off - static let Off = Self(rawValue: 0x0) + public static let Off = Self(rawValue: 0x0) /// LSE oscillator On - static let On = Self(rawValue: 0x1) + public static let On = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.BDCR { - struct LSEDRVValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct LSEDRVValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// Low drive capacity - static let Low = Self(rawValue: 0x0) + public static let Low = Self(rawValue: 0x0) /// Medium-high drive capacity - static let MediumHigh = Self(rawValue: 0x1) + public static let MediumHigh = Self(rawValue: 0x1) /// Medium-low drive capacity - static let MediumLow = Self(rawValue: 0x2) + public static let MediumLow = Self(rawValue: 0x2) /// High drive capacity - static let High = Self(rawValue: 0x3) + public static let High = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.BDCR { - struct RTCSELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct RTCSELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// No clock - static let NoClock = Self(rawValue: 0x0) + public static let NoClock = Self(rawValue: 0x0) /// LSE oscillator clock used as RTC clock - static let LSE = Self(rawValue: 0x1) + public static let LSE = Self(rawValue: 0x1) /// LSI oscillator clock used as RTC clock - static let LSI = Self(rawValue: 0x2) + public static let LSI = Self(rawValue: 0x2) /// HSE oscillator clock divided by a prescaler used as RTC clock - static let HSE = Self(rawValue: 0x3) + public static let HSE = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CSR { - struct LSIONValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LSIONValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// LSI oscillator Off - static let Off = Self(rawValue: 0x0) + public static let Off = Self(rawValue: 0x0) /// LSI oscillator On - static let On = Self(rawValue: 0x1) + public static let On = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.SSCGR { - struct SSCGENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct SSCGENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Spread spectrum modulation disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Spread spectrum modulation enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.SSCGR { - struct SPREADSELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct SPREADSELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Center spread - static let Center = Self(rawValue: 0x0) + public static let Center = Self(rawValue: 0x0) /// Down spread - static let Down = Self(rawValue: 0x1) + public static let Down = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.PLLI2SCFGR { - struct PLLI2SPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct PLLI2SPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// PLL*P=2 - static let Div2 = Self(rawValue: 0x0) + public static let Div2 = Self(rawValue: 0x0) /// PLL*P=4 - static let Div4 = Self(rawValue: 0x1) + public static let Div4 = Self(rawValue: 0x1) /// PLL*P=6 - static let Div6 = Self(rawValue: 0x2) + public static let Div6 = Self(rawValue: 0x2) /// PLL*P=8 - static let Div8 = Self(rawValue: 0x3) + public static let Div8 = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.PLLSAICFGR { - struct PLLSAIPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct PLLSAIPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// PLL*P=2 - static let Div2 = Self(rawValue: 0x0) + public static let Div2 = Self(rawValue: 0x0) /// PLL*P=4 - static let Div4 = Self(rawValue: 0x1) + public static let Div4 = Self(rawValue: 0x1) /// PLL*P=6 - static let Div6 = Self(rawValue: 0x2) + public static let Div6 = Self(rawValue: 0x2) /// PLL*P=8 - static let Div8 = Self(rawValue: 0x3) + public static let Div8 = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR1 { - struct PLLI2SDIVQValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 5 + public struct PLLI2SDIVQValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 5 /// PLLI2SDIVQ = /1 - static let Div1 = Self(rawValue: 0x0) + public static let Div1 = Self(rawValue: 0x0) /// PLLI2SDIVQ = /2 - static let Div2 = Self(rawValue: 0x1) + public static let Div2 = Self(rawValue: 0x1) /// PLLI2SDIVQ = /3 - static let Div3 = Self(rawValue: 0x2) + public static let Div3 = Self(rawValue: 0x2) /// PLLI2SDIVQ = /4 - static let Div4 = Self(rawValue: 0x3) + public static let Div4 = Self(rawValue: 0x3) /// PLLI2SDIVQ = /5 - static let Div5 = Self(rawValue: 0x4) + public static let Div5 = Self(rawValue: 0x4) /// PLLI2SDIVQ = /6 - static let Div6 = Self(rawValue: 0x5) + public static let Div6 = Self(rawValue: 0x5) /// PLLI2SDIVQ = /7 - static let Div7 = Self(rawValue: 0x6) + public static let Div7 = Self(rawValue: 0x6) /// PLLI2SDIVQ = /8 - static let Div8 = Self(rawValue: 0x7) + public static let Div8 = Self(rawValue: 0x7) /// PLLI2SDIVQ = /9 - static let Div9 = Self(rawValue: 0x8) + public static let Div9 = Self(rawValue: 0x8) /// PLLI2SDIVQ = /10 - static let Div10 = Self(rawValue: 0x9) + public static let Div10 = Self(rawValue: 0x9) /// PLLI2SDIVQ = /11 - static let Div11 = Self(rawValue: 0xa) + public static let Div11 = Self(rawValue: 0xa) /// PLLI2SDIVQ = /12 - static let Div12 = Self(rawValue: 0xb) + public static let Div12 = Self(rawValue: 0xb) /// PLLI2SDIVQ = /13 - static let Div13 = Self(rawValue: 0xc) + public static let Div13 = Self(rawValue: 0xc) /// PLLI2SDIVQ = /14 - static let Div14 = Self(rawValue: 0xd) + public static let Div14 = Self(rawValue: 0xd) /// PLLI2SDIVQ = /15 - static let Div15 = Self(rawValue: 0xe) + public static let Div15 = Self(rawValue: 0xe) /// PLLI2SDIVQ = /16 - static let Div16 = Self(rawValue: 0xf) + public static let Div16 = Self(rawValue: 0xf) /// PLLI2SDIVQ = /17 - static let Div17 = Self(rawValue: 0x10) + public static let Div17 = Self(rawValue: 0x10) /// PLLI2SDIVQ = /18 - static let Div18 = Self(rawValue: 0x11) + public static let Div18 = Self(rawValue: 0x11) /// PLLI2SDIVQ = /19 - static let Div19 = Self(rawValue: 0x12) + public static let Div19 = Self(rawValue: 0x12) /// PLLI2SDIVQ = /20 - static let Div20 = Self(rawValue: 0x13) + public static let Div20 = Self(rawValue: 0x13) /// PLLI2SDIVQ = /21 - static let Div21 = Self(rawValue: 0x14) + public static let Div21 = Self(rawValue: 0x14) /// PLLI2SDIVQ = /22 - static let Div22 = Self(rawValue: 0x15) + public static let Div22 = Self(rawValue: 0x15) /// PLLI2SDIVQ = /23 - static let Div23 = Self(rawValue: 0x16) + public static let Div23 = Self(rawValue: 0x16) /// PLLI2SDIVQ = /24 - static let Div24 = Self(rawValue: 0x17) + public static let Div24 = Self(rawValue: 0x17) /// PLLI2SDIVQ = /25 - static let Div25 = Self(rawValue: 0x18) + public static let Div25 = Self(rawValue: 0x18) /// PLLI2SDIVQ = /26 - static let Div26 = Self(rawValue: 0x19) + public static let Div26 = Self(rawValue: 0x19) /// PLLI2SDIVQ = /27 - static let Div27 = Self(rawValue: 0x1a) + public static let Div27 = Self(rawValue: 0x1a) /// PLLI2SDIVQ = /28 - static let Div28 = Self(rawValue: 0x1b) + public static let Div28 = Self(rawValue: 0x1b) /// PLLI2SDIVQ = /29 - static let Div29 = Self(rawValue: 0x1c) + public static let Div29 = Self(rawValue: 0x1c) /// PLLI2SDIVQ = /30 - static let Div30 = Self(rawValue: 0x1d) + public static let Div30 = Self(rawValue: 0x1d) /// PLLI2SDIVQ = /31 - static let Div31 = Self(rawValue: 0x1e) + public static let Div31 = Self(rawValue: 0x1e) /// PLLI2SDIVQ = /32 - static let Div32 = Self(rawValue: 0x1f) + public static let Div32 = Self(rawValue: 0x1f) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR1 { - struct PLLSAIDIVQValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 5 + public struct PLLSAIDIVQValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 5 /// PLLSAIDIVQ = /1 - static let Div1 = Self(rawValue: 0x0) + public static let Div1 = Self(rawValue: 0x0) /// PLLSAIDIVQ = /2 - static let Div2 = Self(rawValue: 0x1) + public static let Div2 = Self(rawValue: 0x1) /// PLLSAIDIVQ = /3 - static let Div3 = Self(rawValue: 0x2) + public static let Div3 = Self(rawValue: 0x2) /// PLLSAIDIVQ = /4 - static let Div4 = Self(rawValue: 0x3) + public static let Div4 = Self(rawValue: 0x3) /// PLLSAIDIVQ = /5 - static let Div5 = Self(rawValue: 0x4) + public static let Div5 = Self(rawValue: 0x4) /// PLLSAIDIVQ = /6 - static let Div6 = Self(rawValue: 0x5) + public static let Div6 = Self(rawValue: 0x5) /// PLLSAIDIVQ = /7 - static let Div7 = Self(rawValue: 0x6) + public static let Div7 = Self(rawValue: 0x6) /// PLLSAIDIVQ = /8 - static let Div8 = Self(rawValue: 0x7) + public static let Div8 = Self(rawValue: 0x7) /// PLLSAIDIVQ = /9 - static let Div9 = Self(rawValue: 0x8) + public static let Div9 = Self(rawValue: 0x8) /// PLLSAIDIVQ = /10 - static let Div10 = Self(rawValue: 0x9) + public static let Div10 = Self(rawValue: 0x9) /// PLLSAIDIVQ = /11 - static let Div11 = Self(rawValue: 0xa) + public static let Div11 = Self(rawValue: 0xa) /// PLLSAIDIVQ = /12 - static let Div12 = Self(rawValue: 0xb) + public static let Div12 = Self(rawValue: 0xb) /// PLLSAIDIVQ = /13 - static let Div13 = Self(rawValue: 0xc) + public static let Div13 = Self(rawValue: 0xc) /// PLLSAIDIVQ = /14 - static let Div14 = Self(rawValue: 0xd) + public static let Div14 = Self(rawValue: 0xd) /// PLLSAIDIVQ = /15 - static let Div15 = Self(rawValue: 0xe) + public static let Div15 = Self(rawValue: 0xe) /// PLLSAIDIVQ = /16 - static let Div16 = Self(rawValue: 0xf) + public static let Div16 = Self(rawValue: 0xf) /// PLLSAIDIVQ = /17 - static let Div17 = Self(rawValue: 0x10) + public static let Div17 = Self(rawValue: 0x10) /// PLLSAIDIVQ = /18 - static let Div18 = Self(rawValue: 0x11) + public static let Div18 = Self(rawValue: 0x11) /// PLLSAIDIVQ = /19 - static let Div19 = Self(rawValue: 0x12) + public static let Div19 = Self(rawValue: 0x12) /// PLLSAIDIVQ = /20 - static let Div20 = Self(rawValue: 0x13) + public static let Div20 = Self(rawValue: 0x13) /// PLLSAIDIVQ = /21 - static let Div21 = Self(rawValue: 0x14) + public static let Div21 = Self(rawValue: 0x14) /// PLLSAIDIVQ = /22 - static let Div22 = Self(rawValue: 0x15) + public static let Div22 = Self(rawValue: 0x15) /// PLLSAIDIVQ = /23 - static let Div23 = Self(rawValue: 0x16) + public static let Div23 = Self(rawValue: 0x16) /// PLLSAIDIVQ = /24 - static let Div24 = Self(rawValue: 0x17) + public static let Div24 = Self(rawValue: 0x17) /// PLLSAIDIVQ = /25 - static let Div25 = Self(rawValue: 0x18) + public static let Div25 = Self(rawValue: 0x18) /// PLLSAIDIVQ = /26 - static let Div26 = Self(rawValue: 0x19) + public static let Div26 = Self(rawValue: 0x19) /// PLLSAIDIVQ = /27 - static let Div27 = Self(rawValue: 0x1a) + public static let Div27 = Self(rawValue: 0x1a) /// PLLSAIDIVQ = /28 - static let Div28 = Self(rawValue: 0x1b) + public static let Div28 = Self(rawValue: 0x1b) /// PLLSAIDIVQ = /29 - static let Div29 = Self(rawValue: 0x1c) + public static let Div29 = Self(rawValue: 0x1c) /// PLLSAIDIVQ = /30 - static let Div30 = Self(rawValue: 0x1d) + public static let Div30 = Self(rawValue: 0x1d) /// PLLSAIDIVQ = /31 - static let Div31 = Self(rawValue: 0x1e) + public static let Div31 = Self(rawValue: 0x1e) /// PLLSAIDIVQ = /32 - static let Div32 = Self(rawValue: 0x1f) + public static let Div32 = Self(rawValue: 0x1f) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR1 { - struct PLLSAIDIVRValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct PLLSAIDIVRValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// PLLSAIDIVR = /2 - static let Div2 = Self(rawValue: 0x0) + public static let Div2 = Self(rawValue: 0x0) /// PLLSAIDIVR = /4 - static let Div4 = Self(rawValue: 0x1) + public static let Div4 = Self(rawValue: 0x1) /// PLLSAIDIVR = /8 - static let Div8 = Self(rawValue: 0x2) + public static let Div8 = Self(rawValue: 0x2) /// PLLSAIDIVR = /16 - static let Div16 = Self(rawValue: 0x3) + public static let Div16 = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR1 { - struct SAI1SELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct SAI1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - static let PLLSAI = Self(rawValue: 0x0) + public static let PLLSAI = Self(rawValue: 0x0) /// SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - static let PLLI2S = Self(rawValue: 0x1) + public static let PLLI2S = Self(rawValue: 0x1) /// SAI1 clock frequency = Alternate function input frequency - static let AFIF = Self(rawValue: 0x2) + public static let AFIF = Self(rawValue: 0x2) /// SAI1 clock frequency = HSI or HSE - static let HSI_HSE = Self(rawValue: 0x3) + public static let HSI_HSE = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR1 { - struct SAI2SELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct SAI2SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - static let PLLSAI = Self(rawValue: 0x0) + public static let PLLSAI = Self(rawValue: 0x0) /// SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - static let PLLI2S = Self(rawValue: 0x1) + public static let PLLI2S = Self(rawValue: 0x1) /// SAI2 clock frequency = Alternate function input frequency - static let AFIF = Self(rawValue: 0x2) + public static let AFIF = Self(rawValue: 0x2) /// SAI2 clock frequency = HSI or HSE - static let HSI_HSE = Self(rawValue: 0x3) + public static let HSI_HSE = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR1 { - struct TIMPREValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TIMPREValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx - static let Mul1Or2 = Self(rawValue: 0x0) + public static let Mul1Or2 = Self(rawValue: 0x0) /// If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx - static let Mul1Or4 = Self(rawValue: 0x1) + public static let Mul1Or4 = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR2 { - struct USART1SELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct USART1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// APB2 clock (PCLK2) is selected as USART clock - static let APB2 = Self(rawValue: 0x0) + public static let APB2 = Self(rawValue: 0x0) /// System clock is selected as USART clock - static let SYSCLK = Self(rawValue: 0x1) + public static let SYSCLK = Self(rawValue: 0x1) /// HSI clock is selected as USART clock - static let HSI = Self(rawValue: 0x2) + public static let HSI = Self(rawValue: 0x2) /// LSE clock is selected as USART clock - static let LSE = Self(rawValue: 0x3) + public static let LSE = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR2 { - struct USART2SELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct USART2SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// APB1 clock (PCLK1) is selected as USART clock - static let APB1 = Self(rawValue: 0x0) + public static let APB1 = Self(rawValue: 0x0) /// System clock is selected as USART clock - static let SYSCLK = Self(rawValue: 0x1) + public static let SYSCLK = Self(rawValue: 0x1) /// HSI clock is selected as USART clock - static let HSI = Self(rawValue: 0x2) + public static let HSI = Self(rawValue: 0x2) /// LSE clock is selected as USART clock - static let LSE = Self(rawValue: 0x3) + public static let LSE = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR2 { - struct I2C1SELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct I2C1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// APB clock selected as I2C clock - static let APB = Self(rawValue: 0x0) + public static let APB = Self(rawValue: 0x0) /// System clock selected as I2C clock - static let SYSCLK = Self(rawValue: 0x1) + public static let SYSCLK = Self(rawValue: 0x1) /// HSI clock selected as I2C clock - static let HSI = Self(rawValue: 0x2) + public static let HSI = Self(rawValue: 0x2) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR2 { - struct LPTIM1SELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct LPTIM1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// APB1 clock (PCLK1) selected as LPTILM1 clock - static let APB1 = Self(rawValue: 0x0) + public static let APB1 = Self(rawValue: 0x0) /// LSI clock is selected as LPTILM1 clock - static let LSI = Self(rawValue: 0x1) + public static let LSI = Self(rawValue: 0x1) /// HSI clock is selected as LPTILM1 clock - static let HSI = Self(rawValue: 0x2) + public static let HSI = Self(rawValue: 0x2) /// LSE clock is selected as LPTILM1 clock - static let LSE = Self(rawValue: 0x3) + public static let LSE = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR2 { - struct CECSELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CECSELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// LSE clock is selected as HDMI-CEC clock - static let LSE = Self(rawValue: 0x0) + public static let LSE = Self(rawValue: 0x0) /// HSI divided by 488 clock is selected as HDMI-CEC clock - static let HSI_Div488 = Self(rawValue: 0x1) + public static let HSI_Div488 = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR2 { - struct CK48MSELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CK48MSELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// 48MHz clock from PLL is selected - static let PLL = Self(rawValue: 0x0) + public static let PLL = Self(rawValue: 0x0) /// 48MHz clock from PLLSAI is selected - static let PLLSAI = Self(rawValue: 0x1) + public static let PLLSAI = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR2 { - struct SDMMC1SELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct SDMMC1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// 48 MHz clock is selected as SD clock - static let CK48M = Self(rawValue: 0x0) + public static let CK48M = Self(rawValue: 0x0) /// System clock is selected as SD clock - static let SYSCLK = Self(rawValue: 0x1) + public static let SYSCLK = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } diff --git a/stm32-neopixel/Sources/STM32F7X6/SPI1.swift b/stm32-neopixel/Sources/STM32F7X6/SPI1.swift new file mode 100644 index 00000000..c08d7a60 --- /dev/null +++ b/stm32-neopixel/Sources/STM32F7X6/SPI1.swift @@ -0,0 +1,1043 @@ +// Generated by svd2swift. + +import MMIO + +/// Serial peripheral interface +@RegisterBlock +public struct SPI1 { + /// control register 1 + @RegisterBlock(offset: 0x0) + public var cr1: Register + + /// control register 2 + @RegisterBlock(offset: 0x4) + public var cr2: Register + + /// status register + @RegisterBlock(offset: 0x8) + public var sr: Register + + /// data register + @RegisterBlock(offset: 0xc) + public var dr: Register + + /// CRC polynomial register + @RegisterBlock(offset: 0x10) + public var crcpr: Register + + /// RX CRC register + @RegisterBlock(offset: 0x14) + public var rxcrcr: Register + + /// TX CRC register + @RegisterBlock(offset: 0x18) + public var txcrcr: Register + + /// I2S configuration register + @RegisterBlock(offset: 0x1c) + public var i2scfgr: Register + + /// I2S prescaler register + @RegisterBlock(offset: 0x20) + public var i2spr: Register +} + +extension SPI1 { + /// control register 1 + @Register(bitWidth: 32) + public struct CR1 { + /// Bidirectional data mode enable + @ReadWrite(bits: 15..<16, as: BIDIMODEValues.self) + public var bidimode: BIDIMODE + + /// Output enable in bidirectional mode + @ReadWrite(bits: 14..<15, as: BIDIOEValues.self) + public var bidioe: BIDIOE + + /// Hardware CRC calculation enable + @ReadWrite(bits: 13..<14, as: CRCENValues.self) + public var crcen: CRCEN + + /// CRC transfer next + @ReadWrite(bits: 12..<13, as: CRCNEXTValues.self) + public var crcnext: CRCNEXT + + /// CRC length + @ReadWrite(bits: 11..<12, as: CRCLValues.self) + public var crcl: CRCL + + /// Receive only + @ReadWrite(bits: 10..<11, as: RXONLYValues.self) + public var rxonly: RXONLY + + /// Software slave management + @ReadWrite(bits: 9..<10, as: SSMValues.self) + public var ssm: SSM + + /// Internal slave select + @ReadWrite(bits: 8..<9, as: SSIValues.self) + public var ssi: SSI + + /// Frame format + @ReadWrite(bits: 7..<8, as: LSBFIRSTValues.self) + public var lsbfirst: LSBFIRST + + /// SPI enable + @ReadWrite(bits: 6..<7, as: SPEValues.self) + public var spe: SPE + + /// Baud rate control + @ReadWrite(bits: 3..<6, as: BRValues.self) + public var br: BR + + /// Master selection + @ReadWrite(bits: 2..<3, as: MSTRValues.self) + public var mstr: MSTR + + /// Clock polarity + @ReadWrite(bits: 1..<2, as: CPOLValues.self) + public var cpol: CPOL + + /// Clock phase + @ReadWrite(bits: 0..<1, as: CPHAValues.self) + public var cpha: CPHA + } + + /// control register 2 + @Register(bitWidth: 32) + public struct CR2 { + /// Rx buffer DMA enable + @ReadWrite(bits: 0..<1, as: RXDMAENValues.self) + public var rxdmaen: RXDMAEN + + /// Tx buffer DMA enable + @ReadWrite(bits: 1..<2, as: TXDMAENValues.self) + public var txdmaen: TXDMAEN + + /// SS output enable + @ReadWrite(bits: 2..<3, as: SSOEValues.self) + public var ssoe: SSOE + + /// NSS pulse management + @ReadWrite(bits: 3..<4, as: NSSPValues.self) + public var nssp: NSSP + + /// Frame format + @ReadWrite(bits: 4..<5, as: FRFValues.self) + public var frf: FRF + + /// Error interrupt enable + @ReadWrite(bits: 5..<6, as: ERRIEValues.self) + public var errie: ERRIE + + /// RX buffer not empty interrupt enable + @ReadWrite(bits: 6..<7, as: RXNEIEValues.self) + public var rxneie: RXNEIE + + /// Tx buffer empty interrupt enable + @ReadWrite(bits: 7..<8, as: TXEIEValues.self) + public var txeie: TXEIE + + /// Data size + @ReadWrite(bits: 8..<12, as: DSValues.self) + public var ds: DS + + /// FIFO reception threshold + @ReadWrite(bits: 12..<13, as: FRXTHValues.self) + public var frxth: FRXTH + + /// Last DMA transfer for reception + @ReadWrite(bits: 13..<14, as: LDMA_RXValues.self) + public var ldma_rx: LDMA_RX + + /// Last DMA transfer for transmission + @ReadWrite(bits: 14..<15, as: LDMA_TXValues.self) + public var ldma_tx: LDMA_TX + } + + /// status register + @Register(bitWidth: 32) + public struct SR { + /// Frame format error + @ReadOnly(bits: 8..<9) + public var fre: FRE + + /// Busy flag + @ReadOnly(bits: 7..<8) + public var bsy: BSY + + /// Overrun flag + @ReadOnly(bits: 6..<7) + public var ovr: OVR + + /// Mode fault + @ReadOnly(bits: 5..<6) + public var modf: MODF + + /// CRC error flag + @ReadWrite(bits: 4..<5) + public var crcerr: CRCERR + + /// Underrun flag + @ReadOnly(bits: 3..<4) + public var udr: UDR + + /// Channel side + @ReadOnly(bits: 2..<3) + public var chside: CHSIDE + + /// Transmit buffer empty + @ReadOnly(bits: 1..<2) + public var txe: TXE + + /// Receive buffer not empty + @ReadOnly(bits: 0..<1) + public var rxne: RXNE + + /// FIFO reception level + @ReadOnly(bits: 9..<11) + public var frlvl: FRLVL + + /// FIFO Transmission Level + @ReadOnly(bits: 11..<13) + public var ftlvl: FTLVL + } + + /// data register + @Register(bitWidth: 32) + public struct DR { + /// Data register + @ReadWrite(bits: 0..<16) + public var dr_field: DR_FIELD + } + + /// CRC polynomial register + @Register(bitWidth: 32) + public struct CRCPR { + /// CRC polynomial register + @ReadWrite(bits: 0..<16) + public var crcpoly: CRCPOLY + } + + /// RX CRC register + @Register(bitWidth: 32) + public struct RXCRCR { + /// Rx CRC register + @ReadOnly(bits: 0..<16) + public var rxcrc: RxCRC + } + + /// TX CRC register + @Register(bitWidth: 32) + public struct TXCRCR { + /// Tx CRC register + @ReadOnly(bits: 0..<16) + public var txcrc: TxCRC + } + + /// I2S configuration register + @Register(bitWidth: 32) + public struct I2SCFGR { + /// I2S mode selection + @ReadWrite(bits: 11..<12, as: I2SMODValues.self) + public var i2smod: I2SMOD + + /// I2S Enable + @ReadWrite(bits: 10..<11, as: I2SEValues.self) + public var i2se: I2SE + + /// I2S configuration mode + @ReadWrite(bits: 8..<10, as: I2SCFGValues.self) + public var i2scfg: I2SCFG + + /// PCM frame synchronization + @ReadWrite(bits: 7..<8, as: PCMSYNCValues.self) + public var pcmsync: PCMSYNC + + /// I2S standard selection + @ReadWrite(bits: 4..<6, as: I2SSTDValues.self) + public var i2sstd: I2SSTD + + /// Steady state clock polarity + @ReadWrite(bits: 3..<4, as: CKPOLValues.self) + public var ckpol: CKPOL + + /// Data length to be transferred + @ReadWrite(bits: 1..<3, as: DATLENValues.self) + public var datlen: DATLEN + + /// Channel length (number of bits per audio channel) + @ReadWrite(bits: 0..<1, as: CHLENValues.self) + public var chlen: CHLEN + + /// Asynchronous start enable + @ReadWrite(bits: 12..<13) + public var astrten: ASTRTEN + } + + /// I2S prescaler register + @Register(bitWidth: 32) + public struct I2SPR { + /// Master clock output enable + @ReadWrite(bits: 9..<10, as: MCKOEValues.self) + public var mckoe: MCKOE + + /// Odd factor for the prescaler + @ReadWrite(bits: 8..<9, as: ODDValues.self) + public var odd: ODD + + /// I2S Linear prescaler + @ReadWrite(bits: 0..<8) + public var i2sdiv: I2SDIV + } +} + +extension SPI1.CR1 { + public struct BIDIMODEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// 2-line unidirectional data mode selected + public static let Unidirectional = Self(rawValue: 0x0) + + /// 1-line bidirectional data mode selected + public static let Bidirectional = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + public struct BIDIOEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Output disabled (receive-only mode) + public static let OutputDisabled = Self(rawValue: 0x0) + + /// Output enabled (transmit-only mode) + public static let OutputEnabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + public struct CRCENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// CRC calculation disabled + public static let Disabled = Self(rawValue: 0x0) + + /// CRC calculation enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + public struct CRCNEXTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Next transmit value is from Tx buffer + public static let TxBuffer = Self(rawValue: 0x0) + + /// Next transmit value is from Tx CRC register + public static let CRC = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + public struct CRCLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// 8-bit CRC length + public static let EightBit = Self(rawValue: 0x0) + + /// 16-bit CRC length + public static let SixteenBit = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + public struct RXONLYValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Full duplex (Transmit and receive) + public static let FullDuplex = Self(rawValue: 0x0) + + /// Output disabled (Receive-only mode) + public static let OutputDisabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + public struct SSMValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Software slave management disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Software slave management enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + public struct SSIValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored + public static let SlaveSelected = Self(rawValue: 0x0) + + /// 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored + public static let SlaveNotSelected = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + public struct LSBFIRSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Data is transmitted/received with the MSB first + public static let MSBFirst = Self(rawValue: 0x0) + + /// Data is transmitted/received with the LSB first + public static let LSBFirst = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + public struct SPEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Peripheral disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Peripheral enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + public struct BRValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 3 + + /// f_PCLK / 2 + public static let Div2 = Self(rawValue: 0x0) + + /// f_PCLK / 4 + public static let Div4 = Self(rawValue: 0x1) + + /// f_PCLK / 8 + public static let Div8 = Self(rawValue: 0x2) + + /// f_PCLK / 16 + public static let Div16 = Self(rawValue: 0x3) + + /// f_PCLK / 32 + public static let Div32 = Self(rawValue: 0x4) + + /// f_PCLK / 64 + public static let Div64 = Self(rawValue: 0x5) + + /// f_PCLK / 128 + public static let Div128 = Self(rawValue: 0x6) + + /// f_PCLK / 256 + public static let Div256 = Self(rawValue: 0x7) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + public struct MSTRValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Slave configuration + public static let Slave = Self(rawValue: 0x0) + + /// Master configuration + public static let Master = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + public struct CPOLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// CK to 0 when idle + public static let IdleLow = Self(rawValue: 0x0) + + /// CK to 1 when idle + public static let IdleHigh = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR1 { + public struct CPHAValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// The first clock transition is the first data capture edge + public static let FirstEdge = Self(rawValue: 0x0) + + /// The second clock transition is the first data capture edge + public static let SecondEdge = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + public struct RXDMAENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Rx buffer DMA disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Rx buffer DMA enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + public struct TXDMAENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Tx buffer DMA disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Tx buffer DMA enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + public struct SSOEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// SS output is disabled in master mode + public static let Disabled = Self(rawValue: 0x0) + + /// SS output is enabled in master mode + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + public struct NSSPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// No NSS pulse + public static let NoPulse = Self(rawValue: 0x0) + + /// NSS pulse generated + public static let PulseGenerated = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + public struct FRFValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// SPI Motorola mode + public static let Motorola = Self(rawValue: 0x0) + + /// SPI TI mode + public static let TI = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + public struct ERRIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Error interrupt masked + public static let Masked = Self(rawValue: 0x0) + + /// Error interrupt not masked + public static let NotMasked = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + public struct RXNEIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// RXE interrupt masked + public static let Masked = Self(rawValue: 0x0) + + /// RXE interrupt not masked + public static let NotMasked = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + public struct TXEIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// TXE interrupt masked + public static let Masked = Self(rawValue: 0x0) + + /// TXE interrupt not masked + public static let NotMasked = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + public struct DSValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 4 + + /// 4-bit + public static let FourBit = Self(rawValue: 0x3) + + /// 5-bit + public static let FiveBit = Self(rawValue: 0x4) + + /// 6-bit + public static let SixBit = Self(rawValue: 0x5) + + /// 7-bit + public static let SevenBit = Self(rawValue: 0x6) + + /// 8-bit + public static let EightBit = Self(rawValue: 0x7) + + /// 9-bit + public static let NineBit = Self(rawValue: 0x8) + + /// 10-bit + public static let TenBit = Self(rawValue: 0x9) + + /// 11-bit + public static let ElevenBit = Self(rawValue: 0xa) + + /// 12-bit + public static let TwelveBit = Self(rawValue: 0xb) + + /// 13-bit + public static let ThirteenBit = Self(rawValue: 0xc) + + /// 14-bit + public static let FourteenBit = Self(rawValue: 0xd) + + /// 15-bit + public static let FifteenBit = Self(rawValue: 0xe) + + /// 16-bit + public static let SixteenBit = Self(rawValue: 0xf) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + public struct FRXTHValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) + public static let Half = Self(rawValue: 0x0) + + /// RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + public static let Quarter = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + public struct LDMA_RXValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Number of data to transfer for receive is even + public static let Even = Self(rawValue: 0x0) + + /// Number of data to transfer for receive is odd + public static let Odd = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.CR2 { + public struct LDMA_TXValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Number of data to transfer for transmit is even + public static let Even = Self(rawValue: 0x0) + + /// Number of data to transfer for transmit is odd + public static let Odd = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.I2SCFGR { + public struct I2SMODValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// SPI mode is selected + public static let SPIMode = Self(rawValue: 0x0) + + /// I2S mode is selected + public static let I2SMode = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.I2SCFGR { + public struct I2SEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// I2S peripheral is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// I2S peripheral is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.I2SCFGR { + public struct I2SCFGValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// Slave - transmit + public static let SlaveTx = Self(rawValue: 0x0) + + /// Slave - receive + public static let SlaveRx = Self(rawValue: 0x1) + + /// Master - transmit + public static let MasterTx = Self(rawValue: 0x2) + + /// Master - receive + public static let MasterRx = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.I2SCFGR { + public struct PCMSYNCValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Short frame synchronisation + public static let Short = Self(rawValue: 0x0) + + /// Long frame synchronisation + public static let Long = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.I2SCFGR { + public struct I2SSTDValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// I2S Philips standard + public static let Philips = Self(rawValue: 0x0) + + /// MSB justified standard + public static let MSB = Self(rawValue: 0x1) + + /// LSB justified standard + public static let LSB = Self(rawValue: 0x2) + + /// PCM standard + public static let PCM = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.I2SCFGR { + public struct CKPOLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// I2S clock inactive state is low level + public static let IdleLow = Self(rawValue: 0x0) + + /// I2S clock inactive state is high level + public static let IdleHigh = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.I2SCFGR { + public struct DATLENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// 16-bit data length + public static let SixteenBit = Self(rawValue: 0x0) + + /// 24-bit data length + public static let TwentyFourBit = Self(rawValue: 0x1) + + /// 32-bit data length + public static let ThirtyTwoBit = Self(rawValue: 0x2) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.I2SCFGR { + public struct CHLENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// 16-bit wide + public static let SixteenBit = Self(rawValue: 0x0) + + /// 32-bit wide + public static let ThirtyTwoBit = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.I2SPR { + public struct MCKOEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Master clock output is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Master clock output is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension SPI1.I2SPR { + public struct ODDValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Real divider value is I2SDIV * 2 + public static let Even = Self(rawValue: 0x0) + + /// Real divider value is (I2SDIV * 2) + 1 + public static let Odd = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} diff --git a/stm32-neopixel/Sources/Application/Registers/SPI2.swift b/stm32-neopixel/Sources/STM32F7X6/SPI2.swift similarity index 71% rename from stm32-neopixel/Sources/Application/Registers/SPI2.swift rename to stm32-neopixel/Sources/STM32F7X6/SPI2.swift index 2e66bcc9..a653238f 100644 --- a/stm32-neopixel/Sources/Application/Registers/SPI2.swift +++ b/stm32-neopixel/Sources/STM32F7X6/SPI2.swift @@ -3,5 +3,5 @@ import MMIO /// Serial peripheral interface -typealias SPI2 = SPI1 +public typealias SPI2 = SPI1 diff --git a/stm32-uart-echo/Sources/Application/Registers/USART1.swift b/stm32-neopixel/Sources/STM32F7X6/USART1.swift similarity index 50% rename from stm32-uart-echo/Sources/Application/Registers/USART1.swift rename to stm32-neopixel/Sources/STM32F7X6/USART1.swift index 6230310f..508d05a1 100644 --- a/stm32-uart-echo/Sources/Application/Registers/USART1.swift +++ b/stm32-neopixel/Sources/STM32F7X6/USART1.swift @@ -4,1550 +4,1550 @@ import MMIO /// Universal synchronous asynchronous receiver transmitter @RegisterBlock -struct USART1 { +public struct USART1 { /// Control register 1 @RegisterBlock(offset: 0x0) - var cr1: Register + public var cr1: Register /// Control register 2 @RegisterBlock(offset: 0x4) - var cr2: Register + public var cr2: Register /// Control register 3 @RegisterBlock(offset: 0x8) - var cr3: Register + public var cr3: Register /// Baud rate register @RegisterBlock(offset: 0xc) - var brr: Register + public var brr: Register /// Guard time and prescaler register @RegisterBlock(offset: 0x10) - var gtpr: Register + public var gtpr: Register /// Receiver timeout register @RegisterBlock(offset: 0x14) - var rtor: Register + public var rtor: Register /// Request register @RegisterBlock(offset: 0x18) - var rqr: Register + public var rqr: Register /// Interrupt & status register @RegisterBlock(offset: 0x1c) - var isr: Register + public var isr: Register /// Interrupt flag clear register @RegisterBlock(offset: 0x20) - var icr: Register + public var icr: Register /// Receive data register @RegisterBlock(offset: 0x24) - var rdr: Register + public var rdr: Register /// Transmit data register @RegisterBlock(offset: 0x28) - var tdr: Register + public var tdr: Register } extension USART1 { /// Control register 1 @Register(bitWidth: 32) - struct CR1 { + public struct CR1 { /// Word length @ReadWrite(bits: 28..<29, as: M1Values.self) - var m1: M1 + public var m1: M1 /// End of Block interrupt enable @ReadWrite(bits: 27..<28, as: EOBIEValues.self) - var eobie: EOBIE + public var eobie: EOBIE /// Receiver timeout interrupt enable @ReadWrite(bits: 26..<27, as: RTOIEValues.self) - var rtoie: RTOIE + public var rtoie: RTOIE /// Oversampling mode @ReadWrite(bits: 15..<16, as: OVER8Values.self) - var over8: OVER8 + public var over8: OVER8 /// Character match interrupt enable @ReadWrite(bits: 14..<15, as: CMIEValues.self) - var cmie: CMIE + public var cmie: CMIE /// Mute mode enable @ReadWrite(bits: 13..<14, as: MMEValues.self) - var mme: MME + public var mme: MME /// Word length @ReadWrite(bits: 12..<13, as: M0Values.self) - var m0: M0 + public var m0: M0 /// Receiver wakeup method @ReadWrite(bits: 11..<12, as: WAKEValues.self) - var wake: WAKE + public var wake: WAKE /// Parity control enable @ReadWrite(bits: 10..<11, as: PCEValues.self) - var pce: PCE + public var pce: PCE /// Parity selection @ReadWrite(bits: 9..<10, as: PSValues.self) - var ps: PS + public var ps: PS /// PE interrupt enable @ReadWrite(bits: 8..<9, as: PEIEValues.self) - var peie: PEIE + public var peie: PEIE /// interrupt enable @ReadWrite(bits: 7..<8, as: TXEIEValues.self) - var txeie: TXEIE + public var txeie: TXEIE /// Transmission complete interrupt enable @ReadWrite(bits: 6..<7, as: TCIEValues.self) - var tcie: TCIE + public var tcie: TCIE /// RXNE interrupt enable @ReadWrite(bits: 5..<6, as: RXNEIEValues.self) - var rxneie: RXNEIE + public var rxneie: RXNEIE /// IDLE interrupt enable @ReadWrite(bits: 4..<5, as: IDLEIEValues.self) - var idleie: IDLEIE + public var idleie: IDLEIE /// Transmitter enable @ReadWrite(bits: 3..<4, as: TEValues.self) - var te: TE + public var te: TE /// Receiver enable @ReadWrite(bits: 2..<3, as: REValues.self) - var re: RE + public var re: RE /// USART enable in Stop mode @ReadWrite(bits: 1..<2, as: UESMValues.self) - var uesm: UESM + public var uesm: UESM /// USART enable @ReadWrite(bits: 0..<1, as: UEValues.self) - var ue: UE + public var ue: UE /// Driver Enable assertion time @ReadWrite(bits: 21..<26) - var deat: DEAT + public var deat: DEAT /// Driver Enable de-assertion time @ReadWrite(bits: 16..<21) - var dedt: DEDT + public var dedt: DEDT } /// Control register 2 @Register(bitWidth: 32) - struct CR2 { + public struct CR2 { /// Receiver timeout enable @ReadWrite(bits: 23..<24, as: RTOENValues.self) - var rtoen: RTOEN + public var rtoen: RTOEN /// Auto baud rate enable @ReadWrite(bits: 20..<21, as: ABRENValues.self) - var abren: ABREN + public var abren: ABREN /// Most significant bit first @ReadWrite(bits: 19..<20, as: MSBFIRSTValues.self) - var msbfirst: MSBFIRST + public var msbfirst: MSBFIRST /// Binary data inversion @ReadWrite(bits: 18..<19, as: DATAINVValues.self) - var datainv: DATAINV + public var datainv: DATAINV /// TX pin active level inversion @ReadWrite(bits: 17..<18, as: TXINVValues.self) - var txinv: TXINV + public var txinv: TXINV /// RX pin active level inversion @ReadWrite(bits: 16..<17, as: RXINVValues.self) - var rxinv: RXINV + public var rxinv: RXINV /// Swap TX/RX pins @ReadWrite(bits: 15..<16, as: SWAPValues.self) - var swap: SWAP + public var swap: SWAP /// LIN mode enable @ReadWrite(bits: 14..<15, as: LINENValues.self) - var linen: LINEN + public var linen: LINEN /// STOP bits @ReadWrite(bits: 12..<14, as: STOPValues.self) - var stop: STOP + public var stop: STOP /// Clock enable @ReadWrite(bits: 11..<12, as: CLKENValues.self) - var clken: CLKEN + public var clken: CLKEN /// Clock polarity @ReadWrite(bits: 10..<11, as: CPOLValues.self) - var cpol: CPOL + public var cpol: CPOL /// Clock phase @ReadWrite(bits: 9..<10, as: CPHAValues.self) - var cpha: CPHA + public var cpha: CPHA /// Last bit clock pulse @ReadWrite(bits: 8..<9, as: LBCLValues.self) - var lbcl: LBCL + public var lbcl: LBCL /// LIN break detection interrupt enable @ReadWrite(bits: 6..<7, as: LBDIEValues.self) - var lbdie: LBDIE + public var lbdie: LBDIE /// LIN break detection length @ReadWrite(bits: 5..<6, as: LBDLValues.self) - var lbdl: LBDL + public var lbdl: LBDL /// 7-bit Address Detection/4-bit Address Detection @ReadWrite(bits: 4..<5, as: ADDM7Values.self) - var addm7: ADDM7 + public var addm7: ADDM7 /// Auto baud rate mode @ReadWrite(bits: 21..<23, as: ABRMODValues.self) - var abrmod: ABRMOD + public var abrmod: ABRMOD /// Address of the USART node @ReadWrite(bits: 24..<32) - var add: ADD + public var add: ADD } /// Control register 3 @Register(bitWidth: 32) - struct CR3 { + public struct CR3 { /// Wakeup from Stop mode interrupt enable @ReadWrite(bits: 22..<23, as: WUFIEValues.self) - var wufie: WUFIE + public var wufie: WUFIE /// Wakeup from Stop mode interrupt flag selection @ReadWrite(bits: 20..<22, as: WUSValues.self) - var wus: WUS + public var wus: WUS /// Smartcard auto-retry count @ReadWrite(bits: 17..<20) - var scarcnt: SCARCNT + public var scarcnt: SCARCNT /// Driver enable polarity selection @ReadWrite(bits: 15..<16, as: DEPValues.self) - var dep: DEP + public var dep: DEP /// Driver enable mode @ReadWrite(bits: 14..<15, as: DEMValues.self) - var dem: DEM + public var dem: DEM /// DMA Disable on Reception Error @ReadWrite(bits: 13..<14, as: DDREValues.self) - var ddre: DDRE + public var ddre: DDRE /// Overrun Disable @ReadWrite(bits: 12..<13, as: OVRDISValues.self) - var ovrdis: OVRDIS + public var ovrdis: OVRDIS /// One sample bit method enable @ReadWrite(bits: 11..<12, as: ONEBITValues.self) - var onebit: ONEBIT + public var onebit: ONEBIT /// CTS interrupt enable @ReadWrite(bits: 10..<11, as: CTSIEValues.self) - var ctsie: CTSIE + public var ctsie: CTSIE /// CTS enable @ReadWrite(bits: 9..<10, as: CTSEValues.self) - var ctse: CTSE + public var ctse: CTSE /// RTS enable @ReadWrite(bits: 8..<9, as: RTSEValues.self) - var rtse: RTSE + public var rtse: RTSE /// DMA enable transmitter @ReadWrite(bits: 7..<8, as: DMATValues.self) - var dmat: DMAT + public var dmat: DMAT /// DMA enable receiver @ReadWrite(bits: 6..<7, as: DMARValues.self) - var dmar: DMAR + public var dmar: DMAR /// Smartcard mode enable @ReadWrite(bits: 5..<6, as: SCENValues.self) - var scen: SCEN + public var scen: SCEN /// Smartcard NACK enable @ReadWrite(bits: 4..<5, as: NACKValues.self) - var nack: NACK + public var nack: NACK /// Half-duplex selection @ReadWrite(bits: 3..<4, as: HDSELValues.self) - var hdsel: HDSEL + public var hdsel: HDSEL /// Ir low-power @ReadWrite(bits: 2..<3, as: IRLPValues.self) - var irlp: IRLP + public var irlp: IRLP /// Ir mode enable @ReadWrite(bits: 1..<2, as: IRENValues.self) - var iren: IREN + public var iren: IREN /// Error interrupt enable @ReadWrite(bits: 0..<1, as: EIEValues.self) - var eie: EIE + public var eie: EIE } /// Baud rate register @Register(bitWidth: 32) - struct BRR { + public struct BRR { /// DIV_Mantissa @ReadWrite(bits: 0..<16) - var brr_field: BRR_FIELD + public var brr_field: BRR_FIELD } /// Guard time and prescaler register @Register(bitWidth: 32) - struct GTPR { + public struct GTPR { /// Guard time value @ReadWrite(bits: 8..<16) - var gt: GT + public var gt: GT /// Prescaler value @ReadWrite(bits: 0..<8) - var psc: PSC + public var psc: PSC } /// Receiver timeout register @Register(bitWidth: 32) - struct RTOR { + public struct RTOR { /// Block Length @ReadWrite(bits: 24..<32) - var blen: BLEN + public var blen: BLEN /// Receiver timeout value @ReadWrite(bits: 0..<24) - var rto: RTO + public var rto: RTO } /// Request register @Register(bitWidth: 32) - struct RQR { + public struct RQR { /// Transmit data flush request @WriteOnly(bits: 4..<5) - var txfrq: TXFRQ + public var txfrq: TXFRQ /// Receive data flush request @WriteOnly(bits: 3..<4) - var rxfrq: RXFRQ + public var rxfrq: RXFRQ /// Mute mode request @WriteOnly(bits: 2..<3) - var mmrq: MMRQ + public var mmrq: MMRQ /// Send break request @WriteOnly(bits: 1..<2) - var sbkrq: SBKRQ + public var sbkrq: SBKRQ /// Auto baud rate request @WriteOnly(bits: 0..<1) - var abrrq: ABRRQ + public var abrrq: ABRRQ } /// Interrupt & status register @Register(bitWidth: 32) - struct ISR { + public struct ISR { /// REACK @ReadOnly(bits: 22..<23) - var reack: REACK + public var reack: REACK /// TEACK @ReadOnly(bits: 21..<22) - var teack: TEACK + public var teack: TEACK /// WUF @ReadOnly(bits: 20..<21) - var wuf: WUF + public var wuf: WUF /// RWU @ReadOnly(bits: 19..<20) - var rwu: RWU + public var rwu: RWU /// SBKF @ReadOnly(bits: 18..<19) - var sbkf: SBKF + public var sbkf: SBKF /// CMF @ReadOnly(bits: 17..<18) - var cmf: CMF + public var cmf: CMF /// BUSY @ReadOnly(bits: 16..<17) - var busy: BUSY + public var busy: BUSY /// ABRF @ReadOnly(bits: 15..<16) - var abrf: ABRF + public var abrf: ABRF /// ABRE @ReadOnly(bits: 14..<15) - var abre: ABRE + public var abre: ABRE /// EOBF @ReadOnly(bits: 12..<13) - var eobf: EOBF + public var eobf: EOBF /// RTOF @ReadOnly(bits: 11..<12) - var rtof: RTOF + public var rtof: RTOF /// CTS @ReadOnly(bits: 10..<11) - var cts: CTS + public var cts: CTS /// CTSIF @ReadOnly(bits: 9..<10) - var ctsif: CTSIF + public var ctsif: CTSIF /// LBDF @ReadOnly(bits: 8..<9) - var lbdf: LBDF + public var lbdf: LBDF /// TXE @ReadOnly(bits: 7..<8) - var txe: TXE + public var txe: TXE /// TC @ReadOnly(bits: 6..<7) - var tc: TC + public var tc: TC /// RXNE @ReadOnly(bits: 5..<6) - var rxne: RXNE + public var rxne: RXNE /// IDLE @ReadOnly(bits: 4..<5) - var idle: IDLE + public var idle: IDLE /// ORE @ReadOnly(bits: 3..<4) - var ore: ORE + public var ore: ORE /// NF @ReadOnly(bits: 2..<3) - var nf: NF + public var nf: NF /// FE @ReadOnly(bits: 1..<2) - var fe: FE + public var fe: FE /// PE @ReadOnly(bits: 0..<1) - var pe: PE + public var pe: PE } /// Interrupt flag clear register @Register(bitWidth: 32) - struct ICR { + public struct ICR { /// Wakeup from Stop mode clear flag @WriteOnly(bits: 20..<21) - var wucf: WUCF + public var wucf: WUCF /// Character match clear flag @WriteOnly(bits: 17..<18) - var cmcf: CMCF + public var cmcf: CMCF /// End of block clear flag @WriteOnly(bits: 12..<13) - var eobcf: EOBCF + public var eobcf: EOBCF /// Receiver timeout clear flag @WriteOnly(bits: 11..<12) - var rtocf: RTOCF + public var rtocf: RTOCF /// CTS clear flag @WriteOnly(bits: 9..<10) - var ctscf: CTSCF + public var ctscf: CTSCF /// LIN break detection clear flag @WriteOnly(bits: 8..<9) - var lbdcf: LBDCF + public var lbdcf: LBDCF /// Transmission complete clear flag @WriteOnly(bits: 6..<7) - var tccf: TCCF + public var tccf: TCCF /// Idle line detected clear flag @WriteOnly(bits: 4..<5) - var idlecf: IDLECF + public var idlecf: IDLECF /// Overrun error clear flag @WriteOnly(bits: 3..<4) - var orecf: ORECF + public var orecf: ORECF /// Noise detected clear flag @WriteOnly(bits: 2..<3) - var ncf: NCF + public var ncf: NCF /// Framing error clear flag @WriteOnly(bits: 1..<2) - var fecf: FECF + public var fecf: FECF /// Parity error clear flag @WriteOnly(bits: 0..<1) - var pecf: PECF + public var pecf: PECF } /// Receive data register @Register(bitWidth: 32) - struct RDR { + public struct RDR { /// Receive data value @ReadOnly(bits: 0..<9) - var rdr_field: RDR_FIELD + public var rdr_field: RDR_FIELD } /// Transmit data register @Register(bitWidth: 32) - struct TDR { + public struct TDR { /// Transmit data value @ReadWrite(bits: 0..<9) - var tdr_field: TDR_FIELD + public var tdr_field: TDR_FIELD } } extension USART1.CR1 { - struct M1Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct M1Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Use M0 to set the data bits - static let M0 = Self(rawValue: 0x0) + public static let M0 = Self(rawValue: 0x0) /// 1 start bit, 7 data bits, n stop bits - static let Bit7 = Self(rawValue: 0x1) + public static let Bit7 = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct EOBIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct EOBIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is inhibited - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// A USART interrupt is generated when the EOBF flag is set in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct RTOIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct RTOIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is inhibited - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// An USART interrupt is generated when the RTOF bit is set in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct OVER8Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct OVER8Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Oversampling by 16 - static let Oversampling16 = Self(rawValue: 0x0) + public static let Oversampling16 = Self(rawValue: 0x0) /// Oversampling by 8 - static let Oversampling8 = Self(rawValue: 0x1) + public static let Oversampling8 = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct CMIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CMIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Interrupt is generated when the CMF bit is set in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct MMEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct MMEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Receiver in active mode permanently - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Receiver can switch between mute mode and active mode - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct M0Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct M0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// 1 start bit, 8 data bits, n stop bits - static let Bit8 = Self(rawValue: 0x0) + public static let Bit8 = Self(rawValue: 0x0) /// 1 start bit, 9 data bits, n stop bits - static let Bit9 = Self(rawValue: 0x1) + public static let Bit9 = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct WAKEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct WAKEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Idle line - static let Idle = Self(rawValue: 0x0) + public static let Idle = Self(rawValue: 0x0) /// Address mask - static let Address = Self(rawValue: 0x1) + public static let Address = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct PCEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct PCEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Parity control disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Parity control enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct PSValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct PSValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Even parity - static let Even = Self(rawValue: 0x0) + public static let Even = Self(rawValue: 0x0) /// Odd parity - static let Odd = Self(rawValue: 0x1) + public static let Odd = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct PEIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct PEIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Interrupt is generated whenever PE=1 in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct TXEIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TXEIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Interrupt is generated whenever TXE=1 in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct TCIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TCIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Interrupt is generated whenever TC=1 in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct RXNEIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct RXNEIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct IDLEIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct IDLEIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Interrupt is generated whenever IDLE=1 in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct TEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Transmitter is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Transmitter is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct REValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct REValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Receiver is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Receiver is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct UESMValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct UESMValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// USART not able to wake up the MCU from Stop mode - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// USART able to wake up the MCU from Stop mode - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct UEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct UEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// UART is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// UART is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct RTOENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct RTOENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Receiver timeout feature disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Receiver timeout feature enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct ABRENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct ABRENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Auto baud rate detection is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Auto baud rate detection is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct MSBFIRSTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct MSBFIRSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// data is transmitted/received with data bit 0 first, following the start bit - static let LSB = Self(rawValue: 0x0) + public static let LSB = Self(rawValue: 0x0) /// data is transmitted/received with MSB (bit 7/8/9) first, following the start bit - static let MSB = Self(rawValue: 0x1) + public static let MSB = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct DATAINVValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DATAINVValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Logical data from the data register are send/received in positive/direct logic - static let Positive = Self(rawValue: 0x0) + public static let Positive = Self(rawValue: 0x0) /// Logical data from the data register are send/received in negative/inverse logic - static let Negative = Self(rawValue: 0x1) + public static let Negative = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct TXINVValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TXINVValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// TX pin signal works using the standard logic levels - static let Standard = Self(rawValue: 0x0) + public static let Standard = Self(rawValue: 0x0) /// TX pin signal values are inverted - static let Inverted = Self(rawValue: 0x1) + public static let Inverted = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct RXINVValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct RXINVValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// RX pin signal works using the standard logic levels - static let Standard = Self(rawValue: 0x0) + public static let Standard = Self(rawValue: 0x0) /// RX pin signal values are inverted - static let Inverted = Self(rawValue: 0x1) + public static let Inverted = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct SWAPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct SWAPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// TX/RX pins are used as defined in standard pinout - static let Standard = Self(rawValue: 0x0) + public static let Standard = Self(rawValue: 0x0) /// The TX and RX pins functions are swapped - static let Swapped = Self(rawValue: 0x1) + public static let Swapped = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct LINENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LINENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// LIN mode disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// LIN mode enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct STOPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct STOPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// 1 stop bit - static let Stop1 = Self(rawValue: 0x0) + public static let Stop1 = Self(rawValue: 0x0) /// 0.5 stop bit - static let Stop0p5 = Self(rawValue: 0x1) + public static let Stop0p5 = Self(rawValue: 0x1) /// 2 stop bit - static let Stop2 = Self(rawValue: 0x2) + public static let Stop2 = Self(rawValue: 0x2) /// 1.5 stop bit - static let Stop1p5 = Self(rawValue: 0x3) + public static let Stop1p5 = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct CLKENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CLKENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// CK pin disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// CK pin enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct CPOLValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CPOLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Steady low value on CK pin outside transmission window - static let Low = Self(rawValue: 0x0) + public static let Low = Self(rawValue: 0x0) /// Steady high value on CK pin outside transmission window - static let High = Self(rawValue: 0x1) + public static let High = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct CPHAValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CPHAValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// The first clock transition is the first data capture edge - static let First = Self(rawValue: 0x0) + public static let First = Self(rawValue: 0x0) /// The second clock transition is the first data capture edge - static let Second = Self(rawValue: 0x1) + public static let Second = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct LBCLValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LBCLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// The clock pulse of the last data bit is not output to the CK pin - static let NotOutput = Self(rawValue: 0x0) + public static let NotOutput = Self(rawValue: 0x0) /// The clock pulse of the last data bit is output to the CK pin - static let Output = Self(rawValue: 0x1) + public static let Output = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct LBDIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LBDIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is inhibited - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// An interrupt is generated whenever LBDF=1 in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct LBDLValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LBDLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// 10-bit break detection - static let Bit10 = Self(rawValue: 0x0) + public static let Bit10 = Self(rawValue: 0x0) /// 11-bit break detection - static let Bit11 = Self(rawValue: 0x1) + public static let Bit11 = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct ADDM7Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct ADDM7Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// 4-bit address detection - static let Bit4 = Self(rawValue: 0x0) + public static let Bit4 = Self(rawValue: 0x0) /// 7-bit address detection - static let Bit7 = Self(rawValue: 0x1) + public static let Bit7 = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct ABRMODValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct ABRMODValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// Measurement of the start bit is used to detect the baud rate - static let Start = Self(rawValue: 0x0) + public static let Start = Self(rawValue: 0x0) /// Falling edge to falling edge measurement - static let Edge = Self(rawValue: 0x1) + public static let Edge = Self(rawValue: 0x1) /// 0x7F frame detection - static let Frame7F = Self(rawValue: 0x2) + public static let Frame7F = Self(rawValue: 0x2) /// 0x55 frame detection - static let Frame55 = Self(rawValue: 0x3) + public static let Frame55 = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct WUFIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct WUFIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is inhibited - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// An USART interrupt is generated whenever WUF=1 in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct WUSValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct WUSValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// WUF active on address match - static let Address = Self(rawValue: 0x0) + public static let Address = Self(rawValue: 0x0) /// WuF active on Start bit detection - static let Start = Self(rawValue: 0x2) + public static let Start = Self(rawValue: 0x2) /// WUF active on RXNE - static let RXNE = Self(rawValue: 0x3) + public static let RXNE = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct DEPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DEPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// DE signal is active high - static let High = Self(rawValue: 0x0) + public static let High = Self(rawValue: 0x0) /// DE signal is active low - static let Low = Self(rawValue: 0x1) + public static let Low = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct DEMValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DEMValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// DE function is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// The DE signal is output on the RTS pin - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct DDREValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DDREValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// DMA is not disabled in case of reception error - static let NotDisabled = Self(rawValue: 0x0) + public static let NotDisabled = Self(rawValue: 0x0) /// DMA is disabled following a reception error - static let Disabled = Self(rawValue: 0x1) + public static let Disabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct OVRDISValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct OVRDISValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Overrun Error Flag, ORE, is set when received data is not read before receiving new data - static let Enabled = Self(rawValue: 0x0) + public static let Enabled = Self(rawValue: 0x0) /// Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register - static let Disabled = Self(rawValue: 0x1) + public static let Disabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct ONEBITValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct ONEBITValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Three sample bit method - static let Sample3 = Self(rawValue: 0x0) + public static let Sample3 = Self(rawValue: 0x0) /// One sample bit method - static let Sample1 = Self(rawValue: 0x1) + public static let Sample1 = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct CTSIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CTSIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is inhibited - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// An interrupt is generated whenever CTSIF=1 in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct CTSEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CTSEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// CTS hardware flow control disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// CTS mode enabled, data is only transmitted when the CTS input is asserted - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct RTSEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct RTSEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// RTS hardware flow control disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// RTS output enabled, data is only requested when there is space in the receive buffer - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct DMATValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DMATValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// DMA mode is disabled for transmission - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// DMA mode is enabled for transmission - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct DMARValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DMARValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// DMA mode is disabled for reception - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// DMA mode is enabled for reception - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct SCENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct SCENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Smartcard Mode disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Smartcard Mode enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct NACKValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct NACKValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// NACK transmission in case of parity error is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// NACK transmission during parity error is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct HDSELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct HDSELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Half duplex mode is not selected - static let NotSelected = Self(rawValue: 0x0) + public static let NotSelected = Self(rawValue: 0x0) /// Half duplex mode is selected - static let Selected = Self(rawValue: 0x1) + public static let Selected = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct IRLPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct IRLPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Normal mode - static let Normal = Self(rawValue: 0x0) + public static let Normal = Self(rawValue: 0x0) /// Low-power mode - static let LowPower = Self(rawValue: 0x1) + public static let LowPower = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct IRENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct IRENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// IrDA disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// IrDA enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct EIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct EIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is inhibited - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } diff --git a/stm32-neopixel/Sources/STM32F7X6/stm32f7x6.patched.svd b/stm32-neopixel/Sources/STM32F7X6/stm32f7x6.patched.svd new file mode 120000 index 00000000..a6442b50 --- /dev/null +++ b/stm32-neopixel/Sources/STM32F7X6/stm32f7x6.patched.svd @@ -0,0 +1 @@ +../../../Tools/SVDs/stm32f7x6.patched.svd \ No newline at end of file diff --git a/stm32-neopixel/Sources/STM32F7X6/svd2swift.json b/stm32-neopixel/Sources/STM32F7X6/svd2swift.json new file mode 100644 index 00000000..cfe41520 --- /dev/null +++ b/stm32-neopixel/Sources/STM32F7X6/svd2swift.json @@ -0,0 +1,14 @@ +{ + "peripherals": [ + "DMA1", + "DMA2", + "GPIOA", + "GPIOB", + "GPIOI", + "RCC", + "SPI1", + "SPI2", + "USART1" + ], + "access-level": "public" +} diff --git a/stm32-uart-echo/Makefile b/stm32-uart-echo/Makefile index 51885ce5..9c8ffe29 100755 --- a/stm32-uart-echo/Makefile +++ b/stm32-uart-echo/Makefile @@ -46,7 +46,10 @@ build: @echo "extracting binary..." $(MACHO2BIN) \ - $(BUILDROOT)/Application $(BUILDROOT)/Application.bin --base-address 0x20010000 --segments '__TEXT,__DATA,__VECTORS' + $(BUILDROOT)/Application \ + $(BUILDROOT)/Application.bin \ + --base-address 0x20010000 \ + --segments '__TEXT,__DATA,__VECTORS' .PHONY: clean clean: diff --git a/stm32-uart-echo/Package.resolved b/stm32-uart-echo/Package.resolved index 25097fb2..bfba35e0 100644 --- a/stm32-uart-echo/Package.resolved +++ b/stm32-uart-echo/Package.resolved @@ -1,5 +1,5 @@ { - "originHash" : "50d5562e902c0a987f43e9c891a6d559c9d71bc593aa215e096917fdd28b5c6c", + "originHash" : "b5206e756e7be7138148bd69eca921f1525d2b038657b90a2712a76adba376d0", "pins" : [ { "identity" : "swift-argument-parser", @@ -16,7 +16,7 @@ "location" : "https://github.com/apple/swift-mmio", "state" : { "branch" : "main", - "revision" : "daf25ecacc0d9b71036c6af32cb7786a01802799" + "revision" : "5232c5129a8c70beafc3d6acfbae2716c1b6822a" } }, { diff --git a/stm32-uart-echo/Package.swift b/stm32-uart-echo/Package.swift index 23b94fd9..e5c40c11 100644 --- a/stm32-uart-echo/Package.swift +++ b/stm32-uart-echo/Package.swift @@ -4,9 +4,6 @@ import PackageDescription let package = Package( name: "stm32-uart-echo", - platforms: [ - .macOS(.v10_15) - ], products: [ .executable(name: "Application", targets: ["Application"]) ], @@ -14,16 +11,24 @@ let package = Package( .package(url: "https://github.com/apple/swift-mmio", branch: "main") ], targets: [ + .executableTarget( + name: "Application", + dependencies: ["STM32F7X6", "Support"]), // SVD2Swift \ - // --input ../Tools/SVDs/stm32f7x6.patched.svd \ - // --output Sources/Application/Registers \ + // --input Sources/STM32F7X6/stm32f7x6.patched.svd \ + // --output Sources/STM32F7X6 \ + // --access-level public \ // --indentation-width 2 \ // --peripherals GPIOA GPIOB RCC USART1 - .executableTarget( - name: "Application", + .target( + name: "STM32F7X6", dependencies: [ - .product(name: "MMIO", package: "swift-mmio"), - "Support", + .product(name: "MMIO", package: "swift-mmio") + ], + plugins: [ + // Plugin disabled because SwiftPM is slow. + // .plugin(name: "SVD2SwiftPlugin", package: "swift-mmio") ]), .target(name: "Support"), - ]) + ], + swiftLanguageModes: [.v5]) diff --git a/stm32-uart-echo/Sources/Application/Application.swift b/stm32-uart-echo/Sources/Application/Application.swift index 362ee811..118c7475 100644 --- a/stm32-uart-echo/Sources/Application/Application.swift +++ b/stm32-uart-echo/Sources/Application/Application.swift @@ -9,6 +9,7 @@ // //===----------------------------------------------------------------------===// +import STM32F7X6 import Support @main diff --git a/stm32-uart-echo/Sources/Application/Registers/GPIO.swift b/stm32-uart-echo/Sources/Application/GPIO.swift similarity index 99% rename from stm32-uart-echo/Sources/Application/Registers/GPIO.swift rename to stm32-uart-echo/Sources/Application/GPIO.swift index a90ecd4e..8e24b427 100644 --- a/stm32-uart-echo/Sources/Application/Registers/GPIO.swift +++ b/stm32-uart-echo/Sources/Application/GPIO.swift @@ -9,6 +9,8 @@ // //===----------------------------------------------------------------------===// +import STM32F7X6 + extension GPIOA { enum Mode: UInt32 { case input = 0x0 diff --git a/stm32-uart-echo/Sources/Application/Registers/Device.swift b/stm32-uart-echo/Sources/Application/Registers/Device.swift deleted file mode 100644 index 8788410d..00000000 --- a/stm32-uart-echo/Sources/Application/Registers/Device.swift +++ /dev/null @@ -1,15 +0,0 @@ -// Generated by svd2swift. - -import MMIO - -/// General-purpose I/Os -let gpioa = GPIOA(unsafeAddress: 0x40020000) - -/// General-purpose I/Os -let gpiob = GPIOB(unsafeAddress: 0x40020400) - -/// Reset and clock control -let rcc = RCC(unsafeAddress: 0x40023800) - -/// Universal synchronous asynchronous receiver transmitter -let usart1 = USART1(unsafeAddress: 0x40011000) diff --git a/stm32-uart-echo/Sources/STM32F7X6/Device.swift b/stm32-uart-echo/Sources/STM32F7X6/Device.swift new file mode 100644 index 00000000..db4a3f50 --- /dev/null +++ b/stm32-uart-echo/Sources/STM32F7X6/Device.swift @@ -0,0 +1,15 @@ +// Generated by svd2swift. + +import MMIO + +/// General-purpose I/Os +public let gpioa = GPIOA(unsafeAddress: 0x40020000) + +/// General-purpose I/Os +public let gpiob = GPIOB(unsafeAddress: 0x40020400) + +/// Reset and clock control +public let rcc = RCC(unsafeAddress: 0x40023800) + +/// Universal synchronous asynchronous receiver transmitter +public let usart1 = USART1(unsafeAddress: 0x40011000) diff --git a/stm32-uart-echo/Sources/STM32F7X6/Empty.swift b/stm32-uart-echo/Sources/STM32F7X6/Empty.swift new file mode 100644 index 00000000..934a795a --- /dev/null +++ b/stm32-uart-echo/Sources/STM32F7X6/Empty.swift @@ -0,0 +1,13 @@ +//===----------------------------------------------------------------------===// +// +// This source file is part of the Swift open source project +// +// Copyright (c) 2024 Apple Inc. and the Swift project authors. +// Licensed under Apache License v2.0 with Runtime Library Exception +// +// See https://swift.org/LICENSE.txt for license information +// +//===----------------------------------------------------------------------===// + +// This file is intentionally left empty for SwiftPM to recognize the target as +// a Swift source module. diff --git a/stm32-neopixel/Sources/Application/Registers/GPIOA.swift b/stm32-uart-echo/Sources/STM32F7X6/GPIOA.swift similarity index 62% rename from stm32-neopixel/Sources/Application/Registers/GPIOA.swift rename to stm32-uart-echo/Sources/STM32F7X6/GPIOA.swift index 3bc4d2ff..a70e68c7 100644 --- a/stm32-neopixel/Sources/Application/Registers/GPIOA.swift +++ b/stm32-uart-echo/Sources/STM32F7X6/GPIOA.swift @@ -4,1071 +4,1071 @@ import MMIO /// General-purpose I/Os @RegisterBlock -struct GPIOA { +public struct GPIOA { /// GPIO port mode register @RegisterBlock(offset: 0x0) - var moder: Register + public var moder: Register /// GPIO port output type register @RegisterBlock(offset: 0x4) - var otyper: Register + public var otyper: Register /// GPIO port output speed register @RegisterBlock(offset: 0x8) - var ospeedr: Register + public var ospeedr: Register /// GPIO port pull-up/pull-down register @RegisterBlock(offset: 0xc) - var pupdr: Register + public var pupdr: Register /// GPIO port input data register @RegisterBlock(offset: 0x10) - var idr: Register + public var idr: Register /// GPIO port output data register @RegisterBlock(offset: 0x14) - var odr: Register + public var odr: Register /// GPIO port bit set/reset register @RegisterBlock(offset: 0x18) - var bsrr: Register + public var bsrr: Register /// GPIO port configuration lock register @RegisterBlock(offset: 0x1c) - var lckr: Register + public var lckr: Register /// GPIO alternate function low register @RegisterBlock(offset: 0x20) - var afrl: Register + public var afrl: Register /// GPIO alternate function high register @RegisterBlock(offset: 0x24) - var afrh: Register + public var afrh: Register /// GPIO port bit reset register @RegisterBlock(offset: 0x28) - var brr: Register + public var brr: Register } extension GPIOA { /// GPIO port mode register @Register(bitWidth: 32) - struct MODER { + public struct MODER { /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 30..<32) - var moder15: MODER15 + public var moder15: MODER15 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 28..<30) - var moder14: MODER14 + public var moder14: MODER14 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 26..<28) - var moder13: MODER13 + public var moder13: MODER13 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 24..<26) - var moder12: MODER12 + public var moder12: MODER12 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 22..<24) - var moder11: MODER11 + public var moder11: MODER11 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 20..<22) - var moder10: MODER10 + public var moder10: MODER10 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 18..<20) - var moder9: MODER9 + public var moder9: MODER9 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 16..<18) - var moder8: MODER8 + public var moder8: MODER8 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 14..<16) - var moder7: MODER7 + public var moder7: MODER7 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 12..<14) - var moder6: MODER6 + public var moder6: MODER6 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 10..<12) - var moder5: MODER5 + public var moder5: MODER5 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 8..<10) - var moder4: MODER4 + public var moder4: MODER4 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 6..<8) - var moder3: MODER3 + public var moder3: MODER3 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 4..<6) - var moder2: MODER2 + public var moder2: MODER2 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 2..<4) - var moder1: MODER1 + public var moder1: MODER1 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 0..<2, as: MODER0Values.self) - var moder0: MODER0 + public var moder0: MODER0 } /// GPIO port output type register @Register(bitWidth: 32) - struct OTYPER { + public struct OTYPER { /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 15..<16) - var ot15: OT15 + public var ot15: OT15 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 14..<15) - var ot14: OT14 + public var ot14: OT14 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 13..<14) - var ot13: OT13 + public var ot13: OT13 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 12..<13) - var ot12: OT12 + public var ot12: OT12 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 11..<12) - var ot11: OT11 + public var ot11: OT11 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 10..<11) - var ot10: OT10 + public var ot10: OT10 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 9..<10) - var ot9: OT9 + public var ot9: OT9 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 8..<9) - var ot8: OT8 + public var ot8: OT8 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 7..<8) - var ot7: OT7 + public var ot7: OT7 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 6..<7) - var ot6: OT6 + public var ot6: OT6 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 5..<6) - var ot5: OT5 + public var ot5: OT5 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 4..<5) - var ot4: OT4 + public var ot4: OT4 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 3..<4) - var ot3: OT3 + public var ot3: OT3 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 2..<3) - var ot2: OT2 + public var ot2: OT2 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 1..<2) - var ot1: OT1 + public var ot1: OT1 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 0..<1, as: OT0Values.self) - var ot0: OT0 + public var ot0: OT0 } /// GPIO port output speed register @Register(bitWidth: 32) - struct OSPEEDR { + public struct OSPEEDR { /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 30..<32) - var ospeedr15: OSPEEDR15 + public var ospeedr15: OSPEEDR15 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 28..<30) - var ospeedr14: OSPEEDR14 + public var ospeedr14: OSPEEDR14 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 26..<28) - var ospeedr13: OSPEEDR13 + public var ospeedr13: OSPEEDR13 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 24..<26) - var ospeedr12: OSPEEDR12 + public var ospeedr12: OSPEEDR12 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 22..<24) - var ospeedr11: OSPEEDR11 + public var ospeedr11: OSPEEDR11 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 20..<22) - var ospeedr10: OSPEEDR10 + public var ospeedr10: OSPEEDR10 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 18..<20) - var ospeedr9: OSPEEDR9 + public var ospeedr9: OSPEEDR9 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 16..<18) - var ospeedr8: OSPEEDR8 + public var ospeedr8: OSPEEDR8 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 14..<16) - var ospeedr7: OSPEEDR7 + public var ospeedr7: OSPEEDR7 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 12..<14) - var ospeedr6: OSPEEDR6 + public var ospeedr6: OSPEEDR6 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 10..<12) - var ospeedr5: OSPEEDR5 + public var ospeedr5: OSPEEDR5 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 8..<10) - var ospeedr4: OSPEEDR4 + public var ospeedr4: OSPEEDR4 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 6..<8) - var ospeedr3: OSPEEDR3 + public var ospeedr3: OSPEEDR3 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 4..<6) - var ospeedr2: OSPEEDR2 + public var ospeedr2: OSPEEDR2 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 2..<4) - var ospeedr1: OSPEEDR1 + public var ospeedr1: OSPEEDR1 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 0..<2, as: OSPEEDR0Values.self) - var ospeedr0: OSPEEDR0 + public var ospeedr0: OSPEEDR0 } /// GPIO port pull-up/pull-down register @Register(bitWidth: 32) - struct PUPDR { + public struct PUPDR { /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 30..<32) - var pupdr15: PUPDR15 + public var pupdr15: PUPDR15 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 28..<30) - var pupdr14: PUPDR14 + public var pupdr14: PUPDR14 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 26..<28) - var pupdr13: PUPDR13 + public var pupdr13: PUPDR13 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 24..<26) - var pupdr12: PUPDR12 + public var pupdr12: PUPDR12 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 22..<24) - var pupdr11: PUPDR11 + public var pupdr11: PUPDR11 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 20..<22) - var pupdr10: PUPDR10 + public var pupdr10: PUPDR10 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 18..<20) - var pupdr9: PUPDR9 + public var pupdr9: PUPDR9 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 16..<18) - var pupdr8: PUPDR8 + public var pupdr8: PUPDR8 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 14..<16) - var pupdr7: PUPDR7 + public var pupdr7: PUPDR7 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 12..<14) - var pupdr6: PUPDR6 + public var pupdr6: PUPDR6 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 10..<12) - var pupdr5: PUPDR5 + public var pupdr5: PUPDR5 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 8..<10) - var pupdr4: PUPDR4 + public var pupdr4: PUPDR4 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 6..<8) - var pupdr3: PUPDR3 + public var pupdr3: PUPDR3 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 4..<6) - var pupdr2: PUPDR2 + public var pupdr2: PUPDR2 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 2..<4) - var pupdr1: PUPDR1 + public var pupdr1: PUPDR1 /// Port x configuration bits (y = 0..15) @ReadWrite(bits: 0..<2, as: PUPDR0Values.self) - var pupdr0: PUPDR0 + public var pupdr0: PUPDR0 } /// GPIO port input data register @Register(bitWidth: 32) - struct IDR { + public struct IDR { /// Port input data (y = 0..15) @ReadOnly(bits: 15..<16) - var idr15: IDR15 + public var idr15: IDR15 /// Port input data (y = 0..15) @ReadOnly(bits: 14..<15) - var idr14: IDR14 + public var idr14: IDR14 /// Port input data (y = 0..15) @ReadOnly(bits: 13..<14) - var idr13: IDR13 + public var idr13: IDR13 /// Port input data (y = 0..15) @ReadOnly(bits: 12..<13) - var idr12: IDR12 + public var idr12: IDR12 /// Port input data (y = 0..15) @ReadOnly(bits: 11..<12) - var idr11: IDR11 + public var idr11: IDR11 /// Port input data (y = 0..15) @ReadOnly(bits: 10..<11) - var idr10: IDR10 + public var idr10: IDR10 /// Port input data (y = 0..15) @ReadOnly(bits: 9..<10) - var idr9: IDR9 + public var idr9: IDR9 /// Port input data (y = 0..15) @ReadOnly(bits: 8..<9) - var idr8: IDR8 + public var idr8: IDR8 /// Port input data (y = 0..15) @ReadOnly(bits: 7..<8) - var idr7: IDR7 + public var idr7: IDR7 /// Port input data (y = 0..15) @ReadOnly(bits: 6..<7) - var idr6: IDR6 + public var idr6: IDR6 /// Port input data (y = 0..15) @ReadOnly(bits: 5..<6) - var idr5: IDR5 + public var idr5: IDR5 /// Port input data (y = 0..15) @ReadOnly(bits: 4..<5) - var idr4: IDR4 + public var idr4: IDR4 /// Port input data (y = 0..15) @ReadOnly(bits: 3..<4) - var idr3: IDR3 + public var idr3: IDR3 /// Port input data (y = 0..15) @ReadOnly(bits: 2..<3) - var idr2: IDR2 + public var idr2: IDR2 /// Port input data (y = 0..15) @ReadOnly(bits: 1..<2) - var idr1: IDR1 + public var idr1: IDR1 /// Port input data (y = 0..15) @ReadOnly(bits: 0..<1) - var idr0: IDR0 + public var idr0: IDR0 } /// GPIO port output data register @Register(bitWidth: 32) - struct ODR { + public struct ODR { /// Port output data (y = 0..15) @ReadWrite(bits: 15..<16) - var odr15: ODR15 + public var odr15: ODR15 /// Port output data (y = 0..15) @ReadWrite(bits: 14..<15) - var odr14: ODR14 + public var odr14: ODR14 /// Port output data (y = 0..15) @ReadWrite(bits: 13..<14) - var odr13: ODR13 + public var odr13: ODR13 /// Port output data (y = 0..15) @ReadWrite(bits: 12..<13) - var odr12: ODR12 + public var odr12: ODR12 /// Port output data (y = 0..15) @ReadWrite(bits: 11..<12) - var odr11: ODR11 + public var odr11: ODR11 /// Port output data (y = 0..15) @ReadWrite(bits: 10..<11) - var odr10: ODR10 + public var odr10: ODR10 /// Port output data (y = 0..15) @ReadWrite(bits: 9..<10) - var odr9: ODR9 + public var odr9: ODR9 /// Port output data (y = 0..15) @ReadWrite(bits: 8..<9) - var odr8: ODR8 + public var odr8: ODR8 /// Port output data (y = 0..15) @ReadWrite(bits: 7..<8) - var odr7: ODR7 + public var odr7: ODR7 /// Port output data (y = 0..15) @ReadWrite(bits: 6..<7) - var odr6: ODR6 + public var odr6: ODR6 /// Port output data (y = 0..15) @ReadWrite(bits: 5..<6) - var odr5: ODR5 + public var odr5: ODR5 /// Port output data (y = 0..15) @ReadWrite(bits: 4..<5) - var odr4: ODR4 + public var odr4: ODR4 /// Port output data (y = 0..15) @ReadWrite(bits: 3..<4) - var odr3: ODR3 + public var odr3: ODR3 /// Port output data (y = 0..15) @ReadWrite(bits: 2..<3) - var odr2: ODR2 + public var odr2: ODR2 /// Port output data (y = 0..15) @ReadWrite(bits: 1..<2) - var odr1: ODR1 + public var odr1: ODR1 /// Port output data (y = 0..15) @ReadWrite(bits: 0..<1, as: ODR0Values.self) - var odr0: ODR0 + public var odr0: ODR0 } /// GPIO port bit set/reset register @Register(bitWidth: 32) - struct BSRR { + public struct BSRR { /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 31..<32) - var br15: BR15 + public var br15: BR15 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 30..<31) - var br14: BR14 + public var br14: BR14 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 29..<30) - var br13: BR13 + public var br13: BR13 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 28..<29) - var br12: BR12 + public var br12: BR12 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 27..<28) - var br11: BR11 + public var br11: BR11 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 26..<27) - var br10: BR10 + public var br10: BR10 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 25..<26) - var br9: BR9 + public var br9: BR9 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 24..<25) - var br8: BR8 + public var br8: BR8 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 23..<24) - var br7: BR7 + public var br7: BR7 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 22..<23) - var br6: BR6 + public var br6: BR6 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 21..<22) - var br5: BR5 + public var br5: BR5 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 20..<21) - var br4: BR4 + public var br4: BR4 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 19..<20) - var br3: BR3 + public var br3: BR3 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 18..<19) - var br2: BR2 + public var br2: BR2 /// Port x reset bit y (y = 0..15) @WriteOnly(bits: 17..<18) - var br1: BR1 + public var br1: BR1 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 16..<17) - var br0: BR0 + public var br0: BR0 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 15..<16) - var bs15: BS15 + public var bs15: BS15 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 14..<15) - var bs14: BS14 + public var bs14: BS14 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 13..<14) - var bs13: BS13 + public var bs13: BS13 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 12..<13) - var bs12: BS12 + public var bs12: BS12 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 11..<12) - var bs11: BS11 + public var bs11: BS11 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 10..<11) - var bs10: BS10 + public var bs10: BS10 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 9..<10) - var bs9: BS9 + public var bs9: BS9 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 8..<9) - var bs8: BS8 + public var bs8: BS8 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 7..<8) - var bs7: BS7 + public var bs7: BS7 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 6..<7) - var bs6: BS6 + public var bs6: BS6 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 5..<6) - var bs5: BS5 + public var bs5: BS5 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 4..<5) - var bs4: BS4 + public var bs4: BS4 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 3..<4) - var bs3: BS3 + public var bs3: BS3 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 2..<3) - var bs2: BS2 + public var bs2: BS2 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 1..<2) - var bs1: BS1 + public var bs1: BS1 /// Port x set bit y (y= 0..15) @WriteOnly(bits: 0..<1) - var bs0: BS0 + public var bs0: BS0 } /// GPIO port configuration lock register @Register(bitWidth: 32) - struct LCKR { + public struct LCKR { /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 16..<17, as: LCKKValues.self) - var lckk: LCKK + public var lckk: LCKK /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 15..<16) - var lck15: LCK15 + public var lck15: LCK15 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 14..<15) - var lck14: LCK14 + public var lck14: LCK14 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 13..<14) - var lck13: LCK13 + public var lck13: LCK13 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 12..<13) - var lck12: LCK12 + public var lck12: LCK12 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 11..<12) - var lck11: LCK11 + public var lck11: LCK11 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 10..<11) - var lck10: LCK10 + public var lck10: LCK10 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 9..<10) - var lck9: LCK9 + public var lck9: LCK9 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 8..<9) - var lck8: LCK8 + public var lck8: LCK8 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 7..<8) - var lck7: LCK7 + public var lck7: LCK7 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 6..<7) - var lck6: LCK6 + public var lck6: LCK6 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 5..<6) - var lck5: LCK5 + public var lck5: LCK5 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 4..<5) - var lck4: LCK4 + public var lck4: LCK4 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 3..<4) - var lck3: LCK3 + public var lck3: LCK3 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 2..<3) - var lck2: LCK2 + public var lck2: LCK2 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 1..<2) - var lck1: LCK1 + public var lck1: LCK1 /// Port x lock bit y (y= 0..15) @ReadWrite(bits: 0..<1, as: LCK0Values.self) - var lck0: LCK0 + public var lck0: LCK0 } /// GPIO alternate function low register @Register(bitWidth: 32) - struct AFRL { + public struct AFRL { /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 28..<32) - var afrl7: AFRL7 + public var afrl7: AFRL7 /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 24..<28) - var afrl6: AFRL6 + public var afrl6: AFRL6 /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 20..<24) - var afrl5: AFRL5 + public var afrl5: AFRL5 /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 16..<20) - var afrl4: AFRL4 + public var afrl4: AFRL4 /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 12..<16) - var afrl3: AFRL3 + public var afrl3: AFRL3 /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 8..<12) - var afrl2: AFRL2 + public var afrl2: AFRL2 /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 4..<8) - var afrl1: AFRL1 + public var afrl1: AFRL1 /// Alternate function selection for port x bit y (y = 0..7) @ReadWrite(bits: 0..<4, as: AFRL0Values.self) - var afrl0: AFRL0 + public var afrl0: AFRL0 } /// GPIO alternate function high register @Register(bitWidth: 32) - struct AFRH { + public struct AFRH { /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 28..<32) - var afrh15: AFRH15 + public var afrh15: AFRH15 /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 24..<28) - var afrh14: AFRH14 + public var afrh14: AFRH14 /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 20..<24) - var afrh13: AFRH13 + public var afrh13: AFRH13 /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 16..<20) - var afrh12: AFRH12 + public var afrh12: AFRH12 /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 12..<16) - var afrh11: AFRH11 + public var afrh11: AFRH11 /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 8..<12) - var afrh10: AFRH10 + public var afrh10: AFRH10 /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 4..<8) - var afrh9: AFRH9 + public var afrh9: AFRH9 /// Alternate function selection for port x bit y (y = 8..15) @ReadWrite(bits: 0..<4, as: AFRH8Values.self) - var afrh8: AFRH8 + public var afrh8: AFRH8 } /// GPIO port bit reset register @Register(bitWidth: 32) - struct BRR { + public struct BRR { /// Port A Reset bit 0 @ReadWrite(bits: 0..<1) - var br0: BR0 + public var br0: BR0 /// Port A Reset bit 1 @ReadWrite(bits: 1..<2) - var br1: BR1 + public var br1: BR1 /// Port A Reset bit 2 @ReadWrite(bits: 2..<3) - var br2: BR2 + public var br2: BR2 /// Port A Reset bit 3 @ReadWrite(bits: 3..<4) - var br3: BR3 + public var br3: BR3 /// Port A Reset bit 4 @ReadWrite(bits: 4..<5) - var br4: BR4 + public var br4: BR4 /// Port A Reset bit 5 @ReadWrite(bits: 5..<6) - var br5: BR5 + public var br5: BR5 /// Port A Reset bit 6 @ReadWrite(bits: 6..<7) - var br6: BR6 + public var br6: BR6 /// Port A Reset bit 7 @ReadWrite(bits: 7..<8) - var br7: BR7 + public var br7: BR7 /// Port A Reset bit 8 @ReadWrite(bits: 8..<9) - var br8: BR8 + public var br8: BR8 /// Port A Reset bit 9 @ReadWrite(bits: 9..<10) - var br9: BR9 + public var br9: BR9 /// Port A Reset bit 10 @ReadWrite(bits: 10..<11) - var br10: BR10 + public var br10: BR10 /// Port A Reset bit 11 @ReadWrite(bits: 11..<12) - var br11: BR11 + public var br11: BR11 /// Port A Reset bit 12 @ReadWrite(bits: 12..<13) - var br12: BR12 + public var br12: BR12 /// Port A Reset bit 13 @ReadWrite(bits: 13..<14) - var br13: BR13 + public var br13: BR13 /// Port A Reset bit 14 @ReadWrite(bits: 14..<15) - var br14: BR14 + public var br14: BR14 /// Port A Reset bit 15 @ReadWrite(bits: 15..<16) - var br15: BR15 + public var br15: BR15 } } extension GPIOA.MODER { - struct MODER0Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct MODER0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// Input mode (reset state) - static let Input = Self(rawValue: 0x0) + public static let Input = Self(rawValue: 0x0) /// General purpose output mode - static let Output = Self(rawValue: 0x1) + public static let Output = Self(rawValue: 0x1) /// Alternate function mode - static let Alternate = Self(rawValue: 0x2) + public static let Alternate = Self(rawValue: 0x2) /// Analog mode - static let Analog = Self(rawValue: 0x3) + public static let Analog = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.OTYPER { - struct OT0Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct OT0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Output push-pull (reset state) - static let PushPull = Self(rawValue: 0x0) + public static let PushPull = Self(rawValue: 0x0) /// Output open-drain - static let OpenDrain = Self(rawValue: 0x1) + public static let OpenDrain = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.OSPEEDR { - struct OSPEEDR0Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct OSPEEDR0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// Low speed - static let LowSpeed = Self(rawValue: 0x0) + public static let LowSpeed = Self(rawValue: 0x0) /// Medium speed - static let MediumSpeed = Self(rawValue: 0x1) + public static let MediumSpeed = Self(rawValue: 0x1) /// High speed - static let HighSpeed = Self(rawValue: 0x2) + public static let HighSpeed = Self(rawValue: 0x2) /// Very high speed - static let VeryHighSpeed = Self(rawValue: 0x3) + public static let VeryHighSpeed = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.PUPDR { - struct PUPDR0Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct PUPDR0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// No pull-up, pull-down - static let Floating = Self(rawValue: 0x0) + public static let Floating = Self(rawValue: 0x0) /// Pull-up - static let PullUp = Self(rawValue: 0x1) + public static let PullUp = Self(rawValue: 0x1) /// Pull-down - static let PullDown = Self(rawValue: 0x2) + public static let PullDown = Self(rawValue: 0x2) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.ODR { - struct ODR0Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct ODR0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Set output to logic low - static let Low = Self(rawValue: 0x0) + public static let Low = Self(rawValue: 0x0) /// Set output to logic high - static let High = Self(rawValue: 0x1) + public static let High = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.LCKR { - struct LCKKValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LCKKValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Port configuration lock key not active - static let NotActive = Self(rawValue: 0x0) + public static let NotActive = Self(rawValue: 0x0) /// Port configuration lock key active - static let Active = Self(rawValue: 0x1) + public static let Active = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.LCKR { - struct LCK0Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LCK0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Port configuration not locked - static let Unlocked = Self(rawValue: 0x0) + public static let Unlocked = Self(rawValue: 0x0) /// Port configuration locked - static let Locked = Self(rawValue: 0x1) + public static let Locked = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.AFRL { - struct AFRL0Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 4 + public struct AFRL0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 4 /// AF0 - static let AF0 = Self(rawValue: 0x0) + public static let AF0 = Self(rawValue: 0x0) /// AF1 - static let AF1 = Self(rawValue: 0x1) + public static let AF1 = Self(rawValue: 0x1) /// AF2 - static let AF2 = Self(rawValue: 0x2) + public static let AF2 = Self(rawValue: 0x2) /// AF3 - static let AF3 = Self(rawValue: 0x3) + public static let AF3 = Self(rawValue: 0x3) /// AF4 - static let AF4 = Self(rawValue: 0x4) + public static let AF4 = Self(rawValue: 0x4) /// AF5 - static let AF5 = Self(rawValue: 0x5) + public static let AF5 = Self(rawValue: 0x5) /// AF6 - static let AF6 = Self(rawValue: 0x6) + public static let AF6 = Self(rawValue: 0x6) /// AF7 - static let AF7 = Self(rawValue: 0x7) + public static let AF7 = Self(rawValue: 0x7) /// AF8 - static let AF8 = Self(rawValue: 0x8) + public static let AF8 = Self(rawValue: 0x8) /// AF9 - static let AF9 = Self(rawValue: 0x9) + public static let AF9 = Self(rawValue: 0x9) /// AF10 - static let AF10 = Self(rawValue: 0xa) + public static let AF10 = Self(rawValue: 0xa) /// AF11 - static let AF11 = Self(rawValue: 0xb) + public static let AF11 = Self(rawValue: 0xb) /// AF12 - static let AF12 = Self(rawValue: 0xc) + public static let AF12 = Self(rawValue: 0xc) /// AF13 - static let AF13 = Self(rawValue: 0xd) + public static let AF13 = Self(rawValue: 0xd) /// AF14 - static let AF14 = Self(rawValue: 0xe) + public static let AF14 = Self(rawValue: 0xe) /// AF15 - static let AF15 = Self(rawValue: 0xf) + public static let AF15 = Self(rawValue: 0xf) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension GPIOA.AFRH { - struct AFRH8Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 4 + public struct AFRH8Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 4 /// AF0 - static let AF0 = Self(rawValue: 0x0) + public static let AF0 = Self(rawValue: 0x0) /// AF1 - static let AF1 = Self(rawValue: 0x1) + public static let AF1 = Self(rawValue: 0x1) /// AF2 - static let AF2 = Self(rawValue: 0x2) + public static let AF2 = Self(rawValue: 0x2) /// AF3 - static let AF3 = Self(rawValue: 0x3) + public static let AF3 = Self(rawValue: 0x3) /// AF4 - static let AF4 = Self(rawValue: 0x4) + public static let AF4 = Self(rawValue: 0x4) /// AF5 - static let AF5 = Self(rawValue: 0x5) + public static let AF5 = Self(rawValue: 0x5) /// AF6 - static let AF6 = Self(rawValue: 0x6) + public static let AF6 = Self(rawValue: 0x6) /// AF7 - static let AF7 = Self(rawValue: 0x7) + public static let AF7 = Self(rawValue: 0x7) /// AF8 - static let AF8 = Self(rawValue: 0x8) + public static let AF8 = Self(rawValue: 0x8) /// AF9 - static let AF9 = Self(rawValue: 0x9) + public static let AF9 = Self(rawValue: 0x9) /// AF10 - static let AF10 = Self(rawValue: 0xa) + public static let AF10 = Self(rawValue: 0xa) /// AF11 - static let AF11 = Self(rawValue: 0xb) + public static let AF11 = Self(rawValue: 0xb) /// AF12 - static let AF12 = Self(rawValue: 0xc) + public static let AF12 = Self(rawValue: 0xc) /// AF13 - static let AF13 = Self(rawValue: 0xd) + public static let AF13 = Self(rawValue: 0xd) /// AF14 - static let AF14 = Self(rawValue: 0xe) + public static let AF14 = Self(rawValue: 0xe) /// AF15 - static let AF15 = Self(rawValue: 0xf) + public static let AF15 = Self(rawValue: 0xf) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } diff --git a/stm32-lcd-logo/Sources/Application/Registers/GPIOB.swift b/stm32-uart-echo/Sources/STM32F7X6/GPIOB.swift similarity index 68% rename from stm32-lcd-logo/Sources/Application/Registers/GPIOB.swift rename to stm32-uart-echo/Sources/STM32F7X6/GPIOB.swift index c820355f..bd0a35ba 100644 --- a/stm32-lcd-logo/Sources/Application/Registers/GPIOB.swift +++ b/stm32-uart-echo/Sources/STM32F7X6/GPIOB.swift @@ -3,5 +3,5 @@ import MMIO /// General-purpose I/Os -typealias GPIOB = GPIOA +public typealias GPIOB = GPIOA diff --git a/stm32-uart-echo/Sources/Application/Registers/RCC.swift b/stm32-uart-echo/Sources/STM32F7X6/RCC.swift similarity index 55% rename from stm32-uart-echo/Sources/Application/Registers/RCC.swift rename to stm32-uart-echo/Sources/STM32F7X6/RCC.swift index 4f5842ef..4a36aea8 100644 --- a/stm32-uart-echo/Sources/Application/Registers/RCC.swift +++ b/stm32-uart-echo/Sources/STM32F7X6/RCC.swift @@ -4,2829 +4,2829 @@ import MMIO /// Reset and clock control @RegisterBlock -struct RCC { +public struct RCC { /// clock control register @RegisterBlock(offset: 0x0) - var cr: Register + public var cr: Register /// PLL configuration register @RegisterBlock(offset: 0x4) - var pllcfgr: Register + public var pllcfgr: Register /// clock configuration register @RegisterBlock(offset: 0x8) - var cfgr: Register + public var cfgr: Register /// clock interrupt register @RegisterBlock(offset: 0xc) - var cir: Register + public var cir: Register /// AHB1 peripheral reset register @RegisterBlock(offset: 0x10) - var ahb1rstr: Register + public var ahb1rstr: Register /// AHB2 peripheral reset register @RegisterBlock(offset: 0x14) - var ahb2rstr: Register + public var ahb2rstr: Register /// AHB3 peripheral reset register @RegisterBlock(offset: 0x18) - var ahb3rstr: Register + public var ahb3rstr: Register /// APB1 peripheral reset register @RegisterBlock(offset: 0x20) - var apb1rstr: Register + public var apb1rstr: Register /// APB2 peripheral reset register @RegisterBlock(offset: 0x24) - var apb2rstr: Register + public var apb2rstr: Register /// AHB1 peripheral clock register @RegisterBlock(offset: 0x30) - var ahb1enr: Register + public var ahb1enr: Register /// AHB2 peripheral clock enable register @RegisterBlock(offset: 0x34) - var ahb2enr: Register + public var ahb2enr: Register /// AHB3 peripheral clock enable register @RegisterBlock(offset: 0x38) - var ahb3enr: Register + public var ahb3enr: Register /// APB1 peripheral clock enable register @RegisterBlock(offset: 0x40) - var apb1enr: Register + public var apb1enr: Register /// APB2 peripheral clock enable register @RegisterBlock(offset: 0x44) - var apb2enr: Register + public var apb2enr: Register /// AHB1 peripheral clock enable in low power mode register @RegisterBlock(offset: 0x50) - var ahb1lpenr: Register + public var ahb1lpenr: Register /// AHB2 peripheral clock enable in low power mode register @RegisterBlock(offset: 0x54) - var ahb2lpenr: Register + public var ahb2lpenr: Register /// AHB3 peripheral clock enable in low power mode register @RegisterBlock(offset: 0x58) - var ahb3lpenr: Register + public var ahb3lpenr: Register /// APB1 peripheral clock enable in low power mode register @RegisterBlock(offset: 0x60) - var apb1lpenr: Register + public var apb1lpenr: Register /// APB2 peripheral clock enabled in low power mode register @RegisterBlock(offset: 0x64) - var apb2lpenr: Register + public var apb2lpenr: Register /// Backup domain control register @RegisterBlock(offset: 0x70) - var bdcr: Register + public var bdcr: Register /// clock control & status register @RegisterBlock(offset: 0x74) - var csr: Register + public var csr: Register /// spread spectrum clock generation register @RegisterBlock(offset: 0x80) - var sscgr: Register + public var sscgr: Register /// PLLI2S configuration register @RegisterBlock(offset: 0x84) - var plli2scfgr: Register + public var plli2scfgr: Register /// PLL configuration register @RegisterBlock(offset: 0x88) - var pllsaicfgr: Register + public var pllsaicfgr: Register /// dedicated clocks configuration register @RegisterBlock(offset: 0x8c) - var dckcfgr1: Register + public var dckcfgr1: Register /// dedicated clocks configuration register @RegisterBlock(offset: 0x90) - var dckcfgr2: Register + public var dckcfgr2: Register } extension RCC { /// clock control register @Register(bitWidth: 32) - struct CR { + public struct CR { /// PLLI2S clock ready flag @ReadOnly(bits: 27..<28) - var plli2srdy: PLLI2SRDY + public var plli2srdy: PLLI2SRDY /// PLLI2S enable @ReadWrite(bits: 26..<27) - var plli2son: PLLI2SON + public var plli2son: PLLI2SON /// Main PLL (PLL) clock ready flag @ReadOnly(bits: 25..<26) - var pllrdy: PLLRDY + public var pllrdy: PLLRDY /// Main PLL (PLL) enable @ReadWrite(bits: 24..<25) - var pllon: PLLON + public var pllon: PLLON /// Clock security system enable @ReadWrite(bits: 19..<20, as: CSSONValues.self) - var csson: CSSON + public var csson: CSSON /// HSE clock bypass @ReadWrite(bits: 18..<19, as: HSEBYPValues.self) - var hsebyp: HSEBYP + public var hsebyp: HSEBYP /// HSE clock ready flag @ReadOnly(bits: 17..<18) - var hserdy: HSERDY + public var hserdy: HSERDY /// HSE clock enable @ReadWrite(bits: 16..<17) - var hseon: HSEON + public var hseon: HSEON /// Internal high-speed clock calibration @ReadOnly(bits: 8..<16) - var hsical: HSICAL + public var hsical: HSICAL /// Internal high-speed clock trimming @ReadWrite(bits: 3..<8) - var hsitrim: HSITRIM + public var hsitrim: HSITRIM /// Internal high-speed clock ready flag @ReadOnly(bits: 1..<2) - var hsirdy: HSIRDY + public var hsirdy: HSIRDY /// Internal high-speed clock enable @ReadWrite(bits: 0..<1, as: HSIONValues.self) - var hsion: HSION + public var hsion: HSION /// PLLSAI clock ready flag @ReadOnly(bits: 29..<30) - var pllsairdy: PLLSAIRDY + public var pllsairdy: PLLSAIRDY /// PLLSAI enable @ReadWrite(bits: 28..<29) - var pllsaion: PLLSAION + public var pllsaion: PLLSAION } /// PLL configuration register @Register(bitWidth: 32) - struct PLLCFGR { + public struct PLLCFGR { /// Main PLL(PLL) and audio PLL (PLLI2S) entry clock source @ReadWrite(bits: 22..<23, as: PLLSRCValues.self) - var pllsrc: PLLSRC + public var pllsrc: PLLSRC /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock @ReadWrite(bits: 0..<6) - var pllm: PLLM + public var pllm: PLLM /// Main PLL (PLL) multiplication factor for VCO @ReadWrite(bits: 6..<15) - var plln: PLLN + public var plln: PLLN /// Main PLL (PLL) division factor for main system clock @ReadWrite(bits: 16..<18, as: PLLPValues.self) - var pllp: PLLP + public var pllp: PLLP /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks @ReadWrite(bits: 24..<28) - var pllq: PLLQ + public var pllq: PLLQ } /// clock configuration register @Register(bitWidth: 32) - struct CFGR { + public struct CFGR { /// Microcontroller clock output 2 @ReadWrite(bits: 30..<32, as: MCO2Values.self) - var mco2: MCO2 + public var mco2: MCO2 /// MCO2 prescaler @ReadWrite(bits: 27..<30) - var mco2pre: MCO2PRE + public var mco2pre: MCO2PRE /// MCO1 prescaler @ReadWrite(bits: 24..<27, as: MCO1PREValues.self) - var mco1pre: MCO1PRE + public var mco1pre: MCO1PRE /// I2S clock selection @ReadWrite(bits: 23..<24, as: I2SSRCValues.self) - var i2ssrc: I2SSRC + public var i2ssrc: I2SSRC /// Microcontroller clock output 1 @ReadWrite(bits: 21..<23, as: MCO1Values.self) - var mco1: MCO1 + public var mco1: MCO1 /// HSE division factor for RTC clock @ReadWrite(bits: 16..<21) - var rtcpre: RTCPRE + public var rtcpre: RTCPRE /// APB high-speed prescaler (APB2) @ReadWrite(bits: 13..<16) - var ppre2: PPRE2 + public var ppre2: PPRE2 /// APB Low speed prescaler (APB1) @ReadWrite(bits: 10..<13, as: PPRE1Values.self) - var ppre1: PPRE1 + public var ppre1: PPRE1 /// AHB prescaler @ReadWrite(bits: 4..<8, as: HPREValues.self) - var hpre: HPRE + public var hpre: HPRE /// System clock switch @Reserved(bits: 0..<2, as: SWValues.self) - var sw: SW + public var sw: SW /// System clock switch status @Reserved(bits: 2..<4) - var sws: SWS + public var sws: SWS } /// clock interrupt register @Register(bitWidth: 32) - struct CIR { + public struct CIR { /// Clock security system interrupt clear @WriteOnly(bits: 23..<24) - var cssc: CSSC + public var cssc: CSSC /// PLLSAI Ready Interrupt Clear @WriteOnly(bits: 22..<23) - var pllsairdyc: PLLSAIRDYC + public var pllsairdyc: PLLSAIRDYC /// PLLI2S ready interrupt clear @WriteOnly(bits: 21..<22) - var plli2srdyc: PLLI2SRDYC + public var plli2srdyc: PLLI2SRDYC /// Main PLL(PLL) ready interrupt clear @WriteOnly(bits: 20..<21) - var pllrdyc: PLLRDYC + public var pllrdyc: PLLRDYC /// HSE ready interrupt clear @WriteOnly(bits: 19..<20) - var hserdyc: HSERDYC + public var hserdyc: HSERDYC /// HSI ready interrupt clear @WriteOnly(bits: 18..<19) - var hsirdyc: HSIRDYC + public var hsirdyc: HSIRDYC /// LSE ready interrupt clear @WriteOnly(bits: 17..<18) - var lserdyc: LSERDYC + public var lserdyc: LSERDYC /// LSI ready interrupt clear @WriteOnly(bits: 16..<17) - var lsirdyc: LSIRDYC + public var lsirdyc: LSIRDYC /// PLLSAI Ready Interrupt Enable @ReadWrite(bits: 14..<15) - var pllsairdyie: PLLSAIRDYIE + public var pllsairdyie: PLLSAIRDYIE /// PLLI2S ready interrupt enable @ReadWrite(bits: 13..<14) - var plli2srdyie: PLLI2SRDYIE + public var plli2srdyie: PLLI2SRDYIE /// Main PLL (PLL) ready interrupt enable @ReadWrite(bits: 12..<13) - var pllrdyie: PLLRDYIE + public var pllrdyie: PLLRDYIE /// HSE ready interrupt enable @ReadWrite(bits: 11..<12) - var hserdyie: HSERDYIE + public var hserdyie: HSERDYIE /// HSI ready interrupt enable @ReadWrite(bits: 10..<11) - var hsirdyie: HSIRDYIE + public var hsirdyie: HSIRDYIE /// LSE ready interrupt enable @ReadWrite(bits: 9..<10) - var lserdyie: LSERDYIE + public var lserdyie: LSERDYIE /// LSI ready interrupt enable @ReadWrite(bits: 8..<9, as: LSIRDYIEValues.self) - var lsirdyie: LSIRDYIE + public var lsirdyie: LSIRDYIE /// Clock security system interrupt flag @ReadOnly(bits: 7..<8) - var cssf: CSSF + public var cssf: CSSF /// PLLSAI ready interrupt flag @ReadOnly(bits: 6..<7) - var pllsairdyf: PLLSAIRDYF + public var pllsairdyf: PLLSAIRDYF /// PLLI2S ready interrupt flag @ReadOnly(bits: 5..<6) - var plli2srdyf: PLLI2SRDYF + public var plli2srdyf: PLLI2SRDYF /// Main PLL (PLL) ready interrupt flag @ReadOnly(bits: 4..<5) - var pllrdyf: PLLRDYF + public var pllrdyf: PLLRDYF /// HSE ready interrupt flag @ReadOnly(bits: 3..<4) - var hserdyf: HSERDYF + public var hserdyf: HSERDYF /// HSI ready interrupt flag @ReadOnly(bits: 2..<3) - var hsirdyf: HSIRDYF + public var hsirdyf: HSIRDYF /// LSE ready interrupt flag @ReadOnly(bits: 1..<2) - var lserdyf: LSERDYF + public var lserdyf: LSERDYF /// LSI ready interrupt flag @ReadOnly(bits: 0..<1) - var lsirdyf: LSIRDYF + public var lsirdyf: LSIRDYF } /// AHB1 peripheral reset register @Register(bitWidth: 32) - struct AHB1RSTR { + public struct AHB1RSTR { /// USB OTG HS module reset @ReadWrite(bits: 29..<30) - var otghsrst: OTGHSRST + public var otghsrst: OTGHSRST /// Ethernet MAC reset @ReadWrite(bits: 25..<26) - var ethmacrst: ETHMACRST + public var ethmacrst: ETHMACRST /// DMA2D reset @ReadWrite(bits: 23..<24) - var dma2drst: DMA2DRST + public var dma2drst: DMA2DRST /// DMA2 reset @ReadWrite(bits: 22..<23) - var dma2rst: DMA2RST + public var dma2rst: DMA2RST /// DMA2 reset @ReadWrite(bits: 21..<22) - var dma1rst: DMA1RST + public var dma1rst: DMA1RST /// CRC reset @ReadWrite(bits: 12..<13) - var crcrst: CRCRST + public var crcrst: CRCRST /// IO port K reset @ReadWrite(bits: 10..<11) - var gpiokrst: GPIOKRST + public var gpiokrst: GPIOKRST /// IO port J reset @ReadWrite(bits: 9..<10) - var gpiojrst: GPIOJRST + public var gpiojrst: GPIOJRST /// IO port I reset @ReadWrite(bits: 8..<9) - var gpioirst: GPIOIRST + public var gpioirst: GPIOIRST /// IO port H reset @ReadWrite(bits: 7..<8) - var gpiohrst: GPIOHRST + public var gpiohrst: GPIOHRST /// IO port G reset @ReadWrite(bits: 6..<7) - var gpiogrst: GPIOGRST + public var gpiogrst: GPIOGRST /// IO port F reset @ReadWrite(bits: 5..<6) - var gpiofrst: GPIOFRST + public var gpiofrst: GPIOFRST /// IO port E reset @ReadWrite(bits: 4..<5) - var gpioerst: GPIOERST + public var gpioerst: GPIOERST /// IO port D reset @ReadWrite(bits: 3..<4) - var gpiodrst: GPIODRST + public var gpiodrst: GPIODRST /// IO port C reset @ReadWrite(bits: 2..<3) - var gpiocrst: GPIOCRST + public var gpiocrst: GPIOCRST /// IO port B reset @ReadWrite(bits: 1..<2) - var gpiobrst: GPIOBRST + public var gpiobrst: GPIOBRST /// IO port A reset @ReadWrite(bits: 0..<1, as: GPIOARSTValues.self) - var gpioarst: GPIOARST + public var gpioarst: GPIOARST } /// AHB2 peripheral reset register @Register(bitWidth: 32) - struct AHB2RSTR { + public struct AHB2RSTR { /// USB OTG FS module reset @ReadWrite(bits: 7..<8) - var otgfsrst: OTGFSRST + public var otgfsrst: OTGFSRST /// Random number generator module reset @ReadWrite(bits: 6..<7) - var rngrst: RNGRST + public var rngrst: RNGRST /// Hash module reset @ReadWrite(bits: 5..<6) - var hsahrst: HSAHRST + public var hsahrst: HSAHRST /// Cryptographic module reset @ReadWrite(bits: 4..<5) - var cryprst: CRYPRST + public var cryprst: CRYPRST /// Camera interface reset @ReadWrite(bits: 0..<1, as: DCMIRSTValues.self) - var dcmirst: DCMIRST + public var dcmirst: DCMIRST } /// AHB3 peripheral reset register @Register(bitWidth: 32) - struct AHB3RSTR { + public struct AHB3RSTR { /// Flexible memory controller module reset @ReadWrite(bits: 0..<1, as: FMCRSTValues.self) - var fmcrst: FMCRST + public var fmcrst: FMCRST /// Quad SPI memory controller reset @ReadWrite(bits: 1..<2) - var qspirst: QSPIRST + public var qspirst: QSPIRST } /// APB1 peripheral reset register @Register(bitWidth: 32) - struct APB1RSTR { + public struct APB1RSTR { /// TIM2 reset @ReadWrite(bits: 0..<1, as: TIM2RSTValues.self) - var tim2rst: TIM2RST + public var tim2rst: TIM2RST /// TIM3 reset @ReadWrite(bits: 1..<2) - var tim3rst: TIM3RST + public var tim3rst: TIM3RST /// TIM4 reset @ReadWrite(bits: 2..<3) - var tim4rst: TIM4RST + public var tim4rst: TIM4RST /// TIM5 reset @ReadWrite(bits: 3..<4) - var tim5rst: TIM5RST + public var tim5rst: TIM5RST /// TIM6 reset @ReadWrite(bits: 4..<5) - var tim6rst: TIM6RST + public var tim6rst: TIM6RST /// TIM7 reset @ReadWrite(bits: 5..<6) - var tim7rst: TIM7RST + public var tim7rst: TIM7RST /// TIM12 reset @ReadWrite(bits: 6..<7) - var tim12rst: TIM12RST + public var tim12rst: TIM12RST /// TIM13 reset @ReadWrite(bits: 7..<8) - var tim13rst: TIM13RST + public var tim13rst: TIM13RST /// TIM14 reset @ReadWrite(bits: 8..<9) - var tim14rst: TIM14RST + public var tim14rst: TIM14RST /// Window watchdog reset @ReadWrite(bits: 11..<12) - var wwdgrst: WWDGRST + public var wwdgrst: WWDGRST /// SPI 2 reset @ReadWrite(bits: 14..<15) - var spi2rst: SPI2RST + public var spi2rst: SPI2RST /// SPI 3 reset @ReadWrite(bits: 15..<16) - var spi3rst: SPI3RST + public var spi3rst: SPI3RST /// USART 2 reset @ReadWrite(bits: 17..<18) - var usart2rst: USART2RST + public var usart2rst: USART2RST /// USART 3 reset @ReadWrite(bits: 18..<19) - var usart3rst: USART3RST + public var usart3rst: USART3RST /// USART 4 reset @ReadWrite(bits: 19..<20) - var uart4rst: UART4RST + public var uart4rst: UART4RST /// USART 5 reset @ReadWrite(bits: 20..<21) - var uart5rst: UART5RST + public var uart5rst: UART5RST /// I2C 1 reset @ReadWrite(bits: 21..<22) - var i2c1rst: I2C1RST + public var i2c1rst: I2C1RST /// I2C 2 reset @ReadWrite(bits: 22..<23) - var i2c2rst: I2C2RST + public var i2c2rst: I2C2RST /// I2C3 reset @ReadWrite(bits: 23..<24) - var i2c3rst: I2C3RST + public var i2c3rst: I2C3RST /// CAN1 reset @ReadWrite(bits: 25..<26) - var can1rst: CAN1RST + public var can1rst: CAN1RST /// CAN2 reset @ReadWrite(bits: 26..<27) - var can2rst: CAN2RST + public var can2rst: CAN2RST /// Power interface reset @ReadWrite(bits: 28..<29) - var pwrrst: PWRRST + public var pwrrst: PWRRST /// DAC reset @ReadWrite(bits: 29..<30) - var dacrst: DACRST + public var dacrst: DACRST /// UART7 reset @ReadWrite(bits: 30..<31) - var uart7rst: UART7RST + public var uart7rst: UART7RST /// UART8 reset @ReadWrite(bits: 31..<32) - var uart8rst: UART8RST + public var uart8rst: UART8RST /// SPDIF-RX reset @ReadWrite(bits: 16..<17) - var spdifrxrst: SPDIFRXRST + public var spdifrxrst: SPDIFRXRST /// HDMI-CEC reset @ReadWrite(bits: 27..<28) - var cecrst: CECRST + public var cecrst: CECRST /// Low power timer 1 reset @ReadWrite(bits: 9..<10) - var lptim1rst: LPTIM1RST + public var lptim1rst: LPTIM1RST /// I2C 4 reset @ReadWrite(bits: 24..<25) - var i2c4rst: I2C4RST + public var i2c4rst: I2C4RST } /// APB2 peripheral reset register @Register(bitWidth: 32) - struct APB2RSTR { + public struct APB2RSTR { /// TIM1 reset @ReadWrite(bits: 0..<1, as: TIM1RSTValues.self) - var tim1rst: TIM1RST + public var tim1rst: TIM1RST /// TIM8 reset @ReadWrite(bits: 1..<2) - var tim8rst: TIM8RST + public var tim8rst: TIM8RST /// USART1 reset @ReadWrite(bits: 4..<5) - var usart1rst: USART1RST + public var usart1rst: USART1RST /// USART6 reset @ReadWrite(bits: 5..<6) - var usart6rst: USART6RST + public var usart6rst: USART6RST /// ADC interface reset (common to all ADCs) @ReadWrite(bits: 8..<9) - var adcrst: ADCRST + public var adcrst: ADCRST /// SPI 1 reset @ReadWrite(bits: 12..<13) - var spi1rst: SPI1RST + public var spi1rst: SPI1RST /// SPI4 reset @ReadWrite(bits: 13..<14) - var spi4rst: SPI4RST + public var spi4rst: SPI4RST /// System configuration controller reset @ReadWrite(bits: 14..<15) - var syscfgrst: SYSCFGRST + public var syscfgrst: SYSCFGRST /// TIM9 reset @ReadWrite(bits: 16..<17) - var tim9rst: TIM9RST + public var tim9rst: TIM9RST /// TIM10 reset @ReadWrite(bits: 17..<18) - var tim10rst: TIM10RST + public var tim10rst: TIM10RST /// TIM11 reset @ReadWrite(bits: 18..<19) - var tim11rst: TIM11RST + public var tim11rst: TIM11RST /// SPI5 reset @ReadWrite(bits: 20..<21) - var spi5rst: SPI5RST + public var spi5rst: SPI5RST /// SPI6 reset @ReadWrite(bits: 21..<22) - var spi6rst: SPI6RST + public var spi6rst: SPI6RST /// SAI1 reset @ReadWrite(bits: 22..<23) - var sai1rst: SAI1RST + public var sai1rst: SAI1RST /// LTDC reset @ReadWrite(bits: 26..<27) - var ltdcrst: LTDCRST + public var ltdcrst: LTDCRST /// SAI2 reset @ReadWrite(bits: 23..<24) - var sai2rst: SAI2RST + public var sai2rst: SAI2RST /// SDMMC1 reset @ReadWrite(bits: 11..<12) - var sdmmc1rst: SDMMC1RST + public var sdmmc1rst: SDMMC1RST } /// AHB1 peripheral clock register @Register(bitWidth: 32) - struct AHB1ENR { + public struct AHB1ENR { /// USB OTG HSULPI clock enable @ReadWrite(bits: 30..<31) - var otghsulpien: OTGHSULPIEN + public var otghsulpien: OTGHSULPIEN /// USB OTG HS clock enable @ReadWrite(bits: 29..<30) - var otghsen: OTGHSEN + public var otghsen: OTGHSEN /// Ethernet PTP clock enable @ReadWrite(bits: 28..<29) - var ethmacptpen: ETHMACPTPEN + public var ethmacptpen: ETHMACPTPEN /// Ethernet Reception clock enable @ReadWrite(bits: 27..<28) - var ethmacrxen: ETHMACRXEN + public var ethmacrxen: ETHMACRXEN /// Ethernet Transmission clock enable @ReadWrite(bits: 26..<27) - var ethmactxen: ETHMACTXEN + public var ethmactxen: ETHMACTXEN /// Ethernet MAC clock enable @ReadWrite(bits: 25..<26) - var ethmacen: ETHMACEN + public var ethmacen: ETHMACEN /// DMA2D clock enable @ReadWrite(bits: 23..<24) - var dma2den: DMA2DEN + public var dma2den: DMA2DEN /// DMA2 clock enable @ReadWrite(bits: 22..<23) - var dma2en: DMA2EN + public var dma2en: DMA2EN /// DMA1 clock enable @ReadWrite(bits: 21..<22) - var dma1en: DMA1EN + public var dma1en: DMA1EN /// CCM data RAM clock enable @ReadWrite(bits: 20..<21) - var dtcmramen: DTCMRAMEN + public var dtcmramen: DTCMRAMEN /// Backup SRAM interface clock enable @ReadWrite(bits: 18..<19) - var bkpsramen: BKPSRAMEN + public var bkpsramen: BKPSRAMEN /// CRC clock enable @ReadWrite(bits: 12..<13) - var crcen: CRCEN + public var crcen: CRCEN /// IO port K clock enable @ReadWrite(bits: 10..<11) - var gpioken: GPIOKEN + public var gpioken: GPIOKEN /// IO port J clock enable @ReadWrite(bits: 9..<10) - var gpiojen: GPIOJEN + public var gpiojen: GPIOJEN /// IO port I clock enable @ReadWrite(bits: 8..<9) - var gpioien: GPIOIEN + public var gpioien: GPIOIEN /// IO port H clock enable @ReadWrite(bits: 7..<8) - var gpiohen: GPIOHEN + public var gpiohen: GPIOHEN /// IO port G clock enable @ReadWrite(bits: 6..<7) - var gpiogen: GPIOGEN + public var gpiogen: GPIOGEN /// IO port F clock enable @ReadWrite(bits: 5..<6) - var gpiofen: GPIOFEN + public var gpiofen: GPIOFEN /// IO port E clock enable @ReadWrite(bits: 4..<5) - var gpioeen: GPIOEEN + public var gpioeen: GPIOEEN /// IO port D clock enable @ReadWrite(bits: 3..<4) - var gpioden: GPIODEN + public var gpioden: GPIODEN /// IO port C clock enable @ReadWrite(bits: 2..<3) - var gpiocen: GPIOCEN + public var gpiocen: GPIOCEN /// IO port B clock enable @ReadWrite(bits: 1..<2) - var gpioben: GPIOBEN + public var gpioben: GPIOBEN /// IO port A clock enable @ReadWrite(bits: 0..<1, as: GPIOAENValues.self) - var gpioaen: GPIOAEN + public var gpioaen: GPIOAEN } /// AHB2 peripheral clock enable register @Register(bitWidth: 32) - struct AHB2ENR { + public struct AHB2ENR { /// USB OTG FS clock enable @ReadWrite(bits: 7..<8) - var otgfsen: OTGFSEN + public var otgfsen: OTGFSEN /// Random number generator clock enable @ReadWrite(bits: 6..<7) - var rngen: RNGEN + public var rngen: RNGEN /// Hash modules clock enable @ReadWrite(bits: 5..<6) - var hashen: HASHEN + public var hashen: HASHEN /// Cryptographic modules clock enable @ReadWrite(bits: 4..<5) - var crypen: CRYPEN + public var crypen: CRYPEN /// Camera interface enable @ReadWrite(bits: 0..<1, as: DCMIENValues.self) - var dcmien: DCMIEN + public var dcmien: DCMIEN } /// AHB3 peripheral clock enable register @Register(bitWidth: 32) - struct AHB3ENR { + public struct AHB3ENR { /// Flexible memory controller module clock enable @ReadWrite(bits: 0..<1, as: FMCENValues.self) - var fmcen: FMCEN + public var fmcen: FMCEN /// Quad SPI memory controller clock enable @ReadWrite(bits: 1..<2) - var qspien: QSPIEN + public var qspien: QSPIEN } /// APB1 peripheral clock enable register @Register(bitWidth: 32) - struct APB1ENR { + public struct APB1ENR { /// TIM2 clock enable @ReadWrite(bits: 0..<1, as: TIM2ENValues.self) - var tim2en: TIM2EN + public var tim2en: TIM2EN /// TIM3 clock enable @ReadWrite(bits: 1..<2) - var tim3en: TIM3EN + public var tim3en: TIM3EN /// TIM4 clock enable @ReadWrite(bits: 2..<3) - var tim4en: TIM4EN + public var tim4en: TIM4EN /// TIM5 clock enable @ReadWrite(bits: 3..<4) - var tim5en: TIM5EN + public var tim5en: TIM5EN /// TIM6 clock enable @ReadWrite(bits: 4..<5) - var tim6en: TIM6EN + public var tim6en: TIM6EN /// TIM7 clock enable @ReadWrite(bits: 5..<6) - var tim7en: TIM7EN + public var tim7en: TIM7EN /// TIM12 clock enable @ReadWrite(bits: 6..<7) - var tim12en: TIM12EN + public var tim12en: TIM12EN /// TIM13 clock enable @ReadWrite(bits: 7..<8) - var tim13en: TIM13EN + public var tim13en: TIM13EN /// TIM14 clock enable @ReadWrite(bits: 8..<9) - var tim14en: TIM14EN + public var tim14en: TIM14EN /// Window watchdog clock enable @ReadWrite(bits: 11..<12) - var wwdgen: WWDGEN + public var wwdgen: WWDGEN /// SPI2 clock enable @ReadWrite(bits: 14..<15) - var spi2en: SPI2EN + public var spi2en: SPI2EN /// SPI3 clock enable @ReadWrite(bits: 15..<16) - var spi3en: SPI3EN + public var spi3en: SPI3EN /// USART 2 clock enable @ReadWrite(bits: 17..<18) - var usart2en: USART2EN + public var usart2en: USART2EN /// USART3 clock enable @ReadWrite(bits: 18..<19) - var usart3en: USART3EN + public var usart3en: USART3EN /// UART4 clock enable @ReadWrite(bits: 19..<20) - var uart4en: UART4EN + public var uart4en: UART4EN /// UART5 clock enable @ReadWrite(bits: 20..<21) - var uart5en: UART5EN + public var uart5en: UART5EN /// I2C1 clock enable @ReadWrite(bits: 21..<22) - var i2c1en: I2C1EN + public var i2c1en: I2C1EN /// I2C2 clock enable @ReadWrite(bits: 22..<23) - var i2c2en: I2C2EN + public var i2c2en: I2C2EN /// I2C3 clock enable @ReadWrite(bits: 23..<24) - var i2c3en: I2C3EN + public var i2c3en: I2C3EN /// CAN 1 clock enable @ReadWrite(bits: 25..<26) - var can1en: CAN1EN + public var can1en: CAN1EN /// CAN 2 clock enable @ReadWrite(bits: 26..<27) - var can2en: CAN2EN + public var can2en: CAN2EN /// Power interface clock enable @ReadWrite(bits: 28..<29) - var pwren: PWREN + public var pwren: PWREN /// DAC interface clock enable @ReadWrite(bits: 29..<30) - var dacen: DACEN + public var dacen: DACEN /// UART7 clock enable @ReadWrite(bits: 30..<31) - var uart7en: UART7EN + public var uart7en: UART7EN /// UART8 clock enable @ReadWrite(bits: 31..<32) - var uart8en: UART8EN + public var uart8en: UART8EN /// SPDIF-RX clock enable @ReadWrite(bits: 16..<17) - var spdifrxen: SPDIFRXEN + public var spdifrxen: SPDIFRXEN /// HDMI-CEN clock enable @ReadWrite(bits: 27..<28) - var cecen: CECEN + public var cecen: CECEN /// Low power timer 1 clock enable @ReadWrite(bits: 9..<10) - var lptim1en: LPTIM1EN + public var lptim1en: LPTIM1EN /// I2C4 clock enable @ReadWrite(bits: 24..<25) - var i2c4en: I2C4EN + public var i2c4en: I2C4EN } /// APB2 peripheral clock enable register @Register(bitWidth: 32) - struct APB2ENR { + public struct APB2ENR { /// TIM1 clock enable @ReadWrite(bits: 0..<1, as: TIM1ENValues.self) - var tim1en: TIM1EN + public var tim1en: TIM1EN /// TIM8 clock enable @ReadWrite(bits: 1..<2) - var tim8en: TIM8EN + public var tim8en: TIM8EN /// USART1 clock enable @ReadWrite(bits: 4..<5) - var usart1en: USART1EN + public var usart1en: USART1EN /// USART6 clock enable @ReadWrite(bits: 5..<6) - var usart6en: USART6EN + public var usart6en: USART6EN /// ADC1 clock enable @ReadWrite(bits: 8..<9) - var adc1en: ADC1EN + public var adc1en: ADC1EN /// ADC2 clock enable @ReadWrite(bits: 9..<10) - var adc2en: ADC2EN + public var adc2en: ADC2EN /// ADC3 clock enable @ReadWrite(bits: 10..<11) - var adc3en: ADC3EN + public var adc3en: ADC3EN /// SPI1 clock enable @ReadWrite(bits: 12..<13) - var spi1en: SPI1EN + public var spi1en: SPI1EN /// SPI4 clock enable @ReadWrite(bits: 13..<14) - var spi4en: SPI4EN + public var spi4en: SPI4EN /// System configuration controller clock enable @ReadWrite(bits: 14..<15) - var syscfgen: SYSCFGEN + public var syscfgen: SYSCFGEN /// TIM9 clock enable @ReadWrite(bits: 16..<17) - var tim9en: TIM9EN + public var tim9en: TIM9EN /// TIM10 clock enable @ReadWrite(bits: 17..<18) - var tim10en: TIM10EN + public var tim10en: TIM10EN /// TIM11 clock enable @ReadWrite(bits: 18..<19) - var tim11en: TIM11EN + public var tim11en: TIM11EN /// SPI5 clock enable @ReadWrite(bits: 20..<21) - var spi5en: SPI5EN + public var spi5en: SPI5EN /// SPI6 clock enable @ReadWrite(bits: 21..<22) - var spi6en: SPI6EN + public var spi6en: SPI6EN /// SAI1 clock enable @ReadWrite(bits: 22..<23) - var sai1en: SAI1EN + public var sai1en: SAI1EN /// LTDC clock enable @ReadWrite(bits: 26..<27) - var ltdcen: LTDCEN + public var ltdcen: LTDCEN /// SAI2 clock enable @ReadWrite(bits: 23..<24) - var sai2en: SAI2EN + public var sai2en: SAI2EN /// SDMMC1 clock enable @ReadWrite(bits: 11..<12) - var sdmmc1en: SDMMC1EN + public var sdmmc1en: SDMMC1EN } /// AHB1 peripheral clock enable in low power mode register @Register(bitWidth: 32) - struct AHB1LPENR { + public struct AHB1LPENR { /// IO port A clock enable during sleep mode @ReadWrite(bits: 0..<1, as: GPIOALPENValues.self) - var gpioalpen: GPIOALPEN + public var gpioalpen: GPIOALPEN /// IO port B clock enable during Sleep mode @ReadWrite(bits: 1..<2) - var gpioblpen: GPIOBLPEN + public var gpioblpen: GPIOBLPEN /// IO port C clock enable during Sleep mode @ReadWrite(bits: 2..<3) - var gpioclpen: GPIOCLPEN + public var gpioclpen: GPIOCLPEN /// IO port D clock enable during Sleep mode @ReadWrite(bits: 3..<4) - var gpiodlpen: GPIODLPEN + public var gpiodlpen: GPIODLPEN /// IO port E clock enable during Sleep mode @ReadWrite(bits: 4..<5) - var gpioelpen: GPIOELPEN + public var gpioelpen: GPIOELPEN /// IO port F clock enable during Sleep mode @ReadWrite(bits: 5..<6) - var gpioflpen: GPIOFLPEN + public var gpioflpen: GPIOFLPEN /// IO port G clock enable during Sleep mode @ReadWrite(bits: 6..<7) - var gpioglpen: GPIOGLPEN + public var gpioglpen: GPIOGLPEN /// IO port H clock enable during Sleep mode @ReadWrite(bits: 7..<8) - var gpiohlpen: GPIOHLPEN + public var gpiohlpen: GPIOHLPEN /// IO port I clock enable during Sleep mode @ReadWrite(bits: 8..<9) - var gpioilpen: GPIOILPEN + public var gpioilpen: GPIOILPEN /// IO port J clock enable during Sleep mode @ReadWrite(bits: 9..<10) - var gpiojlpen: GPIOJLPEN + public var gpiojlpen: GPIOJLPEN /// IO port K clock enable during Sleep mode @ReadWrite(bits: 10..<11) - var gpioklpen: GPIOKLPEN + public var gpioklpen: GPIOKLPEN /// CRC clock enable during Sleep mode @ReadWrite(bits: 12..<13) - var crclpen: CRCLPEN + public var crclpen: CRCLPEN /// Flash interface clock enable during Sleep mode @ReadWrite(bits: 15..<16) - var flitflpen: FLITFLPEN + public var flitflpen: FLITFLPEN /// SRAM 1interface clock enable during Sleep mode @ReadWrite(bits: 16..<17) - var sram1lpen: SRAM1LPEN + public var sram1lpen: SRAM1LPEN /// SRAM 2 interface clock enable during Sleep mode @ReadWrite(bits: 17..<18) - var sram2lpen: SRAM2LPEN + public var sram2lpen: SRAM2LPEN /// Backup SRAM interface clock enable during Sleep mode @ReadWrite(bits: 18..<19) - var bkpsramlpen: BKPSRAMLPEN + public var bkpsramlpen: BKPSRAMLPEN /// SRAM 3 interface clock enable during Sleep mode @ReadWrite(bits: 19..<20) - var sram3lpen: SRAM3LPEN + public var sram3lpen: SRAM3LPEN /// DMA1 clock enable during Sleep mode @ReadWrite(bits: 21..<22) - var dma1lpen: DMA1LPEN + public var dma1lpen: DMA1LPEN /// DMA2 clock enable during Sleep mode @ReadWrite(bits: 22..<23) - var dma2lpen: DMA2LPEN + public var dma2lpen: DMA2LPEN /// DMA2D clock enable during Sleep mode @ReadWrite(bits: 23..<24) - var dma2dlpen: DMA2DLPEN + public var dma2dlpen: DMA2DLPEN /// Ethernet MAC clock enable during Sleep mode @ReadWrite(bits: 25..<26) - var ethmaclpen: ETHMACLPEN + public var ethmaclpen: ETHMACLPEN /// Ethernet transmission clock enable during Sleep mode @ReadWrite(bits: 26..<27) - var ethmactxlpen: ETHMACTXLPEN + public var ethmactxlpen: ETHMACTXLPEN /// Ethernet reception clock enable during Sleep mode @ReadWrite(bits: 27..<28) - var ethmacrxlpen: ETHMACRXLPEN + public var ethmacrxlpen: ETHMACRXLPEN /// Ethernet PTP clock enable during Sleep mode @ReadWrite(bits: 28..<29) - var ethmacptplpen: ETHMACPTPLPEN + public var ethmacptplpen: ETHMACPTPLPEN /// USB OTG HS clock enable during Sleep mode @ReadWrite(bits: 29..<30) - var otghslpen: OTGHSLPEN + public var otghslpen: OTGHSLPEN /// USB OTG HS ULPI clock enable during Sleep mode @ReadWrite(bits: 30..<31) - var otghsulpilpen: OTGHSULPILPEN + public var otghsulpilpen: OTGHSULPILPEN /// AXI to AHB bridge clock enable during Sleep mode @ReadWrite(bits: 13..<14) - var axilpen: AXILPEN + public var axilpen: AXILPEN /// DTCM RAM interface clock enable during Sleep mode @ReadWrite(bits: 20..<21) - var dtcmlpen: DTCMLPEN + public var dtcmlpen: DTCMLPEN } /// AHB2 peripheral clock enable in low power mode register @Register(bitWidth: 32) - struct AHB2LPENR { + public struct AHB2LPENR { /// USB OTG FS clock enable during Sleep mode @ReadWrite(bits: 7..<8) - var otgfslpen: OTGFSLPEN + public var otgfslpen: OTGFSLPEN /// Random number generator clock enable during Sleep mode @ReadWrite(bits: 6..<7) - var rnglpen: RNGLPEN + public var rnglpen: RNGLPEN /// Hash modules clock enable during Sleep mode @ReadWrite(bits: 5..<6) - var hashlpen: HASHLPEN + public var hashlpen: HASHLPEN /// Cryptography modules clock enable during Sleep mode @ReadWrite(bits: 4..<5) - var cryplpen: CRYPLPEN + public var cryplpen: CRYPLPEN /// Camera interface enable during Sleep mode @ReadWrite(bits: 0..<1, as: DCMILPENValues.self) - var dcmilpen: DCMILPEN + public var dcmilpen: DCMILPEN } /// AHB3 peripheral clock enable in low power mode register @Register(bitWidth: 32) - struct AHB3LPENR { + public struct AHB3LPENR { /// Flexible memory controller module clock enable during Sleep mode @ReadWrite(bits: 0..<1, as: FMCLPENValues.self) - var fmclpen: FMCLPEN + public var fmclpen: FMCLPEN /// Quand SPI memory controller clock enable during Sleep mode @ReadWrite(bits: 1..<2) - var qspilpen: QSPILPEN + public var qspilpen: QSPILPEN } /// APB1 peripheral clock enable in low power mode register @Register(bitWidth: 32) - struct APB1LPENR { + public struct APB1LPENR { /// TIM2 clock enable during Sleep mode @ReadWrite(bits: 0..<1, as: TIM2LPENValues.self) - var tim2lpen: TIM2LPEN + public var tim2lpen: TIM2LPEN /// TIM3 clock enable during Sleep mode @ReadWrite(bits: 1..<2) - var tim3lpen: TIM3LPEN + public var tim3lpen: TIM3LPEN /// TIM4 clock enable during Sleep mode @ReadWrite(bits: 2..<3) - var tim4lpen: TIM4LPEN + public var tim4lpen: TIM4LPEN /// TIM5 clock enable during Sleep mode @ReadWrite(bits: 3..<4) - var tim5lpen: TIM5LPEN + public var tim5lpen: TIM5LPEN /// TIM6 clock enable during Sleep mode @ReadWrite(bits: 4..<5) - var tim6lpen: TIM6LPEN + public var tim6lpen: TIM6LPEN /// TIM7 clock enable during Sleep mode @ReadWrite(bits: 5..<6) - var tim7lpen: TIM7LPEN + public var tim7lpen: TIM7LPEN /// TIM12 clock enable during Sleep mode @ReadWrite(bits: 6..<7) - var tim12lpen: TIM12LPEN + public var tim12lpen: TIM12LPEN /// TIM13 clock enable during Sleep mode @ReadWrite(bits: 7..<8) - var tim13lpen: TIM13LPEN + public var tim13lpen: TIM13LPEN /// TIM14 clock enable during Sleep mode @ReadWrite(bits: 8..<9) - var tim14lpen: TIM14LPEN + public var tim14lpen: TIM14LPEN /// Window watchdog clock enable during Sleep mode @ReadWrite(bits: 11..<12) - var wwdglpen: WWDGLPEN + public var wwdglpen: WWDGLPEN /// SPI2 clock enable during Sleep mode @ReadWrite(bits: 14..<15) - var spi2lpen: SPI2LPEN + public var spi2lpen: SPI2LPEN /// SPI3 clock enable during Sleep mode @ReadWrite(bits: 15..<16) - var spi3lpen: SPI3LPEN + public var spi3lpen: SPI3LPEN /// USART2 clock enable during Sleep mode @ReadWrite(bits: 17..<18) - var usart2lpen: USART2LPEN + public var usart2lpen: USART2LPEN /// USART3 clock enable during Sleep mode @ReadWrite(bits: 18..<19) - var usart3lpen: USART3LPEN + public var usart3lpen: USART3LPEN /// UART4 clock enable during Sleep mode @ReadWrite(bits: 19..<20) - var uart4lpen: UART4LPEN + public var uart4lpen: UART4LPEN /// UART5 clock enable during Sleep mode @ReadWrite(bits: 20..<21) - var uart5lpen: UART5LPEN + public var uart5lpen: UART5LPEN /// I2C1 clock enable during Sleep mode @ReadWrite(bits: 21..<22) - var i2c1lpen: I2C1LPEN + public var i2c1lpen: I2C1LPEN /// I2C2 clock enable during Sleep mode @ReadWrite(bits: 22..<23) - var i2c2lpen: I2C2LPEN + public var i2c2lpen: I2C2LPEN /// I2C3 clock enable during Sleep mode @ReadWrite(bits: 23..<24) - var i2c3lpen: I2C3LPEN + public var i2c3lpen: I2C3LPEN /// CAN 1 clock enable during Sleep mode @ReadWrite(bits: 25..<26) - var can1lpen: CAN1LPEN + public var can1lpen: CAN1LPEN /// CAN 2 clock enable during Sleep mode @ReadWrite(bits: 26..<27) - var can2lpen: CAN2LPEN + public var can2lpen: CAN2LPEN /// Power interface clock enable during Sleep mode @ReadWrite(bits: 28..<29) - var pwrlpen: PWRLPEN + public var pwrlpen: PWRLPEN /// DAC interface clock enable during Sleep mode @ReadWrite(bits: 29..<30) - var daclpen: DACLPEN + public var daclpen: DACLPEN /// UART7 clock enable during Sleep mode @ReadWrite(bits: 30..<31) - var uart7lpen: UART7LPEN + public var uart7lpen: UART7LPEN /// UART8 clock enable during Sleep mode @ReadWrite(bits: 31..<32) - var uart8lpen: UART8LPEN + public var uart8lpen: UART8LPEN /// SPDIF-RX clock enable during sleep mode @ReadWrite(bits: 16..<17) - var spdifrxlpen: SPDIFRXLPEN + public var spdifrxlpen: SPDIFRXLPEN /// HDMI-CEN clock enable during Sleep mode @ReadWrite(bits: 27..<28) - var ceclpen: CECLPEN + public var ceclpen: CECLPEN /// low power timer 1 clock enable during Sleep mode @ReadWrite(bits: 9..<10) - var lptim1lpen: LPTIM1LPEN + public var lptim1lpen: LPTIM1LPEN /// I2C4 clock enable during Sleep mode @ReadWrite(bits: 24..<25) - var i2c4lpen: I2C4LPEN + public var i2c4lpen: I2C4LPEN } /// APB2 peripheral clock enabled in low power mode register @Register(bitWidth: 32) - struct APB2LPENR { + public struct APB2LPENR { /// TIM1 clock enable during Sleep mode @ReadWrite(bits: 0..<1, as: TIM1LPENValues.self) - var tim1lpen: TIM1LPEN + public var tim1lpen: TIM1LPEN /// TIM8 clock enable during Sleep mode @ReadWrite(bits: 1..<2) - var tim8lpen: TIM8LPEN + public var tim8lpen: TIM8LPEN /// USART1 clock enable during Sleep mode @ReadWrite(bits: 4..<5) - var usart1lpen: USART1LPEN + public var usart1lpen: USART1LPEN /// USART6 clock enable during Sleep mode @ReadWrite(bits: 5..<6) - var usart6lpen: USART6LPEN + public var usart6lpen: USART6LPEN /// ADC1 clock enable during Sleep mode @ReadWrite(bits: 8..<9) - var adc1lpen: ADC1LPEN + public var adc1lpen: ADC1LPEN /// ADC2 clock enable during Sleep mode @ReadWrite(bits: 9..<10) - var adc2lpen: ADC2LPEN + public var adc2lpen: ADC2LPEN /// ADC 3 clock enable during Sleep mode @ReadWrite(bits: 10..<11) - var adc3lpen: ADC3LPEN + public var adc3lpen: ADC3LPEN /// SPI 1 clock enable during Sleep mode @ReadWrite(bits: 12..<13) - var spi1lpen: SPI1LPEN + public var spi1lpen: SPI1LPEN /// SPI 4 clock enable during Sleep mode @ReadWrite(bits: 13..<14) - var spi4lpen: SPI4LPEN + public var spi4lpen: SPI4LPEN /// System configuration controller clock enable during Sleep mode @ReadWrite(bits: 14..<15) - var syscfglpen: SYSCFGLPEN + public var syscfglpen: SYSCFGLPEN /// TIM9 clock enable during sleep mode @ReadWrite(bits: 16..<17) - var tim9lpen: TIM9LPEN + public var tim9lpen: TIM9LPEN /// TIM10 clock enable during Sleep mode @ReadWrite(bits: 17..<18) - var tim10lpen: TIM10LPEN + public var tim10lpen: TIM10LPEN /// TIM11 clock enable during Sleep mode @ReadWrite(bits: 18..<19) - var tim11lpen: TIM11LPEN + public var tim11lpen: TIM11LPEN /// SPI 5 clock enable during Sleep mode @ReadWrite(bits: 20..<21) - var spi5lpen: SPI5LPEN + public var spi5lpen: SPI5LPEN /// SPI 6 clock enable during Sleep mode @ReadWrite(bits: 21..<22) - var spi6lpen: SPI6LPEN + public var spi6lpen: SPI6LPEN /// SAI1 clock enable during sleep mode @ReadWrite(bits: 22..<23) - var sai1lpen: SAI1LPEN + public var sai1lpen: SAI1LPEN /// LTDC clock enable during sleep mode @ReadWrite(bits: 26..<27) - var ltdclpen: LTDCLPEN + public var ltdclpen: LTDCLPEN /// SAI2 clock enable during sleep mode @ReadWrite(bits: 23..<24) - var sai2lpen: SAI2LPEN + public var sai2lpen: SAI2LPEN /// SDMMC1 clock enable during Sleep mode @ReadWrite(bits: 11..<12) - var sdmmc1lpen: SDMMC1LPEN + public var sdmmc1lpen: SDMMC1LPEN } /// Backup domain control register @Register(bitWidth: 32) - struct BDCR { + public struct BDCR { /// Backup domain software reset @ReadWrite(bits: 16..<17, as: BDRSTValues.self) - var bdrst: BDRST + public var bdrst: BDRST /// RTC clock enable @ReadWrite(bits: 15..<16, as: RTCENValues.self) - var rtcen: RTCEN + public var rtcen: RTCEN /// External low-speed oscillator bypass @ReadWrite(bits: 2..<3, as: LSEBYPValues.self) - var lsebyp: LSEBYP + public var lsebyp: LSEBYP /// External low-speed oscillator ready @ReadOnly(bits: 1..<2) - var lserdy: LSERDY + public var lserdy: LSERDY /// External low-speed oscillator enable @ReadWrite(bits: 0..<1, as: LSEONValues.self) - var lseon: LSEON + public var lseon: LSEON /// LSE oscillator drive capability @ReadWrite(bits: 3..<5, as: LSEDRVValues.self) - var lsedrv: LSEDRV + public var lsedrv: LSEDRV /// RTC clock source selection @Reserved(bits: 8..<10, as: RTCSELValues.self) - var rtcsel: RTCSEL + public var rtcsel: RTCSEL } /// clock control & status register @Register(bitWidth: 32) - struct CSR { + public struct CSR { /// Low-power reset flag @ReadWrite(bits: 31..<32) - var lpwrrstf: LPWRRSTF + public var lpwrrstf: LPWRRSTF /// Window watchdog reset flag @ReadWrite(bits: 30..<31) - var wwdgrstf: WWDGRSTF + public var wwdgrstf: WWDGRSTF /// Independent watchdog reset flag @ReadWrite(bits: 29..<30) - var wdgrstf: WDGRSTF + public var wdgrstf: WDGRSTF /// Software reset flag @ReadWrite(bits: 28..<29) - var sftrstf: SFTRSTF + public var sftrstf: SFTRSTF /// POR/PDR reset flag @ReadWrite(bits: 27..<28) - var porrstf: PORRSTF + public var porrstf: PORRSTF /// PIN reset flag @ReadWrite(bits: 26..<27) - var padrstf: PADRSTF + public var padrstf: PADRSTF /// BOR reset flag @ReadWrite(bits: 25..<26) - var borrstf: BORRSTF + public var borrstf: BORRSTF /// Remove reset flag @ReadWrite(bits: 24..<25) - var rmvf: RMVF + public var rmvf: RMVF /// Internal low-speed oscillator ready @ReadOnly(bits: 1..<2) - var lsirdy: LSIRDY + public var lsirdy: LSIRDY /// Internal low-speed oscillator enable @ReadWrite(bits: 0..<1, as: LSIONValues.self) - var lsion: LSION + public var lsion: LSION } /// spread spectrum clock generation register @Register(bitWidth: 32) - struct SSCGR { + public struct SSCGR { /// Spread spectrum modulation enable @ReadWrite(bits: 31..<32, as: SSCGENValues.self) - var sscgen: SSCGEN + public var sscgen: SSCGEN /// Spread Select @ReadWrite(bits: 30..<31, as: SPREADSELValues.self) - var spreadsel: SPREADSEL + public var spreadsel: SPREADSEL /// Incrementation step @ReadWrite(bits: 13..<28) - var incstep: INCSTEP + public var incstep: INCSTEP /// Modulation period @ReadWrite(bits: 0..<13) - var modper: MODPER + public var modper: MODPER } /// PLLI2S configuration register @Register(bitWidth: 32) - struct PLLI2SCFGR { + public struct PLLI2SCFGR { /// PLLI2S division factor for I2S clocks @ReadWrite(bits: 28..<31) - var plli2sr: PLLI2SR + public var plli2sr: PLLI2SR /// PLLI2S division factor for SAI1 clock @ReadWrite(bits: 24..<28) - var plli2sq: PLLI2SQ + public var plli2sq: PLLI2SQ /// PLLI2S multiplication factor for VCO @ReadWrite(bits: 6..<15) - var plli2sn: PLLI2SN + public var plli2sn: PLLI2SN /// PLLI2S division factor for SPDIFRX clock @ReadWrite(bits: 16..<18, as: PLLI2SPValues.self) - var plli2sp: PLLI2SP + public var plli2sp: PLLI2SP } /// PLL configuration register @Register(bitWidth: 32) - struct PLLSAICFGR { + public struct PLLSAICFGR { /// PLLSAI division factor for VCO @ReadWrite(bits: 6..<15) - var pllsain: PLLSAIN + public var pllsain: PLLSAIN /// PLLSAI division factor for 48MHz clock @ReadWrite(bits: 16..<18, as: PLLSAIPValues.self) - var pllsaip: PLLSAIP + public var pllsaip: PLLSAIP /// PLLSAI division factor for SAI clock @ReadWrite(bits: 24..<28) - var pllsaiq: PLLSAIQ + public var pllsaiq: PLLSAIQ /// PLLSAI division factor for LCD clock @ReadWrite(bits: 28..<31) - var pllsair: PLLSAIR + public var pllsair: PLLSAIR } /// dedicated clocks configuration register @Register(bitWidth: 32) - struct DCKCFGR1 { + public struct DCKCFGR1 { /// PLLI2S division factor for SAI1 clock @ReadWrite(bits: 0..<5, as: PLLI2SDIVQValues.self) - var plli2sdivq: PLLI2SDIVQ + public var plli2sdivq: PLLI2SDIVQ /// PLLSAI division factor for SAI1 clock @ReadWrite(bits: 8..<13, as: PLLSAIDIVQValues.self) - var pllsaidivq: PLLSAIDIVQ + public var pllsaidivq: PLLSAIDIVQ /// division factor for LCD_CLK @ReadWrite(bits: 16..<18, as: PLLSAIDIVRValues.self) - var pllsaidivr: PLLSAIDIVR + public var pllsaidivr: PLLSAIDIVR /// SAI1 clock source selection @ReadWrite(bits: 20..<22, as: SAI1SELValues.self) - var sai1sel: SAI1SEL + public var sai1sel: SAI1SEL /// SAI2 clock source selection @ReadWrite(bits: 22..<24, as: SAI2SELValues.self) - var sai2sel: SAI2SEL + public var sai2sel: SAI2SEL /// Timers clocks prescalers selection @ReadWrite(bits: 24..<25, as: TIMPREValues.self) - var timpre: TIMPRE + public var timpre: TIMPRE } /// dedicated clocks configuration register @Register(bitWidth: 32) - struct DCKCFGR2 { + public struct DCKCFGR2 { /// USART 1 clock source selection @ReadWrite(bits: 0..<2, as: USART1SELValues.self) - var usart1sel: USART1SEL + public var usart1sel: USART1SEL /// USART 2 clock source selection @ReadWrite(bits: 2..<4, as: USART2SELValues.self) - var usart2sel: USART2SEL + public var usart2sel: USART2SEL /// USART 3 clock source selection @ReadWrite(bits: 4..<6) - var usart3sel: USART3SEL + public var usart3sel: USART3SEL /// UART 4 clock source selection @ReadWrite(bits: 6..<8) - var uart4sel: UART4SEL + public var uart4sel: UART4SEL /// UART 5 clock source selection @ReadWrite(bits: 8..<10) - var uart5sel: UART5SEL + public var uart5sel: UART5SEL /// USART 6 clock source selection @ReadWrite(bits: 10..<12) - var usart6sel: USART6SEL + public var usart6sel: USART6SEL /// UART 7 clock source selection @ReadWrite(bits: 12..<14) - var uart7sel: UART7SEL + public var uart7sel: UART7SEL /// UART 8 clock source selection @ReadWrite(bits: 14..<16) - var uart8sel: UART8SEL + public var uart8sel: UART8SEL /// I2C1 clock source selection @ReadWrite(bits: 16..<18, as: I2C1SELValues.self) - var i2c1sel: I2C1SEL + public var i2c1sel: I2C1SEL /// I2C2 clock source selection @ReadWrite(bits: 18..<20) - var i2c2sel: I2C2SEL + public var i2c2sel: I2C2SEL /// I2C3 clock source selection @ReadWrite(bits: 20..<22) - var i2c3sel: I2C3SEL + public var i2c3sel: I2C3SEL /// I2C4 clock source selection @ReadWrite(bits: 22..<24) - var i2c4sel: I2C4SEL + public var i2c4sel: I2C4SEL /// Low power timer 1 clock source selection @ReadWrite(bits: 24..<26, as: LPTIM1SELValues.self) - var lptim1sel: LPTIM1SEL + public var lptim1sel: LPTIM1SEL /// HDMI-CEC clock source selection @ReadWrite(bits: 26..<27, as: CECSELValues.self) - var cecsel: CECSEL + public var cecsel: CECSEL /// 48MHz clock source selection @ReadWrite(bits: 27..<28, as: CK48MSELValues.self) - var ck48msel: CK48MSEL + public var ck48msel: CK48MSEL /// SDMMC clock source selection @ReadWrite(bits: 28..<29, as: SDMMC1SELValues.self) - var sdmmc1sel: SDMMC1SEL + public var sdmmc1sel: SDMMC1SEL } } extension RCC.CR { - struct CSSONValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CSSONValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Clock security system disabled (clock detector OFF) - static let Off = Self(rawValue: 0x0) + public static let Off = Self(rawValue: 0x0) /// Clock security system enable (clock detector ON if the HSE is ready, OFF if not) - static let On = Self(rawValue: 0x1) + public static let On = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CR { - struct HSEBYPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct HSEBYPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// HSE crystal oscillator not bypassed - static let NotBypassed = Self(rawValue: 0x0) + public static let NotBypassed = Self(rawValue: 0x0) /// HSE crystal oscillator bypassed with external clock - static let Bypassed = Self(rawValue: 0x1) + public static let Bypassed = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CR { - struct HSIONValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct HSIONValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Clock Off - static let Off = Self(rawValue: 0x0) + public static let Off = Self(rawValue: 0x0) /// Clock On - static let On = Self(rawValue: 0x1) + public static let On = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.PLLCFGR { - struct PLLSRCValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct PLLSRCValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// HSI clock selected as PLL and PLLI2S clock entry - static let HSI = Self(rawValue: 0x0) + public static let HSI = Self(rawValue: 0x0) /// HSE oscillator clock selected as PLL and PLLI2S clock entry - static let HSE = Self(rawValue: 0x1) + public static let HSE = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.PLLCFGR { - struct PLLPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct PLLPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// PLLP=2 - static let Div2 = Self(rawValue: 0x0) + public static let Div2 = Self(rawValue: 0x0) /// PLLP=4 - static let Div4 = Self(rawValue: 0x1) + public static let Div4 = Self(rawValue: 0x1) /// PLLP=6 - static let Div6 = Self(rawValue: 0x2) + public static let Div6 = Self(rawValue: 0x2) /// PLLP=8 - static let Div8 = Self(rawValue: 0x3) + public static let Div8 = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CFGR { - struct MCO2Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct MCO2Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// System clock (SYSCLK) selected - static let SYSCLK = Self(rawValue: 0x0) + public static let SYSCLK = Self(rawValue: 0x0) /// PLLI2S clock selected - static let PLLI2S = Self(rawValue: 0x1) + public static let PLLI2S = Self(rawValue: 0x1) /// HSE oscillator clock selected - static let HSE = Self(rawValue: 0x2) + public static let HSE = Self(rawValue: 0x2) /// PLL clock selected - static let PLL = Self(rawValue: 0x3) + public static let PLL = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CFGR { - struct MCO1PREValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 3 + public struct MCO1PREValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 3 /// No division - static let Div1 = Self(rawValue: 0x0) + public static let Div1 = Self(rawValue: 0x0) /// Division by 2 - static let Div2 = Self(rawValue: 0x4) + public static let Div2 = Self(rawValue: 0x4) /// Division by 3 - static let Div3 = Self(rawValue: 0x5) + public static let Div3 = Self(rawValue: 0x5) /// Division by 4 - static let Div4 = Self(rawValue: 0x6) + public static let Div4 = Self(rawValue: 0x6) /// Division by 5 - static let Div5 = Self(rawValue: 0x7) + public static let Div5 = Self(rawValue: 0x7) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CFGR { - struct I2SSRCValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct I2SSRCValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// PLLI2S clock used as I2S clock source - static let PLLI2S = Self(rawValue: 0x0) + public static let PLLI2S = Self(rawValue: 0x0) /// External clock mapped on the I2S_CKIN pin used as I2S clock source - static let CKIN = Self(rawValue: 0x1) + public static let CKIN = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CFGR { - struct MCO1Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct MCO1Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// HSI clock selected - static let HSI = Self(rawValue: 0x0) + public static let HSI = Self(rawValue: 0x0) /// LSE oscillator selected - static let LSE = Self(rawValue: 0x1) + public static let LSE = Self(rawValue: 0x1) /// HSE oscillator clock selected - static let HSE = Self(rawValue: 0x2) + public static let HSE = Self(rawValue: 0x2) /// PLL clock selected - static let PLL = Self(rawValue: 0x3) + public static let PLL = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CFGR { - struct PPRE1Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 3 + public struct PPRE1Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 3 /// HCLK not divided - static let Div1 = Self(rawValue: 0x0) + public static let Div1 = Self(rawValue: 0x0) /// HCLK divided by 2 - static let Div2 = Self(rawValue: 0x4) + public static let Div2 = Self(rawValue: 0x4) /// HCLK divided by 4 - static let Div4 = Self(rawValue: 0x5) + public static let Div4 = Self(rawValue: 0x5) /// HCLK divided by 8 - static let Div8 = Self(rawValue: 0x6) + public static let Div8 = Self(rawValue: 0x6) /// HCLK divided by 16 - static let Div16 = Self(rawValue: 0x7) + public static let Div16 = Self(rawValue: 0x7) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CFGR { - struct HPREValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 4 + public struct HPREValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 4 /// SYSCLK not divided - static let Div1 = Self(rawValue: 0x0) + public static let Div1 = Self(rawValue: 0x0) /// SYSCLK divided by 2 - static let Div2 = Self(rawValue: 0x8) + public static let Div2 = Self(rawValue: 0x8) /// SYSCLK divided by 4 - static let Div4 = Self(rawValue: 0x9) + public static let Div4 = Self(rawValue: 0x9) /// SYSCLK divided by 8 - static let Div8 = Self(rawValue: 0xa) + public static let Div8 = Self(rawValue: 0xa) /// SYSCLK divided by 16 - static let Div16 = Self(rawValue: 0xb) + public static let Div16 = Self(rawValue: 0xb) /// SYSCLK divided by 64 - static let Div64 = Self(rawValue: 0xc) + public static let Div64 = Self(rawValue: 0xc) /// SYSCLK divided by 128 - static let Div128 = Self(rawValue: 0xd) + public static let Div128 = Self(rawValue: 0xd) /// SYSCLK divided by 256 - static let Div256 = Self(rawValue: 0xe) + public static let Div256 = Self(rawValue: 0xe) /// SYSCLK divided by 512 - static let Div512 = Self(rawValue: 0xf) + public static let Div512 = Self(rawValue: 0xf) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CFGR { - struct SWValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct SWValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// HSI selected as system clock - static let HSI = Self(rawValue: 0x0) + public static let HSI = Self(rawValue: 0x0) /// HSE selected as system clock - static let HSE = Self(rawValue: 0x1) + public static let HSE = Self(rawValue: 0x1) /// PLL selected as system clock - static let PLL = Self(rawValue: 0x2) + public static let PLL = Self(rawValue: 0x2) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CIR { - struct LSIRDYIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LSIRDYIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Interrupt enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB1RSTR { - struct GPIOARSTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct GPIOARSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Reset the selected module - static let Reset = Self(rawValue: 0x1) + public static let Reset = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB2RSTR { - struct DCMIRSTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DCMIRSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Reset the selected module - static let Reset = Self(rawValue: 0x1) + public static let Reset = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB3RSTR { - struct FMCRSTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct FMCRSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Reset the selected module - static let Reset = Self(rawValue: 0x1) + public static let Reset = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.APB1RSTR { - struct TIM2RSTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TIM2RSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Reset the selected module - static let Reset = Self(rawValue: 0x1) + public static let Reset = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.APB2RSTR { - struct TIM1RSTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TIM1RSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Reset the selected module - static let Reset = Self(rawValue: 0x1) + public static let Reset = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB1ENR { - struct GPIOAENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct GPIOAENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// The selected clock is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// The selected clock is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB2ENR { - struct DCMIENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DCMIENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// The selected clock is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// The selected clock is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB3ENR { - struct FMCENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct FMCENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// The selected clock is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// The selected clock is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.APB1ENR { - struct TIM2ENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TIM2ENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// The selected clock is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// The selected clock is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.APB2ENR { - struct TIM1ENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TIM1ENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// The selected clock is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// The selected clock is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB1LPENR { - struct GPIOALPENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct GPIOALPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Selected module is disabled during Sleep mode - static let DisabledInSleep = Self(rawValue: 0x0) + public static let DisabledInSleep = Self(rawValue: 0x0) /// Selected module is enabled during Sleep mode - static let EnabledInSleep = Self(rawValue: 0x1) + public static let EnabledInSleep = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB2LPENR { - struct DCMILPENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DCMILPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Selected module is disabled during Sleep mode - static let DisabledInSleep = Self(rawValue: 0x0) + public static let DisabledInSleep = Self(rawValue: 0x0) /// Selected module is enabled during Sleep mode - static let EnabledInSleep = Self(rawValue: 0x1) + public static let EnabledInSleep = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.AHB3LPENR { - struct FMCLPENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct FMCLPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Selected module is disabled during Sleep mode - static let DisabledInSleep = Self(rawValue: 0x0) + public static let DisabledInSleep = Self(rawValue: 0x0) /// Selected module is enabled during Sleep mode - static let EnabledInSleep = Self(rawValue: 0x1) + public static let EnabledInSleep = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.APB1LPENR { - struct TIM2LPENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TIM2LPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Selected module is disabled during Sleep mode - static let DisabledInSleep = Self(rawValue: 0x0) + public static let DisabledInSleep = Self(rawValue: 0x0) /// Selected module is enabled during Sleep mode - static let EnabledInSleep = Self(rawValue: 0x1) + public static let EnabledInSleep = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.APB2LPENR { - struct TIM1LPENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TIM1LPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Selected module is disabled during Sleep mode - static let DisabledInSleep = Self(rawValue: 0x0) + public static let DisabledInSleep = Self(rawValue: 0x0) /// Selected module is enabled during Sleep mode - static let EnabledInSleep = Self(rawValue: 0x1) + public static let EnabledInSleep = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.BDCR { - struct BDRSTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct BDRSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Reset not activated - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Reset the entire RTC domain - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.BDCR { - struct RTCENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct RTCENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// RTC clock disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// RTC clock enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.BDCR { - struct LSEBYPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LSEBYPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// LSE crystal oscillator not bypassed - static let NotBypassed = Self(rawValue: 0x0) + public static let NotBypassed = Self(rawValue: 0x0) /// LSE crystal oscillator bypassed with external clock - static let Bypassed = Self(rawValue: 0x1) + public static let Bypassed = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.BDCR { - struct LSEONValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LSEONValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// LSE oscillator Off - static let Off = Self(rawValue: 0x0) + public static let Off = Self(rawValue: 0x0) /// LSE oscillator On - static let On = Self(rawValue: 0x1) + public static let On = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.BDCR { - struct LSEDRVValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct LSEDRVValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// Low drive capacity - static let Low = Self(rawValue: 0x0) + public static let Low = Self(rawValue: 0x0) /// Medium-high drive capacity - static let MediumHigh = Self(rawValue: 0x1) + public static let MediumHigh = Self(rawValue: 0x1) /// Medium-low drive capacity - static let MediumLow = Self(rawValue: 0x2) + public static let MediumLow = Self(rawValue: 0x2) /// High drive capacity - static let High = Self(rawValue: 0x3) + public static let High = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.BDCR { - struct RTCSELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct RTCSELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// No clock - static let NoClock = Self(rawValue: 0x0) + public static let NoClock = Self(rawValue: 0x0) /// LSE oscillator clock used as RTC clock - static let LSE = Self(rawValue: 0x1) + public static let LSE = Self(rawValue: 0x1) /// LSI oscillator clock used as RTC clock - static let LSI = Self(rawValue: 0x2) + public static let LSI = Self(rawValue: 0x2) /// HSE oscillator clock divided by a prescaler used as RTC clock - static let HSE = Self(rawValue: 0x3) + public static let HSE = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.CSR { - struct LSIONValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LSIONValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// LSI oscillator Off - static let Off = Self(rawValue: 0x0) + public static let Off = Self(rawValue: 0x0) /// LSI oscillator On - static let On = Self(rawValue: 0x1) + public static let On = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.SSCGR { - struct SSCGENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct SSCGENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Spread spectrum modulation disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Spread spectrum modulation enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.SSCGR { - struct SPREADSELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct SPREADSELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Center spread - static let Center = Self(rawValue: 0x0) + public static let Center = Self(rawValue: 0x0) /// Down spread - static let Down = Self(rawValue: 0x1) + public static let Down = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.PLLI2SCFGR { - struct PLLI2SPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct PLLI2SPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// PLL*P=2 - static let Div2 = Self(rawValue: 0x0) + public static let Div2 = Self(rawValue: 0x0) /// PLL*P=4 - static let Div4 = Self(rawValue: 0x1) + public static let Div4 = Self(rawValue: 0x1) /// PLL*P=6 - static let Div6 = Self(rawValue: 0x2) + public static let Div6 = Self(rawValue: 0x2) /// PLL*P=8 - static let Div8 = Self(rawValue: 0x3) + public static let Div8 = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.PLLSAICFGR { - struct PLLSAIPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct PLLSAIPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// PLL*P=2 - static let Div2 = Self(rawValue: 0x0) + public static let Div2 = Self(rawValue: 0x0) /// PLL*P=4 - static let Div4 = Self(rawValue: 0x1) + public static let Div4 = Self(rawValue: 0x1) /// PLL*P=6 - static let Div6 = Self(rawValue: 0x2) + public static let Div6 = Self(rawValue: 0x2) /// PLL*P=8 - static let Div8 = Self(rawValue: 0x3) + public static let Div8 = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR1 { - struct PLLI2SDIVQValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 5 + public struct PLLI2SDIVQValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 5 /// PLLI2SDIVQ = /1 - static let Div1 = Self(rawValue: 0x0) + public static let Div1 = Self(rawValue: 0x0) /// PLLI2SDIVQ = /2 - static let Div2 = Self(rawValue: 0x1) + public static let Div2 = Self(rawValue: 0x1) /// PLLI2SDIVQ = /3 - static let Div3 = Self(rawValue: 0x2) + public static let Div3 = Self(rawValue: 0x2) /// PLLI2SDIVQ = /4 - static let Div4 = Self(rawValue: 0x3) + public static let Div4 = Self(rawValue: 0x3) /// PLLI2SDIVQ = /5 - static let Div5 = Self(rawValue: 0x4) + public static let Div5 = Self(rawValue: 0x4) /// PLLI2SDIVQ = /6 - static let Div6 = Self(rawValue: 0x5) + public static let Div6 = Self(rawValue: 0x5) /// PLLI2SDIVQ = /7 - static let Div7 = Self(rawValue: 0x6) + public static let Div7 = Self(rawValue: 0x6) /// PLLI2SDIVQ = /8 - static let Div8 = Self(rawValue: 0x7) + public static let Div8 = Self(rawValue: 0x7) /// PLLI2SDIVQ = /9 - static let Div9 = Self(rawValue: 0x8) + public static let Div9 = Self(rawValue: 0x8) /// PLLI2SDIVQ = /10 - static let Div10 = Self(rawValue: 0x9) + public static let Div10 = Self(rawValue: 0x9) /// PLLI2SDIVQ = /11 - static let Div11 = Self(rawValue: 0xa) + public static let Div11 = Self(rawValue: 0xa) /// PLLI2SDIVQ = /12 - static let Div12 = Self(rawValue: 0xb) + public static let Div12 = Self(rawValue: 0xb) /// PLLI2SDIVQ = /13 - static let Div13 = Self(rawValue: 0xc) + public static let Div13 = Self(rawValue: 0xc) /// PLLI2SDIVQ = /14 - static let Div14 = Self(rawValue: 0xd) + public static let Div14 = Self(rawValue: 0xd) /// PLLI2SDIVQ = /15 - static let Div15 = Self(rawValue: 0xe) + public static let Div15 = Self(rawValue: 0xe) /// PLLI2SDIVQ = /16 - static let Div16 = Self(rawValue: 0xf) + public static let Div16 = Self(rawValue: 0xf) /// PLLI2SDIVQ = /17 - static let Div17 = Self(rawValue: 0x10) + public static let Div17 = Self(rawValue: 0x10) /// PLLI2SDIVQ = /18 - static let Div18 = Self(rawValue: 0x11) + public static let Div18 = Self(rawValue: 0x11) /// PLLI2SDIVQ = /19 - static let Div19 = Self(rawValue: 0x12) + public static let Div19 = Self(rawValue: 0x12) /// PLLI2SDIVQ = /20 - static let Div20 = Self(rawValue: 0x13) + public static let Div20 = Self(rawValue: 0x13) /// PLLI2SDIVQ = /21 - static let Div21 = Self(rawValue: 0x14) + public static let Div21 = Self(rawValue: 0x14) /// PLLI2SDIVQ = /22 - static let Div22 = Self(rawValue: 0x15) + public static let Div22 = Self(rawValue: 0x15) /// PLLI2SDIVQ = /23 - static let Div23 = Self(rawValue: 0x16) + public static let Div23 = Self(rawValue: 0x16) /// PLLI2SDIVQ = /24 - static let Div24 = Self(rawValue: 0x17) + public static let Div24 = Self(rawValue: 0x17) /// PLLI2SDIVQ = /25 - static let Div25 = Self(rawValue: 0x18) + public static let Div25 = Self(rawValue: 0x18) /// PLLI2SDIVQ = /26 - static let Div26 = Self(rawValue: 0x19) + public static let Div26 = Self(rawValue: 0x19) /// PLLI2SDIVQ = /27 - static let Div27 = Self(rawValue: 0x1a) + public static let Div27 = Self(rawValue: 0x1a) /// PLLI2SDIVQ = /28 - static let Div28 = Self(rawValue: 0x1b) + public static let Div28 = Self(rawValue: 0x1b) /// PLLI2SDIVQ = /29 - static let Div29 = Self(rawValue: 0x1c) + public static let Div29 = Self(rawValue: 0x1c) /// PLLI2SDIVQ = /30 - static let Div30 = Self(rawValue: 0x1d) + public static let Div30 = Self(rawValue: 0x1d) /// PLLI2SDIVQ = /31 - static let Div31 = Self(rawValue: 0x1e) + public static let Div31 = Self(rawValue: 0x1e) /// PLLI2SDIVQ = /32 - static let Div32 = Self(rawValue: 0x1f) + public static let Div32 = Self(rawValue: 0x1f) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR1 { - struct PLLSAIDIVQValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 5 + public struct PLLSAIDIVQValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 5 /// PLLSAIDIVQ = /1 - static let Div1 = Self(rawValue: 0x0) + public static let Div1 = Self(rawValue: 0x0) /// PLLSAIDIVQ = /2 - static let Div2 = Self(rawValue: 0x1) + public static let Div2 = Self(rawValue: 0x1) /// PLLSAIDIVQ = /3 - static let Div3 = Self(rawValue: 0x2) + public static let Div3 = Self(rawValue: 0x2) /// PLLSAIDIVQ = /4 - static let Div4 = Self(rawValue: 0x3) + public static let Div4 = Self(rawValue: 0x3) /// PLLSAIDIVQ = /5 - static let Div5 = Self(rawValue: 0x4) + public static let Div5 = Self(rawValue: 0x4) /// PLLSAIDIVQ = /6 - static let Div6 = Self(rawValue: 0x5) + public static let Div6 = Self(rawValue: 0x5) /// PLLSAIDIVQ = /7 - static let Div7 = Self(rawValue: 0x6) + public static let Div7 = Self(rawValue: 0x6) /// PLLSAIDIVQ = /8 - static let Div8 = Self(rawValue: 0x7) + public static let Div8 = Self(rawValue: 0x7) /// PLLSAIDIVQ = /9 - static let Div9 = Self(rawValue: 0x8) + public static let Div9 = Self(rawValue: 0x8) /// PLLSAIDIVQ = /10 - static let Div10 = Self(rawValue: 0x9) + public static let Div10 = Self(rawValue: 0x9) /// PLLSAIDIVQ = /11 - static let Div11 = Self(rawValue: 0xa) + public static let Div11 = Self(rawValue: 0xa) /// PLLSAIDIVQ = /12 - static let Div12 = Self(rawValue: 0xb) + public static let Div12 = Self(rawValue: 0xb) /// PLLSAIDIVQ = /13 - static let Div13 = Self(rawValue: 0xc) + public static let Div13 = Self(rawValue: 0xc) /// PLLSAIDIVQ = /14 - static let Div14 = Self(rawValue: 0xd) + public static let Div14 = Self(rawValue: 0xd) /// PLLSAIDIVQ = /15 - static let Div15 = Self(rawValue: 0xe) + public static let Div15 = Self(rawValue: 0xe) /// PLLSAIDIVQ = /16 - static let Div16 = Self(rawValue: 0xf) + public static let Div16 = Self(rawValue: 0xf) /// PLLSAIDIVQ = /17 - static let Div17 = Self(rawValue: 0x10) + public static let Div17 = Self(rawValue: 0x10) /// PLLSAIDIVQ = /18 - static let Div18 = Self(rawValue: 0x11) + public static let Div18 = Self(rawValue: 0x11) /// PLLSAIDIVQ = /19 - static let Div19 = Self(rawValue: 0x12) + public static let Div19 = Self(rawValue: 0x12) /// PLLSAIDIVQ = /20 - static let Div20 = Self(rawValue: 0x13) + public static let Div20 = Self(rawValue: 0x13) /// PLLSAIDIVQ = /21 - static let Div21 = Self(rawValue: 0x14) + public static let Div21 = Self(rawValue: 0x14) /// PLLSAIDIVQ = /22 - static let Div22 = Self(rawValue: 0x15) + public static let Div22 = Self(rawValue: 0x15) /// PLLSAIDIVQ = /23 - static let Div23 = Self(rawValue: 0x16) + public static let Div23 = Self(rawValue: 0x16) /// PLLSAIDIVQ = /24 - static let Div24 = Self(rawValue: 0x17) + public static let Div24 = Self(rawValue: 0x17) /// PLLSAIDIVQ = /25 - static let Div25 = Self(rawValue: 0x18) + public static let Div25 = Self(rawValue: 0x18) /// PLLSAIDIVQ = /26 - static let Div26 = Self(rawValue: 0x19) + public static let Div26 = Self(rawValue: 0x19) /// PLLSAIDIVQ = /27 - static let Div27 = Self(rawValue: 0x1a) + public static let Div27 = Self(rawValue: 0x1a) /// PLLSAIDIVQ = /28 - static let Div28 = Self(rawValue: 0x1b) + public static let Div28 = Self(rawValue: 0x1b) /// PLLSAIDIVQ = /29 - static let Div29 = Self(rawValue: 0x1c) + public static let Div29 = Self(rawValue: 0x1c) /// PLLSAIDIVQ = /30 - static let Div30 = Self(rawValue: 0x1d) + public static let Div30 = Self(rawValue: 0x1d) /// PLLSAIDIVQ = /31 - static let Div31 = Self(rawValue: 0x1e) + public static let Div31 = Self(rawValue: 0x1e) /// PLLSAIDIVQ = /32 - static let Div32 = Self(rawValue: 0x1f) + public static let Div32 = Self(rawValue: 0x1f) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR1 { - struct PLLSAIDIVRValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct PLLSAIDIVRValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// PLLSAIDIVR = /2 - static let Div2 = Self(rawValue: 0x0) + public static let Div2 = Self(rawValue: 0x0) /// PLLSAIDIVR = /4 - static let Div4 = Self(rawValue: 0x1) + public static let Div4 = Self(rawValue: 0x1) /// PLLSAIDIVR = /8 - static let Div8 = Self(rawValue: 0x2) + public static let Div8 = Self(rawValue: 0x2) /// PLLSAIDIVR = /16 - static let Div16 = Self(rawValue: 0x3) + public static let Div16 = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR1 { - struct SAI1SELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct SAI1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - static let PLLSAI = Self(rawValue: 0x0) + public static let PLLSAI = Self(rawValue: 0x0) /// SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - static let PLLI2S = Self(rawValue: 0x1) + public static let PLLI2S = Self(rawValue: 0x1) /// SAI1 clock frequency = Alternate function input frequency - static let AFIF = Self(rawValue: 0x2) + public static let AFIF = Self(rawValue: 0x2) /// SAI1 clock frequency = HSI or HSE - static let HSI_HSE = Self(rawValue: 0x3) + public static let HSI_HSE = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR1 { - struct SAI2SELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct SAI2SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - static let PLLSAI = Self(rawValue: 0x0) + public static let PLLSAI = Self(rawValue: 0x0) /// SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - static let PLLI2S = Self(rawValue: 0x1) + public static let PLLI2S = Self(rawValue: 0x1) /// SAI2 clock frequency = Alternate function input frequency - static let AFIF = Self(rawValue: 0x2) + public static let AFIF = Self(rawValue: 0x2) /// SAI2 clock frequency = HSI or HSE - static let HSI_HSE = Self(rawValue: 0x3) + public static let HSI_HSE = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR1 { - struct TIMPREValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TIMPREValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx - static let Mul1Or2 = Self(rawValue: 0x0) + public static let Mul1Or2 = Self(rawValue: 0x0) /// If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx - static let Mul1Or4 = Self(rawValue: 0x1) + public static let Mul1Or4 = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR2 { - struct USART1SELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct USART1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// APB2 clock (PCLK2) is selected as USART clock - static let APB2 = Self(rawValue: 0x0) + public static let APB2 = Self(rawValue: 0x0) /// System clock is selected as USART clock - static let SYSCLK = Self(rawValue: 0x1) + public static let SYSCLK = Self(rawValue: 0x1) /// HSI clock is selected as USART clock - static let HSI = Self(rawValue: 0x2) + public static let HSI = Self(rawValue: 0x2) /// LSE clock is selected as USART clock - static let LSE = Self(rawValue: 0x3) + public static let LSE = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR2 { - struct USART2SELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct USART2SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// APB1 clock (PCLK1) is selected as USART clock - static let APB1 = Self(rawValue: 0x0) + public static let APB1 = Self(rawValue: 0x0) /// System clock is selected as USART clock - static let SYSCLK = Self(rawValue: 0x1) + public static let SYSCLK = Self(rawValue: 0x1) /// HSI clock is selected as USART clock - static let HSI = Self(rawValue: 0x2) + public static let HSI = Self(rawValue: 0x2) /// LSE clock is selected as USART clock - static let LSE = Self(rawValue: 0x3) + public static let LSE = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR2 { - struct I2C1SELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct I2C1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// APB clock selected as I2C clock - static let APB = Self(rawValue: 0x0) + public static let APB = Self(rawValue: 0x0) /// System clock selected as I2C clock - static let SYSCLK = Self(rawValue: 0x1) + public static let SYSCLK = Self(rawValue: 0x1) /// HSI clock selected as I2C clock - static let HSI = Self(rawValue: 0x2) + public static let HSI = Self(rawValue: 0x2) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR2 { - struct LPTIM1SELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct LPTIM1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// APB1 clock (PCLK1) selected as LPTILM1 clock - static let APB1 = Self(rawValue: 0x0) + public static let APB1 = Self(rawValue: 0x0) /// LSI clock is selected as LPTILM1 clock - static let LSI = Self(rawValue: 0x1) + public static let LSI = Self(rawValue: 0x1) /// HSI clock is selected as LPTILM1 clock - static let HSI = Self(rawValue: 0x2) + public static let HSI = Self(rawValue: 0x2) /// LSE clock is selected as LPTILM1 clock - static let LSE = Self(rawValue: 0x3) + public static let LSE = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR2 { - struct CECSELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CECSELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// LSE clock is selected as HDMI-CEC clock - static let LSE = Self(rawValue: 0x0) + public static let LSE = Self(rawValue: 0x0) /// HSI divided by 488 clock is selected as HDMI-CEC clock - static let HSI_Div488 = Self(rawValue: 0x1) + public static let HSI_Div488 = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR2 { - struct CK48MSELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CK48MSELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// 48MHz clock from PLL is selected - static let PLL = Self(rawValue: 0x0) + public static let PLL = Self(rawValue: 0x0) /// 48MHz clock from PLLSAI is selected - static let PLLSAI = Self(rawValue: 0x1) + public static let PLLSAI = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension RCC.DCKCFGR2 { - struct SDMMC1SELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct SDMMC1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// 48 MHz clock is selected as SD clock - static let CK48M = Self(rawValue: 0x0) + public static let CK48M = Self(rawValue: 0x0) /// System clock is selected as SD clock - static let SYSCLK = Self(rawValue: 0x1) + public static let SYSCLK = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } diff --git a/stm32-neopixel/Sources/Application/Registers/USART1.swift b/stm32-uart-echo/Sources/STM32F7X6/USART1.swift similarity index 50% rename from stm32-neopixel/Sources/Application/Registers/USART1.swift rename to stm32-uart-echo/Sources/STM32F7X6/USART1.swift index 6230310f..508d05a1 100644 --- a/stm32-neopixel/Sources/Application/Registers/USART1.swift +++ b/stm32-uart-echo/Sources/STM32F7X6/USART1.swift @@ -4,1550 +4,1550 @@ import MMIO /// Universal synchronous asynchronous receiver transmitter @RegisterBlock -struct USART1 { +public struct USART1 { /// Control register 1 @RegisterBlock(offset: 0x0) - var cr1: Register + public var cr1: Register /// Control register 2 @RegisterBlock(offset: 0x4) - var cr2: Register + public var cr2: Register /// Control register 3 @RegisterBlock(offset: 0x8) - var cr3: Register + public var cr3: Register /// Baud rate register @RegisterBlock(offset: 0xc) - var brr: Register + public var brr: Register /// Guard time and prescaler register @RegisterBlock(offset: 0x10) - var gtpr: Register + public var gtpr: Register /// Receiver timeout register @RegisterBlock(offset: 0x14) - var rtor: Register + public var rtor: Register /// Request register @RegisterBlock(offset: 0x18) - var rqr: Register + public var rqr: Register /// Interrupt & status register @RegisterBlock(offset: 0x1c) - var isr: Register + public var isr: Register /// Interrupt flag clear register @RegisterBlock(offset: 0x20) - var icr: Register + public var icr: Register /// Receive data register @RegisterBlock(offset: 0x24) - var rdr: Register + public var rdr: Register /// Transmit data register @RegisterBlock(offset: 0x28) - var tdr: Register + public var tdr: Register } extension USART1 { /// Control register 1 @Register(bitWidth: 32) - struct CR1 { + public struct CR1 { /// Word length @ReadWrite(bits: 28..<29, as: M1Values.self) - var m1: M1 + public var m1: M1 /// End of Block interrupt enable @ReadWrite(bits: 27..<28, as: EOBIEValues.self) - var eobie: EOBIE + public var eobie: EOBIE /// Receiver timeout interrupt enable @ReadWrite(bits: 26..<27, as: RTOIEValues.self) - var rtoie: RTOIE + public var rtoie: RTOIE /// Oversampling mode @ReadWrite(bits: 15..<16, as: OVER8Values.self) - var over8: OVER8 + public var over8: OVER8 /// Character match interrupt enable @ReadWrite(bits: 14..<15, as: CMIEValues.self) - var cmie: CMIE + public var cmie: CMIE /// Mute mode enable @ReadWrite(bits: 13..<14, as: MMEValues.self) - var mme: MME + public var mme: MME /// Word length @ReadWrite(bits: 12..<13, as: M0Values.self) - var m0: M0 + public var m0: M0 /// Receiver wakeup method @ReadWrite(bits: 11..<12, as: WAKEValues.self) - var wake: WAKE + public var wake: WAKE /// Parity control enable @ReadWrite(bits: 10..<11, as: PCEValues.self) - var pce: PCE + public var pce: PCE /// Parity selection @ReadWrite(bits: 9..<10, as: PSValues.self) - var ps: PS + public var ps: PS /// PE interrupt enable @ReadWrite(bits: 8..<9, as: PEIEValues.self) - var peie: PEIE + public var peie: PEIE /// interrupt enable @ReadWrite(bits: 7..<8, as: TXEIEValues.self) - var txeie: TXEIE + public var txeie: TXEIE /// Transmission complete interrupt enable @ReadWrite(bits: 6..<7, as: TCIEValues.self) - var tcie: TCIE + public var tcie: TCIE /// RXNE interrupt enable @ReadWrite(bits: 5..<6, as: RXNEIEValues.self) - var rxneie: RXNEIE + public var rxneie: RXNEIE /// IDLE interrupt enable @ReadWrite(bits: 4..<5, as: IDLEIEValues.self) - var idleie: IDLEIE + public var idleie: IDLEIE /// Transmitter enable @ReadWrite(bits: 3..<4, as: TEValues.self) - var te: TE + public var te: TE /// Receiver enable @ReadWrite(bits: 2..<3, as: REValues.self) - var re: RE + public var re: RE /// USART enable in Stop mode @ReadWrite(bits: 1..<2, as: UESMValues.self) - var uesm: UESM + public var uesm: UESM /// USART enable @ReadWrite(bits: 0..<1, as: UEValues.self) - var ue: UE + public var ue: UE /// Driver Enable assertion time @ReadWrite(bits: 21..<26) - var deat: DEAT + public var deat: DEAT /// Driver Enable de-assertion time @ReadWrite(bits: 16..<21) - var dedt: DEDT + public var dedt: DEDT } /// Control register 2 @Register(bitWidth: 32) - struct CR2 { + public struct CR2 { /// Receiver timeout enable @ReadWrite(bits: 23..<24, as: RTOENValues.self) - var rtoen: RTOEN + public var rtoen: RTOEN /// Auto baud rate enable @ReadWrite(bits: 20..<21, as: ABRENValues.self) - var abren: ABREN + public var abren: ABREN /// Most significant bit first @ReadWrite(bits: 19..<20, as: MSBFIRSTValues.self) - var msbfirst: MSBFIRST + public var msbfirst: MSBFIRST /// Binary data inversion @ReadWrite(bits: 18..<19, as: DATAINVValues.self) - var datainv: DATAINV + public var datainv: DATAINV /// TX pin active level inversion @ReadWrite(bits: 17..<18, as: TXINVValues.self) - var txinv: TXINV + public var txinv: TXINV /// RX pin active level inversion @ReadWrite(bits: 16..<17, as: RXINVValues.self) - var rxinv: RXINV + public var rxinv: RXINV /// Swap TX/RX pins @ReadWrite(bits: 15..<16, as: SWAPValues.self) - var swap: SWAP + public var swap: SWAP /// LIN mode enable @ReadWrite(bits: 14..<15, as: LINENValues.self) - var linen: LINEN + public var linen: LINEN /// STOP bits @ReadWrite(bits: 12..<14, as: STOPValues.self) - var stop: STOP + public var stop: STOP /// Clock enable @ReadWrite(bits: 11..<12, as: CLKENValues.self) - var clken: CLKEN + public var clken: CLKEN /// Clock polarity @ReadWrite(bits: 10..<11, as: CPOLValues.self) - var cpol: CPOL + public var cpol: CPOL /// Clock phase @ReadWrite(bits: 9..<10, as: CPHAValues.self) - var cpha: CPHA + public var cpha: CPHA /// Last bit clock pulse @ReadWrite(bits: 8..<9, as: LBCLValues.self) - var lbcl: LBCL + public var lbcl: LBCL /// LIN break detection interrupt enable @ReadWrite(bits: 6..<7, as: LBDIEValues.self) - var lbdie: LBDIE + public var lbdie: LBDIE /// LIN break detection length @ReadWrite(bits: 5..<6, as: LBDLValues.self) - var lbdl: LBDL + public var lbdl: LBDL /// 7-bit Address Detection/4-bit Address Detection @ReadWrite(bits: 4..<5, as: ADDM7Values.self) - var addm7: ADDM7 + public var addm7: ADDM7 /// Auto baud rate mode @ReadWrite(bits: 21..<23, as: ABRMODValues.self) - var abrmod: ABRMOD + public var abrmod: ABRMOD /// Address of the USART node @ReadWrite(bits: 24..<32) - var add: ADD + public var add: ADD } /// Control register 3 @Register(bitWidth: 32) - struct CR3 { + public struct CR3 { /// Wakeup from Stop mode interrupt enable @ReadWrite(bits: 22..<23, as: WUFIEValues.self) - var wufie: WUFIE + public var wufie: WUFIE /// Wakeup from Stop mode interrupt flag selection @ReadWrite(bits: 20..<22, as: WUSValues.self) - var wus: WUS + public var wus: WUS /// Smartcard auto-retry count @ReadWrite(bits: 17..<20) - var scarcnt: SCARCNT + public var scarcnt: SCARCNT /// Driver enable polarity selection @ReadWrite(bits: 15..<16, as: DEPValues.self) - var dep: DEP + public var dep: DEP /// Driver enable mode @ReadWrite(bits: 14..<15, as: DEMValues.self) - var dem: DEM + public var dem: DEM /// DMA Disable on Reception Error @ReadWrite(bits: 13..<14, as: DDREValues.self) - var ddre: DDRE + public var ddre: DDRE /// Overrun Disable @ReadWrite(bits: 12..<13, as: OVRDISValues.self) - var ovrdis: OVRDIS + public var ovrdis: OVRDIS /// One sample bit method enable @ReadWrite(bits: 11..<12, as: ONEBITValues.self) - var onebit: ONEBIT + public var onebit: ONEBIT /// CTS interrupt enable @ReadWrite(bits: 10..<11, as: CTSIEValues.self) - var ctsie: CTSIE + public var ctsie: CTSIE /// CTS enable @ReadWrite(bits: 9..<10, as: CTSEValues.self) - var ctse: CTSE + public var ctse: CTSE /// RTS enable @ReadWrite(bits: 8..<9, as: RTSEValues.self) - var rtse: RTSE + public var rtse: RTSE /// DMA enable transmitter @ReadWrite(bits: 7..<8, as: DMATValues.self) - var dmat: DMAT + public var dmat: DMAT /// DMA enable receiver @ReadWrite(bits: 6..<7, as: DMARValues.self) - var dmar: DMAR + public var dmar: DMAR /// Smartcard mode enable @ReadWrite(bits: 5..<6, as: SCENValues.self) - var scen: SCEN + public var scen: SCEN /// Smartcard NACK enable @ReadWrite(bits: 4..<5, as: NACKValues.self) - var nack: NACK + public var nack: NACK /// Half-duplex selection @ReadWrite(bits: 3..<4, as: HDSELValues.self) - var hdsel: HDSEL + public var hdsel: HDSEL /// Ir low-power @ReadWrite(bits: 2..<3, as: IRLPValues.self) - var irlp: IRLP + public var irlp: IRLP /// Ir mode enable @ReadWrite(bits: 1..<2, as: IRENValues.self) - var iren: IREN + public var iren: IREN /// Error interrupt enable @ReadWrite(bits: 0..<1, as: EIEValues.self) - var eie: EIE + public var eie: EIE } /// Baud rate register @Register(bitWidth: 32) - struct BRR { + public struct BRR { /// DIV_Mantissa @ReadWrite(bits: 0..<16) - var brr_field: BRR_FIELD + public var brr_field: BRR_FIELD } /// Guard time and prescaler register @Register(bitWidth: 32) - struct GTPR { + public struct GTPR { /// Guard time value @ReadWrite(bits: 8..<16) - var gt: GT + public var gt: GT /// Prescaler value @ReadWrite(bits: 0..<8) - var psc: PSC + public var psc: PSC } /// Receiver timeout register @Register(bitWidth: 32) - struct RTOR { + public struct RTOR { /// Block Length @ReadWrite(bits: 24..<32) - var blen: BLEN + public var blen: BLEN /// Receiver timeout value @ReadWrite(bits: 0..<24) - var rto: RTO + public var rto: RTO } /// Request register @Register(bitWidth: 32) - struct RQR { + public struct RQR { /// Transmit data flush request @WriteOnly(bits: 4..<5) - var txfrq: TXFRQ + public var txfrq: TXFRQ /// Receive data flush request @WriteOnly(bits: 3..<4) - var rxfrq: RXFRQ + public var rxfrq: RXFRQ /// Mute mode request @WriteOnly(bits: 2..<3) - var mmrq: MMRQ + public var mmrq: MMRQ /// Send break request @WriteOnly(bits: 1..<2) - var sbkrq: SBKRQ + public var sbkrq: SBKRQ /// Auto baud rate request @WriteOnly(bits: 0..<1) - var abrrq: ABRRQ + public var abrrq: ABRRQ } /// Interrupt & status register @Register(bitWidth: 32) - struct ISR { + public struct ISR { /// REACK @ReadOnly(bits: 22..<23) - var reack: REACK + public var reack: REACK /// TEACK @ReadOnly(bits: 21..<22) - var teack: TEACK + public var teack: TEACK /// WUF @ReadOnly(bits: 20..<21) - var wuf: WUF + public var wuf: WUF /// RWU @ReadOnly(bits: 19..<20) - var rwu: RWU + public var rwu: RWU /// SBKF @ReadOnly(bits: 18..<19) - var sbkf: SBKF + public var sbkf: SBKF /// CMF @ReadOnly(bits: 17..<18) - var cmf: CMF + public var cmf: CMF /// BUSY @ReadOnly(bits: 16..<17) - var busy: BUSY + public var busy: BUSY /// ABRF @ReadOnly(bits: 15..<16) - var abrf: ABRF + public var abrf: ABRF /// ABRE @ReadOnly(bits: 14..<15) - var abre: ABRE + public var abre: ABRE /// EOBF @ReadOnly(bits: 12..<13) - var eobf: EOBF + public var eobf: EOBF /// RTOF @ReadOnly(bits: 11..<12) - var rtof: RTOF + public var rtof: RTOF /// CTS @ReadOnly(bits: 10..<11) - var cts: CTS + public var cts: CTS /// CTSIF @ReadOnly(bits: 9..<10) - var ctsif: CTSIF + public var ctsif: CTSIF /// LBDF @ReadOnly(bits: 8..<9) - var lbdf: LBDF + public var lbdf: LBDF /// TXE @ReadOnly(bits: 7..<8) - var txe: TXE + public var txe: TXE /// TC @ReadOnly(bits: 6..<7) - var tc: TC + public var tc: TC /// RXNE @ReadOnly(bits: 5..<6) - var rxne: RXNE + public var rxne: RXNE /// IDLE @ReadOnly(bits: 4..<5) - var idle: IDLE + public var idle: IDLE /// ORE @ReadOnly(bits: 3..<4) - var ore: ORE + public var ore: ORE /// NF @ReadOnly(bits: 2..<3) - var nf: NF + public var nf: NF /// FE @ReadOnly(bits: 1..<2) - var fe: FE + public var fe: FE /// PE @ReadOnly(bits: 0..<1) - var pe: PE + public var pe: PE } /// Interrupt flag clear register @Register(bitWidth: 32) - struct ICR { + public struct ICR { /// Wakeup from Stop mode clear flag @WriteOnly(bits: 20..<21) - var wucf: WUCF + public var wucf: WUCF /// Character match clear flag @WriteOnly(bits: 17..<18) - var cmcf: CMCF + public var cmcf: CMCF /// End of block clear flag @WriteOnly(bits: 12..<13) - var eobcf: EOBCF + public var eobcf: EOBCF /// Receiver timeout clear flag @WriteOnly(bits: 11..<12) - var rtocf: RTOCF + public var rtocf: RTOCF /// CTS clear flag @WriteOnly(bits: 9..<10) - var ctscf: CTSCF + public var ctscf: CTSCF /// LIN break detection clear flag @WriteOnly(bits: 8..<9) - var lbdcf: LBDCF + public var lbdcf: LBDCF /// Transmission complete clear flag @WriteOnly(bits: 6..<7) - var tccf: TCCF + public var tccf: TCCF /// Idle line detected clear flag @WriteOnly(bits: 4..<5) - var idlecf: IDLECF + public var idlecf: IDLECF /// Overrun error clear flag @WriteOnly(bits: 3..<4) - var orecf: ORECF + public var orecf: ORECF /// Noise detected clear flag @WriteOnly(bits: 2..<3) - var ncf: NCF + public var ncf: NCF /// Framing error clear flag @WriteOnly(bits: 1..<2) - var fecf: FECF + public var fecf: FECF /// Parity error clear flag @WriteOnly(bits: 0..<1) - var pecf: PECF + public var pecf: PECF } /// Receive data register @Register(bitWidth: 32) - struct RDR { + public struct RDR { /// Receive data value @ReadOnly(bits: 0..<9) - var rdr_field: RDR_FIELD + public var rdr_field: RDR_FIELD } /// Transmit data register @Register(bitWidth: 32) - struct TDR { + public struct TDR { /// Transmit data value @ReadWrite(bits: 0..<9) - var tdr_field: TDR_FIELD + public var tdr_field: TDR_FIELD } } extension USART1.CR1 { - struct M1Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct M1Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Use M0 to set the data bits - static let M0 = Self(rawValue: 0x0) + public static let M0 = Self(rawValue: 0x0) /// 1 start bit, 7 data bits, n stop bits - static let Bit7 = Self(rawValue: 0x1) + public static let Bit7 = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct EOBIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct EOBIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is inhibited - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// A USART interrupt is generated when the EOBF flag is set in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct RTOIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct RTOIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is inhibited - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// An USART interrupt is generated when the RTOF bit is set in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct OVER8Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct OVER8Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Oversampling by 16 - static let Oversampling16 = Self(rawValue: 0x0) + public static let Oversampling16 = Self(rawValue: 0x0) /// Oversampling by 8 - static let Oversampling8 = Self(rawValue: 0x1) + public static let Oversampling8 = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct CMIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CMIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Interrupt is generated when the CMF bit is set in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct MMEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct MMEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Receiver in active mode permanently - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Receiver can switch between mute mode and active mode - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct M0Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct M0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// 1 start bit, 8 data bits, n stop bits - static let Bit8 = Self(rawValue: 0x0) + public static let Bit8 = Self(rawValue: 0x0) /// 1 start bit, 9 data bits, n stop bits - static let Bit9 = Self(rawValue: 0x1) + public static let Bit9 = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct WAKEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct WAKEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Idle line - static let Idle = Self(rawValue: 0x0) + public static let Idle = Self(rawValue: 0x0) /// Address mask - static let Address = Self(rawValue: 0x1) + public static let Address = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct PCEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct PCEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Parity control disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Parity control enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct PSValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct PSValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Even parity - static let Even = Self(rawValue: 0x0) + public static let Even = Self(rawValue: 0x0) /// Odd parity - static let Odd = Self(rawValue: 0x1) + public static let Odd = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct PEIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct PEIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Interrupt is generated whenever PE=1 in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct TXEIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TXEIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Interrupt is generated whenever TXE=1 in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct TCIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TCIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Interrupt is generated whenever TC=1 in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct RXNEIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct RXNEIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct IDLEIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct IDLEIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Interrupt is generated whenever IDLE=1 in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct TEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Transmitter is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Transmitter is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct REValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct REValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Receiver is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Receiver is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct UESMValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct UESMValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// USART not able to wake up the MCU from Stop mode - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// USART able to wake up the MCU from Stop mode - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR1 { - struct UEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct UEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// UART is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// UART is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct RTOENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct RTOENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Receiver timeout feature disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Receiver timeout feature enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct ABRENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct ABRENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Auto baud rate detection is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Auto baud rate detection is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct MSBFIRSTValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct MSBFIRSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// data is transmitted/received with data bit 0 first, following the start bit - static let LSB = Self(rawValue: 0x0) + public static let LSB = Self(rawValue: 0x0) /// data is transmitted/received with MSB (bit 7/8/9) first, following the start bit - static let MSB = Self(rawValue: 0x1) + public static let MSB = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct DATAINVValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DATAINVValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Logical data from the data register are send/received in positive/direct logic - static let Positive = Self(rawValue: 0x0) + public static let Positive = Self(rawValue: 0x0) /// Logical data from the data register are send/received in negative/inverse logic - static let Negative = Self(rawValue: 0x1) + public static let Negative = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct TXINVValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct TXINVValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// TX pin signal works using the standard logic levels - static let Standard = Self(rawValue: 0x0) + public static let Standard = Self(rawValue: 0x0) /// TX pin signal values are inverted - static let Inverted = Self(rawValue: 0x1) + public static let Inverted = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct RXINVValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct RXINVValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// RX pin signal works using the standard logic levels - static let Standard = Self(rawValue: 0x0) + public static let Standard = Self(rawValue: 0x0) /// RX pin signal values are inverted - static let Inverted = Self(rawValue: 0x1) + public static let Inverted = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct SWAPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct SWAPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// TX/RX pins are used as defined in standard pinout - static let Standard = Self(rawValue: 0x0) + public static let Standard = Self(rawValue: 0x0) /// The TX and RX pins functions are swapped - static let Swapped = Self(rawValue: 0x1) + public static let Swapped = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct LINENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LINENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// LIN mode disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// LIN mode enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct STOPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct STOPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// 1 stop bit - static let Stop1 = Self(rawValue: 0x0) + public static let Stop1 = Self(rawValue: 0x0) /// 0.5 stop bit - static let Stop0p5 = Self(rawValue: 0x1) + public static let Stop0p5 = Self(rawValue: 0x1) /// 2 stop bit - static let Stop2 = Self(rawValue: 0x2) + public static let Stop2 = Self(rawValue: 0x2) /// 1.5 stop bit - static let Stop1p5 = Self(rawValue: 0x3) + public static let Stop1p5 = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct CLKENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CLKENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// CK pin disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// CK pin enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct CPOLValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CPOLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Steady low value on CK pin outside transmission window - static let Low = Self(rawValue: 0x0) + public static let Low = Self(rawValue: 0x0) /// Steady high value on CK pin outside transmission window - static let High = Self(rawValue: 0x1) + public static let High = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct CPHAValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CPHAValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// The first clock transition is the first data capture edge - static let First = Self(rawValue: 0x0) + public static let First = Self(rawValue: 0x0) /// The second clock transition is the first data capture edge - static let Second = Self(rawValue: 0x1) + public static let Second = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct LBCLValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LBCLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// The clock pulse of the last data bit is not output to the CK pin - static let NotOutput = Self(rawValue: 0x0) + public static let NotOutput = Self(rawValue: 0x0) /// The clock pulse of the last data bit is output to the CK pin - static let Output = Self(rawValue: 0x1) + public static let Output = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct LBDIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LBDIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is inhibited - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// An interrupt is generated whenever LBDF=1 in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct LBDLValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct LBDLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// 10-bit break detection - static let Bit10 = Self(rawValue: 0x0) + public static let Bit10 = Self(rawValue: 0x0) /// 11-bit break detection - static let Bit11 = Self(rawValue: 0x1) + public static let Bit11 = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct ADDM7Values: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct ADDM7Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// 4-bit address detection - static let Bit4 = Self(rawValue: 0x0) + public static let Bit4 = Self(rawValue: 0x0) /// 7-bit address detection - static let Bit7 = Self(rawValue: 0x1) + public static let Bit7 = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR2 { - struct ABRMODValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct ABRMODValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// Measurement of the start bit is used to detect the baud rate - static let Start = Self(rawValue: 0x0) + public static let Start = Self(rawValue: 0x0) /// Falling edge to falling edge measurement - static let Edge = Self(rawValue: 0x1) + public static let Edge = Self(rawValue: 0x1) /// 0x7F frame detection - static let Frame7F = Self(rawValue: 0x2) + public static let Frame7F = Self(rawValue: 0x2) /// 0x55 frame detection - static let Frame55 = Self(rawValue: 0x3) + public static let Frame55 = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct WUFIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct WUFIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is inhibited - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// An USART interrupt is generated whenever WUF=1 in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct WUSValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 2 + public struct WUSValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 /// WUF active on address match - static let Address = Self(rawValue: 0x0) + public static let Address = Self(rawValue: 0x0) /// WuF active on Start bit detection - static let Start = Self(rawValue: 0x2) + public static let Start = Self(rawValue: 0x2) /// WUF active on RXNE - static let RXNE = Self(rawValue: 0x3) + public static let RXNE = Self(rawValue: 0x3) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct DEPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DEPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// DE signal is active high - static let High = Self(rawValue: 0x0) + public static let High = Self(rawValue: 0x0) /// DE signal is active low - static let Low = Self(rawValue: 0x1) + public static let Low = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct DEMValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DEMValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// DE function is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// The DE signal is output on the RTS pin - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct DDREValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DDREValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// DMA is not disabled in case of reception error - static let NotDisabled = Self(rawValue: 0x0) + public static let NotDisabled = Self(rawValue: 0x0) /// DMA is disabled following a reception error - static let Disabled = Self(rawValue: 0x1) + public static let Disabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct OVRDISValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct OVRDISValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Overrun Error Flag, ORE, is set when received data is not read before receiving new data - static let Enabled = Self(rawValue: 0x0) + public static let Enabled = Self(rawValue: 0x0) /// Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register - static let Disabled = Self(rawValue: 0x1) + public static let Disabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct ONEBITValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct ONEBITValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Three sample bit method - static let Sample3 = Self(rawValue: 0x0) + public static let Sample3 = Self(rawValue: 0x0) /// One sample bit method - static let Sample1 = Self(rawValue: 0x1) + public static let Sample1 = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct CTSIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CTSIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is inhibited - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// An interrupt is generated whenever CTSIF=1 in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct CTSEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct CTSEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// CTS hardware flow control disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// CTS mode enabled, data is only transmitted when the CTS input is asserted - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct RTSEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct RTSEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// RTS hardware flow control disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// RTS output enabled, data is only requested when there is space in the receive buffer - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct DMATValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DMATValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// DMA mode is disabled for transmission - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// DMA mode is enabled for transmission - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct DMARValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct DMARValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// DMA mode is disabled for reception - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// DMA mode is enabled for reception - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct SCENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct SCENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Smartcard Mode disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// Smartcard Mode enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct NACKValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct NACKValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// NACK transmission in case of parity error is disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// NACK transmission during parity error is enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct HDSELValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct HDSELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Half duplex mode is not selected - static let NotSelected = Self(rawValue: 0x0) + public static let NotSelected = Self(rawValue: 0x0) /// Half duplex mode is selected - static let Selected = Self(rawValue: 0x1) + public static let Selected = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct IRLPValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct IRLPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Normal mode - static let Normal = Self(rawValue: 0x0) + public static let Normal = Self(rawValue: 0x0) /// Low-power mode - static let LowPower = Self(rawValue: 0x1) + public static let LowPower = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct IRENValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct IRENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// IrDA disabled - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// IrDA enabled - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } } extension USART1.CR3 { - struct EIEValues: BitFieldProjectable, RawRepresentable { - static let bitWidth = 1 + public struct EIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 /// Interrupt is inhibited - static let Disabled = Self(rawValue: 0x0) + public static let Disabled = Self(rawValue: 0x0) /// An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register - static let Enabled = Self(rawValue: 0x1) + public static let Enabled = Self(rawValue: 0x1) - var rawValue: UInt8 + public var rawValue: UInt8 @inlinable @inline(__always) - init(rawValue: Self.RawValue) { + public init(rawValue: Self.RawValue) { self.rawValue = rawValue } } diff --git a/stm32-uart-echo/Sources/STM32F7X6/stm32f7x6.patched.svd b/stm32-uart-echo/Sources/STM32F7X6/stm32f7x6.patched.svd new file mode 120000 index 00000000..a6442b50 --- /dev/null +++ b/stm32-uart-echo/Sources/STM32F7X6/stm32f7x6.patched.svd @@ -0,0 +1 @@ +../../../Tools/SVDs/stm32f7x6.patched.svd \ No newline at end of file diff --git a/stm32-uart-echo/Sources/STM32F7X6/svd2swift.json b/stm32-uart-echo/Sources/STM32F7X6/svd2swift.json new file mode 100644 index 00000000..a7fe0570 --- /dev/null +++ b/stm32-uart-echo/Sources/STM32F7X6/svd2swift.json @@ -0,0 +1,9 @@ +{ + "peripherals": [ + "GPIOA", + "GPIOB", + "RCC", + "USART1" + ], + "access-level": "public" +}