diff --git a/.github/workflows/build-stm.yml b/.github/workflows/build-stm.yml index bd393eb..57afd2c 100644 --- a/.github/workflows/build-stm.yml +++ b/.github/workflows/build-stm.yml @@ -15,12 +15,16 @@ jobs: strategy: fail-fast: false matrix: - example: [stm32-blink] + example: [stm32-blink, stm32-lvgl] steps: - name: Checkout repo uses: actions/checkout@v4 + - name: Fixup for running locally in act + if: ${{ env.ACT }} + run: echo /opt/acttoolcache/node/18.20.8/x64/bin >> $GITHUB_PATH + - name: Set up Python uses: actions/setup-python@v5 with: @@ -32,8 +36,21 @@ jobs: - name: Install Swift uses: ./.github/actions/install-swift + - name: Set environment variables + run: | + echo "STM_BOARD=STM32F746G_DISCOVERY" >> $GITHUB_ENV + - name: Build ${{ matrix.example }} working-directory: ${{ matrix.example }} run: | - export STM_BOARD=STM32F746G_DISCOVERY - ./build-elf.sh + if [[ -f ./fetch-dependencies.sh ]]; then + ./fetch-dependencies.sh + fi + + if [[ -f ./build-elf.sh ]]; then + ./build-elf.sh + fi + + if [[ -f Makefile ]]; then + make + fi diff --git a/.swiftformatignore b/.swiftformatignore index 3dd7359..cec22c7 100644 --- a/.swiftformatignore +++ b/.swiftformatignore @@ -1,4 +1,6 @@ ./harmony/* +./stm32-lvgl/* ./stm32-lcd-logo/Sources/STM32F7X6/* +./stm32-lvgl/Sources/Registers/* ./stm32-neopixel/Sources/STM32F7X6/* ./stm32-uart-echo/Sources/STM32F7X6/* diff --git a/README.md b/README.md index 6a66e10..ce75082 100644 --- a/README.md +++ b/README.md @@ -33,6 +33,7 @@ Each example in this repository contains build and deployment instructions, howe | [rpi-picow-blink-sdk](./rpi-picow-blink-sdk) | Raspberry Pi Pico W | Pico SDK | Blink an LED to signal 'SOS' in Morse code repeatedly with Swift & the Pico SDK. | | | [stm32-blink](./stm32-blink) | STM32F746G-DISCO | None | Blink an LED repeatedly. | | | [stm32-lcd-logo](./stm32-lcd-logo) | STM32F746G-DISCO | None | Animate the Swift Logo on the built-in LCD. | | +| [stm32-lvgl](./stm32-lvgl) | STM32F746G-DISCO | – | Baremetal setup of LCD, touch panel, DRAM, using the LLVM Embedded toolchain for ARM. Renders graphics, animations, and reacts to user input via LVGL. Includes a macOS/Linux SDL based host simulation app. | | | [stm32-neopixel](./stm32-neopixel) | STM32F746G-DISCO | None | Control NeoPixel LEDs using SPI. | | | [stm32-uart-echo](./stm32-uart-echo) | STM32F746G-DISCO | None | Echo user input using UART. | | diff --git a/Tools/elf2hex.py b/Tools/elf2hex.py index 37d360e..acb8450 100755 --- a/Tools/elf2hex.py +++ b/Tools/elf2hex.py @@ -18,11 +18,23 @@ # file format suitable for flashing onto some embedded devices. # # Usage: -# $ elf2hex.py [--symbol-map ] +# $ elf2hex.py [--symbol-map ] [--relocate-data-segment] # # Example: # $ elf2hex.py ./blink ./blink.hex --symbol-map ./blink.symbols # +# The --relocate-data-segment option expects to be able to locate symbols with names +# - __data_start +# - __flash_data_start +# - __flash_data_len +# and then it physically relocates a segment located at __data_start to +# __flash_data_start, without changing virtual/physical addresses of any ELF +# headers. This means that the .hex file is not validly mapped until a boot-time +# reverse relocation step. +# +# See the linker script used in a particular demo folder for a detailed +# explanation of the linking, packing, and runtime relocation scheme. +# import argparse import json @@ -36,6 +48,7 @@ def main(): parser.add_argument('input') parser.add_argument('output') parser.add_argument('--symbol-map') + parser.add_argument('--relocate-data-segment', action='store_true') args = parser.parse_args() inf = open(args.input, "rb") @@ -70,25 +83,12 @@ def emit(vmaddr, data): vmaddr += chunklen elffile = elftools.elf.elffile.ELFFile(inf) - for segment in elffile.iter_segments(): - if segment.header.p_type != "PT_LOAD": - continue - vmaddr = segment.header.p_paddr - data = segment.data() - emit(segment.header.p_paddr, data) - - chunklen = 0 - vmaddr = 0 - recordtype = "01" # EOF - emitrecord(f"{chunklen:02X}{vmaddr:04X}{recordtype}") symbol_map = {} symtab_section = elffile.get_section_by_name(".symtab") for s in symtab_section.iter_symbols(): if s.entry.st_info.type not in ["STT_FUNC", "STT_NOTYPE"]: continue - if s.entry.st_shndx == "SHN_ABS": - continue if s.name == "": continue symbol_map[s.name] = s.entry.st_value @@ -96,6 +96,41 @@ def emit(vmaddr, data): if args.symbol_map is not None: pathlib.Path(args.symbol_map).write_text(json.dumps(symbol_map)) + relocations = {} + if args.relocate_data_segment: + __flash_data_start = symbol_map["__flash_data_start"] + __data_start = symbol_map["__data_start"] + __flash_data_len = symbol_map["__flash_data_len"] + print("Relocation info:") + print(f" __flash_data_start = 0x{__flash_data_start:08x}") + print(f" __data_start = 0x{__data_start:08x}") + print(f" __flash_data_len = 0x{__flash_data_len:08x}") + relocations = {__data_start: __flash_data_start} + + for segment in elffile.iter_segments(): + if segment.header.p_type != "PT_LOAD": + continue + vmaddr = segment.header.p_paddr + data = segment.data() + flags = "" + flags += "r" if segment.header.p_flags & 0x4 else "-" + flags += "w" if segment.header.p_flags & 0x2 else "-" + flags += "x" if segment.header.p_flags & 0x1 else "-" + print(f"PT_LOAD {flags} at 0x{segment.header.p_paddr:08x} - " + f"0x{segment.header.p_paddr + len(data):08x}, " + f"size {len(data)} " + f"(0x{len(data):04x})") + placement_addr = segment.header.p_paddr + if segment.header.p_paddr in relocations: + placement_addr = relocations[segment.header.p_paddr] + print(f" ... relocating to 0x{placement_addr:08x}") + emit(placement_addr, data) + + chunklen = 0 + vmaddr = 0 + recordtype = "01" # EOF + emitrecord(f"{chunklen:02X}{vmaddr:04X}{recordtype}") + inf.close() outf.close() diff --git a/stm32-lvgl/.gitignore b/stm32-lvgl/.gitignore new file mode 100644 index 0000000..ea5f98b --- /dev/null +++ b/stm32-lvgl/.gitignore @@ -0,0 +1,2 @@ +lvgl +llvm-toolchain diff --git a/stm32-lvgl/.sourcekit-lsp/config.json b/stm32-lvgl/.sourcekit-lsp/config.json new file mode 100644 index 0000000..7f0beef --- /dev/null +++ b/stm32-lvgl/.sourcekit-lsp/config.json @@ -0,0 +1,11 @@ +{ + "swiftPM": { + "configuration": "release", + "triple": "armv7em-none-none-eabi", + "toolsets": ["toolset.json"], + "swiftCompilerFlags": [ + "-enable-experimental-feature", "Embedded", + "-enable-experimental-feature", "Extern" + ] + } +} diff --git a/stm32-lvgl/Makefile b/stm32-lvgl/Makefile new file mode 100644 index 0000000..54f59dd --- /dev/null +++ b/stm32-lvgl/Makefile @@ -0,0 +1,94 @@ +##===----------------------------------------------------------------------===## +## +## This source file is part of the Swift open source project +## +## Copyright (c) 2025 Apple Inc. and the Swift project authors. +## Licensed under Apache License v2.0 with Runtime Library Exception +## +## See https://swift.org/LICENSE.txt for license information +## +##===----------------------------------------------------------------------===## + +# Paths +REPOROOT := $(shell git rev-parse --show-toplevel) +TOOLSROOT := $(REPOROOT)/Tools +TOOLSET := $(PWD)/toolset.json +ELF2HEX := $(TOOLSROOT)/elf2hex.py +SWIFT_BUILD := swift build +NM := nm +LLVM_TOOLCHAIN := $(PWD)/llvm-toolchain + +# Flags +ARCH := armv7em +TARGET := $(ARCH)-none-none-eabi +SWIFT_BUILD_ARGS := \ + --configuration release \ + --triple $(TARGET) \ + --toolset $(TOOLSET) \ + --product Application +BUILDROOT := $(shell $(SWIFT_BUILD) $(SWIFT_BUILD_ARGS) --show-bin-path) + +.PHONY: build +build: + @echo "checking dependencies..." + + if [[ ! -d $(PWD)/lvgl ]]; then echo "\n *** LVGL checkout not found, please run ./fetch-dependencies.sh\n" ; exit 1 ; fi + if [[ ! -d $(PWD)/llvm-toolchain ]]; then echo "\n *** LLVM toolchain checkout not found, please run ./fetch-dependencies.sh\n" ; exit 1 ; fi + + mkdir -p .build + + @echo "configuring LVGL..." + cmake -B .build/lvgl -G Ninja ./lvgl \ + -DCMAKE_EXPORT_COMPILE_COMMANDS=On \ + -DTOOLCHAIN_PATH=$(LLVM_TOOLCHAIN) \ + -DCMAKE_TOOLCHAIN_FILE=../clang-arm-toolchain.cmake \ + -DLV_CONF_PATH=../Sources/CLVGL/include/lv_conf.h + + @echo "building LVGL..." + cmake --build .build/lvgl + + @echo "building..." + $(SWIFT_BUILD) \ + $(SWIFT_BUILD_ARGS) \ + --verbose + + @echo "disassembling..." + $(LLVM_TOOLCHAIN)/bin/llvm-objdump --all-headers --disassemble --mcpu=cortex-m7 \ + $(BUILDROOT)/Application \ + | c++filt | swift demangle > $(BUILDROOT)/Application.disassembly + + @echo "extracting binary..." + $(ELF2HEX) \ + $(BUILDROOT)/Application $(BUILDROOT)/Application.hex --relocate + ls -al $(BUILDROOT)/Application.hex + @echo "\n *** All done, build succeeded!\n" + +flash: + @echo "flashing..." + st-flash --reset --format ihex write $(BUILDROOT)/Application.hex + +simulator: + mkdir -p .build + + @echo "configuring LVGL..." + cmake -B .build/lvgl-host -G Ninja ./lvgl \ + -DCMAKE_EXPORT_COMPILE_COMMANDS=On \ + -DLV_CONF_PATH=../Sources/CLVGL/include/lv_conf.h + + @echo "building LVGL..." + cmake --build .build/lvgl-host + + @echo "building..." + $(SWIFT_BUILD) \ + --configuration release \ + --product HostSDLApp \ + --verbose + + @echo "running..." + $(PWD)/.build/release/HostSDLApp + +.PHONY: clean +clean: + @echo "cleaning..." + @swift package clean + @rm -rf .build diff --git a/stm32-lvgl/Package.resolved b/stm32-lvgl/Package.resolved new file mode 100644 index 0000000..35151e5 --- /dev/null +++ b/stm32-lvgl/Package.resolved @@ -0,0 +1,42 @@ +{ + "originHash" : "27891c7454528c694f8ba4111e7214ff70b5364bdb54bce808c6e0d4b188bd81", + "pins" : [ + { + "identity" : "swift-argument-parser", + "kind" : "remoteSourceControl", + "location" : "https://github.com/apple/swift-argument-parser.git", + "state" : { + "revision" : "41982a3656a71c768319979febd796c6fd111d5c", + "version" : "1.5.0" + } + }, + { + "identity" : "swift-mmio", + "kind" : "remoteSourceControl", + "location" : "https://github.com/apple/swift-mmio", + "state" : { + "branch" : "main", + "revision" : "5232c5129a8c70beafc3d6acfbae2716c1b6822a" + } + }, + { + "identity" : "swift-syntax", + "kind" : "remoteSourceControl", + "location" : "https://github.com/swiftlang/swift-syntax.git", + "state" : { + "revision" : "0687f71944021d616d34d922343dcef086855920", + "version" : "600.0.1" + } + }, + { + "identity" : "swiftsdl2", + "kind" : "remoteSourceControl", + "location" : "https://github.com/ctreffs/SwiftSDL2.git", + "state" : { + "revision" : "30a2886bd68e43fc19ba29b63ffe230ac0e4db7a", + "version" : "1.4.1" + } + } + ], + "version" : 3 +} diff --git a/stm32-lvgl/Package.swift b/stm32-lvgl/Package.swift new file mode 100644 index 0000000..aa27549 --- /dev/null +++ b/stm32-lvgl/Package.swift @@ -0,0 +1,59 @@ +// swift-tools-version: 5.10 + +import PackageDescription + +let package = Package( + name: "stm32-lvgl", + platforms: [ + .macOS(.v11) + ], + products: [ + .executable(name: "Application", targets: ["Application"]) + ], + dependencies: [ + .package(url: "https://github.com/apple/swift-mmio", branch: "main"), + .package(url: "https://github.com/ctreffs/SwiftSDL2.git", from: "1.4.0"), + ], + targets: [ + // + // FIRMWARE TARGETS + // + + .executableTarget( + name: "Application", + dependencies: [ + "Registers", + "Support", + "CLVGL", + ]), + + // SVD2Swift \ + // --input Tools/SVDs/stm32f7x6.patched.svd \ + // --output stm32-lvgl/Sources/STM32F7x6 \ + // --peripherals FLASH LTDC RCC PWR FMC SCB DBGMCU USART1 STK NVIC SYSCFG \ + // GPIOA GPIOB GPIOC GPIOD GPIOE GPIOF GPIOG GPIOH GPIOI GPIOJ GPIOK \ + // I2C1 I2C2 I2C3 I2C4 \ + // --access-level public + .target( + name: "Registers", + dependencies: [ + .product(name: "MMIO", package: "swift-mmio") + ]), + + .target(name: "Support"), + + .target(name: "CLVGL"), + + // + // HOST TARGETS + // + + .executableTarget( + name: "HostSDLApp", + dependencies: [ + .product(name: "SDL", package: "SwiftSDL2"), + "CLVGL", + ], + swiftSettings: [.enableExperimentalFeature("Extern")], + linkerSettings: [.unsafeFlags(["-L.build/lvgl-host/lib", "-llvgl", "-llvgl_demos"])]), + ]) diff --git a/stm32-lvgl/README.md b/stm32-lvgl/README.md new file mode 100644 index 0000000..8a4d932 --- /dev/null +++ b/stm32-lvgl/README.md @@ -0,0 +1,49 @@ +# stm32-lvgl + + + +This sample code is demonstrating a "full" graphical firmware running on an STM32 microcontroller board, concretely the STM32F746G "Discovery" board. It shows using: + +- **ELF file format**, linking with lld, with a custom simple linker script (and thus it builds identically on both macOS and Linux hosts) +- **LLVM Embedded Toolchain for ARM** +- **LVGL** graphical/input/animation library +- The **DRAM, LCD, touch panel, GPIO pins and interrupts** on the STM32F746G +- **No other SDKs or library dependencies** -- all the startup code, including MCU, board and peripheral initialization is done in Swift source code + +Additionally, this sample code: + +- Has **LSP integration** set up via the `.sourcekit-lsp/config.json` file, confirmed to work in multiple code editors (VS Code, Sublime Text, Zed) +- Uses **SwiftPM's toolset.json** to define compiler and linker flags +- Has a host OS (macOS, Linux) **"simulator" using SDL** that can use the same "business logic" code to render the same LVGL UI. + +## How to build and run this example: + +1. Connect the STM32F746G-DISCO board via the ST-LINK USB port to your Mac. +2. Install the right Swift toolchain specified in this repo's `.swift-version` file. This is best done using `swiftly`: +```console +$ swiftly install # Run in the project's directory +``` +3. Install the `stlink` (https://github.com/stlink-org/stlink) command line tools, e.g. via `brew install stlink`. +4. Run a provided shell script that fetches the LVGL and LLVM dependencies: +```console +$ ./fetch-dependencies.sh +``` +5. Build the firmware by running make: +```console +$ make +``` +6. Flash the built firmware by running make with the following target: +```console +$ make flash +``` + +You should now see the UI animating on the board's LCD display, and the touch screen should react to inputs. + +Optionally, you can also run build and run the code in a desktop OS SDL "simulator" by: +```console +$ make simulator +``` + +## Additional information + +- The ELF linking, linker script and packaging scheme is destribed in detail [inside the linker script](Sources/Support/linkerscript.ld). diff --git a/stm32-lvgl/Sources/Application/Clocks.swift b/stm32-lvgl/Sources/Application/Clocks.swift new file mode 100644 index 0000000..2da683d --- /dev/null +++ b/stm32-lvgl/Sources/Application/Clocks.swift @@ -0,0 +1,423 @@ +//===----------------------------------------------------------------------===// +// +// This source file is part of the Swift open source project +// +// Copyright (c) 2025 Apple Inc. and the Swift project authors. +// Licensed under Apache License v2.0 with Runtime Library Exception +// +// See https://swift.org/LICENSE.txt for license information +// +//===----------------------------------------------------------------------===// + +import Registers +import Support + +/* + * STM32F746 clock configuration has the following constraints: + * + * Select HSE_BYPASS if an oscillator is used instead of a crystal. + * + * VCO: 100-432MHz + * PLL input: 0.95-2.1MHz (higher is less jitter, but not required) + * PLL output: 24-216MHz + * + * Maximum HCLK, APB1, APB2: + * + * Power Scale Over-drive VDD12 HCLK APB1 APB2 + * 3 Off 1.14v 144MHz 45MHz 90MHz + * 2 Off 1.26v 168MHz 45MHz 90MHz + * 2 On 1.26v 180MHz 54MHz 108MHz + * 1 Off 1.32v 180MHz 45MHz 90MHz + * 1 On 1.32v 216MHz 54MHz 108MHz + * + * Ethernet requires HCLK>=25MHz, and USB-HS requires HCLK>=30MHz. + * + * Formulas: + * + * HSE = OSC_IN (e.g 25MHz) + * PLL input = HSE / PLLM (1-2MHz, PLLM=2..63) + * VCO = PLL input * PLLN (100-432MHz, PLLN=50..432) + * PLL output = VCO / PLLP (24-216MHz, PLLP=2,4,6,8) + * HCLK = PLL output / HPRE (Power-of-2 divide by 1-512) + * APB1 = HCLK / PPRE1 (Power-of-2 divide by 1-16) + * APB2 = HCLK / PPRE2 (Power-of-2 divide by 1-16) + * USB-FS/RNG = VCO / PLLQ (48MHz, PLLQ=2..15) + * + * APB1/APB2 TIMx timers have dedicated clocks which are 2x or 4x the + * domain they live in, limited to HCLK. This is selected by the + * TIMPRE bit in RCC: + * + * TIMPRE Multiplier + * 0 2x + * 1 4x + * + * USB-FS requires exactly 48MHz, but this is unused. RNG requires + * 48MHz or lower. + */ + +// The STM32F746-DISCO board has an external 25MHz oscillator +let CPU_TARGET_FREQ = 200 + +// Values for 200 MHz target freq: +let HSE_BYPASS = true // Oscillator, not crystal +let PLL_M: UInt32 = 12 // VCO input = 2.083MHz +let PLL_N: UInt32 = 192 // VCO = 400MHz +let PLL_P: UInt32 = 2 // Divide by 2 = 200MHz +let PLL_Q: UInt32 = 9 // Divide by 9 = 44.5MHz +let HPRE: UInt32 = 1 // AHB = 200 / 1 = 200MHz +let PPRE1: UInt32 = 4 // APB1 = 200 / 4 = 50MHz +let PPRE2: UInt32 = 2 // APB2 = 200 / 2 = 100MHz +let VOLTAGE_SCALE: UInt32 = 1 // 180MHz requires voltage scale 1 (1.32v) +let OVERDRIVE = true // Over-drive required for APB clocks +let TIMER_MUL: UInt32 = 2 // Timer clocks are 2xAPB + +// External oscillator or crystal. +let HSE_VALUE: UInt32 = 25_000_000 + +// This is the built-in oscillator. It always runs at 16MHz +let HSI_CLOCK: UInt32 = 16_000_000 + +/// Represents available system clock sources +public enum SystemClock: UInt32 { + case hsi = 0 // High-Speed Internal oscillator + case hse = 1 // High-Speed External oscillator + case pll = 2 // Phase-Locked Loop + case plli2s = 3 // I2S Phase-Locked Loop + case pllsai = 4 // SAI Phase-Locked Loop +} + +public func enableSystemClock(_ clock: SystemClock, enable: Bool) { + let v: UInt32 = enable ? 1 : 0 + switch clock { + case .hsi: + rcc.cr.modify { $1.raw.hsion = v } + case .hse: + rcc.cr.modify { $1.raw.hseon = v } + case .pll: + rcc.cr.modify { $1.raw.pllon = v } + case .plli2s: + rcc.cr.modify { $1.raw.plli2son = v } + case .pllsai: + rcc.cr.modify { $1.raw.pllsaion = v } + } + + // Dummy read-back as barrier. + _ = rcc.cr.read() +} + +public func waitSystemClock(_ clock: SystemClock, enable: Bool) { + let v: UInt32 = enable ? 1 : 0 + switch clock { + case .hsi: + while rcc.cr.read().raw.hsion != v { /* busy wait */ } + case .hse: + while rcc.cr.read().raw.hseon != v { /* busy wait */ } + case .pll: + while rcc.cr.read().raw.pllon != v { /* busy wait */ } + case .plli2s: + while rcc.cr.read().raw.plli2son != v { /* busy wait */ } + case .pllsai: + while rcc.cr.read().raw.pllsaion != v { /* busy wait */ } + } +} + +public func selectSystemClock(_ clock: SystemClock) { + let sw: UInt32 + let sws: UInt32 + + switch clock { + case .hsi: + sw = 0 // RCC_CFGR_SW_HSI + sws = 0 // RCC_CFGR_SWS_HSI + case .hse: + sw = 1 // RCC_CFGR_SW_HSE + sws = 1 // RCC_CFGR_SWS_HSE + case .pll: + sw = 2 // RCC_CFGR_SW_PLL + sws = 2 // RCC_CFGR_SWS_PLL + default: + preconditionFailure("Bad clock \(clock)") + } + + if rcc.cfgr.read().raw.sw != sw { + // Switch system clock source to the new source + rcc.cfgr.modify { $0.raw.sw = sw } + + // Wait until selected + while rcc.cfgr.read().raw.sws != sws { /* busy wait */ } + } +} + +func setFlashWaitStates(_ hclk: UInt32) { + if (hclk == 0) || (hclk > 216_000_000) { + preconditionFailure("HCLK out of range") + } + + // One wait state per 30MHz (exact multiple of 30MHz uses lower number) + let flash_ws = (hclk - 1) / 30_000_000 + + // Set the flash wait states. + flash.acr.modify { $0.latency = .init(rawValue: UInt8(flash_ws)) } + + // Dummy read-back as barrier. + _ = flash.acr.read() +} + +public func setPllConfiguration(_ config: (hse: Bool, q: UInt32, p: UInt32, n: UInt32, m: UInt32)) { + // PLLQ direct mapped 2..15 + // PLLP 2->0, 4->1, 6->2, 8->3 + // PLLN direct mapped 50..432 + // PLLM direct mapped 2..63 + + // Always assert limits. + if (config.q < 2) || (config.q > 15) || (config.p < 2) || (config.p > 8) || ((config.p % 1) != 0) || (config.n < 50) + || (config.n > 432) || (config.m < 2) || (config.m > 63) + { + preconditionFailure("PllConfig") + } + + // Update PLL configuration using structured register access + rcc.pllcfgr.modify { + $0.pllsrc = config.hse ? .HSE : .HSI + $0.raw.pllq = config.q + $0.raw.pllp = (config.p / 2) - 1 + $0.raw.plln = config.n + $0.raw.pllm = config.m + } + + // Dummy barrier read + _ = rcc.pllcfgr.read() +} + +func setVoltageScale(_ scale: UInt32) { + // Select voltage scaling. This is enacted by hardware when the + // PLL is turned on. The hardware encoding is the reverse of the + // documented voltage scale numbers. + let vosCode: UInt32 + if scale == 1 { + vosCode = 3 + } else if scale == 2 { + vosCode = 2 + } else if scale == 3 { + vosCode = 1 + } else { + preconditionFailure("Voltage scale must be 1..3") + } + + pwr.cr1.modify { + $0.raw.vos = vosCode + } + + // Dummy read-back as barrier. + _ = pwr.cr1.read() +} + +func setOverdrive(_ overdrive: Bool) { + // Configure overdrive mode on or off. + if overdrive { + // See "Entering Over-drive mode" section 4.1.4 STM32F746 Ref + // manual. + pwr.cr1.modify { $0.raw.oden = 1 } + + while pwr.csr1.read().raw.odrdy == 0 { + // Wait until overdrive ready + } + + // Enable overdrive switching. This stalls core clock, but + // this delay is hidden because we are regardless still + // waiting for the PLL to lock. + pwr.cr1.modify { $0.raw.odswen = 1 } + + while pwr.csr1.read().raw.odswrdy == 0 { + // Wait until overdrive switch ready + } + } else { + // Overdrive disable, while system clock is still on HSI. + pwr.cr1.modify { + $0.raw.oden = 0 + $0.raw.odswen = 0 + } + + // Dummy read-back as barrier. + _ = pwr.cr1.read() + } +} + +func setTimerMultiplier(_ multiplier: UInt32) { + if multiplier == 2 { + rcc.dckcfgr1.modify { $0.raw.timpre = 0 } + } else if multiplier == 4 { + rcc.dckcfgr1.modify { $0.raw.timpre = 1 } + } else { + preconditionFailure("Bad TIMPRE") + } +} + +func enableCSS(_ enable: Bool) { + rcc.cr.modify { $1.csson = enable ? .On : .Off } + + // Dummy read-back as barrier. + _ = rcc.cr.read() +} + +func setOscillator(_ enable: Bool) { + rcc.cr.modify { $1.hsebyp = enable ? .Bypassed : .NotBypassed } + + // Dummy read-back as barrier. + _ = rcc.cr.read() +} + +extension UInt64 { + func divideRoundingUp(divideBy: UInt64) -> UInt64 { + return (self + divideBy - 1) / divideBy + } +} + +func log2_exact(_ val: UInt32) -> UInt32 { + guard val.nonzeroBitCount == 1 else { + preconditionFailure("Value \(val) is not a power of 2") + } + return UInt32(val.trailingZeroBitCount) +} + +extension Main { + static func setPrescalers(_ prescalers: (hpre: UInt32, ppre1: UInt32, ppre2: UInt32)) { + let log2_ahb: UInt32 = log2_exact(prescalers.hpre) + let log2_apb1: UInt32 = log2_exact(prescalers.ppre1) + let log2_apb2: UInt32 = log2_exact(prescalers.ppre2) + + let hpreCode: UInt32 + if log2_ahb <= 4 { + // 1, 2, 4, 8, 16 -> 7, 8, 9, 10, 11 + hpreCode = 7 + log2_ahb + } else { + // The code for divide-by-32 is skipped for some reason. + // 64, 128, 256, 512 -> 12, 13, 14, 15 + hpreCode = 6 + log2_ahb + } + let ppre1Code: UInt32 = 3 + log2_apb1 // 1,2,4,8,16 -> 3,4,5,6,7 + let ppre2Code: UInt32 = 3 + log2_apb2 // 1,2,4,8,16 -> 3,4,5,6,7 + + withInterruptsDisabled { + rcc.cfgr.modify { + $0.raw.hpre = hpreCode + $0.raw.ppre1 = ppre1Code + $0.raw.ppre2 = ppre2Code + } + // Dummy read + wait up to 16 AHB clocks to take effect + _ = rcc.cfgr.read() + delay(16) + } + } + + static func initClocks() { + enableSystemClock(.hsi, enable: true) + waitSystemClock(.hsi, enable: true) + selectSystemClock(.hsi) + + setPrescalers((1, 1, 1)) + + // Set dedicated timer clock multiplier to default 2x. + setTimerMultiplier(2) + + // 16MHz operation allows zero-wait-state flash. + setFlashWaitStates(HSI_CLOCK) + + // Disable Clock Security System (CSS). + enableCSS(false) + + // Disable HSE, PLL, PLLI2S, PLLSAI. + enableSystemClock(.hse, enable: false) + enableSystemClock(.pll, enable: false) + enableSystemClock(.plli2s, enable: false) + enableSystemClock(.pllsai, enable: false) + waitSystemClock(.hse, enable: false) + waitSystemClock(.pll, enable: false) + waitSystemClock(.plli2s, enable: false) + waitSystemClock(.pllsai, enable: false) + + // Set PLLCFGR (prescalers and source) to the reset default value + // for 48MHz operation. + setPllConfiguration((hse: false, q: 4, p: 2, n: 96, m: 16)) + + // Default is crystal. + setOscillator(false) + + // XXX, HW required delay for the clocks to be set right + // TODO: figure out which exact operation in the sequence requires the + // delay + delay(4) + } + + static func checkQuiesced() { + // Check that the system is running from HSI. Otherwise, the setup + // sequence will disturb active clocks. + let cfgr = rcc.cfgr.read() + if cfgr.raw.sw != 0 || cfgr.raw.sws != 0 { + preconditionFailure("Not quiesced") + } + + // Check that non-HSI clocks are quiesced, otherwise the setup + // sequence will be prevented by hardware from updating + // configuration bits. + let cr = rcc.cr.read() + if cr.raw.hseon != 0 || cr.raw.csson != 0 || cr.raw.pllon != 0 || cr.raw.plli2son != 0 || cr.raw.pllsaion != 0 { + preconditionFailure("Not quiesced") + } + } + + static func systemSetCoreClock() { + withInterruptsDisabled { + // Check the system has started up sufficiently quiesced, or the + // config sequence may disturb clocks out of spec, or the micro + // may prevent some bits from being updated. + checkQuiesced() + + // We need the PWR block enabled. + rcc.apb1enr.modify { $0.raw.pwren = 1 } + delay(32) + + // Set flash controller wait states for the target HCLK. Quiesced + // state accepts any value (it just runs slow). + let hclk = UInt64(UInt64(HSE_VALUE) * UInt64(PLL_N)).divideRoundingUp( + divideBy: UInt64(PLL_M) * UInt64(PLL_P) * UInt64(HPRE)) + if (hclk == 0) || (hclk > 216_000_000) { + preconditionFailure("HCLK out of range") + } + setFlashWaitStates(UInt32(hclk)) + + // Configure the target PLL frequency and required voltage. + setPllConfiguration((hse: true, q: PLL_Q, p: PLL_P, n: PLL_N, m: PLL_M)) + setVoltageScale(VOLTAGE_SCALE) + + // Configure, enable, and wait for the HSE clock. + setOscillator(HSE_BYPASS) + enableSystemClock(.hse, enable: true) + waitSystemClock(.hse, enable: true) + + // Enable and wait for the PLL. PLL t_LOCK<=300usec takes a + // while. Overdrive Tod_swen<=100usec is also slow, and can be + // configure concurrently. + enableSystemClock(.pll, enable: true) + setOverdrive(OVERDRIVE) + waitSystemClock(.pll, enable: true) + + // Increase CPU and peripheral dividers. This will very + // temporarily run the system slow as we are still on 16MHz + // HSI. Then finally switch to the system to PLL. + setPrescalers((HPRE, PPRE1, PPRE2)) + selectSystemClock(.pll) + + // Set dedicated timer clock multiplier 2x or 4x. + setTimerMultiplier(TIMER_MUL) + + // Enable SYSCFG clock in APB2 peripheral clock register + rcc.apb2enr.modify { $0.raw.syscfgen = 1 } + delay(32) + + // Enable I/O Compensation Cell + syscfg.cmpcr.modify { $1.raw.cmp_pd = 1 } + while syscfg.cmpcr.read().raw.ready == 0 { /* busy wait */ } + } + } +} diff --git a/stm32-lvgl/Sources/Application/Debug.swift b/stm32-lvgl/Sources/Application/Debug.swift new file mode 100644 index 0000000..b5788c2 --- /dev/null +++ b/stm32-lvgl/Sources/Application/Debug.swift @@ -0,0 +1,67 @@ +//===----------------------------------------------------------------------===// +// +// This source file is part of the Swift open source project +// +// Copyright (c) 2025 Apple Inc. and the Swift project authors. +// Licensed under Apache License v2.0 with Runtime Library Exception +// +// See https://swift.org/LICENSE.txt for license information +// +//===----------------------------------------------------------------------===// + +import Registers +import Support + +extension Main { + static func initDebug() { + // Keep clocks going when we WFI + dbgmcu.cr.modify { $0.raw.dbg_standby = 1 } + } + + static func initUartOutput() { + // A9 is UART1 TX, which is relayed by ST-LINK over USB + + // Clock configuration + rcc.ahb1enr.modify { $0.raw.gpioaen = 1 } // Enable AHB clock to port A + rcc.apb2enr.modify { $0.raw.usart1en = 1 } // Enable APB clock to usart 1 + + // Configure A9 as UART1 TX + gpioa.moder.modify { $0.raw.moder9 = 0b10 } // Put Pin A9 into alternate function mode + gpioa.otyper.modify { $0.raw.ot9 = 0b0 } // Put Pin A9 into push pull + gpioa.ospeedr.modify { $0.raw.ospeedr9 = 0b00 } // Put Pin A9 into low speed + gpioa.pupdr.modify { $0.raw.pupdr9 = 0b00 } // Disable pull up/down on Pin A9 + gpioa.afrh.modify { $0.raw.afrh9 = 0b0111 } // Set alternate function usart1 on Pin A9 + + // Configure UART1, set the baud rate to 115200 (we boot at 16 MHz) + usart1.brr.modify { $0.raw.storage = 16_000_000 / 115_200 } + + usart1.cr1.modify { + $0.raw.ue = 1 // Enable USART 1 + $0.raw.te = 1 // Enable TX + } + } +} + +func waitTxBufferEmpty() { + // Spin while tx buffer not empty + while usart1.isr.read().raw.txe == 0 {} +} + +func tx(value: UInt8) { + usart1.tdr.write { $0.raw.tdr_field = UInt32(value) } +} + +@_cdecl("putchar") +public func putchar(_ value: CInt) -> CInt { + waitTxBufferEmpty() + tx(value: UInt8(value)) + waitTxBufferEmpty() + return 0 +} + +func log(_ s: String) { + let n = uptimeInMs / 1000 + var m = String(uptimeInMs % 1000) + while m.utf8.count < 3 { m = "0" + m } + print("[\(n).\(m)] " + s) +} diff --git a/stm32-lvgl/Sources/Application/I2C.swift b/stm32-lvgl/Sources/Application/I2C.swift new file mode 100644 index 0000000..266fc6d --- /dev/null +++ b/stm32-lvgl/Sources/Application/I2C.swift @@ -0,0 +1,156 @@ +//===----------------------------------------------------------------------===// +// +// This source file is part of the Swift open source project +// +// Copyright (c) 2025 Apple Inc. and the Swift project authors. +// Licensed under Apache License v2.0 with Runtime Library Exception +// +// See https://swift.org/LICENSE.txt for license information +// +//===----------------------------------------------------------------------===// + +import MMIO +import Registers +import Support + +struct I2C { + let i2c: I2C1 + let deviceAddress: UInt8 + + enum Interface: Int { + case i2c1 = 0 + case i2c2 + case i2c3 + case i2c4 + } + + init(interface: Interface, deviceAddress: UInt8) { + self.deviceAddress = deviceAddress + + switch interface { + case .i2c1: + self.i2c = i2c1 + rcc.apb1enr.modify { $0.raw.i2c1en = 1 } // Enable clock + case .i2c2: + self.i2c = i2c2 + rcc.apb1enr.modify { $0.raw.i2c2en = 1 } // Enable clock + case .i2c3: + self.i2c = i2c3 + rcc.apb1enr.modify { $0.raw.i2c3en = 1 } // Enable clock + case .i2c4: + self.i2c = i2c4 + rcc.apb1enr.modify { $0.raw.i2c4en = 1 } // Enable clock + } + + // Reset I2C peripheral + i2c.cr1.write { $0.raw.pe = 0 } + + // Configure I2C timing for 100KHz (based on 50MHz APB1 clock) + i2c.timingr.write { + $0.raw.presc = 0x09 // Prescaler + $0.raw.scldel = 0x04 // Data setup time + $0.raw.sdadel = 0x02 // Data hold time + $0.raw.sclh = 0x0F // SCL high period + $0.raw.scll = 0x13 // SCL low period + } + + // Enable I2C peripheral + i2c.cr1.modify { + $0.raw.pe = 1 // Enable peripheral + $0.raw.anfoff = 0 // Analog filter enabled + $0.raw.dnf = 0 // Digital filter disabled + } + } + + func write(data: [UInt8]) -> Bool { + // Wait until I2C is not busy + while i2c.isr.read().raw.busy == 1 { /* busy wait */ } + + // Set slave address + i2c.cr2.write { + $0.raw.sadd = UInt32(deviceAddress) << 1 // 7-bit address, shifted left by 1 + $0.raw.nbytes = UInt32(data.count) + $0.raw.autoend = 1 // Automatic end mode + $0.raw.start = 1 // Generate start condition + $0.raw.rd_wrn = 0 // Write transfer + } + + // Send data bytes + for byte in data { + // Wait until TXIS is set (transmit register empty) + while i2c.isr.read().raw.txis == 0 { + // Check for errors + let isr = i2c.isr.read().raw + if isr.nackf == 1 { + // NACK received + i2c.icr.write { $0.raw.nackcf = 1 } // Clear NACK flag + return false + } + } + + // Write data to TXDR + i2c.txdr.write { $0.raw.txdata = UInt32(byte) } + } + + // Wait for transfer complete + while i2c.isr.read().raw.tc == 0 && i2c.isr.read().raw.tcr == 0 && i2c.isr.read().raw.stopf == 0 { + // Check for errors + if i2c.isr.read().raw.nackf == 1 { + i2c.icr.write { $0.raw.nackcf = 1 } // Clear NACK flag + return false + } + } + + // Clear flags + let isr = i2c.isr.read().raw + i2c.icr.write { + $0.raw.stopcf = isr.stopf + $0.raw.nackcf = isr.nackf + } + + return true + } + + func read(buffer: inout [UInt8], length: Int) -> Bool { + // Wait until I2C is not busy + while i2c.isr.read().raw.busy == 1 { /* busy wait */ } + + // Set slave address and read operation + i2c.cr2.write { + $0.raw.sadd = UInt32(deviceAddress) << 1 // 7-bit address, shifted left by 1 + $0.raw.nbytes = UInt32(length) + $0.raw.autoend = 1 // Automatic end mode + $0.raw.rd_wrn = 1 // Read transfer + $0.raw.start = 1 // Generate start condition + } + + // Read data + for i in 0.. Void) { + let oldMask = primask_get() + cpsid_i() + body() + primask_set(oldMask) +} + +extension Main { + static func initInterrupts() { + // Disable then clear all RCC interrupts. + rcc.cir.modify { + $1.raw.lsirdyie = 0 + $1.raw.lserdyie = 0 + $1.raw.hsirdyie = 0 + $1.raw.hserdyie = 0 + $1.raw.pllrdyie = 0 + $1.raw.plli2srdyie = 0 + $1.raw.pllsairdyie = 0 + } + rcc.cir.modify { + $1.raw.lsirdyie = 1 + $1.raw.lserdyie = 1 + $1.raw.hsirdyie = 1 + $1.raw.hserdyie = 1 + $1.raw.pllrdyie = 1 + $1.raw.plli2srdyie = 1 + $1.raw.pllsairdyie = 1 + } + } +} + +var uptimeInMs = 0 + +extension Main { + static func initSysTick() { + stk.rvr.write { $0.raw.reload = 200_000 } // Set the reload value, ~1ms + stk.cvr.write { $0.raw.current = 0 } // Clear the current value + + // Enable the SysTick timer with processor clock + stk.csr.modify { + $0.raw.enable = 1 + $0.raw.tickint = 1 + $0.raw.clksource = 1 + } + + // Wait one tick for wrap. This eliminates ambiguity at the + // zero count. This is only possible if SysTick is + // (significantly) slower than the core clock. + while stk.cvr.read().raw.current == 0 { /* busy wait */ } + } +} + +@_cdecl("SystickTimerISR") +func SystickTimerISR() { + uptimeInMs += 1 +} + +var lcdInterruptVerticalSyncHandler: (() -> Void)? = nil + +@_cdecl("LtdcIntHandlerISR") +func LtdcIntHandlerISR() { + let sr = ltdc.isr.read() + ltdc.icr.write { $0.storage = sr.storage } + if sr.raw.rrif != 0 { + lcdInterruptVerticalSyncHandler?() + } +} diff --git a/stm32-lvgl/Sources/Application/Lcd.swift b/stm32-lvgl/Sources/Application/Lcd.swift new file mode 100644 index 0000000..bd8b26d --- /dev/null +++ b/stm32-lvgl/Sources/Application/Lcd.swift @@ -0,0 +1,128 @@ +//===----------------------------------------------------------------------===// +// +// This source file is part of the Swift open source project +// +// Copyright (c) 2025 Apple Inc. and the Swift project authors. +// Licensed under Apache License v2.0 with Runtime Library Exception +// +// See https://swift.org/LICENSE.txt for license information +// +//===----------------------------------------------------------------------===// + +import MMIO +import Registers +import Support + +enum Lcd { + static let LCD_HSYNC: UInt32 = 10 + static let LCD_VSYNC: UInt32 = 2 + static let LCD_HBP: UInt32 = 43 + static let LCD_VBP: UInt32 = 12 + static let LCD_WIDTH: UInt32 = 480 + static let LCD_HEIGHT: UInt32 = 272 + static let LCD_HFP: UInt32 = 8 + static let LCD_VFP: UInt32 = 4 + static let LCD_PIXSIZE: UInt32 = 4 + static let SDRAM_BASE: UInt32 = 0xC000_0000 + + /// Initialize the LTDC module and get the display panel running. + static func initialize() { + // Configure the PLL for the display refresh. The LTDC has its own PLL. + // This code sets the DOTCLK to 8MHz or so. + let sain: UInt32 = 192 + let saiq = rcc.pllsaicfgr.read().raw.pllsaiq + let sair: UInt32 = 4 + + rcc.pllsaicfgr.write { + $0.raw.pllsain = sain + $0.raw.pllsaiq = saiq + $0.raw.pllsair = sair + } + rcc.dckcfgr1.modify { $0.pllsaidivr = .Div8 } + rcc.cr.modify { $1.raw.pllsaion = 1 } + + // Wait for PLLSAI to be ready + while rcc.cr.read().raw.pllsairdy == 0 { /* busy wait */ } + + // Enable clock to the LCD controller + rcc.apb2enr.modify { $0.raw.ltdcen = 1 } + + // Program the timing parameters for the panel + ltdc.sscr.write { + $0.raw.hsw = LCD_HSYNC - 1 + $0.raw.vsh = LCD_VSYNC - 1 + } + ltdc.bpcr.write { + $0.raw.ahbp = LCD_HSYNC + LCD_HBP - 1 + $0.raw.avbp = LCD_VSYNC + LCD_VBP - 1 + } + ltdc.awcr.write { + $0.raw.aaw = LCD_HSYNC + LCD_HBP + LCD_WIDTH - 1 + $0.raw.aah = LCD_VSYNC + LCD_VBP + LCD_HEIGHT - 1 + } + ltdc.twcr.write { + $0.raw.totalw = LCD_HSYNC + LCD_HBP + LCD_WIDTH + LCD_HFP - 1 + $0.raw.totalh = LCD_VSYNC + LCD_VBP + LCD_HEIGHT + LCD_VFP - 1 + } + + // Set background color to black + ltdc.bccr.write { $0.raw.storage = 0 } + + // Configure layer 1 + let h_start = LCD_HSYNC + LCD_HBP + 0 + let h_stop = LCD_HSYNC + LCD_HBP + LCD_WIDTH - 1 + let v_start = LCD_VSYNC + LCD_VBP + 0 + let v_stop = LCD_VSYNC + LCD_VBP + LCD_HEIGHT - 1 + let pitch = LCD_WIDTH * LCD_PIXSIZE + let length = LCD_WIDTH * LCD_PIXSIZE + 3 + ltdc.layer[0].whpcr.write { + $0.raw.whsppos = h_stop + $0.raw.whstpos = h_start + } + ltdc.layer[0].wvpcr.write { + $0.raw.wvsppos = v_stop + $0.raw.wvstpos = v_start + } + ltdc.layer[0].pfcr.write { + $0.raw.pf = 0 // ARGB8888 + } + ltdc.layer[0].cfbar.write { + $0.raw.cfbadd = SDRAM_BASE + } + ltdc.layer[0].cfblr.write { + $0.raw.cfbp = pitch + $0.raw.cfbll = length + } + ltdc.layer[0].cfblnr.write { + $0.raw.cfblnbr = LCD_HEIGHT + } + ltdc.layer[0].cacr.write { + $0.raw.consta = 0xFF + } + ltdc.layer[0].bfcr.write { + $0.raw.bf1 = 6 + $0.raw.bf2 = 7 + } + + // Enable layer 1 + ltdc.layer[0].cr.modify { $0.raw.len = 1 } + + // Turn on the display + ltdc.srcr.modify { $0.raw.vbr = 1 } + ltdc.gcr.modify { $1.ltdcen = .Enabled } + + // Enable interrupts + ltdc.ier.modify { $0.raw.rrie = 1 } + nvic.iser2.modify { + $0.raw.setena = (1 << (88 - 64)) // LTDC_IRQn is typically 88 + } + } + + static func setFrameBuffer(_ p: UnsafeRawPointer) { + ltdc.layer[0].cfbar.write { $0.raw.cfbadd = UInt32(UInt(bitPattern: p)) } + } + + static func reloadConfiguration() { + ltdc.srcr.modify { $0.raw.vbr = 1 } + } +} diff --git a/stm32-lvgl/Sources/Application/Main.swift b/stm32-lvgl/Sources/Application/Main.swift new file mode 100644 index 0000000..d2722dc --- /dev/null +++ b/stm32-lvgl/Sources/Application/Main.swift @@ -0,0 +1,163 @@ +//===----------------------------------------------------------------------===// +// +// This source file is part of the Swift open source project +// +// Copyright (c) 2025 Apple Inc. and the Swift project authors. +// Licensed under Apache License v2.0 with Runtime Library Exception +// +// See https://swift.org/LICENSE.txt for license information +// +//===----------------------------------------------------------------------===// + +import CLVGL +import Registers +import Support + +@main +struct Main { + static func main() { + // main is called very early in the boot process; here we are just after + // (1) reset IRQ entrypoint, (2) enabling FPU, (3) relocating data sections + // from flash to SRAM. Notably, no HW register configuration has been done + // yet (except for the FPU enablement), and no static constructors have been + // called yet. + + // We boot at 16 MHz. + initDebug() + initUartOutput() + + withInterruptsDisabled { + log("initClock()") + initClocks() + + log("initInterrupts()") + initInterrupts() + + // Reset the vector table to where it should be. + log("init VTOR") + scb.vtor.modify { $0.storage = 0x0800_0000 } + } + + log("systemSetCoreClock()") + systemSetCoreClock() + + // We are running at 200 MHz CPU frequency now. Set the UART baud rate to + // 115200 again based on the new CPU frequency. + usart1.brr.modify { $0.raw.storage = 100_000_000 / 115_200 } + + log("initGpio()") + initGpio() + log("initSdram()") + initSdram() + log("Lcd.initialize()") + Lcd.initialize() + + log("initSysTick") + initSysTick() + + log("TouchPanel.initialize()") + TouchPanel.initialize() + + // Everything is initialized now. Run application logic. + + //log("dramTest()") + //dramTest() + + log("lvglDemo()") + lvglDemo() + } + + static func dramTest() { + let dramSizeInUInt32 = dramSize / 4 + + func fillAndCheck(pattern: UInt32) { + for i in 0.. 0 { + data!.pointee.point.x = Int32(touchData.x) + data!.pointee.point.y = Int32(touchData.y) + data!.pointee.state = LV_INDEV_STATE_PRESSED + //print("pressed: \(touchData.x) \(touchData.y)") + } else { + data!.pointee.state = LV_INDEV_STATE_RELEASED + //print("released") + } + }) + + // Add UI of application logic + UIAppLogic.createUI() + + log("LVGL setup done, starting render loop") + + while true { + // If we're pending a render, wait. + while lcdInterruptVerticalSyncHandler != nil { /* busy wait */ nop() } + + lv_timer_handler() + + // Update UI of application logic + UIAppLogic.updateFrame() + } + } +} diff --git a/stm32-lvgl/Sources/Application/Pins.swift b/stm32-lvgl/Sources/Application/Pins.swift new file mode 100644 index 0000000..b117108 --- /dev/null +++ b/stm32-lvgl/Sources/Application/Pins.swift @@ -0,0 +1,882 @@ +//===----------------------------------------------------------------------===// +// +// This source file is part of the Swift open source project +// +// Copyright (c) 2025 Apple Inc. and the Swift project authors. +// Licensed under Apache License v2.0 with Runtime Library Exception +// +// See https://swift.org/LICENSE.txt for license information +// +//===----------------------------------------------------------------------===// + +import MMIO +import Registers +import Support + +/// GPIO Port enumerations +enum GPIOPort: UInt32 { + case portA = 0 + case portB, portC, portD, portE, portF, portG, portH, portI, portJ, portK +} + +/// GPIO Pin numbers +enum GPIOPinNumber: UInt32 { + case pin0 = 0 + case pin1, pin2, pin3, pin4, pin5, pin6, pin7 + case pin8, pin9, pin10, pin11, pin12, pin13, pin14, pin15 + case pin16, pin17, pin18, pin19, pin20, pin21, pin22, pin23 + case pin24, pin25, pin26, pin27, pin28, pin29, pin30, pin31 + case pin32, pin33, pin34, pin35, pin36, pin37, pin38, pin39 + case pin40, pin41 +} + +/// Alternate Function modes +enum AltFunction: UInt8 { + case altFunc0 = 0 + case altFunc1, altFunc2, altFunc3, altFunc4, altFunc5, altFunc6, altFunc7 + case altFunc8, altFunc9, altFunc10, altFunc11, altFunc12, altFunc13, altFunc14, altFunc15 +} + +/// Pull-up/Pull-down configurations +enum GPIOPull: UInt32 { + case none = 0 + case pullUp + case pullDown +} + +/// GPIO pin speed configurations +enum GPIOSpeed: UInt8 { + case low = 0 + case medium + case high + case max +} + +/// GPIO pin modes +enum GPIOMode: UInt32 { + case input = 0 + case output + case alternate + case analog + case disabled +} + +/// GPIO output modes +enum GPIOOutput: UInt32 { + case pushPull = 0 + case openDrain +} + +/// GPIO pin definition structure +struct GPIOPin { + let name: String + let port: GPIOPort + let number: GPIOPinNumber + let mode: GPIOMode + let pull: GPIOPull + let outputType: GPIOOutput + let altFunction: AltFunction + let defaultValue: Bool + let speed: GPIOSpeed + let activeLow: Bool + let inUse: Bool + let isEndOfTable: Bool +} + +/// GPIO direct output control structure +struct GPIOOutputDirect { + let setRegister: UnsafeMutablePointer + let setValue: UInt32 + let clearRegister: UnsafeMutablePointer + let clearValue: UInt32 +} + +/// GPIO direct input control structure +struct GPIOInputDirect { + let register: UnsafeMutablePointer + let mask: UInt32 +} + +/// GPIO mode control structure +struct GPIOModeDirect { + let modeRegister: UnsafeMutablePointer + let modeMask: UInt32 + let inputMode: UInt32 + let outputMode: UInt32 +} + +/// Typealias for GPIO identifier +typealias GPIO = Int + +/// Helper functions to create pin configurations +extension GPIOPin { + static func gpioOutput(name: String, port: GPIOPort, pin: GPIOPinNumber, defaultValue: Bool) -> GPIOPin { + return GPIOPin( + name: name, + port: port, + number: pin, + mode: .output, + pull: .none, + outputType: .pushPull, + altFunction: .altFunc0, + defaultValue: defaultValue, + speed: .low, + activeLow: false, + inUse: true, + isEndOfTable: false + ) + } + + static func gpioOutputSpeed(name: String, port: GPIOPort, pin: GPIOPinNumber, defaultValue: Bool, speed: GPIOSpeed) + -> GPIOPin + { + return GPIOPin( + name: name, + port: port, + number: pin, + mode: .output, + pull: .none, + outputType: .pushPull, + altFunction: .altFunc0, + defaultValue: defaultValue, + speed: speed, + activeLow: false, + inUse: true, + isEndOfTable: false + ) + } + + static func gpioOutputActiveLow(name: String, port: GPIOPort, pin: GPIOPinNumber, defaultValue: Bool) -> GPIOPin { + return GPIOPin( + name: name, + port: port, + number: pin, + mode: .output, + pull: .none, + outputType: .pushPull, + altFunction: .altFunc0, + defaultValue: defaultValue, + speed: .low, + activeLow: true, + inUse: true, + isEndOfTable: false + ) + } + + static func gpioOutputOpenDrain(name: String, port: GPIOPort, pin: GPIOPinNumber, defaultValue: Bool) -> GPIOPin { + return GPIOPin( + name: name, + port: port, + number: pin, + mode: .output, + pull: .none, + outputType: .openDrain, + altFunction: .altFunc0, + defaultValue: defaultValue, + speed: .low, + activeLow: false, + inUse: true, + isEndOfTable: false + ) + } + + static func gpioOutputOpenDrainActiveLow(name: String, port: GPIOPort, pin: GPIOPinNumber, defaultValue: Bool) + -> GPIOPin + { + return GPIOPin( + name: name, + port: port, + number: pin, + mode: .output, + pull: .none, + outputType: .openDrain, + altFunction: .altFunc0, + defaultValue: defaultValue, + speed: .low, + activeLow: true, + inUse: true, + isEndOfTable: false + ) + } + + static func altFunction(name: String, port: GPIOPort, pin: GPIOPinNumber, alt: AltFunction, outputType: GPIOOutput) + -> GPIOPin + { + return GPIOPin( + name: name, + port: port, + number: pin, + mode: .alternate, + pull: .none, + outputType: outputType, + altFunction: alt, + defaultValue: false, + speed: .low, + activeLow: false, + inUse: true, + isEndOfTable: false + ) + } + + static func altFunctionSpeed( + name: String, port: GPIOPort, pin: GPIOPinNumber, alt: AltFunction, outputType: GPIOOutput, speed: GPIOSpeed + ) -> GPIOPin { + return GPIOPin( + name: name, + port: port, + number: pin, + mode: .alternate, + pull: .none, + outputType: outputType, + altFunction: alt, + defaultValue: false, + speed: speed, + activeLow: false, + inUse: true, + isEndOfTable: false + ) + } + + static func altFunctionSpeedPullUp( + name: String, port: GPIOPort, pin: GPIOPinNumber, alt: AltFunction, outputType: GPIOOutput, speed: GPIOSpeed + ) -> GPIOPin { + return GPIOPin( + name: name, + port: port, + number: pin, + mode: .alternate, + pull: .pullUp, + outputType: outputType, + altFunction: alt, + defaultValue: false, + speed: speed, + activeLow: false, + inUse: true, + isEndOfTable: false + ) + } + + static func analog(name: String, port: GPIOPort, pin: GPIOPinNumber) -> GPIOPin { + return GPIOPin( + name: name, + port: port, + number: pin, + mode: .analog, + pull: .none, + outputType: .pushPull, + altFunction: .altFunc0, + defaultValue: false, + speed: .low, + activeLow: false, + inUse: true, + isEndOfTable: false + ) + } + + static func disabled(name: String, port: GPIOPort, pin: GPIOPinNumber) -> GPIOPin { + return GPIOPin( + name: name, + port: port, + number: pin, + mode: .disabled, + pull: .none, + outputType: .pushPull, + altFunction: .altFunc0, + defaultValue: false, + speed: .low, + activeLow: false, + inUse: true, + isEndOfTable: false + ) + } + + static func gpioInput(name: String, port: GPIOPort, pin: GPIOPinNumber) -> GPIOPin { + return GPIOPin( + name: name, + port: port, + number: pin, + mode: .input, + pull: .none, + outputType: .pushPull, + altFunction: .altFunc0, + defaultValue: false, + speed: .low, + activeLow: false, + inUse: true, + isEndOfTable: false + ) + } + + static func gpioInputSpeed(name: String, port: GPIOPort, pin: GPIOPinNumber, speed: GPIOSpeed) -> GPIOPin { + return GPIOPin( + name: name, + port: port, + number: pin, + mode: .input, + pull: .none, + outputType: .pushPull, + altFunction: .altFunc0, + defaultValue: false, + speed: speed, + activeLow: false, + inUse: true, + isEndOfTable: false + ) + } + + static func gpioInputPullUp(name: String, port: GPIOPort, pin: GPIOPinNumber) -> GPIOPin { + return GPIOPin( + name: name, + port: port, + number: pin, + mode: .input, + pull: .pullUp, + outputType: .pushPull, + altFunction: .altFunc0, + defaultValue: false, + speed: .low, + activeLow: false, + inUse: true, + isEndOfTable: false + ) + } + + static func gpioInputPullDown(name: String, port: GPIOPort, pin: GPIOPinNumber) -> GPIOPin { + return GPIOPin( + name: name, + port: port, + number: pin, + mode: .input, + pull: .pullDown, + outputType: .pushPull, + altFunction: .altFunc0, + defaultValue: false, + speed: .low, + activeLow: false, + inUse: true, + isEndOfTable: false + ) + } + + static func gpioInputActiveLow(name: String, port: GPIOPort, pin: GPIOPinNumber) -> GPIOPin { + return GPIOPin( + name: name, + port: port, + number: pin, + mode: .input, + pull: .none, + outputType: .pushPull, + altFunction: .altFunc0, + defaultValue: false, + speed: .low, + activeLow: true, + inUse: true, + isEndOfTable: false + ) + } + + static func gpioInputActiveLowPullUp(name: String, port: GPIOPort, pin: GPIOPinNumber) -> GPIOPin { + return GPIOPin( + name: name, + port: port, + number: pin, + mode: .input, + pull: .pullUp, + outputType: .pushPull, + altFunction: .altFunc0, + defaultValue: false, + speed: .low, + activeLow: true, + inUse: true, + isEndOfTable: false + ) + } + + static func gpioInputActiveLowPullDown(name: String, port: GPIOPort, pin: GPIOPinNumber) -> GPIOPin { + return GPIOPin( + name: name, + port: port, + number: pin, + mode: .input, + pull: .pullDown, + outputType: .pushPull, + altFunction: .altFunc0, + defaultValue: false, + speed: .low, + activeLow: true, + inUse: true, + isEndOfTable: false + ) + } + + static func endTable(name: String) -> GPIOPin { + return GPIOPin( + name: name, + port: .portA, + number: .pin0, + mode: .disabled, + pull: .none, + outputType: .pushPull, + altFunction: .altFunc0, + defaultValue: false, + speed: .low, + activeLow: false, + inUse: false, + isEndOfTable: true + ) + } +} + +/// GPIO pin identifier enum +enum GPIOPinID: Int { + case greenLED, blueButton + case uart1TX, uart1RX + case i2c1SCL, i2c1SDA, i2c3SCL, i2c3SDA + case bbI2C_SCL, bbI2C_SDA + case lcdBLCtrl, lcdINT, lcdDISP + case _sdramA0, _sdramA1, _sdramA2, _sdramA3, _sdramA4, _sdramA5, _sdramA6, _sdramA7 + case _sdramA8, _sdramA9, _sdramA10, _sdramA11 + case _sdramBA0, _sdramBA1 + case _sdramDQ0, _sdramDQ1, _sdramDQ2, _sdramDQ3, _sdramDQ4, _sdramDQ5, _sdramDQ6, _sdramDQ7 + case _sdramDQ8, _sdramDQ9, _sdramDQ10, _sdramDQ11, _sdramDQ12, _sdramDQ13, _sdramDQ14, _sdramDQ15 + case _sdramSDNE0, _sdramSDNWE, _sdramSDNRAS, _sdramSDNCAS, _sdramSDCLK, _sdramSDCKE0 + case _sdramNBL0, _sdramNBL1 + case _lcdHSYNC, _lcdVSYNC, _lcdDOTCLK, _lcdENABLE + case _lcdB0, _lcdB1, _lcdB2, _lcdB3, _lcdB4, _lcdB5, _lcdB6, _lcdB7 + case _lcdR0, _lcdR1, _lcdR2, _lcdR3, _lcdR4, _lcdR5, _lcdR6, _lcdR7 + case _lcdG0, _lcdG1, _lcdG2, _lcdG3, _lcdG4, _lcdG5, _lcdG6, _lcdG7 + case _ethTXEN, _ethTXD0, _ethTXD1, _ethRXD0, _ethRXD1, _ethRXER, _ethCRSDV + case _ethMDC, _ethMDIO, _ethREFCLK + case _ulpiCK, _ulpiSTP, _ulpiDIR, _ulpiNXT + case _ulpiD0, _ulpiD1, _ulpiD2, _ulpiD3, _ulpiD4, _ulpiD5, _ulpiD6, _ulpiD7 + case otgHSOC + case tableEnd +} + +/// Pin table definition +/// Note: This implementation uses a dictionary-based lookup which requires: +/// - Memory allocations for the dictionary storage +/// - Runtime dependencies (e.g. on getentropy for hash randomization) +/// - Additional overhead for hash table operations +/// +/// If these dependencies are unwanted, this code could be optimized to use a +/// compile-time array or a switch statement instead. +let pinTable: [GPIOPinID: GPIOPin] = [ + // The LED on the eval board + .greenLED: .gpioOutput(name: "GREEN_LED", port: .portI, pin: .pin1, defaultValue: true), + + // User button on the board + .blueButton: .gpioInput(name: "BLUE_BUTTON", port: .portI, pin: .pin11), + + // Console UART + .uart1TX: .altFunction(name: "UART1_TX", port: .portA, pin: .pin9, alt: .altFunc7, outputType: .pushPull), + .uart1RX: .altFunction(name: "UART1_RX", port: .portB, pin: .pin7, alt: .altFunc7, outputType: .pushPull), + + // I2C buses + .i2c1SCL: .altFunction(name: "I2C1_SCL", port: .portB, pin: .pin8, alt: .altFunc4, outputType: .openDrain), + .i2c1SDA: .altFunction(name: "I2C1_SDA", port: .portB, pin: .pin9, alt: .altFunc4, outputType: .openDrain), + .i2c3SCL: .altFunction(name: "I2C3_SCL", port: .portH, pin: .pin7, alt: .altFunc4, outputType: .openDrain), + .i2c3SDA: .altFunction(name: "I2C3_SDA", port: .portH, pin: .pin8, alt: .altFunc4, outputType: .openDrain), + .bbI2C_SCL: .gpioInput(name: "BBI2C_SCL", port: .portF, pin: .pin8), + .bbI2C_SDA: .gpioInput(name: "BBI2C_SDA", port: .portF, pin: .pin9), + + // LCD pins + .lcdBLCtrl: .gpioOutput(name: "LCD_BL_CTRL", port: .portK, pin: .pin3, defaultValue: true), + .lcdINT: .gpioInputPullUp(name: "LCD_INT", port: .portI, pin: .pin13), + .lcdDISP: .gpioOutput(name: "LCD_DISP", port: .portI, pin: .pin12, defaultValue: true), + + // SDRAM pins + ._sdramA0: .altFunctionSpeed( + name: "_SDRAM_A0", port: .portF, pin: .pin0, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramA1: .altFunctionSpeed( + name: "_SDRAM_A1", port: .portF, pin: .pin1, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramA2: .altFunctionSpeed( + name: "_SDRAM_A2", port: .portF, pin: .pin2, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramA3: .altFunctionSpeed( + name: "_SDRAM_A3", port: .portF, pin: .pin3, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramA4: .altFunctionSpeed( + name: "_SDRAM_A4", port: .portF, pin: .pin4, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramA5: .altFunctionSpeed( + name: "_SDRAM_A5", port: .portF, pin: .pin5, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramA6: .altFunctionSpeed( + name: "_SDRAM_A6", port: .portF, pin: .pin12, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramA7: .altFunctionSpeed( + name: "_SDRAM_A7", port: .portF, pin: .pin13, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramA8: .altFunctionSpeed( + name: "_SDRAM_A8", port: .portF, pin: .pin14, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramA9: .altFunctionSpeed( + name: "_SDRAM_A9", port: .portF, pin: .pin15, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramA10: .altFunctionSpeed( + name: "_SDRAM_A10", port: .portG, pin: .pin0, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramA11: .altFunctionSpeed( + name: "_SDRAM_A11", port: .portG, pin: .pin1, alt: .altFunc12, outputType: .pushPull, speed: .max), + + ._sdramBA0: .altFunctionSpeed( + name: "_SDRAM_BA0", port: .portG, pin: .pin4, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramBA1: .altFunctionSpeed( + name: "_SDRAM_BA1", port: .portG, pin: .pin5, alt: .altFunc12, outputType: .pushPull, speed: .max), + + ._sdramDQ0: .altFunctionSpeed( + name: "_SDRAM_DQ0", port: .portD, pin: .pin14, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramDQ1: .altFunctionSpeed( + name: "_SDRAM_DQ1", port: .portD, pin: .pin15, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramDQ2: .altFunctionSpeed( + name: "_SDRAM_DQ2", port: .portD, pin: .pin0, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramDQ3: .altFunctionSpeed( + name: "_SDRAM_DQ3", port: .portD, pin: .pin1, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramDQ4: .altFunctionSpeed( + name: "_SDRAM_DQ4", port: .portE, pin: .pin7, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramDQ5: .altFunctionSpeed( + name: "_SDRAM_DQ5", port: .portE, pin: .pin8, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramDQ6: .altFunctionSpeed( + name: "_SDRAM_DQ6", port: .portE, pin: .pin9, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramDQ7: .altFunctionSpeed( + name: "_SDRAM_DQ7", port: .portE, pin: .pin10, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramDQ8: .altFunctionSpeed( + name: "_SDRAM_DQ8", port: .portE, pin: .pin11, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramDQ9: .altFunctionSpeed( + name: "_SDRAM_DQ9", port: .portE, pin: .pin12, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramDQ10: .altFunctionSpeed( + name: "_SDRAM_DQ10", port: .portE, pin: .pin13, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramDQ11: .altFunctionSpeed( + name: "_SDRAM_DQ11", port: .portE, pin: .pin14, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramDQ12: .altFunctionSpeed( + name: "_SDRAM_DQ12", port: .portE, pin: .pin15, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramDQ13: .altFunctionSpeed( + name: "_SDRAM_DQ13", port: .portD, pin: .pin8, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramDQ14: .altFunctionSpeed( + name: "_SDRAM_DQ14", port: .portD, pin: .pin9, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramDQ15: .altFunctionSpeed( + name: "_SDRAM_DQ15", port: .portD, pin: .pin10, alt: .altFunc12, outputType: .pushPull, speed: .max), + + ._sdramSDNE0: .altFunctionSpeed( + name: "_SDRAM_SDNE0", port: .portH, pin: .pin3, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramSDNWE: .altFunctionSpeed( + name: "_SDRAM_SDNWE", port: .portH, pin: .pin5, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramSDNRAS: .altFunctionSpeed( + name: "_SDRAM_SDNRAS", port: .portF, pin: .pin11, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramSDNCAS: .altFunctionSpeed( + name: "_SDRAM_SDNCAS", port: .portG, pin: .pin15, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramSDCLK: .altFunctionSpeed( + name: "_SDRAM_SDCLK", port: .portG, pin: .pin8, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramSDCKE0: .altFunctionSpeed( + name: "_SDRAM_SDCKE0", port: .portC, pin: .pin3, alt: .altFunc12, outputType: .pushPull, speed: .max), + + ._sdramNBL0: .altFunctionSpeed( + name: "_SDRAM_NBL0", port: .portE, pin: .pin0, alt: .altFunc12, outputType: .pushPull, speed: .max), + ._sdramNBL1: .altFunctionSpeed( + name: "_SDRAM_NBL1", port: .portE, pin: .pin1, alt: .altFunc12, outputType: .pushPull, speed: .max), + + // LCD pins + ._lcdHSYNC: .altFunction(name: "_LCD_HSYNC", port: .portI, pin: .pin9, alt: .altFunc14, outputType: .pushPull), + ._lcdVSYNC: .altFunction(name: "_LCD_VSYNC", port: .portI, pin: .pin8, alt: .altFunc14, outputType: .pushPull), + ._lcdDOTCLK: .altFunction(name: "_LCD_DOTCLK", port: .portI, pin: .pin14, alt: .altFunc14, outputType: .pushPull), + ._lcdENABLE: .altFunction(name: "_LCD_ENABLE", port: .portK, pin: .pin7, alt: .altFunc14, outputType: .pushPull), + + ._lcdB0: .altFunctionSpeed( + name: "_LCD_B0", port: .portE, pin: .pin4, alt: .altFunc14, outputType: .pushPull, speed: .max), + ._lcdB1: .altFunctionSpeed( + name: "_LCD_B1", port: .portJ, pin: .pin13, alt: .altFunc14, outputType: .pushPull, speed: .max), + ._lcdB2: .altFunctionSpeed( + name: "_LCD_B2", port: .portJ, pin: .pin14, alt: .altFunc14, outputType: .pushPull, speed: .max), + ._lcdB3: .altFunctionSpeed( + name: "_LCD_B3", port: .portJ, pin: .pin15, alt: .altFunc14, outputType: .pushPull, speed: .max), + ._lcdB4: .altFunctionSpeed( + name: "_LCD_B4", port: .portG, pin: .pin12, alt: .altFunc14, outputType: .pushPull, speed: .max), + ._lcdB5: .altFunctionSpeed( + name: "_LCD_B5", port: .portK, pin: .pin4, alt: .altFunc14, outputType: .pushPull, speed: .max), + ._lcdB6: .altFunctionSpeed( + name: "_LCD_B6", port: .portK, pin: .pin5, alt: .altFunc14, outputType: .pushPull, speed: .max), + ._lcdB7: .altFunctionSpeed( + name: "_LCD_B7", port: .portK, pin: .pin6, alt: .altFunc14, outputType: .pushPull, speed: .max), + + ._lcdR0: .altFunctionSpeed( + name: "_LCD_R0", port: .portI, pin: .pin15, alt: .altFunc14, outputType: .pushPull, speed: .max), + ._lcdR1: .altFunctionSpeed( + name: "_LCD_R1", port: .portJ, pin: .pin0, alt: .altFunc14, outputType: .pushPull, speed: .max), + ._lcdR2: .altFunctionSpeed( + name: "_LCD_R2", port: .portJ, pin: .pin1, alt: .altFunc14, outputType: .pushPull, speed: .max), + ._lcdR3: .altFunctionSpeed( + name: "_LCD_R3", port: .portJ, pin: .pin2, alt: .altFunc14, outputType: .pushPull, speed: .max), + ._lcdR4: .altFunctionSpeed( + name: "_LCD_R4", port: .portJ, pin: .pin3, alt: .altFunc14, outputType: .pushPull, speed: .max), + ._lcdR5: .altFunctionSpeed( + name: "_LCD_R5", port: .portJ, pin: .pin4, alt: .altFunc14, outputType: .pushPull, speed: .max), + ._lcdR6: .altFunctionSpeed( + name: "_LCD_R6", port: .portJ, pin: .pin5, alt: .altFunc14, outputType: .pushPull, speed: .max), + ._lcdR7: .altFunctionSpeed( + name: "_LCD_R7", port: .portJ, pin: .pin6, alt: .altFunc14, outputType: .pushPull, speed: .max), + + ._lcdG0: .altFunctionSpeed( + name: "_LCD_G0", port: .portJ, pin: .pin7, alt: .altFunc14, outputType: .pushPull, speed: .max), + ._lcdG1: .altFunctionSpeed( + name: "_LCD_G1", port: .portJ, pin: .pin8, alt: .altFunc14, outputType: .pushPull, speed: .max), + ._lcdG2: .altFunctionSpeed( + name: "_LCD_G2", port: .portJ, pin: .pin9, alt: .altFunc14, outputType: .pushPull, speed: .max), + ._lcdG3: .altFunctionSpeed( + name: "_LCD_G3", port: .portJ, pin: .pin10, alt: .altFunc14, outputType: .pushPull, speed: .max), + ._lcdG4: .altFunctionSpeed( + name: "_LCD_G4", port: .portJ, pin: .pin10, alt: .altFunc14, outputType: .pushPull, speed: .max), + ._lcdG5: .altFunctionSpeed( + name: "_LCD_G5", port: .portK, pin: .pin0, alt: .altFunc14, outputType: .pushPull, speed: .max), + ._lcdG6: .altFunctionSpeed( + name: "_LCD_G6", port: .portK, pin: .pin1, alt: .altFunc14, outputType: .pushPull, speed: .max), + ._lcdG7: .altFunctionSpeed( + name: "_LCD_G7", port: .portK, pin: .pin2, alt: .altFunc14, outputType: .pushPull, speed: .max), + + // Ethernet + ._ethTXEN: .altFunctionSpeed( + name: "_ETH_TX_EN", port: .portG, pin: .pin11, alt: .altFunc11, outputType: .pushPull, speed: .max), + ._ethTXD0: .altFunctionSpeed( + name: "_ETH_TXD0", port: .portG, pin: .pin13, alt: .altFunc11, outputType: .pushPull, speed: .max), + ._ethTXD1: .altFunctionSpeed( + name: "_ETH_TXD1", port: .portG, pin: .pin14, alt: .altFunc11, outputType: .pushPull, speed: .max), + ._ethRXD0: .altFunctionSpeed( + name: "_ETH_RXD0", port: .portC, pin: .pin4, alt: .altFunc11, outputType: .pushPull, speed: .max), + ._ethRXD1: .altFunctionSpeed( + name: "_ETH_RXD1", port: .portC, pin: .pin5, alt: .altFunc11, outputType: .pushPull, speed: .max), + ._ethRXER: .altFunctionSpeed( + name: "_ETH_RXER", port: .portG, pin: .pin2, alt: .altFunc11, outputType: .pushPull, speed: .max), + ._ethCRSDV: .altFunctionSpeed( + name: "_ETH_CRS_DV", port: .portA, pin: .pin7, alt: .altFunc11, outputType: .pushPull, speed: .max), + ._ethMDC: .altFunctionSpeed( + name: "_ETH_MDC", port: .portC, pin: .pin1, alt: .altFunc11, outputType: .pushPull, speed: .max), + ._ethMDIO: .altFunctionSpeed( + name: "_ETH_MDIO", port: .portA, pin: .pin2, alt: .altFunc11, outputType: .pushPull, speed: .max), + ._ethREFCLK: .altFunctionSpeed( + name: "_ETH_REF_CLK", port: .portA, pin: .pin1, alt: .altFunc11, outputType: .pushPull, speed: .max), + + // USB HS + ._ulpiCK: .altFunctionSpeed( + name: "_ULPI_CK", port: .portA, pin: .pin5, alt: .altFunc10, outputType: .pushPull, speed: .max), + ._ulpiSTP: .altFunctionSpeed( + name: "_ULPI_STP", port: .portC, pin: .pin0, alt: .altFunc10, outputType: .pushPull, speed: .max), + ._ulpiDIR: .altFunctionSpeed( + name: "_ULPI_DIR", port: .portC, pin: .pin2, alt: .altFunc10, outputType: .pushPull, speed: .max), + ._ulpiNXT: .altFunctionSpeed( + name: "_ULPI_NXT", port: .portH, pin: .pin4, alt: .altFunc10, outputType: .pushPull, speed: .max), + ._ulpiD0: .altFunctionSpeed( + name: "_ULPI_D0", port: .portA, pin: .pin3, alt: .altFunc10, outputType: .pushPull, speed: .max), + ._ulpiD1: .altFunctionSpeed( + name: "_ULPI_D1", port: .portB, pin: .pin0, alt: .altFunc10, outputType: .pushPull, speed: .max), + ._ulpiD2: .altFunctionSpeed( + name: "_ULPI_D2", port: .portB, pin: .pin1, alt: .altFunc10, outputType: .pushPull, speed: .max), + ._ulpiD3: .altFunctionSpeed( + name: "_ULPI_D3", port: .portB, pin: .pin10, alt: .altFunc10, outputType: .pushPull, speed: .max), + ._ulpiD4: .altFunctionSpeed( + name: "_ULPI_D4", port: .portB, pin: .pin11, alt: .altFunc10, outputType: .pushPull, speed: .max), + ._ulpiD5: .altFunctionSpeed( + name: "_ULPI_D5", port: .portB, pin: .pin12, alt: .altFunc10, outputType: .pushPull, speed: .max), + ._ulpiD6: .altFunctionSpeed( + name: "_ULPI_D6", port: .portB, pin: .pin13, alt: .altFunc10, outputType: .pushPull, speed: .max), + ._ulpiD7: .altFunctionSpeed( + name: "_ULPI_D7", port: .portB, pin: .pin5, alt: .altFunc10, outputType: .pushPull, speed: .max), + + .otgHSOC: .gpioInput(name: "OTG_HS_OC", port: .portE, pin: .pin3), +] + +let GPIO_CHANNELS = 11 + +/// Initialize all GPIO pins +func initGpio() { + for (_, pin) in pinTable { + if pin.inUse { + gpioInitPin(pin: pin) + } + } +} + +/// Track which ports have been enabled +var gpioPortEnabled: [Bool] = Array(repeating: false, count: GPIO_CHANNELS) + +/// GPIO port base registers indexed by the port enum +let gpioPortBases: [GPIOA] = [ + gpioa, + gpiob, + gpioc, + gpiod, + gpioe, + gpiof, + gpiog, + gpioh, + gpioi, + gpioj, + gpiok, +] + +/// Map of GPIO pull values to hardware values +let gpioPullupMap: [UInt8] = [ + 0, // GPIO_PINPULL_NONE - See 7.4.4 in RM0390 + 1, // GPIO_PINPULL_UP + 2, // GPIO_PINPULL_DOWN +] + +extension Register { + func set(index: Int, value: GPIOA.PUPDR.PUPDR0Values) { + self.clear(index: index) + self.modify { $0.storage |= UInt32(value.rawValue) << (2 * index) } + } + func clear(index: Int) { + self.modify { $0.storage &= ~(0b11 << (2 * index)) } + } +} +extension Register { + func set(index: Int, value: GPIOA.MODER.MODER0Values) { + self.clear(index: index) + self.modify { $0.storage |= UInt32(value.rawValue) << (2 * index) } + } + func clear(index: Int) { + self.modify { $0.storage &= ~(0b11 << (2 * index)) } + } +} +extension Register { + func set(index: Int, value: GPIOA.OSPEEDR.OSPEEDR0Values) { + self.clear(index: index) + self.modify { $0.storage |= UInt32(value.rawValue) << (2 * index) } + } + func clear(index: Int) { + self.modify { $0.storage &= ~(0b11 << (2 * index)) } + } +} +extension Register { + func set(index: Int, value: Bool = true) { + guard value else { + self.clear(index: index) + return + } + self.modify { $0.storage |= 1 << (1 * index) } + } + func clear(index: Int) { + self.modify { $0.storage &= ~(1 << (1 * index)) } + } +} +extension Register { + func set(gpioPort index: Int) { + self.modify { $0.storage |= 1 << (1 * index) } + } + func clear(gpioPort index: Int) { + self.modify { $0.storage &= ~(1 << (1 * index)) } + } +} +extension Register { + func set(index: Int) { + self.write { $0.storage = UInt32(1) << Int(index) } + } + func clear(index: Int) { + self.write { $0.storage = UInt32(1) << (16 + Int(index)) } + } +} +extension GPIOA { + func afrSet(index: Int, value: GPIOA.AFRL.AFRL0Values) { + precondition(index >= 0 && index < 16) + let afrShift = (index % 8) * 4 + if index >= 8 { + self.afrh.modify { + $0.storage &= ~(0b1111 << afrShift) + $0.storage |= UInt32(value.rawValue) << afrShift + } + } else { + self.afrl.modify { + $0.storage &= ~(0b1111 << afrShift) + $0.storage |= UInt32(value.rawValue) << afrShift + } + } + } +} + +/// Disable a pin (effectively reset to POR-state) +private func gpioDisabled(pin: GPIOPin) { + let port = gpioPortBases[Int(pin.port.rawValue)] + let pinNumber = Int(pin.number.rawValue) + + port.moder.clear(index: pinNumber) // clear mode to INPUT + port.otyper.clear(index: pinNumber) // push-pull + + port.pupdr.clear(index: pinNumber) // set mode to no pulls + port.ospeedr.set(index: pinNumber, value: .init(rawValue: pin.speed.rawValue)) // set speed +} + +/// Disable a pin by its GPIO identifier +/// +/// - Parameter gpio: The GPIO identifier +func gpioDisabled(gpio: GPIO) { + if let pin = pinTable[GPIOPinID(rawValue: gpio) ?? .tableEnd] { + gpioDisabled(pin: pin) + } +} + +/// Enable clock for a specific GPIO port +/// +/// - Parameter port: The port number to enable +private func enableClockForPort(port: UInt32) { + // Enable each port at most once, and leave it enabled + precondition(port < UInt32(GPIO_CHANNELS)) + + withInterruptsDisabled { + + if !gpioPortEnabled[Int(port)] { + gpioPortEnabled[Int(port)] = true + + // Enable the clock for this port + rcc.ahb1enr.set(gpioPort: Int(port)) + + // Wait two peripheral clocks + delay(2) + } + + } +} + +/// Initialize a single GPIO pin from its configuration +/// +/// - Parameter pin: The pin configuration +func gpioInitPin(pin: GPIOPin) { + // Enable clocks to this port, and leave enabled at all times + enableClockForPort(port: pin.port.rawValue) + + // Handy pointers + let port = gpioPortBases[Int(pin.port.rawValue)] + let pinNumber = pin.number.rawValue + + // Default everything to the state at POR + gpioDisabled(pin: pin) + + // Set up the pin + switch pin.mode { + case .input: + // For a real input pin, set the pullup mode + port.pupdr.set(index: Int(pinNumber), value: .init(rawValue: gpioPullupMap[Int(pin.pull.rawValue)])) + + case .output: + port.moder.set(index: Int(pinNumber), value: .init(rawValue: 1)) // mode OUTPUT + + if pin.outputType == .pushPull { + port.otyper.clear(index: Int(pinNumber)) // push-pull + } else { + port.otyper.set(index: Int(pinNumber)) // open-drain + } + + // Set the default output value + if pin.defaultValue { + port.bsrr.set(index: Int(pinNumber)) + } else { + port.bsrr.clear(index: Int(pinNumber)) + } + + case .alternate: + port.moder.set(index: Int(pinNumber), value: .init(rawValue: 2)) // mode ALT FUNC + + // Set the alternate function + port.afrSet(index: Int(pinNumber), value: .init(rawValue: pin.altFunction.rawValue)) + + // push-pull or open-drain + port.otyper.set(index: Int(pinNumber), value: pin.outputType == .openDrain) + + case .analog: + port.moder.set(index: Int(pinNumber), value: .init(rawValue: 3)) // mode ANALOG + + case .disabled: + // Already handled by gpioDisabled + break + } +} diff --git a/stm32-lvgl/Sources/Application/Sdram.swift b/stm32-lvgl/Sources/Application/Sdram.swift new file mode 100644 index 0000000..392af04 --- /dev/null +++ b/stm32-lvgl/Sources/Application/Sdram.swift @@ -0,0 +1,109 @@ +//===----------------------------------------------------------------------===// +// +// This source file is part of the Swift open source project +// +// Copyright (c) 2025 Apple Inc. and the Swift project authors. +// Licensed under Apache License v2.0 with Runtime Library Exception +// +// See https://swift.org/LICENSE.txt for license information +// +//===----------------------------------------------------------------------===// + +import MMIO +import Registers +import Support + +let dramBase = UnsafeMutableRawPointer(bitPattern: 0xC000_0000 as UInt)! +let dramBaseAsUInt32 = UnsafeMutablePointer(bitPattern: 0xC000_0000 as UInt)! +let dramSize = 0x0080_0000 // 8 MB + +// SDRAM part is a MT48LC4M32B2B5 (Micron) +// Geometry (bits): 12 row, 8 col, 2 bank +// Data width: 16 bits +// Clock frequency: 133Mhz +// Refresh rate: 4K/64ms. + +// The SDRAM clock can only be generated as 1/2 or 1/3 the core clock, +// so we'll run it at 168 / 2 = 84MHz. Kinda pokey. +// CAS Latency will be 3. + +// Initialize the SDRAM controller. This is somewhat specific to +// the chip populated on the discovery board. +func initSdram() { + // Enable clock to the FMC + rcc.ahb3enr.modify { $0.fmcen = .Enabled } + + // Program memory device features into FMC_SDCRx + fmc.sdcr[0].write { + $0.rpipe = .Clocks1 // One clock cycle pipe delay + $0.sdclk = .Div2 // SDCLK is 1/2 HCLK + $0.cas = .Clocks3 // CAS latency 3 + $0.nb = .NB4 // 4 banks + $0.mwid = .Bits16 // 16 bits wide + $0.nr = .Bits12 // 12 row bits + $0.nc = .Bits8 // 8 col bits + } + + // Program memory timing into FMC_SDTRx + fmc.sdtr[0].write { + $0.raw.tmrd = 1 // 1 cycle + $0.raw.txsr = 5 // 6 cycles, 72ns + $0.raw.tras = 3 // 4 cycles, 48ns + $0.raw.trc = 5 // 6 cycles, 72ns + $0.raw.twr = 1 // 2 cycles for CAS=3 + $0.raw.trp = 1 // 2 cycles, 24ns + $0.raw.trcd = 1 // 2 cycles, 24ns + } + + while fmc.sdsr.read().raw.busy != 0 { /* busy wait */ } + + // Set mode bits to '001' and configure FMC_SDCMR to start clock + fmc.sdcmr.write { + $0.raw.mode = 1 // Clock config enable + $0.raw.nrfs = 1 // Number of refresh cycles + $0.raw.ctb1 = 1 // Chip is on 1st csel + } + + delay(1000) // Wait + + // Set mode bits to '010' and configure FMC_SDCMR to issue "precharge all" + fmc.sdcmr.write { + $0.raw.mode = 2 // Precharge All + $0.raw.nrfs = 1 // Number of refresh cycles + $0.raw.ctb1 = 1 // Chip is on 1st csel + } + + while fmc.sdsr.read().raw.busy != 0 { /* busy wait */ } + + // Set mode bits to '011' and configure FMC_SDCMR to start auto-refresh + fmc.sdcmr.write { + $0.raw.mode = 3 // Start auto-refresh + $0.raw.nrfs = 4 // Number of refresh cycles + $0.raw.ctb1 = 1 // Chip is on 1st csel + } + + while fmc.sdsr.read().raw.busy != 0 { /* busy wait */ } + + // Configure MRD field for specific device (latency) and issue "Load Mode Register" + fmc.sdcmr.write { + $0.raw.mode = 4 // Load Mode Register + $0.raw.nrfs = 1 // Number of refresh cycles + $0.raw.mrd = 0x230 // Mode value (2<<4) + $0.raw.ctb1 = 1 // Chip is on 1st csel + } + + while fmc.sdsr.read().raw.busy != 0 { /* busy wait */ } + + // Program refresh rate into FMC_SDRTR. 64ms spread out over 4K rows, so 15.625us/row + // with 12ns per cycle, that's 1302 cycles/row. Subtract 20 so 1282. + fmc.sdrtr.write { + $0.raw.count = 683 // Refresh rate + } + + while fmc.sdsr.read().raw.busy != 0 { /* busy wait */ } + + // Clear out memory. + for i in 0.. TouchData { + // Read device registers 0x00 through 0x06: + // 0x00 DEVIDE_MODE Device Mode (bits 4...6) + // 0x01 GEST_ID Gesture ID + // 0x02 TD_STATUS Number of touch points (bits 0...3) + // 0x03 TOUCH1_XH 1st Event Flag (bits 6...7), 1st Touch X Position Hi Bits (bits 0...3) + // 0x04 TOUCH1_XL 1st Touch X Position Lo Bits + // 0x05 TOUCH1_YH 1st Touch ID (bits 4...7), 1st Touch Y Position Hi Bits (bits 0...3) + // 0x06 TOUCH1_YL 1st Touch Y Position Lo Bits + + guard touchPanel.write(data: [0x00]) else { + print("Send failed") + return TouchData(numberOfTouchPoints: 0, x: 0, y: 0) + } + + var buf = [UInt8](repeating: 0, count: 7) + guard touchPanel.read(buffer: &buf, length: 7) else { + print("Read failed") + return TouchData(numberOfTouchPoints: 0, x: 0, y: 0) + } + + let x = Int(buf[3] & 0b1111) << 8 | Int(buf[4]) + let y = Int(buf[5] & 0b1111) << 8 | Int(buf[6]) + + // On STM32F746G discovery board, the x and y are swapped. + return TouchData(numberOfTouchPoints: Int(buf[2] & 0b1111), x: y, y: x) + } + +} diff --git a/stm32-lvgl/Sources/Application/UIAppLogic.swift b/stm32-lvgl/Sources/Application/UIAppLogic.swift new file mode 100644 index 0000000..67dbfec --- /dev/null +++ b/stm32-lvgl/Sources/Application/UIAppLogic.swift @@ -0,0 +1,139 @@ +//===----------------------------------------------------------------------===// +// +// This source file is part of the Swift open source project +// +// Copyright (c) 2025 Apple Inc. and the Swift project authors. +// Licensed under Apache License v2.0 with Runtime Library Exception +// +// See https://swift.org/LICENSE.txt for license information +// +//===----------------------------------------------------------------------===// + +import CLVGL + +// This is shared code (via a symlink) between the firmware build and the host +// SDL-based "simulator" app. No platform/firmware specific logic to stay +// portable. +enum UIAppLogic { + static var clickCount = 0 + static var button: OpaquePointer! = nil + static var buttonLabel: OpaquePointer! = nil + static var spinnerLabel: OpaquePointer! = nil + + static var frameCounter = 0 + + // Keep styles persistent for the lifetime of the application + static var style = lv_style_t() + static var labelStyle = lv_style_t() + static var gradient = lv_grad_dsc_t() + + static var widgetDemoScreen: OpaquePointer! = nil + + static func createUI() { + // Get the active screen + let screen = lv_screen_active() + + // Create a gradient background + lv_style_init(&style) + + // Create gradient colors (blue to red) + gradient.dir = LV_GRAD_DIR_VER + gradient.stops_count = 2 + gradient.stops.0.color = lv_color_make(0, 0, 0) // Black + gradient.stops.0.opa = UInt8(LV_OPA_COVER) + gradient.stops.0.frac = 0 + gradient.stops.1.color = lv_color_make(255, 0, 0) // Red + gradient.stops.1.opa = UInt8(LV_OPA_COVER) + gradient.stops.1.frac = 255 + + // Apply gradient to the style background + lv_style_set_bg_grad(&style, &gradient) + lv_style_set_bg_opa(&style, UInt8(LV_OPA_COVER)) + + // Apply the style to the screen + lv_obj_add_style(screen, &style, 0) + + // Create a button in the top right + button = lv_button_create(screen) + lv_obj_set_size(button, 120, 50) + lv_obj_align(button, LV_ALIGN_TOP_RIGHT, -10, 10) + buttonLabel = lv_label_create(button) + lv_label_set_text(buttonLabel, "Click me") + lv_obj_center(buttonLabel) + lv_obj_add_event_cb( + button, + { event in + Self.clickCount += 1 + lv_label_set_text(Self.buttonLabel, "Clicked \(Self.clickCount)") + }, LV_EVENT_CLICKED, nil) + + // Create a 'Demo' button in the bottom right + let demoButton = lv_button_create(screen) + lv_obj_set_size(demoButton, 120, 50) + lv_obj_align(demoButton, LV_ALIGN_BOTTOM_RIGHT, -10, -10) + let demoButtonLabel = lv_label_create(demoButton) + lv_label_set_text(demoButtonLabel, "Widget Demo") + lv_obj_center(demoButtonLabel) + lv_obj_add_event_cb( + demoButton, + { event in + lv_screen_load(Self.widgetDemoScreen) + }, LV_EVENT_CLICKED, nil) + + // Create a label + let label = lv_label_create(screen) + lv_label_set_text(label, "Hello LVGL!") + lv_obj_align(label, LV_ALIGN_TOP_MID, 0, 20) + + // Make the label white for better visibility + lv_style_init(&labelStyle) + lv_style_set_text_color(&labelStyle, lv_color_white()) + lv_obj_add_style(label, &labelStyle, 0) + + // Create a spinner + let spinner = lv_spinner_create(screen) + + // Set spinner size + lv_obj_set_size(spinner, 60, 60) + + // Center the spinner on screen + lv_obj_align(spinner, LV_ALIGN_CENTER, 0, 0) + + // Configure spinner animation + lv_spinner_set_anim_params(spinner, 2_000, 200) // anim time, angle + + // Create a dropdown menu + let dropdown = lv_dropdown_create(screen) + lv_dropdown_set_options(dropdown, "Option 1\nOption 2\nOption 3\nOption 4") + lv_obj_set_size(dropdown, 150, 40) + lv_obj_align(dropdown, LV_ALIGN_TOP_LEFT, 10, 10) + + // Add event handler for dropdown selection + lv_obj_add_event_cb( + dropdown, + { event in + let dropdown = lv_event_get_target_obj(event) + let selectedIndex = lv_dropdown_get_selected(dropdown) + print("Selected option \(selectedIndex)") + }, LV_EVENT_VALUE_CHANGED, nil) + + // Add a label under the spinner + spinnerLabel = lv_label_create(screen) + lv_label_set_text(spinnerLabel, "Loading...") + lv_obj_align(spinnerLabel, LV_ALIGN_BOTTOM_LEFT, 20, -20) + lv_obj_add_style(spinnerLabel, &labelStyle, 0) + + // Create a 2nd screen with the widgets demo app from LVGL, then switch back + // to the original screen. + widgetDemoScreen = lv_obj_create(nil) + lv_screen_load(widgetDemoScreen) + @_extern(c) func lv_demo_widgets() + lv_demo_widgets() + lv_screen_load(screen) + } + + static func updateFrame() { + frameCounter += 1 + lv_label_set_text(spinnerLabel, "Uptime (ms): \(uptimeInMs)\nFrames: \(frameCounter)") + } +} diff --git a/stm32-lvgl/Sources/CLVGL/include/CLVGL.h b/stm32-lvgl/Sources/CLVGL/include/CLVGL.h new file mode 100644 index 0000000..8898024 --- /dev/null +++ b/stm32-lvgl/Sources/CLVGL/include/CLVGL.h @@ -0,0 +1,12 @@ +//===----------------------------------------------------------------------===// +// +// This source file is part of the Swift open source project +// +// Copyright (c) 2025 Apple Inc. and the Swift project authors. +// Licensed under Apache License v2.0 with Runtime Library Exception +// +// See https://swift.org/LICENSE.txt for license information +// +//===----------------------------------------------------------------------===// + +#include "../../../lvgl/lvgl.h" diff --git a/stm32-lvgl/Sources/CLVGL/include/lv_conf.h b/stm32-lvgl/Sources/CLVGL/include/lv_conf.h new file mode 100644 index 0000000..ea619dc --- /dev/null +++ b/stm32-lvgl/Sources/CLVGL/include/lv_conf.h @@ -0,0 +1,1273 @@ +#ifndef LV_CONF_H +#define LV_CONF_H + +/*==================== + COLOR SETTINGS + *====================*/ + +/** Color depth: 1 (I1), 8 (L8), 16 (RGB565), 24 (RGB888), 32 (XRGB8888) */ +#define LV_COLOR_DEPTH 32 + +/********************* + * DEMO USAGE + *********************/ + +#define LV_USE_DEMO_WIDGETS 1 + +/*========================= + STDLIB WRAPPER SETTINGS + *=========================*/ + +/** Possible values + * - LV_STDLIB_BUILTIN: LVGL's built in implementation + * - LV_STDLIB_CLIB: Standard C functions, like malloc, strlen, etc + * - LV_STDLIB_MICROPYTHON: MicroPython implementation + * - LV_STDLIB_RTTHREAD: RT-Thread implementation + * - LV_STDLIB_CUSTOM: Implement the functions externally + */ +#define LV_USE_STDLIB_MALLOC LV_STDLIB_BUILTIN + +/** Possible values + * - LV_STDLIB_BUILTIN: LVGL's built in implementation + * - LV_STDLIB_CLIB: Standard C functions, like malloc, strlen, etc + * - LV_STDLIB_MICROPYTHON: MicroPython implementation + * - LV_STDLIB_RTTHREAD: RT-Thread implementation + * - LV_STDLIB_CUSTOM: Implement the functions externally + */ +#define LV_USE_STDLIB_STRING LV_STDLIB_BUILTIN + +/** Possible values + * - LV_STDLIB_BUILTIN: LVGL's built in implementation + * - LV_STDLIB_CLIB: Standard C functions, like malloc, strlen, etc + * - LV_STDLIB_MICROPYTHON: MicroPython implementation + * - LV_STDLIB_RTTHREAD: RT-Thread implementation + * - LV_STDLIB_CUSTOM: Implement the functions externally + */ +#define LV_USE_STDLIB_SPRINTF LV_STDLIB_BUILTIN + +#define LV_STDINT_INCLUDE +#define LV_STDDEF_INCLUDE +#define LV_STDBOOL_INCLUDE +#define LV_INTTYPES_INCLUDE +#define LV_LIMITS_INCLUDE +#define LV_STDARG_INCLUDE + +#if LV_USE_STDLIB_MALLOC == LV_STDLIB_BUILTIN + /** Size of memory available for `lv_malloc()` in bytes (>= 2kB) */ + #define LV_MEM_SIZE (96 * 1024U) /**< [bytes] */ + + /** Size of the memory expand for `lv_malloc()` in bytes */ + #define LV_MEM_POOL_EXPAND_SIZE 0 + + /** Set an address for the memory pool instead of allocating it as a normal array. Can be in external SRAM too. */ + #define LV_MEM_ADR 0 /**< 0: unused*/ + /* Instead of an address give a memory allocator that will be called to get a memory pool for LVGL. E.g. my_malloc */ + #if LV_MEM_ADR == 0 + #undef LV_MEM_POOL_INCLUDE + #undef LV_MEM_POOL_ALLOC + #endif +#endif /*LV_USE_STDLIB_MALLOC == LV_STDLIB_BUILTIN*/ + +/*==================== + HAL SETTINGS + *====================*/ + +/** Default display refresh, input device read and animation step period. */ +#define LV_DEF_REFR_PERIOD 33 /**< [ms] */ + +/** Default Dots Per Inch. Used to initialize default sizes such as widgets sized, style paddings. + * (Not so important, you can adjust it to modify default sizes and spaces.) */ +#define LV_DPI_DEF 130 /**< [px/inch] */ + +/*================= + * OPERATING SYSTEM + *=================*/ +/** Select operating system to use. Possible options: + * - LV_OS_NONE + * - LV_OS_PTHREAD + * - LV_OS_FREERTOS + * - LV_OS_CMSIS_RTOS2 + * - LV_OS_RTTHREAD + * - LV_OS_WINDOWS + * - LV_OS_MQX + * - LV_OS_SDL2 + * - LV_OS_CUSTOM */ +#define LV_USE_OS LV_OS_NONE + +#if LV_USE_OS == LV_OS_CUSTOM + #define LV_OS_CUSTOM_INCLUDE +#endif +#if LV_USE_OS == LV_OS_FREERTOS + /* + * Unblocking an RTOS task with a direct notification is 45% faster and uses less RAM + * than unblocking a task using an intermediary object such as a binary semaphore. + * RTOS task notifications can only be used when there is only one task that can be the recipient of the event. + */ + #define LV_USE_FREERTOS_TASK_NOTIFY 1 +#endif + +/*======================== + * RENDERING CONFIGURATION + *========================*/ + +/** Align stride of all layers and images to this bytes */ +#define LV_DRAW_BUF_STRIDE_ALIGN 1 + +/** Align start address of draw_buf addresses to this bytes*/ +#define LV_DRAW_BUF_ALIGN 4 + +/** Using matrix for transformations. + * Requirements: + * - `LV_USE_MATRIX = 1`. + * - Rendering engine needs to support 3x3 matrix transformations. */ +#define LV_DRAW_TRANSFORM_USE_MATRIX 0 + +/* If a widget has `style_opa < 255` (not `bg_opa`, `text_opa` etc) or not NORMAL blend mode + * it is buffered into a "simple" layer before rendering. The widget can be buffered in smaller chunks. + * "Transformed layers" (if `transform_angle/zoom` are set) use larger buffers + * and can't be drawn in chunks. */ + +/** The target buffer size for simple layer chunks. */ +#define LV_DRAW_LAYER_SIMPLE_BUF_SIZE (24 * 1024) /**< [bytes]*/ + +/* Limit the max allocated memory for simple and transformed layers. + * It should be at least `LV_DRAW_LAYER_SIMPLE_BUF_SIZE` sized but if transformed layers are also used + * it should be enough to store the largest widget too (width x height x 4 area). + * Set it to 0 to have no limit. */ +#define LV_DRAW_LAYER_MAX_MEMORY 0 /**< No limit by default [bytes]*/ + +/** Stack size of drawing thread. + * NOTE: If FreeType or ThorVG is enabled, it is recommended to set it to 32KB or more. + */ +#define LV_DRAW_THREAD_STACK_SIZE (8 * 1024) /**< [bytes]*/ + +#define LV_USE_DRAW_SW 1 +#if LV_USE_DRAW_SW == 1 + /* + * Selectively disable color format support in order to reduce code size. + * NOTE: some features use certain color formats internally, e.g. + * - gradients use RGB888 + * - bitmaps with transparency may use ARGB8888 + */ + #define LV_DRAW_SW_SUPPORT_RGB565 1 + #define LV_DRAW_SW_SUPPORT_RGB565A8 1 + #define LV_DRAW_SW_SUPPORT_RGB888 1 + #define LV_DRAW_SW_SUPPORT_XRGB8888 1 + #define LV_DRAW_SW_SUPPORT_ARGB8888 1 + #define LV_DRAW_SW_SUPPORT_L8 1 + #define LV_DRAW_SW_SUPPORT_AL88 1 + #define LV_DRAW_SW_SUPPORT_A8 1 + #define LV_DRAW_SW_SUPPORT_I1 1 + + /* The threshold of the luminance to consider a pixel as + * active in indexed color format */ + #define LV_DRAW_SW_I1_LUM_THRESHOLD 127 + + /** Set number of draw units. + * - > 1 requires operating system to be enabled in `LV_USE_OS`. + * - > 1 means multiple threads will render the screen in parallel. */ + #define LV_DRAW_SW_DRAW_UNIT_CNT 1 + + /** Use Arm-2D to accelerate software (sw) rendering. */ + #define LV_USE_DRAW_ARM2D_SYNC 0 + + /** Enable native helium assembly to be compiled. */ + #define LV_USE_NATIVE_HELIUM_ASM 0 + + /** + * - 0: Use a simple renderer capable of drawing only simple rectangles with gradient, images, text, and straight lines only. + * - 1: Use a complex renderer capable of drawing rounded corners, shadow, skew lines, and arcs too. */ + #define LV_DRAW_SW_COMPLEX 1 + + #if LV_DRAW_SW_COMPLEX == 1 + /** Allow buffering some shadow calculation. + * LV_DRAW_SW_SHADOW_CACHE_SIZE is the maximum shadow size to buffer, where shadow size is + * `shadow_width + radius`. Caching has LV_DRAW_SW_SHADOW_CACHE_SIZE^2 RAM cost. */ + #define LV_DRAW_SW_SHADOW_CACHE_SIZE 0 + + /** Set number of maximally-cached circle data. + * The circumference of 1/4 circle are saved for anti-aliasing. + * `radius * 4` bytes are used per circle (the most often used radiuses are saved). + * - 0: disables caching */ + #define LV_DRAW_SW_CIRCLE_CACHE_SIZE 4 + #endif + + #define LV_USE_DRAW_SW_ASM LV_DRAW_SW_ASM_NONE + + #if LV_USE_DRAW_SW_ASM == LV_DRAW_SW_ASM_CUSTOM + #define LV_DRAW_SW_ASM_CUSTOM_INCLUDE "" + #endif + + /** Enable drawing complex gradients in software: linear at an angle, radial or conical */ + #define LV_USE_DRAW_SW_COMPLEX_GRADIENTS 0 + +#endif + +/*Use TSi's aka (Think Silicon) NemaGFX */ +#define LV_USE_NEMA_GFX 0 + +#if LV_USE_NEMA_GFX + /** Select which NemaGFX HAL to use. Possible options: + * - LV_NEMA_HAL_CUSTOM + * - LV_NEMA_HAL_STM32 */ + #define LV_USE_NEMA_HAL LV_NEMA_HAL_CUSTOM + #if LV_USE_NEMA_HAL == LV_NEMA_HAL_STM32 + #define LV_NEMA_STM32_HAL_INCLUDE + #endif + + /*Enable Vector Graphics Operations. Available only if NemaVG library is present*/ + #define LV_USE_NEMA_VG 0 + #if LV_USE_NEMA_VG + /*Define application's resolution used for VG related buffer allocation */ + #define LV_NEMA_GFX_MAX_RESX 800 + #define LV_NEMA_GFX_MAX_RESY 600 + #endif +#endif + +/** Use NXP's VG-Lite GPU on iMX RTxxx platforms. */ +#define LV_USE_DRAW_VGLITE 0 + +#if LV_USE_DRAW_VGLITE + /** Enable blit quality degradation workaround recommended for screen's dimension > 352 pixels. */ + #define LV_USE_VGLITE_BLIT_SPLIT 0 + + #if LV_USE_OS + /** Use additional draw thread for VG-Lite processing. */ + #define LV_USE_VGLITE_DRAW_THREAD 1 + + #if LV_USE_VGLITE_DRAW_THREAD + /** Enable VGLite draw async. Queue multiple tasks and flash them once to the GPU. */ + #define LV_USE_VGLITE_DRAW_ASYNC 1 + #endif + #endif + + /** Enable VGLite asserts. */ + #define LV_USE_VGLITE_ASSERT 0 +#endif + +/** Use NXP's PXP on iMX RTxxx platforms. */ +#define LV_USE_PXP 0 + +#if LV_USE_PXP + /** Use PXP for drawing.*/ + #define LV_USE_DRAW_PXP 1 + + /** Use PXP to rotate display.*/ + #define LV_USE_ROTATE_PXP 0 + + #if LV_USE_DRAW_PXP && LV_USE_OS + /** Use additional draw thread for PXP processing.*/ + #define LV_USE_PXP_DRAW_THREAD 1 + #endif + + /** Enable PXP asserts. */ + #define LV_USE_PXP_ASSERT 0 +#endif + +/** Use NXP's G2D on MPU platforms. */ +#define LV_USE_DRAW_G2D 0 + +#if LV_USE_DRAW_G2D + /** Maximum number of buffers that can be stored for G2D draw unit. + * Includes the frame buffers and assets. */ + #define LV_G2D_HASH_TABLE_SIZE 50 + + #if LV_USE_OS + /** Use additional draw thread for G2D processing.*/ + #define LV_USE_G2D_DRAW_THREAD 1 + #endif + + /** Enable G2D asserts. */ + #define LV_USE_G2D_ASSERT 0 +#endif + +/** Use Renesas Dave2D on RA platforms. */ +#define LV_USE_DRAW_DAVE2D 0 + +/** Draw using cached SDL textures*/ +#define LV_USE_DRAW_SDL 0 + +/** Use VG-Lite GPU. */ +#define LV_USE_DRAW_VG_LITE 0 + +#if LV_USE_DRAW_VG_LITE + /** Enable VG-Lite custom external 'gpu_init()' function */ + #define LV_VG_LITE_USE_GPU_INIT 0 + + /** Enable VG-Lite assert. */ + #define LV_VG_LITE_USE_ASSERT 0 + + /** VG-Lite flush commit trigger threshold. GPU will try to batch these many draw tasks. */ + #define LV_VG_LITE_FLUSH_MAX_COUNT 8 + + /** Enable border to simulate shadow. + * NOTE: which usually improves performance, + * but does not guarantee the same rendering quality as the software. */ + #define LV_VG_LITE_USE_BOX_SHADOW 0 + + /** VG-Lite gradient maximum cache number. + * @note The memory usage of a single gradient image is 4K bytes. */ + #define LV_VG_LITE_GRAD_CACHE_CNT 32 + + /** VG-Lite stroke maximum cache number. */ + #define LV_VG_LITE_STROKE_CACHE_CNT 32 +#endif + +/** Accelerate blends, fills, etc. with STM32 DMA2D */ +#define LV_USE_DRAW_DMA2D 0 + +#if LV_USE_DRAW_DMA2D + #define LV_DRAW_DMA2D_HAL_INCLUDE "stm32h7xx_hal.h" + + /* if enabled, the user is required to call `lv_draw_dma2d_transfer_complete_interrupt_handler` + * upon receiving the DMA2D global interrupt + */ + #define LV_USE_DRAW_DMA2D_INTERRUPT 0 +#endif + +/** Draw using cached OpenGLES textures */ +#define LV_USE_DRAW_OPENGLES 0 + +/*======================= + * FEATURE CONFIGURATION + *=======================*/ + +/*------------- + * Logging + *-----------*/ + +/** Enable log module */ +#define LV_USE_LOG 1 +#if LV_USE_LOG + /** Set value to one of the following levels of logging detail: + * - LV_LOG_LEVEL_TRACE Log detailed information. + * - LV_LOG_LEVEL_INFO Log important events. + * - LV_LOG_LEVEL_WARN Log if something unwanted happened but didn't cause a problem. + * - LV_LOG_LEVEL_ERROR Log only critical issues, when system may fail. + * - LV_LOG_LEVEL_USER Log only custom log messages added by the user. + * - LV_LOG_LEVEL_NONE Do not log anything. */ + #define LV_LOG_LEVEL LV_LOG_LEVEL_WARN + + /** - 1: Print log with 'printf'; + * - 0: User needs to register a callback with `lv_log_register_print_cb()`. */ + #define LV_LOG_PRINTF 0 + + /** Set callback to print logs. + * E.g `my_print`. The prototype should be `void my_print(lv_log_level_t level, const char * buf)`. + * Can be overwritten by `lv_log_register_print_cb`. */ + //#define LV_LOG_PRINT_CB + + /** - 1: Enable printing timestamp; + * - 0: Disable printing timestamp. */ + #define LV_LOG_USE_TIMESTAMP 1 + + /** - 1: Print file and line number of the log; + * - 0: Do not print file and line number of the log. */ + #define LV_LOG_USE_FILE_LINE 1 + + /* Enable/disable LV_LOG_TRACE in modules that produces a huge number of logs. */ + #define LV_LOG_TRACE_MEM 1 /**< Enable/disable trace logs in memory operations. */ + #define LV_LOG_TRACE_TIMER 1 /**< Enable/disable trace logs in timer operations. */ + #define LV_LOG_TRACE_INDEV 1 /**< Enable/disable trace logs in input device operations. */ + #define LV_LOG_TRACE_DISP_REFR 1 /**< Enable/disable trace logs in display re-draw operations. */ + #define LV_LOG_TRACE_EVENT 1 /**< Enable/disable trace logs in event dispatch logic. */ + #define LV_LOG_TRACE_OBJ_CREATE 1 /**< Enable/disable trace logs in object creation (core `obj` creation plus every widget). */ + #define LV_LOG_TRACE_LAYOUT 1 /**< Enable/disable trace logs in flex- and grid-layout operations. */ + #define LV_LOG_TRACE_ANIM 1 /**< Enable/disable trace logs in animation logic. */ + #define LV_LOG_TRACE_CACHE 1 /**< Enable/disable trace logs in cache operations. */ +#endif /*LV_USE_LOG*/ + +/*------------- + * Asserts + *-----------*/ + +/* Enable assertion failures if an operation fails or invalid data is found. + * If LV_USE_LOG is enabled, an error message will be printed on failure. */ +#define LV_USE_ASSERT_NULL 1 /**< Check if the parameter is NULL. (Very fast, recommended) */ +#define LV_USE_ASSERT_MALLOC 1 /**< Checks is the memory is successfully allocated or no. (Very fast, recommended) */ +#define LV_USE_ASSERT_STYLE 0 /**< Check if the styles are properly initialized. (Very fast, recommended) */ +#define LV_USE_ASSERT_MEM_INTEGRITY 0 /**< Check the integrity of `lv_mem` after critical operations. (Slow) */ +#define LV_USE_ASSERT_OBJ 0 /**< Check the object's type and existence (e.g. not deleted). (Slow) */ + +/** Add a custom handler when assert happens e.g. to restart MCU. */ +#define LV_ASSERT_HANDLER_INCLUDE +#define LV_ASSERT_HANDLER while(1); /**< Halt by default */ + +/*------------- + * Debug + *-----------*/ + +/** 1: Draw random colored rectangles over the redrawn areas. */ +#define LV_USE_REFR_DEBUG 0 + +/** 1: Draw a red overlay for ARGB layers and a green overlay for RGB layers*/ +#define LV_USE_LAYER_DEBUG 0 + +/** 1: Adds the following behaviors for debugging: + * - Draw overlays with different colors for each draw_unit's tasks. + * - Draw index number of draw unit on white background. + * - For layers, draws index number of draw unit on black background. */ +#define LV_USE_PARALLEL_DRAW_DEBUG 0 + +/*------------- + * Others + *-----------*/ + +#define LV_ENABLE_GLOBAL_CUSTOM 0 +#if LV_ENABLE_GLOBAL_CUSTOM + /** Header to include for custom 'lv_global' function" */ + #define LV_GLOBAL_CUSTOM_INCLUDE +#endif + +/** Default cache size in bytes. + * Used by image decoders such as `lv_lodepng` to keep the decoded image in memory. + * If size is not set to 0, the decoder will fail to decode when the cache is full. + * If size is 0, the cache function is not enabled and the decoded memory will be + * released immediately after use. */ +#define LV_CACHE_DEF_SIZE 0 + +/** Default number of image header cache entries. The cache is used to store the headers of images + * The main logic is like `LV_CACHE_DEF_SIZE` but for image headers. */ +#define LV_IMAGE_HEADER_CACHE_DEF_CNT 0 + +/** Number of stops allowed per gradient. Increase this to allow more stops. + * This adds (sizeof(lv_color_t) + 1) bytes per additional stop. */ +#define LV_GRADIENT_MAX_STOPS 2 + +/** Adjust color mix functions rounding. GPUs might calculate color mix (blending) differently. + * - 0: round down, + * - 64: round up from x.75, + * - 128: round up from half, + * - 192: round up from x.25, + * - 254: round up */ +#define LV_COLOR_MIX_ROUND_OFS 0 + +/** Add 2 x 32-bit variables to each `lv_obj_t` to speed up getting style properties */ +#define LV_OBJ_STYLE_CACHE 0 + +/** Add `id` field to `lv_obj_t` */ +#define LV_USE_OBJ_ID 0 + +/** Enable support widget names*/ +#define LV_USE_OBJ_NAME 0 + +/** Automatically assign an ID when obj is created */ +#define LV_OBJ_ID_AUTO_ASSIGN LV_USE_OBJ_ID + +/** Use builtin obj ID handler functions: +* - lv_obj_assign_id: Called when a widget is created. Use a separate counter for each widget class as an ID. +* - lv_obj_id_compare: Compare the ID to decide if it matches with a requested value. +* - lv_obj_stringify_id: Return string-ified identifier, e.g. "button3". +* - lv_obj_free_id: Does nothing, as there is no memory allocation for the ID. +* When disabled these functions needs to be implemented by the user.*/ +#define LV_USE_OBJ_ID_BUILTIN 1 + +/** Use obj property set/get API. */ +#define LV_USE_OBJ_PROPERTY 0 + +/** Enable property name support. */ +#define LV_USE_OBJ_PROPERTY_NAME 1 + +/* Use VG-Lite Simulator. + * - Requires: LV_USE_THORVG_INTERNAL or LV_USE_THORVG_EXTERNAL */ +#define LV_USE_VG_LITE_THORVG 0 + +#if LV_USE_VG_LITE_THORVG + /** Enable LVGL's blend mode support */ + #define LV_VG_LITE_THORVG_LVGL_BLEND_SUPPORT 0 + + /** Enable YUV color format support */ + #define LV_VG_LITE_THORVG_YUV_SUPPORT 0 + + /** Enable Linear gradient extension support */ + #define LV_VG_LITE_THORVG_LINEAR_GRADIENT_EXT_SUPPORT 0 + + /** Enable alignment on 16 pixels */ + #define LV_VG_LITE_THORVG_16PIXELS_ALIGN 1 + + /** Buffer address alignment */ + #define LV_VG_LITE_THORVG_BUF_ADDR_ALIGN 64 + + /** Enable multi-thread render */ + #define LV_VG_LITE_THORVG_THREAD_RENDER 0 +#endif + +/* Enable the multi-touch gesture recognition feature */ +/* Gesture recognition requires the use of floats */ +#define LV_USE_GESTURE_RECOGNITION 0 + +/*===================== + * COMPILER SETTINGS + *====================*/ + +/** For big endian systems set to 1 */ +#define LV_BIG_ENDIAN_SYSTEM 0 + +/** Define a custom attribute for `lv_tick_inc` function */ +#define LV_ATTRIBUTE_TICK_INC + +/** Define a custom attribute for `lv_timer_handler` function */ +#define LV_ATTRIBUTE_TIMER_HANDLER + +/** Define a custom attribute for `lv_display_flush_ready` function */ +#define LV_ATTRIBUTE_FLUSH_READY + +/** Align VG_LITE buffers on this number of bytes. + * @note vglite_src_buf_aligned() uses this value to validate alignment of passed buffer pointers. */ +#define LV_ATTRIBUTE_MEM_ALIGN_SIZE 1 + +/** Will be added where memory needs to be aligned (with -Os data might not be aligned to boundary by default). + * E.g. __attribute__((aligned(4)))*/ +#define LV_ATTRIBUTE_MEM_ALIGN + +/** Attribute to mark large constant arrays, for example for font bitmaps */ +#define LV_ATTRIBUTE_LARGE_CONST + +/** Compiler prefix for a large array declaration in RAM */ +#define LV_ATTRIBUTE_LARGE_RAM_ARRAY + +/** Place performance critical functions into a faster memory (e.g RAM) */ +#define LV_ATTRIBUTE_FAST_MEM + +/** Export integer constant to binding. This macro is used with constants in the form of LV_ that + * should also appear on LVGL binding API such as MicroPython. */ +#define LV_EXPORT_CONST_INT(int_value) struct _silence_gcc_warning /**< The default value just prevents GCC warning */ + +/** Prefix all global extern data with this */ +#define LV_ATTRIBUTE_EXTERN_DATA + +/** Use `float` as `lv_value_precise_t` */ +#define LV_USE_FLOAT 0 + +/** Enable matrix support + * - Requires `LV_USE_FLOAT = 1` */ +#define LV_USE_MATRIX 0 + +/** Include `lvgl_private.h` in `lvgl.h` to access internal data and functions by default */ +#define LV_USE_PRIVATE_API 0 + +/*================== + * FONT USAGE + *===================*/ + +/* Montserrat fonts with ASCII range and some symbols using bpp = 4 + * https://fonts.google.com/specimen/Montserrat */ +#define LV_FONT_MONTSERRAT_8 0 +#define LV_FONT_MONTSERRAT_10 0 +#define LV_FONT_MONTSERRAT_12 0 +#define LV_FONT_MONTSERRAT_14 1 +#define LV_FONT_MONTSERRAT_16 0 +#define LV_FONT_MONTSERRAT_18 0 +#define LV_FONT_MONTSERRAT_20 0 +#define LV_FONT_MONTSERRAT_22 0 +#define LV_FONT_MONTSERRAT_24 0 +#define LV_FONT_MONTSERRAT_26 0 +#define LV_FONT_MONTSERRAT_28 0 +#define LV_FONT_MONTSERRAT_30 0 +#define LV_FONT_MONTSERRAT_32 0 +#define LV_FONT_MONTSERRAT_34 0 +#define LV_FONT_MONTSERRAT_36 0 +#define LV_FONT_MONTSERRAT_38 0 +#define LV_FONT_MONTSERRAT_40 0 +#define LV_FONT_MONTSERRAT_42 0 +#define LV_FONT_MONTSERRAT_44 0 +#define LV_FONT_MONTSERRAT_46 0 +#define LV_FONT_MONTSERRAT_48 0 + +/* Demonstrate special features */ +#define LV_FONT_MONTSERRAT_28_COMPRESSED 0 /**< bpp = 3 */ +#define LV_FONT_DEJAVU_16_PERSIAN_HEBREW 0 /**< Hebrew, Arabic, Persian letters and all their forms */ +#define LV_FONT_SIMSUN_14_CJK 0 /**< 1000 most common CJK radicals */ +#define LV_FONT_SIMSUN_16_CJK 0 /**< 1000 most common CJK radicals */ + +/** Pixel perfect monospaced fonts */ +#define LV_FONT_UNSCII_8 0 +#define LV_FONT_UNSCII_16 0 + +/** Optionally declare custom fonts here. + * + * You can use any of these fonts as the default font too and they will be available + * globally. Example: + * + * @code + * #define LV_FONT_CUSTOM_DECLARE LV_FONT_DECLARE(my_font_1) LV_FONT_DECLARE(my_font_2) + * @endcode + */ +#define LV_FONT_CUSTOM_DECLARE + +/** Always set a default font */ +#define LV_FONT_DEFAULT &lv_font_montserrat_14 + +/** Enable handling large font and/or fonts with a lot of characters. + * The limit depends on the font size, font face and bpp. + * A compiler error will be triggered if a font needs it. */ +#define LV_FONT_FMT_TXT_LARGE 0 + +/** Enables/disables support for compressed fonts. */ +#define LV_USE_FONT_COMPRESSED 0 + +/** Enable drawing placeholders when glyph dsc is not found. */ +#define LV_USE_FONT_PLACEHOLDER 1 + +/*================= + * TEXT SETTINGS + *=================*/ + +/** + * Select a character encoding for strings. + * Your IDE or editor should have the same character encoding. + * - LV_TXT_ENC_UTF8 + * - LV_TXT_ENC_ASCII + */ +#define LV_TXT_ENC LV_TXT_ENC_UTF8 + +/** While rendering text strings, break (wrap) text on these chars. */ +#define LV_TXT_BREAK_CHARS " ,.;:-_)]}" + +/** If a word is at least this long, will break wherever "prettiest". + * To disable, set to a value <= 0. */ +#define LV_TXT_LINE_BREAK_LONG_LEN 0 + +/** Minimum number of characters in a long word to put on a line before a break. + * Depends on LV_TXT_LINE_BREAK_LONG_LEN. */ +#define LV_TXT_LINE_BREAK_LONG_PRE_MIN_LEN 3 + +/** Minimum number of characters in a long word to put on a line after a break. + * Depends on LV_TXT_LINE_BREAK_LONG_LEN. */ +#define LV_TXT_LINE_BREAK_LONG_POST_MIN_LEN 3 + +/** Support bidirectional text. Allows mixing Left-to-Right and Right-to-Left text. + * The direction will be processed according to the Unicode Bidirectional Algorithm: + * https://www.w3.org/International/articles/inline-bidi-markup/uba-basics */ +#define LV_USE_BIDI 0 +#if LV_USE_BIDI + /*Set the default direction. Supported values: + *`LV_BASE_DIR_LTR` Left-to-Right + *`LV_BASE_DIR_RTL` Right-to-Left + *`LV_BASE_DIR_AUTO` detect text base direction*/ + #define LV_BIDI_BASE_DIR_DEF LV_BASE_DIR_AUTO +#endif + +/** Enable Arabic/Persian processing + * In these languages characters should be replaced with another form based on their position in the text */ +#define LV_USE_ARABIC_PERSIAN_CHARS 0 + +/*The control character to use for signaling text recoloring*/ +#define LV_TXT_COLOR_CMD "#" + +/*================== + * WIDGETS + *================*/ +/* Documentation for widgets can be found here: https://docs.lvgl.io/master/details/widgets/index.html . */ + +/** 1: Causes these widgets to be given default values at creation time. + * - lv_buttonmatrix_t: Get default maps: {"Btn1", "Btn2", "Btn3", "\n", "Btn4", "Btn5", ""}, else map not set. + * - lv_checkbox_t : String label set to "Check box", else set to empty string. + * - lv_dropdown_t : Options set to "Option 1", "Option 2", "Option 3", else no values are set. + * - lv_roller_t : Options set to "Option 1", "Option 2", "Option 3", "Option 4", "Option 5", else no values are set. + * - lv_label_t : Text set to "Text", else empty string. + * */ +#define LV_WIDGETS_HAS_DEFAULT_VALUE 1 + +#define LV_USE_ANIMIMG 1 + +#define LV_USE_ARC 1 + +#define LV_USE_BAR 1 + +#define LV_USE_BUTTON 1 + +#define LV_USE_BUTTONMATRIX 1 + +#define LV_USE_CALENDAR 1 +#if LV_USE_CALENDAR + #define LV_CALENDAR_WEEK_STARTS_MONDAY 0 + #if LV_CALENDAR_WEEK_STARTS_MONDAY + #define LV_CALENDAR_DEFAULT_DAY_NAMES {"Mo", "Tu", "We", "Th", "Fr", "Sa", "Su"} + #else + #define LV_CALENDAR_DEFAULT_DAY_NAMES {"Su", "Mo", "Tu", "We", "Th", "Fr", "Sa"} + #endif + + #define LV_CALENDAR_DEFAULT_MONTH_NAMES {"January", "February", "March", "April", "May", "June", "July", "August", "September", "October", "November", "December"} + #define LV_USE_CALENDAR_HEADER_ARROW 1 + #define LV_USE_CALENDAR_HEADER_DROPDOWN 1 + #define LV_USE_CALENDAR_CHINESE 0 +#endif /*LV_USE_CALENDAR*/ + +#define LV_USE_CANVAS 1 + +#define LV_USE_CHART 1 + +#define LV_USE_CHECKBOX 1 + +#define LV_USE_DROPDOWN 1 /**< Requires: lv_label */ + +#define LV_USE_IMAGE 1 /**< Requires: lv_label */ + +#define LV_USE_IMAGEBUTTON 1 + +#define LV_USE_KEYBOARD 1 + +#define LV_USE_LABEL 1 +#if LV_USE_LABEL + #define LV_LABEL_TEXT_SELECTION 1 /**< Enable selecting text of the label */ + #define LV_LABEL_LONG_TXT_HINT 1 /**< Store some extra info in labels to speed up drawing of very long text */ + #define LV_LABEL_WAIT_CHAR_COUNT 3 /**< The count of wait chart */ +#endif + +#define LV_USE_LED 1 + +#define LV_USE_LINE 1 + +#define LV_USE_LIST 1 + +#define LV_USE_LOTTIE 0 /**< Requires: lv_canvas, thorvg */ + +#define LV_USE_MENU 1 + +#define LV_USE_MSGBOX 1 + +#define LV_USE_ROLLER 1 /**< Requires: lv_label */ + +#define LV_USE_SCALE 1 + +#define LV_USE_SLIDER 1 /**< Requires: lv_bar */ + +#define LV_USE_SPAN 1 +#if LV_USE_SPAN + /** A line of text can contain this maximum number of span descriptors. */ + #define LV_SPAN_SNIPPET_STACK_SIZE 64 +#endif + +#define LV_USE_SPINBOX 1 + +#define LV_USE_SPINNER 1 + +#define LV_USE_SWITCH 1 + +#define LV_USE_TABLE 1 + +#define LV_USE_TABVIEW 1 + +#define LV_USE_TEXTAREA 1 /**< Requires: lv_label */ +#if LV_USE_TEXTAREA != 0 + #define LV_TEXTAREA_DEF_PWD_SHOW_TIME 1500 /**< [ms] */ +#endif + +#define LV_USE_TILEVIEW 1 + +#define LV_USE_WIN 1 + +/*================== + * THEMES + *==================*/ +/* Documentation for themes can be found here: https://docs.lvgl.io/master/details/common-widget-features/styles/style.html#themes . */ + +/** A simple, impressive and very complete theme */ +#define LV_USE_THEME_DEFAULT 1 +#if LV_USE_THEME_DEFAULT + /** 0: Light mode; 1: Dark mode */ + #define LV_THEME_DEFAULT_DARK 0 + + /** 1: Enable grow on press */ + #define LV_THEME_DEFAULT_GROW 1 + + /** Default transition time in ms. */ + #define LV_THEME_DEFAULT_TRANSITION_TIME 80 +#endif /*LV_USE_THEME_DEFAULT*/ + +/** A very simple theme that is a good starting point for a custom theme */ +#define LV_USE_THEME_SIMPLE 1 + +/** A theme designed for monochrome displays */ +#define LV_USE_THEME_MONO 1 + +/*================== + * LAYOUTS + *==================*/ +/* Documentation for layouts can be found here: https://docs.lvgl.io/master/details/common-widget-features/layouts/index.html . */ + +/** A layout similar to Flexbox in CSS. */ +#define LV_USE_FLEX 1 + +/** A layout similar to Grid in CSS. */ +#define LV_USE_GRID 1 + +/*==================== + * 3RD PARTS LIBRARIES + *====================*/ +/* Documentation for libraries can be found here: https://docs.lvgl.io/master/details/libs/index.html . */ + +/* File system interfaces for common APIs */ + +/** Setting a default driver letter allows skipping the driver prefix in filepaths. + * Documentation about how to use the below driver-identifier letters can be found at + * https://docs.lvgl.io/master/details/main-modules/fs.html#lv-fs-identifier-letters . */ +#define LV_FS_DEFAULT_DRIVER_LETTER '\0' + +/** API for fopen, fread, etc. */ +#define LV_USE_FS_STDIO 0 +#if LV_USE_FS_STDIO + #define LV_FS_STDIO_LETTER '\0' /**< Set an upper-case driver-identifier letter for this driver (e.g. 'A'). */ + #define LV_FS_STDIO_PATH "" /**< Set the working directory. File/directory paths will be appended to it. */ + #define LV_FS_STDIO_CACHE_SIZE 0 /**< >0 to cache this number of bytes in lv_fs_read() */ +#endif + +/** API for open, read, etc. */ +#define LV_USE_FS_POSIX 0 +#if LV_USE_FS_POSIX + #define LV_FS_POSIX_LETTER '\0' /**< Set an upper-case driver-identifier letter for this driver (e.g. 'A'). */ + #define LV_FS_POSIX_PATH "" /**< Set the working directory. File/directory paths will be appended to it. */ + #define LV_FS_POSIX_CACHE_SIZE 0 /**< >0 to cache this number of bytes in lv_fs_read() */ +#endif + +/** API for CreateFile, ReadFile, etc. */ +#define LV_USE_FS_WIN32 0 +#if LV_USE_FS_WIN32 + #define LV_FS_WIN32_LETTER '\0' /**< Set an upper-case driver-identifier letter for this driver (e.g. 'A'). */ + #define LV_FS_WIN32_PATH "" /**< Set the working directory. File/directory paths will be appended to it. */ + #define LV_FS_WIN32_CACHE_SIZE 0 /**< >0 to cache this number of bytes in lv_fs_read() */ +#endif + +/** API for FATFS (needs to be added separately). Uses f_open, f_read, etc. */ +#define LV_USE_FS_FATFS 0 +#if LV_USE_FS_FATFS + #define LV_FS_FATFS_LETTER '\0' /**< Set an upper-case driver-identifier letter for this driver (e.g. 'A'). */ + #define LV_FS_FATFS_PATH "" /**< Set the working directory. File/directory paths will be appended to it. */ + #define LV_FS_FATFS_CACHE_SIZE 0 /**< >0 to cache this number of bytes in lv_fs_read() */ +#endif + +/** API for memory-mapped file access. */ +#define LV_USE_FS_MEMFS 0 +#if LV_USE_FS_MEMFS + #define LV_FS_MEMFS_LETTER '\0' /**< Set an upper-case driver-identifier letter for this driver (e.g. 'A'). */ +#endif + +/** API for LittleFs. */ +#define LV_USE_FS_LITTLEFS 0 +#if LV_USE_FS_LITTLEFS + #define LV_FS_LITTLEFS_LETTER '\0' /**< Set an upper-case driver-identifier letter for this driver (e.g. 'A'). */ + #define LV_FS_LITTLEFS_PATH "" /**< Set the working directory. File/directory paths will be appended to it. */ +#endif + +/** API for Arduino LittleFs. */ +#define LV_USE_FS_ARDUINO_ESP_LITTLEFS 0 +#if LV_USE_FS_ARDUINO_ESP_LITTLEFS + #define LV_FS_ARDUINO_ESP_LITTLEFS_LETTER '\0' /**< Set an upper-case driver-identifier letter for this driver (e.g. 'A'). */ + #define LV_FS_ARDUINO_ESP_LITTLEFS_PATH "" /**< Set the working directory. File/directory paths will be appended to it. */ +#endif + +/** API for Arduino Sd. */ +#define LV_USE_FS_ARDUINO_SD 0 +#if LV_USE_FS_ARDUINO_SD + #define LV_FS_ARDUINO_SD_LETTER '\0' /**< Set an upper-case driver-identifier letter for this driver (e.g. 'A'). */ + #define LV_FS_ARDUINO_SD_PATH "" /**< Set the working directory. File/directory paths will be appended to it. */ +#endif + +/** API for UEFI */ +#define LV_USE_FS_UEFI 0 +#if LV_USE_FS_UEFI + #define LV_FS_UEFI_LETTER '\0' /**< Set an upper-case driver-identifier letter for this driver (e.g. 'A'). */ +#endif + +/** LODEPNG decoder library */ +#define LV_USE_LODEPNG 0 + +/** PNG decoder(libpng) library */ +#define LV_USE_LIBPNG 0 + +/** BMP decoder library */ +#define LV_USE_BMP 0 + +/** JPG + split JPG decoder library. + * Split JPG is a custom format optimized for embedded systems. */ +#define LV_USE_TJPGD 0 + +/** libjpeg-turbo decoder library. + * - Supports complete JPEG specifications and high-performance JPEG decoding. */ +#define LV_USE_LIBJPEG_TURBO 0 + +/** GIF decoder library */ +#define LV_USE_GIF 0 +#if LV_USE_GIF + /** GIF decoder accelerate */ + #define LV_GIF_CACHE_DECODE_DATA 0 +#endif + + +/** Decode bin images to RAM */ +#define LV_BIN_DECODER_RAM_LOAD 0 + +/** RLE decompress library */ +#define LV_USE_RLE 0 + +/** QR code library */ +#define LV_USE_QRCODE 0 + +/** Barcode code library */ +#define LV_USE_BARCODE 0 + +/** FreeType library */ +#define LV_USE_FREETYPE 0 +#if LV_USE_FREETYPE + /** Let FreeType use LVGL memory and file porting */ + #define LV_FREETYPE_USE_LVGL_PORT 0 + + /** Cache count of glyphs in FreeType, i.e. number of glyphs that can be cached. + * The higher the value, the more memory will be used. */ + #define LV_FREETYPE_CACHE_FT_GLYPH_CNT 256 +#endif + +/** Built-in TTF decoder */ +#define LV_USE_TINY_TTF 0 +#if LV_USE_TINY_TTF + /* Enable loading TTF data from files */ + #define LV_TINY_TTF_FILE_SUPPORT 0 + #define LV_TINY_TTF_CACHE_GLYPH_CNT 256 +#endif + +/** Rlottie library */ +#define LV_USE_RLOTTIE 0 + +/** Enable Vector Graphic APIs + * - Requires `LV_USE_MATRIX = 1` */ +#define LV_USE_VECTOR_GRAPHIC 0 + +/** Enable ThorVG (vector graphics library) from the src/libs folder */ +#define LV_USE_THORVG_INTERNAL 0 + +/** Enable ThorVG by assuming that its installed and linked to the project */ +#define LV_USE_THORVG_EXTERNAL 0 + +/** Use lvgl built-in LZ4 lib */ +#define LV_USE_LZ4_INTERNAL 0 + +/** Use external LZ4 library */ +#define LV_USE_LZ4_EXTERNAL 0 + +/*SVG library + * - Requires `LV_USE_VECTOR_GRAPHIC = 1` */ +#define LV_USE_SVG 0 +#define LV_USE_SVG_ANIMATION 0 +#define LV_USE_SVG_DEBUG 0 + +/** FFmpeg library for image decoding and playing videos. + * Supports all major image formats so do not enable other image decoder with it. */ +#define LV_USE_FFMPEG 0 +#if LV_USE_FFMPEG + /** Dump input information to stderr */ + #define LV_FFMPEG_DUMP_FORMAT 0 + /** Use lvgl file path in FFmpeg Player widget + * You won't be able to open URLs after enabling this feature. + * Note that FFmpeg image decoder will always use lvgl file system. */ + #define LV_FFMPEG_PLAYER_USE_LV_FS 0 +#endif + +/*================== + * OTHERS + *==================*/ +/* Documentation for several of the below items can be found here: https://docs.lvgl.io/master/details/auxiliary-modules/index.html . */ + +/** 1: Enable API to take snapshot for object */ +#define LV_USE_SNAPSHOT 0 + +/** 1: Enable system monitor component */ +#define LV_USE_SYSMON 0 +#if LV_USE_SYSMON + /** Get the idle percentage. E.g. uint32_t my_get_idle(void); */ + #define LV_SYSMON_GET_IDLE lv_os_get_idle_percent + + /** 1: Show CPU usage and FPS count. + * - Requires `LV_USE_SYSMON = 1` */ + #define LV_USE_PERF_MONITOR 0 + #if LV_USE_PERF_MONITOR + #define LV_USE_PERF_MONITOR_POS LV_ALIGN_BOTTOM_RIGHT + + /** 0: Displays performance data on the screen; 1: Prints performance data using log. */ + #define LV_USE_PERF_MONITOR_LOG_MODE 0 + #endif + + /** 1: Show used memory and memory fragmentation. + * - Requires `LV_USE_STDLIB_MALLOC = LV_STDLIB_BUILTIN` + * - Requires `LV_USE_SYSMON = 1`*/ + #define LV_USE_MEM_MONITOR 0 + #if LV_USE_MEM_MONITOR + #define LV_USE_MEM_MONITOR_POS LV_ALIGN_BOTTOM_LEFT + #endif +#endif /*LV_USE_SYSMON*/ + +/** 1: Enable runtime performance profiler */ +#define LV_USE_PROFILER 0 +#if LV_USE_PROFILER + /** 1: Enable the built-in profiler */ + #define LV_USE_PROFILER_BUILTIN 1 + #if LV_USE_PROFILER_BUILTIN + /** Default profiler trace buffer size */ + #define LV_PROFILER_BUILTIN_BUF_SIZE (16 * 1024) /**< [bytes] */ + #endif + + /** Header to include for profiler */ + #define LV_PROFILER_INCLUDE "lvgl/src/misc/lv_profiler_builtin.h" + + /** Profiler start point function */ + #define LV_PROFILER_BEGIN LV_PROFILER_BUILTIN_BEGIN + + /** Profiler end point function */ + #define LV_PROFILER_END LV_PROFILER_BUILTIN_END + + /** Profiler start point function with custom tag */ + #define LV_PROFILER_BEGIN_TAG LV_PROFILER_BUILTIN_BEGIN_TAG + + /** Profiler end point function with custom tag */ + #define LV_PROFILER_END_TAG LV_PROFILER_BUILTIN_END_TAG + + /*Enable layout profiler*/ + #define LV_PROFILER_LAYOUT 1 + + /*Enable disp refr profiler*/ + #define LV_PROFILER_REFR 1 + + /*Enable draw profiler*/ + #define LV_PROFILER_DRAW 1 + + /*Enable indev profiler*/ + #define LV_PROFILER_INDEV 1 + + /*Enable decoder profiler*/ + #define LV_PROFILER_DECODER 1 + + /*Enable font profiler*/ + #define LV_PROFILER_FONT 1 + + /*Enable fs profiler*/ + #define LV_PROFILER_FS 1 + + /*Enable style profiler*/ + #define LV_PROFILER_STYLE 0 + + /*Enable timer profiler*/ + #define LV_PROFILER_TIMER 1 + + /*Enable cache profiler*/ + #define LV_PROFILER_CACHE 1 + + /*Enable event profiler*/ + #define LV_PROFILER_EVENT 1 +#endif + +/** 1: Enable Monkey test */ +#define LV_USE_MONKEY 0 + +/** 1: Enable grid navigation */ +#define LV_USE_GRIDNAV 0 + +/** 1: Enable `lv_obj` fragment logic */ +#define LV_USE_FRAGMENT 0 + +/** 1: Support using images as font in label or span widgets */ +#define LV_USE_IMGFONT 0 + +/** 1: Enable an observer pattern implementation */ +#define LV_USE_OBSERVER 1 + +/** 1: Enable Pinyin input method + * - Requires: lv_keyboard */ +#define LV_USE_IME_PINYIN 0 +#if LV_USE_IME_PINYIN + /** 1: Use default thesaurus. + * @note If you do not use the default thesaurus, be sure to use `lv_ime_pinyin` after setting the thesaurus. */ + #define LV_IME_PINYIN_USE_DEFAULT_DICT 1 + /** Set maximum number of candidate panels that can be displayed. + * @note This needs to be adjusted according to size of screen. */ + #define LV_IME_PINYIN_CAND_TEXT_NUM 6 + + /** Use 9-key input (k9). */ + #define LV_IME_PINYIN_USE_K9_MODE 1 + #if LV_IME_PINYIN_USE_K9_MODE == 1 + #define LV_IME_PINYIN_K9_CAND_TEXT_NUM 3 + #endif /*LV_IME_PINYIN_USE_K9_MODE*/ +#endif + +/** 1: Enable file explorer. + * - Requires: lv_table */ +#define LV_USE_FILE_EXPLORER 0 +#if LV_USE_FILE_EXPLORER + /** Maximum length of path */ + #define LV_FILE_EXPLORER_PATH_MAX_LEN (128) + /** Quick access bar, 1:use, 0:do not use. + * - Requires: lv_list */ + #define LV_FILE_EXPLORER_QUICK_ACCESS 1 +#endif + +/** 1: Enable freetype font manager + * - Requires: LV_USE_FREETYPE */ +#define LV_USE_FONT_MANAGER 0 +#if LV_USE_FONT_MANAGER + +/**Font manager name max length*/ +#define LV_FONT_MANAGER_NAME_MAX_LEN 32 + +#endif + +/** Enable emulated input devices, time emulation, and screenshot compares. */ +#define LV_USE_TEST 0 +#if LV_USE_TEST + +/** Enable `lv_test_screenshot_compare`. + * Requires libpng and a few MB of extra RAM. */ +#define LV_USE_TEST_SCREENSHOT_COMPARE 0 +#endif /*LV_USE_TEST*/ + +/** Enable loading XML UIs runtime */ +#define LV_USE_XML 0 + +/*1: Enable color filter style*/ +#define LV_USE_COLOR_FILTER 0 +/*================== + * DEVICES + *==================*/ + +/** Use SDL to open window on PC and handle mouse and keyboard. */ +#define LV_USE_SDL 0 +#if LV_USE_SDL + #define LV_SDL_INCLUDE_PATH + #define LV_SDL_RENDER_MODE LV_DISPLAY_RENDER_MODE_DIRECT /**< LV_DISPLAY_RENDER_MODE_DIRECT is recommended for best performance */ + #define LV_SDL_BUF_COUNT 1 /**< 1 or 2 */ + #define LV_SDL_ACCELERATED 1 /**< 1: Use hardware acceleration*/ + #define LV_SDL_FULLSCREEN 0 /**< 1: Make the window full screen by default */ + #define LV_SDL_DIRECT_EXIT 1 /**< 1: Exit the application when all SDL windows are closed */ + #define LV_SDL_MOUSEWHEEL_MODE LV_SDL_MOUSEWHEEL_MODE_ENCODER /*LV_SDL_MOUSEWHEEL_MODE_ENCODER/CROWN*/ +#endif + +/** Use X11 to open window on Linux desktop and handle mouse and keyboard */ +#define LV_USE_X11 0 +#if LV_USE_X11 + #define LV_X11_DIRECT_EXIT 1 /**< Exit application when all X11 windows have been closed */ + #define LV_X11_DOUBLE_BUFFER 1 /**< Use double buffers for rendering */ + /* Select only 1 of the following render modes (LV_X11_RENDER_MODE_PARTIAL preferred!). */ + #define LV_X11_RENDER_MODE_PARTIAL 1 /**< Partial render mode (preferred) */ + #define LV_X11_RENDER_MODE_DIRECT 0 /**< Direct render mode */ + #define LV_X11_RENDER_MODE_FULL 0 /**< Full render mode */ +#endif + +/** Use Wayland to open a window and handle input on Linux or BSD desktops */ +#define LV_USE_WAYLAND 0 +#if LV_USE_WAYLAND + #define LV_WAYLAND_WINDOW_DECORATIONS 0 /**< Draw client side window decorations only necessary on Mutter/GNOME */ + #define LV_WAYLAND_WL_SHELL 0 /**< Use the legacy wl_shell protocol instead of the default XDG shell */ +#endif + +/** Driver for /dev/fb */ +#define LV_USE_LINUX_FBDEV 0 +#if LV_USE_LINUX_FBDEV + #define LV_LINUX_FBDEV_BSD 0 + #define LV_LINUX_FBDEV_RENDER_MODE LV_DISPLAY_RENDER_MODE_PARTIAL + #define LV_LINUX_FBDEV_BUFFER_COUNT 0 + #define LV_LINUX_FBDEV_BUFFER_SIZE 60 +#endif + +/** Use Nuttx to open window and handle touchscreen */ +#define LV_USE_NUTTX 0 + +#if LV_USE_NUTTX + #define LV_USE_NUTTX_INDEPENDENT_IMAGE_HEAP 0 + + /** Use independent image heap for default draw buffer */ + #define LV_NUTTX_DEFAULT_DRAW_BUF_USE_INDEPENDENT_IMAGE_HEAP 0 + + #define LV_USE_NUTTX_LIBUV 0 + + /** Use Nuttx custom init API to open window and handle touchscreen */ + #define LV_USE_NUTTX_CUSTOM_INIT 0 + + /** Driver for /dev/lcd */ + #define LV_USE_NUTTX_LCD 0 + #if LV_USE_NUTTX_LCD + #define LV_NUTTX_LCD_BUFFER_COUNT 0 + #define LV_NUTTX_LCD_BUFFER_SIZE 60 + #endif + + /** Driver for /dev/input */ + #define LV_USE_NUTTX_TOUCHSCREEN 0 + + /*Touchscreen cursor size in pixels(<=0: disable cursor)*/ + #define LV_NUTTX_TOUCHSCREEN_CURSOR_SIZE 0 +#endif + +/** Driver for /dev/dri/card */ +#define LV_USE_LINUX_DRM 0 + +#if LV_USE_LINUX_DRM + + /* Use the MESA GBM library to allocate DMA buffers that can be + * shared across sub-systems and libraries using the Linux DMA-BUF API. + * The GBM library aims to provide a platform independent memory management system + * it supports the major GPU vendors - This option requires linking with libgbm */ + #define LV_LINUX_DRM_GBM_BUFFERS 0 +#endif + +/** Interface for TFT_eSPI */ +#define LV_USE_TFT_ESPI 0 + +/** Driver for evdev input devices */ +#define LV_USE_EVDEV 0 + +/** Driver for libinput input devices */ +#define LV_USE_LIBINPUT 0 + +#if LV_USE_LIBINPUT + #define LV_LIBINPUT_BSD 0 + + /** Full keyboard support */ + #define LV_LIBINPUT_XKB 0 + #if LV_LIBINPUT_XKB + /** "setxkbmap -query" can help find the right values for your keyboard */ + #define LV_LIBINPUT_XKB_KEY_MAP { .rules = NULL, .model = "pc101", .layout = "us", .variant = NULL, .options = NULL } + #endif +#endif + +/* Drivers for LCD devices connected via SPI/parallel port */ +#define LV_USE_ST7735 0 +#define LV_USE_ST7789 0 +#define LV_USE_ST7796 0 +#define LV_USE_ILI9341 0 + +#if (LV_USE_ST7735 | LV_USE_ST7789 | LV_USE_ST7796 | LV_USE_ILI9341) + #define LV_USE_GENERIC_MIPI 1 +#else + #define LV_USE_GENERIC_MIPI 0 +#endif + +/** Driver for Renesas GLCD */ +#define LV_USE_RENESAS_GLCDC 0 + +/** Driver for ST LTDC */ +#define LV_USE_ST_LTDC 0 +#if LV_USE_ST_LTDC + /* Only used for partial. */ + #define LV_ST_LTDC_USE_DMA2D_FLUSH 0 +#endif + +/** LVGL Windows backend */ +#define LV_USE_WINDOWS 0 + +/** LVGL UEFI backend */ +#define LV_USE_UEFI 0 +#if LV_USE_UEFI + #define LV_USE_UEFI_INCLUDE "myefi.h" /**< Header that hides the actual framework (EDK2, gnu-efi, ...) */ + #define LV_UEFI_USE_MEMORY_SERVICES 0 /**< Use the memory functions from the boot services table */ +#endif + +/** Use OpenGL to open window on PC and handle mouse and keyboard */ +#define LV_USE_OPENGLES 0 +#if LV_USE_OPENGLES + #define LV_USE_OPENGLES_DEBUG 1 /**< Enable or disable debug for opengles */ +#endif + +/** QNX Screen display and input drivers */ +#define LV_USE_QNX 0 +#if LV_USE_QNX + #define LV_QNX_BUF_COUNT 1 /**< 1 or 2 */ +#endif + +#endif /*LV_CONF_H*/ diff --git a/stm32-lvgl/Sources/CLVGL/include/module.modulemap b/stm32-lvgl/Sources/CLVGL/include/module.modulemap new file mode 100644 index 0000000..0961fcc --- /dev/null +++ b/stm32-lvgl/Sources/CLVGL/include/module.modulemap @@ -0,0 +1,15 @@ +//===----------------------------------------------------------------------===// +// +// This source file is part of the Swift open source project +// +// Copyright (c) 2025 Apple Inc. and the Swift project authors. +// Licensed under Apache License v2.0 with Runtime Library Exception +// +// See https://swift.org/LICENSE.txt for license information +// +//===----------------------------------------------------------------------===// + +module CLVGL [system] { + header "CLVGL.h" + export * +} diff --git a/stm32-lvgl/Sources/HostSDLApp/Main.swift b/stm32-lvgl/Sources/HostSDLApp/Main.swift new file mode 100644 index 0000000..58f2a20 --- /dev/null +++ b/stm32-lvgl/Sources/HostSDLApp/Main.swift @@ -0,0 +1,127 @@ +//===----------------------------------------------------------------------===// +// +// This source file is part of the Swift open source project +// +// Copyright (c) 2025 Apple Inc. and the Swift project authors. +// Licensed under Apache License v2.0 with Runtime Library Exception +// +// See https://swift.org/LICENSE.txt for license information +// +//===----------------------------------------------------------------------===// + +import CLVGL +import Foundation +import SDL + +let drawSize: (width: Int32, height: Int32) = (width: 480, height: 272) +let windowScale: Int32 = 2 + +var clickCount = 0 +var button: OpaquePointer! = nil +var buttonLabel: OpaquePointer! = nil +var uptimeInMs: Int = 0 + +var texture: OpaquePointer! = nil +var mouseEvent = SDL_Event() + +@main +struct Main { + static func main() { + lv_init() + lv_log_register_print_cb({ level, buf in print(String(cString: buf!), terminator: "") }) + lv_tick_set_cb({ UInt32(uptimeInMs) }) + + let bufSize: UInt32 = UInt32(drawSize.width * drawSize.height * 4) + let buf1 = UnsafeMutableRawPointer.allocate(byteCount: Int(bufSize), alignment: 16) + let buf2 = UnsafeMutableRawPointer.allocate(byteCount: Int(bufSize), alignment: 16) + + let disp = lv_display_create(Int32(drawSize.width), Int32(drawSize.height))! + lv_display_set_color_format(disp, LV_COLOR_FORMAT_ARGB8888) + lv_display_set_buffers(disp, buf1, buf2, bufSize, LV_DISPLAY_RENDER_MODE_FULL) + lv_display_set_flush_cb( + disp, + { disp, _, bufferToShow in + _ = SDL_UpdateTexture(texture, nil, bufferToShow, Int32(drawSize.width * 4)) + lv_display_flush_ready(disp) + }) + + let touch = lv_indev_create() + lv_indev_set_type(touch, LV_INDEV_TYPE_POINTER) + lv_indev_set_read_cb( + touch, + { indev, data in + if mouseEvent.type == SDL_MOUSEBUTTONDOWN.rawValue { + data!.pointee.point.x = Int32(mouseEvent.button.x) / windowScale + data!.pointee.point.y = Int32(mouseEvent.button.y) / windowScale + data!.pointee.state = LV_INDEV_STATE_PRESSED + } else if mouseEvent.type == SDL_MOUSEMOTION.rawValue && mouseEvent.motion.state & 0x1 != 0 { + data!.pointee.point.x = Int32(mouseEvent.motion.x) / windowScale + data!.pointee.point.y = Int32(mouseEvent.motion.y) / windowScale + data!.pointee.state = LV_INDEV_STATE_PRESSED + } else { + data!.pointee.state = LV_INDEV_STATE_RELEASED + } + }) + + UIAppLogic.createUI() + + // Initialize SDL video systems + guard SDL_Init(SDL_INIT_VIDEO) == 0 else { + fatalError("SDL could not initialize! SDL_Error: \(String(cString: SDL_GetError()))") + } + + // Create a window at the center of the screen + let window = SDL_CreateWindow( + "SDL Window", Int32(SDL_WINDOWPOS_CENTERED_MASK), + Int32(SDL_WINDOWPOS_CENTERED_MASK), drawSize.width * windowScale, drawSize.height * windowScale, + SDL_WINDOW_SHOWN.rawValue) + + // Create renderer + guard let renderer = SDL_CreateRenderer(window, -1, SDL_RENDERER_ACCELERATED.rawValue) else { + fatalError("Renderer could not be created! SDL_Error: \(String(cString: SDL_GetError()))") + } + + // Create texture + texture = SDL_CreateTexture( + renderer, SDL_PIXELFORMAT_ARGB8888.rawValue, + Int32(SDL_TEXTUREACCESS_STREAMING.rawValue), drawSize.width, drawSize.height) + guard texture != nil else { + fatalError("Texture could not be created! SDL_Error: \(String(cString: SDL_GetError()))") + } + + var event = SDL_Event() + var frameCounter = 0 + let startTime = Date() + mainLoop: while true { + uptimeInMs = Int(Date().timeIntervalSince(startTime) * 1000) + let delay = lv_timer_handler() + + // Clear renderer, copy texture to renderer, and present + SDL_RenderClear(renderer) + SDL_RenderCopy(renderer, texture, nil, nil) + SDL_RenderPresent(renderer) + + while SDL_PollEvent(&event) > 0 { + if event.type == SDL_MOUSEBUTTONDOWN.rawValue { + mouseEvent = event + } + if event.type == SDL_MOUSEBUTTONUP.rawValue { + mouseEvent = event + } + if event.type == SDL_MOUSEMOTION.rawValue { + mouseEvent = event + } + if event.type == SDL_QUIT.rawValue { + break mainLoop + } + } + + SDL_Delay(delay) + + UIAppLogic.updateFrame() + } + + SDL_DestroyWindow(window) + SDL_Quit() + } +} diff --git a/stm32-lvgl/Sources/HostSDLApp/UIAppLogic.swift b/stm32-lvgl/Sources/HostSDLApp/UIAppLogic.swift new file mode 120000 index 0000000..a5ab221 --- /dev/null +++ b/stm32-lvgl/Sources/HostSDLApp/UIAppLogic.swift @@ -0,0 +1 @@ +../Application/UIAppLogic.swift \ No newline at end of file diff --git a/stm32-lvgl/Sources/Registers/DBGMCU.swift b/stm32-lvgl/Sources/Registers/DBGMCU.swift new file mode 100644 index 0000000..c1a7a0b --- /dev/null +++ b/stm32-lvgl/Sources/Registers/DBGMCU.swift @@ -0,0 +1,153 @@ +// Generated by svd2swift. + +import MMIO + +/// Debug support +@RegisterBlock +public struct DBGMCU { + /// IDCODE + @RegisterBlock(offset: 0x0) + public var idcode: Register + + /// Control Register + @RegisterBlock(offset: 0x4) + public var cr: Register + + /// Debug MCU APB1 Freeze registe + @RegisterBlock(offset: 0x8) + public var apb1_fz: Register + + /// Debug MCU APB2 Freeze registe + @RegisterBlock(offset: 0xc) + public var apb2_fz: Register +} + +extension DBGMCU { + /// IDCODE + @Register(bitWidth: 32) + public struct IDCODE { + /// DEV_ID + @ReadOnly(bits: 0..<12) + public var dev_id: DEV_ID + + /// REV_ID + @ReadOnly(bits: 16..<32) + public var rev_id: REV_ID + } + + /// Control Register + @Register(bitWidth: 32) + public struct CR { + /// DBG_SLEEP + @ReadWrite(bits: 0..<1) + public var dbg_sleep: DBG_SLEEP + + /// DBG_STOP + @ReadWrite(bits: 1..<2) + public var dbg_stop: DBG_STOP + + /// DBG_STANDBY + @ReadWrite(bits: 2..<3) + public var dbg_standby: DBG_STANDBY + + /// TRACE_IOEN + @ReadWrite(bits: 5..<6) + public var trace_ioen: TRACE_IOEN + + /// TRACE_MODE + @ReadWrite(bits: 6..<8) + public var trace_mode: TRACE_MODE + } + + /// Debug MCU APB1 Freeze registe + @Register(bitWidth: 32) + public struct APB1_FZ { + /// DBG_TIM2_STOP + @ReadWrite(bits: 0..<1) + public var dbg_tim2_stop: DBG_TIM2_STOP + + /// DBG_TIM3 _STOP + @ReadWrite(bits: 1..<2) + public var dbg_tim3_stop: DBG_TIM3_STOP + + /// DBG_TIM4_STOP + @ReadWrite(bits: 2..<3) + public var dbg_tim4_stop: DBG_TIM4_STOP + + /// DBG_TIM5_STOP + @ReadWrite(bits: 3..<4) + public var dbg_tim5_stop: DBG_TIM5_STOP + + /// DBG_TIM6_STOP + @ReadWrite(bits: 4..<5) + public var dbg_tim6_stop: DBG_TIM6_STOP + + /// DBG_TIM7_STOP + @ReadWrite(bits: 5..<6) + public var dbg_tim7_stop: DBG_TIM7_STOP + + /// DBG_TIM12_STOP + @ReadWrite(bits: 6..<7) + public var dbg_tim12_stop: DBG_TIM12_STOP + + /// DBG_TIM13_STOP + @ReadWrite(bits: 7..<8) + public var dbg_tim13_stop: DBG_TIM13_STOP + + /// DBG_TIM14_STOP + @ReadWrite(bits: 8..<9) + public var dbg_tim14_stop: DBG_TIM14_STOP + + /// DBG_WWDG_STOP + @ReadWrite(bits: 11..<12) + public var dbg_wwdg_stop: DBG_WWDG_STOP + + /// DBG_IWDEG_STOP + @ReadWrite(bits: 12..<13) + public var dbg_iwdg_stop: DBG_IWDG_STOP + + /// DBG_J2C1_SMBUS_TIMEOUT + @ReadWrite(bits: 21..<22) + public var dbg_j2c1_smbus_timeout: DBG_J2C1_SMBUS_TIMEOUT + + /// DBG_J2C2_SMBUS_TIMEOUT + @ReadWrite(bits: 22..<23) + public var dbg_j2c2_smbus_timeout: DBG_J2C2_SMBUS_TIMEOUT + + /// DBG_J2C3SMBUS_TIMEOUT + @ReadWrite(bits: 23..<24) + public var dbg_j2c3smbus_timeout: DBG_J2C3SMBUS_TIMEOUT + + /// DBG_CAN1_STOP + @ReadWrite(bits: 25..<26) + public var dbg_can1_stop: DBG_CAN1_STOP + + /// DBG_CAN2_STOP + @ReadWrite(bits: 26..<27) + public var dbg_can2_stop: DBG_CAN2_STOP + } + + /// Debug MCU APB2 Freeze registe + @Register(bitWidth: 32) + public struct APB2_FZ { + /// TIM1 counter stopped when core is halted + @ReadWrite(bits: 0..<1) + public var dbg_tim1_stop: DBG_TIM1_STOP + + /// TIM8 counter stopped when core is halted + @ReadWrite(bits: 1..<2) + public var dbg_tim8_stop: DBG_TIM8_STOP + + /// TIM9 counter stopped when core is halted + @ReadWrite(bits: 16..<17) + public var dbg_tim9_stop: DBG_TIM9_STOP + + /// TIM10 counter stopped when core is halted + @ReadWrite(bits: 17..<18) + public var dbg_tim10_stop: DBG_TIM10_STOP + + /// TIM11 counter stopped when core is halted + @ReadWrite(bits: 18..<19) + public var dbg_tim11_stop: DBG_TIM11_STOP + } +} diff --git a/stm32-lvgl/Sources/Registers/Device.swift b/stm32-lvgl/Sources/Registers/Device.swift new file mode 100644 index 0000000..f62c96b --- /dev/null +++ b/stm32-lvgl/Sources/Registers/Device.swift @@ -0,0 +1,81 @@ +// Generated by svd2swift. + +import MMIO + +/// Debug support +public let dbgmcu = DBGMCU(unsafeAddress: 0xe0042000) + +/// FLASH +public let flash = FLASH(unsafeAddress: 0x40023c00) + +/// Flexible memory controller +public let fmc = FMC(unsafeAddress: 0xa0000000) + +/// General-purpose I/Os +public let gpioa = GPIOA(unsafeAddress: 0x40020000) + +/// General-purpose I/Os +public let gpiob = GPIOB(unsafeAddress: 0x40020400) + +/// General-purpose I/Os +public let gpioc = GPIOC(unsafeAddress: 0x40020800) + +/// General-purpose I/Os +public let gpiod = GPIOD(unsafeAddress: 0x40020c00) + +/// General-purpose I/Os +public let gpioe = GPIOE(unsafeAddress: 0x40021000) + +/// General-purpose I/Os +public let gpiof = GPIOF(unsafeAddress: 0x40021400) + +/// General-purpose I/Os +public let gpiog = GPIOG(unsafeAddress: 0x40021800) + +/// General-purpose I/Os +public let gpioh = GPIOH(unsafeAddress: 0x40021c00) + +/// General-purpose I/Os +public let gpioi = GPIOI(unsafeAddress: 0x40022000) + +/// General-purpose I/Os +public let gpioj = GPIOJ(unsafeAddress: 0x40022400) + +/// General-purpose I/Os +public let gpiok = GPIOK(unsafeAddress: 0x40022800) + +/// Inter-integrated circuit +public let i2c1 = I2C1(unsafeAddress: 0x40005400) + +/// Inter-integrated circuit +public let i2c2 = I2C2(unsafeAddress: 0x40005800) + +/// Inter-integrated circuit +public let i2c3 = I2C3(unsafeAddress: 0x40005c00) + +/// Inter-integrated circuit +public let i2c4 = I2C4(unsafeAddress: 0x40006000) + +/// LCD-TFT Controller +public let ltdc = LTDC(unsafeAddress: 0x40016800) + +/// Nested Vectored Interrupt Controller +public let nvic = NVIC(unsafeAddress: 0xe000e100) + +/// Power control +public let pwr = PWR(unsafeAddress: 0x40007000) + +/// Reset and clock control +public let rcc = RCC(unsafeAddress: 0x40023800) + +/// System control block +public let scb = SCB(unsafeAddress: 0xe000ed00) + +/// SysTick timer +public let stk = STK(unsafeAddress: 0xe000e010) + +/// System configuration controller +public let syscfg = SYSCFG(unsafeAddress: 0x40013800) + +/// Universal synchronous asynchronous receiver transmitter +public let usart1 = USART1(unsafeAddress: 0x40011000) diff --git a/stm32-lvgl/Sources/Registers/FLASH.swift b/stm32-lvgl/Sources/Registers/FLASH.swift new file mode 100644 index 0000000..bfceb4f --- /dev/null +++ b/stm32-lvgl/Sources/Registers/FLASH.swift @@ -0,0 +1,469 @@ +// Generated by svd2swift. + +import MMIO + +/// FLASH +@RegisterBlock +public struct FLASH { + /// Flash access control register + @RegisterBlock(offset: 0x0) + public var acr: Register + + /// Flash key register + @RegisterBlock(offset: 0x4) + public var keyr: Register + + /// Flash option key register + @RegisterBlock(offset: 0x8) + public var optkeyr: Register + + /// Status register + @RegisterBlock(offset: 0xc) + public var sr: Register + + /// Control register + @RegisterBlock(offset: 0x10) + public var cr: Register + + /// Flash option control register + @RegisterBlock(offset: 0x14) + public var optcr: Register + + /// Flash option control register 1 + @RegisterBlock(offset: 0x18) + public var optcr1: Register +} + +extension FLASH { + /// Flash access control register + @Register(bitWidth: 32) + public struct ACR { + /// Latency + @ReadWrite(bits: 0..<4, as: LATENCYValues.self) + public var latency: LATENCY + + /// Prefetch enable + @ReadWrite(bits: 8..<9, as: PRFTENValues.self) + public var prften: PRFTEN + + /// ART Accelerator Enable + @ReadWrite(bits: 9..<10, as: ARTENValues.self) + public var arten: ARTEN + + /// ART Accelerator reset + @ReadWrite(bits: 11..<12, as: ARTRSTValues.self) + public var artrst: ARTRST + } + + /// Flash key register + @Register(bitWidth: 32) + public struct KEYR { + /// FPEC key + @WriteOnly(bits: 0..<32) + public var key: KEY + } + + /// Flash option key register + @Register(bitWidth: 32) + public struct OPTKEYR { + /// Option byte key + @WriteOnly(bits: 0..<32) + public var optkeyr_field: OPTKEYR_FIELD + } + + /// Status register + @Register(bitWidth: 32) + public struct SR { + /// End of operation + @ReadWrite(bits: 0..<1) + public var eop: EOP + + /// Operation error + @ReadWrite(bits: 1..<2) + public var operr: OPERR + + /// Write protection error + @ReadWrite(bits: 4..<5) + public var wrperr: WRPERR + + /// Programming alignment error + @ReadWrite(bits: 5..<6) + public var pgaerr: PGAERR + + /// Programming parallelism error + @ReadWrite(bits: 6..<7) + public var pgperr: PGPERR + + /// Programming sequence error + @ReadWrite(bits: 7..<8) + public var erserr: ERSERR + + /// Busy + @ReadOnly(bits: 16..<17) + public var bsy: BSY + } + + /// Control register + @Register(bitWidth: 32) + public struct CR { + /// Programming + @ReadWrite(bits: 0..<1, as: PGValues.self) + public var pg: PG + + /// Sector Erase + @ReadWrite(bits: 1..<2, as: SERValues.self) + public var ser: SER + + /// Mass Erase of sectors 0 to 11 + @ReadWrite(bits: 2..<3, as: MERValues.self) + public var mer: MER + + /// Sector number + @ReadWrite(bits: 3..<7) + public var snb: SNB + + /// Program size + @ReadWrite(bits: 8..<10, as: PSIZEValues.self) + public var psize: PSIZE + + /// Start + @ReadWrite(bits: 16..<17, as: STRTValues.self) + public var strt: STRT + + /// End of operation interrupt enable + @ReadWrite(bits: 24..<25, as: EOPIEValues.self) + public var eopie: EOPIE + + /// Error interrupt enable + @ReadWrite(bits: 25..<26, as: ERRIEValues.self) + public var errie: ERRIE + + /// Lock + @ReadWrite(bits: 31..<32, as: LOCKValues.self) + public var lock: LOCK + } + + /// Flash option control register + @Register(bitWidth: 32) + public struct OPTCR { + /// Option lock + @ReadWrite(bits: 0..<1) + public var optlock: OPTLOCK + + /// Option start + @ReadWrite(bits: 1..<2) + public var optstrt: OPTSTRT + + /// BOR reset Level + @ReadWrite(bits: 2..<4) + public var bor_lev: BOR_LEV + + /// User option bytes + @ReadWrite(bits: 4..<5) + public var wwdg_sw: WWDG_SW + + /// User option bytes + @ReadWrite(bits: 5..<6) + public var iwdg_sw: IWDG_SW + + /// User option bytes + @ReadWrite(bits: 6..<7) + public var nrst_stop: nRST_STOP + + /// User option bytes + @ReadWrite(bits: 7..<8) + public var nrst_stdby: nRST_STDBY + + /// Read protect + @ReadWrite(bits: 8..<16) + public var rdp: RDP + + /// Not write protect + @ReadWrite(bits: 16..<24) + public var nwrp: nWRP + + /// Independent watchdog counter freeze in standby mode + @ReadWrite(bits: 30..<31) + public var iwdg_stdby: IWDG_STDBY + + /// Independent watchdog counter freeze in Stop mode + @ReadWrite(bits: 31..<32) + public var iwdg_stop: IWDG_STOP + } + + /// Flash option control register 1 + @Register(bitWidth: 32) + public struct OPTCR1 { + /// Boot base address when Boot pin =0 + @ReadWrite(bits: 0..<16) + public var boot_add0: BOOT_ADD0 + + /// Boot base address when Boot pin =1 + @ReadWrite(bits: 16..<32) + public var boot_add1: BOOT_ADD1 + } +} + +extension FLASH.ACR { + public struct LATENCYValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 4 + + /// 0 wait states + public static let WS0 = Self(rawValue: 0x0) + + /// 1 wait states + public static let WS1 = Self(rawValue: 0x1) + + /// 2 wait states + public static let WS2 = Self(rawValue: 0x2) + + /// 3 wait states + public static let WS3 = Self(rawValue: 0x3) + + /// 4 wait states + public static let WS4 = Self(rawValue: 0x4) + + /// 5 wait states + public static let WS5 = Self(rawValue: 0x5) + + /// 6 wait states + public static let WS6 = Self(rawValue: 0x6) + + /// 7 wait states + public static let WS7 = Self(rawValue: 0x7) + + /// 8 wait states + public static let WS8 = Self(rawValue: 0x8) + + /// 9 wait states + public static let WS9 = Self(rawValue: 0x9) + + /// 10 wait states + public static let WS10 = Self(rawValue: 0xa) + + /// 11 wait states + public static let WS11 = Self(rawValue: 0xb) + + /// 12 wait states + public static let WS12 = Self(rawValue: 0xc) + + /// 13 wait states + public static let WS13 = Self(rawValue: 0xd) + + /// 14 wait states + public static let WS14 = Self(rawValue: 0xe) + + /// 15 wait states + public static let WS15 = Self(rawValue: 0xf) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FLASH.ACR { + public struct PRFTENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Prefetch is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Prefetch is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FLASH.ACR { + public struct ARTENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// ART Accelerator is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// ART Accelerator is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FLASH.ACR { + public struct ARTRSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Accelerator is not reset + public static let NotReset = Self(rawValue: 0x0) + + /// Accelerator is reset + public static let Reset = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FLASH.CR { + public struct PGValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Flash programming activated + public static let Program = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FLASH.CR { + public struct SERValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Erase activated for selected sector + public static let SectorErase = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FLASH.CR { + public struct MERValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Erase activated for all user sectors + public static let MassErase = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FLASH.CR { + public struct PSIZEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// Program x8 + public static let PSIZE8 = Self(rawValue: 0x0) + + /// Program x16 + public static let PSIZE16 = Self(rawValue: 0x1) + + /// Program x32 + public static let PSIZE32 = Self(rawValue: 0x2) + + /// Program x64 + public static let PSIZE64 = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FLASH.CR { + public struct STRTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Trigger an erase operation + public static let Start = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FLASH.CR { + public struct EOPIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// End of operation interrupt disabled + public static let Disabled = Self(rawValue: 0x0) + + /// End of operation interrupt enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FLASH.CR { + public struct ERRIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Error interrupt generation disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Error interrupt generation enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FLASH.CR { + public struct LOCKValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// FLASH_CR register is unlocked + public static let Unlocked = Self(rawValue: 0x0) + + /// FLASH_CR register is locked + public static let Locked = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} diff --git a/stm32-lvgl/Sources/Registers/FMC.swift b/stm32-lvgl/Sources/Registers/FMC.swift new file mode 100644 index 0000000..6e207f2 --- /dev/null +++ b/stm32-lvgl/Sources/Registers/FMC.swift @@ -0,0 +1,1611 @@ +// Generated by svd2swift. + +import MMIO + +/// Flexible memory controller +@RegisterBlock +public struct FMC { + /// SRAM/NOR-Flash chip-select control register 1 + @RegisterBlock(offset: 0x0) + public var bcr1: Register + + /// SRAM/NOR-Flash chip-select timing register 1 + @RegisterBlock(offset: 0x4, stride: 0x8, count: 4) + public var btr: RegisterArray + + /// SRAM/NOR-Flash chip-select control register 2 + @RegisterBlock(offset: 0x8, stride: 0x8, count: 3) + public var bcr: RegisterArray + + /// PC Card/NAND Flash control register + @RegisterBlock(offset: 0x80) + public var pcr: Register + + /// FIFO status and interrupt register + @RegisterBlock(offset: 0x84) + public var sr: Register + + /// Common memory space timing register + @RegisterBlock(offset: 0x88) + public var pmem: Register + + /// Attribute memory space timing register + @RegisterBlock(offset: 0x8c) + public var patt: Register + + /// ECC result register + @RegisterBlock(offset: 0x94) + public var eccr: Register + + /// SRAM/NOR-Flash write timing registers 1 + @RegisterBlock(offset: 0x104, stride: 0x8, count: 4) + public var bwtr: RegisterArray + + /// SDRAM Control Register 1 + @RegisterBlock(offset: 0x140, stride: 0x4, count: 2) + public var sdcr: RegisterArray + + /// SDRAM Timing register 1 + @RegisterBlock(offset: 0x148, stride: 0x4, count: 2) + public var sdtr: RegisterArray + + /// SDRAM Command Mode register + @RegisterBlock(offset: 0x150) + public var sdcmr: Register + + /// SDRAM Refresh Timer register + @RegisterBlock(offset: 0x154) + public var sdrtr: Register + + /// SDRAM Status register + @RegisterBlock(offset: 0x158) + public var sdsr: Register +} + +extension FMC { + /// SRAM/NOR-Flash chip-select control register 1 + @Register(bitWidth: 32) + public struct BCR1 { + /// CCLKEN + @ReadWrite(bits: 20..<21, as: CCLKENValues.self) + public var cclken: CCLKEN + + /// CBURSTRW + @ReadWrite(bits: 19..<20, as: CBURSTRWValues.self) + public var cburstrw: CBURSTRW + + /// ASYNCWAIT + @ReadWrite(bits: 15..<16, as: ASYNCWAITValues.self) + public var asyncwait: ASYNCWAIT + + /// EXTMOD + @ReadWrite(bits: 14..<15, as: EXTMODValues.self) + public var extmod: EXTMOD + + /// WAITEN + @ReadWrite(bits: 13..<14, as: WAITENValues.self) + public var waiten: WAITEN + + /// WREN + @ReadWrite(bits: 12..<13, as: WRENValues.self) + public var wren: WREN + + /// WAITCFG + @ReadWrite(bits: 11..<12, as: WAITCFGValues.self) + public var waitcfg: WAITCFG + + /// WAITPOL + @ReadWrite(bits: 9..<10, as: WAITPOLValues.self) + public var waitpol: WAITPOL + + /// BURSTEN + @ReadWrite(bits: 8..<9, as: BURSTENValues.self) + public var bursten: BURSTEN + + /// FACCEN + @ReadWrite(bits: 6..<7, as: FACCENValues.self) + public var faccen: FACCEN + + /// MWID + @ReadWrite(bits: 4..<6, as: MWIDValues.self) + public var mwid: MWID + + /// MTYP + @ReadWrite(bits: 2..<4, as: MTYPValues.self) + public var mtyp: MTYP + + /// MUXEN + @ReadWrite(bits: 1..<2, as: MUXENValues.self) + public var muxen: MUXEN + + /// MBKEN + @ReadWrite(bits: 0..<1, as: MBKENValues.self) + public var mbken: MBKEN + + /// WRAPMOD + @ReadWrite(bits: 10..<11) + public var wrapmod: WRAPMOD + + /// Write FIFO disable + @ReadWrite(bits: 21..<22, as: WFDISValues.self) + public var wfdis: WFDIS + + /// CRAM page size + @ReadWrite(bits: 16..<19, as: CPSIZEValues.self) + public var cpsize: CPSIZE + } + + /// SRAM/NOR-Flash chip-select timing register 1 + @Register(bitWidth: 32) + public struct BTR { + /// ACCMOD + @ReadWrite(bits: 28..<30, as: ACCMODValues.self) + public var accmod: ACCMOD + + /// DATLAT + @ReadWrite(bits: 24..<28) + public var datlat: DATLAT + + /// CLKDIV + @ReadWrite(bits: 20..<24) + public var clkdiv: CLKDIV + + /// BUSTURN + @ReadWrite(bits: 16..<20) + public var busturn: BUSTURN + + /// DATAST + @ReadWrite(bits: 8..<16) + public var datast: DATAST + + /// ADDHLD + @ReadWrite(bits: 4..<8) + public var addhld: ADDHLD + + /// ADDSET + @ReadWrite(bits: 0..<4) + public var addset: ADDSET + } + + /// SRAM/NOR-Flash chip-select control register 2 + @Register(bitWidth: 32) + public struct BCR { + /// CBURSTRW + @ReadWrite(bits: 19..<20, as: CBURSTRWValues.self) + public var cburstrw: CBURSTRW + + /// ASYNCWAIT + @ReadWrite(bits: 15..<16, as: ASYNCWAITValues.self) + public var asyncwait: ASYNCWAIT + + /// EXTMOD + @ReadWrite(bits: 14..<15, as: EXTMODValues.self) + public var extmod: EXTMOD + + /// WAITEN + @ReadWrite(bits: 13..<14, as: WAITENValues.self) + public var waiten: WAITEN + + /// WREN + @ReadWrite(bits: 12..<13, as: WRENValues.self) + public var wren: WREN + + /// WAITCFG + @ReadWrite(bits: 11..<12, as: WAITCFGValues.self) + public var waitcfg: WAITCFG + + /// WRAPMOD + @ReadWrite(bits: 10..<11) + public var wrapmod: WRAPMOD + + /// WAITPOL + @ReadWrite(bits: 9..<10, as: WAITPOLValues.self) + public var waitpol: WAITPOL + + /// BURSTEN + @ReadWrite(bits: 8..<9, as: BURSTENValues.self) + public var bursten: BURSTEN + + /// FACCEN + @ReadWrite(bits: 6..<7, as: FACCENValues.self) + public var faccen: FACCEN + + /// MWID + @ReadWrite(bits: 4..<6, as: MWIDValues.self) + public var mwid: MWID + + /// MTYP + @ReadWrite(bits: 2..<4, as: MTYPValues.self) + public var mtyp: MTYP + + /// MUXEN + @ReadWrite(bits: 1..<2, as: MUXENValues.self) + public var muxen: MUXEN + + /// MBKEN + @ReadWrite(bits: 0..<1, as: MBKENValues.self) + public var mbken: MBKEN + + /// CRAM page size + @ReadWrite(bits: 16..<19, as: CPSIZEValues.self) + public var cpsize: CPSIZE + } + + /// PC Card/NAND Flash control register + @Register(bitWidth: 32) + public struct PCR { + /// ECCPS + @ReadWrite(bits: 17..<20, as: ECCPSValues.self) + public var eccps: ECCPS + + /// TAR + @ReadWrite(bits: 13..<17) + public var tar: TAR + + /// TCLR + @ReadWrite(bits: 9..<13) + public var tclr: TCLR + + /// ECCEN + @ReadWrite(bits: 6..<7, as: ECCENValues.self) + public var eccen: ECCEN + + /// PWID + @ReadWrite(bits: 4..<6, as: PWIDValues.self) + public var pwid: PWID + + /// PTYP + @ReadWrite(bits: 3..<4, as: PTYPValues.self) + public var ptyp: PTYP + + /// PBKEN + @ReadWrite(bits: 2..<3, as: PBKENValues.self) + public var pbken: PBKEN + + /// PWAITEN + @ReadWrite(bits: 1..<2, as: PWAITENValues.self) + public var pwaiten: PWAITEN + } + + /// FIFO status and interrupt register + @Register(bitWidth: 32) + public struct SR { + /// FEMPT + @ReadOnly(bits: 6..<7) + public var fempt: FEMPT + + /// IFEN + @ReadWrite(bits: 5..<6, as: IFENValues.self) + public var ifen: IFEN + + /// ILEN + @ReadWrite(bits: 4..<5, as: ILENValues.self) + public var ilen: ILEN + + /// IREN + @ReadWrite(bits: 3..<4, as: IRENValues.self) + public var iren: IREN + + /// IFS + @ReadWrite(bits: 2..<3, as: IFSValues.self) + public var ifs: IFS + + /// ILS + @ReadWrite(bits: 1..<2, as: ILSValues.self) + public var ils: ILS + + /// IRS + @ReadWrite(bits: 0..<1, as: IRSValues.self) + public var irs: IRS + } + + /// Common memory space timing register + @Register(bitWidth: 32) + public struct PMEM { + /// MEMHIZx + @ReadWrite(bits: 24..<32) + public var memhiz: MEMHIZ + + /// MEMHOLDx + @ReadWrite(bits: 16..<24) + public var memhold: MEMHOLD + + /// MEMWAITx + @ReadWrite(bits: 8..<16) + public var memwait: MEMWAIT + + /// MEMSETx + @ReadWrite(bits: 0..<8) + public var memset: MEMSET + } + + /// Attribute memory space timing register + @Register(bitWidth: 32) + public struct PATT { + /// ATTHIZx + @ReadWrite(bits: 24..<32) + public var atthiz: ATTHIZ + + /// ATTHOLDx + @ReadWrite(bits: 16..<24) + public var atthold: ATTHOLD + + /// ATTWAITx + @ReadWrite(bits: 8..<16) + public var attwait: ATTWAIT + + /// ATTSETx + @ReadWrite(bits: 0..<8) + public var attset: ATTSET + } + + /// ECC result register + @Register(bitWidth: 32) + public struct ECCR { + /// ECCx + @ReadOnly(bits: 0..<32) + public var ecc: ECC + } + + /// SRAM/NOR-Flash write timing registers 1 + @Register(bitWidth: 32) + public struct BWTR { + /// ACCMOD + @ReadWrite(bits: 28..<30, as: ACCMODValues.self) + public var accmod: ACCMOD + + /// DATLAT + @ReadWrite(bits: 24..<28) + public var datlat: DATLAT + + /// CLKDIV + @ReadWrite(bits: 20..<24) + public var clkdiv: CLKDIV + + /// DATAST + @ReadWrite(bits: 8..<16) + public var datast: DATAST + + /// ADDHLD + @ReadWrite(bits: 4..<8) + public var addhld: ADDHLD + + /// ADDSET + @ReadWrite(bits: 0..<4) + public var addset: ADDSET + + /// Bus turnaround phase duration + @ReadWrite(bits: 16..<20) + public var busturn: BUSTURN + } + + /// SDRAM Control Register 1 + @Register(bitWidth: 32) + public struct SDCR { + /// Number of column address bits + @ReadWrite(bits: 0..<2, as: NCValues.self) + public var nc: NC + + /// Number of row address bits + @ReadWrite(bits: 2..<4, as: NRValues.self) + public var nr: NR + + /// Memory data bus width + @ReadWrite(bits: 4..<6, as: MWIDValues.self) + public var mwid: MWID + + /// Number of internal banks + @ReadWrite(bits: 6..<7, as: NBValues.self) + public var nb: NB + + /// CAS latency + @ReadWrite(bits: 7..<9, as: CASValues.self) + public var cas: CAS + + /// Write protection + @ReadWrite(bits: 9..<10, as: WPValues.self) + public var wp: WP + + /// SDRAM clock configuration + @ReadWrite(bits: 10..<12, as: SDCLKValues.self) + public var sdclk: SDCLK + + /// Burst read + @ReadWrite(bits: 12..<13, as: RBURSTValues.self) + public var rburst: RBURST + + /// Read pipe + @ReadWrite(bits: 13..<15, as: RPIPEValues.self) + public var rpipe: RPIPE + } + + /// SDRAM Timing register 1 + @Register(bitWidth: 32) + public struct SDTR { + /// Load Mode Register to Active + @ReadWrite(bits: 0..<4) + public var tmrd: TMRD + + /// Exit self-refresh delay + @ReadWrite(bits: 4..<8) + public var txsr: TXSR + + /// Self refresh time + @ReadWrite(bits: 8..<12) + public var tras: TRAS + + /// Row cycle delay + @ReadWrite(bits: 12..<16) + public var trc: TRC + + /// Recovery delay + @ReadWrite(bits: 16..<20) + public var twr: TWR + + /// Row precharge delay + @ReadWrite(bits: 20..<24) + public var trp: TRP + + /// Row to column delay + @ReadWrite(bits: 24..<28) + public var trcd: TRCD + } + + /// SDRAM Command Mode register + @Register(bitWidth: 32) + public struct SDCMR { + /// Command mode + @WriteOnly(bits: 0..<3) + public var mode: MODE + + /// Command target bank 2 + @WriteOnly(bits: 3..<4) + public var ctb2: CTB2 + + /// Command target bank 1 + @WriteOnly(bits: 4..<5) + public var ctb1: CTB1 + + /// Number of Auto-refresh + @ReadWrite(bits: 5..<9) + public var nrfs: NRFS + + /// Mode Register definition + @ReadWrite(bits: 9..<22) + public var mrd: MRD + } + + /// SDRAM Refresh Timer register + @Register(bitWidth: 32) + public struct SDRTR { + /// Clear Refresh error flag + @WriteOnly(bits: 0..<1) + public var cre: CRE + + /// Refresh Timer Count + @ReadWrite(bits: 1..<14) + public var count: COUNT + + /// RES Interrupt Enable + @ReadWrite(bits: 14..<15, as: REIEValues.self) + public var reie: REIE + } + + /// SDRAM Status register + @Register(bitWidth: 32) + public struct SDSR { + /// Refresh error flag + @ReadOnly(bits: 0..<1) + public var re: RE + + /// Status Mode for Bank 1 + @ReadOnly(bits: 1..<3) + public var modes1: MODES1 + + /// Status Mode for Bank 2 + @ReadOnly(bits: 3..<5) + public var modes2: MODES2 + + /// Busy status + @ReadOnly(bits: 5..<6) + public var busy: BUSY + } +} + +extension FMC.BCR1 { + public struct CCLKENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// The FMC_CLK is generated continuously during asynchronous and synchronous access. The FMC_CLK clock is activated when the CCLKEN is set + public static let Disabled = Self(rawValue: 0x0) + + /// The FMC_CLK is only generated during the synchronous memory access (read/write transaction) + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR1 { + public struct CBURSTRWValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Write operations are always performed in asynchronous mode + public static let Disabled = Self(rawValue: 0x0) + + /// Write operations are performed in synchronous mode + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR1 { + public struct ASYNCWAITValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Wait signal not used in asynchronous mode + public static let Disabled = Self(rawValue: 0x0) + + /// Wait signal used even in asynchronous mode + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR1 { + public struct EXTMODValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Values inside the FMC_BWTR are not taken into account + public static let Disabled = Self(rawValue: 0x0) + + /// Values inside the FMC_BWTR are taken into account + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR1 { + public struct WAITENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Values inside the FMC_BWTR are taken into account + public static let Disabled = Self(rawValue: 0x0) + + /// NWAIT signal enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR1 { + public struct WRENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Write operations disabled for the bank by the FMC + public static let Disabled = Self(rawValue: 0x0) + + /// Write operations enabled for the bank by the FMC + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR1 { + public struct WAITCFGValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// NWAIT signal is active one data cycle before wait state + public static let BeforeWaitState = Self(rawValue: 0x0) + + /// NWAIT signal is active during wait state + public static let DuringWaitState = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR1 { + public struct WAITPOLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// NWAIT active low + public static let ActiveLow = Self(rawValue: 0x0) + + /// NWAIT active high + public static let ActiveHigh = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR1 { + public struct BURSTENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Burst mode disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Burst mode enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR1 { + public struct FACCENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Corresponding NOR Flash memory access is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Corresponding NOR Flash memory access is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR1 { + public struct MWIDValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// Memory data bus width 8 bits + public static let Bits8 = Self(rawValue: 0x0) + + /// Memory data bus width 16 bits + public static let Bits16 = Self(rawValue: 0x1) + + /// Memory data bus width 32 bits + public static let Bits32 = Self(rawValue: 0x2) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR1 { + public struct MTYPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// SRAM memory type + public static let SRAM = Self(rawValue: 0x0) + + /// PSRAM (CRAM) memory type + public static let PSRAM = Self(rawValue: 0x1) + + /// NOR Flash/OneNAND Flash + public static let Flash = Self(rawValue: 0x2) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR1 { + public struct MUXENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Address/Data non-multiplexed + public static let Disabled = Self(rawValue: 0x0) + + /// Address/Data multiplexed on databus + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR1 { + public struct MBKENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Corresponding memory bank is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Corresponding memory bank is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR1 { + public struct WFDISValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Write FIFO enabled + public static let Enabled = Self(rawValue: 0x0) + + /// Write FIFO disabled + public static let Disabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR1 { + public struct CPSIZEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 3 + + /// No burst split when crossing page boundary + public static let NoBurstSplit = Self(rawValue: 0x0) + + /// 128 bytes CRAM page size + public static let Bytes128 = Self(rawValue: 0x1) + + /// 256 bytes CRAM page size + public static let Bytes256 = Self(rawValue: 0x2) + + /// 512 bytes CRAM page size + public static let Bytes512 = Self(rawValue: 0x3) + + /// 1024 bytes CRAM page size + public static let Bytes1024 = Self(rawValue: 0x4) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BTR { + public struct ACCMODValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// Access mode A + public static let A = Self(rawValue: 0x0) + + /// Access mode B + public static let B = Self(rawValue: 0x1) + + /// Access mode C + public static let C = Self(rawValue: 0x2) + + /// Access mode D + public static let D = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR { + public struct CBURSTRWValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Write operations are always performed in asynchronous mode + public static let Disabled = Self(rawValue: 0x0) + + /// Write operations are performed in synchronous mode + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR { + public struct ASYNCWAITValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Wait signal not used in asynchronous mode + public static let Disabled = Self(rawValue: 0x0) + + /// Wait signal used even in asynchronous mode + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR { + public struct EXTMODValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Values inside the FMC_BWTR are not taken into account + public static let Disabled = Self(rawValue: 0x0) + + /// Values inside the FMC_BWTR are taken into account + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR { + public struct WAITENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Values inside the FMC_BWTR are taken into account + public static let Disabled = Self(rawValue: 0x0) + + /// NWAIT signal enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR { + public struct WRENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Write operations disabled for the bank by the FMC + public static let Disabled = Self(rawValue: 0x0) + + /// Write operations enabled for the bank by the FMC + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR { + public struct WAITCFGValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// NWAIT signal is active one data cycle before wait state + public static let BeforeWaitState = Self(rawValue: 0x0) + + /// NWAIT signal is active during wait state + public static let DuringWaitState = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR { + public struct WAITPOLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// NWAIT active low + public static let ActiveLow = Self(rawValue: 0x0) + + /// NWAIT active high + public static let ActiveHigh = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR { + public struct BURSTENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Burst mode disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Burst mode enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR { + public struct FACCENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Corresponding NOR Flash memory access is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Corresponding NOR Flash memory access is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR { + public struct MWIDValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// Memory data bus width 8 bits + public static let Bits8 = Self(rawValue: 0x0) + + /// Memory data bus width 16 bits + public static let Bits16 = Self(rawValue: 0x1) + + /// Memory data bus width 32 bits + public static let Bits32 = Self(rawValue: 0x2) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR { + public struct MTYPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// SRAM memory type + public static let SRAM = Self(rawValue: 0x0) + + /// PSRAM (CRAM) memory type + public static let PSRAM = Self(rawValue: 0x1) + + /// NOR Flash/OneNAND Flash + public static let Flash = Self(rawValue: 0x2) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR { + public struct MUXENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Address/Data non-multiplexed + public static let Disabled = Self(rawValue: 0x0) + + /// Address/Data multiplexed on databus + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR { + public struct MBKENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Corresponding memory bank is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Corresponding memory bank is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BCR { + public struct CPSIZEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 3 + + /// No burst split when crossing page boundary + public static let NoBurstSplit = Self(rawValue: 0x0) + + /// 128 bytes CRAM page size + public static let Bytes128 = Self(rawValue: 0x1) + + /// 256 bytes CRAM page size + public static let Bytes256 = Self(rawValue: 0x2) + + /// 512 bytes CRAM page size + public static let Bytes512 = Self(rawValue: 0x3) + + /// 1024 bytes CRAM page size + public static let Bytes1024 = Self(rawValue: 0x4) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.PCR { + public struct ECCPSValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 3 + + /// ECC page size 256 bytes + public static let Bytes256 = Self(rawValue: 0x0) + + /// ECC page size 512 bytes + public static let Bytes512 = Self(rawValue: 0x1) + + /// ECC page size 1024 bytes + public static let Bytes1024 = Self(rawValue: 0x2) + + /// ECC page size 2048 bytes + public static let Bytes2048 = Self(rawValue: 0x3) + + /// ECC page size 4096 bytes + public static let Bytes4096 = Self(rawValue: 0x4) + + /// ECC page size 8192 bytes + public static let Bytes8192 = Self(rawValue: 0x5) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.PCR { + public struct ECCENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// ECC logic is disabled and reset + public static let Disabled = Self(rawValue: 0x0) + + /// ECC logic is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.PCR { + public struct PWIDValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// External memory device width 8 bits + public static let Bits8 = Self(rawValue: 0x0) + + /// External memory device width 16 bits + public static let Bits16 = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.PCR { + public struct PTYPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// NAND Flash + public static let NANDFlash = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.PCR { + public struct PBKENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Corresponding memory bank is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Corresponding memory bank is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.PCR { + public struct PWAITENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Wait feature disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Wait feature enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.SR { + public struct IFENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Interrupt falling edge detection request disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Interrupt falling edge detection request enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.SR { + public struct ILENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Interrupt high-level detection request disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Interrupt high-level detection request enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.SR { + public struct IRENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Interrupt rising edge detection request disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Interrupt rising edge detection request enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.SR { + public struct IFSValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Interrupt falling edge did not occur + public static let DidNotOccur = Self(rawValue: 0x0) + + /// Interrupt falling edge occurred + public static let Occurred = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.SR { + public struct ILSValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Interrupt high-level did not occur + public static let DidNotOccur = Self(rawValue: 0x0) + + /// Interrupt high-level occurred + public static let Occurred = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.SR { + public struct IRSValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Interrupt rising edge did not occur + public static let DidNotOccur = Self(rawValue: 0x0) + + /// Interrupt rising edge occurred + public static let Occurred = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.BWTR { + public struct ACCMODValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// Access mode A + public static let A = Self(rawValue: 0x0) + + /// Access mode B + public static let B = Self(rawValue: 0x1) + + /// Access mode C + public static let C = Self(rawValue: 0x2) + + /// Access mode D + public static let D = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.SDCR { + public struct NCValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// 8 bits + public static let Bits8 = Self(rawValue: 0x0) + + /// 9 bits + public static let Bits9 = Self(rawValue: 0x1) + + /// 10 bits + public static let Bits10 = Self(rawValue: 0x2) + + /// 11 bits + public static let Bits11 = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.SDCR { + public struct NRValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// 11 bits + public static let Bits11 = Self(rawValue: 0x0) + + /// 12 bits + public static let Bits12 = Self(rawValue: 0x1) + + /// 13 bits + public static let Bits13 = Self(rawValue: 0x2) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.SDCR { + public struct MWIDValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// Memory data bus width 8 bits + public static let Bits8 = Self(rawValue: 0x0) + + /// Memory data bus width 16 bits + public static let Bits16 = Self(rawValue: 0x1) + + /// Memory data bus width 32 bits + public static let Bits32 = Self(rawValue: 0x2) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.SDCR { + public struct NBValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Two internal Banks + public static let NB2 = Self(rawValue: 0x0) + + /// Four internal Banks + public static let NB4 = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.SDCR { + public struct CASValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// 1 cycle + public static let Clocks1 = Self(rawValue: 0x1) + + /// 2 cycles + public static let Clocks2 = Self(rawValue: 0x2) + + /// 3 cycles + public static let Clocks3 = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.SDCR { + public struct WPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Write accesses allowed + public static let Disabled = Self(rawValue: 0x0) + + /// Write accesses ignored + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.SDCR { + public struct SDCLKValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// SDCLK clock disabled + public static let Disabled = Self(rawValue: 0x0) + + /// SDCLK period = 2 x HCLK period + public static let Div2 = Self(rawValue: 0x2) + + /// SDCLK period = 3 x HCLK period + public static let Div3 = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.SDCR { + public struct RBURSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Single read requests are not managed as bursts + public static let Disabled = Self(rawValue: 0x0) + + /// Single read requests are always managed as bursts + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.SDCR { + public struct RPIPEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// No clock cycle delay + public static let NoDelay = Self(rawValue: 0x0) + + /// One clock cycle delay + public static let Clocks1 = Self(rawValue: 0x1) + + /// Two clock cycles delay + public static let Clocks2 = Self(rawValue: 0x2) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension FMC.SDRTR { + public struct REIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Interrupt is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Interrupt is generated if RE = 1 + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} diff --git a/stm32-lvgl/Sources/Registers/GPIOA.swift b/stm32-lvgl/Sources/Registers/GPIOA.swift new file mode 100644 index 0000000..9513b88 --- /dev/null +++ b/stm32-lvgl/Sources/Registers/GPIOA.swift @@ -0,0 +1,1075 @@ +// Generated by svd2swift. + +import MMIO + +/// General-purpose I/Os +@RegisterBlock +public struct GPIOA { + /// GPIO port mode register + @RegisterBlock(offset: 0x0) + public var moder: Register + + /// GPIO port output type register + @RegisterBlock(offset: 0x4) + public var otyper: Register + + /// GPIO port output speed register + @RegisterBlock(offset: 0x8) + public var ospeedr: Register + + /// GPIO port pull-up/pull-down register + @RegisterBlock(offset: 0xc) + public var pupdr: Register + + /// GPIO port input data register + @RegisterBlock(offset: 0x10) + public var idr: Register + + /// GPIO port output data register + @RegisterBlock(offset: 0x14) + public var odr: Register + + /// GPIO port bit set/reset register + @RegisterBlock(offset: 0x18) + public var bsrr: Register + + /// GPIO port configuration lock register + @RegisterBlock(offset: 0x1c) + public var lckr: Register + + /// GPIO alternate function low register + @RegisterBlock(offset: 0x20) + public var afrl: Register + + /// GPIO alternate function high register + @RegisterBlock(offset: 0x24) + public var afrh: Register + + /// GPIO port bit reset register + @RegisterBlock(offset: 0x28) + public var brr: Register +} + +extension GPIOA { + /// GPIO port mode register + @Register(bitWidth: 32) + public struct MODER { + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 30..<32) + public var moder15: MODER15 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 28..<30) + public var moder14: MODER14 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 26..<28) + public var moder13: MODER13 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 24..<26) + public var moder12: MODER12 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 22..<24) + public var moder11: MODER11 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 20..<22) + public var moder10: MODER10 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 18..<20) + public var moder9: MODER9 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 16..<18) + public var moder8: MODER8 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 14..<16) + public var moder7: MODER7 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 12..<14) + public var moder6: MODER6 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 10..<12) + public var moder5: MODER5 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 8..<10) + public var moder4: MODER4 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 6..<8) + public var moder3: MODER3 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 4..<6) + public var moder2: MODER2 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 2..<4) + public var moder1: MODER1 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 0..<2, as: MODER0Values.self) + public var moder0: MODER0 + } + + /// GPIO port output type register + @Register(bitWidth: 32) + public struct OTYPER { + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 15..<16) + public var ot15: OT15 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 14..<15) + public var ot14: OT14 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 13..<14) + public var ot13: OT13 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 12..<13) + public var ot12: OT12 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 11..<12) + public var ot11: OT11 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 10..<11) + public var ot10: OT10 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 9..<10) + public var ot9: OT9 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 8..<9) + public var ot8: OT8 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 7..<8) + public var ot7: OT7 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 6..<7) + public var ot6: OT6 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 5..<6) + public var ot5: OT5 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 4..<5) + public var ot4: OT4 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 3..<4) + public var ot3: OT3 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 2..<3) + public var ot2: OT2 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 1..<2) + public var ot1: OT1 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 0..<1, as: OT0Values.self) + public var ot0: OT0 + } + + /// GPIO port output speed register + @Register(bitWidth: 32) + public struct OSPEEDR { + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 30..<32) + public var ospeedr15: OSPEEDR15 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 28..<30) + public var ospeedr14: OSPEEDR14 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 26..<28) + public var ospeedr13: OSPEEDR13 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 24..<26) + public var ospeedr12: OSPEEDR12 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 22..<24) + public var ospeedr11: OSPEEDR11 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 20..<22) + public var ospeedr10: OSPEEDR10 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 18..<20) + public var ospeedr9: OSPEEDR9 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 16..<18) + public var ospeedr8: OSPEEDR8 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 14..<16) + public var ospeedr7: OSPEEDR7 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 12..<14) + public var ospeedr6: OSPEEDR6 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 10..<12) + public var ospeedr5: OSPEEDR5 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 8..<10) + public var ospeedr4: OSPEEDR4 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 6..<8) + public var ospeedr3: OSPEEDR3 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 4..<6) + public var ospeedr2: OSPEEDR2 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 2..<4) + public var ospeedr1: OSPEEDR1 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 0..<2, as: OSPEEDR0Values.self) + public var ospeedr0: OSPEEDR0 + } + + /// GPIO port pull-up/pull-down register + @Register(bitWidth: 32) + public struct PUPDR { + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 30..<32) + public var pupdr15: PUPDR15 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 28..<30) + public var pupdr14: PUPDR14 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 26..<28) + public var pupdr13: PUPDR13 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 24..<26) + public var pupdr12: PUPDR12 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 22..<24) + public var pupdr11: PUPDR11 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 20..<22) + public var pupdr10: PUPDR10 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 18..<20) + public var pupdr9: PUPDR9 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 16..<18) + public var pupdr8: PUPDR8 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 14..<16) + public var pupdr7: PUPDR7 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 12..<14) + public var pupdr6: PUPDR6 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 10..<12) + public var pupdr5: PUPDR5 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 8..<10) + public var pupdr4: PUPDR4 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 6..<8) + public var pupdr3: PUPDR3 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 4..<6) + public var pupdr2: PUPDR2 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 2..<4) + public var pupdr1: PUPDR1 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 0..<2, as: PUPDR0Values.self) + public var pupdr0: PUPDR0 + } + + /// GPIO port input data register + @Register(bitWidth: 32) + public struct IDR { + /// Port input data (y = 0..15) + @ReadOnly(bits: 15..<16) + public var idr15: IDR15 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 14..<15) + public var idr14: IDR14 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 13..<14) + public var idr13: IDR13 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 12..<13) + public var idr12: IDR12 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 11..<12) + public var idr11: IDR11 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 10..<11) + public var idr10: IDR10 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 9..<10) + public var idr9: IDR9 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 8..<9) + public var idr8: IDR8 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 7..<8) + public var idr7: IDR7 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 6..<7) + public var idr6: IDR6 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 5..<6) + public var idr5: IDR5 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 4..<5) + public var idr4: IDR4 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 3..<4) + public var idr3: IDR3 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 2..<3) + public var idr2: IDR2 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 1..<2) + public var idr1: IDR1 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 0..<1) + public var idr0: IDR0 + } + + /// GPIO port output data register + @Register(bitWidth: 32) + public struct ODR { + /// Port output data (y = 0..15) + @ReadWrite(bits: 15..<16) + public var odr15: ODR15 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 14..<15) + public var odr14: ODR14 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 13..<14) + public var odr13: ODR13 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 12..<13) + public var odr12: ODR12 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 11..<12) + public var odr11: ODR11 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 10..<11) + public var odr10: ODR10 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 9..<10) + public var odr9: ODR9 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 8..<9) + public var odr8: ODR8 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 7..<8) + public var odr7: ODR7 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 6..<7) + public var odr6: ODR6 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 5..<6) + public var odr5: ODR5 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 4..<5) + public var odr4: ODR4 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 3..<4) + public var odr3: ODR3 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 2..<3) + public var odr2: ODR2 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 1..<2) + public var odr1: ODR1 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 0..<1, as: ODR0Values.self) + public var odr0: ODR0 + } + + /// GPIO port bit set/reset register + @Register(bitWidth: 32) + public struct BSRR { + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 31..<32) + public var br15: BR15 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 30..<31) + public var br14: BR14 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 29..<30) + public var br13: BR13 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 28..<29) + public var br12: BR12 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 27..<28) + public var br11: BR11 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 26..<27) + public var br10: BR10 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 25..<26) + public var br9: BR9 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 24..<25) + public var br8: BR8 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 23..<24) + public var br7: BR7 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 22..<23) + public var br6: BR6 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 21..<22) + public var br5: BR5 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 20..<21) + public var br4: BR4 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 19..<20) + public var br3: BR3 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 18..<19) + public var br2: BR2 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 17..<18) + public var br1: BR1 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 16..<17) + public var br0: BR0 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 15..<16) + public var bs15: BS15 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 14..<15) + public var bs14: BS14 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 13..<14) + public var bs13: BS13 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 12..<13) + public var bs12: BS12 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 11..<12) + public var bs11: BS11 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 10..<11) + public var bs10: BS10 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 9..<10) + public var bs9: BS9 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 8..<9) + public var bs8: BS8 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 7..<8) + public var bs7: BS7 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 6..<7) + public var bs6: BS6 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 5..<6) + public var bs5: BS5 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 4..<5) + public var bs4: BS4 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 3..<4) + public var bs3: BS3 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 2..<3) + public var bs2: BS2 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 1..<2) + public var bs1: BS1 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 0..<1) + public var bs0: BS0 + } + + /// GPIO port configuration lock register + @Register(bitWidth: 32) + public struct LCKR { + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 16..<17, as: LCKKValues.self) + public var lckk: LCKK + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 15..<16) + public var lck15: LCK15 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 14..<15) + public var lck14: LCK14 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 13..<14) + public var lck13: LCK13 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 12..<13) + public var lck12: LCK12 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 11..<12) + public var lck11: LCK11 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 10..<11) + public var lck10: LCK10 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 9..<10) + public var lck9: LCK9 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 8..<9) + public var lck8: LCK8 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 7..<8) + public var lck7: LCK7 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 6..<7) + public var lck6: LCK6 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 5..<6) + public var lck5: LCK5 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 4..<5) + public var lck4: LCK4 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 3..<4) + public var lck3: LCK3 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 2..<3) + public var lck2: LCK2 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 1..<2) + public var lck1: LCK1 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 0..<1, as: LCK0Values.self) + public var lck0: LCK0 + } + + /// GPIO alternate function low register + @Register(bitWidth: 32) + public struct AFRL { + /// Alternate function selection for port x bit y (y = 0..7) + @ReadWrite(bits: 28..<32) + public var afrl7: AFRL7 + + /// Alternate function selection for port x bit y (y = 0..7) + @ReadWrite(bits: 24..<28) + public var afrl6: AFRL6 + + /// Alternate function selection for port x bit y (y = 0..7) + @ReadWrite(bits: 20..<24) + public var afrl5: AFRL5 + + /// Alternate function selection for port x bit y (y = 0..7) + @ReadWrite(bits: 16..<20) + public var afrl4: AFRL4 + + /// Alternate function selection for port x bit y (y = 0..7) + @ReadWrite(bits: 12..<16) + public var afrl3: AFRL3 + + /// Alternate function selection for port x bit y (y = 0..7) + @ReadWrite(bits: 8..<12) + public var afrl2: AFRL2 + + /// Alternate function selection for port x bit y (y = 0..7) + @ReadWrite(bits: 4..<8) + public var afrl1: AFRL1 + + /// Alternate function selection for port x bit y (y = 0..7) + @ReadWrite(bits: 0..<4, as: AFRL0Values.self) + public var afrl0: AFRL0 + } + + /// GPIO alternate function high register + @Register(bitWidth: 32) + public struct AFRH { + /// Alternate function selection for port x bit y (y = 8..15) + @ReadWrite(bits: 28..<32) + public var afrh15: AFRH15 + + /// Alternate function selection for port x bit y (y = 8..15) + @ReadWrite(bits: 24..<28) + public var afrh14: AFRH14 + + /// Alternate function selection for port x bit y (y = 8..15) + @ReadWrite(bits: 20..<24) + public var afrh13: AFRH13 + + /// Alternate function selection for port x bit y (y = 8..15) + @ReadWrite(bits: 16..<20) + public var afrh12: AFRH12 + + /// Alternate function selection for port x bit y (y = 8..15) + @ReadWrite(bits: 12..<16) + public var afrh11: AFRH11 + + /// Alternate function selection for port x bit y (y = 8..15) + @ReadWrite(bits: 8..<12) + public var afrh10: AFRH10 + + /// Alternate function selection for port x bit y (y = 8..15) + @ReadWrite(bits: 4..<8) + public var afrh9: AFRH9 + + /// Alternate function selection for port x bit y (y = 8..15) + @ReadWrite(bits: 0..<4, as: AFRH8Values.self) + public var afrh8: AFRH8 + } + + /// GPIO port bit reset register + @Register(bitWidth: 32) + public struct BRR { + /// Port A Reset bit 0 + @ReadWrite(bits: 0..<1) + public var br0: BR0 + + /// Port A Reset bit 1 + @ReadWrite(bits: 1..<2) + public var br1: BR1 + + /// Port A Reset bit 2 + @ReadWrite(bits: 2..<3) + public var br2: BR2 + + /// Port A Reset bit 3 + @ReadWrite(bits: 3..<4) + public var br3: BR3 + + /// Port A Reset bit 4 + @ReadWrite(bits: 4..<5) + public var br4: BR4 + + /// Port A Reset bit 5 + @ReadWrite(bits: 5..<6) + public var br5: BR5 + + /// Port A Reset bit 6 + @ReadWrite(bits: 6..<7) + public var br6: BR6 + + /// Port A Reset bit 7 + @ReadWrite(bits: 7..<8) + public var br7: BR7 + + /// Port A Reset bit 8 + @ReadWrite(bits: 8..<9) + public var br8: BR8 + + /// Port A Reset bit 9 + @ReadWrite(bits: 9..<10) + public var br9: BR9 + + /// Port A Reset bit 10 + @ReadWrite(bits: 10..<11) + public var br10: BR10 + + /// Port A Reset bit 11 + @ReadWrite(bits: 11..<12) + public var br11: BR11 + + /// Port A Reset bit 12 + @ReadWrite(bits: 12..<13) + public var br12: BR12 + + /// Port A Reset bit 13 + @ReadWrite(bits: 13..<14) + public var br13: BR13 + + /// Port A Reset bit 14 + @ReadWrite(bits: 14..<15) + public var br14: BR14 + + /// Port A Reset bit 15 + @ReadWrite(bits: 15..<16) + public var br15: BR15 + } +} + +extension GPIOA.MODER { + public struct MODER0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// Input mode (reset state) + public static let Input = Self(rawValue: 0x0) + + /// General purpose output mode + public static let Output = Self(rawValue: 0x1) + + /// Alternate function mode + public static let Alternate = Self(rawValue: 0x2) + + /// Analog mode + public static let Analog = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.OTYPER { + public struct OT0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Output push-pull (reset state) + public static let PushPull = Self(rawValue: 0x0) + + /// Output open-drain + public static let OpenDrain = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.OSPEEDR { + public struct OSPEEDR0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// Low speed + public static let LowSpeed = Self(rawValue: 0x0) + + /// Medium speed + public static let MediumSpeed = Self(rawValue: 0x1) + + /// High speed + public static let HighSpeed = Self(rawValue: 0x2) + + /// Very high speed + public static let VeryHighSpeed = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.PUPDR { + public struct PUPDR0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// No pull-up, pull-down + public static let Floating = Self(rawValue: 0x0) + + /// Pull-up + public static let PullUp = Self(rawValue: 0x1) + + /// Pull-down + public static let PullDown = Self(rawValue: 0x2) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.ODR { + public struct ODR0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Set output to logic low + public static let Low = Self(rawValue: 0x0) + + /// Set output to logic high + public static let High = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.LCKR { + public struct LCKKValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Port configuration lock key not active + public static let NotActive = Self(rawValue: 0x0) + + /// Port configuration lock key active + public static let Active = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.LCKR { + public struct LCK0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Port configuration not locked + public static let Unlocked = Self(rawValue: 0x0) + + /// Port configuration locked + public static let Locked = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.AFRL { + public struct AFRL0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 4 + + /// AF0 + public static let AF0 = Self(rawValue: 0x0) + + /// AF1 + public static let AF1 = Self(rawValue: 0x1) + + /// AF2 + public static let AF2 = Self(rawValue: 0x2) + + /// AF3 + public static let AF3 = Self(rawValue: 0x3) + + /// AF4 + public static let AF4 = Self(rawValue: 0x4) + + /// AF5 + public static let AF5 = Self(rawValue: 0x5) + + /// AF6 + public static let AF6 = Self(rawValue: 0x6) + + /// AF7 + public static let AF7 = Self(rawValue: 0x7) + + /// AF8 + public static let AF8 = Self(rawValue: 0x8) + + /// AF9 + public static let AF9 = Self(rawValue: 0x9) + + /// AF10 + public static let AF10 = Self(rawValue: 0xa) + + /// AF11 + public static let AF11 = Self(rawValue: 0xb) + + /// AF12 + public static let AF12 = Self(rawValue: 0xc) + + /// AF13 + public static let AF13 = Self(rawValue: 0xd) + + /// AF14 + public static let AF14 = Self(rawValue: 0xe) + + /// AF15 + public static let AF15 = Self(rawValue: 0xf) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.AFRH { + public struct AFRH8Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 4 + + /// AF0 + public static let AF0 = Self(rawValue: 0x0) + + /// AF1 + public static let AF1 = Self(rawValue: 0x1) + + /// AF2 + public static let AF2 = Self(rawValue: 0x2) + + /// AF3 + public static let AF3 = Self(rawValue: 0x3) + + /// AF4 + public static let AF4 = Self(rawValue: 0x4) + + /// AF5 + public static let AF5 = Self(rawValue: 0x5) + + /// AF6 + public static let AF6 = Self(rawValue: 0x6) + + /// AF7 + public static let AF7 = Self(rawValue: 0x7) + + /// AF8 + public static let AF8 = Self(rawValue: 0x8) + + /// AF9 + public static let AF9 = Self(rawValue: 0x9) + + /// AF10 + public static let AF10 = Self(rawValue: 0xa) + + /// AF11 + public static let AF11 = Self(rawValue: 0xb) + + /// AF12 + public static let AF12 = Self(rawValue: 0xc) + + /// AF13 + public static let AF13 = Self(rawValue: 0xd) + + /// AF14 + public static let AF14 = Self(rawValue: 0xe) + + /// AF15 + public static let AF15 = Self(rawValue: 0xf) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} diff --git a/stm32-lvgl/Sources/Registers/GPIOB.swift b/stm32-lvgl/Sources/Registers/GPIOB.swift new file mode 100644 index 0000000..bd0a35b --- /dev/null +++ b/stm32-lvgl/Sources/Registers/GPIOB.swift @@ -0,0 +1,7 @@ +// Generated by svd2swift. + +import MMIO + +/// General-purpose I/Os +public typealias GPIOB = GPIOA + diff --git a/stm32-lvgl/Sources/Registers/GPIOC.swift b/stm32-lvgl/Sources/Registers/GPIOC.swift new file mode 100644 index 0000000..c46e669 --- /dev/null +++ b/stm32-lvgl/Sources/Registers/GPIOC.swift @@ -0,0 +1,7 @@ +// Generated by svd2swift. + +import MMIO + +/// General-purpose I/Os +public typealias GPIOC = GPIOA + diff --git a/stm32-lvgl/Sources/Registers/GPIOD.swift b/stm32-lvgl/Sources/Registers/GPIOD.swift new file mode 100644 index 0000000..d51ac80 --- /dev/null +++ b/stm32-lvgl/Sources/Registers/GPIOD.swift @@ -0,0 +1,7 @@ +// Generated by svd2swift. + +import MMIO + +/// General-purpose I/Os +public typealias GPIOD = GPIOA + diff --git a/stm32-lvgl/Sources/Registers/GPIOE.swift b/stm32-lvgl/Sources/Registers/GPIOE.swift new file mode 100644 index 0000000..c78fa87 --- /dev/null +++ b/stm32-lvgl/Sources/Registers/GPIOE.swift @@ -0,0 +1,7 @@ +// Generated by svd2swift. + +import MMIO + +/// General-purpose I/Os +public typealias GPIOE = GPIOA + diff --git a/stm32-lvgl/Sources/Registers/GPIOF.swift b/stm32-lvgl/Sources/Registers/GPIOF.swift new file mode 100644 index 0000000..f4dce7f --- /dev/null +++ b/stm32-lvgl/Sources/Registers/GPIOF.swift @@ -0,0 +1,7 @@ +// Generated by svd2swift. + +import MMIO + +/// General-purpose I/Os +public typealias GPIOF = GPIOA + diff --git a/stm32-lvgl/Sources/Registers/GPIOG.swift b/stm32-lvgl/Sources/Registers/GPIOG.swift new file mode 100644 index 0000000..88fb4c6 --- /dev/null +++ b/stm32-lvgl/Sources/Registers/GPIOG.swift @@ -0,0 +1,7 @@ +// Generated by svd2swift. + +import MMIO + +/// General-purpose I/Os +public typealias GPIOG = GPIOA + diff --git a/stm32-lvgl/Sources/Registers/GPIOH.swift b/stm32-lvgl/Sources/Registers/GPIOH.swift new file mode 100644 index 0000000..5a558ef --- /dev/null +++ b/stm32-lvgl/Sources/Registers/GPIOH.swift @@ -0,0 +1,7 @@ +// Generated by svd2swift. + +import MMIO + +/// General-purpose I/Os +public typealias GPIOH = GPIOA + diff --git a/stm32-lvgl/Sources/Registers/GPIOI.swift b/stm32-lvgl/Sources/Registers/GPIOI.swift new file mode 100644 index 0000000..6b2b518 --- /dev/null +++ b/stm32-lvgl/Sources/Registers/GPIOI.swift @@ -0,0 +1,7 @@ +// Generated by svd2swift. + +import MMIO + +/// General-purpose I/Os +public typealias GPIOI = GPIOA + diff --git a/stm32-lvgl/Sources/Registers/GPIOJ.swift b/stm32-lvgl/Sources/Registers/GPIOJ.swift new file mode 100644 index 0000000..98b3c09 --- /dev/null +++ b/stm32-lvgl/Sources/Registers/GPIOJ.swift @@ -0,0 +1,7 @@ +// Generated by svd2swift. + +import MMIO + +/// General-purpose I/Os +public typealias GPIOJ = GPIOA + diff --git a/stm32-lvgl/Sources/Registers/GPIOK.swift b/stm32-lvgl/Sources/Registers/GPIOK.swift new file mode 100644 index 0000000..c1f074b --- /dev/null +++ b/stm32-lvgl/Sources/Registers/GPIOK.swift @@ -0,0 +1,7 @@ +// Generated by svd2swift. + +import MMIO + +/// General-purpose I/Os +public typealias GPIOK = GPIOA + diff --git a/stm32-lvgl/Sources/Registers/I2C1.swift b/stm32-lvgl/Sources/Registers/I2C1.swift new file mode 100644 index 0000000..c68ff9e --- /dev/null +++ b/stm32-lvgl/Sources/Registers/I2C1.swift @@ -0,0 +1,1069 @@ +// Generated by svd2swift. + +import MMIO + +/// Inter-integrated circuit +@RegisterBlock +public struct I2C1 { + /// Control register 1 + @RegisterBlock(offset: 0x0) + public var cr1: Register + + /// Control register 2 + @RegisterBlock(offset: 0x4) + public var cr2: Register + + /// Own address register 1 + @RegisterBlock(offset: 0x8) + public var oar1: Register + + /// Own address register 2 + @RegisterBlock(offset: 0xc) + public var oar2: Register + + /// Timing register + @RegisterBlock(offset: 0x10) + public var timingr: Register + + /// Status register 1 + @RegisterBlock(offset: 0x14) + public var timeoutr: Register + + /// Interrupt and Status register + @RegisterBlock(offset: 0x18) + public var isr: Register + + /// Interrupt clear register + @RegisterBlock(offset: 0x1c) + public var icr: Register + + /// PEC register + @RegisterBlock(offset: 0x20) + public var pecr: Register + + /// Receive data register + @RegisterBlock(offset: 0x24) + public var rxdr: Register + + /// Transmit data register + @RegisterBlock(offset: 0x28) + public var txdr: Register +} + +extension I2C1 { + /// Control register 1 + @Register(bitWidth: 32) + public struct CR1 { + /// Peripheral enable + @ReadWrite(bits: 0..<1, as: PEValues.self) + public var pe: PE + + /// TX Interrupt enable + @ReadWrite(bits: 1..<2, as: TXIEValues.self) + public var txie: TXIE + + /// RX Interrupt enable + @ReadWrite(bits: 2..<3, as: RXIEValues.self) + public var rxie: RXIE + + /// Address match interrupt enable (slave only) + @ReadWrite(bits: 3..<4, as: ADDRIEValues.self) + public var addrie: ADDRIE + + /// Not acknowledge received interrupt enable + @ReadWrite(bits: 4..<5, as: NACKIEValues.self) + public var nackie: NACKIE + + /// STOP detection Interrupt enable + @ReadWrite(bits: 5..<6, as: STOPIEValues.self) + public var stopie: STOPIE + + /// Transfer Complete interrupt enable + @ReadWrite(bits: 6..<7, as: TCIEValues.self) + public var tcie: TCIE + + /// Error interrupts enable + @ReadWrite(bits: 7..<8, as: ERRIEValues.self) + public var errie: ERRIE + + /// Digital noise filter + @ReadWrite(bits: 8..<12, as: DNFValues.self) + public var dnf: DNF + + /// Analog noise filter OFF + @ReadWrite(bits: 12..<13, as: ANFOFFValues.self) + public var anfoff: ANFOFF + + /// DMA transmission requests enable + @ReadWrite(bits: 14..<15, as: TXDMAENValues.self) + public var txdmaen: TXDMAEN + + /// DMA reception requests enable + @ReadWrite(bits: 15..<16, as: RXDMAENValues.self) + public var rxdmaen: RXDMAEN + + /// Slave byte control + @ReadWrite(bits: 16..<17, as: SBCValues.self) + public var sbc: SBC + + /// Clock stretching disable + @ReadWrite(bits: 17..<18, as: NOSTRETCHValues.self) + public var nostretch: NOSTRETCH + + /// Wakeup from STOP enable + @ReadWrite(bits: 18..<19, as: WUPENValues.self) + public var wupen: WUPEN + + /// General call enable + @ReadWrite(bits: 19..<20, as: GCENValues.self) + public var gcen: GCEN + + /// SMBus Host address enable + @ReadWrite(bits: 20..<21, as: SMBHENValues.self) + public var smbhen: SMBHEN + + /// SMBus Device Default address enable + @ReadWrite(bits: 21..<22, as: SMBDENValues.self) + public var smbden: SMBDEN + + /// SMBUS alert enable + @ReadWrite(bits: 22..<23, as: ALERTENValues.self) + public var alerten: ALERTEN + + /// PEC enable + @ReadWrite(bits: 23..<24, as: PECENValues.self) + public var pecen: PECEN + } + + /// Control register 2 + @Register(bitWidth: 32) + public struct CR2 { + /// Packet error checking byte + @ReadWrite(bits: 26..<27) + public var pecbyte: PECBYTE + + /// Automatic end mode (master mode) + @ReadWrite(bits: 25..<26, as: AUTOENDValues.self) + public var autoend: AUTOEND + + /// NBYTES reload mode + @ReadWrite(bits: 24..<25, as: RELOADValues.self) + public var reload: RELOAD + + /// Number of bytes + @ReadWrite(bits: 16..<24) + public var nbytes: NBYTES + + /// NACK generation (slave mode) + @ReadWrite(bits: 15..<16) + public var nack: NACK + + /// Stop generation (master mode) + @ReadWrite(bits: 14..<15) + public var stop: STOP + + /// Start generation + @ReadWrite(bits: 13..<14) + public var start: START + + /// 10-bit address header only read direction (master receiver mode) + @ReadWrite(bits: 12..<13, as: HEAD10RValues.self) + public var head10r: HEAD10R + + /// 10-bit addressing mode (master mode) + @ReadWrite(bits: 11..<12, as: ADD10Values.self) + public var add10: ADD10 + + /// Transfer direction (master mode) + @ReadWrite(bits: 10..<11, as: RD_WRNValues.self) + public var rd_wrn: RD_WRN + + /// Slave address bit (master mode) + @ReadWrite(bits: 0..<10) + public var sadd: SADD + } + + /// Own address register 1 + @Register(bitWidth: 32) + public struct OAR1 { + /// Interface address + @ReadWrite(bits: 0..<10) + public var oa1: OA1 + + /// Own Address 1 10-bit mode + @ReadWrite(bits: 10..<11, as: OA1MODEValues.self) + public var oa1mode: OA1MODE + + /// Own Address 1 enable + @ReadWrite(bits: 15..<16, as: OA1ENValues.self) + public var oa1en: OA1EN + } + + /// Own address register 2 + @Register(bitWidth: 32) + public struct OAR2 { + /// Interface address + @ReadWrite(bits: 1..<8) + public var oa2: OA2 + + /// Own Address 2 masks + @ReadWrite(bits: 8..<11, as: OA2MSKValues.self) + public var oa2msk: OA2MSK + + /// Own Address 2 enable + @ReadWrite(bits: 15..<16, as: OA2ENValues.self) + public var oa2en: OA2EN + } + + /// Timing register + @Register(bitWidth: 32) + public struct TIMINGR { + /// SCL low period (master mode) + @ReadWrite(bits: 0..<8) + public var scll: SCLL + + /// SCL high period (master mode) + @ReadWrite(bits: 8..<16) + public var sclh: SCLH + + /// Data hold time + @ReadWrite(bits: 16..<20) + public var sdadel: SDADEL + + /// Data setup time + @ReadWrite(bits: 20..<24) + public var scldel: SCLDEL + + /// Timing prescaler + @ReadWrite(bits: 28..<32) + public var presc: PRESC + } + + /// Status register 1 + @Register(bitWidth: 32) + public struct TIMEOUTR { + /// Bus timeout A + @ReadWrite(bits: 0..<12) + public var timeouta: TIMEOUTA + + /// Idle clock timeout detection + @ReadWrite(bits: 12..<13, as: TIDLEValues.self) + public var tidle: TIDLE + + /// Clock timeout enable + @ReadWrite(bits: 15..<16, as: TIMOUTENValues.self) + public var timouten: TIMOUTEN + + /// Bus timeout B + @ReadWrite(bits: 16..<28) + public var timeoutb: TIMEOUTB + + /// Extended clock timeout enable + @ReadWrite(bits: 31..<32, as: TEXTENValues.self) + public var texten: TEXTEN + } + + /// Interrupt and Status register + @Register(bitWidth: 32) + public struct ISR { + /// Address match code (Slave mode) + @ReadOnly(bits: 17..<24) + public var addcode: ADDCODE + + /// Transfer direction (Slave mode) + @ReadOnly(bits: 16..<17) + public var dir: DIR + + /// Bus busy + @ReadOnly(bits: 15..<16) + public var busy: BUSY + + /// SMBus alert + @ReadOnly(bits: 13..<14) + public var alert: ALERT + + /// Timeout or t_low detection flag + @ReadOnly(bits: 12..<13) + public var timeout: TIMEOUT + + /// PEC Error in reception + @ReadOnly(bits: 11..<12) + public var pecerr: PECERR + + /// Overrun/Underrun (slave mode) + @ReadOnly(bits: 10..<11) + public var ovr: OVR + + /// Arbitration lost + @ReadOnly(bits: 9..<10) + public var arlo: ARLO + + /// Bus error + @ReadOnly(bits: 8..<9) + public var berr: BERR + + /// Transfer Complete Reload + @ReadOnly(bits: 7..<8) + public var tcr: TCR + + /// Transfer Complete (master mode) + @ReadOnly(bits: 6..<7) + public var tc: TC + + /// Stop detection flag + @ReadOnly(bits: 5..<6) + public var stopf: STOPF + + /// Not acknowledge received flag + @ReadOnly(bits: 4..<5) + public var nackf: NACKF + + /// Address matched (slave mode) + @ReadOnly(bits: 3..<4) + public var addr: ADDR + + /// Receive data register not empty (receivers) + @ReadOnly(bits: 2..<3) + public var rxne: RXNE + + /// Transmit interrupt status (transmitters) + @ReadWrite(bits: 1..<2) + public var txis: TXIS + + /// Transmit data register empty (transmitters) + @ReadWrite(bits: 0..<1) + public var txe: TXE + } + + /// Interrupt clear register + @Register(bitWidth: 32) + public struct ICR { + /// Alert flag clear + @WriteOnly(bits: 13..<14) + public var alertcf: ALERTCF + + /// Timeout detection flag clear + @WriteOnly(bits: 12..<13) + public var timoutcf: TIMOUTCF + + /// PEC Error flag clear + @WriteOnly(bits: 11..<12) + public var peccf: PECCF + + /// Overrun/Underrun flag clear + @WriteOnly(bits: 10..<11) + public var ovrcf: OVRCF + + /// Arbitration lost flag clear + @WriteOnly(bits: 9..<10) + public var arlocf: ARLOCF + + /// Bus error flag clear + @WriteOnly(bits: 8..<9) + public var berrcf: BERRCF + + /// Stop detection flag clear + @WriteOnly(bits: 5..<6) + public var stopcf: STOPCF + + /// Not Acknowledge flag clear + @WriteOnly(bits: 4..<5) + public var nackcf: NACKCF + + /// Address Matched flag clear + @WriteOnly(bits: 3..<4) + public var addrcf: ADDRCF + } + + /// PEC register + @Register(bitWidth: 32) + public struct PECR { + /// Packet error checking register + @ReadOnly(bits: 0..<8) + public var pec: PEC + } + + /// Receive data register + @Register(bitWidth: 32) + public struct RXDR { + /// 8-bit receive data + @ReadOnly(bits: 0..<8) + public var rxdata: RXDATA + } + + /// Transmit data register + @Register(bitWidth: 32) + public struct TXDR { + /// 8-bit transmit data + @ReadWrite(bits: 0..<8) + public var txdata: TXDATA + } +} + +extension I2C1.CR1 { + public struct PEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Peripheral disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Peripheral enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR1 { + public struct TXIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Transmit (TXIS) interrupt disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Transmit (TXIS) interrupt enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR1 { + public struct RXIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Receive (RXNE) interrupt disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Receive (RXNE) interrupt enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR1 { + public struct ADDRIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Address match (ADDR) interrupts disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Address match (ADDR) interrupts enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR1 { + public struct NACKIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Not acknowledge (NACKF) received interrupts disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Not acknowledge (NACKF) received interrupts enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR1 { + public struct STOPIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Stop detection (STOPF) interrupt disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Stop detection (STOPF) interrupt enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR1 { + public struct TCIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Transfer Complete interrupt disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Transfer Complete interrupt enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR1 { + public struct ERRIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Error detection interrupts disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Error detection interrupts enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR1 { + public struct DNFValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 4 + + /// Digital filter disabled + public static let NoFilter = Self(rawValue: 0x0) + + /// Digital filter enabled and filtering capability up to 1 tI2CCLK + public static let Filter1 = Self(rawValue: 0x1) + + /// Digital filter enabled and filtering capability up to 2 tI2CCLK + public static let Filter2 = Self(rawValue: 0x2) + + /// Digital filter enabled and filtering capability up to 3 tI2CCLK + public static let Filter3 = Self(rawValue: 0x3) + + /// Digital filter enabled and filtering capability up to 4 tI2CCLK + public static let Filter4 = Self(rawValue: 0x4) + + /// Digital filter enabled and filtering capability up to 5 tI2CCLK + public static let Filter5 = Self(rawValue: 0x5) + + /// Digital filter enabled and filtering capability up to 6 tI2CCLK + public static let Filter6 = Self(rawValue: 0x6) + + /// Digital filter enabled and filtering capability up to 7 tI2CCLK + public static let Filter7 = Self(rawValue: 0x7) + + /// Digital filter enabled and filtering capability up to 8 tI2CCLK + public static let Filter8 = Self(rawValue: 0x8) + + /// Digital filter enabled and filtering capability up to 9 tI2CCLK + public static let Filter9 = Self(rawValue: 0x9) + + /// Digital filter enabled and filtering capability up to 10 tI2CCLK + public static let Filter10 = Self(rawValue: 0xa) + + /// Digital filter enabled and filtering capability up to 11 tI2CCLK + public static let Filter11 = Self(rawValue: 0xb) + + /// Digital filter enabled and filtering capability up to 12 tI2CCLK + public static let Filter12 = Self(rawValue: 0xc) + + /// Digital filter enabled and filtering capability up to 13 tI2CCLK + public static let Filter13 = Self(rawValue: 0xd) + + /// Digital filter enabled and filtering capability up to 14 tI2CCLK + public static let Filter14 = Self(rawValue: 0xe) + + /// Digital filter enabled and filtering capability up to 15 tI2CCLK + public static let Filter15 = Self(rawValue: 0xf) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR1 { + public struct ANFOFFValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Analog noise filter enabled + public static let Enabled = Self(rawValue: 0x0) + + /// Analog noise filter disabled + public static let Disabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR1 { + public struct TXDMAENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// DMA mode disabled for transmission + public static let Disabled = Self(rawValue: 0x0) + + /// DMA mode enabled for transmission + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR1 { + public struct RXDMAENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// DMA mode disabled for reception + public static let Disabled = Self(rawValue: 0x0) + + /// DMA mode enabled for reception + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR1 { + public struct SBCValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Slave byte control disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Slave byte control enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR1 { + public struct NOSTRETCHValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Clock stretching enabled + public static let Enabled = Self(rawValue: 0x0) + + /// Clock stretching disabled + public static let Disabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR1 { + public struct WUPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Wakeup from Stop mode disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Wakeup from Stop mode enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR1 { + public struct GCENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// General call disabled. Address 0b00000000 is NACKed + public static let Disabled = Self(rawValue: 0x0) + + /// General call enabled. Address 0b00000000 is ACKed + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR1 { + public struct SMBHENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Host address disabled. Address 0b0001000x is NACKed + public static let Disabled = Self(rawValue: 0x0) + + /// Host address enabled. Address 0b0001000x is ACKed + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR1 { + public struct SMBDENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Device default address disabled. Address 0b1100001x is NACKed + public static let Disabled = Self(rawValue: 0x0) + + /// Device default address enabled. Address 0b1100001x is ACKed + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR1 { + public struct ALERTENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported + public static let Disabled = Self(rawValue: 0x0) + + /// In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR1 { + public struct PECENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// PEC calculation disabled + public static let Disabled = Self(rawValue: 0x0) + + /// PEC calculation enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR2 { + public struct AUTOENDValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low + public static let Software = Self(rawValue: 0x0) + + /// Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred + public static let Automatic = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR2 { + public struct RELOADValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) + public static let Completed = Self(rawValue: 0x0) + + /// The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) + public static let NotCompleted = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR2 { + public struct HEAD10RValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// The master sends the complete 10 bit slave address read sequence + public static let Complete = Self(rawValue: 0x0) + + /// The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction + public static let Partial = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR2 { + public struct ADD10Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// The master operates in 7-bit addressing mode + public static let Bit7 = Self(rawValue: 0x0) + + /// The master operates in 10-bit addressing mode + public static let Bit10 = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.CR2 { + public struct RD_WRNValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Master requests a write transfer + public static let Write = Self(rawValue: 0x0) + + /// Master requests a read transfer + public static let Read = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.OAR1 { + public struct OA1MODEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Own address 1 is a 7-bit address + public static let Bit7 = Self(rawValue: 0x0) + + /// Own address 1 is a 10-bit address + public static let Bit10 = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.OAR1 { + public struct OA1ENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Own address 1 disabled. The received slave address OA1 is NACKed + public static let Disabled = Self(rawValue: 0x0) + + /// Own address 1 enabled. The received slave address OA1 is ACKed + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.OAR2 { + public struct OA2MSKValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 3 + + /// No mask + public static let NoMask = Self(rawValue: 0x0) + + /// OA2[1] is masked and don’t care. Only OA2[7:2] are compared + public static let Mask1 = Self(rawValue: 0x1) + + /// OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared + public static let Mask2 = Self(rawValue: 0x2) + + /// OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared + public static let Mask3 = Self(rawValue: 0x3) + + /// OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared + public static let Mask4 = Self(rawValue: 0x4) + + /// OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared + public static let Mask5 = Self(rawValue: 0x5) + + /// OA2[6:1] are masked and don’t care. Only OA2[7] is compared. + public static let Mask6 = Self(rawValue: 0x6) + + /// OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged + public static let Mask7 = Self(rawValue: 0x7) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.OAR2 { + public struct OA2ENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Own address 2 disabled. The received slave address OA2 is NACKed + public static let Disabled = Self(rawValue: 0x0) + + /// Own address 2 enabled. The received slave address OA2 is ACKed + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.TIMEOUTR { + public struct TIDLEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// TIMEOUTA is used to detect SCL low timeout + public static let Disabled = Self(rawValue: 0x0) + + /// TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.TIMEOUTR { + public struct TIMOUTENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// SCL timeout detection is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// SCL timeout detection is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension I2C1.TIMEOUTR { + public struct TEXTENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Extended clock timeout detection is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Extended clock timeout detection is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} diff --git a/stm32-lvgl/Sources/Registers/I2C2.swift b/stm32-lvgl/Sources/Registers/I2C2.swift new file mode 100644 index 0000000..a10d209 --- /dev/null +++ b/stm32-lvgl/Sources/Registers/I2C2.swift @@ -0,0 +1,7 @@ +// Generated by svd2swift. + +import MMIO + +/// Inter-integrated circuit +public typealias I2C2 = I2C1 + diff --git a/stm32-lvgl/Sources/Registers/I2C3.swift b/stm32-lvgl/Sources/Registers/I2C3.swift new file mode 100644 index 0000000..e05597b --- /dev/null +++ b/stm32-lvgl/Sources/Registers/I2C3.swift @@ -0,0 +1,7 @@ +// Generated by svd2swift. + +import MMIO + +/// Inter-integrated circuit +public typealias I2C3 = I2C1 + diff --git a/stm32-lvgl/Sources/Registers/I2C4.swift b/stm32-lvgl/Sources/Registers/I2C4.swift new file mode 100644 index 0000000..bbfbd90 --- /dev/null +++ b/stm32-lvgl/Sources/Registers/I2C4.swift @@ -0,0 +1,7 @@ +// Generated by svd2swift. + +import MMIO + +/// Inter-integrated circuit +public typealias I2C4 = I2C1 + diff --git a/stm32-lvgl/Sources/Registers/LTDC.swift b/stm32-lvgl/Sources/Registers/LTDC.swift new file mode 100644 index 0000000..d5d4614 --- /dev/null +++ b/stm32-lvgl/Sources/Registers/LTDC.swift @@ -0,0 +1,847 @@ +// Generated by svd2swift. + +import MMIO + +/// LCD-TFT Controller +@RegisterBlock +public struct LTDC { + /// Synchronization Size Configuration Register + @RegisterBlock(offset: 0x8) + public var sscr: Register + + /// Back Porch Configuration Register + @RegisterBlock(offset: 0xc) + public var bpcr: Register + + /// Active Width Configuration Register + @RegisterBlock(offset: 0x10) + public var awcr: Register + + /// Total Width Configuration Register + @RegisterBlock(offset: 0x14) + public var twcr: Register + + /// Global Control Register + @RegisterBlock(offset: 0x18) + public var gcr: Register + + /// Shadow Reload Configuration Register + @RegisterBlock(offset: 0x24) + public var srcr: Register + + /// Background Color Configuration Register + @RegisterBlock(offset: 0x2c) + public var bccr: Register + + /// Interrupt Enable Register + @RegisterBlock(offset: 0x34) + public var ier: Register + + /// Interrupt Status Register + @RegisterBlock(offset: 0x38) + public var isr: Register + + /// Interrupt Clear Register + @RegisterBlock(offset: 0x3c) + public var icr: Register + + /// Line Interrupt Position Configuration Register + @RegisterBlock(offset: 0x40) + public var lipcr: Register + + /// Current Position Status Register + @RegisterBlock(offset: 0x44) + public var cpsr: Register + + /// Current Display Status Register + @RegisterBlock(offset: 0x48) + public var cdsr: Register + + /// Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR + @RegisterBlock(offset: 0x84, stride: 0x80, count: 2) + public var layer: RegisterArray +} + +extension LTDC { + /// Synchronization Size Configuration Register + @Register(bitWidth: 32) + public struct SSCR { + /// Horizontal Synchronization Width (in units of pixel clock period) + @ReadWrite(bits: 16..<28) + public var hsw: HSW + + /// Vertical Synchronization Height (in units of horizontal scan line) + @ReadWrite(bits: 0..<11) + public var vsh: VSH + } + + /// Back Porch Configuration Register + @Register(bitWidth: 32) + public struct BPCR { + /// Accumulated Horizontal back porch (in units of pixel clock period) + @ReadWrite(bits: 16..<28) + public var ahbp: AHBP + + /// Accumulated Vertical back porch (in units of horizontal scan line) + @ReadWrite(bits: 0..<11) + public var avbp: AVBP + } + + /// Active Width Configuration Register + @Register(bitWidth: 32) + public struct AWCR { + /// Accumulated Active Width (in units of pixel clock period) + @ReadWrite(bits: 16..<28) + public var aaw: AAW + + /// Accumulated Active Height (in units of horizontal scan line) + @ReadWrite(bits: 0..<11) + public var aah: AAH + } + + /// Total Width Configuration Register + @Register(bitWidth: 32) + public struct TWCR { + /// Total Width (in units of pixel clock period) + @ReadWrite(bits: 16..<28) + public var totalw: TOTALW + + /// Total Height (in units of horizontal scan line) + @ReadWrite(bits: 0..<11) + public var totalh: TOTALH + } + + /// Global Control Register + @Register(bitWidth: 32) + public struct GCR { + /// Horizontal Synchronization Polarity + @ReadWrite(bits: 31..<32, as: HSPOLValues.self) + public var hspol: HSPOL + + /// Vertical Synchronization Polarity + @ReadWrite(bits: 30..<31, as: VSPOLValues.self) + public var vspol: VSPOL + + /// Data Enable Polarity + @ReadWrite(bits: 29..<30, as: DEPOLValues.self) + public var depol: DEPOL + + /// Pixel Clock Polarity + @ReadWrite(bits: 28..<29, as: PCPOLValues.self) + public var pcpol: PCPOL + + /// Dither Enable + @ReadWrite(bits: 16..<17, as: DENValues.self) + public var den: DEN + + /// Dither Red Width + @ReadOnly(bits: 12..<15) + public var drw: DRW + + /// Dither Green Width + @ReadOnly(bits: 8..<11) + public var dgw: DGW + + /// Dither Blue Width + @ReadOnly(bits: 4..<7) + public var dbw: DBW + + /// LCD-TFT controller enable bit + @ReadWrite(bits: 0..<1, as: LTDCENValues.self) + public var ltdcen: LTDCEN + } + + /// Shadow Reload Configuration Register + @Register(bitWidth: 32) + public struct SRCR { + /// Vertical Blanking Reload + @ReadWrite(bits: 1..<2, as: VBRValues.self) + public var vbr: VBR + + /// Immediate Reload + @ReadWrite(bits: 0..<1, as: IMRValues.self) + public var imr: IMR + } + + /// Background Color Configuration Register + @Register(bitWidth: 32) + public struct BCCR { + /// Background color blue value + @ReadWrite(bits: 0..<8) + public var bcblue: BCBLUE + + /// Background color green value + @ReadWrite(bits: 8..<16) + public var bcgreen: BCGREEN + + /// Background color red value + @ReadWrite(bits: 16..<24) + public var bcred: BCRED + } + + /// Interrupt Enable Register + @Register(bitWidth: 32) + public struct IER { + /// Register Reload interrupt enable + @ReadWrite(bits: 3..<4, as: RRIEValues.self) + public var rrie: RRIE + + /// Transfer Error Interrupt Enable + @ReadWrite(bits: 2..<3, as: TERRIEValues.self) + public var terrie: TERRIE + + /// FIFO Underrun Interrupt Enable + @ReadWrite(bits: 1..<2, as: FUIEValues.self) + public var fuie: FUIE + + /// Line Interrupt Enable + @ReadWrite(bits: 0..<1, as: LIEValues.self) + public var lie: LIE + } + + /// Interrupt Status Register + @Register(bitWidth: 32) + public struct ISR { + /// Register Reload Interrupt Flag + @ReadOnly(bits: 3..<4) + public var rrif: RRIF + + /// Transfer Error interrupt flag + @ReadOnly(bits: 2..<3) + public var terrif: TERRIF + + /// FIFO Underrun Interrupt flag + @ReadOnly(bits: 1..<2) + public var fuif: FUIF + + /// Line Interrupt flag + @ReadOnly(bits: 0..<1) + public var lif: LIF + } + + /// Interrupt Clear Register + @Register(bitWidth: 32) + public struct ICR { + /// Clears Register Reload Interrupt Flag + @WriteOnly(bits: 3..<4) + public var crrif: CRRIF + + /// Clears the Transfer Error Interrupt Flag + @WriteOnly(bits: 2..<3) + public var cterrif: CTERRIF + + /// Clears the FIFO Underrun Interrupt flag + @WriteOnly(bits: 1..<2) + public var cfuif: CFUIF + + /// Clears the Line Interrupt Flag + @WriteOnly(bits: 0..<1) + public var clif: CLIF + } + + /// Line Interrupt Position Configuration Register + @Register(bitWidth: 32) + public struct LIPCR { + /// Line Interrupt Position + @ReadWrite(bits: 0..<11) + public var lipos: LIPOS + } + + /// Current Position Status Register + @Register(bitWidth: 32) + public struct CPSR { + /// Current X Position + @ReadOnly(bits: 16..<32) + public var cxpos: CXPOS + + /// Current Y Position + @ReadOnly(bits: 0..<16) + public var cypos: CYPOS + } + + /// Current Display Status Register + @Register(bitWidth: 32) + public struct CDSR { + /// Horizontal Synchronization display Status + @ReadOnly(bits: 3..<4) + public var hsyncs: HSYNCS + + /// Vertical Synchronization display Status + @ReadOnly(bits: 2..<3) + public var vsyncs: VSYNCS + + /// Horizontal Data Enable display Status + @ReadOnly(bits: 1..<2) + public var hdes: HDES + + /// Vertical Data Enable display Status + @ReadOnly(bits: 0..<1) + public var vdes: VDES + } + + /// Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR + @RegisterBlock + public struct LAYER { + /// Layerx Control Register + @RegisterBlock(offset: 0x0) + public var cr: Register + + /// Layerx Window Horizontal Position Configuration Register + @RegisterBlock(offset: 0x4) + public var whpcr: Register + + /// Layerx Window Vertical Position Configuration Register + @RegisterBlock(offset: 0x8) + public var wvpcr: Register + + /// Layerx Color Keying Configuration Register + @RegisterBlock(offset: 0xc) + public var ckcr: Register + + /// Layerx Pixel Format Configuration Register + @RegisterBlock(offset: 0x10) + public var pfcr: Register + + /// Layerx Constant Alpha Configuration Register + @RegisterBlock(offset: 0x14) + public var cacr: Register + + /// Layerx Default Color Configuration Register + @RegisterBlock(offset: 0x18) + public var dccr: Register + + /// Layerx Blending Factors Configuration Register + @RegisterBlock(offset: 0x1c) + public var bfcr: Register + + /// Layerx Color Frame Buffer Address Register + @RegisterBlock(offset: 0x28) + public var cfbar: Register + + /// Layerx Color Frame Buffer Length Register + @RegisterBlock(offset: 0x2c) + public var cfblr: Register + + /// Layerx ColorFrame Buffer Line Number Register + @RegisterBlock(offset: 0x30) + public var cfblnr: Register + + /// Layerx CLUT Write Register + @RegisterBlock(offset: 0x40) + public var clutwr: Register + } +} + +extension LTDC.LAYER { + /// Layerx Control Register + @Register(bitWidth: 32) + public struct CR { + /// Color Look-Up Table Enable + @ReadWrite(bits: 4..<5, as: CLUTENValues.self) + public var cluten: CLUTEN + + /// Color Keying Enable + @ReadWrite(bits: 1..<2, as: COLKENValues.self) + public var colken: COLKEN + + /// Layer Enable + @ReadWrite(bits: 0..<1, as: LENValues.self) + public var len: LEN + } + + /// Layerx Window Horizontal Position Configuration Register + @Register(bitWidth: 32) + public struct WHPCR { + /// Window Horizontal Stop Position + @ReadWrite(bits: 16..<28) + public var whsppos: WHSPPOS + + /// Window Horizontal Start Position + @ReadWrite(bits: 0..<12) + public var whstpos: WHSTPOS + } + + /// Layerx Window Vertical Position Configuration Register + @Register(bitWidth: 32) + public struct WVPCR { + /// Window Vertical Stop Position + @ReadWrite(bits: 16..<27) + public var wvsppos: WVSPPOS + + /// Window Vertical Start Position + @ReadWrite(bits: 0..<11) + public var wvstpos: WVSTPOS + } + + /// Layerx Color Keying Configuration Register + @Register(bitWidth: 32) + public struct CKCR { + /// Color Key Red value + @ReadWrite(bits: 16..<24) + public var ckred: CKRED + + /// Color Key Green value + @ReadWrite(bits: 8..<16) + public var ckgreen: CKGREEN + + /// Color Key Blue value + @ReadWrite(bits: 0..<8) + public var ckblue: CKBLUE + } + + /// Layerx Pixel Format Configuration Register + @Register(bitWidth: 32) + public struct PFCR { + /// Pixel Format + @ReadWrite(bits: 0..<3, as: PFValues.self) + public var pf: PF + } + + /// Layerx Constant Alpha Configuration Register + @Register(bitWidth: 32) + public struct CACR { + /// Constant Alpha + @ReadWrite(bits: 0..<8) + public var consta: CONSTA + } + + /// Layerx Default Color Configuration Register + @Register(bitWidth: 32) + public struct DCCR { + /// Default Color Alpha + @ReadWrite(bits: 24..<32) + public var dcalpha: DCALPHA + + /// Default Color Red + @ReadWrite(bits: 16..<24) + public var dcred: DCRED + + /// Default Color Green + @ReadWrite(bits: 8..<16) + public var dcgreen: DCGREEN + + /// Default Color Blue + @ReadWrite(bits: 0..<8) + public var dcblue: DCBLUE + } + + /// Layerx Blending Factors Configuration Register + @Register(bitWidth: 32) + public struct BFCR { + /// Blending Factor 1 + @ReadWrite(bits: 8..<11, as: BF1Values.self) + public var bf1: BF1 + + /// Blending Factor 2 + @ReadWrite(bits: 0..<3, as: BF2Values.self) + public var bf2: BF2 + } + + /// Layerx Color Frame Buffer Address Register + @Register(bitWidth: 32) + public struct CFBAR { + /// Color Frame Buffer Start Address + @ReadWrite(bits: 0..<32) + public var cfbadd: CFBADD + } + + /// Layerx Color Frame Buffer Length Register + @Register(bitWidth: 32) + public struct CFBLR { + /// Color Frame Buffer Pitch in bytes + @ReadWrite(bits: 16..<29) + public var cfbp: CFBP + + /// Color Frame Buffer Line Length + @ReadWrite(bits: 0..<13) + public var cfbll: CFBLL + } + + /// Layerx ColorFrame Buffer Line Number Register + @Register(bitWidth: 32) + public struct CFBLNR { + /// Frame Buffer Line Number + @ReadWrite(bits: 0..<11) + public var cfblnbr: CFBLNBR + } + + /// Layerx CLUT Write Register + @Register(bitWidth: 32) + public struct CLUTWR { + /// CLUT Address + @WriteOnly(bits: 24..<32) + public var clutadd: CLUTADD + + /// Red value + @WriteOnly(bits: 16..<24) + public var red: RED + + /// Green value + @WriteOnly(bits: 8..<16) + public var green: GREEN + + /// Blue value + @WriteOnly(bits: 0..<8) + public var blue: BLUE + } +} + +extension LTDC.GCR { + public struct HSPOLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Horizontal synchronization polarity is active low + public static let ActiveLow = Self(rawValue: 0x0) + + /// Horizontal synchronization polarity is active high + public static let ActiveHigh = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension LTDC.GCR { + public struct VSPOLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Vertical synchronization polarity is active low + public static let ActiveLow = Self(rawValue: 0x0) + + /// Vertical synchronization polarity is active high + public static let ActiveHigh = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension LTDC.GCR { + public struct DEPOLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Data enable polarity is active low + public static let ActiveLow = Self(rawValue: 0x0) + + /// Data enable polarity is active high + public static let ActiveHigh = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension LTDC.GCR { + public struct PCPOLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Pixel clock on rising edge + public static let RisingEdge = Self(rawValue: 0x0) + + /// Pixel clock on falling edge + public static let FallingEdge = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension LTDC.GCR { + public struct DENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Dither disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Dither enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension LTDC.GCR { + public struct LTDCENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// LCD-TFT controller disabled + public static let Disabled = Self(rawValue: 0x0) + + /// LCD-TFT controller enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension LTDC.SRCR { + public struct VBRValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) + public static let NoEffect = Self(rawValue: 0x0) + + /// The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). + public static let Reload = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension LTDC.SRCR { + public struct IMRValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set) + public static let NoEffect = Self(rawValue: 0x0) + + /// The shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload + public static let Reload = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension LTDC.IER { + public struct RRIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Register reload interrupt disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Register reload interrupt enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension LTDC.IER { + public struct TERRIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Transfer error interrupt disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Transfer error interrupt enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension LTDC.IER { + public struct FUIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// FIFO underrun interrupt disabled + public static let Disabled = Self(rawValue: 0x0) + + /// FIFO underrun interrupt enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension LTDC.IER { + public struct LIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Line interrupt disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Line interrupt enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension LTDC.LAYER.CR { + public struct CLUTENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Color look-up table disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Color look-up table enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension LTDC.LAYER.CR { + public struct COLKENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Color keying disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Color keying enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension LTDC.LAYER.CR { + public struct LENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Layer disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Layer enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension LTDC.LAYER.PFCR { + public struct PFValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 3 + + /// ARGB8888 + public static let ARGB8888 = Self(rawValue: 0x0) + + /// RGB888 + public static let RGB888 = Self(rawValue: 0x1) + + /// RGB565 + public static let RGB565 = Self(rawValue: 0x2) + + /// ARGB1555 + public static let ARGB1555 = Self(rawValue: 0x3) + + /// ARGB4444 + public static let ARGB4444 = Self(rawValue: 0x4) + + /// L8 (8-bit luminance) + public static let L8 = Self(rawValue: 0x5) + + /// AL44 (4-bit alpha, 4-bit luminance) + public static let AL44 = Self(rawValue: 0x6) + + /// AL88 (8-bit alpha, 8-bit luminance) + public static let AL88 = Self(rawValue: 0x7) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension LTDC.LAYER.BFCR { + public struct BF1Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 3 + + /// BF1 = constant alpha + public static let Constant = Self(rawValue: 0x4) + + /// BF1 = pixel alpha * constant alpha + public static let Pixel = Self(rawValue: 0x6) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension LTDC.LAYER.BFCR { + public struct BF2Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 3 + + /// BF2 = 1 - constant alpha + public static let Constant = Self(rawValue: 0x5) + + /// BF2 = 1 - pixel alpha * constant alpha + public static let Pixel = Self(rawValue: 0x7) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} diff --git a/stm32-lvgl/Sources/Registers/NVIC.swift b/stm32-lvgl/Sources/Registers/NVIC.swift new file mode 100644 index 0000000..9876eea --- /dev/null +++ b/stm32-lvgl/Sources/Registers/NVIC.swift @@ -0,0 +1,813 @@ +// Generated by svd2swift. + +import MMIO + +/// Nested Vectored Interrupt Controller +@RegisterBlock +public struct NVIC { + /// Interrupt Set-Enable Register + @RegisterBlock(offset: 0x0) + public var iser0: Register + + /// Interrupt Set-Enable Register + @RegisterBlock(offset: 0x4) + public var iser1: Register + + /// Interrupt Set-Enable Register + @RegisterBlock(offset: 0x8) + public var iser2: Register + + /// Interrupt Clear-Enable Register + @RegisterBlock(offset: 0x80) + public var icer0: Register + + /// Interrupt Clear-Enable Register + @RegisterBlock(offset: 0x84) + public var icer1: Register + + /// Interrupt Clear-Enable Register + @RegisterBlock(offset: 0x88) + public var icer2: Register + + /// Interrupt Set-Pending Register + @RegisterBlock(offset: 0x100) + public var ispr0: Register + + /// Interrupt Set-Pending Register + @RegisterBlock(offset: 0x104) + public var ispr1: Register + + /// Interrupt Set-Pending Register + @RegisterBlock(offset: 0x108) + public var ispr2: Register + + /// Interrupt Clear-Pending Register + @RegisterBlock(offset: 0x180) + public var icpr0: Register + + /// Interrupt Clear-Pending Register + @RegisterBlock(offset: 0x184) + public var icpr1: Register + + /// Interrupt Clear-Pending Register + @RegisterBlock(offset: 0x188) + public var icpr2: Register + + /// Interrupt Active Bit Register + @RegisterBlock(offset: 0x200) + public var iabr0: Register + + /// Interrupt Active Bit Register + @RegisterBlock(offset: 0x204) + public var iabr1: Register + + /// Interrupt Active Bit Register + @RegisterBlock(offset: 0x208) + public var iabr2: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x300) + public var ipr0: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x304) + public var ipr1: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x308) + public var ipr2: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x30c) + public var ipr3: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x310) + public var ipr4: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x314) + public var ipr5: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x318) + public var ipr6: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x31c) + public var ipr7: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x320) + public var ipr8: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x324) + public var ipr9: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x328) + public var ipr10: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x32c) + public var ipr11: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x330) + public var ipr12: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x334) + public var ipr13: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x338) + public var ipr14: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x33c) + public var ipr15: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x340) + public var ipr16: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x344) + public var ipr17: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x348) + public var ipr18: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x34c) + public var ipr19: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x350) + public var ipr20: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x354) + public var ipr21: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x358) + public var ipr22: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x35c) + public var ipr23: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x360) + public var ipr24: Register + + /// Interrupt Priority Register + @RegisterBlock(offset: 0x364) + public var ipr25: Register +} + +extension NVIC { + /// Interrupt Set-Enable Register + @Register(bitWidth: 32) + public struct ISER0 { + /// SETENA + @ReadWrite(bits: 0..<32) + public var setena: SETENA + } + + /// Interrupt Set-Enable Register + @Register(bitWidth: 32) + public struct ISER1 { + /// SETENA + @ReadWrite(bits: 0..<32) + public var setena: SETENA + } + + /// Interrupt Set-Enable Register + @Register(bitWidth: 32) + public struct ISER2 { + /// SETENA + @ReadWrite(bits: 0..<32) + public var setena: SETENA + } + + /// Interrupt Clear-Enable Register + @Register(bitWidth: 32) + public struct ICER0 { + /// CLRENA + @ReadWrite(bits: 0..<32) + public var clrena: CLRENA + } + + /// Interrupt Clear-Enable Register + @Register(bitWidth: 32) + public struct ICER1 { + /// CLRENA + @ReadWrite(bits: 0..<32) + public var clrena: CLRENA + } + + /// Interrupt Clear-Enable Register + @Register(bitWidth: 32) + public struct ICER2 { + /// CLRENA + @ReadWrite(bits: 0..<32) + public var clrena: CLRENA + } + + /// Interrupt Set-Pending Register + @Register(bitWidth: 32) + public struct ISPR0 { + /// SETPEND + @ReadWrite(bits: 0..<32) + public var setpend: SETPEND + } + + /// Interrupt Set-Pending Register + @Register(bitWidth: 32) + public struct ISPR1 { + /// SETPEND + @ReadWrite(bits: 0..<32) + public var setpend: SETPEND + } + + /// Interrupt Set-Pending Register + @Register(bitWidth: 32) + public struct ISPR2 { + /// SETPEND + @ReadWrite(bits: 0..<32) + public var setpend: SETPEND + } + + /// Interrupt Clear-Pending Register + @Register(bitWidth: 32) + public struct ICPR0 { + /// CLRPEND + @ReadWrite(bits: 0..<32) + public var clrpend: CLRPEND + } + + /// Interrupt Clear-Pending Register + @Register(bitWidth: 32) + public struct ICPR1 { + /// CLRPEND + @ReadWrite(bits: 0..<32) + public var clrpend: CLRPEND + } + + /// Interrupt Clear-Pending Register + @Register(bitWidth: 32) + public struct ICPR2 { + /// CLRPEND + @ReadWrite(bits: 0..<32) + public var clrpend: CLRPEND + } + + /// Interrupt Active Bit Register + @Register(bitWidth: 32) + public struct IABR0 { + /// ACTIVE + @ReadOnly(bits: 0..<32) + public var active: ACTIVE + } + + /// Interrupt Active Bit Register + @Register(bitWidth: 32) + public struct IABR1 { + /// ACTIVE + @ReadOnly(bits: 0..<32) + public var active: ACTIVE + } + + /// Interrupt Active Bit Register + @Register(bitWidth: 32) + public struct IABR2 { + /// ACTIVE + @ReadOnly(bits: 0..<32) + public var active: ACTIVE + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR0 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR1 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR2 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR3 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR4 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR5 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR6 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR7 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR8 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR9 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR10 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR11 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR12 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR13 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR14 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR15 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR16 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR17 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR18 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR19 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR20 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR21 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR22 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR23 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR24 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } + + /// Interrupt Priority Register + @Register(bitWidth: 32) + public struct IPR25 { + /// IPR_N0 + @ReadWrite(bits: 0..<8) + public var ipr_n0: IPR_N0 + + /// IPR_N1 + @ReadWrite(bits: 8..<16) + public var ipr_n1: IPR_N1 + + /// IPR_N2 + @ReadWrite(bits: 16..<24) + public var ipr_n2: IPR_N2 + + /// IPR_N3 + @ReadWrite(bits: 24..<32) + public var ipr_n3: IPR_N3 + } +} diff --git a/stm32-lvgl/Sources/Registers/PWR.swift b/stm32-lvgl/Sources/Registers/PWR.swift new file mode 100644 index 0000000..eb8cdca --- /dev/null +++ b/stm32-lvgl/Sources/Registers/PWR.swift @@ -0,0 +1,270 @@ +// Generated by svd2swift. + +import MMIO + +/// Power control +@RegisterBlock +public struct PWR { + /// power control register + @RegisterBlock(offset: 0x0) + public var cr1: Register + + /// power control/status register + @RegisterBlock(offset: 0x4) + public var csr1: Register + + /// power control register + @RegisterBlock(offset: 0x8) + public var cr2: Register + + /// power control/status register + @RegisterBlock(offset: 0xc) + public var csr2: Register +} + +extension PWR { + /// power control register + @Register(bitWidth: 32) + public struct CR1 { + /// Low-power deep sleep + @ReadWrite(bits: 0..<1) + public var lpds: LPDS + + /// Power down deepsleep + @ReadWrite(bits: 1..<2, as: PDDSValues.self) + public var pdds: PDDS + + /// Clear standby flag + @ReadWrite(bits: 3..<4) + public var csbf: CSBF + + /// Power voltage detector enable + @ReadWrite(bits: 4..<5) + public var pvde: PVDE + + /// PVD level selection + @ReadWrite(bits: 5..<8) + public var pls: PLS + + /// Disable backup domain write protection + @ReadWrite(bits: 8..<9) + public var dbp: DBP + + /// Flash power down in Stop mode + @ReadWrite(bits: 9..<10) + public var fpds: FPDS + + /// Low-power regulator in deepsleep under-drive mode + @ReadWrite(bits: 10..<11) + public var lpuds: LPUDS + + /// Main regulator in deepsleep under-drive mode + @ReadWrite(bits: 11..<12) + public var mruds: MRUDS + + /// ADCDC1 + @ReadWrite(bits: 13..<14) + public var adcdc1: ADCDC1 + + /// Regulator voltage scaling output selection + @ReadWrite(bits: 14..<16, as: VOSValues.self) + public var vos: VOS + + /// Over-drive enable + @ReadWrite(bits: 16..<17) + public var oden: ODEN + + /// Over-drive switching enabled + @ReadWrite(bits: 17..<18) + public var odswen: ODSWEN + + /// Under-drive enable in stop mode + @ReadWrite(bits: 18..<20) + public var uden: UDEN + } + + /// power control/status register + @Register(bitWidth: 32) + public struct CSR1 { + /// Wakeup internal flag + @ReadOnly(bits: 0..<1) + public var wuif: WUIF + + /// Standby flag + @ReadOnly(bits: 1..<2) + public var sbf: SBF + + /// PVD output + @ReadOnly(bits: 2..<3) + public var pvdo: PVDO + + /// Backup regulator ready + @ReadOnly(bits: 3..<4) + public var brr: BRR + + /// Backup regulator enable + @ReadWrite(bits: 9..<10) + public var bre: BRE + + /// Regulator voltage scaling output selection ready bit + @ReadWrite(bits: 14..<15) + public var vosrdy: VOSRDY + + /// Over-drive mode ready + @ReadWrite(bits: 16..<17) + public var odrdy: ODRDY + + /// Over-drive mode switching ready + @ReadWrite(bits: 17..<18) + public var odswrdy: ODSWRDY + + /// Under-drive ready flag + @ReadWrite(bits: 18..<20) + public var udrdy: UDRDY + } + + /// power control register + @Register(bitWidth: 32) + public struct CR2 { + /// Clear Wakeup Pin flag for PA0 + @ReadOnly(bits: 0..<1) + public var cwupf1: CWUPF1 + + /// Clear Wakeup Pin flag for PA2 + @ReadOnly(bits: 1..<2) + public var cwupf2: CWUPF2 + + /// Clear Wakeup Pin flag for PC1 + @ReadOnly(bits: 2..<3) + public var cwupf3: CWUPF3 + + /// Clear Wakeup Pin flag for PC13 + @ReadOnly(bits: 3..<4) + public var cwupf4: CWUPF4 + + /// Clear Wakeup Pin flag for PI8 + @ReadOnly(bits: 4..<5) + public var cwupf5: CWUPF5 + + /// Clear Wakeup Pin flag for PI11 + @ReadOnly(bits: 5..<6) + public var cwupf6: CWUPF6 + + /// Wakeup pin polarity bit for PA0 + @ReadWrite(bits: 8..<9) + public var wupp1: WUPP1 + + /// Wakeup pin polarity bit for PA2 + @ReadWrite(bits: 9..<10) + public var wupp2: WUPP2 + + /// Wakeup pin polarity bit for PC1 + @ReadWrite(bits: 10..<11) + public var wupp3: WUPP3 + + /// Wakeup pin polarity bit for PC13 + @ReadWrite(bits: 11..<12) + public var wupp4: WUPP4 + + /// Wakeup pin polarity bit for PI8 + @ReadWrite(bits: 12..<13) + public var wupp5: WUPP5 + + /// Wakeup pin polarity bit for PI11 + @ReadWrite(bits: 13..<14) + public var wupp6: WUPP6 + } + + /// power control/status register + @Register(bitWidth: 32) + public struct CSR2 { + /// Wakeup Pin flag for PA0 + @ReadOnly(bits: 0..<1) + public var wupf1: WUPF1 + + /// Wakeup Pin flag for PA2 + @ReadOnly(bits: 1..<2) + public var wupf2: WUPF2 + + /// Wakeup Pin flag for PC1 + @ReadOnly(bits: 2..<3) + public var wupf3: WUPF3 + + /// Wakeup Pin flag for PC13 + @ReadOnly(bits: 3..<4) + public var wupf4: WUPF4 + + /// Wakeup Pin flag for PI8 + @ReadOnly(bits: 4..<5) + public var wupf5: WUPF5 + + /// Wakeup Pin flag for PI11 + @ReadOnly(bits: 5..<6) + public var wupf6: WUPF6 + + /// Enable Wakeup pin for PA0 + @ReadWrite(bits: 8..<9) + public var ewup1: EWUP1 + + /// Enable Wakeup pin for PA2 + @ReadWrite(bits: 9..<10) + public var ewup2: EWUP2 + + /// Enable Wakeup pin for PC1 + @ReadWrite(bits: 10..<11) + public var ewup3: EWUP3 + + /// Enable Wakeup pin for PC13 + @ReadWrite(bits: 11..<12) + public var ewup4: EWUP4 + + /// Enable Wakeup pin for PI8 + @ReadWrite(bits: 12..<13) + public var ewup5: EWUP5 + + /// Enable Wakeup pin for PI11 + @ReadWrite(bits: 13..<14) + public var ewup6: EWUP6 + } +} + +extension PWR.CR1 { + public struct PDDSValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Enter Stop mode when the CPU enters deepsleep + public static let STOP_MODE = Self(rawValue: 0x0) + + /// Enter Standby mode when the CPU enters deepsleep + public static let STANDBY_MODE = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension PWR.CR1 { + public struct VOSValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// Scale 3 mode + public static let SCALE3 = Self(rawValue: 0x1) + + /// Scale 2 mode + public static let SCALE2 = Self(rawValue: 0x2) + + /// Scale 1 mode (reset value) + public static let SCALE1 = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} diff --git a/stm32-lvgl/Sources/Registers/RCC.swift b/stm32-lvgl/Sources/Registers/RCC.swift new file mode 100644 index 0000000..57d1fdc --- /dev/null +++ b/stm32-lvgl/Sources/Registers/RCC.swift @@ -0,0 +1,2833 @@ +// Generated by svd2swift. + +import MMIO + +/// Reset and clock control +@RegisterBlock +public struct RCC { + /// clock control register + @RegisterBlock(offset: 0x0) + public var cr: Register + + /// PLL configuration register + @RegisterBlock(offset: 0x4) + public var pllcfgr: Register + + /// clock configuration register + @RegisterBlock(offset: 0x8) + public var cfgr: Register + + /// clock interrupt register + @RegisterBlock(offset: 0xc) + public var cir: Register + + /// AHB1 peripheral reset register + @RegisterBlock(offset: 0x10) + public var ahb1rstr: Register + + /// AHB2 peripheral reset register + @RegisterBlock(offset: 0x14) + public var ahb2rstr: Register + + /// AHB3 peripheral reset register + @RegisterBlock(offset: 0x18) + public var ahb3rstr: Register + + /// APB1 peripheral reset register + @RegisterBlock(offset: 0x20) + public var apb1rstr: Register + + /// APB2 peripheral reset register + @RegisterBlock(offset: 0x24) + public var apb2rstr: Register + + /// AHB1 peripheral clock register + @RegisterBlock(offset: 0x30) + public var ahb1enr: Register + + /// AHB2 peripheral clock enable register + @RegisterBlock(offset: 0x34) + public var ahb2enr: Register + + /// AHB3 peripheral clock enable register + @RegisterBlock(offset: 0x38) + public var ahb3enr: Register + + /// APB1 peripheral clock enable register + @RegisterBlock(offset: 0x40) + public var apb1enr: Register + + /// APB2 peripheral clock enable register + @RegisterBlock(offset: 0x44) + public var apb2enr: Register + + /// AHB1 peripheral clock enable in low power mode register + @RegisterBlock(offset: 0x50) + public var ahb1lpenr: Register + + /// AHB2 peripheral clock enable in low power mode register + @RegisterBlock(offset: 0x54) + public var ahb2lpenr: Register + + /// AHB3 peripheral clock enable in low power mode register + @RegisterBlock(offset: 0x58) + public var ahb3lpenr: Register + + /// APB1 peripheral clock enable in low power mode register + @RegisterBlock(offset: 0x60) + public var apb1lpenr: Register + + /// APB2 peripheral clock enabled in low power mode register + @RegisterBlock(offset: 0x64) + public var apb2lpenr: Register + + /// Backup domain control register + @RegisterBlock(offset: 0x70) + public var bdcr: Register + + /// clock control & status register + @RegisterBlock(offset: 0x74) + public var csr: Register + + /// spread spectrum clock generation register + @RegisterBlock(offset: 0x80) + public var sscgr: Register + + /// PLLI2S configuration register + @RegisterBlock(offset: 0x84) + public var plli2scfgr: Register + + /// PLL configuration register + @RegisterBlock(offset: 0x88) + public var pllsaicfgr: Register + + /// dedicated clocks configuration register + @RegisterBlock(offset: 0x8c) + public var dckcfgr1: Register + + /// dedicated clocks configuration register + @RegisterBlock(offset: 0x90) + public var dckcfgr2: Register +} + +extension RCC { + /// clock control register + @Register(bitWidth: 32) + public struct CR { + /// PLLI2S clock ready flag + @ReadOnly(bits: 27..<28) + public var plli2srdy: PLLI2SRDY + + /// PLLI2S enable + @ReadWrite(bits: 26..<27) + public var plli2son: PLLI2SON + + /// Main PLL (PLL) clock ready flag + @ReadOnly(bits: 25..<26) + public var pllrdy: PLLRDY + + /// Main PLL (PLL) enable + @ReadWrite(bits: 24..<25) + public var pllon: PLLON + + /// Clock security system enable + @ReadWrite(bits: 19..<20, as: CSSONValues.self) + public var csson: CSSON + + /// HSE clock bypass + @ReadWrite(bits: 18..<19, as: HSEBYPValues.self) + public var hsebyp: HSEBYP + + /// HSE clock ready flag + @ReadOnly(bits: 17..<18) + public var hserdy: HSERDY + + /// HSE clock enable + @ReadWrite(bits: 16..<17) + public var hseon: HSEON + + /// Internal high-speed clock calibration + @ReadOnly(bits: 8..<16) + public var hsical: HSICAL + + /// Internal high-speed clock trimming + @ReadWrite(bits: 3..<8) + public var hsitrim: HSITRIM + + /// Internal high-speed clock ready flag + @ReadOnly(bits: 1..<2) + public var hsirdy: HSIRDY + + /// Internal high-speed clock enable + @ReadWrite(bits: 0..<1, as: HSIONValues.self) + public var hsion: HSION + + /// PLLSAI clock ready flag + @ReadOnly(bits: 29..<30) + public var pllsairdy: PLLSAIRDY + + /// PLLSAI enable + @ReadWrite(bits: 28..<29) + public var pllsaion: PLLSAION + } + + /// PLL configuration register + @Register(bitWidth: 32) + public struct PLLCFGR { + /// Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + @ReadWrite(bits: 22..<23, as: PLLSRCValues.self) + public var pllsrc: PLLSRC + + /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + @ReadWrite(bits: 0..<6) + public var pllm: PLLM + + /// Main PLL (PLL) multiplication factor for VCO + @ReadWrite(bits: 6..<15) + public var plln: PLLN + + /// Main PLL (PLL) division factor for main system clock + @ReadWrite(bits: 16..<18, as: PLLPValues.self) + public var pllp: PLLP + + /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + @ReadWrite(bits: 24..<28) + public var pllq: PLLQ + } + + /// clock configuration register + @Register(bitWidth: 32) + public struct CFGR { + /// Microcontroller clock output 2 + @ReadWrite(bits: 30..<32, as: MCO2Values.self) + public var mco2: MCO2 + + /// MCO2 prescaler + @ReadWrite(bits: 27..<30) + public var mco2pre: MCO2PRE + + /// MCO1 prescaler + @ReadWrite(bits: 24..<27, as: MCO1PREValues.self) + public var mco1pre: MCO1PRE + + /// I2S clock selection + @ReadWrite(bits: 23..<24, as: I2SSRCValues.self) + public var i2ssrc: I2SSRC + + /// Microcontroller clock output 1 + @ReadWrite(bits: 21..<23, as: MCO1Values.self) + public var mco1: MCO1 + + /// HSE division factor for RTC clock + @ReadWrite(bits: 16..<21) + public var rtcpre: RTCPRE + + /// APB high-speed prescaler (APB2) + @ReadWrite(bits: 13..<16) + public var ppre2: PPRE2 + + /// APB Low speed prescaler (APB1) + @ReadWrite(bits: 10..<13, as: PPRE1Values.self) + public var ppre1: PPRE1 + + /// AHB prescaler + @ReadWrite(bits: 4..<8, as: HPREValues.self) + public var hpre: HPRE + + /// System clock switch + @Reserved(bits: 0..<2, as: SWValues.self) + public var sw: SW + + /// System clock switch status + @Reserved(bits: 2..<4) + public var sws: SWS + } + + /// clock interrupt register + @Register(bitWidth: 32) + public struct CIR { + /// Clock security system interrupt clear + @WriteOnly(bits: 23..<24) + public var cssc: CSSC + + /// PLLSAI Ready Interrupt Clear + @WriteOnly(bits: 22..<23) + public var pllsairdyc: PLLSAIRDYC + + /// PLLI2S ready interrupt clear + @WriteOnly(bits: 21..<22) + public var plli2srdyc: PLLI2SRDYC + + /// Main PLL(PLL) ready interrupt clear + @WriteOnly(bits: 20..<21) + public var pllrdyc: PLLRDYC + + /// HSE ready interrupt clear + @WriteOnly(bits: 19..<20) + public var hserdyc: HSERDYC + + /// HSI ready interrupt clear + @WriteOnly(bits: 18..<19) + public var hsirdyc: HSIRDYC + + /// LSE ready interrupt clear + @WriteOnly(bits: 17..<18) + public var lserdyc: LSERDYC + + /// LSI ready interrupt clear + @WriteOnly(bits: 16..<17) + public var lsirdyc: LSIRDYC + + /// PLLSAI Ready Interrupt Enable + @ReadWrite(bits: 14..<15) + public var pllsairdyie: PLLSAIRDYIE + + /// PLLI2S ready interrupt enable + @ReadWrite(bits: 13..<14) + public var plli2srdyie: PLLI2SRDYIE + + /// Main PLL (PLL) ready interrupt enable + @ReadWrite(bits: 12..<13) + public var pllrdyie: PLLRDYIE + + /// HSE ready interrupt enable + @ReadWrite(bits: 11..<12) + public var hserdyie: HSERDYIE + + /// HSI ready interrupt enable + @ReadWrite(bits: 10..<11) + public var hsirdyie: HSIRDYIE + + /// LSE ready interrupt enable + @ReadWrite(bits: 9..<10) + public var lserdyie: LSERDYIE + + /// LSI ready interrupt enable + @ReadWrite(bits: 8..<9, as: LSIRDYIEValues.self) + public var lsirdyie: LSIRDYIE + + /// Clock security system interrupt flag + @ReadOnly(bits: 7..<8) + public var cssf: CSSF + + /// PLLSAI ready interrupt flag + @ReadOnly(bits: 6..<7) + public var pllsairdyf: PLLSAIRDYF + + /// PLLI2S ready interrupt flag + @ReadOnly(bits: 5..<6) + public var plli2srdyf: PLLI2SRDYF + + /// Main PLL (PLL) ready interrupt flag + @ReadOnly(bits: 4..<5) + public var pllrdyf: PLLRDYF + + /// HSE ready interrupt flag + @ReadOnly(bits: 3..<4) + public var hserdyf: HSERDYF + + /// HSI ready interrupt flag + @ReadOnly(bits: 2..<3) + public var hsirdyf: HSIRDYF + + /// LSE ready interrupt flag + @ReadOnly(bits: 1..<2) + public var lserdyf: LSERDYF + + /// LSI ready interrupt flag + @ReadOnly(bits: 0..<1) + public var lsirdyf: LSIRDYF + } + + /// AHB1 peripheral reset register + @Register(bitWidth: 32) + public struct AHB1RSTR { + /// USB OTG HS module reset + @ReadWrite(bits: 29..<30) + public var otghsrst: OTGHSRST + + /// Ethernet MAC reset + @ReadWrite(bits: 25..<26) + public var ethmacrst: ETHMACRST + + /// DMA2D reset + @ReadWrite(bits: 23..<24) + public var dma2drst: DMA2DRST + + /// DMA2 reset + @ReadWrite(bits: 22..<23) + public var dma2rst: DMA2RST + + /// DMA2 reset + @ReadWrite(bits: 21..<22) + public var dma1rst: DMA1RST + + /// CRC reset + @ReadWrite(bits: 12..<13) + public var crcrst: CRCRST + + /// IO port K reset + @ReadWrite(bits: 10..<11) + public var gpiokrst: GPIOKRST + + /// IO port J reset + @ReadWrite(bits: 9..<10) + public var gpiojrst: GPIOJRST + + /// IO port I reset + @ReadWrite(bits: 8..<9) + public var gpioirst: GPIOIRST + + /// IO port H reset + @ReadWrite(bits: 7..<8) + public var gpiohrst: GPIOHRST + + /// IO port G reset + @ReadWrite(bits: 6..<7) + public var gpiogrst: GPIOGRST + + /// IO port F reset + @ReadWrite(bits: 5..<6) + public var gpiofrst: GPIOFRST + + /// IO port E reset + @ReadWrite(bits: 4..<5) + public var gpioerst: GPIOERST + + /// IO port D reset + @ReadWrite(bits: 3..<4) + public var gpiodrst: GPIODRST + + /// IO port C reset + @ReadWrite(bits: 2..<3) + public var gpiocrst: GPIOCRST + + /// IO port B reset + @ReadWrite(bits: 1..<2) + public var gpiobrst: GPIOBRST + + /// IO port A reset + @ReadWrite(bits: 0..<1, as: GPIOARSTValues.self) + public var gpioarst: GPIOARST + } + + /// AHB2 peripheral reset register + @Register(bitWidth: 32) + public struct AHB2RSTR { + /// USB OTG FS module reset + @ReadWrite(bits: 7..<8) + public var otgfsrst: OTGFSRST + + /// Random number generator module reset + @ReadWrite(bits: 6..<7) + public var rngrst: RNGRST + + /// Hash module reset + @ReadWrite(bits: 5..<6) + public var hsahrst: HSAHRST + + /// Cryptographic module reset + @ReadWrite(bits: 4..<5) + public var cryprst: CRYPRST + + /// Camera interface reset + @ReadWrite(bits: 0..<1, as: DCMIRSTValues.self) + public var dcmirst: DCMIRST + } + + /// AHB3 peripheral reset register + @Register(bitWidth: 32) + public struct AHB3RSTR { + /// Flexible memory controller module reset + @ReadWrite(bits: 0..<1, as: FMCRSTValues.self) + public var fmcrst: FMCRST + + /// Quad SPI memory controller reset + @ReadWrite(bits: 1..<2) + public var qspirst: QSPIRST + } + + /// APB1 peripheral reset register + @Register(bitWidth: 32) + public struct APB1RSTR { + /// TIM2 reset + @ReadWrite(bits: 0..<1, as: TIM2RSTValues.self) + public var tim2rst: TIM2RST + + /// TIM3 reset + @ReadWrite(bits: 1..<2) + public var tim3rst: TIM3RST + + /// TIM4 reset + @ReadWrite(bits: 2..<3) + public var tim4rst: TIM4RST + + /// TIM5 reset + @ReadWrite(bits: 3..<4) + public var tim5rst: TIM5RST + + /// TIM6 reset + @ReadWrite(bits: 4..<5) + public var tim6rst: TIM6RST + + /// TIM7 reset + @ReadWrite(bits: 5..<6) + public var tim7rst: TIM7RST + + /// TIM12 reset + @ReadWrite(bits: 6..<7) + public var tim12rst: TIM12RST + + /// TIM13 reset + @ReadWrite(bits: 7..<8) + public var tim13rst: TIM13RST + + /// TIM14 reset + @ReadWrite(bits: 8..<9) + public var tim14rst: TIM14RST + + /// Window watchdog reset + @ReadWrite(bits: 11..<12) + public var wwdgrst: WWDGRST + + /// SPI 2 reset + @ReadWrite(bits: 14..<15) + public var spi2rst: SPI2RST + + /// SPI 3 reset + @ReadWrite(bits: 15..<16) + public var spi3rst: SPI3RST + + /// USART 2 reset + @ReadWrite(bits: 17..<18) + public var usart2rst: USART2RST + + /// USART 3 reset + @ReadWrite(bits: 18..<19) + public var usart3rst: USART3RST + + /// USART 4 reset + @ReadWrite(bits: 19..<20) + public var uart4rst: UART4RST + + /// USART 5 reset + @ReadWrite(bits: 20..<21) + public var uart5rst: UART5RST + + /// I2C 1 reset + @ReadWrite(bits: 21..<22) + public var i2c1rst: I2C1RST + + /// I2C 2 reset + @ReadWrite(bits: 22..<23) + public var i2c2rst: I2C2RST + + /// I2C3 reset + @ReadWrite(bits: 23..<24) + public var i2c3rst: I2C3RST + + /// CAN1 reset + @ReadWrite(bits: 25..<26) + public var can1rst: CAN1RST + + /// CAN2 reset + @ReadWrite(bits: 26..<27) + public var can2rst: CAN2RST + + /// Power interface reset + @ReadWrite(bits: 28..<29) + public var pwrrst: PWRRST + + /// DAC reset + @ReadWrite(bits: 29..<30) + public var dacrst: DACRST + + /// UART7 reset + @ReadWrite(bits: 30..<31) + public var uart7rst: UART7RST + + /// UART8 reset + @ReadWrite(bits: 31..<32) + public var uart8rst: UART8RST + + /// SPDIF-RX reset + @ReadWrite(bits: 16..<17) + public var spdifrxrst: SPDIFRXRST + + /// HDMI-CEC reset + @ReadWrite(bits: 27..<28) + public var cecrst: CECRST + + /// Low power timer 1 reset + @ReadWrite(bits: 9..<10) + public var lptim1rst: LPTIM1RST + + /// I2C 4 reset + @ReadWrite(bits: 24..<25) + public var i2c4rst: I2C4RST + } + + /// APB2 peripheral reset register + @Register(bitWidth: 32) + public struct APB2RSTR { + /// TIM1 reset + @ReadWrite(bits: 0..<1, as: TIM1RSTValues.self) + public var tim1rst: TIM1RST + + /// TIM8 reset + @ReadWrite(bits: 1..<2) + public var tim8rst: TIM8RST + + /// USART1 reset + @ReadWrite(bits: 4..<5) + public var usart1rst: USART1RST + + /// USART6 reset + @ReadWrite(bits: 5..<6) + public var usart6rst: USART6RST + + /// ADC interface reset (common to all ADCs) + @ReadWrite(bits: 8..<9) + public var adcrst: ADCRST + + /// SPI 1 reset + @ReadWrite(bits: 12..<13) + public var spi1rst: SPI1RST + + /// SPI4 reset + @ReadWrite(bits: 13..<14) + public var spi4rst: SPI4RST + + /// System configuration controller reset + @ReadWrite(bits: 14..<15) + public var syscfgrst: SYSCFGRST + + /// TIM9 reset + @ReadWrite(bits: 16..<17) + public var tim9rst: TIM9RST + + /// TIM10 reset + @ReadWrite(bits: 17..<18) + public var tim10rst: TIM10RST + + /// TIM11 reset + @ReadWrite(bits: 18..<19) + public var tim11rst: TIM11RST + + /// SPI5 reset + @ReadWrite(bits: 20..<21) + public var spi5rst: SPI5RST + + /// SPI6 reset + @ReadWrite(bits: 21..<22) + public var spi6rst: SPI6RST + + /// SAI1 reset + @ReadWrite(bits: 22..<23) + public var sai1rst: SAI1RST + + /// LTDC reset + @ReadWrite(bits: 26..<27) + public var ltdcrst: LTDCRST + + /// SAI2 reset + @ReadWrite(bits: 23..<24) + public var sai2rst: SAI2RST + + /// SDMMC1 reset + @ReadWrite(bits: 11..<12) + public var sdmmc1rst: SDMMC1RST + } + + /// AHB1 peripheral clock register + @Register(bitWidth: 32) + public struct AHB1ENR { + /// USB OTG HSULPI clock enable + @ReadWrite(bits: 30..<31) + public var otghsulpien: OTGHSULPIEN + + /// USB OTG HS clock enable + @ReadWrite(bits: 29..<30) + public var otghsen: OTGHSEN + + /// Ethernet PTP clock enable + @ReadWrite(bits: 28..<29) + public var ethmacptpen: ETHMACPTPEN + + /// Ethernet Reception clock enable + @ReadWrite(bits: 27..<28) + public var ethmacrxen: ETHMACRXEN + + /// Ethernet Transmission clock enable + @ReadWrite(bits: 26..<27) + public var ethmactxen: ETHMACTXEN + + /// Ethernet MAC clock enable + @ReadWrite(bits: 25..<26) + public var ethmacen: ETHMACEN + + /// DMA2D clock enable + @ReadWrite(bits: 23..<24) + public var dma2den: DMA2DEN + + /// DMA2 clock enable + @ReadWrite(bits: 22..<23) + public var dma2en: DMA2EN + + /// DMA1 clock enable + @ReadWrite(bits: 21..<22) + public var dma1en: DMA1EN + + /// CCM data RAM clock enable + @ReadWrite(bits: 20..<21) + public var dtcmramen: DTCMRAMEN + + /// Backup SRAM interface clock enable + @ReadWrite(bits: 18..<19) + public var bkpsramen: BKPSRAMEN + + /// CRC clock enable + @ReadWrite(bits: 12..<13) + public var crcen: CRCEN + + /// IO port K clock enable + @ReadWrite(bits: 10..<11) + public var gpioken: GPIOKEN + + /// IO port J clock enable + @ReadWrite(bits: 9..<10) + public var gpiojen: GPIOJEN + + /// IO port I clock enable + @ReadWrite(bits: 8..<9) + public var gpioien: GPIOIEN + + /// IO port H clock enable + @ReadWrite(bits: 7..<8) + public var gpiohen: GPIOHEN + + /// IO port G clock enable + @ReadWrite(bits: 6..<7) + public var gpiogen: GPIOGEN + + /// IO port F clock enable + @ReadWrite(bits: 5..<6) + public var gpiofen: GPIOFEN + + /// IO port E clock enable + @ReadWrite(bits: 4..<5) + public var gpioeen: GPIOEEN + + /// IO port D clock enable + @ReadWrite(bits: 3..<4) + public var gpioden: GPIODEN + + /// IO port C clock enable + @ReadWrite(bits: 2..<3) + public var gpiocen: GPIOCEN + + /// IO port B clock enable + @ReadWrite(bits: 1..<2) + public var gpioben: GPIOBEN + + /// IO port A clock enable + @ReadWrite(bits: 0..<1, as: GPIOAENValues.self) + public var gpioaen: GPIOAEN + } + + /// AHB2 peripheral clock enable register + @Register(bitWidth: 32) + public struct AHB2ENR { + /// USB OTG FS clock enable + @ReadWrite(bits: 7..<8) + public var otgfsen: OTGFSEN + + /// Random number generator clock enable + @ReadWrite(bits: 6..<7) + public var rngen: RNGEN + + /// Hash modules clock enable + @ReadWrite(bits: 5..<6) + public var hashen: HASHEN + + /// Cryptographic modules clock enable + @ReadWrite(bits: 4..<5) + public var crypen: CRYPEN + + /// Camera interface enable + @ReadWrite(bits: 0..<1, as: DCMIENValues.self) + public var dcmien: DCMIEN + } + + /// AHB3 peripheral clock enable register + @Register(bitWidth: 32) + public struct AHB3ENR { + /// Flexible memory controller module clock enable + @ReadWrite(bits: 0..<1, as: FMCENValues.self) + public var fmcen: FMCEN + + /// Quad SPI memory controller clock enable + @ReadWrite(bits: 1..<2) + public var qspien: QSPIEN + } + + /// APB1 peripheral clock enable register + @Register(bitWidth: 32) + public struct APB1ENR { + /// TIM2 clock enable + @ReadWrite(bits: 0..<1, as: TIM2ENValues.self) + public var tim2en: TIM2EN + + /// TIM3 clock enable + @ReadWrite(bits: 1..<2) + public var tim3en: TIM3EN + + /// TIM4 clock enable + @ReadWrite(bits: 2..<3) + public var tim4en: TIM4EN + + /// TIM5 clock enable + @ReadWrite(bits: 3..<4) + public var tim5en: TIM5EN + + /// TIM6 clock enable + @ReadWrite(bits: 4..<5) + public var tim6en: TIM6EN + + /// TIM7 clock enable + @ReadWrite(bits: 5..<6) + public var tim7en: TIM7EN + + /// TIM12 clock enable + @ReadWrite(bits: 6..<7) + public var tim12en: TIM12EN + + /// TIM13 clock enable + @ReadWrite(bits: 7..<8) + public var tim13en: TIM13EN + + /// TIM14 clock enable + @ReadWrite(bits: 8..<9) + public var tim14en: TIM14EN + + /// Window watchdog clock enable + @ReadWrite(bits: 11..<12) + public var wwdgen: WWDGEN + + /// SPI2 clock enable + @ReadWrite(bits: 14..<15) + public var spi2en: SPI2EN + + /// SPI3 clock enable + @ReadWrite(bits: 15..<16) + public var spi3en: SPI3EN + + /// USART 2 clock enable + @ReadWrite(bits: 17..<18) + public var usart2en: USART2EN + + /// USART3 clock enable + @ReadWrite(bits: 18..<19) + public var usart3en: USART3EN + + /// UART4 clock enable + @ReadWrite(bits: 19..<20) + public var uart4en: UART4EN + + /// UART5 clock enable + @ReadWrite(bits: 20..<21) + public var uart5en: UART5EN + + /// I2C1 clock enable + @ReadWrite(bits: 21..<22) + public var i2c1en: I2C1EN + + /// I2C2 clock enable + @ReadWrite(bits: 22..<23) + public var i2c2en: I2C2EN + + /// I2C3 clock enable + @ReadWrite(bits: 23..<24) + public var i2c3en: I2C3EN + + /// CAN 1 clock enable + @ReadWrite(bits: 25..<26) + public var can1en: CAN1EN + + /// CAN 2 clock enable + @ReadWrite(bits: 26..<27) + public var can2en: CAN2EN + + /// Power interface clock enable + @ReadWrite(bits: 28..<29) + public var pwren: PWREN + + /// DAC interface clock enable + @ReadWrite(bits: 29..<30) + public var dacen: DACEN + + /// UART7 clock enable + @ReadWrite(bits: 30..<31) + public var uart7en: UART7EN + + /// UART8 clock enable + @ReadWrite(bits: 31..<32) + public var uart8en: UART8EN + + /// SPDIF-RX clock enable + @ReadWrite(bits: 16..<17) + public var spdifrxen: SPDIFRXEN + + /// HDMI-CEN clock enable + @ReadWrite(bits: 27..<28) + public var cecen: CECEN + + /// Low power timer 1 clock enable + @ReadWrite(bits: 9..<10) + public var lptim1en: LPTIM1EN + + /// I2C4 clock enable + @ReadWrite(bits: 24..<25) + public var i2c4en: I2C4EN + } + + /// APB2 peripheral clock enable register + @Register(bitWidth: 32) + public struct APB2ENR { + /// TIM1 clock enable + @ReadWrite(bits: 0..<1, as: TIM1ENValues.self) + public var tim1en: TIM1EN + + /// TIM8 clock enable + @ReadWrite(bits: 1..<2) + public var tim8en: TIM8EN + + /// USART1 clock enable + @ReadWrite(bits: 4..<5) + public var usart1en: USART1EN + + /// USART6 clock enable + @ReadWrite(bits: 5..<6) + public var usart6en: USART6EN + + /// ADC1 clock enable + @ReadWrite(bits: 8..<9) + public var adc1en: ADC1EN + + /// ADC2 clock enable + @ReadWrite(bits: 9..<10) + public var adc2en: ADC2EN + + /// ADC3 clock enable + @ReadWrite(bits: 10..<11) + public var adc3en: ADC3EN + + /// SPI1 clock enable + @ReadWrite(bits: 12..<13) + public var spi1en: SPI1EN + + /// SPI4 clock enable + @ReadWrite(bits: 13..<14) + public var spi4en: SPI4EN + + /// System configuration controller clock enable + @ReadWrite(bits: 14..<15) + public var syscfgen: SYSCFGEN + + /// TIM9 clock enable + @ReadWrite(bits: 16..<17) + public var tim9en: TIM9EN + + /// TIM10 clock enable + @ReadWrite(bits: 17..<18) + public var tim10en: TIM10EN + + /// TIM11 clock enable + @ReadWrite(bits: 18..<19) + public var tim11en: TIM11EN + + /// SPI5 clock enable + @ReadWrite(bits: 20..<21) + public var spi5en: SPI5EN + + /// SPI6 clock enable + @ReadWrite(bits: 21..<22) + public var spi6en: SPI6EN + + /// SAI1 clock enable + @ReadWrite(bits: 22..<23) + public var sai1en: SAI1EN + + /// LTDC clock enable + @ReadWrite(bits: 26..<27) + public var ltdcen: LTDCEN + + /// SAI2 clock enable + @ReadWrite(bits: 23..<24) + public var sai2en: SAI2EN + + /// SDMMC1 clock enable + @ReadWrite(bits: 11..<12) + public var sdmmc1en: SDMMC1EN + } + + /// AHB1 peripheral clock enable in low power mode register + @Register(bitWidth: 32) + public struct AHB1LPENR { + /// IO port A clock enable during sleep mode + @ReadWrite(bits: 0..<1, as: GPIOALPENValues.self) + public var gpioalpen: GPIOALPEN + + /// IO port B clock enable during Sleep mode + @ReadWrite(bits: 1..<2) + public var gpioblpen: GPIOBLPEN + + /// IO port C clock enable during Sleep mode + @ReadWrite(bits: 2..<3) + public var gpioclpen: GPIOCLPEN + + /// IO port D clock enable during Sleep mode + @ReadWrite(bits: 3..<4) + public var gpiodlpen: GPIODLPEN + + /// IO port E clock enable during Sleep mode + @ReadWrite(bits: 4..<5) + public var gpioelpen: GPIOELPEN + + /// IO port F clock enable during Sleep mode + @ReadWrite(bits: 5..<6) + public var gpioflpen: GPIOFLPEN + + /// IO port G clock enable during Sleep mode + @ReadWrite(bits: 6..<7) + public var gpioglpen: GPIOGLPEN + + /// IO port H clock enable during Sleep mode + @ReadWrite(bits: 7..<8) + public var gpiohlpen: GPIOHLPEN + + /// IO port I clock enable during Sleep mode + @ReadWrite(bits: 8..<9) + public var gpioilpen: GPIOILPEN + + /// IO port J clock enable during Sleep mode + @ReadWrite(bits: 9..<10) + public var gpiojlpen: GPIOJLPEN + + /// IO port K clock enable during Sleep mode + @ReadWrite(bits: 10..<11) + public var gpioklpen: GPIOKLPEN + + /// CRC clock enable during Sleep mode + @ReadWrite(bits: 12..<13) + public var crclpen: CRCLPEN + + /// Flash interface clock enable during Sleep mode + @ReadWrite(bits: 15..<16) + public var flitflpen: FLITFLPEN + + /// SRAM 1interface clock enable during Sleep mode + @ReadWrite(bits: 16..<17) + public var sram1lpen: SRAM1LPEN + + /// SRAM 2 interface clock enable during Sleep mode + @ReadWrite(bits: 17..<18) + public var sram2lpen: SRAM2LPEN + + /// Backup SRAM interface clock enable during Sleep mode + @ReadWrite(bits: 18..<19) + public var bkpsramlpen: BKPSRAMLPEN + + /// SRAM 3 interface clock enable during Sleep mode + @ReadWrite(bits: 19..<20) + public var sram3lpen: SRAM3LPEN + + /// DMA1 clock enable during Sleep mode + @ReadWrite(bits: 21..<22) + public var dma1lpen: DMA1LPEN + + /// DMA2 clock enable during Sleep mode + @ReadWrite(bits: 22..<23) + public var dma2lpen: DMA2LPEN + + /// DMA2D clock enable during Sleep mode + @ReadWrite(bits: 23..<24) + public var dma2dlpen: DMA2DLPEN + + /// Ethernet MAC clock enable during Sleep mode + @ReadWrite(bits: 25..<26) + public var ethmaclpen: ETHMACLPEN + + /// Ethernet transmission clock enable during Sleep mode + @ReadWrite(bits: 26..<27) + public var ethmactxlpen: ETHMACTXLPEN + + /// Ethernet reception clock enable during Sleep mode + @ReadWrite(bits: 27..<28) + public var ethmacrxlpen: ETHMACRXLPEN + + /// Ethernet PTP clock enable during Sleep mode + @ReadWrite(bits: 28..<29) + public var ethmacptplpen: ETHMACPTPLPEN + + /// USB OTG HS clock enable during Sleep mode + @ReadWrite(bits: 29..<30) + public var otghslpen: OTGHSLPEN + + /// USB OTG HS ULPI clock enable during Sleep mode + @ReadWrite(bits: 30..<31) + public var otghsulpilpen: OTGHSULPILPEN + + /// AXI to AHB bridge clock enable during Sleep mode + @ReadWrite(bits: 13..<14) + public var axilpen: AXILPEN + + /// DTCM RAM interface clock enable during Sleep mode + @ReadWrite(bits: 20..<21) + public var dtcmlpen: DTCMLPEN + } + + /// AHB2 peripheral clock enable in low power mode register + @Register(bitWidth: 32) + public struct AHB2LPENR { + /// USB OTG FS clock enable during Sleep mode + @ReadWrite(bits: 7..<8) + public var otgfslpen: OTGFSLPEN + + /// Random number generator clock enable during Sleep mode + @ReadWrite(bits: 6..<7) + public var rnglpen: RNGLPEN + + /// Hash modules clock enable during Sleep mode + @ReadWrite(bits: 5..<6) + public var hashlpen: HASHLPEN + + /// Cryptography modules clock enable during Sleep mode + @ReadWrite(bits: 4..<5) + public var cryplpen: CRYPLPEN + + /// Camera interface enable during Sleep mode + @ReadWrite(bits: 0..<1, as: DCMILPENValues.self) + public var dcmilpen: DCMILPEN + } + + /// AHB3 peripheral clock enable in low power mode register + @Register(bitWidth: 32) + public struct AHB3LPENR { + /// Flexible memory controller module clock enable during Sleep mode + @ReadWrite(bits: 0..<1, as: FMCLPENValues.self) + public var fmclpen: FMCLPEN + + /// Quand SPI memory controller clock enable during Sleep mode + @ReadWrite(bits: 1..<2) + public var qspilpen: QSPILPEN + } + + /// APB1 peripheral clock enable in low power mode register + @Register(bitWidth: 32) + public struct APB1LPENR { + /// TIM2 clock enable during Sleep mode + @ReadWrite(bits: 0..<1, as: TIM2LPENValues.self) + public var tim2lpen: TIM2LPEN + + /// TIM3 clock enable during Sleep mode + @ReadWrite(bits: 1..<2) + public var tim3lpen: TIM3LPEN + + /// TIM4 clock enable during Sleep mode + @ReadWrite(bits: 2..<3) + public var tim4lpen: TIM4LPEN + + /// TIM5 clock enable during Sleep mode + @ReadWrite(bits: 3..<4) + public var tim5lpen: TIM5LPEN + + /// TIM6 clock enable during Sleep mode + @ReadWrite(bits: 4..<5) + public var tim6lpen: TIM6LPEN + + /// TIM7 clock enable during Sleep mode + @ReadWrite(bits: 5..<6) + public var tim7lpen: TIM7LPEN + + /// TIM12 clock enable during Sleep mode + @ReadWrite(bits: 6..<7) + public var tim12lpen: TIM12LPEN + + /// TIM13 clock enable during Sleep mode + @ReadWrite(bits: 7..<8) + public var tim13lpen: TIM13LPEN + + /// TIM14 clock enable during Sleep mode + @ReadWrite(bits: 8..<9) + public var tim14lpen: TIM14LPEN + + /// Window watchdog clock enable during Sleep mode + @ReadWrite(bits: 11..<12) + public var wwdglpen: WWDGLPEN + + /// SPI2 clock enable during Sleep mode + @ReadWrite(bits: 14..<15) + public var spi2lpen: SPI2LPEN + + /// SPI3 clock enable during Sleep mode + @ReadWrite(bits: 15..<16) + public var spi3lpen: SPI3LPEN + + /// USART2 clock enable during Sleep mode + @ReadWrite(bits: 17..<18) + public var usart2lpen: USART2LPEN + + /// USART3 clock enable during Sleep mode + @ReadWrite(bits: 18..<19) + public var usart3lpen: USART3LPEN + + /// UART4 clock enable during Sleep mode + @ReadWrite(bits: 19..<20) + public var uart4lpen: UART4LPEN + + /// UART5 clock enable during Sleep mode + @ReadWrite(bits: 20..<21) + public var uart5lpen: UART5LPEN + + /// I2C1 clock enable during Sleep mode + @ReadWrite(bits: 21..<22) + public var i2c1lpen: I2C1LPEN + + /// I2C2 clock enable during Sleep mode + @ReadWrite(bits: 22..<23) + public var i2c2lpen: I2C2LPEN + + /// I2C3 clock enable during Sleep mode + @ReadWrite(bits: 23..<24) + public var i2c3lpen: I2C3LPEN + + /// CAN 1 clock enable during Sleep mode + @ReadWrite(bits: 25..<26) + public var can1lpen: CAN1LPEN + + /// CAN 2 clock enable during Sleep mode + @ReadWrite(bits: 26..<27) + public var can2lpen: CAN2LPEN + + /// Power interface clock enable during Sleep mode + @ReadWrite(bits: 28..<29) + public var pwrlpen: PWRLPEN + + /// DAC interface clock enable during Sleep mode + @ReadWrite(bits: 29..<30) + public var daclpen: DACLPEN + + /// UART7 clock enable during Sleep mode + @ReadWrite(bits: 30..<31) + public var uart7lpen: UART7LPEN + + /// UART8 clock enable during Sleep mode + @ReadWrite(bits: 31..<32) + public var uart8lpen: UART8LPEN + + /// SPDIF-RX clock enable during sleep mode + @ReadWrite(bits: 16..<17) + public var spdifrxlpen: SPDIFRXLPEN + + /// HDMI-CEN clock enable during Sleep mode + @ReadWrite(bits: 27..<28) + public var ceclpen: CECLPEN + + /// low power timer 1 clock enable during Sleep mode + @ReadWrite(bits: 9..<10) + public var lptim1lpen: LPTIM1LPEN + + /// I2C4 clock enable during Sleep mode + @ReadWrite(bits: 24..<25) + public var i2c4lpen: I2C4LPEN + } + + /// APB2 peripheral clock enabled in low power mode register + @Register(bitWidth: 32) + public struct APB2LPENR { + /// TIM1 clock enable during Sleep mode + @ReadWrite(bits: 0..<1, as: TIM1LPENValues.self) + public var tim1lpen: TIM1LPEN + + /// TIM8 clock enable during Sleep mode + @ReadWrite(bits: 1..<2) + public var tim8lpen: TIM8LPEN + + /// USART1 clock enable during Sleep mode + @ReadWrite(bits: 4..<5) + public var usart1lpen: USART1LPEN + + /// USART6 clock enable during Sleep mode + @ReadWrite(bits: 5..<6) + public var usart6lpen: USART6LPEN + + /// ADC1 clock enable during Sleep mode + @ReadWrite(bits: 8..<9) + public var adc1lpen: ADC1LPEN + + /// ADC2 clock enable during Sleep mode + @ReadWrite(bits: 9..<10) + public var adc2lpen: ADC2LPEN + + /// ADC 3 clock enable during Sleep mode + @ReadWrite(bits: 10..<11) + public var adc3lpen: ADC3LPEN + + /// SPI 1 clock enable during Sleep mode + @ReadWrite(bits: 12..<13) + public var spi1lpen: SPI1LPEN + + /// SPI 4 clock enable during Sleep mode + @ReadWrite(bits: 13..<14) + public var spi4lpen: SPI4LPEN + + /// System configuration controller clock enable during Sleep mode + @ReadWrite(bits: 14..<15) + public var syscfglpen: SYSCFGLPEN + + /// TIM9 clock enable during sleep mode + @ReadWrite(bits: 16..<17) + public var tim9lpen: TIM9LPEN + + /// TIM10 clock enable during Sleep mode + @ReadWrite(bits: 17..<18) + public var tim10lpen: TIM10LPEN + + /// TIM11 clock enable during Sleep mode + @ReadWrite(bits: 18..<19) + public var tim11lpen: TIM11LPEN + + /// SPI 5 clock enable during Sleep mode + @ReadWrite(bits: 20..<21) + public var spi5lpen: SPI5LPEN + + /// SPI 6 clock enable during Sleep mode + @ReadWrite(bits: 21..<22) + public var spi6lpen: SPI6LPEN + + /// SAI1 clock enable during sleep mode + @ReadWrite(bits: 22..<23) + public var sai1lpen: SAI1LPEN + + /// LTDC clock enable during sleep mode + @ReadWrite(bits: 26..<27) + public var ltdclpen: LTDCLPEN + + /// SAI2 clock enable during sleep mode + @ReadWrite(bits: 23..<24) + public var sai2lpen: SAI2LPEN + + /// SDMMC1 clock enable during Sleep mode + @ReadWrite(bits: 11..<12) + public var sdmmc1lpen: SDMMC1LPEN + } + + /// Backup domain control register + @Register(bitWidth: 32) + public struct BDCR { + /// Backup domain software reset + @ReadWrite(bits: 16..<17, as: BDRSTValues.self) + public var bdrst: BDRST + + /// RTC clock enable + @ReadWrite(bits: 15..<16, as: RTCENValues.self) + public var rtcen: RTCEN + + /// External low-speed oscillator bypass + @ReadWrite(bits: 2..<3, as: LSEBYPValues.self) + public var lsebyp: LSEBYP + + /// External low-speed oscillator ready + @ReadOnly(bits: 1..<2) + public var lserdy: LSERDY + + /// External low-speed oscillator enable + @ReadWrite(bits: 0..<1, as: LSEONValues.self) + public var lseon: LSEON + + /// LSE oscillator drive capability + @ReadWrite(bits: 3..<5, as: LSEDRVValues.self) + public var lsedrv: LSEDRV + + /// RTC clock source selection + @Reserved(bits: 8..<10, as: RTCSELValues.self) + public var rtcsel: RTCSEL + } + + /// clock control & status register + @Register(bitWidth: 32) + public struct CSR { + /// Low-power reset flag + @ReadWrite(bits: 31..<32) + public var lpwrrstf: LPWRRSTF + + /// Window watchdog reset flag + @ReadWrite(bits: 30..<31) + public var wwdgrstf: WWDGRSTF + + /// Independent watchdog reset flag + @ReadWrite(bits: 29..<30) + public var wdgrstf: WDGRSTF + + /// Software reset flag + @ReadWrite(bits: 28..<29) + public var sftrstf: SFTRSTF + + /// POR/PDR reset flag + @ReadWrite(bits: 27..<28) + public var porrstf: PORRSTF + + /// PIN reset flag + @ReadWrite(bits: 26..<27) + public var padrstf: PADRSTF + + /// BOR reset flag + @ReadWrite(bits: 25..<26) + public var borrstf: BORRSTF + + /// Remove reset flag + @ReadWrite(bits: 24..<25) + public var rmvf: RMVF + + /// Internal low-speed oscillator ready + @ReadOnly(bits: 1..<2) + public var lsirdy: LSIRDY + + /// Internal low-speed oscillator enable + @ReadWrite(bits: 0..<1, as: LSIONValues.self) + public var lsion: LSION + } + + /// spread spectrum clock generation register + @Register(bitWidth: 32) + public struct SSCGR { + /// Spread spectrum modulation enable + @ReadWrite(bits: 31..<32, as: SSCGENValues.self) + public var sscgen: SSCGEN + + /// Spread Select + @ReadWrite(bits: 30..<31, as: SPREADSELValues.self) + public var spreadsel: SPREADSEL + + /// Incrementation step + @ReadWrite(bits: 13..<28) + public var incstep: INCSTEP + + /// Modulation period + @ReadWrite(bits: 0..<13) + public var modper: MODPER + } + + /// PLLI2S configuration register + @Register(bitWidth: 32) + public struct PLLI2SCFGR { + /// PLLI2S division factor for I2S clocks + @ReadWrite(bits: 28..<31) + public var plli2sr: PLLI2SR + + /// PLLI2S division factor for SAI1 clock + @ReadWrite(bits: 24..<28) + public var plli2sq: PLLI2SQ + + /// PLLI2S multiplication factor for VCO + @ReadWrite(bits: 6..<15) + public var plli2sn: PLLI2SN + + /// PLLI2S division factor for SPDIFRX clock + @ReadWrite(bits: 16..<18, as: PLLI2SPValues.self) + public var plli2sp: PLLI2SP + } + + /// PLL configuration register + @Register(bitWidth: 32) + public struct PLLSAICFGR { + /// PLLSAI division factor for VCO + @ReadWrite(bits: 6..<15) + public var pllsain: PLLSAIN + + /// PLLSAI division factor for 48MHz clock + @ReadWrite(bits: 16..<18, as: PLLSAIPValues.self) + public var pllsaip: PLLSAIP + + /// PLLSAI division factor for SAI clock + @ReadWrite(bits: 24..<28) + public var pllsaiq: PLLSAIQ + + /// PLLSAI division factor for LCD clock + @ReadWrite(bits: 28..<31) + public var pllsair: PLLSAIR + } + + /// dedicated clocks configuration register + @Register(bitWidth: 32) + public struct DCKCFGR1 { + /// PLLI2S division factor for SAI1 clock + @ReadWrite(bits: 0..<5, as: PLLI2SDIVQValues.self) + public var plli2sdivq: PLLI2SDIVQ + + /// PLLSAI division factor for SAI1 clock + @ReadWrite(bits: 8..<13, as: PLLSAIDIVQValues.self) + public var pllsaidivq: PLLSAIDIVQ + + /// division factor for LCD_CLK + @ReadWrite(bits: 16..<18, as: PLLSAIDIVRValues.self) + public var pllsaidivr: PLLSAIDIVR + + /// SAI1 clock source selection + @ReadWrite(bits: 20..<22, as: SAI1SELValues.self) + public var sai1sel: SAI1SEL + + /// SAI2 clock source selection + @ReadWrite(bits: 22..<24, as: SAI2SELValues.self) + public var sai2sel: SAI2SEL + + /// Timers clocks prescalers selection + @ReadWrite(bits: 24..<25, as: TIMPREValues.self) + public var timpre: TIMPRE + } + + /// dedicated clocks configuration register + @Register(bitWidth: 32) + public struct DCKCFGR2 { + /// USART 1 clock source selection + @ReadWrite(bits: 0..<2, as: USART1SELValues.self) + public var usart1sel: USART1SEL + + /// USART 2 clock source selection + @ReadWrite(bits: 2..<4, as: USART2SELValues.self) + public var usart2sel: USART2SEL + + /// USART 3 clock source selection + @ReadWrite(bits: 4..<6) + public var usart3sel: USART3SEL + + /// UART 4 clock source selection + @ReadWrite(bits: 6..<8) + public var uart4sel: UART4SEL + + /// UART 5 clock source selection + @ReadWrite(bits: 8..<10) + public var uart5sel: UART5SEL + + /// USART 6 clock source selection + @ReadWrite(bits: 10..<12) + public var usart6sel: USART6SEL + + /// UART 7 clock source selection + @ReadWrite(bits: 12..<14) + public var uart7sel: UART7SEL + + /// UART 8 clock source selection + @ReadWrite(bits: 14..<16) + public var uart8sel: UART8SEL + + /// I2C1 clock source selection + @ReadWrite(bits: 16..<18, as: I2C1SELValues.self) + public var i2c1sel: I2C1SEL + + /// I2C2 clock source selection + @ReadWrite(bits: 18..<20) + public var i2c2sel: I2C2SEL + + /// I2C3 clock source selection + @ReadWrite(bits: 20..<22) + public var i2c3sel: I2C3SEL + + /// I2C4 clock source selection + @ReadWrite(bits: 22..<24) + public var i2c4sel: I2C4SEL + + /// Low power timer 1 clock source selection + @ReadWrite(bits: 24..<26, as: LPTIM1SELValues.self) + public var lptim1sel: LPTIM1SEL + + /// HDMI-CEC clock source selection + @ReadWrite(bits: 26..<27, as: CECSELValues.self) + public var cecsel: CECSEL + + /// 48MHz clock source selection + @ReadWrite(bits: 27..<28, as: CK48MSELValues.self) + public var ck48msel: CK48MSEL + + /// SDMMC clock source selection + @ReadWrite(bits: 28..<29, as: SDMMC1SELValues.self) + public var sdmmc1sel: SDMMC1SEL + } +} + +extension RCC.CR { + public struct CSSONValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Clock security system disabled (clock detector OFF) + public static let Off = Self(rawValue: 0x0) + + /// Clock security system enable (clock detector ON if the HSE is ready, OFF if not) + public static let On = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CR { + public struct HSEBYPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// HSE crystal oscillator not bypassed + public static let NotBypassed = Self(rawValue: 0x0) + + /// HSE crystal oscillator bypassed with external clock + public static let Bypassed = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CR { + public struct HSIONValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Clock Off + public static let Off = Self(rawValue: 0x0) + + /// Clock On + public static let On = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.PLLCFGR { + public struct PLLSRCValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// HSI clock selected as PLL and PLLI2S clock entry + public static let HSI = Self(rawValue: 0x0) + + /// HSE oscillator clock selected as PLL and PLLI2S clock entry + public static let HSE = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.PLLCFGR { + public struct PLLPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// PLLP=2 + public static let Div2 = Self(rawValue: 0x0) + + /// PLLP=4 + public static let Div4 = Self(rawValue: 0x1) + + /// PLLP=6 + public static let Div6 = Self(rawValue: 0x2) + + /// PLLP=8 + public static let Div8 = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + public struct MCO2Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// System clock (SYSCLK) selected + public static let SYSCLK = Self(rawValue: 0x0) + + /// PLLI2S clock selected + public static let PLLI2S = Self(rawValue: 0x1) + + /// HSE oscillator clock selected + public static let HSE = Self(rawValue: 0x2) + + /// PLL clock selected + public static let PLL = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + public struct MCO1PREValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 3 + + /// No division + public static let Div1 = Self(rawValue: 0x0) + + /// Division by 2 + public static let Div2 = Self(rawValue: 0x4) + + /// Division by 3 + public static let Div3 = Self(rawValue: 0x5) + + /// Division by 4 + public static let Div4 = Self(rawValue: 0x6) + + /// Division by 5 + public static let Div5 = Self(rawValue: 0x7) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + public struct I2SSRCValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// PLLI2S clock used as I2S clock source + public static let PLLI2S = Self(rawValue: 0x0) + + /// External clock mapped on the I2S_CKIN pin used as I2S clock source + public static let CKIN = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + public struct MCO1Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// HSI clock selected + public static let HSI = Self(rawValue: 0x0) + + /// LSE oscillator selected + public static let LSE = Self(rawValue: 0x1) + + /// HSE oscillator clock selected + public static let HSE = Self(rawValue: 0x2) + + /// PLL clock selected + public static let PLL = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + public struct PPRE1Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 3 + + /// HCLK not divided + public static let Div1 = Self(rawValue: 0x0) + + /// HCLK divided by 2 + public static let Div2 = Self(rawValue: 0x4) + + /// HCLK divided by 4 + public static let Div4 = Self(rawValue: 0x5) + + /// HCLK divided by 8 + public static let Div8 = Self(rawValue: 0x6) + + /// HCLK divided by 16 + public static let Div16 = Self(rawValue: 0x7) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + public struct HPREValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 4 + + /// SYSCLK not divided + public static let Div1 = Self(rawValue: 0x0) + + /// SYSCLK divided by 2 + public static let Div2 = Self(rawValue: 0x8) + + /// SYSCLK divided by 4 + public static let Div4 = Self(rawValue: 0x9) + + /// SYSCLK divided by 8 + public static let Div8 = Self(rawValue: 0xa) + + /// SYSCLK divided by 16 + public static let Div16 = Self(rawValue: 0xb) + + /// SYSCLK divided by 64 + public static let Div64 = Self(rawValue: 0xc) + + /// SYSCLK divided by 128 + public static let Div128 = Self(rawValue: 0xd) + + /// SYSCLK divided by 256 + public static let Div256 = Self(rawValue: 0xe) + + /// SYSCLK divided by 512 + public static let Div512 = Self(rawValue: 0xf) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + public struct SWValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// HSI selected as system clock + public static let HSI = Self(rawValue: 0x0) + + /// HSE selected as system clock + public static let HSE = Self(rawValue: 0x1) + + /// PLL selected as system clock + public static let PLL = Self(rawValue: 0x2) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CIR { + public struct LSIRDYIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Interrupt disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Interrupt enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB1RSTR { + public struct GPIOARSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Reset the selected module + public static let Reset = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB2RSTR { + public struct DCMIRSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Reset the selected module + public static let Reset = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB3RSTR { + public struct FMCRSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Reset the selected module + public static let Reset = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB1RSTR { + public struct TIM2RSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Reset the selected module + public static let Reset = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB2RSTR { + public struct TIM1RSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Reset the selected module + public static let Reset = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB1ENR { + public struct GPIOAENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// The selected clock is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// The selected clock is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB2ENR { + public struct DCMIENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// The selected clock is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// The selected clock is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB3ENR { + public struct FMCENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// The selected clock is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// The selected clock is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB1ENR { + public struct TIM2ENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// The selected clock is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// The selected clock is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB2ENR { + public struct TIM1ENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// The selected clock is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// The selected clock is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB1LPENR { + public struct GPIOALPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Selected module is disabled during Sleep mode + public static let DisabledInSleep = Self(rawValue: 0x0) + + /// Selected module is enabled during Sleep mode + public static let EnabledInSleep = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB2LPENR { + public struct DCMILPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Selected module is disabled during Sleep mode + public static let DisabledInSleep = Self(rawValue: 0x0) + + /// Selected module is enabled during Sleep mode + public static let EnabledInSleep = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB3LPENR { + public struct FMCLPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Selected module is disabled during Sleep mode + public static let DisabledInSleep = Self(rawValue: 0x0) + + /// Selected module is enabled during Sleep mode + public static let EnabledInSleep = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB1LPENR { + public struct TIM2LPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Selected module is disabled during Sleep mode + public static let DisabledInSleep = Self(rawValue: 0x0) + + /// Selected module is enabled during Sleep mode + public static let EnabledInSleep = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB2LPENR { + public struct TIM1LPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Selected module is disabled during Sleep mode + public static let DisabledInSleep = Self(rawValue: 0x0) + + /// Selected module is enabled during Sleep mode + public static let EnabledInSleep = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + public struct BDRSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Reset not activated + public static let Disabled = Self(rawValue: 0x0) + + /// Reset the entire RTC domain + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + public struct RTCENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// RTC clock disabled + public static let Disabled = Self(rawValue: 0x0) + + /// RTC clock enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + public struct LSEBYPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// LSE crystal oscillator not bypassed + public static let NotBypassed = Self(rawValue: 0x0) + + /// LSE crystal oscillator bypassed with external clock + public static let Bypassed = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + public struct LSEONValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// LSE oscillator Off + public static let Off = Self(rawValue: 0x0) + + /// LSE oscillator On + public static let On = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + public struct LSEDRVValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// Low drive capacity + public static let Low = Self(rawValue: 0x0) + + /// Medium-high drive capacity + public static let MediumHigh = Self(rawValue: 0x1) + + /// Medium-low drive capacity + public static let MediumLow = Self(rawValue: 0x2) + + /// High drive capacity + public static let High = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + public struct RTCSELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// No clock + public static let NoClock = Self(rawValue: 0x0) + + /// LSE oscillator clock used as RTC clock + public static let LSE = Self(rawValue: 0x1) + + /// LSI oscillator clock used as RTC clock + public static let LSI = Self(rawValue: 0x2) + + /// HSE oscillator clock divided by a prescaler used as RTC clock + public static let HSE = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CSR { + public struct LSIONValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// LSI oscillator Off + public static let Off = Self(rawValue: 0x0) + + /// LSI oscillator On + public static let On = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.SSCGR { + public struct SSCGENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Spread spectrum modulation disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Spread spectrum modulation enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.SSCGR { + public struct SPREADSELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Center spread + public static let Center = Self(rawValue: 0x0) + + /// Down spread + public static let Down = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.PLLI2SCFGR { + public struct PLLI2SPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// PLL*P=2 + public static let Div2 = Self(rawValue: 0x0) + + /// PLL*P=4 + public static let Div4 = Self(rawValue: 0x1) + + /// PLL*P=6 + public static let Div6 = Self(rawValue: 0x2) + + /// PLL*P=8 + public static let Div8 = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.PLLSAICFGR { + public struct PLLSAIPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// PLL*P=2 + public static let Div2 = Self(rawValue: 0x0) + + /// PLL*P=4 + public static let Div4 = Self(rawValue: 0x1) + + /// PLL*P=6 + public static let Div6 = Self(rawValue: 0x2) + + /// PLL*P=8 + public static let Div8 = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + public struct PLLI2SDIVQValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 5 + + /// PLLI2SDIVQ = /1 + public static let Div1 = Self(rawValue: 0x0) + + /// PLLI2SDIVQ = /2 + public static let Div2 = Self(rawValue: 0x1) + + /// PLLI2SDIVQ = /3 + public static let Div3 = Self(rawValue: 0x2) + + /// PLLI2SDIVQ = /4 + public static let Div4 = Self(rawValue: 0x3) + + /// PLLI2SDIVQ = /5 + public static let Div5 = Self(rawValue: 0x4) + + /// PLLI2SDIVQ = /6 + public static let Div6 = Self(rawValue: 0x5) + + /// PLLI2SDIVQ = /7 + public static let Div7 = Self(rawValue: 0x6) + + /// PLLI2SDIVQ = /8 + public static let Div8 = Self(rawValue: 0x7) + + /// PLLI2SDIVQ = /9 + public static let Div9 = Self(rawValue: 0x8) + + /// PLLI2SDIVQ = /10 + public static let Div10 = Self(rawValue: 0x9) + + /// PLLI2SDIVQ = /11 + public static let Div11 = Self(rawValue: 0xa) + + /// PLLI2SDIVQ = /12 + public static let Div12 = Self(rawValue: 0xb) + + /// PLLI2SDIVQ = /13 + public static let Div13 = Self(rawValue: 0xc) + + /// PLLI2SDIVQ = /14 + public static let Div14 = Self(rawValue: 0xd) + + /// PLLI2SDIVQ = /15 + public static let Div15 = Self(rawValue: 0xe) + + /// PLLI2SDIVQ = /16 + public static let Div16 = Self(rawValue: 0xf) + + /// PLLI2SDIVQ = /17 + public static let Div17 = Self(rawValue: 0x10) + + /// PLLI2SDIVQ = /18 + public static let Div18 = Self(rawValue: 0x11) + + /// PLLI2SDIVQ = /19 + public static let Div19 = Self(rawValue: 0x12) + + /// PLLI2SDIVQ = /20 + public static let Div20 = Self(rawValue: 0x13) + + /// PLLI2SDIVQ = /21 + public static let Div21 = Self(rawValue: 0x14) + + /// PLLI2SDIVQ = /22 + public static let Div22 = Self(rawValue: 0x15) + + /// PLLI2SDIVQ = /23 + public static let Div23 = Self(rawValue: 0x16) + + /// PLLI2SDIVQ = /24 + public static let Div24 = Self(rawValue: 0x17) + + /// PLLI2SDIVQ = /25 + public static let Div25 = Self(rawValue: 0x18) + + /// PLLI2SDIVQ = /26 + public static let Div26 = Self(rawValue: 0x19) + + /// PLLI2SDIVQ = /27 + public static let Div27 = Self(rawValue: 0x1a) + + /// PLLI2SDIVQ = /28 + public static let Div28 = Self(rawValue: 0x1b) + + /// PLLI2SDIVQ = /29 + public static let Div29 = Self(rawValue: 0x1c) + + /// PLLI2SDIVQ = /30 + public static let Div30 = Self(rawValue: 0x1d) + + /// PLLI2SDIVQ = /31 + public static let Div31 = Self(rawValue: 0x1e) + + /// PLLI2SDIVQ = /32 + public static let Div32 = Self(rawValue: 0x1f) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + public struct PLLSAIDIVQValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 5 + + /// PLLSAIDIVQ = /1 + public static let Div1 = Self(rawValue: 0x0) + + /// PLLSAIDIVQ = /2 + public static let Div2 = Self(rawValue: 0x1) + + /// PLLSAIDIVQ = /3 + public static let Div3 = Self(rawValue: 0x2) + + /// PLLSAIDIVQ = /4 + public static let Div4 = Self(rawValue: 0x3) + + /// PLLSAIDIVQ = /5 + public static let Div5 = Self(rawValue: 0x4) + + /// PLLSAIDIVQ = /6 + public static let Div6 = Self(rawValue: 0x5) + + /// PLLSAIDIVQ = /7 + public static let Div7 = Self(rawValue: 0x6) + + /// PLLSAIDIVQ = /8 + public static let Div8 = Self(rawValue: 0x7) + + /// PLLSAIDIVQ = /9 + public static let Div9 = Self(rawValue: 0x8) + + /// PLLSAIDIVQ = /10 + public static let Div10 = Self(rawValue: 0x9) + + /// PLLSAIDIVQ = /11 + public static let Div11 = Self(rawValue: 0xa) + + /// PLLSAIDIVQ = /12 + public static let Div12 = Self(rawValue: 0xb) + + /// PLLSAIDIVQ = /13 + public static let Div13 = Self(rawValue: 0xc) + + /// PLLSAIDIVQ = /14 + public static let Div14 = Self(rawValue: 0xd) + + /// PLLSAIDIVQ = /15 + public static let Div15 = Self(rawValue: 0xe) + + /// PLLSAIDIVQ = /16 + public static let Div16 = Self(rawValue: 0xf) + + /// PLLSAIDIVQ = /17 + public static let Div17 = Self(rawValue: 0x10) + + /// PLLSAIDIVQ = /18 + public static let Div18 = Self(rawValue: 0x11) + + /// PLLSAIDIVQ = /19 + public static let Div19 = Self(rawValue: 0x12) + + /// PLLSAIDIVQ = /20 + public static let Div20 = Self(rawValue: 0x13) + + /// PLLSAIDIVQ = /21 + public static let Div21 = Self(rawValue: 0x14) + + /// PLLSAIDIVQ = /22 + public static let Div22 = Self(rawValue: 0x15) + + /// PLLSAIDIVQ = /23 + public static let Div23 = Self(rawValue: 0x16) + + /// PLLSAIDIVQ = /24 + public static let Div24 = Self(rawValue: 0x17) + + /// PLLSAIDIVQ = /25 + public static let Div25 = Self(rawValue: 0x18) + + /// PLLSAIDIVQ = /26 + public static let Div26 = Self(rawValue: 0x19) + + /// PLLSAIDIVQ = /27 + public static let Div27 = Self(rawValue: 0x1a) + + /// PLLSAIDIVQ = /28 + public static let Div28 = Self(rawValue: 0x1b) + + /// PLLSAIDIVQ = /29 + public static let Div29 = Self(rawValue: 0x1c) + + /// PLLSAIDIVQ = /30 + public static let Div30 = Self(rawValue: 0x1d) + + /// PLLSAIDIVQ = /31 + public static let Div31 = Self(rawValue: 0x1e) + + /// PLLSAIDIVQ = /32 + public static let Div32 = Self(rawValue: 0x1f) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + public struct PLLSAIDIVRValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// PLLSAIDIVR = /2 + public static let Div2 = Self(rawValue: 0x0) + + /// PLLSAIDIVR = /4 + public static let Div4 = Self(rawValue: 0x1) + + /// PLLSAIDIVR = /8 + public static let Div8 = Self(rawValue: 0x2) + + /// PLLSAIDIVR = /16 + public static let Div16 = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + public struct SAI1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + public static let PLLSAI = Self(rawValue: 0x0) + + /// SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + public static let PLLI2S = Self(rawValue: 0x1) + + /// SAI1 clock frequency = Alternate function input frequency + public static let AFIF = Self(rawValue: 0x2) + + /// SAI1 clock frequency = HSI or HSE + public static let HSI_HSE = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + public struct SAI2SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + public static let PLLSAI = Self(rawValue: 0x0) + + /// SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + public static let PLLI2S = Self(rawValue: 0x1) + + /// SAI2 clock frequency = Alternate function input frequency + public static let AFIF = Self(rawValue: 0x2) + + /// SAI2 clock frequency = HSI or HSE + public static let HSI_HSE = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + public struct TIMPREValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx + public static let Mul1Or2 = Self(rawValue: 0x0) + + /// If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx + public static let Mul1Or4 = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + public struct USART1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// APB2 clock (PCLK2) is selected as USART clock + public static let APB2 = Self(rawValue: 0x0) + + /// System clock is selected as USART clock + public static let SYSCLK = Self(rawValue: 0x1) + + /// HSI clock is selected as USART clock + public static let HSI = Self(rawValue: 0x2) + + /// LSE clock is selected as USART clock + public static let LSE = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + public struct USART2SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// APB1 clock (PCLK1) is selected as USART clock + public static let APB1 = Self(rawValue: 0x0) + + /// System clock is selected as USART clock + public static let SYSCLK = Self(rawValue: 0x1) + + /// HSI clock is selected as USART clock + public static let HSI = Self(rawValue: 0x2) + + /// LSE clock is selected as USART clock + public static let LSE = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + public struct I2C1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// APB clock selected as I2C clock + public static let APB = Self(rawValue: 0x0) + + /// System clock selected as I2C clock + public static let SYSCLK = Self(rawValue: 0x1) + + /// HSI clock selected as I2C clock + public static let HSI = Self(rawValue: 0x2) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + public struct LPTIM1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// APB1 clock (PCLK1) selected as LPTILM1 clock + public static let APB1 = Self(rawValue: 0x0) + + /// LSI clock is selected as LPTILM1 clock + public static let LSI = Self(rawValue: 0x1) + + /// HSI clock is selected as LPTILM1 clock + public static let HSI = Self(rawValue: 0x2) + + /// LSE clock is selected as LPTILM1 clock + public static let LSE = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + public struct CECSELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// LSE clock is selected as HDMI-CEC clock + public static let LSE = Self(rawValue: 0x0) + + /// HSI divided by 488 clock is selected as HDMI-CEC clock + public static let HSI_Div488 = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + public struct CK48MSELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// 48MHz clock from PLL is selected + public static let PLL = Self(rawValue: 0x0) + + /// 48MHz clock from PLLSAI is selected + public static let PLLSAI = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + public struct SDMMC1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// 48 MHz clock is selected as SD clock + public static let CK48M = Self(rawValue: 0x0) + + /// System clock is selected as SD clock + public static let SYSCLK = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} diff --git a/stm32-lvgl/Sources/Registers/SCB.swift b/stm32-lvgl/Sources/Registers/SCB.swift new file mode 100644 index 0000000..08a12ae --- /dev/null +++ b/stm32-lvgl/Sources/Registers/SCB.swift @@ -0,0 +1,429 @@ +// Generated by svd2swift. + +import MMIO + +/// System control block +@RegisterBlock +public struct SCB { + /// CPUID base register + @RegisterBlock(offset: 0x0) + public var cpuid: Register + + /// Interrupt control and state register + @RegisterBlock(offset: 0x4) + public var icsr: Register + + /// Vector table offset register + @RegisterBlock(offset: 0x8) + public var vtor: Register + + /// Application interrupt and reset control register + @RegisterBlock(offset: 0xc) + public var aircr: Register + + /// System control register + @RegisterBlock(offset: 0x10) + public var scr: Register + + /// Configuration and control register + @RegisterBlock(offset: 0x14) + public var ccr: Register + + /// System handler priority registers + @RegisterBlock(offset: 0x18) + public var shpr1: Register + + /// System handler priority registers + @RegisterBlock(offset: 0x1c) + public var shpr2: Register + + /// System handler priority registers + @RegisterBlock(offset: 0x20) + public var shpr3: Register + + /// System handler control and state register + @RegisterBlock(offset: 0x24) + public var shcrs: Register + + /// Configurable fault status register + @RegisterBlock(offset: 0x28) + public var cfsr_ufsr_bfsr_mmfsr: Register + + /// Hard fault status register + @RegisterBlock(offset: 0x2c) + public var hfsr: Register + + /// Memory management fault address register + @RegisterBlock(offset: 0x34) + public var mmfar: Register + + /// Bus fault address register + @RegisterBlock(offset: 0x38) + public var bfar: Register +} + +extension SCB { + /// CPUID base register + @Register(bitWidth: 32) + public struct CPUID { + /// Revision number + @ReadOnly(bits: 0..<4) + public var revision: Revision + + /// Part number of the processor + @ReadOnly(bits: 4..<16) + public var partno: PartNo + + /// Reads as 0xF + @ReadOnly(bits: 16..<20) + public var constant: Constant + + /// Variant number + @ReadOnly(bits: 20..<24) + public var variant: Variant + + /// Implementer code + @ReadOnly(bits: 24..<32) + public var implementer: Implementer + } + + /// Interrupt control and state register + @Register(bitWidth: 32) + public struct ICSR { + /// Active vector + @ReadWrite(bits: 0..<9) + public var vectactive: VECTACTIVE + + /// Return to base level + @ReadWrite(bits: 11..<12) + public var rettobase: RETTOBASE + + /// Pending vector + @ReadWrite(bits: 12..<19) + public var vectpending: VECTPENDING + + /// Interrupt pending flag + @ReadWrite(bits: 22..<23) + public var isrpending: ISRPENDING + + /// SysTick exception clear-pending bit + @ReadWrite(bits: 25..<26) + public var pendstclr: PENDSTCLR + + /// SysTick exception set-pending bit + @ReadWrite(bits: 26..<27) + public var pendstset: PENDSTSET + + /// PendSV clear-pending bit + @ReadWrite(bits: 27..<28) + public var pendsvclr: PENDSVCLR + + /// PendSV set-pending bit + @ReadWrite(bits: 28..<29) + public var pendsvset: PENDSVSET + + /// NMI set-pending bit. + @ReadWrite(bits: 31..<32) + public var nmipendset: NMIPENDSET + } + + /// Vector table offset register + @Register(bitWidth: 32) + public struct VTOR { + /// Vector table base offset field + @ReadWrite(bits: 9..<30) + public var tbloff: TBLOFF + } + + /// Application interrupt and reset control register + @Register(bitWidth: 32) + public struct AIRCR { + /// VECTRESET + @ReadWrite(bits: 0..<1) + public var vectreset: VECTRESET + + /// VECTCLRACTIVE + @ReadWrite(bits: 1..<2) + public var vectclractive: VECTCLRACTIVE + + /// SYSRESETREQ + @ReadWrite(bits: 2..<3) + public var sysresetreq: SYSRESETREQ + + /// PRIGROUP + @ReadWrite(bits: 8..<11) + public var prigroup: PRIGROUP + + /// ENDIANESS + @ReadWrite(bits: 15..<16) + public var endianess: ENDIANESS + + /// Register key + @ReadWrite(bits: 16..<32) + public var vectkeystat: VECTKEYSTAT + } + + /// System control register + @Register(bitWidth: 32) + public struct SCR { + /// SLEEPONEXIT + @ReadWrite(bits: 1..<2) + public var sleeponexit: SLEEPONEXIT + + /// SLEEPDEEP + @ReadWrite(bits: 2..<3) + public var sleepdeep: SLEEPDEEP + + /// Send Event on Pending bit + @ReadWrite(bits: 4..<5) + public var seveonpend: SEVEONPEND + } + + /// Configuration and control register + @Register(bitWidth: 32) + public struct CCR { + /// Configures how the processor enters Thread mode + @ReadWrite(bits: 0..<1) + public var nonbasethrdena: NONBASETHRDENA + + /// USERSETMPEND + @ReadWrite(bits: 1..<2) + public var usersetmpend: USERSETMPEND + + /// UNALIGN_ TRP + @ReadWrite(bits: 3..<4) + public var unalign__trp: UNALIGN__TRP + + /// DIV_0_TRP + @ReadWrite(bits: 4..<5) + public var div_0_trp: DIV_0_TRP + + /// BFHFNMIGN + @ReadWrite(bits: 8..<9) + public var bfhfnmign: BFHFNMIGN + + /// STKALIGN + @ReadWrite(bits: 9..<10) + public var stkalign: STKALIGN + + /// DC + @ReadWrite(bits: 16..<17) + public var dc: DC + + /// IC + @ReadWrite(bits: 17..<18) + public var ic: IC + + /// BP + @ReadWrite(bits: 18..<19) + public var bp: BP + } + + /// System handler priority registers + @Register(bitWidth: 32) + public struct SHPR1 { + /// Priority of system handler 4 + @ReadWrite(bits: 0..<8) + public var pri_4: PRI_4 + + /// Priority of system handler 5 + @ReadWrite(bits: 8..<16) + public var pri_5: PRI_5 + + /// Priority of system handler 6 + @ReadWrite(bits: 16..<24) + public var pri_6: PRI_6 + } + + /// System handler priority registers + @Register(bitWidth: 32) + public struct SHPR2 { + /// Priority of system handler 11 + @ReadWrite(bits: 24..<32) + public var pri_11: PRI_11 + } + + /// System handler priority registers + @Register(bitWidth: 32) + public struct SHPR3 { + /// Priority of system handler 14 + @ReadWrite(bits: 16..<24) + public var pri_14: PRI_14 + + /// Priority of system handler 15 + @ReadWrite(bits: 24..<32) + public var pri_15: PRI_15 + } + + /// System handler control and state register + @Register(bitWidth: 32) + public struct SHCRS { + /// Memory management fault exception active bit + @ReadWrite(bits: 0..<1) + public var memfaultact: MEMFAULTACT + + /// Bus fault exception active bit + @ReadWrite(bits: 1..<2) + public var busfaultact: BUSFAULTACT + + /// Usage fault exception active bit + @ReadWrite(bits: 3..<4) + public var usgfaultact: USGFAULTACT + + /// SVC call active bit + @ReadWrite(bits: 7..<8) + public var svcallact: SVCALLACT + + /// Debug monitor active bit + @ReadWrite(bits: 8..<9) + public var monitoract: MONITORACT + + /// PendSV exception active bit + @ReadWrite(bits: 10..<11) + public var pendsvact: PENDSVACT + + /// SysTick exception active bit + @ReadWrite(bits: 11..<12) + public var systickact: SYSTICKACT + + /// Usage fault exception pending bit + @ReadWrite(bits: 12..<13) + public var usgfaultpended: USGFAULTPENDED + + /// Memory management fault exception pending bit + @ReadWrite(bits: 13..<14) + public var memfaultpended: MEMFAULTPENDED + + /// Bus fault exception pending bit + @ReadWrite(bits: 14..<15) + public var busfaultpended: BUSFAULTPENDED + + /// SVC call pending bit + @ReadWrite(bits: 15..<16) + public var svcallpended: SVCALLPENDED + + /// Memory management fault enable bit + @ReadWrite(bits: 16..<17) + public var memfaultena: MEMFAULTENA + + /// Bus fault enable bit + @ReadWrite(bits: 17..<18) + public var busfaultena: BUSFAULTENA + + /// Usage fault enable bit + @ReadWrite(bits: 18..<19) + public var usgfaultena: USGFAULTENA + } + + /// Configurable fault status register + @Register(bitWidth: 32) + public struct CFSR_UFSR_BFSR_MMFSR { + /// IACCVIOL + @ReadWrite(bits: 0..<1) + public var iaccviol: IACCVIOL + + /// DACCVIOL + @ReadWrite(bits: 1..<2) + public var daccviol: DACCVIOL + + /// MUNSTKERR + @ReadWrite(bits: 3..<4) + public var munstkerr: MUNSTKERR + + /// MSTKERR + @ReadWrite(bits: 4..<5) + public var mstkerr: MSTKERR + + /// MLSPERR + @ReadWrite(bits: 5..<6) + public var mlsperr: MLSPERR + + /// MMARVALID + @ReadWrite(bits: 7..<8) + public var mmarvalid: MMARVALID + + /// Instruction bus error + @ReadWrite(bits: 8..<9) + public var ibuserr: IBUSERR + + /// Precise data bus error + @ReadWrite(bits: 9..<10) + public var preciserr: PRECISERR + + /// Imprecise data bus error + @ReadWrite(bits: 10..<11) + public var impreciserr: IMPRECISERR + + /// Bus fault on unstacking for a return from exception + @ReadWrite(bits: 11..<12) + public var unstkerr: UNSTKERR + + /// Bus fault on stacking for exception entry + @ReadWrite(bits: 12..<13) + public var stkerr: STKERR + + /// Bus fault on floating-point lazy state preservation + @ReadWrite(bits: 13..<14) + public var lsperr: LSPERR + + /// Bus Fault Address Register (BFAR) valid flag + @ReadWrite(bits: 15..<16) + public var bfarvalid: BFARVALID + + /// Undefined instruction usage fault + @ReadWrite(bits: 16..<17) + public var undefinstr: UNDEFINSTR + + /// Invalid state usage fault + @ReadWrite(bits: 17..<18) + public var invstate: INVSTATE + + /// Invalid PC load usage fault + @ReadWrite(bits: 18..<19) + public var invpc: INVPC + + /// No coprocessor usage fault. + @ReadWrite(bits: 19..<20) + public var nocp: NOCP + + /// Unaligned access usage fault + @ReadWrite(bits: 24..<25) + public var unaligned: UNALIGNED + + /// Divide by zero usage fault + @ReadWrite(bits: 25..<26) + public var divbyzero: DIVBYZERO + } + + /// Hard fault status register + @Register(bitWidth: 32) + public struct HFSR { + /// Vector table hard fault + @ReadWrite(bits: 1..<2) + public var vecttbl: VECTTBL + + /// Forced hard fault + @ReadWrite(bits: 30..<31) + public var forced: FORCED + + /// Reserved for Debug use + @ReadWrite(bits: 31..<32) + public var debug_vt: DEBUG_VT + } + + /// Memory management fault address register + @Register(bitWidth: 32) + public struct MMFAR { + /// Memory management fault address + @ReadWrite(bits: 0..<32) + public var address: ADDRESS + } + + /// Bus fault address register + @Register(bitWidth: 32) + public struct BFAR { + /// Bus fault address + @ReadWrite(bits: 0..<32) + public var address: ADDRESS + } +} diff --git a/stm32-lvgl/Sources/Registers/STK.swift b/stm32-lvgl/Sources/Registers/STK.swift new file mode 100644 index 0000000..e5b20c5 --- /dev/null +++ b/stm32-lvgl/Sources/Registers/STK.swift @@ -0,0 +1,77 @@ +// Generated by svd2swift. + +import MMIO + +/// SysTick timer +@RegisterBlock +public struct STK { + /// SysTick control and status register + @RegisterBlock(offset: 0x0) + public var csr: Register + + /// SysTick reload value register + @RegisterBlock(offset: 0x4) + public var rvr: Register + + /// SysTick current value register + @RegisterBlock(offset: 0x8) + public var cvr: Register + + /// SysTick calibration value register + @RegisterBlock(offset: 0xc) + public var calib: Register +} + +extension STK { + /// SysTick control and status register + @Register(bitWidth: 32) + public struct CSR { + /// Counter enable + @ReadWrite(bits: 0..<1) + public var enable: ENABLE + + /// SysTick exception request enable + @ReadWrite(bits: 1..<2) + public var tickint: TICKINT + + /// Clock source selection + @ReadWrite(bits: 2..<3) + public var clksource: CLKSOURCE + + /// COUNTFLAG + @ReadWrite(bits: 16..<17) + public var countflag: COUNTFLAG + } + + /// SysTick reload value register + @Register(bitWidth: 32) + public struct RVR { + /// RELOAD value + @ReadWrite(bits: 0..<24) + public var reload: RELOAD + } + + /// SysTick current value register + @Register(bitWidth: 32) + public struct CVR { + /// Current counter value + @ReadWrite(bits: 0..<24) + public var current: CURRENT + } + + /// SysTick calibration value register + @Register(bitWidth: 32) + public struct CALIB { + /// Calibration value + @ReadWrite(bits: 0..<24) + public var tenms: TENMS + + /// SKEW flag: Indicates whether the TENMS value is exact + @ReadWrite(bits: 30..<31) + public var skew: SKEW + + /// NOREF flag. Reads as zero + @ReadWrite(bits: 31..<32) + public var noref: NOREF + } +} diff --git a/stm32-lvgl/Sources/Registers/SYSCFG.swift b/stm32-lvgl/Sources/Registers/SYSCFG.swift new file mode 100644 index 0000000..cacf50b --- /dev/null +++ b/stm32-lvgl/Sources/Registers/SYSCFG.swift @@ -0,0 +1,161 @@ +// Generated by svd2swift. + +import MMIO + +/// System configuration controller +@RegisterBlock +public struct SYSCFG { + /// memory remap register + @RegisterBlock(offset: 0x0) + public var memrmp: Register + + /// peripheral mode configuration register + @RegisterBlock(offset: 0x4) + public var pmc: Register + + /// external interrupt configuration register 1 + @RegisterBlock(offset: 0x8) + public var exticr1: Register + + /// external interrupt configuration register 2 + @RegisterBlock(offset: 0xc) + public var exticr2: Register + + /// external interrupt configuration register 3 + @RegisterBlock(offset: 0x10) + public var exticr3: Register + + /// external interrupt configuration register 4 + @RegisterBlock(offset: 0x14) + public var exticr4: Register + + /// Compensation cell control register + @RegisterBlock(offset: 0x20) + public var cmpcr: Register +} + +extension SYSCFG { + /// memory remap register + @Register(bitWidth: 32) + public struct MEMRMP { + /// Memory mapping selection + @ReadWrite(bits: 0..<1) + public var mem_boot: MEM_BOOT + + /// FMC memory mapping swap + @ReadWrite(bits: 10..<12) + public var swp_fmc: SWP_FMC + } + + /// peripheral mode configuration register + @Register(bitWidth: 32) + public struct PMC { + /// Ethernet PHY interface selection + @ReadWrite(bits: 23..<24) + public var mii_rmii_sel: MII_RMII_SEL + + /// ADC1DC2 + @ReadWrite(bits: 16..<17) + public var adc1dc2: ADC1DC2 + + /// ADC2DC2 + @ReadWrite(bits: 17..<18) + public var adc2dc2: ADC2DC2 + + /// ADC3DC2 + @ReadWrite(bits: 18..<19) + public var adc3dc2: ADC3DC2 + } + + /// external interrupt configuration register 1 + @Register(bitWidth: 32) + public struct EXTICR1 { + /// EXTI x configuration (x = 0 to 3) + @ReadWrite(bits: 12..<16) + public var exti3: EXTI3 + + /// EXTI x configuration (x = 0 to 3) + @ReadWrite(bits: 8..<12) + public var exti2: EXTI2 + + /// EXTI x configuration (x = 0 to 3) + @ReadWrite(bits: 4..<8) + public var exti1: EXTI1 + + /// EXTI x configuration (x = 0 to 3) + @ReadWrite(bits: 0..<4) + public var exti0: EXTI0 + } + + /// external interrupt configuration register 2 + @Register(bitWidth: 32) + public struct EXTICR2 { + /// EXTI x configuration (x = 4 to 7) + @ReadWrite(bits: 12..<16) + public var exti7: EXTI7 + + /// EXTI x configuration (x = 4 to 7) + @ReadWrite(bits: 8..<12) + public var exti6: EXTI6 + + /// EXTI x configuration (x = 4 to 7) + @ReadWrite(bits: 4..<8) + public var exti5: EXTI5 + + /// EXTI x configuration (x = 4 to 7) + @ReadWrite(bits: 0..<4) + public var exti4: EXTI4 + } + + /// external interrupt configuration register 3 + @Register(bitWidth: 32) + public struct EXTICR3 { + /// EXTI x configuration (x = 8 to 11) + @ReadWrite(bits: 12..<16) + public var exti11: EXTI11 + + /// EXTI10 + @ReadWrite(bits: 8..<12) + public var exti10: EXTI10 + + /// EXTI x configuration (x = 8 to 11) + @ReadWrite(bits: 4..<8) + public var exti9: EXTI9 + + /// EXTI x configuration (x = 8 to 11) + @ReadWrite(bits: 0..<4) + public var exti8: EXTI8 + } + + /// external interrupt configuration register 4 + @Register(bitWidth: 32) + public struct EXTICR4 { + /// EXTI x configuration (x = 12 to 15) + @ReadWrite(bits: 12..<16) + public var exti15: EXTI15 + + /// EXTI x configuration (x = 12 to 15) + @ReadWrite(bits: 8..<12) + public var exti14: EXTI14 + + /// EXTI x configuration (x = 12 to 15) + @ReadWrite(bits: 4..<8) + public var exti13: EXTI13 + + /// EXTI x configuration (x = 12 to 15) + @ReadWrite(bits: 0..<4) + public var exti12: EXTI12 + } + + /// Compensation cell control register + @Register(bitWidth: 32) + public struct CMPCR { + /// READY + @ReadOnly(bits: 8..<9) + public var ready: READY + + /// Compensation cell power-down + @ReadOnly(bits: 0..<1) + public var cmp_pd: CMP_PD + } +} diff --git a/stm32-lvgl/Sources/Registers/USART1.swift b/stm32-lvgl/Sources/Registers/USART1.swift new file mode 100644 index 0000000..04d26f6 --- /dev/null +++ b/stm32-lvgl/Sources/Registers/USART1.swift @@ -0,0 +1,1554 @@ +// Generated by svd2swift. + +import MMIO + +/// Universal synchronous asynchronous receiver transmitter +@RegisterBlock +public struct USART1 { + /// Control register 1 + @RegisterBlock(offset: 0x0) + public var cr1: Register + + /// Control register 2 + @RegisterBlock(offset: 0x4) + public var cr2: Register + + /// Control register 3 + @RegisterBlock(offset: 0x8) + public var cr3: Register + + /// Baud rate register + @RegisterBlock(offset: 0xc) + public var brr: Register + + /// Guard time and prescaler register + @RegisterBlock(offset: 0x10) + public var gtpr: Register + + /// Receiver timeout register + @RegisterBlock(offset: 0x14) + public var rtor: Register + + /// Request register + @RegisterBlock(offset: 0x18) + public var rqr: Register + + /// Interrupt & status register + @RegisterBlock(offset: 0x1c) + public var isr: Register + + /// Interrupt flag clear register + @RegisterBlock(offset: 0x20) + public var icr: Register + + /// Receive data register + @RegisterBlock(offset: 0x24) + public var rdr: Register + + /// Transmit data register + @RegisterBlock(offset: 0x28) + public var tdr: Register +} + +extension USART1 { + /// Control register 1 + @Register(bitWidth: 32) + public struct CR1 { + /// Word length + @ReadWrite(bits: 28..<29, as: M1Values.self) + public var m1: M1 + + /// End of Block interrupt enable + @ReadWrite(bits: 27..<28, as: EOBIEValues.self) + public var eobie: EOBIE + + /// Receiver timeout interrupt enable + @ReadWrite(bits: 26..<27, as: RTOIEValues.self) + public var rtoie: RTOIE + + /// Oversampling mode + @ReadWrite(bits: 15..<16, as: OVER8Values.self) + public var over8: OVER8 + + /// Character match interrupt enable + @ReadWrite(bits: 14..<15, as: CMIEValues.self) + public var cmie: CMIE + + /// Mute mode enable + @ReadWrite(bits: 13..<14, as: MMEValues.self) + public var mme: MME + + /// Word length + @ReadWrite(bits: 12..<13, as: M0Values.self) + public var m0: M0 + + /// Receiver wakeup method + @ReadWrite(bits: 11..<12, as: WAKEValues.self) + public var wake: WAKE + + /// Parity control enable + @ReadWrite(bits: 10..<11, as: PCEValues.self) + public var pce: PCE + + /// Parity selection + @ReadWrite(bits: 9..<10, as: PSValues.self) + public var ps: PS + + /// PE interrupt enable + @ReadWrite(bits: 8..<9, as: PEIEValues.self) + public var peie: PEIE + + /// interrupt enable + @ReadWrite(bits: 7..<8, as: TXEIEValues.self) + public var txeie: TXEIE + + /// Transmission complete interrupt enable + @ReadWrite(bits: 6..<7, as: TCIEValues.self) + public var tcie: TCIE + + /// RXNE interrupt enable + @ReadWrite(bits: 5..<6, as: RXNEIEValues.self) + public var rxneie: RXNEIE + + /// IDLE interrupt enable + @ReadWrite(bits: 4..<5, as: IDLEIEValues.self) + public var idleie: IDLEIE + + /// Transmitter enable + @ReadWrite(bits: 3..<4, as: TEValues.self) + public var te: TE + + /// Receiver enable + @ReadWrite(bits: 2..<3, as: REValues.self) + public var re: RE + + /// USART enable in Stop mode + @ReadWrite(bits: 1..<2, as: UESMValues.self) + public var uesm: UESM + + /// USART enable + @ReadWrite(bits: 0..<1, as: UEValues.self) + public var ue: UE + + /// Driver Enable assertion time + @ReadWrite(bits: 21..<26) + public var deat: DEAT + + /// Driver Enable de-assertion time + @ReadWrite(bits: 16..<21) + public var dedt: DEDT + } + + /// Control register 2 + @Register(bitWidth: 32) + public struct CR2 { + /// Receiver timeout enable + @ReadWrite(bits: 23..<24, as: RTOENValues.self) + public var rtoen: RTOEN + + /// Auto baud rate enable + @ReadWrite(bits: 20..<21, as: ABRENValues.self) + public var abren: ABREN + + /// Most significant bit first + @ReadWrite(bits: 19..<20, as: MSBFIRSTValues.self) + public var msbfirst: MSBFIRST + + /// Binary data inversion + @ReadWrite(bits: 18..<19, as: DATAINVValues.self) + public var datainv: DATAINV + + /// TX pin active level inversion + @ReadWrite(bits: 17..<18, as: TXINVValues.self) + public var txinv: TXINV + + /// RX pin active level inversion + @ReadWrite(bits: 16..<17, as: RXINVValues.self) + public var rxinv: RXINV + + /// Swap TX/RX pins + @ReadWrite(bits: 15..<16, as: SWAPValues.self) + public var swap: SWAP + + /// LIN mode enable + @ReadWrite(bits: 14..<15, as: LINENValues.self) + public var linen: LINEN + + /// STOP bits + @ReadWrite(bits: 12..<14, as: STOPValues.self) + public var stop: STOP + + /// Clock enable + @ReadWrite(bits: 11..<12, as: CLKENValues.self) + public var clken: CLKEN + + /// Clock polarity + @ReadWrite(bits: 10..<11, as: CPOLValues.self) + public var cpol: CPOL + + /// Clock phase + @ReadWrite(bits: 9..<10, as: CPHAValues.self) + public var cpha: CPHA + + /// Last bit clock pulse + @ReadWrite(bits: 8..<9, as: LBCLValues.self) + public var lbcl: LBCL + + /// LIN break detection interrupt enable + @ReadWrite(bits: 6..<7, as: LBDIEValues.self) + public var lbdie: LBDIE + + /// LIN break detection length + @ReadWrite(bits: 5..<6, as: LBDLValues.self) + public var lbdl: LBDL + + /// 7-bit Address Detection/4-bit Address Detection + @ReadWrite(bits: 4..<5, as: ADDM7Values.self) + public var addm7: ADDM7 + + /// Auto baud rate mode + @ReadWrite(bits: 21..<23, as: ABRMODValues.self) + public var abrmod: ABRMOD + + /// Address of the USART node + @ReadWrite(bits: 24..<32) + public var add: ADD + } + + /// Control register 3 + @Register(bitWidth: 32) + public struct CR3 { + /// Wakeup from Stop mode interrupt enable + @ReadWrite(bits: 22..<23, as: WUFIEValues.self) + public var wufie: WUFIE + + /// Wakeup from Stop mode interrupt flag selection + @ReadWrite(bits: 20..<22, as: WUSValues.self) + public var wus: WUS + + /// Smartcard auto-retry count + @ReadWrite(bits: 17..<20) + public var scarcnt: SCARCNT + + /// Driver enable polarity selection + @ReadWrite(bits: 15..<16, as: DEPValues.self) + public var dep: DEP + + /// Driver enable mode + @ReadWrite(bits: 14..<15, as: DEMValues.self) + public var dem: DEM + + /// DMA Disable on Reception Error + @ReadWrite(bits: 13..<14, as: DDREValues.self) + public var ddre: DDRE + + /// Overrun Disable + @ReadWrite(bits: 12..<13, as: OVRDISValues.self) + public var ovrdis: OVRDIS + + /// One sample bit method enable + @ReadWrite(bits: 11..<12, as: ONEBITValues.self) + public var onebit: ONEBIT + + /// CTS interrupt enable + @ReadWrite(bits: 10..<11, as: CTSIEValues.self) + public var ctsie: CTSIE + + /// CTS enable + @ReadWrite(bits: 9..<10, as: CTSEValues.self) + public var ctse: CTSE + + /// RTS enable + @ReadWrite(bits: 8..<9, as: RTSEValues.self) + public var rtse: RTSE + + /// DMA enable transmitter + @ReadWrite(bits: 7..<8, as: DMATValues.self) + public var dmat: DMAT + + /// DMA enable receiver + @ReadWrite(bits: 6..<7, as: DMARValues.self) + public var dmar: DMAR + + /// Smartcard mode enable + @ReadWrite(bits: 5..<6, as: SCENValues.self) + public var scen: SCEN + + /// Smartcard NACK enable + @ReadWrite(bits: 4..<5, as: NACKValues.self) + public var nack: NACK + + /// Half-duplex selection + @ReadWrite(bits: 3..<4, as: HDSELValues.self) + public var hdsel: HDSEL + + /// Ir low-power + @ReadWrite(bits: 2..<3, as: IRLPValues.self) + public var irlp: IRLP + + /// Ir mode enable + @ReadWrite(bits: 1..<2, as: IRENValues.self) + public var iren: IREN + + /// Error interrupt enable + @ReadWrite(bits: 0..<1, as: EIEValues.self) + public var eie: EIE + } + + /// Baud rate register + @Register(bitWidth: 32) + public struct BRR { + /// DIV_Mantissa + @ReadWrite(bits: 0..<16) + public var brr_field: BRR_FIELD + } + + /// Guard time and prescaler register + @Register(bitWidth: 32) + public struct GTPR { + /// Guard time value + @ReadWrite(bits: 8..<16) + public var gt: GT + + /// Prescaler value + @ReadWrite(bits: 0..<8) + public var psc: PSC + } + + /// Receiver timeout register + @Register(bitWidth: 32) + public struct RTOR { + /// Block Length + @ReadWrite(bits: 24..<32) + public var blen: BLEN + + /// Receiver timeout value + @ReadWrite(bits: 0..<24) + public var rto: RTO + } + + /// Request register + @Register(bitWidth: 32) + public struct RQR { + /// Transmit data flush request + @WriteOnly(bits: 4..<5) + public var txfrq: TXFRQ + + /// Receive data flush request + @WriteOnly(bits: 3..<4) + public var rxfrq: RXFRQ + + /// Mute mode request + @WriteOnly(bits: 2..<3) + public var mmrq: MMRQ + + /// Send break request + @WriteOnly(bits: 1..<2) + public var sbkrq: SBKRQ + + /// Auto baud rate request + @WriteOnly(bits: 0..<1) + public var abrrq: ABRRQ + } + + /// Interrupt & status register + @Register(bitWidth: 32) + public struct ISR { + /// REACK + @ReadOnly(bits: 22..<23) + public var reack: REACK + + /// TEACK + @ReadOnly(bits: 21..<22) + public var teack: TEACK + + /// WUF + @ReadOnly(bits: 20..<21) + public var wuf: WUF + + /// RWU + @ReadOnly(bits: 19..<20) + public var rwu: RWU + + /// SBKF + @ReadOnly(bits: 18..<19) + public var sbkf: SBKF + + /// CMF + @ReadOnly(bits: 17..<18) + public var cmf: CMF + + /// BUSY + @ReadOnly(bits: 16..<17) + public var busy: BUSY + + /// ABRF + @ReadOnly(bits: 15..<16) + public var abrf: ABRF + + /// ABRE + @ReadOnly(bits: 14..<15) + public var abre: ABRE + + /// EOBF + @ReadOnly(bits: 12..<13) + public var eobf: EOBF + + /// RTOF + @ReadOnly(bits: 11..<12) + public var rtof: RTOF + + /// CTS + @ReadOnly(bits: 10..<11) + public var cts: CTS + + /// CTSIF + @ReadOnly(bits: 9..<10) + public var ctsif: CTSIF + + /// LBDF + @ReadOnly(bits: 8..<9) + public var lbdf: LBDF + + /// TXE + @ReadOnly(bits: 7..<8) + public var txe: TXE + + /// TC + @ReadOnly(bits: 6..<7) + public var tc: TC + + /// RXNE + @ReadOnly(bits: 5..<6) + public var rxne: RXNE + + /// IDLE + @ReadOnly(bits: 4..<5) + public var idle: IDLE + + /// ORE + @ReadOnly(bits: 3..<4) + public var ore: ORE + + /// NF + @ReadOnly(bits: 2..<3) + public var nf: NF + + /// FE + @ReadOnly(bits: 1..<2) + public var fe: FE + + /// PE + @ReadOnly(bits: 0..<1) + public var pe: PE + } + + /// Interrupt flag clear register + @Register(bitWidth: 32) + public struct ICR { + /// Wakeup from Stop mode clear flag + @WriteOnly(bits: 20..<21) + public var wucf: WUCF + + /// Character match clear flag + @WriteOnly(bits: 17..<18) + public var cmcf: CMCF + + /// End of block clear flag + @WriteOnly(bits: 12..<13) + public var eobcf: EOBCF + + /// Receiver timeout clear flag + @WriteOnly(bits: 11..<12) + public var rtocf: RTOCF + + /// CTS clear flag + @WriteOnly(bits: 9..<10) + public var ctscf: CTSCF + + /// LIN break detection clear flag + @WriteOnly(bits: 8..<9) + public var lbdcf: LBDCF + + /// Transmission complete clear flag + @WriteOnly(bits: 6..<7) + public var tccf: TCCF + + /// Idle line detected clear flag + @WriteOnly(bits: 4..<5) + public var idlecf: IDLECF + + /// Overrun error clear flag + @WriteOnly(bits: 3..<4) + public var orecf: ORECF + + /// Noise detected clear flag + @WriteOnly(bits: 2..<3) + public var ncf: NCF + + /// Framing error clear flag + @WriteOnly(bits: 1..<2) + public var fecf: FECF + + /// Parity error clear flag + @WriteOnly(bits: 0..<1) + public var pecf: PECF + } + + /// Receive data register + @Register(bitWidth: 32) + public struct RDR { + /// Receive data value + @ReadOnly(bits: 0..<9) + public var rdr_field: RDR_FIELD + } + + /// Transmit data register + @Register(bitWidth: 32) + public struct TDR { + /// Transmit data value + @ReadWrite(bits: 0..<9) + public var tdr_field: TDR_FIELD + } +} + +extension USART1.CR1 { + public struct M1Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Use M0 to set the data bits + public static let M0 = Self(rawValue: 0x0) + + /// 1 start bit, 7 data bits, n stop bits + public static let Bit7 = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + public struct EOBIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Interrupt is inhibited + public static let Disabled = Self(rawValue: 0x0) + + /// A USART interrupt is generated when the EOBF flag is set in the ISR register + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + public struct RTOIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Interrupt is inhibited + public static let Disabled = Self(rawValue: 0x0) + + /// An USART interrupt is generated when the RTOF bit is set in the ISR register + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + public struct OVER8Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Oversampling by 16 + public static let Oversampling16 = Self(rawValue: 0x0) + + /// Oversampling by 8 + public static let Oversampling8 = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + public struct CMIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Interrupt is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Interrupt is generated when the CMF bit is set in the ISR register + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + public struct MMEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Receiver in active mode permanently + public static let Disabled = Self(rawValue: 0x0) + + /// Receiver can switch between mute mode and active mode + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + public struct M0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// 1 start bit, 8 data bits, n stop bits + public static let Bit8 = Self(rawValue: 0x0) + + /// 1 start bit, 9 data bits, n stop bits + public static let Bit9 = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + public struct WAKEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Idle line + public static let Idle = Self(rawValue: 0x0) + + /// Address mask + public static let Address = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + public struct PCEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Parity control disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Parity control enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + public struct PSValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Even parity + public static let Even = Self(rawValue: 0x0) + + /// Odd parity + public static let Odd = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + public struct PEIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Interrupt is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Interrupt is generated whenever PE=1 in the ISR register + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + public struct TXEIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Interrupt is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Interrupt is generated whenever TXE=1 in the ISR register + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + public struct TCIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Interrupt is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Interrupt is generated whenever TC=1 in the ISR register + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + public struct RXNEIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Interrupt is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + public struct IDLEIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Interrupt is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Interrupt is generated whenever IDLE=1 in the ISR register + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + public struct TEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Transmitter is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Transmitter is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + public struct REValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Receiver is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Receiver is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + public struct UESMValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// USART not able to wake up the MCU from Stop mode + public static let Disabled = Self(rawValue: 0x0) + + /// USART able to wake up the MCU from Stop mode + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR1 { + public struct UEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// UART is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// UART is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + public struct RTOENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Receiver timeout feature disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Receiver timeout feature enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + public struct ABRENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Auto baud rate detection is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Auto baud rate detection is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + public struct MSBFIRSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// data is transmitted/received with data bit 0 first, following the start bit + public static let LSB = Self(rawValue: 0x0) + + /// data is transmitted/received with MSB (bit 7/8/9) first, following the start bit + public static let MSB = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + public struct DATAINVValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Logical data from the data register are send/received in positive/direct logic + public static let Positive = Self(rawValue: 0x0) + + /// Logical data from the data register are send/received in negative/inverse logic + public static let Negative = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + public struct TXINVValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// TX pin signal works using the standard logic levels + public static let Standard = Self(rawValue: 0x0) + + /// TX pin signal values are inverted + public static let Inverted = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + public struct RXINVValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// RX pin signal works using the standard logic levels + public static let Standard = Self(rawValue: 0x0) + + /// RX pin signal values are inverted + public static let Inverted = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + public struct SWAPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// TX/RX pins are used as defined in standard pinout + public static let Standard = Self(rawValue: 0x0) + + /// The TX and RX pins functions are swapped + public static let Swapped = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + public struct LINENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// LIN mode disabled + public static let Disabled = Self(rawValue: 0x0) + + /// LIN mode enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + public struct STOPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// 1 stop bit + public static let Stop1 = Self(rawValue: 0x0) + + /// 0.5 stop bit + public static let Stop0p5 = Self(rawValue: 0x1) + + /// 2 stop bit + public static let Stop2 = Self(rawValue: 0x2) + + /// 1.5 stop bit + public static let Stop1p5 = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + public struct CLKENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// CK pin disabled + public static let Disabled = Self(rawValue: 0x0) + + /// CK pin enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + public struct CPOLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Steady low value on CK pin outside transmission window + public static let Low = Self(rawValue: 0x0) + + /// Steady high value on CK pin outside transmission window + public static let High = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + public struct CPHAValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// The first clock transition is the first data capture edge + public static let First = Self(rawValue: 0x0) + + /// The second clock transition is the first data capture edge + public static let Second = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + public struct LBCLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// The clock pulse of the last data bit is not output to the CK pin + public static let NotOutput = Self(rawValue: 0x0) + + /// The clock pulse of the last data bit is output to the CK pin + public static let Output = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + public struct LBDIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Interrupt is inhibited + public static let Disabled = Self(rawValue: 0x0) + + /// An interrupt is generated whenever LBDF=1 in the ISR register + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + public struct LBDLValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// 10-bit break detection + public static let Bit10 = Self(rawValue: 0x0) + + /// 11-bit break detection + public static let Bit11 = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + public struct ADDM7Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// 4-bit address detection + public static let Bit4 = Self(rawValue: 0x0) + + /// 7-bit address detection + public static let Bit7 = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR2 { + public struct ABRMODValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// Measurement of the start bit is used to detect the baud rate + public static let Start = Self(rawValue: 0x0) + + /// Falling edge to falling edge measurement + public static let Edge = Self(rawValue: 0x1) + + /// 0x7F frame detection + public static let Frame7F = Self(rawValue: 0x2) + + /// 0x55 frame detection + public static let Frame55 = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + public struct WUFIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Interrupt is inhibited + public static let Disabled = Self(rawValue: 0x0) + + /// An USART interrupt is generated whenever WUF=1 in the ISR register + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + public struct WUSValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// WUF active on address match + public static let Address = Self(rawValue: 0x0) + + /// WuF active on Start bit detection + public static let Start = Self(rawValue: 0x2) + + /// WUF active on RXNE + public static let RXNE = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + public struct DEPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// DE signal is active high + public static let High = Self(rawValue: 0x0) + + /// DE signal is active low + public static let Low = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + public struct DEMValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// DE function is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// The DE signal is output on the RTS pin + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + public struct DDREValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// DMA is not disabled in case of reception error + public static let NotDisabled = Self(rawValue: 0x0) + + /// DMA is disabled following a reception error + public static let Disabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + public struct OVRDISValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Overrun Error Flag, ORE, is set when received data is not read before receiving new data + public static let Enabled = Self(rawValue: 0x0) + + /// Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register + public static let Disabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + public struct ONEBITValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Three sample bit method + public static let Sample3 = Self(rawValue: 0x0) + + /// One sample bit method + public static let Sample1 = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + public struct CTSIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Interrupt is inhibited + public static let Disabled = Self(rawValue: 0x0) + + /// An interrupt is generated whenever CTSIF=1 in the ISR register + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + public struct CTSEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// CTS hardware flow control disabled + public static let Disabled = Self(rawValue: 0x0) + + /// CTS mode enabled, data is only transmitted when the CTS input is asserted + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + public struct RTSEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// RTS hardware flow control disabled + public static let Disabled = Self(rawValue: 0x0) + + /// RTS output enabled, data is only requested when there is space in the receive buffer + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + public struct DMATValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// DMA mode is disabled for transmission + public static let Disabled = Self(rawValue: 0x0) + + /// DMA mode is enabled for transmission + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + public struct DMARValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// DMA mode is disabled for reception + public static let Disabled = Self(rawValue: 0x0) + + /// DMA mode is enabled for reception + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + public struct SCENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Smartcard Mode disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Smartcard Mode enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + public struct NACKValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// NACK transmission in case of parity error is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// NACK transmission during parity error is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + public struct HDSELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Half duplex mode is not selected + public static let NotSelected = Self(rawValue: 0x0) + + /// Half duplex mode is selected + public static let Selected = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + public struct IRLPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Normal mode + public static let Normal = Self(rawValue: 0x0) + + /// Low-power mode + public static let LowPower = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + public struct IRENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// IrDA disabled + public static let Disabled = Self(rawValue: 0x0) + + /// IrDA enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension USART1.CR3 { + public struct EIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Interrupt is inhibited + public static let Disabled = Self(rawValue: 0x0) + + /// An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} diff --git a/stm32-lvgl/Sources/Support/Startup.c b/stm32-lvgl/Sources/Support/Startup.c new file mode 100644 index 0000000..1c70ffa --- /dev/null +++ b/stm32-lvgl/Sources/Support/Startup.c @@ -0,0 +1,163 @@ +//===----------------------------------------------------------------------===// +// +// This source file is part of the Swift open source project +// +// Copyright (c) 2025 Apple Inc. and the Swift project authors. +// Licensed under Apache License v2.0 with Runtime Library Exception +// +// See https://swift.org/LICENSE.txt for license information +// +//===----------------------------------------------------------------------===// + +#include +#include + +void enable_fpu(void) { + *(volatile uint32_t *)0xE000ED88 |= (0xF << 20); // set CP10 and CP11 Full Access +} + +// Reset entrypoint. Enables FPU, relocates the data sections from FLASH to DRAM +// and jumps to main (implemented in Application/Main.swift). +// +// See linkerscript.ld for a detailed explanation. +__attribute__((naked)) __attribute__((noreturn)) void ResetISR(void) { + asm volatile("bl enable_fpu"); + asm volatile("ldr r0, =__data_start // dst"); + asm volatile("ldr r1, =__flash_data_start // src"); + asm volatile("ldr r2, =__flash_data_len // size"); + asm volatile("bl memcpy"); + asm volatile("bl main"); + + // If main returns, spin. + asm volatile("b ."); +} + +// Implemented in Application/Interrupts.swift +void SystickTimerISR(void); +void LtdcIntHandlerISR(void); + +void IntDefaultHandlerISR() { __builtin_trap(); } + +// These are provided by the linker script +extern void *__stack_start; +extern void *__stack_end; + +// Primary interrupt vector table +__attribute__((section(".vectors"))) const void *Vectors[] = { + (void *)(((uintptr_t)&__stack_end) - 4), // initial SP + ResetISR, // 1 0x04 The reset handler + IntDefaultHandlerISR, // 2 0x08 The NMI handler + IntDefaultHandlerISR, // 3 0x0C The hard fault handler + IntDefaultHandlerISR, // 4 0x10 The MPU fault handler + IntDefaultHandlerISR, // 5 0x14 The bus fault handler + IntDefaultHandlerISR, // 6 0x18 The usage fault handler + 0, // 7 0x1c Reserved + 0, // 8 0x20 Reserved + 0, // 9 0x24 Reserved + 0, // 10 0x28 Reserved + IntDefaultHandlerISR, // 11 0x2c SVCall handler + IntDefaultHandlerISR, // 12 0x30 Debug monitor handler + IntDefaultHandlerISR, // 13 0x34 Reserved + IntDefaultHandlerISR, // 14 0x38 The PendSV handler + SystickTimerISR, // 15 0x3c The SysTick handler + IntDefaultHandlerISR, // 16 0x40 + IntDefaultHandlerISR, // 17 0x44 + IntDefaultHandlerISR, // 18 0x48 + IntDefaultHandlerISR, // 19 0x4C + IntDefaultHandlerISR, // 20 0x50 + IntDefaultHandlerISR, // 21 0x54 + IntDefaultHandlerISR, // 22 0x58 + IntDefaultHandlerISR, // 23 0x5C + IntDefaultHandlerISR, // 24 0x60 + IntDefaultHandlerISR, // 25 0x64 + IntDefaultHandlerISR, // 26 0x68 + IntDefaultHandlerISR, // 27 0x6C + IntDefaultHandlerISR, // 28 0x70 + IntDefaultHandlerISR, // 29 0x74 + IntDefaultHandlerISR, // 30 0x78 + IntDefaultHandlerISR, // 31 0x7C + IntDefaultHandlerISR, // 32 0x80 + IntDefaultHandlerISR, // 33 0x84 + IntDefaultHandlerISR, // 34 0x88 + IntDefaultHandlerISR, // 35 0x8c + IntDefaultHandlerISR, // 36 0x90 + IntDefaultHandlerISR, // 37 0x94 + IntDefaultHandlerISR, // 38 0x98 + IntDefaultHandlerISR, // 39 0x9c + IntDefaultHandlerISR, // 40 0xA0 + IntDefaultHandlerISR, // 41 0xA4 + IntDefaultHandlerISR, // 42 0xA8 + IntDefaultHandlerISR, // 43 0xAC + IntDefaultHandlerISR, // 44 0xB0 + IntDefaultHandlerISR, // 45 0xB4 + IntDefaultHandlerISR, // 46 0xB8 + IntDefaultHandlerISR, // 47 0xBC + IntDefaultHandlerISR, // 48 0xC0 + IntDefaultHandlerISR, // 49 0xC4 + IntDefaultHandlerISR, // 50 0xC8 + IntDefaultHandlerISR, // 51 0xCC + IntDefaultHandlerISR, // 52 0xD0 + IntDefaultHandlerISR, // 53 0xD4 + IntDefaultHandlerISR, // 54 0xD8 + IntDefaultHandlerISR, // 55 0xDC + IntDefaultHandlerISR, // 56 0xE0 + IntDefaultHandlerISR, // 57 0xE4 + IntDefaultHandlerISR, // 58 0xE8 + IntDefaultHandlerISR, // 59 0xEC + IntDefaultHandlerISR, // 60 0xF0 + IntDefaultHandlerISR, // 61 0xF4 + IntDefaultHandlerISR, // 62 0xF8 + IntDefaultHandlerISR, // 63 0xFC + IntDefaultHandlerISR, // 64 0x100 + IntDefaultHandlerISR, // 65 0x104 + IntDefaultHandlerISR, // 66 0x108 + IntDefaultHandlerISR, // 67 0x10C + IntDefaultHandlerISR, // 68 0x110 + IntDefaultHandlerISR, // 69 0x114 + IntDefaultHandlerISR, // 70 0x118 + IntDefaultHandlerISR, // 71 0x11C + IntDefaultHandlerISR, // 72 0x120 + IntDefaultHandlerISR, // 73 0x124 + IntDefaultHandlerISR, // 74 0x128 + IntDefaultHandlerISR, // 75 0x12C + IntDefaultHandlerISR, // 76 0x130 + IntDefaultHandlerISR, // 77 0x134 + 0, // 78 0x138 + IntDefaultHandlerISR, // 79 0x13C + IntDefaultHandlerISR, // 80 0x140 + IntDefaultHandlerISR, // 81 0x144 + IntDefaultHandlerISR, // 82 0x148 + IntDefaultHandlerISR, // 83 0x14C + IntDefaultHandlerISR, // 84 0x150 + IntDefaultHandlerISR, // 85 0x154 + IntDefaultHandlerISR, // 86 0x158 + IntDefaultHandlerISR, // 87 0x15C + IntDefaultHandlerISR, // 88 0x160 + IntDefaultHandlerISR, // 89 0x164 + IntDefaultHandlerISR, // 90 0x168 + IntDefaultHandlerISR, // 91 0x16C + IntDefaultHandlerISR, // 92 0x170 + IntDefaultHandlerISR, // 93 0x174 + IntDefaultHandlerISR, // 94 0x178 + 0, // 95 0x17C + 0, // 96 0x180 + IntDefaultHandlerISR, // 97 0x184 + 0, // 98 0x188 + 0, // 99 0x18C + IntDefaultHandlerISR, // 100 0x190 + 0, // 101 0x194 + IntDefaultHandlerISR, // 102 0x198 + IntDefaultHandlerISR, // 103 0x19C + LtdcIntHandlerISR, // 104 0x1A0 + 0, // 105 0x1A4 + 0, // 106 0x1A8 + IntDefaultHandlerISR, // 107 0x1AC + IntDefaultHandlerISR, // 108 0x1B0 + IntDefaultHandlerISR, // 109 0x1B4 + IntDefaultHandlerISR, // 110 0x1B8 + IntDefaultHandlerISR, // 111 0x1BC + IntDefaultHandlerISR, // 112 0x1C0 +}; + +// ELF entrypoint, not actually called at runtime, but it's a GC root +void *_start_elf(void) { return (void *)&Vectors; } diff --git a/stm32-lvgl/Sources/Support/Stubs.c b/stm32-lvgl/Sources/Support/Stubs.c new file mode 100644 index 0000000..c67b280 --- /dev/null +++ b/stm32-lvgl/Sources/Support/Stubs.c @@ -0,0 +1,27 @@ +//===----------------------------------------------------------------------===// +// +// This source file is part of the Swift open source project +// +// Copyright (c) 2025 Apple Inc. and the Swift project authors. +// Licensed under Apache License v2.0 with Runtime Library Exception +// +// See https://swift.org/LICENSE.txt for license information +// +//===----------------------------------------------------------------------===// + +#include +#include + +// This is NOT real entropy. This implementation is a stub that generates +// predictable, sequential values for testing purposes only. Do not use this +// in production code where actual cryptographic randomness is required. +int getentropy(char *buffer, size_t length) { + for (size_t i = 0; i < length; i++) { + buffer[i] = i % 256; + } + return 0; +} + +void _exit(int status) { + __builtin_trap(); +} diff --git a/stm32-lvgl/Sources/Support/include/Support.h b/stm32-lvgl/Sources/Support/include/Support.h new file mode 100644 index 0000000..63765c2 --- /dev/null +++ b/stm32-lvgl/Sources/Support/include/Support.h @@ -0,0 +1,43 @@ +//===----------------------------------------------------------------------===// +// +// This source file is part of the Swift open source project +// +// Copyright (c) 2025 Apple Inc. and the Swift project authors. +// Licensed under Apache License v2.0 with Runtime Library Exception +// +// See https://swift.org/LICENSE.txt for license information +// +//===----------------------------------------------------------------------===// + +#pragma once + +#include + +static inline void nop() { + asm volatile("nop"); +} + +static inline uint32_t primask_get(void) { + uint32_t r; + asm volatile("mrs %0, primask" : "=r" (r)); + return r; +} + +static inline void primask_set(uint32_t m) { + asm volatile("msr primask, %0" : : "r" (m)); +} + +static inline void cpsid_i(void) { + asm volatile("cpsid i"); +} + +static inline void delay(uint32_t i) { + __asm__ volatile( + " .align 2 \n" + "1: subs %0, #1\n" + " bhi 1b\n" + : "=r"(i) + : "0" (i) + : "cc" + ); +} diff --git a/stm32-lvgl/Sources/Support/linkerscript.ld b/stm32-lvgl/Sources/Support/linkerscript.ld new file mode 100644 index 0000000..f3c07fd --- /dev/null +++ b/stm32-lvgl/Sources/Support/linkerscript.ld @@ -0,0 +1,103 @@ +/*===----------------------------------------------------------------------===*/ +/* */ +/* This source file is part of the Swift open source project */ +/* */ +/* Copyright (c) 2025 Apple Inc. and the Swift project authors. */ +/* Licensed under Apache License v2.0 with Runtime Library Exception */ +/* */ +/* See https://swift.org/LICENSE.txt for license information */ +/* */ +/*===----------------------------------------------------------------------===*/ + +/* + * This application uses ELF for linking, and uses the elf2hex.py post-processing tool for package the result into a + * form suitable for flashing. The entire memory layout scheme (which this linker script participates in) is: + * + * - At normal application runtime, the expected memory layout is: + * + * - 0x08000000-0x08100000 (flash) ... code + read-only globals + * - 0x20000000-0x20008000 (SRAM) ... stack + * - 0x20008000-0x20030000 (SRAM) ... read-write globals, and bss (zero initialized globals) + * - 0x20030000-0x20050000 (SRAM) ... heap + * + * - However, this layout cannot be flashed as is (because it uses the SRAM too), so a few more steps are needed. + * + * - In a linked ELF file, the memory locations of the sections match the expected runtime layout. The ELF file does not + * contain the stack and the heap, so we don't have to worry about those (there is also no expectation that the memory + * for those is zeroed out at program start). + * + * - The ELF file is given to the elf2hex.py tool, which will produce a .hex output, and we use the + * --relocate-data-segment flag to relocate the read-write globals region (0x20008000-0x20030000) into the flash + * region, concretely the region is appended at a 4-byte-aligned location after the other contents of the flash. + * + * - This is concretely achieved using the __flash_data_start+__flash_data_len and __data_start+__data_end symbols + * defined in this linker script. The elf2hex.py script finds the addresses of these symbols and performs the + * relocation of those bytes. + * - Note that after the relocation, the segments in ELF headers (PT_LOAD commands) don't match the actual physical + * layout. However, this relocation is reversed at early startup time, so that at "normal" runtime, the layout is + * as expected. See below. + * + * - The ARM core loads the initial stack pointer, and initial program counter from the vector table which is placed at + * a well-known location, concretely the very beginning of flash, 0x08000000. The linker script places the .vectors + * section as the very first section into the flash to satisfy this. See Startup.c for the concrete content of the + * vector table, and how the initial SP and PC are set up. + * + * - The initial startup code (ResetISR in Startup.c) only does one setup step (enabling the FPU) before performing the + * reverse relocation of the data segment. The runtime back-relocation is simply a memcpy from __flash_data_start back + * into __data_start (in the SRAM region). + * + * - During this and before this (e.g. when doing the FPU enablement), read-write globals cannot be used. Reading + * a read-write global won't read the correct initial value of that global. + * - That's why the ResetISR code is written as attribute((naked)) asm implementation. The implementation is also + * very simple and it's easy to see that it indeed does not touch any globals. + * - We expect that the implementation of memcpy is also not accessing any globals. This is a reasonable expectation + * on any embedded-friendly memcpy implementation. + * + * - After that, the normal runtime memory layout is matched, and the application continues to initialize itself and + * run. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K /* end: 0x08100000 */ + sram_stack (rw) : ORIGIN = 0x20000000, LENGTH = 32K /* end: 0x20008000 */ + sram_data (rw) : ORIGIN = 0x20008000, LENGTH = 160K /* end: 0x20030000 */ + sram_heap (rw) : ORIGIN = 0x20030000, LENGTH = 128K /* end: 0x20050000 */ +} + +SECTIONS +{ + .text : { *(.vectors*) ; *(.text*) } > flash + .rodata : { *(.rodata*) ; *(.got*) } > flash + + __flash_data_start = (. + 3) & ~ 3; /* 4-byte aligned end of text is where data is going to be placed (by elf2hex) */ + + .bss : { *(.bss*) } > sram_data + .tbss : { *(.tbss*) } > sram_data + .data : { *(.data*) } > sram_data + + __flash_data_len = . - ORIGIN(sram_data); + + /* TODO: Add a safeguard to detect when adding data to flash would overflow the flash memory */ + + /DISCARD/ : { *(.swift_modhash*) } + + /* ARM metadata sections */ + /DISCARD/ : { *(.ARM.attributes*) *(.ARM.exidx) } + + /* ELF metadata sections */ + .symtab : { *(.symtab) } + .strtab : { *(.strtab) } + .shstrtab : { *(.shstrtab) } + .debug : { *(.debug*) } + .comment : { *(.comment) } +} + +__stack_start = ORIGIN(sram_stack); +__stack_end = ORIGIN(sram_stack) + LENGTH(sram_stack); + +__data_start = ORIGIN(sram_data); +__data_end = ORIGIN(sram_data) + LENGTH(sram_data); + +__heap_start = ORIGIN(sram_heap); +__heap_end = ORIGIN(sram_heap) + LENGTH(sram_heap); diff --git a/stm32-lvgl/clang-arm-toolchain.cmake b/stm32-lvgl/clang-arm-toolchain.cmake new file mode 100644 index 0000000..db28d2d --- /dev/null +++ b/stm32-lvgl/clang-arm-toolchain.cmake @@ -0,0 +1,21 @@ +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR arm) +set(CMAKE_CROSSCOMPILING TRUE) + +# Specify the compilers +set(CMAKE_C_COMPILER "${TOOLCHAIN_PATH}/bin/clang") +set(CMAKE_CXX_COMPILER "${TOOLCHAIN_PATH}/bin/clang++") +set(CMAKE_ASM_COMPILER "${TOOLCHAIN_PATH}/bin/clang") + +# Target flags +set(CMAKE_C_FLAGS "-target arm-none-eabi -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -ffunction-sections -fdata-sections") +set(CMAKE_CXX_FLAGS "${CMAKE_C_FLAGS} -std=c++11 -fno-exceptions -fno-rtti") +set(CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS}") + +# Search paths for libraries +set(CMAKE_FIND_ROOT_PATH "${TOOLCHAIN_PATH}") +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) + +set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) diff --git a/stm32-lvgl/fetch-dependencies.sh b/stm32-lvgl/fetch-dependencies.sh new file mode 100755 index 0000000..02e2eed --- /dev/null +++ b/stm32-lvgl/fetch-dependencies.sh @@ -0,0 +1,63 @@ +#!/bin/bash + +set -vex + +### +### LLVM Embedded Toolchain for ARM +### + +VER=19.1.5 + +if [[ "$(uname -s)" == "Darwin" ]]; then + FILE=LLVM-ET-Arm-${VER}-Darwin-universal + EXT=dmg + SHA=0451e67dc9a9066c17f746c26654962fa3889d4df468db1245d1bae69438eaf5 +elif [[ "$(uname -s)" == "Linux" && "$(uname -m)" == "aarch64" ]]; then + FILE=LLVM-ET-Arm-${VER}-Linux-AArch64 + EXT=tar.xz + SHA=5e2f6b8c77464371ae2d7445114b4bdc19f56138e8aa864495181b52f57d0b85 +elif [[ "$(uname -s)" == "Linux" && "$(uname -m)" == "x86_64" ]]; then + FILE=LLVM-ET-Arm-${VER}-Linux-x86_64 + EXT=tar.xz + SHA=34ee877aadc78c5e9f067e603a1bc9745ed93ca7ae5dbfc9b4406508dc153920 +else + echo "No LLVM toolchain for this OS/arch ($(uname -s), $(uname -m))" + exit 1 +fi + +FOUND=no +SHA_MATCHES=no +if [[ -f /tmp/${FILE}.${EXT} ]]; then + FOUND=yes + if sha256 -c $SHA /tmp/${FILE}.${EXT}; then + SHA_MATCHES=yes + fi +fi + +if [[ "$FOUND" = "no" || "$SHA_MATCHES" = "no" ]]; then + curl https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-${VER}/${FILE}.${EXT} \ + -L -O --output-dir /tmp +fi + +if [[ "$EXT" = "dmg" ]]; then + hdiutil attach /tmp/${FILE}.${EXT} + ls -al /Volumes/${FILE} + rm -r ./llvm-toolchain || true + cp -a /Volumes/${FILE}/${FILE} ./llvm-toolchain + diskutil eject /Volumes/${FILE} +elif [[ "$EXT" = "tar.xz" ]]; then + rm -r ./llvm-toolchain || true + mkdir -p ./llvm-toolchain + tar -xvf /tmp/${FILE}.${EXT} -C ./llvm-toolchain --strip-components 1 +else + exit 1 +fi + + + +### +### LVGL +### + +rm -rf ./lvgl || true +git clone https://github.com/lvgl/lvgl.git --branch release/v9.2 diff --git a/stm32-lvgl/toolset.json b/stm32-lvgl/toolset.json new file mode 100644 index 0000000..ba5ab79 --- /dev/null +++ b/stm32-lvgl/toolset.json @@ -0,0 +1,44 @@ +{ + "schemaVersion": "1.0", + "swiftCompiler": { + "extraCLIOptions": [ + "-Xfrontend", "-disable-stack-protector", + "-enable-experimental-feature", "Embedded", + "-enable-experimental-feature", "Extern", + "-Xclang-linker", "-nostdlib", + "-Xfrontend", "-function-sections", + "-Xfrontend", "-mergeable-symbols", + "-Xfrontend", "-enable-single-module-llvm-emission", + "-assert-config", "Debug", + "-Xclang-linker", "-fuse-ld=lld" + ] + }, + "cCompiler": { + "extraCLIOptions": [ + "-nostdlib", + "-ffunction-sections", + "-Illvm-toolchain/lib/clang-runtimes/arm-none-eabi/armv7m_soft_fpv4_sp_d16_exn_rtti/include", + "-mthumb", + "-Werror", + "-Wall", + "-static", + "-fno-stack-protector", + "-fno-common" + ] + }, + "linker": { + "extraCLIOptions": [ + "-nostdlib", + "-t", "-v", + "-T", "Sources/Support/linkerscript.ld", + "-Lllvm-toolchain/lib/clang-runtimes/arm-none-eabi/armv7m_soft_fpv4_sp_d16_exn_rtti/lib", + "-lc", + "-lclang_rt.builtins", + "-L.build/lvgl/lib", + "-llvgl", "-llvgl_demos", + "-static", + "-e", "_start_elf", + "--orphan-handling=error" + ] + } +}