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Merge pull request #1 from stm32duino/svd_1.16.0
chore: update to STM32CubeCLT version 1.16.0
2 parents 92431b8 + 96a170f commit 4883313

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lines changed

‎svd/STM32C0xx/STM32C071.svd

Lines changed: 67357 additions & 0 deletions
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‎svd/STM32CubeCLT.version

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
1.15.1
1+
1.16.0

‎svd/STM32G0xx/STM32G030.svd

Lines changed: 48 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics.
2020
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
2121
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
2222
<name>STM32G030</name>
23-
<version>1.6</version>
23+
<version>1.7</version>
2424
<description>STM32G030</description>
2525
<cpu>
2626
<name>CM0</name>
@@ -3968,6 +3968,53 @@ Note: The software is allowed to write this bit only when ADSTART=0 (which ensur
39683968
</field>
39693969
</fields>
39703970
</register>
3971+
<register>
3972+
<name>ECCR2</name>
3973+
<displayName>ECCR2</displayName>
3974+
<description>Flash ECC register 2</description>
3975+
<addressOffset>0x01C</addressOffset>
3976+
<size>0x20</size>
3977+
<resetValue>0x00000000</resetValue>
3978+
<fields>
3979+
<field>
3980+
<name>ADDR_ECC</name>
3981+
<description>ECC fail address</description>
3982+
<bitOffset>0</bitOffset>
3983+
<bitWidth>14</bitWidth>
3984+
<access>read-only</access>
3985+
</field>
3986+
<field>
3987+
<name>SYSF_ECC</name>
3988+
<description>ECC fail for Corrected ECC Error or
3989+
Double ECC Error in info block</description>
3990+
<bitOffset>20</bitOffset>
3991+
<bitWidth>1</bitWidth>
3992+
<access>read-only</access>
3993+
</field>
3994+
<field>
3995+
<name>ECCIE</name>
3996+
<description>ECC correction interrupt
3997+
enable</description>
3998+
<bitOffset>24</bitOffset>
3999+
<bitWidth>1</bitWidth>
4000+
<access>read-write</access>
4001+
</field>
4002+
<field>
4003+
<name>ECCC</name>
4004+
<description>ECC correction</description>
4005+
<bitOffset>30</bitOffset>
4006+
<bitWidth>1</bitWidth>
4007+
<access>read-write</access>
4008+
</field>
4009+
<field>
4010+
<name>ECCD</name>
4011+
<description>ECC detection</description>
4012+
<bitOffset>31</bitOffset>
4013+
<bitWidth>1</bitWidth>
4014+
<access>read-write</access>
4015+
</field>
4016+
</fields>
4017+
</register>
39714018
<register>
39724019
<name>OPTR</name>
39734020
<displayName>OPTR</displayName>

‎svd/STM32G0xx/STM32G031.svd

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics.
2020
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
2121
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
2222
<name>STM32G031</name>
23-
<version>1.6</version>
23+
<version>1.7</version>
2424
<description>STM32G031</description>
2525
<cpu>
2626
<name>CM0</name>
@@ -608,7 +608,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
608608
<name>ADDR_ECC</name>
609609
<description>ECC fail address</description>
610610
<bitOffset>0</bitOffset>
611-
<bitWidth>15</bitWidth>
611+
<bitWidth>14</bitWidth>
612612
<access>read-only</access>
613613
</field>
614614
<field>

‎svd/STM32G0xx/STM32G041.svd

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics.
2020
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
2121
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
2222
<name>STM32G041</name>
23-
<version>1.5</version>
23+
<version>1.6</version>
2424
<description>STM32G041</description>
2525
<cpu>
2626
<name>CM0</name>
@@ -608,7 +608,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
608608
<name>ADDR_ECC</name>
609609
<description>ECC fail address</description>
610610
<bitOffset>0</bitOffset>
611-
<bitWidth>15</bitWidth>
611+
<bitWidth>14</bitWidth>
612612
<access>read-only</access>
613613
</field>
614614
<field>

‎svd/STM32G0xx/STM32G050.svd

Lines changed: 48 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics.
1818
-->
1919
<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
2020
<name>STM32G050</name>
21-
<version>1.3</version>
21+
<version>1.4</version>
2222
<description>STM32G050</description>
2323
<cpu>
2424
<name>CM0</name>
@@ -11076,6 +11076,53 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
1107611076
</field>
1107711077
</fields>
1107811078
</register>
11079+
<register>
11080+
<name>ECCR2</name>
11081+
<displayName>ECCR2</displayName>
11082+
<description>Flash ECC register 2</description>
11083+
<addressOffset>0x01C</addressOffset>
11084+
<size>0x20</size>
11085+
<resetValue>0x00000000</resetValue>
11086+
<fields>
11087+
<field>
11088+
<name>ADDR_ECC</name>
11089+
<description>ECC fail address</description>
11090+
<bitOffset>0</bitOffset>
11091+
<bitWidth>14</bitWidth>
11092+
<access>read-only</access>
11093+
</field>
11094+
<field>
11095+
<name>SYSF_ECC</name>
11096+
<description>ECC fail for Corrected ECC Error or
11097+
Double ECC Error in info block</description>
11098+
<bitOffset>20</bitOffset>
11099+
<bitWidth>1</bitWidth>
11100+
<access>read-only</access>
11101+
</field>
11102+
<field>
11103+
<name>ECCIE</name>
11104+
<description>ECC correction interrupt
11105+
enable</description>
11106+
<bitOffset>24</bitOffset>
11107+
<bitWidth>1</bitWidth>
11108+
<access>read-write</access>
11109+
</field>
11110+
<field>
11111+
<name>ECCC</name>
11112+
<description>ECC correction</description>
11113+
<bitOffset>30</bitOffset>
11114+
<bitWidth>1</bitWidth>
11115+
<access>read-write</access>
11116+
</field>
11117+
<field>
11118+
<name>ECCD</name>
11119+
<description>ECC detection</description>
11120+
<bitOffset>31</bitOffset>
11121+
<bitWidth>1</bitWidth>
11122+
<access>read-write</access>
11123+
</field>
11124+
</fields>
11125+
</register>
1107911126
<register>
1108011127
<name>OPTR</name>
1108111128
<displayName>OPTR</displayName>

‎svd/STM32G0xx/STM32G051.svd

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics.
1818
-->
1919
<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
2020
<name>STM32G051</name>
21-
<version>1.4</version>
21+
<version>1.5</version>
2222
<description>STM32G051</description>
2323
<cpu>
2424
<name>CM0</name>
@@ -4074,7 +4074,7 @@ This bit is set by software and cleared by a system reset. It locks the whole co
40744074
</register>
40754075
<register>
40764076
<name>COMP3_CSR</name>
4077-
<displayName>COMP2_CSR</displayName>
4077+
<displayName>COMP3_CSR</displayName>
40784078
<description>Comparator 2 control and status register </description>
40794079
<addressOffset>0x8</addressOffset>
40804080
<size>0x20</size>
@@ -12706,7 +12706,7 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
1270612706
<name>ADDR_ECC</name>
1270712707
<description>ECC fail address</description>
1270812708
<bitOffset>0</bitOffset>
12709-
<bitWidth>15</bitWidth>
12709+
<bitWidth>14</bitWidth>
1271012710
<access>read-only</access>
1271112711
</field>
1271212712
<field>

‎svd/STM32G0xx/STM32G061.svd

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics.
1818
-->
1919
<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
2020
<name>STM32G061</name>
21-
<version>1.4</version>
21+
<version>1.5</version>
2222
<description>STM32G061</description>
2323
<cpu>
2424
<name>CM0</name>
@@ -12772,7 +12772,7 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
1277212772
<name>ADDR_ECC</name>
1277312773
<description>ECC fail address</description>
1277412774
<bitOffset>0</bitOffset>
12775-
<bitWidth>15</bitWidth>
12775+
<bitWidth>14</bitWidth>
1277612776
<access>read-only</access>
1277712777
</field>
1277812778
<field>

‎svd/STM32G0xx/STM32G070.svd

Lines changed: 48 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics.
2020
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
2121
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
2222
<name>STM32G070</name>
23-
<version>1.9</version>
23+
<version>2.0</version>
2424
<description>STM32G070</description>
2525
<cpu>
2626
<name>CM0</name>
@@ -4049,6 +4049,53 @@ Note: The software is allowed to write this bit only when ADSTART=0 (which ensur
40494049
</field>
40504050
</fields>
40514051
</register>
4052+
<register>
4053+
<name>ECCR2</name>
4054+
<displayName>ECCR2</displayName>
4055+
<description>Flash ECC register 2</description>
4056+
<addressOffset>0x01C</addressOffset>
4057+
<size>0x20</size>
4058+
<resetValue>0x00000000</resetValue>
4059+
<fields>
4060+
<field>
4061+
<name>ADDR_ECC</name>
4062+
<description>ECC fail address</description>
4063+
<bitOffset>0</bitOffset>
4064+
<bitWidth>14</bitWidth>
4065+
<access>read-only</access>
4066+
</field>
4067+
<field>
4068+
<name>SYSF_ECC</name>
4069+
<description>ECC fail for Corrected ECC Error or
4070+
Double ECC Error in info block</description>
4071+
<bitOffset>20</bitOffset>
4072+
<bitWidth>1</bitWidth>
4073+
<access>read-only</access>
4074+
</field>
4075+
<field>
4076+
<name>ECCIE</name>
4077+
<description>ECC correction interrupt
4078+
enable</description>
4079+
<bitOffset>24</bitOffset>
4080+
<bitWidth>1</bitWidth>
4081+
<access>read-write</access>
4082+
</field>
4083+
<field>
4084+
<name>ECCC</name>
4085+
<description>ECC correction</description>
4086+
<bitOffset>30</bitOffset>
4087+
<bitWidth>1</bitWidth>
4088+
<access>read-write</access>
4089+
</field>
4090+
<field>
4091+
<name>ECCD</name>
4092+
<description>ECC detection</description>
4093+
<bitOffset>31</bitOffset>
4094+
<bitWidth>1</bitWidth>
4095+
<access>read-write</access>
4096+
</field>
4097+
</fields>
4098+
</register>
40524099
<register>
40534100
<name>OPTR</name>
40544101
<displayName>OPTR</displayName>

‎svd/STM32G0xx/STM32G071.svd

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics.
2020
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
2121
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
2222
<name>STM32G071</name>
23-
<version>2.5</version>
23+
<version>2.6</version>
2424
<description>STM32G071</description>
2525
<cpu>
2626
<name>CM0</name>
@@ -689,7 +689,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
689689
<name>ADDR_ECC</name>
690690
<description>ECC fail address</description>
691691
<bitOffset>0</bitOffset>
692-
<bitWidth>15</bitWidth>
692+
<bitWidth>14</bitWidth>
693693
<access>read-only</access>
694694
</field>
695695
<field>

‎svd/STM32G0xx/STM32G081.svd

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics.
2020
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
2121
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
2222
<name>STM32G081</name>
23-
<version>1.8</version>
23+
<version>1.9</version>
2424
<description>STM32G081</description>
2525
<cpu>
2626
<name>CM0</name>
@@ -689,7 +689,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
689689
<name>ADDR_ECC</name>
690690
<description>ECC fail address</description>
691691
<bitOffset>0</bitOffset>
692-
<bitWidth>15</bitWidth>
692+
<bitWidth>14</bitWidth>
693693
<access>read-only</access>
694694
</field>
695695
<field>

‎svd/STM32G0xx/STM32G0B0.svd

Lines changed: 49 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics.
2020
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
2121
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
2222
<name>STM32G0B0</name>
23-
<version>1.6</version>
23+
<version>1.7</version>
2424
<description>STM32G0B0</description>
2525
<cpu>
2626
<name>CM0</name>
@@ -10441,6 +10441,53 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
1044110441
</field>
1044210442
</fields>
1044310443
</register>
10444+
<register>
10445+
<name>ECCR2</name>
10446+
<displayName>ECCR2</displayName>
10447+
<description>Flash ECC register 2</description>
10448+
<addressOffset>0x01C</addressOffset>
10449+
<size>0x20</size>
10450+
<resetValue>0x00000000</resetValue>
10451+
<fields>
10452+
<field>
10453+
<name>ADDR_ECC</name>
10454+
<description>ECC fail address</description>
10455+
<bitOffset>0</bitOffset>
10456+
<bitWidth>14</bitWidth>
10457+
<access>read-only</access>
10458+
</field>
10459+
<field>
10460+
<name>SYSF_ECC</name>
10461+
<description>ECC fail for Corrected ECC Error or
10462+
Double ECC Error in info block</description>
10463+
<bitOffset>20</bitOffset>
10464+
<bitWidth>1</bitWidth>
10465+
<access>read-only</access>
10466+
</field>
10467+
<field>
10468+
<name>ECCIE</name>
10469+
<description>ECC correction interrupt
10470+
enable</description>
10471+
<bitOffset>24</bitOffset>
10472+
<bitWidth>1</bitWidth>
10473+
<access>read-write</access>
10474+
</field>
10475+
<field>
10476+
<name>ECCC</name>
10477+
<description>ECC correction</description>
10478+
<bitOffset>30</bitOffset>
10479+
<bitWidth>1</bitWidth>
10480+
<access>read-write</access>
10481+
</field>
10482+
<field>
10483+
<name>ECCD</name>
10484+
<description>ECC detection</description>
10485+
<bitOffset>31</bitOffset>
10486+
<bitWidth>1</bitWidth>
10487+
<access>read-write</access>
10488+
</field>
10489+
</fields>
10490+
</register>
1044410491
<register>
1044510492
<name>OPTR</name>
1044610493
<displayName>OPTR</displayName>
@@ -10532,7 +10579,7 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
1053210579
<bitWidth>1</bitWidth>
1053310580
</field>
1053410581
</fields>
10535-
</register>
10582+
</register>
1053610583
<register>
1053710584
<name>WRP1AR</name>
1053810585
<displayName>WRP1AR</displayName>

‎svd/STM32G0xx/STM32G0B1.svd

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics.
2020
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
2121
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
2222
<name>STM32G0B1</name>
23-
<version>1.8</version>
23+
<version>1.9</version>
2424
<description>STM32G0B1</description>
2525
<cpu>
2626
<name>CM0</name>
@@ -16111,7 +16111,7 @@ These are protected write (P) bits, which means that write access by the bits is
1611116111
<name>ADDR_ECC</name>
1611216112
<description>ECC fail address</description>
1611316113
<bitOffset>0</bitOffset>
16114-
<bitWidth>15</bitWidth>
16114+
<bitWidth>14</bitWidth>
1611516115
<access>read-only</access>
1611616116
</field>
1611716117
<field>

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