diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h index cda513ca29..c6a6979724 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h @@ -933,127 +933,127 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 256 KB) base address */ -#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 48 KB) base address */ -#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(16 KB) base address */ -#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */ -#define QSPI_BASE ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 256 KB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 48 KB) base address */ +#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(16 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ -#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */ -#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ +#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ /* Legacy defines */ #define SRAM_BASE SRAM1_BASE #define SRAM_BB_BASE SRAM1_BB_BASE -#define SRAM1_SIZE_MAX ((uint32_t)0x0000C000U) /*!< maximum SRAM1 size (up to 48 KBytes) */ -#define SRAM2_SIZE ((uint32_t)0x00004000U) /*!< SRAM2 size (16 KBytes) */ +#define SRAM1_SIZE_MAX (0x0000C000UL) /*!< maximum SRAM1 size (up to 48 KBytes) */ +#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) /*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800U) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) -#define CRS_BASE (APB1PERIPH_BASE + 0x6000U) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) -#define DAC1_BASE (APB1PERIPH_BASE + 0x7400U) -#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U) -#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U) -#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U) -#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U) -#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U) -#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U) +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x6000UL) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) +#define DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) +#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) /*!< APB2 peripherals */ -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U) -#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U) -#define COMP1_BASE (APB2PERIPH_BASE + 0x0200U) -#define COMP2_BASE (APB2PERIPH_BASE + 0x0204U) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400U) -#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U) -#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800U) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000U) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400U) -#define SAI1_BASE (APB2PERIPH_BASE + 0x5400U) -#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) -#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL) +#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) /*!< AHB1 peripherals */ #define DMA1_BASE (AHB1PERIPH_BASE) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U) -#define RCC_BASE (AHB1PERIPH_BASE + 0x1000U) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) -#define TSC_BASE (AHB1PERIPH_BASE + 0x4000U) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define TSC_BASE (AHB1PERIPH_BASE + 0x4000UL) -#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U) -#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) -#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U) -#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU) -#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U) -#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U) -#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U) -#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU) -#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U) -#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U) +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) /*!< AHB2 peripherals */ -#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U) -#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U) -#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U) -#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U) -#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U) -#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U) +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL) -#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U) -#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U) +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) +#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) -#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U) +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) /* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t)0xE0042000U) +#define DBGMCU_BASE (0xE0042000UL) -#define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */ -#define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */ -#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ /** * @} */ @@ -1176,72 +1176,72 @@ typedef struct /******************** Bit definition for ADC_ISR register *******************/ #define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ #define ADC_ISR_EOSMP_Pos (1U) -#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ #define ADC_ISR_EOC_Pos (2U) -#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ #define ADC_ISR_EOS_Pos (3U) -#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ #define ADC_ISR_OVR_Pos (4U) -#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ #define ADC_ISR_JEOC_Pos (5U) -#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ #define ADC_ISR_JEOS_Pos (6U) -#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ #define ADC_ISR_AWD1_Pos (7U) -#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ #define ADC_ISR_AWD2_Pos (8U) -#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ #define ADC_ISR_AWD3_Pos (9U) -#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ #define ADC_ISR_JQOVF_Pos (10U) -#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ /******************** Bit definition for ADC_IER register *******************/ #define ADC_IER_ADRDYIE_Pos (0U) -#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ #define ADC_IER_EOSMPIE_Pos (1U) -#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ #define ADC_IER_EOCIE_Pos (2U) -#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ #define ADC_IER_EOSIE_Pos (3U) -#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ #define ADC_IER_OVRIE_Pos (4U) -#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ #define ADC_IER_JEOCIE_Pos (5U) -#define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ #define ADC_IER_JEOSIE_Pos (6U) -#define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ #define ADC_IER_AWD1IE_Pos (7U) -#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ #define ADC_IER_AWD2IE_Pos (8U) -#define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ #define ADC_IER_AWD3IE_Pos (9U) -#define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ #define ADC_IER_JQOVFIE_Pos (10U) -#define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ /* Legacy defines */ @@ -1259,926 +1259,926 @@ typedef struct /******************** Bit definition for ADC_CR register ********************/ #define ADC_CR_ADEN_Pos (0U) -#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ #define ADC_CR_ADDIS_Pos (1U) -#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ #define ADC_CR_ADSTART_Pos (2U) -#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ #define ADC_CR_JADSTART_Pos (3U) -#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ #define ADC_CR_ADSTP_Pos (4U) -#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ #define ADC_CR_JADSTP_Pos (5U) -#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ #define ADC_CR_ADVREGEN_Pos (28U) -#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ #define ADC_CR_DEEPPWD_Pos (29U) -#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ #define ADC_CR_ADCALDIF_Pos (30U) -#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ #define ADC_CR_ADCAL_Pos (31U) -#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR register ******************/ #define ADC_CFGR_DMAEN_Pos (0U) -#define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ #define ADC_CFGR_DMACFG_Pos (1U) -#define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ #define ADC_CFGR_RES_Pos (3U) -#define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ -#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ -#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ #define ADC_CFGR_ALIGN_Pos (5U) -#define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ #define ADC_CFGR_EXTSEL_Pos (6U) -#define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ +#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ -#define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ -#define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ -#define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ #define ADC_CFGR_EXTEN_Pos (10U) -#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ -#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ -#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ #define ADC_CFGR_OVRMOD_Pos (12U) -#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ #define ADC_CFGR_CONT_Pos (13U) -#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ #define ADC_CFGR_AUTDLY_Pos (14U) -#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_DISCEN_Pos (16U) -#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ #define ADC_CFGR_DISCNUM_Pos (17U) -#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ -#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ -#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ -#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ #define ADC_CFGR_JDISCEN_Pos (20U) -#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ #define ADC_CFGR_JQM_Pos (21U) -#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ #define ADC_CFGR_AWD1SGL_Pos (22U) -#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ #define ADC_CFGR_AWD1EN_Pos (23U) -#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ #define ADC_CFGR_JAWD1EN_Pos (24U) -#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ #define ADC_CFGR_JAUTO_Pos (25U) -#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ #define ADC_CFGR_AWD1CH_Pos (26U) -#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ -#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ -#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ -#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ -#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ -#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ #define ADC_CFGR_JQDIS_Pos (31U) -#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ /******************** Bit definition for ADC_CFGR2 register *****************/ #define ADC_CFGR2_ROVSE_Pos (0U) -#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ #define ADC_CFGR2_JOVSE_Pos (1U) -#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ #define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ -#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ #define ADC_CFGR2_OVSS_Pos (5U) -#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ -#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ -#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ -#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ -#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ #define ADC_CFGR2_TROVS_Pos (9U) -#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ #define ADC_CFGR2_ROVSM_Pos (10U) -#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ /******************** Bit definition for ADC_SMPR1 register *****************/ #define ADC_SMPR1_SMP0_Pos (0U) -#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ -#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ -#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ -#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ #define ADC_SMPR1_SMP1_Pos (3U) -#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ -#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ -#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ -#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ #define ADC_SMPR1_SMP2_Pos (6U) -#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ -#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ -#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ -#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ #define ADC_SMPR1_SMP3_Pos (9U) -#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ -#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ -#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ -#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ #define ADC_SMPR1_SMP4_Pos (12U) -#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ -#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ -#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ -#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ #define ADC_SMPR1_SMP5_Pos (15U) -#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ -#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ -#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ -#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ #define ADC_SMPR1_SMP6_Pos (18U) -#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ -#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ -#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ -#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ #define ADC_SMPR1_SMP7_Pos (21U) -#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ -#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ -#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ -#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ #define ADC_SMPR1_SMP8_Pos (24U) -#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ -#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ -#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ -#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ #define ADC_SMPR1_SMP9_Pos (27U) -#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ -#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ -#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ -#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_SMPR2 register *****************/ #define ADC_SMPR2_SMP10_Pos (0U) -#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ -#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ -#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ -#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ #define ADC_SMPR2_SMP11_Pos (3U) -#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ -#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ -#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ -#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ #define ADC_SMPR2_SMP12_Pos (6U) -#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ -#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ -#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ -#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ #define ADC_SMPR2_SMP13_Pos (9U) -#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ -#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ -#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ -#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ #define ADC_SMPR2_SMP14_Pos (12U) -#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ -#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ -#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ -#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ #define ADC_SMPR2_SMP15_Pos (15U) -#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ -#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ -#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ -#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ #define ADC_SMPR2_SMP16_Pos (18U) -#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ -#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ -#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ -#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ #define ADC_SMPR2_SMP17_Pos (21U) -#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ -#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ -#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ -#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ #define ADC_SMPR2_SMP18_Pos (24U) -#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ -#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ -#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ -#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ /******************** Bit definition for ADC_TR1 register *******************/ #define ADC_TR1_LT1_Pos (0U) -#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ -#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ #define ADC_TR1_HT1_Pos (16U) -#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ -#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ -#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ -#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ -#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ -#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ -#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ -#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ -#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ -#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ -#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ -#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ -#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_TR2 register *******************/ #define ADC_TR2_LT2_Pos (0U) -#define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ -#define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ -#define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ -#define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ -#define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ -#define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ -#define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ -#define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ -#define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ +#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ #define ADC_TR2_HT2_Pos (16U) -#define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ -#define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ -#define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ -#define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ -#define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ -#define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ -#define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ -#define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ -#define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ +#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_TR3 register *******************/ #define ADC_TR3_LT3_Pos (0U) -#define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ -#define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ -#define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ -#define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ -#define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ -#define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ -#define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ -#define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ -#define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ +#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ #define ADC_TR3_HT3_Pos (16U) -#define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ -#define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ -#define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ -#define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ -#define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ -#define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ -#define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ -#define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ -#define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ +#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_SQR1 register ******************/ #define ADC_SQR1_L_Pos (0U) -#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ -#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */ -#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */ -#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */ -#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ #define ADC_SQR1_SQ1_Pos (6U) -#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ -#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ -#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ -#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ -#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ -#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ #define ADC_SQR1_SQ2_Pos (12U) -#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ -#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ -#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ -#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ -#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ -#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ #define ADC_SQR1_SQ3_Pos (18U) -#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ -#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ -#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ -#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ -#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ -#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ #define ADC_SQR1_SQ4_Pos (24U) -#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ -#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ -#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ -#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ -#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ -#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ******************/ #define ADC_SQR2_SQ5_Pos (0U) -#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ -#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ -#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ -#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ -#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ -#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ #define ADC_SQR2_SQ6_Pos (6U) -#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ -#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ -#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ -#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ -#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ -#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ #define ADC_SQR2_SQ7_Pos (12U) -#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ -#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ -#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ -#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ -#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ -#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ #define ADC_SQR2_SQ8_Pos (18U) -#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ -#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ -#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ -#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ -#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ -#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ #define ADC_SQR2_SQ9_Pos (24U) -#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ -#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ -#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ -#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ -#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ -#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ******************/ #define ADC_SQR3_SQ10_Pos (0U) -#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ -#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ -#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ -#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ -#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ -#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ #define ADC_SQR3_SQ11_Pos (6U) -#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ -#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ -#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ -#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ -#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ -#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ #define ADC_SQR3_SQ12_Pos (12U) -#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ -#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ -#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ -#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ -#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ -#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ #define ADC_SQR3_SQ13_Pos (18U) -#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ -#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ -#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ -#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ -#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ -#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ #define ADC_SQR3_SQ14_Pos (24U) -#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ -#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ -#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ -#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ -#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ -#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ******************/ #define ADC_SQR4_SQ15_Pos (0U) -#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ -#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ -#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ -#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ -#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ -#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ #define ADC_SQR4_SQ16_Pos (6U) -#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ -#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ -#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ -#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ -#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ -#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ -#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ -#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ -#define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ -#define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ -#define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ -#define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ -#define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ -#define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ -#define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ -#define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ -#define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ -#define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ -#define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ -#define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ -#define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ -#define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JSQR register ******************/ #define ADC_JSQR_JL_Pos (0U) -#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ -#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ -#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ #define ADC_JSQR_JEXTSEL_Pos (2U) -#define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ +#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ -#define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ -#define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ -#define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ -#define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JEXTEN_Pos (6U) -#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ -#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ -#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JSQ1_Pos (8U) -#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ -#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ -#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ -#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ -#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ -#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ2_Pos (14U) -#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ -#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ -#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ -#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ -#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ -#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ3_Pos (20U) -#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ -#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ -#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ -#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ -#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ -#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ #define ADC_JSQR_JSQ4_Pos (26U) -#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ -#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ -#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ -#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ -#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ -#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_OFR1 register ******************/ #define ADC_OFR1_OFFSET1_Pos (0U) -#define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ -#define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ -#define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ -#define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ -#define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ -#define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ -#define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ -#define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ -#define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ -#define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ -#define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ -#define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ -#define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ #define ADC_OFR1_OFFSET1_CH_Pos (26U) -#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ -#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR1_OFFSET1_EN_Pos (31U) -#define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ /******************** Bit definition for ADC_OFR2 register ******************/ #define ADC_OFR2_OFFSET2_Pos (0U) -#define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ -#define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ -#define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ -#define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ -#define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ -#define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ -#define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ -#define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ -#define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ -#define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ -#define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ -#define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ -#define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ #define ADC_OFR2_OFFSET2_CH_Pos (26U) -#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ -#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR2_OFFSET2_EN_Pos (31U) -#define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ /******************** Bit definition for ADC_OFR3 register ******************/ #define ADC_OFR3_OFFSET3_Pos (0U) -#define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ -#define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ -#define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ -#define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ -#define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ -#define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ -#define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ -#define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ -#define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ -#define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ -#define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ -#define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ -#define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ #define ADC_OFR3_OFFSET3_CH_Pos (26U) -#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ -#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR3_OFFSET3_EN_Pos (31U) -#define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ /******************** Bit definition for ADC_OFR4 register ******************/ #define ADC_OFR4_OFFSET4_Pos (0U) -#define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ -#define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ -#define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ -#define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ -#define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ -#define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ -#define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ -#define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ -#define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ -#define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ -#define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ -#define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ -#define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ #define ADC_OFR4_OFFSET4_CH_Pos (26U) -#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ -#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR4_OFFSET4_EN_Pos (31U) -#define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ /******************** Bit definition for ADC_JDR1 register ******************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ -#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR2 register ******************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ -#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR3 register ******************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ -#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR4 register ******************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ -#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_AWD2CR register ****************/ #define ADC_AWD2CR_AWD2CH_Pos (0U) -#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ -#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) -#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ -#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_DIFSEL register ****************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) -#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ -#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ -#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ -#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ -#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ -#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ -#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ -#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ -#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ -#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ -#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ -#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ -#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ -#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ -#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ -#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ -#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ -#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ -#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ -#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_CALFACT register ***************/ #define ADC_CALFACT_CALFACT_S_Pos (0U) -#define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ -#define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ -#define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ -#define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ -#define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ -#define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ -#define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ -#define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ #define ADC_CALFACT_CALFACT_D_Pos (16U) -#define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ -#define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ -#define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ -#define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ -#define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ -#define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ -#define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ -#define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CCR register *******************/ #define ADC_CCR_CKMODE_Pos (16U) -#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ -#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ -#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ #define ADC_CCR_PRESC_Pos (18U) -#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ -#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ -#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ -#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ -#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ #define ADC_CCR_VREFEN_Pos (22U) -#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ #define ADC_CCR_TSEN_Pos (23U) -#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) -#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ /******************************************************************************/ @@ -2189,3475 +2189,3475 @@ typedef struct /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_HFSEL_Pos (15U) -#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ #define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_HFSEL_Pos (15U) -#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ #define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_HFSEL_Pos (15U) -#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ #define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_HFSEL_Pos (15U) -#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ #define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_HFSEL_Pos (15U) -#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ #define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_HFSEL_Pos (15U) -#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ #define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!

Update History

-

V1.4.2 / 22-December-2017

Main Changes

  • SPI_TypeDef cleanup of Reserved fields.

V1.4.1 / 13-October-2017

Main Changes

  • stm32l4r5xx.h, stm32l4r7xx.h, stm32l4r9xx.h, stm32l4s5xx.h, stm32l4s7xx.h and stm32l4s9xx.h devices description files
    • Fix SDMMC_STA_DPSMACT and SDMMC_STA_CPSMACT definitions
  • stm32l4r5xx.h and stm32l4s5xx.h devices description files
    • Remove LTDC peripheral definitions as LTDC not available on STM32L4R5xx/STM32L4S5xx devices

V1.4.0 / 25-August-2017

Main Changes

  • Add the support of STM32L4R5xx/STM32L4R7xx/STM32L4R9xx/STM32L4S5xx/STM32L4S7xx/STM32L4S9xx devices
    • Add stm32l4r5xx.h, stm32l4r7xx.h, stm32l4r9xx.h, stm32l4s5xx.h, stm32l4s7xx.h and stm32l4s9xx.h device description files
    • Add startup files startup_stm32l4r5xx.s, startup_stm32l4r7xx.s,  startup_stm32l4r9xx.s,  startup_stm32l4s5xx.s,  startup_stm32l4s7xx.s and startup_stm32l4s9xx.s for EWARM, MDK-ARM and SW4STM32 toolchains
    • Add EWARM associated linker files for execution from internal RAM or internal FLASH 
  • stm32l4xx.h
    • Add the following device defines:
      • "#define STM32L4R5xx" for all STM32L4R5xx devices
      • "#define STM32L4R7xx" for all STM32L4R7xx devices
      • "#define STM32L4R9xx" for all STM32L4R9xx devices
      • "#define STM32L4S5xx" for all STM32L4S5xx devices
      • "#define STM32L4S7xx" for all STM32L4S7xx devices
      • "#define STM32L4S9xx" for all STM32L4S9xx devices
  • all adequate stm32l4XXxx.h device description files
    • PWR: Rename PWR_CR3_EIWF to PWR_CR3_EIWUL
    • TIM: Add missing TIM8 check in debug macro IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE() devices
    • USB: Fix USB_EP0R...USB_EP7R definitions
  • system_stm32l4xx.c
    • Fix MISRA C 2004 rule 10.6 : a 'U' suffix shall be applied to all constants of 'unsigned' type

V1.3.2 +

V1.4.3 / 30-April-2018

Main Changes

  • all stm32l4XXxx.h device description files
    • Fix DFSDM_FLTICR_CLRSCDF definition
    • Cleanup USB Host & Device bit definitions
    • [MISRAC2012-Rule-10.6] Use 'UL' postfix for _Msk definitions and memory/peripheral base addresses
  • stm32l4r5xx.h, stm32l4r7xx.h, stm32l4r9xx.h, stm32l4s5xx.h, stm32l4s7xx.h and stm32l4s9xx.h devices description files
    • Fix SDMMC_STA_DPSMACT and SDMMC_STA_CPSMACT definitions (V1.4.1 update was incorrect)
  • all stm32l4XXxx.h device description files except stm32l4r5xx.h, stm32l4r7xx.h, stm32l4r9xx.h, stm32l4s5xx.h, stm32l4s7xx.h and stm32l4s9xx.h
    • Add missing USART_CR3_UCESM bit definition

V1.4.2 / 22-December-2017

Main Changes

  • SPI_TypeDef cleanup of Reserved fields.

V1.4.1 / 13-October-2017

Main Changes

  • stm32l4r5xx.h, stm32l4r7xx.h, stm32l4r9xx.h, stm32l4s5xx.h, stm32l4s7xx.h and stm32l4s9xx.h devices description files
    • Fix SDMMC_STA_DPSMACT and SDMMC_STA_CPSMACT definitions
  • stm32l4r5xx.h and stm32l4s5xx.h devices description files
    • Remove LTDC peripheral definitions as LTDC not available on STM32L4R5xx/STM32L4S5xx devices

V1.4.0 / 25-August-2017

Main Changes

  • Add the support of STM32L4R5xx/STM32L4R7xx/STM32L4R9xx/STM32L4S5xx/STM32L4S7xx/STM32L4S9xx devices
    • Add stm32l4r5xx.h, stm32l4r7xx.h, stm32l4r9xx.h, stm32l4s5xx.h, stm32l4s7xx.h and stm32l4s9xx.h device description files
    • Add startup files startup_stm32l4r5xx.s, startup_stm32l4r7xx.s,  startup_stm32l4r9xx.s,  startup_stm32l4s5xx.s,  startup_stm32l4s7xx.s and startup_stm32l4s9xx.s for EWARM, MDK-ARM and SW4STM32 toolchains
    • Add EWARM associated linker files for execution from internal RAM or internal FLASH 
  • stm32l4xx.h
    • Add the following device defines:
      • "#define STM32L4R5xx" for all STM32L4R5xx devices
      • "#define STM32L4R7xx" for all STM32L4R7xx devices
      • "#define STM32L4R9xx" for all STM32L4R9xx devices
      • "#define STM32L4S5xx" for all STM32L4S5xx devices
      • "#define STM32L4S7xx" for all STM32L4S7xx devices
      • "#define STM32L4S9xx" for all STM32L4S9xx devices
  • all adequate stm32l4XXxx.h device description files
    • PWR: Rename PWR_CR3_EIWF to PWR_CR3_EIWUL
    • TIM: Add missing TIM8 check in debug macro IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE() devices
    • USB: Fix USB_EP0R...USB_EP7R definitions
  • system_stm32l4xx.c
    • Fix MISRA C 2004 rule 10.6 : a 'U' suffix shall be applied to all constants of 'unsigned' type

V1.3.2 / 16-June-2017

Main Changes

diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 96d6b9e57f..cb9f4972f7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -8,7 +8,7 @@ * STM32F7: 1.2.2 * STM32L0: 1.7.2 * STM32L1: 2.2.3 - * STM32L4: 1.4.2 + * STM32L4: 1.4.3 Release notes of each STM32YYxx CMSIS available here: diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h index ca95785d3e..9762483f59 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h @@ -70,6 +70,27 @@ /** @defgroup HAL_Exported_Constants HAL Exported Constants * @{ */ + +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; +/** + * @} + */ + +/** + * @} + */ +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ /** @defgroup SYSCFG_BitAddress_AliasRegion SYSCFG registers bit address in the alias region * @brief SYSCFG registers bit address in the alias region * @{ @@ -847,6 +868,16 @@ */ #endif /* SYSCFG_RCR_PAGE0 */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) /** * @} */ @@ -875,10 +906,13 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); */ /* Peripheral Control functions ************************************************/ void HAL_IncTick(void); -void HAL_Delay(__IO uint32_t Delay); +void HAL_Delay(uint32_t Delay); void HAL_SuspendTick(void); void HAL_ResumeTick(void); uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); uint32_t HAL_GetHalVersion(void); uint32_t HAL_GetREVID(void); uint32_t HAL_GetDEVID(void); diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h index 3a13224bf8..69568d168f 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h @@ -72,10 +72,13 @@ typedef enum } HAL_LockTypeDef; /* Exported macro ------------------------------------------------------------*/ + +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ + #define HAL_MAX_DELAY 0xFFFFFFFFU -#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET) -#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == BIT) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \ do{ \ @@ -83,8 +86,6 @@ typedef enum (__DMA_HANDLE_).Parent = (__HANDLE__); \ } while(0U) -#define UNUSED(x) ((void)(x)) - /** @brief Reset the Handle's State field. * @param __HANDLE__ specifies the Peripheral Handle. * @note This macro can be used for the following purpose: @@ -123,7 +124,7 @@ typedef enum }while (0U) #endif /* USE_RTOS */ -#if defined ( __GNUC__ ) +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __weak #define __weak __attribute__((weak)) #endif /* __weak */ @@ -134,7 +135,7 @@ typedef enum /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ -#if defined (__GNUC__) /* GNU Compiler */ +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4))) #endif /* __ALIGN_END */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h index 4e34973969..dcbbe475b2 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h @@ -248,6 +248,7 @@ typedef struct __I2C_HandleTypeDef #define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) #define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) #define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) /** * @} */ @@ -335,9 +336,9 @@ typedef struct __I2C_HandleTypeDef * @{ */ #define I2C_NO_STARTSTOP (0x00000000U) -#define I2C_GENERATE_STOP I2C_CR2_STOP -#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) -#define I2C_GENERATE_START_WRITE I2C_CR2_START +#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /** * @} */ @@ -659,7 +660,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ ((REQUEST) == I2C_NEXT_FRAME) || \ ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ - ((REQUEST) == I2C_LAST_FRAME)) + ((REQUEST) == I2C_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME_NO_STOP)) #define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd.h index c1df95988e..e680185307 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd.h @@ -402,10 +402,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); */ /* SetENDPOINT */ -#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))= (uint16_t)(wRegValue)) +#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*((__IO uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))= (uint16_t)(wRegValue)) /* GetENDPOINT */ -#define PCD_GET_ENDPOINT(USBx, bEpNum) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))) +#define PCD_GET_ENDPOINT(USBx, bEpNum) (*((__IO uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))) diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smbus.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smbus.h index c980e4297d..6d64cfff61 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smbus.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smbus.h @@ -279,9 +279,9 @@ typedef struct */ #define SMBUS_NO_STARTSTOP (0x00000000U) -#define SMBUS_GENERATE_STOP I2C_CR2_STOP -#define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) -#define SMBUS_GENERATE_START_WRITE I2C_CR2_START +#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /** * @} */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_adc.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_adc.h index a087dd1e77..e584b01edc 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_adc.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_adc.h @@ -421,7 +421,7 @@ extern "C" { * @retval Pointer to register address */ #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ - ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) + ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) /** * @} @@ -2967,7 +2967,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); MODIFY_REG(*preg, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, @@ -3040,7 +3040,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); } @@ -3066,7 +3066,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Off */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1); } @@ -3099,7 +3099,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offse */ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState) { - register uint32_t *preg = (uint32_t *)((uint32_t) + register __IO uint32_t *preg = (__IO uint32_t *)((uint32_t) ((uint32_t)(&ADCx->OFR1) + (Offsety*4U))); MODIFY_REG(*preg, @@ -3126,7 +3126,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN); } @@ -3629,7 +3629,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); MODIFY_REG(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), @@ -3730,7 +3730,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); return (uint32_t) (READ_BIT(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) @@ -4833,7 +4833,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); MODIFY_REG(*preg, ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), @@ -4917,7 +4917,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C */ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); return (uint32_t)(READ_BIT(*preg, ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) @@ -5189,7 +5189,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t /* in register and register position depending on parameter "AWDy". */ /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ /* containing other bits reserved for other purpose. */ - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK) + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); MODIFY_REG(*preg, @@ -5321,7 +5321,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK) + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); /* Variable "AWDy" used to retrieve appropriate bitfield corresponding to */ @@ -5423,7 +5423,7 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t /* "AWDy". */ /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ /* containing other bits reserved for other purpose. */ - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); MODIFY_REG(*preg, ADC_TR1_HT1 | ADC_TR1_LT1, @@ -5487,7 +5487,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW /* "AWDThresholdsHighLow" and "AWDy". */ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ /* containing other bits reserved for other purpose. */ - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); MODIFY_REG(*preg, AWDThresholdsHighLow, @@ -5524,7 +5524,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); return (uint32_t)(READ_BIT(*preg, (AWDThresholdsHighLow | ADC_TR1_LT1)) @@ -6218,7 +6218,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6245,7 +6245,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6272,7 +6272,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6299,7 +6299,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6326,7 +6326,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32 */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -9294,7 +9294,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); MODIFY_REG(*preg, ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK), @@ -9384,7 +9384,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); return (uint32_t) (READ_BIT(*preg, ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) @@ -9850,7 +9850,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); MODIFY_REG(*preg, ADC_JOFR1_JOFFSET1, @@ -9877,7 +9877,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); return (uint32_t)(READ_BIT(*preg, ADC_JOFR1_JOFFSET1) @@ -9970,7 +9970,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); MODIFY_REG(*preg, ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), @@ -10039,7 +10039,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C */ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); return (uint32_t)(READ_BIT(*preg, ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) @@ -10263,7 +10263,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); MODIFY_REG(*preg, ADC_HTR_HT, @@ -10286,7 +10286,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT)); } @@ -10509,7 +10509,7 @@ __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -10536,7 +10536,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h index 4422b6300b..e121df5ac5 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h @@ -141,7 +141,7 @@ extern "C" { * @retval Pointer to register address */ #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ - ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) + ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) /** * @} @@ -1210,7 +1210,7 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Cha */ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK)); MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, @@ -1235,7 +1235,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_ */ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK)); MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, @@ -1260,7 +1260,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t */ __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK)); MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, @@ -1345,7 +1345,7 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint */ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK)); + register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK)); return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); } diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_hrtim.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_hrtim.h index 65fe425823..1c12132198 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_hrtim.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_hrtim.h @@ -2021,7 +2021,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(HRTIM_TypeDef *HRTIMx, uint32 __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src) { register uint32_t shift = 3 * ADCTrig; - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + REG_OFFSET_TAB_ADCxR[ADCTrig])); MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift)); WRITE_REG(*pReg, Src); @@ -2291,7 +2291,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src) { - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + REG_OFFSET_TAB_ADCxR[ADCTrig])); WRITE_REG(*pReg, Src); } @@ -2503,7 +2503,7 @@ __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCT */ __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) { - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + REG_OFFSET_TAB_ADCxR[ADCTrig])); return (*pReg); } @@ -2644,7 +2644,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(HRTIM_TypeDef *HRTIMx, ui __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_MCR_CK_PSC, Prescaler); } @@ -2673,7 +2673,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t T __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCR_CK_PSC)); } @@ -2700,7 +2700,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32 __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, (HRTIM_TIMCR_RETRIG | HRTIM_MCR_CONT), Mode); } @@ -2726,7 +2726,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, (HRTIM_MCR_RETRIG | HRTIM_MCR_CONT))); } @@ -2750,7 +2750,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef *HRTIMx, uint __STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MCR_HALF); } @@ -2771,7 +2771,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MCR_HALF); } @@ -2792,7 +2792,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCR_HALF) == HRTIM_MCR_HALF); } @@ -2813,7 +2813,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef *HRTIMx, u __STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MCR_SYNCSTRTM); } @@ -2834,7 +2834,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint3 __STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MCR_SYNCSTRTM); } @@ -2855,7 +2855,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCR_SYNCSTRTM) == HRTIM_MCR_SYNCSTRTM); } @@ -2876,7 +2876,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx __STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MCR_SYNCRSTM); } @@ -2897,7 +2897,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint3 __STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MCR_SYNCRSTM); } @@ -2918,7 +2918,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCR_SYNCRSTM) == HRTIM_MCR_SYNCRSTM); } @@ -2944,7 +2944,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_MCR_DACSYNC, DACTrig); } @@ -2969,7 +2969,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Tim __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCR_DACSYNC)); } @@ -2993,7 +2993,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MCR_PREEN); } @@ -3014,7 +3014,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MCR_PREEN); } @@ -3035,7 +3035,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCR_PREEN) == HRTIM_MCR_PREEN); } @@ -3078,7 +3078,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx, ui __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]); } @@ -3119,7 +3119,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer]) >> REG_SHIFT_TAB_UPDATETRIG[iTimer]); } @@ -3157,7 +3157,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint3 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer])); } @@ -3194,7 +3194,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >> REG_SHIFT_TAB_UPDATEGATING[iTimer]); } @@ -3213,7 +3213,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef *HRTIMx, uin __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL); } @@ -3233,7 +3233,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL); } @@ -3253,7 +3253,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uin __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == HRTIM_TIMCR_PSHPLL); } @@ -3284,7 +3284,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t uint32_t Mode) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + REG_OFFSET_TAB_TIMER[iTimer])); register uint32_t shift = POSITION_VAL(CompareUnit) - POSITION_VAL(LL_HRTIM_COMPAREUNIT_2); MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift)); @@ -3313,7 +3313,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + REG_OFFSET_TAB_TIMER[iTimer])); register uint32_t shift = POSITION_VAL(CompareUnit) - POSITION_VAL(LL_HRTIM_COMPAREUNIT_2); return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >> shift); @@ -3343,7 +3343,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter); } @@ -3365,7 +3365,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Tim __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR)); } @@ -3388,7 +3388,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period); } @@ -3410,7 +3410,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Time __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MPER_MPER)); } @@ -3433,7 +3433,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition); } @@ -3455,7 +3455,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MREP_MREP)); } @@ -3480,7 +3480,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint3 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue); } @@ -3504,7 +3504,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Ti __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R)); } @@ -3529,7 +3529,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue); } @@ -3553,7 +3553,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Ti __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R)); } @@ -3578,7 +3578,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue); } @@ -3602,7 +3602,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Ti __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R)); } @@ -3627,7 +3627,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue); } @@ -3651,7 +3651,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Ti __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R)); } @@ -3738,7 +3738,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_ __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + REG_OFFSET_TAB_TIMER[iTimer])); WRITE_REG(*pReg, ResetTrig); } @@ -3818,7 +3818,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t T __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -3838,7 +3838,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -3858,7 +3858,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -3946,7 +3946,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t uint32_t CaptureTrig) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xCR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xCR) + REG_OFFSET_TAB_TIMER[iTimer] + CaptureUnit * 4)); WRITE_REG(*pReg, CaptureTrig); } @@ -4032,7 +4032,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xCR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xCR) + REG_OFFSET_TAB_TIMER[iTimer] + CaptureUnit * 4)); return (READ_REG(*pReg)); } @@ -4052,7 +4052,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_DTEN); } @@ -4072,7 +4072,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN); } @@ -4092,7 +4092,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_OUTR_DTEN) == HRTIM_OUTR_DTEN); } @@ -4136,7 +4136,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, u __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode); } @@ -4177,7 +4177,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT)); } @@ -4198,7 +4198,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint3 __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); } @@ -4219,7 +4219,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); } @@ -4239,7 +4239,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == HRTIM_OUTR_DLYPRTEN); } @@ -4269,7 +4269,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uin __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, Faults); } @@ -4299,7 +4299,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Ti __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, Faults); } @@ -4329,7 +4329,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t T __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, Fault) == (Fault)); } @@ -4350,7 +4350,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_FLTR_FLTLCK); } @@ -4492,7 +4492,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef *HRTIMx, __STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + 4 * iTimer)); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + 4 * iTimer)); WRITE_REG(*pReg, Registers); } @@ -4514,7 +4514,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT)); } @@ -4536,7 +4536,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HR __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT)); } @@ -4595,7 +4595,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4652,7 +4652,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef *HRTIMx, uint { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -4698,7 +4698,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uin { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4741,7 +4741,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -4775,7 +4775,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration); } @@ -4804,7 +4804,7 @@ __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, u __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler); } @@ -4832,7 +4832,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Ti __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC)); } @@ -4853,7 +4853,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_ __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue); } @@ -4873,7 +4873,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_DTR)); } @@ -4896,7 +4896,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef *HRTIMx, uint3 __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign); } @@ -4918,7 +4918,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t T __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_SDTR)); } @@ -4939,7 +4939,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef *HRTIMx, uint32 __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos); } @@ -4959,7 +4959,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos); } @@ -4982,7 +4982,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef *HRTIMx, uint __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign); } @@ -5004,7 +5004,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_SDTF)); } @@ -5024,7 +5024,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint3 __STATIC_INLINE void LL_HRTIM_DT_LockRising(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTRLK); } @@ -5044,7 +5044,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockRising(HRTIM_TypeDef *HRTIMx, uint32_t Time __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTRSLK); } @@ -5064,7 +5064,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTFLK); } @@ -5084,7 +5084,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Tim __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTFSLK); } @@ -5120,7 +5120,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration); } @@ -5160,7 +5160,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler); } @@ -5196,7 +5196,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t T __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ)); } @@ -5228,7 +5228,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32 __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle); } @@ -5256,7 +5256,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t T __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY)); } @@ -5295,7 +5295,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32 __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth); } @@ -5331,7 +5331,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_STRPW)); } @@ -5460,7 +5460,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint3 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + REG_OFFSET_TAB_SETxR[iOutput])); WRITE_REG(*pReg, SetSrc); } @@ -5580,7 +5580,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + REG_OFFSET_TAB_SETxR[iOutput])); return (uint32_t) READ_REG(*pReg); } @@ -5701,7 +5701,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uin __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + REG_OFFSET_TAB_SETxR[iOutput])); WRITE_REG(*pReg, ResetSrc); } @@ -5821,7 +5821,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint3 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + REG_OFFSET_TAB_SETxR[iOutput])); return (uint32_t) READ_REG(*pReg); } @@ -5864,7 +5864,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, u __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]), (Configuration << REG_SHIFT_TAB_OUTxR[iOutput])); @@ -5894,7 +5894,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -5922,7 +5922,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Ou __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -5952,7 +5952,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleMode << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -5980,7 +5980,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Ou __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (HRTIM_OUTR_IDLM1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6011,7 +6011,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6039,7 +6039,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t O __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6072,7 +6072,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32 __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6102,7 +6102,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6132,7 +6132,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef *HRTIMx, uint3 __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6160,7 +6160,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6190,7 +6190,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef *HRTIMx, uint __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6218,7 +6218,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6247,7 +6247,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef *HRTIMx, uint32_t Output) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + REG_OFFSET_TAB_OUTxR[iOutput])); return ((READ_BIT(*pReg, (HRTIM_TIMISR_O1STAT << REG_SHIFT_TAB_OxSTAT[iOutput])) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> HRTIM_TIMISR_O1STAT_Pos); @@ -6279,7 +6279,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef *HRTIMx, __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t OutputLevel) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel])); SET_BIT(*pReg, HRTIM_SET1R_SST); } @@ -6307,7 +6307,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Out __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + REG_OFFSET_TAB_OUTxR[iOutput])); return ((READ_BIT(*pReg, (HRTIM_TIMISR_O1CPY << REG_SHIFT_TAB_OxSTAT[iOutput])) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> HRTIM_TIMISR_O1CPY_Pos); @@ -6388,7 +6388,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t O __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration) { register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]), (Configuration << REG_SHIFT_TAB_EExSRC[iEvent])); @@ -6428,7 +6428,7 @@ __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, u __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src) { register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6466,7 +6466,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, u __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event) { register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6505,7 +6505,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Even __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity) { register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6541,7 +6541,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Eve __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event) { register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6581,7 +6581,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity) { register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6619,7 +6619,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event) { register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6652,7 +6652,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef *HRTIMx, uint3 __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode) { register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6683,7 +6683,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Eve __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event) { register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6836,7 +6836,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(HRTIM_TypeDef *HRTIMx) __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration) { register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLT_CONFIG_MASK << REG_SHIFT_TAB_FLTxE[iFault]), (Configuration << REG_SHIFT_TAB_FLTxE[iFault])); @@ -6865,7 +6865,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Src) { register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault]), (Src << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -6891,7 +6891,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -6919,7 +6919,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fau __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity) { register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault]), (Polarity << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -6945,7 +6945,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fa __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -6987,7 +6987,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_ __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter) { register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault]), (Filter << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7027,7 +7027,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Faul __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -7083,7 +7083,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(HRTIM_TypeDef *HRTIMx) __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7107,7 +7107,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault) __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7131,7 +7131,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7155,7 +7155,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); return ((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) == (HRTIM_IER_FLT1)); @@ -7839,7 +7839,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(HRTIM_TypeDef *HRTIMx) __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MUPD); } @@ -7861,7 +7861,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)); } @@ -7883,7 +7883,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uin __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MREP); @@ -7906,7 +7906,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)); } @@ -7928,7 +7928,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP1); } @@ -7950,7 +7950,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)); } @@ -7972,7 +7972,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint3 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP2); } @@ -7994,7 +7994,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)); } @@ -8016,7 +8016,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint3 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP3); } @@ -8038,7 +8038,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)); } @@ -8060,7 +8060,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint3 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP4); } @@ -8082,7 +8082,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)); } @@ -8102,7 +8102,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint3 __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_CPT1C); } @@ -8122,7 +8122,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)); } @@ -8142,7 +8142,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint3 __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_CPT2C); } @@ -8162,7 +8162,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)); } @@ -8182,7 +8182,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint3 __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_SET1C); } @@ -8202,7 +8202,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)); } @@ -8222,7 +8222,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef *HRTIMx, uint3 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RST1C); } @@ -8242,7 +8242,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)); } @@ -8262,7 +8262,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef *HRTIMx, uint3 __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_SET2C); } @@ -8282,7 +8282,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)); } @@ -8302,7 +8302,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef *HRTIMx, uint3 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RST2C); } @@ -8322,7 +8322,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)); } @@ -8342,7 +8342,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef *HRTIMx, uint3 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RSTC); } @@ -8362,7 +8362,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)); } @@ -8382,7 +8382,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef *HRTIMx, uint32 __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_DLYPRT1C); } @@ -8402,7 +8402,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)); } @@ -8729,7 +8729,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(HRTIM_TypeDef *HRTIMx) __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MUPDIE); } @@ -8751,7 +8751,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Ti __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE); } @@ -8773,7 +8773,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE)); } @@ -8795,7 +8795,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MREPIE); } @@ -8817,7 +8817,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE); } @@ -8839,7 +8839,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE)); } @@ -8861,7 +8861,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef *HRTIMx, uint32_ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE); } @@ -8883,7 +8883,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Time __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE); } @@ -8905,7 +8905,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE)); } @@ -8927,7 +8927,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE); } @@ -8949,7 +8949,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Time __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE); } @@ -8971,7 +8971,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE)); } @@ -8993,7 +8993,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE); } @@ -9015,7 +9015,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Time __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE); } @@ -9037,7 +9037,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE)); } @@ -9059,7 +9059,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE); } @@ -9081,7 +9081,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Time __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE); } @@ -9103,7 +9103,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE)); } @@ -9123,7 +9123,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32 __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); } @@ -9143,7 +9143,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Time __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); } @@ -9163,7 +9163,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE)); } @@ -9183,7 +9183,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32 __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); } @@ -9203,7 +9203,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Time __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); } @@ -9223,7 +9223,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE)); } @@ -9243,7 +9243,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32 __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE); } @@ -9263,7 +9263,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Time __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE); } @@ -9283,7 +9283,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE)); } @@ -9303,7 +9303,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef *HRTIMx, uint32 __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE); } @@ -9323,7 +9323,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Time __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE); } @@ -9343,7 +9343,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE)); } @@ -9363,7 +9363,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef *HRTIMx, uint32 __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE); } @@ -9383,7 +9383,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Time __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE); } @@ -9403,7 +9403,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE)); } @@ -9423,7 +9423,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef *HRTIMx, uint32 __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE); } @@ -9443,7 +9443,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Time __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE); } @@ -9463,7 +9463,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE)); } @@ -9483,7 +9483,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef *HRTIMx, uint32 __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE); } @@ -9503,7 +9503,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE); } @@ -9523,7 +9523,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE)); } @@ -9543,7 +9543,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef *HRTIMx, uint32_ __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); } @@ -9563,7 +9563,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Ti __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); } @@ -9583,7 +9583,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE)); } @@ -9646,7 +9646,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(HRTIM_TypeDef *HRTIMx) __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MUPDDE); } @@ -9668,7 +9668,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE); } @@ -9690,7 +9690,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE)); } @@ -9712,7 +9712,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MREPDE); } @@ -9734,7 +9734,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t T __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE); } @@ -9756,7 +9756,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE)); } @@ -9778,7 +9778,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef *HRTIMx, uin __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE); } @@ -9800,7 +9800,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE); } @@ -9822,7 +9822,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE)); } @@ -9844,7 +9844,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, ui __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE); } @@ -9866,7 +9866,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE); } @@ -9888,7 +9888,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE)); } @@ -9910,7 +9910,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, ui __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE); } @@ -9932,7 +9932,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE); } @@ -9954,7 +9954,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE)); } @@ -9976,7 +9976,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, ui __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE); } @@ -9998,7 +9998,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE); } @@ -10020,7 +10020,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE)); } @@ -10040,7 +10040,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, ui __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); } @@ -10060,7 +10060,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); } @@ -10080,7 +10080,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE)); } @@ -10100,7 +10100,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, ui __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); } @@ -10120,7 +10120,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); } @@ -10140,7 +10140,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE)); } @@ -10160,7 +10160,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, ui __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE); } @@ -10180,7 +10180,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE); } @@ -10200,7 +10200,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE)); } @@ -10220,7 +10220,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef *HRTIMx, ui __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE); } @@ -10240,7 +10240,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE); } @@ -10260,7 +10260,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE)); } @@ -10280,7 +10280,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef *HRTIMx, ui __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE); } @@ -10300,7 +10300,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE); } @@ -10320,7 +10320,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE)); } @@ -10340,7 +10340,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef *HRTIMx, ui __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE); } @@ -10360,7 +10360,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE); } @@ -10380,7 +10380,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE)); } @@ -10400,7 +10400,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef *HRTIMx, ui __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE); } @@ -10420,7 +10420,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t T __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE); } @@ -10440,7 +10440,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE)); } @@ -10460,7 +10460,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef *HRTIMx, uin __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); } @@ -10480,7 +10480,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); } @@ -10500,7 +10500,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE)); } diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_i2c.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_i2c.h index f2a8105531..92edb412cd 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_i2c.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_i2c.h @@ -281,14 +281,14 @@ typedef struct /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation * @{ */ -#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */ -#define LL_I2C_GENERATE_STOP I2C_CR2_STOP /*!< Generate Stop condition (Size should be set to 0). */ -#define LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */ -#define LL_I2C_GENERATE_START_WRITE I2C_CR2_START /*!< Generate Start for write request. */ -#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */ -#define LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 7Bit address. */ -#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */ -#define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 10Bit address.*/ +#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */ +#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */ +#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */ +#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Start for write request. */ +#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/ /** * @} */ @@ -2106,7 +2106,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request) { - MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request); } diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h index b3e7b66fd7..f3118539ec 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h @@ -146,7 +146,7 @@ typedef struct #endif /* LSE_VALUE */ #if !defined (LSI_VALUE) -#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#define LSI_VALUE 40000U /*!< Value of the LSI oscillator in Hz */ #endif /* LSI_VALUE */ /** * @} diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rtc.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rtc.h index a8d667b385..0d1393a175 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rtc.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rtc.h @@ -1216,10 +1216,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) */ __STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU)); - return (uint32_t)((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)); + return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos); } /** @@ -1254,10 +1251,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) */ __STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)); - return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)); + return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU))>> RTC_TR_MNU_Pos); } /** @@ -1292,10 +1286,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) */ __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)); - return (uint32_t)((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)); + return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos); } /** @@ -1488,10 +1479,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) */ __STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU)); - return (uint32_t)((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)); + return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos); } /** @@ -1584,10 +1572,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) */ __STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU)); - return (uint32_t)((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)); + return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU)))>> RTC_DR_MU_Pos); } /** @@ -1617,10 +1602,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) */ __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU)); - return (uint32_t)((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)); + return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos); } /** @@ -1817,10 +1799,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day) */ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU)); - return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_ALRMAR_DT_Pos) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos)); + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos); } /** @@ -1912,10 +1891,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) */ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU)); - return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_ALRMAR_HT_Pos) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_ALRMAR_HU_Pos)); + return (uint32_t)(( READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos); } /** @@ -1943,10 +1919,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) */ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)); - return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_ALRMAR_MNT_Pos) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_ALRMAR_MNU_Pos)); + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos); } /** @@ -1974,10 +1947,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) */ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); - return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_ALRMAR_ST_Pos) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_ALRMAR_SU_Pos)); + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos); } /** @@ -2195,10 +2165,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) */ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU)); - return (uint32_t)((((temp & RTC_ALRMBR_DT) >> RTC_ALRMBR_DT_Pos) << 4U) | ((temp & RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos)); + return (uint32_t)(( READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos); } /** @@ -2290,10 +2257,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) */ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU)); - return (uint32_t)((((temp & RTC_ALRMBR_HT) >> RTC_ALRMBR_HT_Pos) << 4U) | ((temp & RTC_ALRMBR_HU) >> RTC_ALRMBR_HU_Pos)); + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos); } /** @@ -2321,10 +2285,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) */ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)); - return (uint32_t)((((temp & RTC_ALRMBR_MNT) >> RTC_ALRMBR_MNT_Pos) << 4U) | ((temp & RTC_ALRMBR_MNU) >> RTC_ALRMBR_MNU_Pos)); +return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos); } /** @@ -2352,10 +2313,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) */ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU)); - return (uint32_t)((((temp & RTC_ALRMBR_ST) >> RTC_ALRMBR_ST_Pos) << 4U) | ((temp & RTC_ALRMBR_SU) >> RTC_ALRMBR_SU_Pos)); + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos); } /** diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_spi.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_spi.h index f92314826b..469deadd14 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_spi.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_spi.h @@ -1373,7 +1373,12 @@ __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) */ __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) { +#if defined (__GNUC__) + __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR); + *spidr = TxData; +#else *((__IO uint8_t *)&SPIx->DR) = TxData; +#endif } /** @@ -1385,7 +1390,12 @@ __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) */ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) { +#if defined (__GNUC__) + __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR); + *spidr = TxData; +#else *((__IO uint16_t *)&SPIx->DR) = TxData; +#endif } /** diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h index 31932538da..0652ca9867 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h @@ -1418,11 +1418,11 @@ __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) * @brief Indicates whether update event generation is enabled. * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent * @param TIMx Timer instance - * @retval State of bit (1 or 0). + * @retval Inverted state of bit (0 or 1). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS)); + return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET); } /** @@ -1984,7 +1984,7 @@ __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); @@ -2045,7 +2045,7 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); } @@ -2100,7 +2100,7 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); } @@ -2274,7 +2274,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Chan __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); } @@ -2310,7 +2310,7 @@ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); } @@ -2346,7 +2346,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; return (READ_BIT(*pReg, bitfield) == bitfield); } @@ -2382,7 +2382,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Cha __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); } @@ -2417,7 +2417,7 @@ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); } @@ -2452,7 +2452,7 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; return (READ_BIT(*pReg, bitfield) == bitfield); } @@ -2491,7 +2491,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); } @@ -2528,7 +2528,7 @@ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); } @@ -2567,7 +2567,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; return (READ_BIT(*pReg, bitfield) == bitfield); } @@ -2887,7 +2887,7 @@ __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t G __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), @@ -2915,7 +2915,7 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -2939,7 +2939,7 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -2965,7 +2965,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Ch __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -2990,7 +2990,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -3028,7 +3028,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Chan __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -3065,7 +3065,7 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h index 99fb02f232..5f46fcd6ec 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h @@ -250,6 +250,7 @@ __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ } diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32F3xx_HAL_Driver/Release_Notes.html index 496a79a1f9..7f23eded23 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32F3xx_HAL_Driver/Release_Notes.html @@ -676,10 +676,22 @@

Update History

-

V1.5.0 +

V1.5.1 +/ 11-May-2018

Main changes

  • Patch release to fix known defects and +enhancements implementation

HAL Drivers changes

  • HAL update
    • Update HAL driver to allow user to change systick period to 1ms, 10 ms or 100 ms :
      • Add the following API's :  
        • HAL_GetTickPrio(): Returns a tick priority.
        • HAL_SetTickFreq(): Sets new tick frequency.
        • HAL_GetTickFreq(): Returns tick frequency.
      • Add HAL_TickFreqTypeDef enumeration for the different Tick Frequencies: 10 Hz, 100 Hz and 1KHz (default).
    • Update UNUSED() macro implementation to avoid GCC warning
      • The warning is detected when the UNUSED() macro is called from C++ file
    • Update __weak and __packed defined values for ARM compiler
    • Update __ALIGN_BEGIN and __ALIGN_END defined values for ARM compiler
  • HAL I2C update
    • Update Interface APIs headers to remove confusing message about device address
    • Update I2C_WaitOnRXNEFlagUntilTimeout() to resolve a race condition between STOPF and RXNE Flags
    • Update I2C_TransferConfig() to fix wrong bit management
  • HAL SMBUS update
    • Update conditions on HAL SMBUS slave transfer APIs to avoid block on read or write operations
  • HAL FLASH update
    • HAL_FLASH_Unlock() update to return state error when the FLASH is already unlocked
  • HAL PCD update
    • Update +redefinition of registers with adjusted address by adding volatile +keyword to avoid unexpected change of Memory-mapped peripheral registers

LL Drivers changes

  • LL ADC
    • Update +redefinition of registers with adjusted address by adding volatile +keyword to avoid unexpected change of Memory-mapped peripheral registers
  • LL DAC
    • Update +redefinition of registers with adjusted address by adding volatile +keyword to avoid unexpected change of Memory-mapped peripheral registers
  • LL HRTIM
    • Update +redefinition of registers with adjusted address by adding volatile +keyword to avoid unexpected change of Memory-mapped peripheral registers
  • LL I2C 
    • Update LL_I2C_HandleTransfer() to fix wrong bit management
  • LL RCC
    • Fix wrong defined value of LSI
  • LL RTC
    • LL RTC macros optimization:
      • LL_RTC_TIME_GetHour()
      • LL_RTC_TIME_GetMinute()
      • LL_RTC_TIME_GetSecond()
      • LL_RTC_DATE_GetYear()
      • LL_RTC_DATE_GetMonth()
      • LL_RTC_DATE_GetDay()
      • LL_RTC_ALMA_GetDay()
      • LL_RTC_ALMA_GetHour()
      • LL_RTC_ALMA_GetMinute()
      • LL_RTC_ALMA_GetSecond()
      • LL_RTC_ALMB_GetDay()
      • LL_RTC_ALMB_GetHour()
      • LL_RTC_ALMB_GetMinute()
      • LL_RTC_ALMB_GetSecond()
  • LL SPI
    • Update LL_SPI_TransmitData8() and LL_SPI_TransmitData16() to fix compilation issues with GCC
  • LL TIM
    • Update +redefinition of registers with adjusted address by adding volatile +keyword to avoid unexpected change of Memory-mapped peripheral registers
    • Fix behavior of LL_TIM_IsEnabledUpdateEvent() 
  • LL UTILS
    • Update LL_InitTick() to set SysTick_CTRL_TICKINT bit in SysTick->CTRL 

V1.5.0 / 23-June-2017

Main changes

  • Maintenance release to fix known defects and enhancements implementation

Generic drivers changes

  • MISRA C 2004 rule 11.4 (A cast should not be performed between a pointer to object type and a different pointer to object type).
  • MISRA C 2004 rule 12.4 (The right-hand operand of a logical  or  I  I  operator shall not
    contain side effects).
  • MISRA C 2004 rule 17.4 (Array indexing shall be the only allowed form of pointer arithmetic).
  • Remove uselesss cast (uint32_t ) cast in case of 'U' suffix.
  • Fix Code Sonar warnings (useless assignment, cast alters value, empty while statement ...).
  • Minor improvement of - Doxygen Tags for CHM UM generation.
  • Replace POSITION_VAL(xxx) macro by corresponding CMSIS_Pos definitions.

HAL Drivers changes

  • The following changes done on the HAL drivers require an update on the application code based on HAL V1.3.0
    • HAL NAND driver: Overall driver rework with compatibility break versus previous HAL version (see below).

  • HAL
    • Correct RTC_PREDIV values (for LSI clock) in hal_timebase_rtc_alam_template.c and hal_timebase_rtc_wakeup_template.c
    • Add definition of USE_SPI_CRC in hal_conf_template.h
    • Modify HAL_Delay() function to garantee minimum delay.
    • New API : HAL_GetUIDwx() read the unique device identifier word x.
  • HAL ADC
    • Remove unused litteral ADC_EOC_SINGLE_SEQ_CONV.
    • Correct name of one ADC1 external trigger of regular group : ADC_EXTERNALTRIGCONV_T4_CC4.
  • HAL CAN
    • Add transmission abort when timeout is reached in HAL_CAN_Transmit().
    • Add managment of overrun error. 
    • Store missing FIFO number in received message.
    • Extend SET_BIT, CLEAR_BIT macro usage.
    • Allow possibility to receive messages from the 2 RX FIFOs in parallel via interrupt.
    • Fix message lost issue with specific sequence of transmit requests.
  • HAL COMP
    • COMP_WINDOWMODE litterals clean-up according to family diversity.
  • HAL NAND
    • Overall driver rework in order to support NAND flash memories with higher capacities. 
    • Add support of 16 bits adressing mode
    • API changes :
      • Add HAL_NAND_ConfigDevice() function
      • Split HAL_NAND_Read_Page(), + Doxygen Tags for CHM UM generation.
      • Replace POSITION_VAL(xxx) macro by corresponding CMSIS_Pos definitions.

      HAL Drivers changes

      • The following changes done on the HAL drivers require an update on the application code based on HAL V1.4.0
        • HAL NAND driver: Overall driver rework with compatibility break versus previous HAL version (see below).

      • HAL
        • Correct RTC_PREDIV values (for LSI clock) in hal_timebase_rtc_alam_template.c and hal_timebase_rtc_wakeup_template.c
        • Add definition of USE_SPI_CRC in hal_conf_template.h
        • Modify HAL_Delay() function to garantee minimum delay.
        • New API : HAL_GetUIDwx() read the unique device identifier word x.
      • HAL ADC
        • Remove unused litteral ADC_EOC_SINGLE_SEQ_CONV.
        • Correct name of one ADC external trigger of regular group : ADC_EXTERNALTRIGCONV_T4_CC4.
      • HAL CAN
        • Add transmission abort when timeout is reached in HAL_CAN_Transmit().
        • Add managment of overrun error. 
        • Store missing FIFO number in received message.
        • Extend SET_BIT, CLEAR_BIT macro usage.
        • Allow possibility to receive messages from the 2 RX FIFOs in parallel via interrupt.
        • Fix message lost issue with specific sequence of transmit requests.
      • HAL COMP
        • COMP_WINDOWMODE litterals clean-up according to family diversity.
      • HAL NAND
        • Overall driver rework in order to support NAND flash memories with higher capacities. 
        • Add support of 16 bits adressing mode
        • API changes :
          • Add HAL_NAND_ConfigDevice() function
          • Split HAL_NAND_Read_Page(), HAL_NAND_Write_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_SpareArea() in _8b and  _ 16b functions to select the proper adressing mode.
      • HAL HRTIM
        • Modify __HAL_HRTIM_SETCLOCKPRESCALER macro to clear CKPSC and CKPSCx bits before setting new prescaler value.
        • Correct HRTIM_EVENTFASTMODE_DISABLE and HRTIM_EVENTFASTMODE_ENABLE defines.
      • HAL I2C
        • Editorial modification : astyle clean-up
      • HAL SMBUS
        • New API : Digital/Analog filter configuration with HAL_SMBUS_ConfigAnalogFilter() and HAL_SMBUS_ConfigDigitalFilter().
      • HAL diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c index 5be17ad4b1..4c252d7d14 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c @@ -68,11 +68,11 @@ * @{ */ /** - * @brief STM32F3xx HAL Driver version number V1.5.0 + * @brief STM32F3xx HAL Driver version number V1.5.1 */ #define __STM32F3xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32F3xx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */ -#define __STM32F3xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32F3xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ #define __STM32F3xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24U)\ |(__STM32F3xx_HAL_VERSION_SUB1 << 16U)\ @@ -90,6 +90,8 @@ * @{ */ __IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ /** * @} */ @@ -109,12 +111,12 @@ __IO uint32_t uwTick; =============================================================================== [..] This section provides functions allowing to: (+) Initializes the Flash interface, the NVIC allocation and initial clock - configuration. It initializes the source of time base also when timeout - is needed and the backup domain when enabled. + configuration. It initializes the systick also when timeout is needed + and the backup domain when enabled. (+) de-Initializes common part of the HAL. (+) Configure The time base source to have 1ms time base with a dedicated Tick interrupt priority. - (++) Systick timer is used by default as source of time base, but user + (++) SysTick timer is used by default as source of time base, but user can eventually implement his proper time base source (a general purpose timer for example or other time source), keeping in mind that Time base duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and @@ -170,8 +172,7 @@ HAL_StatusTypeDef HAL_Init(void) } /** - * @brief This function de-Initializes common part of the HAL and stops the source - * of time base. + * @brief This function de-Initializes common part of the HAL and stops the systick. * @note This function is optional. * @retval HAL status */ @@ -195,23 +196,23 @@ HAL_StatusTypeDef HAL_DeInit(void) } /** - * @brief Initializes the MSP. + * @brief Initialize the MSP. * @retval None */ __weak void HAL_MspInit(void) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspInit could be implemented in the user file */ } /** - * @brief DeInitializes the MSP. + * @brief DeInitialize the MSP. * @retval None */ __weak void HAL_MspDeInit(void) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspDeInit could be implemented in the user file */ } @@ -225,7 +226,7 @@ __weak void HAL_MspDeInit(void) * @note In the default implementation , SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals. * Care must be taken if HAL_Delay() is called from a peripheral ISR process, - * The the SysTick interrupt must have higher priority (numerically lower) + * The SysTick interrupt must have higher priority (numerically lower) * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * The function is declared as __Weak to be overwritten in case of other * implementation in user file. @@ -234,12 +235,22 @@ __weak void HAL_MspDeInit(void) */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { - /*Configure the SysTick to have interrupt in 1ms time basis*/ - HAL_SYSTICK_Config(SystemCoreClock / 1000U); - - /*Configure the SysTick IRQ priority */ - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U); + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + { + return HAL_ERROR; + } + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + return HAL_ERROR; + } /* Return function status */ return HAL_OK; } @@ -275,14 +286,14 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) * @brief This function is called to increment a global variable "uwTick" * used as application time base. * @note In the default implementation, this variable is incremented each 1ms - * in Systick ISR. + * in SysTick ISR. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { - uwTick++; + uwTick += uwTickFreq; } /** @@ -296,6 +307,44 @@ __weak uint32_t HAL_GetTick(void) return uwTick; } +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval Status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval tick period in Hz + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + /** * @brief This function provides accurate delay (in milliseconds) based * on variable incremented. @@ -307,15 +356,15 @@ __weak uint32_t HAL_GetTick(void) * @param Delay specifies the delay time length, in milliseconds. * @retval None */ -__weak void HAL_Delay(__IO uint32_t Delay) +__weak void HAL_Delay(uint32_t Delay) { uint32_t tickstart = HAL_GetTick(); uint32_t wait = Delay; - /* Add a period to guarantee minimum wait */ + /* Add freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) { - wait++; + wait += (uint32_t)(uwTickFreq); } while((HAL_GetTick() - tickstart) < wait) @@ -360,7 +409,7 @@ __weak void HAL_ResumeTick(void) /** * @brief This function returns the HAL revision - * @retval version : 0xXYZR (8bits for each decimal, R for RC) + * @retval version 0xXYZR (8bits for each decimal, R for RC) */ uint32_t HAL_GetHalVersion(void) { diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c index 5762694e32..b29dcdc6d0 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c @@ -495,18 +495,22 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { - if (HAL_IS_BIT_SET(FLASH->CR, FLASH_CR_LOCK)) + HAL_StatusTypeDef status = HAL_OK; + + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) { /* Authorize the FLASH Registers access */ WRITE_REG(FLASH->KEYR, FLASH_KEY1); WRITE_REG(FLASH->KEYR, FLASH_KEY2); - } - else - { - return HAL_ERROR; + + /* Verify Flash is unlocked */ + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + status = HAL_ERROR; + } } - return HAL_OK; + return status; } /** diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c index 7328bf6ca2..c7b6684bdf 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c @@ -105,6 +105,12 @@ (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address and with new data to transfer if the direction change or manage only the new data to transfer if no direction change and with a final stop condition in both cases + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential + interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using HAL_I2C_Master_Sequential_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Sequential_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. (+) Differents sequential I2C interfaces are listed below: (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() @@ -301,8 +307,8 @@ /* Private macro -------------------------------------------------------------*/ #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \ - ((uint32_t)((__HANDLE__)->hdmatx->Instance->CNDTR)) : \ - ((uint32_t)((__HANDLE__)->hdmarx->Instance->CNDTR))) + ((uint32_t)(((DMA_Channel_TypeDef *)(__HANDLE__)->hdmatx->Instance)->CNDTR)) : \ + ((uint32_t)(((DMA_Channel_TypeDef *)(__HANDLE__)->hdmarx->Instance)->CNDTR))) /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -618,7 +624,7 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration @@ -742,7 +748,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration @@ -1138,7 +1144,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status @@ -1207,7 +1213,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status @@ -1374,7 +1380,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status @@ -1482,7 +1488,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status @@ -1720,7 +1726,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -1873,7 +1879,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2018,7 +2024,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2117,7 +2123,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2215,7 +2221,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2331,7 +2337,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2447,7 +2453,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param Trials Number of trials * @param Timeout Timeout duration * @retval HAL status @@ -2566,7 +2572,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS @@ -2639,7 +2645,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS @@ -2914,7 +2920,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) @@ -3632,7 +3638,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param Timeout Timeout duration @@ -3699,7 +3705,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param Timeout Timeout duration @@ -4584,20 +4590,31 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check if a STOPF is detected */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) { - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Check if an RXNE is pending */ + /* Store Last receive data if any */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) + { + /* Return HAL_OK */ + /* The Reading of data from RXDR will be done in caller function */ + return HAL_OK; + } + else + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } /* Check for the Timeout */ @@ -4691,25 +4708,14 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 */ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { - uint32_t tmpreg = 0U; - /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); - /* Get the CR2 register value */ - tmpreg = hi2c->Instance->CR2; - - /* clear tmpreg specific bits */ - tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); - - /* update tmpreg */ - tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request); - /* update CR2 register */ - hi2c->Instance->CR2 = tmpreg; + MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); } /** diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c index e58a72eb3e..3a5c2ea41a 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c @@ -17,7 +17,8 @@ (+) Possibility to disable or enable Analog Noise Filter (+) Use of a configured Digital Noise Filter - (+) Disable or enable wakeup from Stop mode + (+) Disable or enable wakeup from Stop mode(s) + (+) Disable or enable Fast Mode Plus ##### How to use this driver ##### ============================================================================== @@ -96,6 +97,7 @@ [..] This section provides functions allowing to: (+) Configure Noise Filters (+) Configure Wake Up Feature + (+) Configure Fast Mode Plus @endverbatim * @{ @@ -198,7 +200,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ } /** - * @brief Enable I2C wakeup from stop mode. + * @brief Enable I2C wakeup from Stop mode(s). * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2Cx peripheral. * @retval HAL status @@ -237,7 +239,7 @@ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) } /** - * @brief Disable I2C wakeup from stop mode. + * @brief Disable I2C wakeup from Stop mode(s). * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2Cx peripheral. * @retval HAL status diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smbus.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smbus.c index e1256ac71c..52277c6974 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smbus.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smbus.c @@ -542,7 +542,7 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition @@ -635,7 +635,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition @@ -722,7 +722,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @retval HAL status */ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress) @@ -791,7 +791,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { if ((pData == NULL) || (Size == 0U)) { @@ -804,7 +804,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Process Locked */ __HAL_LOCK(hsmbus); - hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX; + hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_TX | HAL_SMBUS_STATE_LISTEN); hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; /* Set SBC bit to manage Acknowledge at each bit */ @@ -884,7 +884,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { if ((pData == NULL) || (Size == 0U)) { @@ -897,7 +897,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* Process Locked */ __HAL_LOCK(hsmbus); - hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX; + hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_RX | HAL_SMBUS_STATE_LISTEN); hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; /* Set SBC bit to manage Acknowledge at each bit */ @@ -1031,7 +1031,7 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param Trials Number of trials * @param Timeout Timeout duration * @retval HAL status @@ -1200,7 +1200,7 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET))) { - if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { SMBUS_Slave_ISR(hsmbus); } @@ -1683,7 +1683,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* or only the last Byte of Transfer */ /* So reset the RELOAD bit mode */ hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE; - SMBUS_TransferConfig(hsmbus, 0U , 1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } else if (hsmbus->XferCount == 0U) { @@ -2097,25 +2097,14 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu */ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { - uint32_t tmpreg = 0U; - /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); assert_param(IS_SMBUS_TRANSFER_MODE(Mode)); assert_param(IS_SMBUS_TRANSFER_REQUEST(Request)); - /* Get the CR2 register value */ - tmpreg = hsmbus->Instance->CR2; - - /* clear tmpreg specific bits */ - tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)); - - /* update tmpreg */ - tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request); - /* update CR2 register */ - hsmbus->Instance->CR2 = tmpreg; + MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); } /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index c37602b2a3..79999700e8 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -35,8 +35,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32_HAL_LEGACY -#define __STM32_HAL_LEGACY +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY #ifdef __cplusplus extern "C" { @@ -274,7 +274,96 @@ #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#endif /* STM32L4 */ +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#endif /* STM32H7 */ /** * @} @@ -355,6 +444,30 @@ #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ /** * @} @@ -456,78 +569,6 @@ * @} */ -/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose - * @{ - */ - -#if defined(STM32H7) - #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE - #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE - #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET - #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET - #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE - #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE - - #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 - #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 - - #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX - #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX - - #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT - #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT - #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT - #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT - #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT - #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT - #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 - #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO - - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT - #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT - #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 - #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 - #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT - #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT - #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT - #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT - #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT - #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT - - #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT - #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING - #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING - #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING - - -#endif /* STM32H7 */ - - -/** - * @} - */ - - /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose * @{ */ @@ -887,6 +928,10 @@ #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif /** * @} */ @@ -1047,8 +1092,8 @@ * @} */ -#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ - defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose * @{ */ @@ -2804,7 +2849,7 @@ #if defined(STM32L4) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#elif defined(STM32WB) || defined(STM32G0) +#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif @@ -3253,7 +3298,10 @@ * @{ */ #define __HAL_LTDC_LAYER LTDC_LAYER +#if defined(STM32F7) +#else #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +#endif /** * @} */ @@ -3303,7 +3351,7 @@ } #endif -#endif /* ___STM32_HAL_LEGACY */ +#endif /* STM32_HAL_LEGACY */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h index 361af21c7d..6d137f361d 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h @@ -361,26 +361,59 @@ typedef struct * @} */ -/** +/** * @brief ADC handle Structure definition */ -typedef struct +typedef struct __ADC_HandleTypeDef { ADC_TypeDef *Instance; /*!< Register base address */ - ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ - DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ - HAL_LockTypeDef Lock; /*!< ADC locking object */ - __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ - __IO uint32_t ErrorCode; /*!< ADC Error code */ - ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ + void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ + void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ + void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ + void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ + void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */ + void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ + void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ + void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ + void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ + void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ }ADC_HandleTypeDef; +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL ADC Callback ID enumeration definition + */ +typedef enum +{ + HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ + HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ + HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ + HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ + HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ + HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */ + HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ + HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ + HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ + HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ + HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ +} HAL_ADC_CallbackIDTypeDef; + +/** + * @brief HAL ADC Callback pointer definition + */ +typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ + +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + /** * @} */ @@ -395,12 +428,15 @@ typedef struct /** @defgroup ADC_Error_Code ADC Error Code * @{ */ -#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ -#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error (problem of clocking, - enable/disable, erroneous state, ...) */ -#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ -#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ -#define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ +#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ +#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error (problem of clocking, + enable/disable, erroneous state, ...) */ +#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ +#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ +#define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ @@ -689,17 +725,17 @@ typedef struct /** @defgroup ADC_interrupts_definition ADC interrupts definition * @{ */ -#define ADC_IT_RDY ADC_IER_ADRDY /*!< ADC Ready interrupt source */ -#define ADC_IT_EOSMP ADC_IER_EOSMP /*!< ADC End of sampling interrupt source */ -#define ADC_IT_EOC ADC_IER_EOC /*!< ADC End of regular conversion interrupt source */ -#define ADC_IT_EOS ADC_IER_EOS /*!< ADC End of regular sequence of conversions interrupt source */ -#define ADC_IT_OVR ADC_IER_OVR /*!< ADC overrun interrupt source */ -#define ADC_IT_JEOC ADC_IER_JEOC /*!< ADC End of injected conversion interrupt source */ -#define ADC_IT_JEOS ADC_IER_JEOS /*!< ADC End of injected sequence of conversions interrupt source */ -#define ADC_IT_AWD1 ADC_IER_AWD1 /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ -#define ADC_IT_AWD2 ADC_IER_AWD2 /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ -#define ADC_IT_AWD3 ADC_IER_AWD3 /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ -#define ADC_IT_JQOVF ADC_IER_JQOVF /*!< ADC Injected Context Queue Overflow interrupt source */ +#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ +#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ +#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ +#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ +#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ +#define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ +#define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ +#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ +#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ +#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ +#define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ #define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ @@ -1026,8 +1062,17 @@ typedef struct * @param __HANDLE__ ADC handle * @retval None */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ ((__HANDLE__)->State = HAL_ADC_STATE_RESET) +#endif /** * @brief Enable ADC interrupt. @@ -1698,6 +1743,12 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_can.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_can.h index 37bf98b9f8..445c2c4ebc 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_can.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_can.h @@ -151,7 +151,7 @@ typedef struct This parameter can be a value of @ref CAN_filter_scale */ uint32_t FilterActivation; /*!< Enable or disable the filter. - This parameter can be set to ENABLE or DISABLE. */ + This parameter can be a value of @ref CAN_filter_activation */ uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance. For single CAN instances, this parameter is meaningless. @@ -233,8 +233,58 @@ typedef struct __CAN_HandleTypeDef __IO uint32_t ErrorCode; /*!< CAN Error code. This parameter can be a value of @ref CAN_Error_Code */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback */ + void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback */ + void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback */ + void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 0 abort callback */ + void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 1 abort callback */ + void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 2 abort callback */ + void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback */ + void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 full callback */ + void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback */ + void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 full callback */ + void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Sleep callback */ + void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Wake Up from Rx msg callback */ + void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Error callback */ + + void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp Init callback */ + void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp DeInit callback */ + +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ } CAN_HandleTypeDef; +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +/** + * @brief HAL CAN common Callback ID enumeration definition + */ +typedef enum +{ + HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID = 0x00U, /*!< CAN Tx Mailbox 0 complete callback ID */ + HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID = 0x01U, /*!< CAN Tx Mailbox 1 complete callback ID */ + HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID = 0x02U, /*!< CAN Tx Mailbox 2 complete callback ID */ + HAL_CAN_TX_MAILBOX0_ABORT_CB_ID = 0x03U, /*!< CAN Tx Mailbox 0 abort callback ID */ + HAL_CAN_TX_MAILBOX1_ABORT_CB_ID = 0x04U, /*!< CAN Tx Mailbox 1 abort callback ID */ + HAL_CAN_TX_MAILBOX2_ABORT_CB_ID = 0x05U, /*!< CAN Tx Mailbox 2 abort callback ID */ + HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID = 0x06U, /*!< CAN Rx FIFO 0 message pending callback ID */ + HAL_CAN_RX_FIFO0_FULL_CB_ID = 0x07U, /*!< CAN Rx FIFO 0 full callback ID */ + HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */ + HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */ + HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */ + HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up fropm Rx msg callback ID */ + HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */ + + HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */ + HAL_CAN_MSPDEINIT_CB_ID = 0x0EU, /*!< CAN MspDeInit callback ID */ + +} HAL_CAN_CallbackIDTypeDef; + +/** + * @brief HAL CAN Callback pointer definition + */ +typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function */ + +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /** * @} */ @@ -272,6 +322,11 @@ typedef struct __CAN_HandleTypeDef #define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */ #define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error */ +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +#define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */ + /** * @} */ @@ -364,6 +419,15 @@ typedef struct __CAN_HandleTypeDef * @} */ +/** @defgroup CAN_filter_activation CAN Filter Activation + * @{ + */ +#define CAN_FILTER_DISABLE (0x00000000U) /*!< Disable filter */ +#define CAN_FILTER_ENABLE (0x00000001U) /*!< Enable filter */ +/** + * @} + */ + /** @defgroup CAN_filter_FIFO CAN Filter FIFO * @{ */ @@ -496,7 +560,15 @@ typedef struct __CAN_HandleTypeDef * @param __HANDLE__ CAN handle. * @retval None */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_CAN_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) +#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */ /** * @brief Enable the specified CAN interrupts. @@ -587,6 +659,12 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan); void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan); void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan)); +HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID); + +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ /** * @} */ @@ -738,6 +816,8 @@ HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); ((MODE) == CAN_FILTERMODE_IDLIST)) #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ ((SCALE) == CAN_FILTERSCALE_32BIT)) +#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \ + ((ACTIVATION) == CAN_FILTER_ENABLE)) #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ ((FIFO) == CAN_FILTER_FIFO1)) #define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_comp.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_comp.h index 51f573a3b3..bb5a94ae71 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_comp.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_comp.h @@ -38,11 +38,9 @@ #define __STM32L4xx_HAL_COMP_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -#if defined (COMP1) || defined (COMP2) - /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" #include "stm32l4xx_ll_exti.h" @@ -50,6 +48,7 @@ /** @addtogroup STM32L4xx_HAL_Driver * @{ */ +#if defined (COMP1) || defined (COMP2) /** @addtogroup COMP * @{ @@ -113,14 +112,38 @@ typedef enum /** * @brief COMP Handle Structure definition */ -typedef struct +typedef struct __COMP_HandleTypeDef { COMP_TypeDef *Instance; /*!< Register base address */ COMP_InitTypeDef Init; /*!< COMP required parameters */ HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */ + __IO uint32_t ErrorCode; /*!< COMP error code */ +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) + void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP trigger callback */ + void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp Init callback */ + void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */ +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ } COMP_HandleTypeDef; +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) +/** + * @brief HAL COMP Callback ID enumeration definition + */ +typedef enum +{ + HAL_COMP_TRIGGER_CB_ID = 0x00U, /*!< COMP trigger callback ID */ + HAL_COMP_MSPINIT_CB_ID = 0x01U, /*!< COMP Msp Init callback ID */ + HAL_COMP_MSPDEINIT_CB_ID = 0x02U /*!< COMP Msp DeInit callback ID */ +} HAL_COMP_CallbackIDTypeDef; + +/** + * @brief HAL COMP Callback pointer definition + */ +typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */ + +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + /** * @} */ @@ -130,6 +153,17 @@ typedef struct * @{ */ +/** @defgroup COMP_Error_Code COMP Error Code + * @{ + */ +#define HAL_COMP_ERROR_NONE (0x00U) /*!< No error */ +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) +#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01U) /*!< Invalid Callback error */ +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ +/** + * @} + */ + /** @defgroup COMP_WindowMode COMP Window Mode * @{ */ @@ -268,7 +302,22 @@ typedef struct * @param __HANDLE__ COMP handle * @retval None */ +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) +#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_COMP_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET) +#endif + +/** + * @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE"). + * @param __HANDLE__ COMP handle + * @retval None + */ +#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE) /** * @brief Enable the specified comparator. @@ -667,6 +716,12 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp); HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp); void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp); void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp); + +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ /** * @} */ @@ -699,6 +754,7 @@ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); * @{ */ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp); /** * @} */ @@ -710,7 +766,7 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); /** * @} */ - +#endif /* COMP1 || COMP2 */ /** * @} */ @@ -719,8 +775,6 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); } #endif -#endif /* COMP1 || COMP2 */ - #endif /* __STM32L4xx_HAL_COMP_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_conf_template.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_conf_template.h index c647a79075..7e26da71bc 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_conf_template.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_conf_template.h @@ -107,11 +107,11 @@ * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -119,7 +119,7 @@ * This value is the default MSI range value after Reset. */ #if !defined (MSI_VALUE) - #define MSI_VALUE ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/ + #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* MSI_VALUE */ /** @@ -128,7 +128,7 @@ * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** @@ -139,7 +139,7 @@ * which is subject to manufacturing process variations. */ #if !defined (HSI48_VALUE) - #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. + #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. The real value my vary depending on manufacturing process variations.*/ #endif /* HSI48_VALUE */ @@ -147,8 +147,8 @@ * @brief Internal Low Speed oscillator (LSI) value. */ #if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature.*/ /** @@ -156,11 +156,11 @@ * This value is used by the UART, RTC HAL module to compute the system frequency */ #if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/ + #define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/ #endif /* LSE_VALUE */ #if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -169,7 +169,7 @@ * frequency. */ #if !defined (EXTERNAL_SAI1_CLOCK_VALUE) - #define EXTERNAL_SAI1_CLOCK_VALUE ((uint32_t)48000U) /*!< Value of the SAI1 External clock source in Hz*/ + #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1 External clock source in Hz*/ #endif /* EXTERNAL_SAI1_CLOCK_VALUE */ /** @@ -178,7 +178,7 @@ * frequency. */ #if !defined (EXTERNAL_SAI2_CLOCK_VALUE) - #define EXTERNAL_SAI2_CLOCK_VALUE ((uint32_t)48000U) /*!< Value of the SAI2 External clock source in Hz*/ + #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2 External clock source in Hz*/ #endif /* EXTERNAL_SAI2_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, @@ -188,8 +188,8 @@ /** * @brief This is the HAL system configuration section */ -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0x0FU) /*!< tick interrupt priority */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ #define USE_RTOS 0U #define PREFETCH_ENABLE 0U #define INSTRUCTION_CACHE_ENABLE 1U @@ -202,6 +202,50 @@ */ /* #define USE_FULL_ASSERT 1U */ +/* ################## Register callback feature configuration ############### */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/deregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32l4xx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U +#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_TSC_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U + /* ################## SPI peripheral configuration ########################## */ /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc.h index c663af46f2..7d92bebc2d 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc.h @@ -30,7 +30,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -38,7 +38,7 @@ #define __STM32L4xx_HAL_CRC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -50,48 +50,45 @@ /** @addtogroup CRC * @{ - */ - -/* Exported types ------------------------------------------------------------*/ + */ +/* Exported types ------------------------------------------------------------*/ /** @defgroup CRC_Exported_Types CRC Exported Types * @{ */ -/** - * @brief CRC HAL State Structure definition - */ +/** + * @brief CRC HAL State Structure definition + */ typedef enum -{ - HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */ - HAL_CRC_STATE_READY = 0x01, /*!< CRC initialized and ready for use */ - HAL_CRC_STATE_BUSY = 0x02, /*!< CRC internal process is ongoing */ - HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC timeout state */ - HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */ -}HAL_CRC_StateTypeDef; - - +{ + HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */ + HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */ + HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */ + HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */ + HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */ +} HAL_CRC_StateTypeDef; -/** - * @brief CRC Init Structure definition - */ +/** + * @brief CRC Init Structure definition + */ typedef struct { - uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used. - If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default - X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. + uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used. + If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default + X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. In that case, there is no need to set GeneratingPolynomial field. If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */ - uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used. + uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used. If set to DEFAULT_INIT_VALUE_ENABLE, resort to default - 0xFFFFFFFF value. In that case, there is no need to set InitValue field. + 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */ uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree - respectively equal to 7, 8, 16 or 32. This field is written in normal representation, + respectively equal to 7, 8, 16 or 32. This field is written in normal representation, e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65. - No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */ + No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */ uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length. Value can be either one of @@ -99,49 +96,45 @@ typedef struct @arg @ref CRC_POLYLENGTH_16B (16-bit CRC), @arg @ref CRC_POLYLENGTH_8B (8-bit CRC), @arg @ref CRC_POLYLENGTH_7B (7-bit CRC). */ - - uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse - is set to DEFAULT_INIT_VALUE_ENABLE. */ - - uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode. - Can be either one of the following values + + uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse + is set to DEFAULT_INIT_VALUE_ENABLE. */ + + uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode. + Can be either one of the following values @arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2 @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C - @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */ - - uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode. - Can be either - @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, - @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */ -}CRC_InitTypeDef; - + @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */ + uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode. + Can be either + @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, + @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */ +} CRC_InitTypeDef; -/** - * @brief CRC Handle Structure definition - */ +/** + * @brief CRC Handle Structure definition + */ typedef struct { - CRC_TypeDef *Instance; /*!< Register base address */ - + CRC_TypeDef *Instance; /*!< Register base address */ + CRC_InitTypeDef Init; /*!< CRC configuration parameters */ - + HAL_LockTypeDef Lock; /*!< CRC Locking object */ - + __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */ - - uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format. - Can be either + + uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format. + Can be either @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data) @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data) @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bit data) - - Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error - must occur if InputBufferFormat is not one of the three values listed above */ -}CRC_HandleTypeDef; - + Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error + must occur if InputBufferFormat is not one of the three values listed above */ +} CRC_HandleTypeDef; /** * @} */ @@ -170,15 +163,15 @@ typedef struct /** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used * @{ */ -#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */ -#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */ +#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */ +#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */ /** * @} */ - + /** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used * @{ - */ + */ #define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */ #define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */ /** @@ -188,10 +181,10 @@ typedef struct /** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP * @{ */ -#define CRC_POLYLENGTH_32B (0x00000000U) /*!< Resort to a 32-bit long generating polynomial */ -#define CRC_POLYLENGTH_16B (CRC_CR_POLYSIZE_0) /*!< Resort to a 16-bit long generating polynomial */ -#define CRC_POLYLENGTH_8B (CRC_CR_POLYSIZE_1) /*!< Resort to a 8-bit long generating polynomial */ -#define CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE) /*!< Resort to a 7-bit long generating polynomial */ +#define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */ +#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */ +#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */ +#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */ /** * @} */ @@ -199,29 +192,29 @@ typedef struct /** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions * @{ */ -#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */ -#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */ -#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */ -#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */ +#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */ +#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */ +#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */ +#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */ /** * @} - */ + */ /** @defgroup CRC_Input_Buffer_Format Input Buffer Format * @{ */ /* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but - * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set - * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for - * the CRC APIs to provide a correct result */ -#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */ -#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */ -#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */ -#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */ -/** + * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set + * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for + * the CRC APIs to provide a correct result */ +#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */ +#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */ +#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */ +#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */ +/** * @} */ - + /** @defgroup CRC_Aliases CRC API aliases * @{ */ @@ -235,45 +228,44 @@ typedef struct * @} */ - /* Exported macros -----------------------------------------------------------*/ /** @defgroup CRC_Exported_Macros CRC Exported Macros * @{ */ /** @brief Reset CRC handle state. - * @param __HANDLE__: CRC handle. + * @param __HANDLE__ CRC handle. * @retval None */ #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) /** * @brief Reset CRC Data Register. - * @param __HANDLE__: CRC handle + * @param __HANDLE__ CRC handle * @retval None */ #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET) /** * @brief Set CRC INIT non-default value - * @param __HANDLE__: CRC handle - * @param __INIT__: 32-bit initial value + * @param __HANDLE__ CRC handle + * @param __INIT__ 32-bit initial value * @retval None */ -#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__)) +#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__)) /** * @brief Store data in the Independent Data (ID) register. - * @param __HANDLE__: CRC handle - * @param __VALUE__: Value to be stored in the ID register + * @param __HANDLE__ CRC handle + * @param __VALUE__ Value to be stored in the ID register * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits * @retval None */ -#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (MODIFY_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__))) +#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__))) /** * @brief Return the data stored in the Independent Data (ID) register. - * @param __HANDLE__: CRC handle + * @param __HANDLE__ CRC handle * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits * @retval Value of the ID register */ @@ -284,25 +276,25 @@ typedef struct /* Private macros --------------------------------------------------------*/ -/** @addtogroup CRC_Private_Macros CRC Private Macros +/** @defgroup CRC_Private_Macros CRC Private Macros * @{ */ #define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \ ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE)) - + #define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \ - ((VALUE) == DEFAULT_INIT_VALUE_DISABLE)) - + ((VALUE) == DEFAULT_INIT_VALUE_DISABLE)) + #define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \ ((LENGTH) == CRC_POLYLENGTH_16B) || \ ((LENGTH) == CRC_POLYLENGTH_8B) || \ - ((LENGTH) == CRC_POLYLENGTH_7B)) + ((LENGTH) == CRC_POLYLENGTH_7B)) -#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \ +#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \ ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \ - ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS)) + ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS)) /** * @} @@ -319,9 +311,9 @@ typedef struct /* Initialization and de-initialization functions ****************************/ /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions * @{ - */ + */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc); -HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc); +HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc); void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc); void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc); /** @@ -353,7 +345,7 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc); /** * @} - */ + */ /** * @} diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc_ex.h index 69c0687032..5bf97b47b2 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc_ex.h @@ -30,7 +30,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -38,7 +38,7 @@ #define __STM32L4xx_HAL_CRC_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -50,21 +50,21 @@ /** @addtogroup CRCEx * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ -/** @defgroup CRCEx_Exported_Constants CRCEx Exported Constants +/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants * @{ */ /** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes * @{ */ -#define CRC_INPUTDATA_INVERSION_NONE (0x00000000U) /*!< No input data inversion */ -#define CRC_INPUTDATA_INVERSION_BYTE (CRC_CR_REV_IN_0) /*!< Byte-wise input data inversion */ -#define CRC_INPUTDATA_INVERSION_HALFWORD (CRC_CR_REV_IN_1) /*!< HalfWord-wise input data inversion */ -#define CRC_INPUTDATA_INVERSION_WORD (CRC_CR_REV_IN) /*!< Word-wise input data inversion */ +#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */ +#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */ +#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */ +#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */ /** * @} */ @@ -72,39 +72,39 @@ /** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes * @{ */ -#define CRC_OUTPUTDATA_INVERSION_DISABLE (0x00000000U) /*!< No output data inversion */ -#define CRC_OUTPUTDATA_INVERSION_ENABLE (CRC_CR_REV_OUT) /*!< Bit-wise output data inversion */ +#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */ +#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */ /** * @} */ -/** +/** * @} */ /* Exported macro ------------------------------------------------------------*/ -/** @defgroup CRCEx_Exported_Macros CRCEx Exported Macros +/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros * @{ */ - + /** * @brief Set CRC output reversal - * @param __HANDLE__: CRC handle + * @param __HANDLE__ CRC handle * @retval None */ -#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT) +#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT) /** * @brief Unset CRC output reversal - * @param __HANDLE__: CRC handle + * @param __HANDLE__ CRC handle * @retval None */ -#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT)) +#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT)) /** * @brief Set CRC non-default polynomial - * @param __HANDLE__: CRC handle - * @param __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial + * @param __HANDLE__ CRC handle + * @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial * @retval None */ #define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__)) @@ -114,18 +114,17 @@ */ /* Private macros --------------------------------------------------------*/ -/** @addtogroup CRCEx_Private_Macros CRCEx Private Macros +/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros * @{ */ - -#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \ - ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \ + +#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \ + ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \ ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \ ((MODE) == CRC_INPUTDATA_INVERSION_WORD)) - #define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \ - ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE)) + ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE)) /** * @} @@ -133,14 +132,13 @@ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup CRCEx_Exported_Functions CRC Extended Exported Functions +/** @addtogroup CRCEx_Exported_Functions * @{ */ - -/** @addtogroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions + +/** @addtogroup CRCEx_Exported_Functions_Group1 * @{ */ - /* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength); HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode); @@ -148,20 +146,20 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ /** * @} */ - + #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp.h index 2b98e88e1c..6f3eb3e872 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp.h @@ -31,7 +31,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L4xx_HAL_CRYP_H @@ -41,7 +41,7 @@ extern "C" { #endif -#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(AES) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -59,7 +59,7 @@ * @{ */ -/** +/** * @brief CRYP Configuration Structure definition */ typedef struct @@ -67,36 +67,36 @@ typedef struct uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string. This parameter can be a value of @ref CRYP_Data_Type */ - uint32_t KeySize; /*!< 128 or 256-bit key length. + uint32_t KeySize; /*!< 128 or 256-bit key length. This parameter can be a value of @ref CRYP_Key_Size */ - - uint32_t OperatingMode; /*!< AES operating mode. + + uint32_t OperatingMode; /*!< AES operating mode. This parameter can be a value of @ref CRYP_AES_OperatingMode */ - - uint32_t ChainingMode; /*!< AES chaining mode. + + uint32_t ChainingMode; /*!< AES chaining mode. This parameter can be a value of @ref CRYP_AES_ChainingMode */ - - uint32_t KeyWriteFlag; /*!< Allows to bypass or not key write-up before decryption. - This parameter can be a value of @ref CRYP_Key_Write */ - - uint32_t GCMCMACPhase; /*!< Indicates the processing phase of the Galois Counter Mode (GCM), - Galois Message Authentication Code (GMAC), Cipher Message - Authentication Code (CMAC) (when applicable) or Counter with Cipher + + uint32_t KeyWriteFlag; /*!< Allows to bypass or not key write-up before decryption. + This parameter can be a value of @ref CRYP_Key_Write */ + + uint32_t GCMCMACPhase; /*!< Indicates the processing phase of the Galois Counter Mode (GCM), + Galois Message Authentication Code (GMAC), Cipher Message + Authentication Code (CMAC) (when applicable) or Counter with Cipher Mode (CCM) (when applicable). - This parameter can be a value of @ref CRYP_GCM_CMAC_Phase */ + This parameter can be a value of @ref CRYP_GCM_CMAC_Phase */ uint8_t* pKey; /*!< Encryption/Decryption Key */ - uint8_t* pInitVect; /*!< Initialization Vector used for CTR, CBC, GCM/GMAC, CMAC (when applicable) + uint8_t* pInitVect; /*!< Initialization Vector used for CTR, CBC, GCM/GMAC, CMAC (when applicable) and CCM (when applicable) modes */ uint8_t* Header; /*!< Header used in GCM/GMAC, CMAC (when applicable) and CCM (when applicable) modes */ uint64_t HeaderSize; /*!< Header size in bytes */ - + }CRYP_InitTypeDef; -/** +/** * @brief HAL CRYP State structures definition */ typedef enum @@ -109,47 +109,65 @@ typedef enum HAL_CRYP_STATE_SUSPENDED = 0x05 /*!< CRYP suspended */ }HAL_CRYP_STATETypeDef; -/** +/** * @brief HAL CRYP phase structures definition */ typedef enum { HAL_CRYP_PHASE_READY = 0x01, /*!< CRYP peripheral is ready for initialization. */ HAL_CRYP_PHASE_PROCESS = 0x02, /*!< CRYP peripheral is in processing phase */ - HAL_CRYP_PHASE_START = 0x03, /*!< CRYP peripheral has been initialized but + HAL_CRYP_PHASE_START = 0x03, /*!< CRYP peripheral has been initialized but GCM/GMAC(/CMAC)(/CCM) initialization phase has not started */ - HAL_CRYP_PHASE_INIT_OVER = 0x04, /*!< GCM/GMAC(/CMAC)(/CCM) init phase has been carried out */ - HAL_CRYP_PHASE_HEADER_OVER = 0x05, /*!< GCM/GMAC(/CMAC)(/CCM) header phase has been carried out */ - HAL_CRYP_PHASE_PAYLOAD_OVER = 0x06, /*!< GCM(/CCM) payload phase has been carried out */ + HAL_CRYP_PHASE_INIT_OVER = 0x04, /*!< GCM/GMAC(/CMAC)(/CCM) init phase has been carried out */ + HAL_CRYP_PHASE_HEADER_OVER = 0x05, /*!< GCM/GMAC(/CMAC)(/CCM) header phase has been carried out */ + HAL_CRYP_PHASE_PAYLOAD_OVER = 0x06, /*!< GCM(/CCM) payload phase has been carried out */ HAL_CRYP_PHASE_FINAL_OVER = 0x07, /*!< GCM/GMAC(/CMAC)(/CCM) final phase has been carried out */ HAL_CRYP_PHASE_HEADER_SUSPENDED = 0x08, /*!< GCM/GMAC(/CMAC)(/CCM) header phase has been suspended */ - HAL_CRYP_PHASE_PAYLOAD_SUSPENDED = 0x09, /*!< GCM(/CCM) payload phase has been suspended */ - HAL_CRYP_PHASE_NOT_USED = 0x0a /*!< Phase is irrelevant to the current chaining mode */ + HAL_CRYP_PHASE_PAYLOAD_SUSPENDED = 0x09, /*!< GCM(/CCM) payload phase has been suspended */ + HAL_CRYP_PHASE_NOT_USED = 0x0a /*!< Phase is irrelevant to the current chaining mode */ }HAL_PhaseTypeDef; -/** +/** * @brief HAL CRYP mode suspend definitions */ typedef enum { HAL_CRYP_SUSPEND_NONE = 0x00, /*!< CRYP peripheral suspension not requested */ - HAL_CRYP_SUSPEND = 0x01 /*!< CRYP peripheral suspension requested */ + HAL_CRYP_SUSPEND = 0x01 /*!< CRYP peripheral suspension requested */ }HAL_SuspendTypeDef; -/** - * @brief HAL CRYP Error Codes definition - */ +/** + * @brief HAL CRYP Error Codes definition + */ #define HAL_CRYP_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ #define HAL_CRYP_WRITE_ERROR ((uint32_t)0x00000001) /*!< Write error */ #define HAL_CRYP_READ_ERROR ((uint32_t)0x00000002) /*!< Read error */ -#define HAL_CRYP_DMA_ERROR ((uint32_t)0x00000004) /*!< DMA error */ -#define HAL_CRYP_BUSY_ERROR ((uint32_t)0x00000008) /*!< Busy flag error */ +#define HAL_CRYP_DMA_ERROR ((uint32_t)0x00000004) /*!< DMA error */ +#define HAL_CRYP_BUSY_ERROR ((uint32_t)0x00000008) /*!< Busy flag error */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) +#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */ +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) +/** + * @brief HAL CRYP common Callback ID enumeration definition + */ +typedef enum +{ + HAL_CRYP_INPUTCPLT_CB_ID = 0x01U, /*!< CRYP input DMA transfer completion callback ID */ + HAL_CRYP_OUTPUTCPLT_CB_ID = 0x02U, /*!< CRYP output DMA transfer completion callback ID */ + HAL_CRYP_COMPCPLT_CB_ID = 0x03U, /*!< CRYP computation completion callback ID */ + HAL_CRYP_ERROR_CB_ID = 0x04U, /*!< CRYP error callback ID */ + HAL_CRYP_MSPINIT_CB_ID = 0x05U, /*!< CRYP MspInit callback ID */ + HAL_CRYP_MSPDEINIT_CB_ID = 0x06U, /*!< CRYP MspDeInit callback ID */ +}HAL_CRYP_CallbackIDTypeDef; +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ -/** +/** * @brief CRYP handle Structure definition - */ -typedef struct + */ +typedef struct __CRYP_HandleTypeDef { AES_TypeDef *Instance; /*!< Register base address */ @@ -159,7 +177,7 @@ typedef struct uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) output buffer */ - uint32_t CrypInCount; /*!< Input data size in bytes or, after suspension, the remaining + uint32_t CrypInCount; /*!< Input data size in bytes or, after suspension, the remaining number of bytes to process */ uint32_t CrypOutCount; /*!< Output data size in bytes */ @@ -176,13 +194,35 @@ typedef struct HAL_LockTypeDef Lock; /*!< CRYP locking object */ __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */ - + __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */ - - HAL_SuspendTypeDef SuspendRequest; /*!< CRYP peripheral suspension request flag */ + + HAL_SuspendTypeDef SuspendRequest; /*!< CRYP peripheral suspension request flag */ + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + void (* InCpltCallback)( struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP input DMA transfer completion callback */ + + void (* OutCpltCallback)( struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP output DMA transfer completion callback */ + + void (* CompCpltCallback)( struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP computation completion callback */ + + void (* ErrorCallback)( struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP error callback */ + + void (* MspInitCallback)( struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp Init callback */ + + void (* MspDeInitCallback)( struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp DeInit callback */ + +#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ }CRYP_HandleTypeDef; -/** + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) +/** + * @brief HAL CRYP Callback pointer definition + */ +typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< pointer to a CRYP common callback functions */ +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ +/** * @} */ @@ -195,8 +235,8 @@ typedef struct /** @defgroup CRYP_Key_Size Key size selection * @{ */ -#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000) /*!< 128-bit long key */ -#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */ +#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000) /*!< 128-bit long key */ +#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */ /** * @} */ @@ -211,19 +251,19 @@ typedef struct /** * @} */ - + /** @defgroup CRYP_AES_State AES Enable state * @{ - */ + */ #define CRYP_AES_DISABLE ((uint32_t)0x00000000) /*!< Disable AES */ #define CRYP_AES_ENABLE AES_CR_EN /*!< Enable AES */ /** * @} - */ - + */ + /** @defgroup CRYP_AES_OperatingMode AES operating mode * @{ - */ + */ #define CRYP_ALGOMODE_ENCRYPT ((uint32_t)0x00000000) /*!< Encryption mode */ #define CRYP_ALGOMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode */ #define CRYP_ALGOMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption */ @@ -231,11 +271,11 @@ typedef struct #define CRYP_ALGOMODE_TAG_GENERATION ((uint32_t)0x00000000) /*!< GMAC or CMAC (when applicable) authentication tag generation */ /** * @} - */ + */ /** @defgroup CRYP_AES_ChainingMode AES chaining mode * @{ - */ + */ #define CRYP_CHAINMODE_AES_ECB ((uint32_t)0x00000000) /*!< Electronic codebook chaining algorithm */ #define CRYP_CHAINMODE_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */ #define CRYP_CHAINMODE_AES_CTR AES_CR_CHMOD_1 /*!< Counter mode chaining algorithm */ @@ -245,19 +285,19 @@ typedef struct #else #define CRYP_CHAINMODE_AES_CMAC AES_CR_CHMOD_2 /*!< Cipher message authentication code */ #endif -/** +/** * @} */ - + /** @defgroup CRYP_Key_Write AES decryption key write-up flag * @{ - */ -#define CRYP_KEY_WRITE_ENABLE ((uint32_t)0x00000000) /*!< Enable decryption key writing */ -#define CRYP_KEY_WRITE_DISABLE ((uint32_t)0x00000001) /*!< Disable decryption key writing */ + */ +#define CRYP_KEY_WRITE_ENABLE ((uint32_t)0x00000000) /*!< Enable decryption key writing */ +#define CRYP_KEY_WRITE_DISABLE ((uint32_t)0x00000001) /*!< Disable decryption key writing */ /** * @} - */ - + */ + /** @defgroup CRYP_DMAIN DMA Input phase management enable state * @{ */ @@ -266,7 +306,7 @@ typedef struct /** * @} */ - + /** @defgroup CRYP_DMAOUT DMA Output phase management enable state * @{ */ @@ -274,22 +314,22 @@ typedef struct #define CRYP_DMAOUT_ENABLE AES_CR_DMAOUTEN /*!< Enable DMA Output phase management */ /** * @} - */ - - + */ + + /** @defgroup CRYP_GCM_CMAC_Phase GCM/GMAC and CCM/CMAC (when applicable) processing phase selection * @{ */ -#define CRYP_GCM_INIT_PHASE ((uint32_t)0x00000000) /*!< GCM/GMAC (or CCM) init phase */ -#define CRYP_GCMCMAC_HEADER_PHASE AES_CR_GCMPH_0 /*!< GCM/GMAC/CCM/CMAC header phase */ -#define CRYP_GCM_PAYLOAD_PHASE AES_CR_GCMPH_1 /*!< GCM/CCM payload phase */ -#define CRYP_GCMCMAC_FINAL_PHASE AES_CR_GCMPH /*!< GCM/GMAC/CCM/CMAC final phase */ -/* Definitions duplication for code readibility's sake: +#define CRYP_GCM_INIT_PHASE ((uint32_t)0x00000000) /*!< GCM/GMAC (or CCM) init phase */ +#define CRYP_GCMCMAC_HEADER_PHASE AES_CR_GCMPH_0 /*!< GCM/GMAC/CCM/CMAC header phase */ +#define CRYP_GCM_PAYLOAD_PHASE AES_CR_GCMPH_1 /*!< GCM/CCM payload phase */ +#define CRYP_GCMCMAC_FINAL_PHASE AES_CR_GCMPH /*!< GCM/GMAC/CCM/CMAC final phase */ +/* Definitions duplication for code readibility's sake: supported or not supported chain modes are not specified for each phase */ -#define CRYP_INIT_PHASE ((uint32_t)0x00000000) /*!< Init phase */ -#define CRYP_HEADER_PHASE AES_CR_GCMPH_0 /*!< Header phase */ -#define CRYP_PAYLOAD_PHASE AES_CR_GCMPH_1 /*!< Payload phase */ -#define CRYP_FINAL_PHASE AES_CR_GCMPH /*!< Final phase */ +#define CRYP_INIT_PHASE ((uint32_t)0x00000000) /*!< Init phase */ +#define CRYP_HEADER_PHASE AES_CR_GCMPH_0 /*!< Header phase */ +#define CRYP_PAYLOAD_PHASE AES_CR_GCMPH_1 /*!< Payload phase */ +#define CRYP_FINAL_PHASE AES_CR_GCMPH /*!< Final phase */ /** * @} */ @@ -305,7 +345,7 @@ typedef struct /** * @} */ - + /** @defgroup CRYP_Clear_Flags AES clearing flags * @{ */ @@ -318,7 +358,7 @@ typedef struct /** @defgroup AES_Interrupts_Enable AES Interrupts Enable bits * @{ - */ + */ #define CRYP_IT_CCFIE AES_CR_CCFIE /*!< Computation Complete interrupt enable */ #define CRYP_IT_ERRIE AES_CR_ERRIE /*!< Error interrupt enable */ /** @@ -348,49 +388,57 @@ typedef struct * @param __HANDLE__: specifies the CRYP handle. * @retval None */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) +#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\ + (__HANDLE__)->State = HAL_CRYP_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + }while(0) +#else #define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET) +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ /** * @brief Enable the CRYP AES peripheral. - * @param __HANDLE__: specifies the CRYP handle. + * @param __HANDLE__: specifies the CRYP handle. * @retval None */ #define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN) /** * @brief Disable the CRYP AES peripheral. - * @param __HANDLE__: specifies the CRYP handle. + * @param __HANDLE__: specifies the CRYP handle. * @retval None */ #define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN) /** * @brief Set the algorithm operating mode. - * @param __HANDLE__: specifies the CRYP handle. + * @param __HANDLE__: specifies the CRYP handle. * @param __OPERATING_MODE__: specifies the operating mode * This parameter can be one of the following values: - * @arg @ref CRYP_ALGOMODE_ENCRYPT encryption - * @arg @ref CRYP_ALGOMODE_KEYDERIVATION key derivation - * @arg @ref CRYP_ALGOMODE_DECRYPT decryption - * @arg @ref CRYP_ALGOMODE_KEYDERIVATION_DECRYPT key derivation and decryption + * @arg @ref CRYP_ALGOMODE_ENCRYPT encryption + * @arg @ref CRYP_ALGOMODE_KEYDERIVATION key derivation + * @arg @ref CRYP_ALGOMODE_DECRYPT decryption + * @arg @ref CRYP_ALGOMODE_KEYDERIVATION_DECRYPT key derivation and decryption * @retval None */ -#define __HAL_CRYP_SET_OPERATINGMODE(__HANDLE__, __OPERATING_MODE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_MODE, (__OPERATING_MODE__)) +#define __HAL_CRYP_SET_OPERATINGMODE(__HANDLE__, __OPERATING_MODE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_MODE, (__OPERATING_MODE__)) /** * @brief Set the algorithm chaining mode. - * @param __HANDLE__: specifies the CRYP handle. + * @param __HANDLE__: specifies the CRYP handle. * @param __CHAINING_MODE__: specifies the chaining mode * This parameter can be one of the following values: - * @arg @ref CRYP_CHAINMODE_AES_ECB Electronic CodeBook - * @arg @ref CRYP_CHAINMODE_AES_CBC Cipher Block Chaining + * @arg @ref CRYP_CHAINMODE_AES_ECB Electronic CodeBook + * @arg @ref CRYP_CHAINMODE_AES_CBC Cipher Block Chaining * @arg @ref CRYP_CHAINMODE_AES_CTR CounTeR mode - * @arg @ref CRYP_CHAINMODE_AES_GCM_GMAC Galois Counter Mode or Galois Message Authentication Code + * @arg @ref CRYP_CHAINMODE_AES_GCM_GMAC Galois Counter Mode or Galois Message Authentication Code * @arg @ref CRYP_CHAINMODE_AES_CMAC Cipher Message Authentication Code (or Counter with Cipher Mode when applicable) * @retval None */ -#define __HAL_CRYP_SET_CHAININGMODE(__HANDLE__, __CHAINING_MODE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_CHMOD, (__CHAINING_MODE__)) +#define __HAL_CRYP_SET_CHAININGMODE(__HANDLE__, __CHAINING_MODE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_CHMOD, (__CHAINING_MODE__)) @@ -398,10 +446,10 @@ typedef struct * @param __HANDLE__: specifies the CRYP handle. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: - * @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden - * @arg @ref CRYP_IT_WRERR Write Error - * @arg @ref CRYP_IT_RDERR Read Error - * @arg @ref CRYP_IT_CCF Computation Complete + * @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden + * @arg @ref CRYP_IT_WRERR Write Error + * @arg @ref CRYP_IT_RDERR Read Error + * @arg @ref CRYP_IT_CCF Computation Complete * @retval The state of __FLAG__ (TRUE or FALSE). */ #define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) @@ -412,7 +460,7 @@ typedef struct * @param __FLAG__: specifies the flag to clear. * This parameter can be one of the following values: * @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear - * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear + * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear * @retval None */ #define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__)) @@ -424,7 +472,7 @@ typedef struct * @param __INTERRUPT__: CRYP interrupt source to check * This parameter can be one of the following values: * @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR) - * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt + * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt * @retval State of interruption (TRUE or FALSE). */ #define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) @@ -434,9 +482,9 @@ typedef struct * @param __HANDLE__: specifies the CRYP handle. * @param __INTERRUPT__: specifies the interrupt to check. * This parameter can be one of the following values: - * @arg @ref CRYP_IT_WRERR Write Error - * @arg @ref CRYP_IT_RDERR Read Error - * @arg @ref CRYP_IT_CCF Computation Complete + * @arg @ref CRYP_IT_WRERR Write Error + * @arg @ref CRYP_IT_RDERR Read Error + * @arg @ref CRYP_IT_CCF Computation Complete * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ #define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__)) @@ -448,19 +496,19 @@ typedef struct * @param __INTERRUPT__: specifies the IT to clear. * This parameter can be one of the following values: * @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear - * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear + * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear * @retval None */ #define __HAL_CRYP_CLEAR_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) /** - * @brief Enable the CRYP interrupt. - * @param __HANDLE__: specifies the CRYP handle. + * @brief Enable the CRYP interrupt. + * @param __HANDLE__: specifies the CRYP handle. * @param __INTERRUPT__: CRYP Interrupt. - * This parameter can be one of the following values: + * This parameter can be one of the following values: * @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR) - * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt + * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt * @retval None */ #define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) @@ -468,11 +516,11 @@ typedef struct /** * @brief Disable the CRYP interrupt. - * @param __HANDLE__: specifies the CRYP handle. + * @param __HANDLE__: specifies the CRYP handle. * @param __INTERRUPT__: CRYP Interrupt. - * This parameter can be one of the following values: + * This parameter can be one of the following values: * @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR) - * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt + * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt * @retval None */ #define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) @@ -488,9 +536,9 @@ typedef struct /** * @brief Verify the key size length. - * @param __KEYSIZE__: Ciphering/deciphering algorithm key size. + * @param __KEYSIZE__: Ciphering/deciphering algorithm key size. * @retval SET (__KEYSIZE__ is a valid value) or RESET (__KEYSIZE__ is invalid) - */ + */ #define IS_CRYP_KEYSIZE(__KEYSIZE__) (((__KEYSIZE__) == CRYP_KEYSIZE_128B) || \ ((__KEYSIZE__) == CRYP_KEYSIZE_256B)) @@ -498,7 +546,7 @@ typedef struct * @brief Verify the input data type. * @param __DATATYPE__: Ciphering/deciphering algorithm input data type. * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid) - */ + */ #define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \ ((__DATATYPE__) == CRYP_DATATYPE_16B) || \ ((__DATATYPE__) == CRYP_DATATYPE_8B) || \ @@ -508,45 +556,45 @@ typedef struct * @brief Verify the CRYP AES IP running mode. * @param __MODE__: CRYP AES IP running mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ + */ #define IS_CRYP_AES(__MODE__) (((__MODE__) == CRYP_AES_DISABLE) || \ - ((__MODE__) == CRYP_AES_ENABLE)) + ((__MODE__) == CRYP_AES_ENABLE)) /** * @brief Verify the selected CRYP algorithm. * @param __ALGOMODE__: Selected CRYP algorithm (ciphering, deciphering, key derivation or a combination of the latter). * @retval SET (__ALGOMODE__ is valid) or RESET (__ALGOMODE__ is invalid) - */ + */ #define IS_CRYP_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == CRYP_ALGOMODE_ENCRYPT) || \ ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION) || \ ((__ALGOMODE__) == CRYP_ALGOMODE_DECRYPT) || \ ((__ALGOMODE__) == CRYP_ALGOMODE_TAG_GENERATION) || \ - ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT)) + ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT)) /** * @brief Verify the selected CRYP chaining algorithm. * @param __CHAINMODE__: Selected CRYP chaining algorithm. * @retval SET (__CHAINMODE__ is valid) or RESET (__CHAINMODE__ is invalid) - */ + */ #if defined(AES_CR_NPBLB) #define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB) || \ ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC) || \ ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR) || \ ((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \ - ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CCM)) + ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CCM)) #else #define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB) || \ ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC) || \ ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR) || \ ((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \ - ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CMAC)) -#endif + ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CMAC)) +#endif /** * @brief Verify the deciphering key write option. * @param __WRITE__: deciphering key write option. * @retval SET (__WRITE__ is valid) or RESET (__WRITE__ is invalid) - */ + */ #define IS_CRYP_WRITE(__WRITE__) (((__WRITE__) == CRYP_KEY_WRITE_ENABLE) || \ ((__WRITE__) == CRYP_KEY_WRITE_DISABLE)) @@ -554,28 +602,28 @@ typedef struct * @brief Verify the CRYP input data DMA mode. * @param __MODE__: CRYP input data DMA mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ + */ #define IS_CRYP_DMAIN(__MODE__) (((__MODE__) == CRYP_DMAIN_DISABLE) || \ - ((__MODE__) == CRYP_DMAIN_ENABLE)) + ((__MODE__) == CRYP_DMAIN_ENABLE)) /** * @brief Verify the CRYP output data DMA mode. * @param __MODE__: CRYP output data DMA mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ + */ #define IS_CRYP_DMAOUT(__MODE__) (((__MODE__) == CRYP_DMAOUT_DISABLE) || \ - ((__MODE__) == CRYP_DMAOUT_ENABLE)) + ((__MODE__) == CRYP_DMAOUT_ENABLE)) /** * @brief Verify the CRYP AES ciphering/deciphering/authentication algorithm phase. * @param __PHASE__: CRYP AES ciphering/deciphering/authentication algorithm phase. * @retval SET (__PHASE__ is valid) or RESET (__PHASE__ is invalid) - */ + */ #define IS_CRYP_GCMCMAC_PHASE(__PHASE__) (((__PHASE__) == CRYP_INIT_PHASE) || \ ((__PHASE__) == CRYP_HEADER_PHASE) || \ ((__PHASE__) == CRYP_PAYLOAD_PHASE) || \ ((__PHASE__) == CRYP_FINAL_PHASE)) - + /** * @} */ @@ -587,11 +635,11 @@ typedef struct /** @addtogroup CRYP_Exported_Functions CRYP Exported Functions * @{ */ - + /** @addtogroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions * @{ */ - + /* Initialization/de-initialization functions ********************************/ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp); HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp); @@ -603,10 +651,10 @@ void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp); /** * @} */ - -/** @addtogroup CRYP_Exported_Functions_Group2 AES processing functions + +/** @addtogroup CRYP_Exported_Functions_Group2 AES processing functions * @{ - */ + */ /* AES encryption/decryption processing functions ****************************/ @@ -637,22 +685,27 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uin /** * @} */ - + /** @addtogroup CRYP_Exported_Functions_Group3 Callback functions * @{ - */ + */ /* CallBack functions ********************************************************/ void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp); void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp); -void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp); - +void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + /** * @} */ - -/** @addtogroup CRYP_Exported_Functions_Group4 CRYP IRQ handler + +/** @addtogroup CRYP_Exported_Functions_Group4 CRYP IRQ handler * @{ - */ + */ /* AES interrupt handling function *******************************************/ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp); @@ -660,8 +713,8 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp); /** * @} */ - -/** @addtogroup CRYP_Exported_Functions_Group5 Peripheral State functions + +/** @addtogroup CRYP_Exported_Functions_Group5 Peripheral State functions * @{ */ @@ -675,18 +728,18 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ - -#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */ - + */ + +#endif /* AES */ + #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp_ex.h index 29485a9dca..a6107ff503 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp_ex.h @@ -31,7 +31,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L4xx_HAL_CRYP_EX_H @@ -41,8 +41,7 @@ extern "C" { #endif -#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - +#if defined(AES) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -53,9 +52,9 @@ /** @addtogroup CRYPEx * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -72,7 +71,7 @@ void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp); /** * @} - */ + */ /** @addtogroup CRYPEx_Exported_Functions_Group2 * @{ @@ -90,7 +89,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI /** * @} - */ + */ /** @addtogroup CRYPEx_Exported_Functions_Group3 * @{ @@ -109,13 +108,13 @@ void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp); /** * @} - */ - + */ + /** * @} - */ - + */ + /* Private functions -----------------------------------------------------------*/ /** @addtogroup CRYPEx_Private_Functions CRYPEx Private Functions * @{ @@ -125,18 +124,18 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp); /** * @} */ - + /** * @} - */ + */ /** * @} - */ - -#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */ - + */ + +#endif /* AES */ + #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac.h index 22441fe0c8..ba2c7951a7 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac.h @@ -44,7 +44,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" - + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ @@ -59,9 +59,9 @@ * @{ */ -/** - * @brief HAL State structures definition - */ +/** + * @brief HAL State structures definition + */ typedef enum { HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */ @@ -69,81 +69,120 @@ typedef enum HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */ HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */ HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */ - + }HAL_DAC_StateTypeDef; - -/** - * @brief DAC handle Structure definition - */ -typedef struct + +/** + * @brief DAC handle Structure definition + */ +typedef struct __DAC_HandleTypeDef { DAC_TypeDef *Instance; /*!< Register base address */ - + __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */ HAL_LockTypeDef Lock; /*!< DAC locking object */ - + DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ - - DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ - + + DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ + __IO uint32_t ErrorCode; /*!< DAC Error code */ - + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac); + void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac); + void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef* hdac); + void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef* hdac); + + void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac); + void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + }DAC_HandleTypeDef; -/** - * @brief DAC Configuration sample and hold Channel structure definition - */ +/** + * @brief DAC Configuration sample and hold Channel structure definition + */ typedef struct { uint32_t DAC_SampleTime ; /*!< Specifies the Sample time for the selected channel. - This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. - This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ + This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. + This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ uint32_t DAC_HoldTime ; /*!< Specifies the hold time for the selected channel - This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. - This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ - + This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. + This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ + uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel - This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. - This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ + This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. + This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ } DAC_SampleAndHoldConfTypeDef; -/** - * @brief DAC Configuration regular Channel structure definition - */ +/** + * @brief DAC Configuration regular Channel structure definition + */ typedef struct { #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) - uint32_t DAC_HighFrequency; /*!< Specifies the frequency interface mode + uint32_t DAC_HighFrequency; /*!< Specifies the frequency interface mode This parameter can be a value of @ref DAC_HighFrequency */ #endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ - + uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode. This parameter can be a value of @ref DAC_SampleAndHold */ - + uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. This parameter can be a value of @ref DAC_trigger_selection */ - + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of @ref DAC_output_buffer */ uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral . This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */ - - uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode - This parameter must be a value of @ref DAC_UserTrimming + + uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode + This parameter must be a value of @ref DAC_UserTrimming DAC_UserTrimming is either factory or user trimming */ - - uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value - i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. + + uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value + i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ - DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */ - + DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */ + }DAC_ChannelConfTypeDef; +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL DAC Callback ID enumeration definition + */ +typedef enum +{ + HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */ + HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */ + HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */ + HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */ + HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */ + HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */ + HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */ + HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */ + HAL_DAC_MSP_INIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */ + HAL_DAC_MSP_DEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */ + HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */ +}HAL_DAC_CallbackIDTypeDef; + +/** + * @brief HAL DAC Callback pointer definition + */ +typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + /** * @} */ @@ -157,11 +196,15 @@ typedef struct /** @defgroup DAC_Error_Code DAC Error Code * @{ */ -#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DMA underrun error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DMA underrun error */ -#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */ -#define HAL_DAC_ERROR_TIMEOUT 0x08 /*!< Timeout error */ +#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */ +#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */ +#define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */ +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + /** * @} */ @@ -171,7 +214,7 @@ typedef struct */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register +#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ @@ -180,17 +223,17 @@ typedef struct #define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ -#endif /* STM32L451xx STM32L452xx STM32L462xx */ - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register +#endif /* STM32L451xx STM32L452xx STM32L462xx */ + +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 |DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ @@ -204,8 +247,8 @@ typedef struct #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register - has been loaded, and not by external trigger */ +#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register + has been loaded, and not by external trigger */ #define DAC_TRIGGER_T1_TRGO ((uint32_t) (DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T2_TRGO ((uint32_t) (DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T4_TRGO ((uint32_t) (DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */ @@ -215,16 +258,16 @@ typedef struct #define DAC_TRIGGER_T8_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T15_TRGO ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_LPTIM1_OUT ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_LPTIM2_OUT ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< LPTIM2 OUT TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_LPTIM2_OUT ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< LPTIM2 OUT TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_EXT_IT9 ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_SOFTWARE ((uint32_t) (DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ #endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ - + /** * @} - */ + */ /** @defgroup DAC_output_buffer DAC output buffer * @{ @@ -235,7 +278,7 @@ typedef struct /** * @} */ - + /** @defgroup DAC_Channel_selection DAC Channel selection * @{ */ @@ -244,7 +287,7 @@ typedef struct defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) #define DAC_CHANNEL_2 ((uint32_t)0x00000010) -#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ +#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ @@ -265,9 +308,9 @@ typedef struct /** @defgroup DAC_flags_definition DAC flags definition * @{ - */ + */ #define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) -#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) +#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) /** * @} @@ -275,14 +318,14 @@ typedef struct /** @defgroup DAC_IT_definition DAC IT definition * @{ - */ + */ #define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) -#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) +#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) /** * @} */ - + /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral * @{ */ @@ -299,10 +342,10 @@ typedef struct #define DAC_TRIMMING_FACTORY ((uint32_t)0x00000000) /*!< Factory trimming */ #define DAC_TRIMMING_USER ((uint32_t)0x00000001) /*!< User trimming */ - + /** * @} - */ + */ /** @defgroup DAC_SampleAndHold DAC power mode * @{ @@ -314,18 +357,18 @@ typedef struct * @} */ #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) -/** @defgroup DAC_HighFrequency DAC high frequency interface mode +/** @defgroup DAC_HighFrequency DAC high frequency interface mode * @{ */ #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE ((uint32_t)0x00000000) /*!< High frequency interface mode disabled */ #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ ((uint32_t)DAC_CR_HFSEL) /*!< High frequency interface mode enabled */ #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC ((uint32_t)0x00000002) /*!< High frequency interface mode automatic */ - + /** * @} */ -#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ - +#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ + /** * @} */ @@ -340,7 +383,15 @@ typedef struct * @param __HANDLE__: specifies the DAC handle. * @retval None */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_DAC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /** @brief Enable the DAC channel. * @param __HANDLE__: specifies the DAC handle. @@ -357,7 +408,7 @@ typedef struct */ #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__))) - + /** @brief Set DHR12R1 alignment. * @param __ALIGNMENT__: specifies the DAC alignment * @retval None @@ -428,7 +479,7 @@ typedef struct /** * @} - */ + */ /* Private macro -------------------------------------------------------------*/ @@ -443,13 +494,13 @@ typedef struct defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ ((CHANNEL) == DAC_CHANNEL_2)) -#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ +#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1) -#endif /* STM32L451xx STM32L452xx STM32L462xx */ +#endif /* STM32L451xx STM32L452xx STM32L462xx */ #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ ((ALIGN) == DAC_ALIGN_12B_L) || \ @@ -462,11 +513,11 @@ typedef struct /** * @} */ - + /* Include DAC HAL Extended module */ -#include "stm32l4xx_hal_dac_ex.h" +#include "stm32l4xx_hal_dac_ex.h" -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup DAC_Exported_Functions * @{ @@ -474,8 +525,8 @@ typedef struct /** @addtogroup DAC_Exported_Functions_Group1 * @{ - */ -/* Initialization and de-initialization functions *****************************/ + */ +/* Initialization and de-initialization functions *****************************/ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac); HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac); void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac); @@ -487,7 +538,7 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac); /** @addtogroup DAC_Exported_Functions_Group2 * @{ - */ + */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel); @@ -502,13 +553,20 @@ void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac); void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac); void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +/* DAC callback registering/unregistering */ +HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + /** * @} */ /** @addtogroup DAC_Exported_Functions_Group3 * @{ - */ + */ /* Peripheral Control functions ***********************************************/ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel); @@ -519,7 +577,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf /** @addtogroup DAC_Exported_Functions_Group4 * @{ - */ + */ /* Peripheral State and Error functions ***************************************/ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac); uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); @@ -535,15 +593,15 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); /** * @} */ - + /** * @} */ - + #ifdef __cplusplus } -#endif - +#endif + #endif /*__STM32L4xx_HAL_DAC_H */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac_ex.h index d642835541..13e1680151 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac_ex.h @@ -43,7 +43,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" - + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ @@ -53,17 +53,17 @@ */ /* Exported types ------------------------------------------------------------*/ - -/** - * @brief HAL State structures definition - */ + +/** + * @brief HAL State structures definition + */ /* Exported constants --------------------------------------------------------*/ /** @defgroup DACEx_Exported_Constants DACEx Exported Constants * @{ - */ - + */ + /** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude * @{ */ @@ -94,7 +94,7 @@ /** * @} - */ + */ /** * @} @@ -107,7 +107,7 @@ /** @defgroup DACEx_Private_Macros DACEx Private Macros * @{ - */ + */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ @@ -117,7 +117,7 @@ ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ @@ -134,7 +134,7 @@ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ - ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) + ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) #endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) @@ -155,9 +155,9 @@ #define IS_DAC_HIGH_FREQUENCY_MODE(MODE) (((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE) || \ ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ) || \ ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC)) - + #endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ - + #define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FF) #define IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FF) @@ -207,7 +207,7 @@ * @} */ -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /* Extended features functions ***********************************************/ /** @addtogroup DACEx_Exported_Functions @@ -216,15 +216,15 @@ /** @addtogroup DACEx_Exported_Functions_Group2 * @{ - */ + */ /* IO operation functions *****************************************************/ - + HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude); HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude); #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ @@ -249,19 +249,19 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_Channe /** @addtogroup DACEx_Exported_Functions_Group3 * @{ - */ + */ /* Peripheral Control functions ***********************************************/ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac); #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel); - + /** * @} */ @@ -300,7 +300,7 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); #ifdef __cplusplus } -#endif +#endif #endif /*__STM32L4xx_HAL_DAC_EX_H */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dcmi.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dcmi.h index 14108e54b0..7f128df3a7 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dcmi.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dcmi.h @@ -31,7 +31,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L4xx_HAL_DCMI_H @@ -41,12 +41,10 @@ extern "C" { #endif -#if defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" +#if defined (DCMI) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -55,15 +53,16 @@ /** @addtogroup DCMI DCMI * @brief DCMI HAL module driver * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup DCMI_Exported_Types DCMI Exported Types * @{ */ -/** + +/** * @brief DCMI Embedded Synchronisation CODE Init structure definition - */ + */ typedef struct { uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */ @@ -73,9 +72,9 @@ typedef struct }DCMI_CodesInitTypeDef; -/** +/** * @brief DCMI Embedded Synchronisation CODE Init structure definition - */ + */ typedef struct { uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */ @@ -85,52 +84,51 @@ typedef struct }DCMI_SyncUnmaskTypeDef; -/** +/** * @brief DCMI Init structure definition - */ + */ typedef struct { uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded. - This parameter can be a value of @ref DCMI_Synchronization_Mode. */ + This parameter can be a value of @ref DCMI_Synchronization_Mode */ uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising. - This parameter can be a value of @ref DCMI_PIXCK_Polarity. */ + This parameter can be a value of @ref DCMI_PIXCK_Polarity */ uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low. - This parameter can be a value of @ref DCMI_VSYNC_Polarity. */ + This parameter can be a value of @ref DCMI_VSYNC_Polarity */ uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low. - This parameter can be a value of @ref DCMI_HSYNC_Polarity. */ + This parameter can be a value of @ref DCMI_HSYNC_Polarity */ uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4. - This parameter can be a value of @ref DCMI_Capture_Rate. */ + This parameter can be a value of @ref DCMI_Capture_Rate */ uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit. - This parameter can be a value of @ref DCMI_Extended_Data_Mode. */ + This parameter can be a value of @ref DCMI_Extended_Data_Mode */ DCMI_CodesInitTypeDef SynchroCode; /*!< Specifies the frame start delimiter codes. */ - uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode. - This parameter can be a value of @ref DCMI_JPEG_Mode. */ - - uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface. - This parameter can be a value of @ref DCMI_Byte_Select_Mode. */ - - uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd. - This parameter can be a value of @ref DCMI_Byte_Select_Start. */ - - uint32_t LineSelectMode; /*!< Specifies the data line to be captured by the interface. - This parameter can be a value of @ref DCMI_Line_Select_Mode. */ - - uint32_t LineSelectStart; /*!< Specifies if the data line to be captured by the interface is even or odd. - This parameter can be a value of @ref DCMI_Line_Select_Start. */ - + uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode. + This parameter can be a value of @ref DCMI_MODE_JPEG */ + + uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface + This parameter can be a value of @ref DCMI_Byte_Select_Mode */ + + uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd + This parameter can be a value of @ref DCMI_Byte_Select_Start */ + + uint32_t LineSelectMode; /*!< Specifies the line of data to be captured by the interface + This parameter can be a value of @ref DCMI_Line_Select_Mode */ + + uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd + This parameter can be a value of @ref DCMI_Line_Select_Start */ }DCMI_InitTypeDef; -/** +/** * @brief HAL DCMI State structures definition - */ + */ typedef enum { HAL_DCMI_STATE_RESET = 0x00U, /*!< DCMI not yet initialized or disabled */ @@ -138,14 +136,14 @@ typedef enum HAL_DCMI_STATE_BUSY = 0x02U, /*!< DCMI internal processing is ongoing */ HAL_DCMI_STATE_TIMEOUT = 0x03U, /*!< DCMI timeout state */ HAL_DCMI_STATE_ERROR = 0x04U, /*!< DCMI error state */ - HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */ + HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */ }HAL_DCMI_StateTypeDef; -/** +/** * @brief DCMI handle Structure definition */ -typedef struct +typedef struct __DCMI_HandleTypeDef { DCMI_TypeDef *Instance; /*!< DCMI Register base address */ @@ -164,17 +162,42 @@ typedef struct DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to DMA handler */ DMA_HandleTypeDef *DMAM2M_Handle; /*!< Pointer to DMA handler for memory to memory copy - (case picture size > maximum DMA transfer length) */ + (case picture size > maximum DMA transfer length) */ __IO uint32_t ErrorCode; /*!< DCMI Error code */ - - uint32_t pCircularBuffer; /*!< Pointer to intermediate copy buffer - (case picture size > maximum DMA transfer length) */ - + + uint32_t pCircularBuffer; /*!< Pointer to intermediate copy buffer + (case picture size > maximum DMA transfer length) */ + uint32_t HalfCopyLength; /*!< Intermediate copies length - (case picture size > maximum DMA transfer length) */ + (case picture size > maximum DMA transfer length) */ + +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) + void (* FrameEventCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Frame Event Callback */ + void (* VsyncEventCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Vsync Event Callback */ + void (* LineEventCallback ) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Line Event Callback */ + void (* ErrorCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Error Callback */ + void (* MspInitCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp Init callback */ + void (* MspDeInitCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp DeInit callback */ +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ }DCMI_HandleTypeDef; + +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) +typedef enum +{ + HAL_DCMI_FRAME_EVENT_CB_ID = 0x00U, /*!< DCMI Frame Event Callback ID */ + HAL_DCMI_VSYNC_EVENT_CB_ID = 0x01U, /*!< DCMI Vsync Event Callback ID */ + HAL_DCMI_LINE_EVENT_CB_ID = 0x02U, /*!< DCMI Line Event Callback ID */ + HAL_DCMI_ERROR_CB_ID = 0x03U, /*!< DCMI Error Callback ID */ + HAL_DCMI_MSPINIT_CB_ID = 0x04U, /*!< DCMI MspInit callback ID */ + HAL_DCMI_MSPDEINIT_CB_ID = 0x05U /*!< DCMI MspDeInit callback ID */ + +}HAL_DCMI_CallbackIDTypeDef; + +typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi); +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ + /** * @} */ @@ -187,21 +210,24 @@ typedef struct /** @defgroup DCMI_Error_Code DCMI Error Code * @{ */ -#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_DCMI_ERROR_OVR ((uint32_t)0x00000001) /*!< Overrun error */ -#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002) /*!< Synchronization error */ -#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ -#define HAL_DCMI_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error */ +#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_DCMI_ERROR_OVR ((uint32_t)0x00000001U) /*!< Overrun error */ +#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002U) /*!< Synchronization error */ +#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ +#define HAL_DCMI_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error */ +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) +#define HAL_DCMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid callback error */ +#endif /** * @} */ /** @defgroup DCMI_Capture_Mode DCMI Capture Mode * @{ - */ -#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000) /*!< The received data are transferred continuously + */ +#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< The received data are transferred continuously into the destination memory through the DMA */ -#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of +#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA */ /** * @} @@ -209,10 +235,10 @@ typedef struct /** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode * @{ - */ -#define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000) /*!< Hardware synchronization data capture (frame/line start/stop) + */ +#define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000U) /*!< Hardware synchronization data capture (frame/line start/stop) is synchronized with the HSYNC/VSYNC signals */ -#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with +#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow */ /** @@ -222,17 +248,17 @@ typedef struct /** @defgroup DCMI_PIXCK_Polarity DCMI Pixel Clock Polarity * @{ */ -#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000) /*!< Pixel clock active on Falling edge */ +#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000U) /*!< Pixel clock active on Falling edge */ #define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */ /** * @} */ - + /** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity * @{ */ -#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Vertical synchronization active Low */ +#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000U) /*!< Vertical synchronization active Low */ #define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */ /** @@ -241,8 +267,8 @@ typedef struct /** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity * @{ - */ -#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Horizontal synchronization active Low */ + */ +#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000U) /*!< Horizontal synchronization active Low */ #define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */ /** @@ -252,7 +278,7 @@ typedef struct /** @defgroup DCMI_JPEG_Mode DCMI JPEG Mode * @{ */ -#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000) /*!< JPEG mode disabled */ +#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000U) /*!< JPEG mode disabled */ #define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< JPEG mode enabled */ /** @@ -262,7 +288,7 @@ typedef struct /** @defgroup DCMI_Capture_Rate DCMI Capture Rate * @{ */ -#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000) /*!< All frames are captured */ +#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000U) /*!< All frames are captured */ #define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */ #define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */ @@ -273,7 +299,7 @@ typedef struct /** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode * @{ */ -#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000) /*!< Interface captures 8-bit data on every pixel clock */ +#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000U) /*!< Interface captures 8-bit data on every pixel clock */ #define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */ #define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */ #define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */ @@ -285,7 +311,7 @@ typedef struct /** @defgroup DCMI_Byte_Select_Mode DCMI Byte Select Mode * @{ */ -#define DCMI_BSM_ALL ((uint32_t)0x00000000) /*!< Interface captures all received data */ +#define DCMI_BSM_ALL ((uint32_t)0x00000000U) /*!< Interface captures all received data */ #define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */ #define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */ #define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */ @@ -296,8 +322,8 @@ typedef struct /** @defgroup DCMI_Byte_Select_Start DCMI Byte Select Start * @{ - */ -#define DCMI_OEBS_ODD ((uint32_t)0x00000000) /*!< Interface captures first data from the frame/line start, second one being dropped */ + */ +#define DCMI_OEBS_ODD ((uint32_t)0x00000000U) /*!< Interface captures first data from the frame/line start, second one being dropped */ #define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */ /** @@ -307,7 +333,7 @@ typedef struct /** @defgroup DCMI_Line_Select_Mode DCMI Line Select Mode * @{ */ -#define DCMI_LSM_ALL ((uint32_t)0x00000000) /*!< Interface captures all received lines */ +#define DCMI_LSM_ALL ((uint32_t)0x00000000U) /*!< Interface captures all received lines */ #define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */ /** @@ -316,8 +342,8 @@ typedef struct /** @defgroup DCMI_Line_Select_Start DCMI Line Select Start * @{ - */ -#define DCMI_OELS_ODD ((uint32_t)0x00000000) /*!< Interface captures first line from the frame start, second one being dropped */ + */ +#define DCMI_OELS_ODD ((uint32_t)0x00000000U) /*!< Interface captures first line from the frame start, second one being dropped */ #define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */ /** @@ -341,57 +367,65 @@ typedef struct * @{ */ -/** +/** * @brief DCMI SR register - */ + */ #define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines) */ #define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */ #define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE) /*!< FIFO not empty flag */ -/** - * @brief DCMI RIS register - */ -#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS) /*!< Capture complete interrupt flag */ -#define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS) /*!< Overrun interrupt flag */ -#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS) /*!< Synchronization error interrupt flag */ -#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS) /*!< VSYNC interrupt flag */ -#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS) /*!< Line interrupt flag */ -/** - * @brief DCMI MIS register - */ -#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Capture complete masked interrupt status */ -#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */ -#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */ -#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */ -#define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS ) /*!< DCMI Line masked interrupt status */ +/** + * @brief DCMI RIS register + */ +#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS) /*!< Capture complete interrupt flag */ +#define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS) /*!< Overrun interrupt flag */ +#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS) /*!< Synchronization error interrupt flag */ +#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS) /*!< VSYNC interrupt flag */ +#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS) /*!< Line interrupt flag */ +/** + * @brief DCMI MIS register + */ +#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Capture complete masked interrupt status */ +#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */ +#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */ +#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */ +#define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS ) /*!< DCMI Line masked interrupt status */ /** * @} - */ + */ /** * @} */ - + /* Exported macro ------------------------------------------------------------*/ /** @defgroup DCMI_Exported_Macros DCMI Exported Macros * @{ */ - + /** @brief Reset DCMI handle state - * @param __HANDLE__: specifies the DCMI handle. + * @param __HANDLE__ specifies the DCMI handle. * @retval None */ +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) +#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_DCMI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET) +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ /** * @brief Enable the DCMI. - * @param __HANDLE__: DCMI handle + * @param __HANDLE__ DCMI handle * @retval None */ #define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE) /** * @brief Disable the DCMI. - * @param __HANDLE__: DCMI handle + * @param __HANDLE__ DCMI handle * @retval None */ #define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE)) @@ -399,22 +433,22 @@ typedef struct /* Interrupt & Flag management */ /** * @brief Get the DCMI pending flag. - * @param __HANDLE__: DCMI handle - * @param __FLAG__: Get the specified flag. + * @param __HANDLE__ DCMI handle + * @param __FLAG__ Get the specified flag. * This parameter can be one of the following values (no combination allowed) - * @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines) - * @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames) - * @arg DCMI_FLAG_FNE: FIFO empty flag + * @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines) + * @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames) + * @arg DCMI_FLAG_FNE: FIFO empty flag * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag * @arg DCMI_FLAG_OVRRI: Overrun flag * @arg DCMI_FLAG_ERRRI: Synchronization error flag * @arg DCMI_FLAG_VSYNCRI: VSYNC flag * @arg DCMI_FLAG_LINERI: Line flag - * @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status - * @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status - * @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status - * @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status - * @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status + * @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status + * @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status + * @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status + * @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status + * @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status * @retval The state of FLAG. */ #define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\ @@ -423,8 +457,8 @@ typedef struct /** * @brief Clear the DCMI pending flag. - * @param __HANDLE__: DCMI handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DCMI handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag * @arg DCMI_FLAG_OVRRI: Overrun flag @@ -437,8 +471,8 @@ typedef struct /** * @brief Enable the specified DCMI interrupts. - * @param __HANDLE__: DCMI handle - * @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. + * @param __HANDLE__ DCMI handle + * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg DCMI_IT_FRAME: Frame capture complete interrupt * @arg DCMI_IT_OVR: Overrun interrupt @@ -451,8 +485,8 @@ typedef struct /** * @brief Disable the specified DCMI interrupts. - * @param __HANDLE__: DCMI handle - * @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. + * @param __HANDLE__ DCMI handle + * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg DCMI_IT_FRAME: Frame capture complete interrupt * @arg DCMI_IT_OVR: Overrun interrupt @@ -464,11 +498,11 @@ typedef struct #define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) /** - * @brief Check whether or not the specified DCMI interrupt has occurred and that the interruption is enabled at the same time. - * @note A bit in MIS register is set if the corresponding enable bit in + * @brief Check whether the specified DCMI interrupt has occurred or not. + * @note A bit in MIS register is set if the corresponding enable bit in * DCMI_IER is set and the corresponding bit in DCMI_RIS is set. - * @param __HANDLE__: DCMI handle - * @param __INTERRUPT__: specifies the DCMI interrupt flag and source to check. + * @param __HANDLE__ DCMI handle + * @param __INTERRUPT__ specifies the DCMI interrupt flag and source to check. * This parameter can be one of the following values: * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask * @arg DCMI_IT_OVR: Overrun interrupt mask @@ -482,29 +516,35 @@ typedef struct /** * @} */ - + /* Exported functions --------------------------------------------------------*/ /** @addtogroup DCMI_Exported_Functions * @{ */ -/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions +/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions * @{ */ - + /* Initialization and de-initialization functions *****************************/ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi); HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi); void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi); void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ /** * @} */ - -/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions + +/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions * @{ */ - + /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length); HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi); @@ -518,8 +558,8 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi); /** * @} */ - -/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions + +/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions * @{ */ /* Peripheral Control functions ***********************************************/ @@ -530,8 +570,8 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_ /** * @} */ - -/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions + +/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions * @{ */ /* Peripheral State functions *************************************************/ @@ -547,71 +587,71 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ /** @addtogroup DCMI_Private_Constants DCMI Private Constants * @{ */ - + /** @defgroup DCMI_Registers_Indices DCMI Registers Indices * @{ - */ -#define DCMI_MIS_INDEX ((uint32_t)0x1000) /*!< DCMI MIS register index */ -#define DCMI_SR_INDEX ((uint32_t)0x2000) /*!< DCMI SR register index */ + */ +#define DCMI_MIS_INDEX ((uint32_t)0x1000U) /*!< DCMI MIS register index */ +#define DCMI_SR_INDEX ((uint32_t)0x2000U) /*!< DCMI SR register index */ /** * @} - */ + */ /** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate * @{ */ -#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFF) /*!< Window coordinate */ +#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFFU) /*!< Window coordinate */ /** * @} */ /** @defgroup DCMI_Window_Height DCMI Window Height * @{ - */ -#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFF) /*!< Window Height */ + */ +#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFFU) /*!< Window Height */ /** * @} */ /** * @} - */ - + */ + /* Private macro -------------------------------------------------------------*/ /** @defgroup DCMI_Private_Macros DCMI Private Macros * @{ */ #define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \ ((MODE) == DCMI_MODE_SNAPSHOT)) - + #define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \ ((MODE) == DCMI_SYNCHRO_EMBEDDED)) - + #define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \ ((POLARITY) == DCMI_PCKPOLARITY_RISING)) - + #define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \ ((POLARITY) == DCMI_VSPOLARITY_HIGH)) - + #define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \ ((POLARITY) == DCMI_HSPOLARITY_HIGH)) - + #define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \ ((JPEG_MODE) == DCMI_JPEG_ENABLE)) - + #define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \ ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \ ((RATE) == DCMI_CR_ALTERNATE_4_FRAME)) - + #define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \ ((DATA) == DCMI_EXTEND_DATA_10B) || \ ((DATA) == DCMI_EXTEND_DATA_12B) || \ ((DATA) == DCMI_EXTEND_DATA_14B)) - + #define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE) #define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT) @@ -620,18 +660,15 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); ((MODE) == DCMI_BSM_OTHER) || \ ((MODE) == DCMI_BSM_ALTERNATE_4) || \ ((MODE) == DCMI_BSM_ALTERNATE_2)) - + #define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \ ((POLARITY) == DCMI_OEBS_EVEN)) - + #define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \ ((MODE) == DCMI_LSM_ALTERNATE_2)) - -#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \ - ((POLARITY) == DCMI_OELS_EVEN)) - -#define IS_DCMI_INTERRUPTS(INTERRUPTS) ((INTERRUPTS) <= DCMI_IER_INT_IE) +#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \ + ((POLARITY) == DCMI_OELS_EVEN)) /** * @} @@ -640,13 +677,12 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); /** * @} */ - + /** * @} - */ + */ -#endif /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* DCMI */ #ifdef __cplusplus } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h index a089d33625..dec652bcc3 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h @@ -71,10 +71,12 @@ typedef enum /* Exported macros -----------------------------------------------------------*/ +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ + #define HAL_MAX_DELAY 0xFFFFFFFFU #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) -#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ do{ \ @@ -82,8 +84,6 @@ typedef enum (__DMA_HANDLE__).Parent = (__HANDLE__); \ } while(0) -#define UNUSED(x) ((void)(x)) - /** @brief Reset the Handle's State field. * @param __HANDLE__: specifies the Peripheral Handle. * @note This macro can be used for the following purpose: diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm.h index b70f9d1c4b..f56cfd0cde 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm.h @@ -34,11 +34,11 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DFSDM_H -#define __STM32L4xx_HAL_DFSDM_H +#ifndef STM32L4xx_HAL_DFSDM_H +#define STM32L4xx_HAL_DFSDM_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ @@ -55,26 +55,26 @@ /** @addtogroup DFSDM * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup DFSDM_Exported_Types DFSDM Exported Types * @{ */ -/** - * @brief HAL DFSDM Channel states definition - */ +/** + * @brief HAL DFSDM Channel states definition + */ typedef enum { HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */ HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */ HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */ -}HAL_DFSDM_Channel_StateTypeDef; +} HAL_DFSDM_Channel_StateTypeDef; -/** - * @brief DFSDM channel output clock structure definition - */ +/** + * @brief DFSDM channel output clock structure definition + */ typedef struct { FunctionalState Activation; /*!< Output clock enable/disable */ @@ -82,11 +82,11 @@ typedef struct This parameter can be a value of @ref DFSDM_Channel_OuputClock */ uint32_t Divider; /*!< Output clock divider. This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ -}DFSDM_Channel_OutputClockTypeDef; +} DFSDM_Channel_OutputClockTypeDef; -/** - * @brief DFSDM channel input structure definition - */ +/** + * @brief DFSDM channel input structure definition + */ typedef struct { uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output. @@ -98,33 +98,33 @@ typedef struct This parameter can be a value of @ref DFSDM_Channel_DataPacking */ uint32_t Pins; /*!< Input pins are taken from same or following channel. This parameter can be a value of @ref DFSDM_Channel_InputPins */ -}DFSDM_Channel_InputTypeDef; +} DFSDM_Channel_InputTypeDef; -/** - * @brief DFSDM channel serial interface structure definition - */ +/** + * @brief DFSDM channel serial interface structure definition + */ typedef struct { uint32_t Type; /*!< SPI or Manchester modes. This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */ uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point). This parameter can be a value of @ref DFSDM_Channel_SpiClock */ -}DFSDM_Channel_SerialInterfaceTypeDef; +} DFSDM_Channel_SerialInterfaceTypeDef; -/** - * @brief DFSDM channel analog watchdog structure definition - */ +/** + * @brief DFSDM channel analog watchdog structure definition + */ typedef struct { uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order. This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */ uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio. This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ -}DFSDM_Channel_AwdTypeDef; +} DFSDM_Channel_AwdTypeDef; -/** - * @brief DFSDM channel init structure definition - */ +/** + * @brief DFSDM channel init structure definition + */ typedef struct { DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */ @@ -135,21 +135,45 @@ typedef struct This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ uint32_t RightBitShift; /*!< DFSDM channel right bit shift. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ -}DFSDM_Channel_InitTypeDef; +} DFSDM_Channel_InitTypeDef; -/** - * @brief DFSDM channel handle structure definition - */ -typedef struct +/** + * @brief DFSDM channel handle structure definition + */ +typedef struct __DFSDM_Channel_HandleTypeDef { DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */ DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */ HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */ -}DFSDM_Channel_HandleTypeDef; +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + void (*CkabCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel clock absence detection callback */ + void (*ScdCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel short circuit detection callback */ + void (*MspInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */ + void (*MspDeInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP de-init callback */ +#endif +} DFSDM_Channel_HandleTypeDef; -/** - * @brief HAL DFSDM Filter states definition - */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) +/** + * @brief DFSDM channel callback ID enumeration definition + */ +typedef enum +{ + HAL_DFSDM_CHANNEL_CKAB_CB_ID = 0x00U, /*!< DFSDM channel clock absence detection callback ID */ + HAL_DFSDM_CHANNEL_SCD_CB_ID = 0x01U, /*!< DFSDM channel short circuit detection callback ID */ + HAL_DFSDM_CHANNEL_MSPINIT_CB_ID = 0x02U, /*!< DFSDM channel MSP init callback ID */ + HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U /*!< DFSDM channel MSP de-init callback ID */ +} HAL_DFSDM_Channel_CallbackIDTypeDef; + +/** + * @brief DFSDM channel callback pointer definition + */ +typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); +#endif + +/** + * @brief HAL DFSDM Filter states definition + */ typedef enum { HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */ @@ -158,22 +182,22 @@ typedef enum HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */ HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */ HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */ -}HAL_DFSDM_Filter_StateTypeDef; +} HAL_DFSDM_Filter_StateTypeDef; -/** - * @brief DFSDM filter regular conversion parameters structure definition - */ +/** + * @brief DFSDM filter regular conversion parameters structure definition + */ typedef struct { uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous. This parameter can be a value of @ref DFSDM_Filter_Trigger */ FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */ FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */ -}DFSDM_Filter_RegularParamTypeDef; +} DFSDM_Filter_RegularParamTypeDef; -/** - * @brief DFSDM filter injected conversion parameters structure definition - */ +/** + * @brief DFSDM filter injected conversion parameters structure definition + */ typedef struct { uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous. @@ -184,11 +208,11 @@ typedef struct This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */ uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both. This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */ -}DFSDM_Filter_InjectedParamTypeDef; +} DFSDM_Filter_InjectedParamTypeDef; -/** - * @brief DFSDM filter parameters structure definition - */ +/** + * @brief DFSDM filter parameters structure definition + */ typedef struct { uint32_t SincOrder; /*!< Sinc filter order. @@ -197,22 +221,22 @@ typedef struct This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ uint32_t IntOversampling; /*!< Integrator oversampling ratio. This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ -}DFSDM_Filter_FilterParamTypeDef; +} DFSDM_Filter_FilterParamTypeDef; -/** - * @brief DFSDM filter init structure definition - */ +/** + * @brief DFSDM filter init structure definition + */ typedef struct { DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */ DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */ DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */ -}DFSDM_Filter_InitTypeDef; +} DFSDM_Filter_InitTypeDef; -/** - * @brief DFSDM filter handle structure definition - */ -typedef struct +/** + * @brief DFSDM filter handle structure definition + */ +typedef struct __DFSDM_Filter_HandleTypeDef { DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */ DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */ @@ -226,12 +250,23 @@ typedef struct uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */ uint32_t InjConvRemaining; /*!< Injected conversions remaining */ HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */ - uint32_t ErrorCode; /*!< DFSDM filter error code */ -}DFSDM_Filter_HandleTypeDef; + uint32_t ErrorCode; /*!< DFSDM filter error code */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + void (*AwdCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */ + void (*RegConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter regular conversion complete callback */ + void (*RegConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half regular conversion complete callback */ + void (*InjConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter injected conversion complete callback */ + void (*InjConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half injected conversion complete callback */ + void (*ErrorCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter error callback */ + void (*MspInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP init callback */ + void (*MspDeInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP de-init callback */ +#endif +} DFSDM_Filter_HandleTypeDef; -/** - * @brief DFSDM filter analog watchdog parameters structure definition - */ +/** + * @brief DFSDM filter analog watchdog parameters structure definition + */ typedef struct { uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter. @@ -246,11 +281,33 @@ typedef struct This parameter can be a values combination of @ref DFSDM_BreakSignals */ uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event. This parameter can be a values combination of @ref DFSDM_BreakSignals */ -}DFSDM_Filter_AwdParamTypeDef; +} DFSDM_Filter_AwdParamTypeDef; + +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) +/** + * @brief DFSDM filter callback ID enumeration definition + */ +typedef enum +{ + HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID = 0x00U, /*!< DFSDM filter regular conversion complete callback ID */ + HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, /*!< DFSDM filter half regular conversion complete callback ID */ + HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID = 0x02U, /*!< DFSDM filter injected conversion complete callback ID */ + HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U, /*!< DFSDM filter half injected conversion complete callback ID */ + HAL_DFSDM_FILTER_ERROR_CB_ID = 0x04U, /*!< DFSDM filter error callback ID */ + HAL_DFSDM_FILTER_MSPINIT_CB_ID = 0x05U, /*!< DFSDM filter MSP init callback ID */ + HAL_DFSDM_FILTER_MSPDEINIT_CB_ID = 0x06U /*!< DFSDM filter MSP de-init callback ID */ +} HAL_DFSDM_Filter_CallbackIDTypeDef; + +/** + * @brief DFSDM filter callback pointer definition + */ +typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); +#endif /** * @} - */ + */ /* End of exported types -----------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ @@ -261,7 +318,7 @@ typedef struct /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection * @{ */ -#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U) /*!< Source for ouput clock is system clock */ +#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */ #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */ /** * @} @@ -270,7 +327,7 @@ typedef struct /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer * @{ */ -#define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */ +#define DFSDM_CHANNEL_EXTERNAL_INPUTS 0x00000000U /*!< Data are taken from external inputs */ #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ defined(STM32L496xx) || defined(STM32L4A6xx) || \ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) @@ -284,7 +341,7 @@ typedef struct /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing * @{ */ -#define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000U) /*!< Standard data packing mode */ +#define DFSDM_CHANNEL_STANDARD_MODE 0x00000000U /*!< Standard data packing mode */ #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */ #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */ /** @@ -294,7 +351,7 @@ typedef struct /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins * @{ */ -#define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000U) /*!< Input from pins on same channel */ +#define DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U /*!< Input from pins on same channel */ #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */ /** * @} @@ -303,7 +360,7 @@ typedef struct /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type * @{ */ -#define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000U) /*!< SPI with rising edge */ +#define DFSDM_CHANNEL_SPI_RISING 0x00000000U /*!< SPI with rising edge */ #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */ #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */ #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */ @@ -314,7 +371,7 @@ typedef struct /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection * @{ */ -#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000U) /*!< External SPI clock */ +#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U /*!< External SPI clock */ #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */ #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */ #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */ @@ -325,7 +382,7 @@ typedef struct /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order * @{ */ -#define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */ +#define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */ #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */ #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */ @@ -336,9 +393,9 @@ typedef struct /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger * @{ */ -#define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000U) /*!< Software trigger */ -#define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U) /*!< Synchronous with DFSDM_FLT0 */ -#define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002U) /*!< External trigger (only for injected conversion) */ +#define DFSDM_FILTER_SW_TRIGGER 0x00000000U /*!< Software trigger */ +#define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */ +#define DFSDM_FILTER_EXT_TRIGGER 0x00000002U /*!< External trigger (only for injected conversion) */ /** * @} */ @@ -347,7 +404,7 @@ typedef struct * @{ */ #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) -#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */ +#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */ @@ -355,7 +412,7 @@ typedef struct #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */ #elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For all DFSDM filters */ #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For all DFSDM filters */ #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For all DFSDM filters */ #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */ @@ -371,7 +428,7 @@ typedef struct #define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \ DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ #else -#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */ +#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */ @@ -400,7 +457,7 @@ typedef struct /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order * @{ */ -#define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */ +#define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */ #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */ #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */ @@ -413,7 +470,7 @@ typedef struct /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source * @{ */ -#define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000U) /*!< From digital filter */ +#define DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U /*!< From digital filter */ #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */ /** * @} @@ -421,11 +478,14 @@ typedef struct /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code * @{ - */ -#define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001U) /*!< Overrun occurs during regular conversion */ -#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U) /*!< Overrun occurs during injected conversion */ -#define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003U) /*!< DMA error occurs */ + */ +#define DFSDM_FILTER_ERROR_NONE 0x00000000U /*!< No error */ +#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /*!< Overrun occurs during regular conversion */ +#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */ +#define DFSDM_FILTER_ERROR_DMA 0x00000003U /*!< DMA error occurs */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) +#define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid callback error occurs */ +#endif /** * @} */ @@ -433,11 +493,11 @@ typedef struct /** @defgroup DFSDM_BreakSignals DFSDM break signals * @{ */ -#define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U) /*!< No break signal */ -#define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001U) /*!< Break signal 0 */ -#define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002U) /*!< Break signal 1 */ -#define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004U) /*!< Break signal 2 */ -#define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008U) /*!< Break signal 3 */ +#define DFSDM_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */ +#define DFSDM_BREAK_SIGNAL_0 0x00000001U /*!< Break signal 0 */ +#define DFSDM_BREAK_SIGNAL_1 0x00000002U /*!< Break signal 1 */ +#define DFSDM_BREAK_SIGNAL_2 0x00000004U /*!< Break signal 2 */ +#define DFSDM_BREAK_SIGNAL_3 0x00000008U /*!< Break signal 3 */ /** * @} */ @@ -451,22 +511,22 @@ typedef struct - in 16-bit MSB the channel number is set e.g. for channel 5 definition: - the channel mask is 0x00000020 (bit 5 is set) - - the channel number 5 is 0x00050000 + - the channel number 5 is 0x00050000 --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */ #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) -#define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U) -#define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U) -#define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U) -#define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U) +#define DFSDM_CHANNEL_0 0x00000001U +#define DFSDM_CHANNEL_1 0x00010002U +#define DFSDM_CHANNEL_2 0x00020004U +#define DFSDM_CHANNEL_3 0x00030008U #else -#define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U) -#define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U) -#define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U) -#define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U) -#define DFSDM_CHANNEL_4 ((uint32_t)0x00040010U) -#define DFSDM_CHANNEL_5 ((uint32_t)0x00050020U) -#define DFSDM_CHANNEL_6 ((uint32_t)0x00060040U) -#define DFSDM_CHANNEL_7 ((uint32_t)0x00070080U) +#define DFSDM_CHANNEL_0 0x00000001U +#define DFSDM_CHANNEL_1 0x00010002U +#define DFSDM_CHANNEL_2 0x00020004U +#define DFSDM_CHANNEL_3 0x00030008U +#define DFSDM_CHANNEL_4 0x00040010U +#define DFSDM_CHANNEL_5 0x00050020U +#define DFSDM_CHANNEL_6 0x00060040U +#define DFSDM_CHANNEL_7 0x00070080U #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ /** * @} @@ -475,8 +535,8 @@ typedef struct /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode * @{ */ -#define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000U) /*!< Conversion are not continuous */ -#define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001U) /*!< Conversion are continuous */ +#define DFSDM_CONTINUOUS_CONV_OFF 0x00000000U /*!< Conversion are not continuous */ +#define DFSDM_CONTINUOUS_CONV_ON 0x00000001U /*!< Conversion are continuous */ /** * @} */ @@ -484,15 +544,15 @@ typedef struct /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold * @{ */ -#define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000U) /*!< Analog watchdog high threshold */ -#define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001U) /*!< Analog watchdog low threshold */ +#define DFSDM_AWD_HIGH_THRESHOLD 0x00000000U /*!< Analog watchdog high threshold */ +#define DFSDM_AWD_LOW_THRESHOLD 0x00000001U /*!< Analog watchdog low threshold */ /** * @} */ /** * @} - */ + */ /* End of exported constants -------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/ @@ -504,13 +564,29 @@ typedef struct * @param __HANDLE__ DFSDM channel handle. * @retval None */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) +#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) +#endif /** @brief Reset DFSDM filter handle state. * @param __HANDLE__ DFSDM filter handle. * @retval None */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) +#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) +#endif /** * @} @@ -535,6 +611,15 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); + +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) +/* Channel callbacks register/unregister functions ****************************/ +HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, + HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID, + pDFSDM_Channel_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, + HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID); +#endif /** * @} */ @@ -582,6 +667,18 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); + +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) +/* Filter callbacks register/unregister functions ****************************/ +HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID, + pDFSDM_Filter_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + pDFSDM_Filter_AwdCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +#endif /** * @} */ @@ -618,15 +715,15 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsd HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - DFSDM_Filter_AwdParamTypeDef* awdParam); + DFSDM_Filter_AwdParamTypeDef *awdParam); HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); -int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); -int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); -int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); +int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); +int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); +int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); +int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); @@ -665,7 +762,7 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe */ #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \ ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) -#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256)) +#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U)) #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ defined(STM32L496xx) || defined(STM32L4A6xx) || \ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) @@ -676,8 +773,8 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +/* STM32L496xx || STM32L4A6xx || */ +/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \ ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \ ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) @@ -695,10 +792,10 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \ ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \ ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER)) -#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32)) +#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 32U)) #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) -#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F) -#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF) +#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU) +#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU) #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER)) #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ @@ -747,8 +844,8 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \ ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \ ((ORDER) == DFSDM_FILTER_SINC5_ORDER)) -#define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024)) -#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256)) +#define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 1024U)) +#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 256U)) #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \ ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA)) #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) @@ -758,7 +855,7 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe ((CHANNEL) == DFSDM_CHANNEL_1) || \ ((CHANNEL) == DFSDM_CHANNEL_2) || \ ((CHANNEL) == DFSDM_CHANNEL_3)) -#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x0003000FU)) +#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU)) #else #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ ((CHANNEL) == DFSDM_CHANNEL_1) || \ @@ -768,31 +865,31 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe ((CHANNEL) == DFSDM_CHANNEL_5) || \ ((CHANNEL) == DFSDM_CHANNEL_6) || \ ((CHANNEL) == DFSDM_CHANNEL_7)) -#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU)) +#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU)) #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \ ((MODE) == DFSDM_CONTINUOUS_CONV_ON)) /** * @} - */ + */ /* End of private macros -----------------------------------------------------*/ /** * @} - */ + */ /** * @} */ #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ +/* STM32L496xx || STM32L4A6xx || */ +/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_HAL_DFSDM_H */ +#endif /* STM32L4xx_HAL_DFSDM_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm_ex.h index c05990cece..7d0a7c2a12 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm_ex.h @@ -31,21 +31,21 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DFSDM_EX_H -#define __STM32L4xx_HAL_DFSDM_EX_H +#ifndef STM32L4xx_HAL_DFSDM_EX_H +#define STM32L4xx_HAL_DFSDM_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" - + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ @@ -68,15 +68,15 @@ */ HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue); -HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t* PulsesValue); +HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue); /** * @} - */ + */ /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ @@ -88,11 +88,11 @@ HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeD /** * @} - */ + */ /** * @} - */ + */ /** * @} @@ -104,6 +104,6 @@ HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeD } #endif -#endif /* __STM32L4xx_HAL_DFSDM_EX_H */ +#endif /* STM32L4xx_HAL_DFSDM_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h index 6fdad2f067..0aa5c85b2e 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h @@ -95,10 +95,10 @@ typedef struct */ typedef enum { - HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ - HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */ - HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ - HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ }HAL_DMA_StateTypeDef; /** @@ -106,8 +106,8 @@ typedef enum */ typedef enum { - HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ - HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ }HAL_DMA_LevelCompleteTypeDef; @@ -116,12 +116,11 @@ typedef enum */ typedef enum { - HAL_DMA_XFER_CPLT_CB_ID = 0x00, /*!< Full transfer */ - HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01, /*!< Half transfer */ - HAL_DMA_XFER_ERROR_CB_ID = 0x02, /*!< Error */ - HAL_DMA_XFER_ABORT_CB_ID = 0x03, /*!< Abort */ - HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */ - + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ }HAL_DMA_CallbackIDTypeDef; /** @@ -169,6 +168,7 @@ typedef struct __DMA_HandleTypeDef #endif /* DMAMUX1 */ }DMA_HandleTypeDef; + /** * @} */ @@ -182,13 +182,13 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Error_Code DMA Error Code * @{ */ -#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ -#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U) /*!< Abort requested with no Xfer ongoing */ -#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ -#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */ -#define HAL_DMA_ERROR_SYNC ((uint32_t)0x00000200U) /*!< DMAMUX sync overrun error */ -#define HAL_DMA_ERROR_REQGEN ((uint32_t)0x00000400U) /*!< DMAMUX request generator overrun error */ +#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ +#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ +#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ +#define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ +#define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ /** * @} @@ -199,14 +199,14 @@ typedef struct __DMA_HandleTypeDef */ #if !defined (DMAMUX1) -#define DMA_REQUEST_0 ((uint32_t)0x00000000) -#define DMA_REQUEST_1 ((uint32_t)0x00000001) -#define DMA_REQUEST_2 ((uint32_t)0x00000002) -#define DMA_REQUEST_3 ((uint32_t)0x00000003) -#define DMA_REQUEST_4 ((uint32_t)0x00000004) -#define DMA_REQUEST_5 ((uint32_t)0x00000005) -#define DMA_REQUEST_6 ((uint32_t)0x00000006) -#define DMA_REQUEST_7 ((uint32_t)0x00000007) +#define DMA_REQUEST_0 0U +#define DMA_REQUEST_1 1U +#define DMA_REQUEST_2 2U +#define DMA_REQUEST_3 3U +#define DMA_REQUEST_4 4U +#define DMA_REQUEST_5 5U +#define DMA_REQUEST_6 6U +#define DMA_REQUEST_7 7U #endif @@ -339,9 +339,9 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction * @{ */ -#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ -#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ -#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ +#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ /** * @} */ @@ -349,8 +349,8 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode * @{ */ -#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ -#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */ +#define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */ +#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ /** * @} */ @@ -358,8 +358,8 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode * @{ */ -#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ -#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ +#define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */ +#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ /** * @} */ @@ -701,7 +701,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ ((STATE) == DMA_PINC_DISABLE)) diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma2d.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma2d.h index a66c2c4142..72be0fbde5 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma2d.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma2d.h @@ -31,19 +31,17 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DMA2D_H -#define __STM32L4xx_HAL_DMA2D_H +#ifndef STM32L4xx_HAL_DMA2D_H +#define STM32L4xx_HAL_DMA2D_H #ifdef __cplusplus extern "C" { #endif -#if defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - +#if defined (DMA2D) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -60,9 +58,9 @@ /** @defgroup DMA2D_Exported_Types DMA2D Exported Types * @{ */ -#define MAX_DMA2D_LAYER 2U +#define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */ -/** +/** * @brief DMA2D color Structure definition */ typedef struct @@ -77,7 +75,7 @@ typedef struct This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ } DMA2D_ColorTypeDef; -/** +/** * @brief DMA2D CLUT Structure definition */ typedef struct @@ -87,11 +85,11 @@ typedef struct uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. This parameter can be one value of @ref DMA2D_CLUT_CM. */ - uint32_t Size; /*!< Configures the DMA2D CLUT size. + uint32_t Size; /*!< Configures the DMA2D CLUT size. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ } DMA2D_CLUTCfgTypeDef; -/** +/** * @brief DMA2D Init structure definition */ typedef struct @@ -102,29 +100,30 @@ typedef struct uint32_t ColorMode; /*!< Configures the color format of the output image. This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ - uint32_t OutputOffset; /*!< Specifies the Offset value. + uint32_t OutputOffset; /*!< Specifies the Offset value. This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ - uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter. This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ - + uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR) for the output pixel format converter. - This parameter can be one value of @ref DMA2D_RB_Swap. */ + This parameter can be one value of @ref DMA2D_RB_Swap. */ + -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) uint32_t BytesSwap; /*!< Select byte regular mode or bytes swap mode (two by two). This parameter can be one value of @ref DMA2D_Bytes_Swap. */ +#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ - uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset for the foreground, background and output. +#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) + uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset for the foreground, background and output. This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */ - -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ } DMA2D_InitTypeDef; -/** +/** * @brief DMA2D Layer structure definition */ typedef struct @@ -132,29 +131,30 @@ typedef struct uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ - uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. + uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ - uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. + uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. This parameter can be one value of @ref DMA2D_Alpha_Mode. */ - uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode. + uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below. - @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between - Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where + @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between + Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where - InputAlpha[24:31] is the alpha value ALPHA[0:7] - InputAlpha[16:23] is the red value RED[0:7] - InputAlpha[8:15] is the green value GREEN[0:7] - InputAlpha[0:7] is the blue value BLUE[0:7]. */ - uint32_t AlphaInverted; /*!< Select regular or inverted alpha value. This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ - + uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR). This parameter can be one value of @ref DMA2D_RB_Swap. */ + + } DMA2D_LayerCfgTypeDef; -/** +/** * @brief HAL DMA2D State structures definition */ typedef enum @@ -167,27 +167,45 @@ typedef enum HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ }HAL_DMA2D_StateTypeDef; -/** +/** * @brief DMA2D handle Structure definition */ typedef struct __DMA2D_HandleTypeDef { DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ - + DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */ - - void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */ - - DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ - HAL_LockTypeDef Lock; /*!< DMA2D lock. */ - + void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */ + +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) + void (* LineEventCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D line event callback. */ + + void (* CLUTLoadingCpltCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D CLUT loading completion callback. */ + + void (* MspInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp Init callback. */ + + void (* MspDeInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp DeInit callback. */ + +#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ + + DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ + + HAL_LockTypeDef Lock; /*!< DMA2D lock. */ + __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ - - __IO uint32_t ErrorCode; /*!< DMA2D error code. */ + + __IO uint32_t ErrorCode; /*!< DMA2D error code. */ } DMA2D_HandleTypeDef; + +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +/** + * @brief HAL DMA2D Callback pointer definition + */ +typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Pointer to a DMA2D common callback function */ +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ /** * @} */ @@ -200,34 +218,38 @@ typedef struct __DMA2D_HandleTypeDef /** @defgroup DMA2D_Error_Code DMA2D Error Code * @{ */ -#define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ -#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002U) /*!< Configuration error */ -#define HAL_DMA2D_ERROR_CAE ((uint32_t)0x00000004U) /*!< CLUT access error */ -#define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ +#define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */ +#define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */ +#define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */ +#define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +#define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + /** * @} */ -/** @defgroup DMA2D_Mode DMA2D Mode +/** @defgroup DMA2D_Mode DMA2D Mode * @{ */ -#define DMA2D_M2M ((uint32_t)0x00000000U) /*!< DMA2D memory to memory transfer mode */ +#define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ #define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ #define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT) #define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */ #define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */ -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT */ /** * @} */ -/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode +/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode * @{ */ -#define DMA2D_OUTPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D color mode */ +#define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */ #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ @@ -239,17 +261,17 @@ typedef struct __DMA2D_HandleTypeDef /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode * @{ */ -#define DMA2D_INPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 color mode */ -#define DMA2D_INPUT_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 color mode */ -#define DMA2D_INPUT_RGB565 ((uint32_t)0x00000002U) /*!< RGB565 color mode */ -#define DMA2D_INPUT_ARGB1555 ((uint32_t)0x00000003U) /*!< ARGB1555 color mode */ -#define DMA2D_INPUT_ARGB4444 ((uint32_t)0x00000004U) /*!< ARGB4444 color mode */ -#define DMA2D_INPUT_L8 ((uint32_t)0x00000005U) /*!< L8 color mode */ -#define DMA2D_INPUT_AL44 ((uint32_t)0x00000006U) /*!< AL44 color mode */ -#define DMA2D_INPUT_AL88 ((uint32_t)0x00000007U) /*!< AL88 color mode */ -#define DMA2D_INPUT_L4 ((uint32_t)0x00000008U) /*!< L4 color mode */ -#define DMA2D_INPUT_A8 ((uint32_t)0x00000009U) /*!< A8 color mode */ -#define DMA2D_INPUT_A4 ((uint32_t)0x0000000AU) /*!< A4 color mode */ +#define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */ +#define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */ +#define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */ +#define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */ +#define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */ +#define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */ +#define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */ +#define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */ +#define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */ +#define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */ +#define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */ /** * @} */ @@ -257,19 +279,19 @@ typedef struct __DMA2D_HandleTypeDef /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode * @{ */ -#define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */ -#define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001U) /*!< Replace original alpha channel value by programmed alpha value */ -#define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002U) /*!< Replace original alpha channel value by programmed alpha value +#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ +#define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ +#define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value with original alpha channel value */ /** * @} - */ + */ /** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion * @{ */ -#define DMA2D_REGULAR_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */ -#define DMA2D_INVERTED_ALPHA ((uint32_t)0x00000001U) /*!< Invert the alpha channel value */ +#define DMA2D_REGULAR_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ +#define DMA2D_INVERTED_ALPHA 0x00000001U /*!< Invert the alpha channel value */ /** * @} */ @@ -277,43 +299,47 @@ typedef struct __DMA2D_HandleTypeDef /** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap * @{ */ -#define DMA2D_RB_REGULAR ((uint32_t)0x00000000U) /*!< Select regular mode (RGB or ARGB) */ -#define DMA2D_RB_SWAP ((uint32_t)0x00000001U) /*!< Select swap mode (BGR or ABGR) */ +#define DMA2D_RB_REGULAR 0x00000000U /*!< Select regular mode (RGB or ARGB) */ +#define DMA2D_RB_SWAP 0x00000001U /*!< Select swap mode (BGR or ABGR) */ /** * @} - */ + */ + -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + +#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) /** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode * @{ */ -#define DMA2D_LOM_PIXELS ((uint32_t)0x00000000U) /*!< Line offsets expressed in pixels */ -#define DMA2D_LOM_BYTES DMA2D_CR_LOM /*!< Line offsets expressed in bytes */ +#define DMA2D_LOM_PIXELS 0x00000000U /*!< Line offsets expressed in pixels */ +#define DMA2D_LOM_BYTES DMA2D_CR_LOM /*!< Line offsets expressed in bytes */ /** * @} */ +#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ +#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) /** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap * @{ */ -#define DMA2D_BYTES_REGULAR ((uint32_t)0x00000000U) /*!< Bytes in regular order in output FIFO */ -#define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB /*!< Bytes are swapped two by two in output FIFO */ +#define DMA2D_BYTES_REGULAR 0x00000000U /*!< Bytes in regular order in output FIFO */ +#define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB /*!< Bytes are swapped two by two in output FIFO */ /** * @} - */ + */ +#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode * @{ */ -#define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D CLUT color mode */ -#define DMA2D_CCM_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 DMA2D CLUT color mode */ +#define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */ +#define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */ /** * @} */ -/** @defgroup DMA2D_Interrupts DMA2D Interrupts +/** @defgroup DMA2D_Interrupts DMA2D Interrupts * @{ */ #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ @@ -322,13 +348,13 @@ typedef struct __DMA2D_HandleTypeDef #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ -/** - * @} - */ - -/** @defgroup DMA2D_Flags DMA2D Flags - * @{ - */ +/** + * @} + */ + +/** @defgroup DMA2D_Flags DMA2D Flags + * @{ + */ #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ @@ -338,7 +364,7 @@ typedef struct __DMA2D_HandleTypeDef /** * @} */ - + /** @defgroup DMA2D_Aliases DMA2D API Aliases * @{ */ @@ -346,8 +372,23 @@ typedef struct __DMA2D_HandleTypeDef /** * @} */ - - + +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +/** + * @brief HAL DMA2D common Callback ID enumeration definition + */ +typedef enum +{ + HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */ + HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */ + HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */ + HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */ + HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */ + HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */ +}HAL_DMA2D_CallbackIDTypeDef; +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ + + /** * @} */ @@ -357,14 +398,23 @@ typedef struct __DMA2D_HandleTypeDef */ /** @brief Reset DMA2D handle state - * @param __HANDLE__: specifies the DMA2D handle. + * @param __HANDLE__ specifies the DMA2D handle. * @retval None */ +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + }while(0) +#else #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ + /** * @brief Enable the DMA2D. - * @param __HANDLE__: DMA2D handle + * @param __HANDLE__ DMA2D handle * @retval None. */ #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) @@ -373,38 +423,38 @@ typedef struct __DMA2D_HandleTypeDef /* Interrupt & Flag management */ /** * @brief Get the DMA2D pending flags. - * @param __HANDLE__: DMA2D handle - * @param __FLAG__: flag to check. + * @param __HANDLE__ DMA2D handle + * @param __FLAG__ flag to check. * This parameter can be any combination of the following values: * @arg DMA2D_FLAG_CE: Configuration error flag * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag * @arg DMA2D_FLAG_CAE: CLUT access error flag * @arg DMA2D_FLAG_TW: Transfer Watermark flag * @arg DMA2D_FLAG_TC: Transfer complete flag - * @arg DMA2D_FLAG_TE: Transfer error flag + * @arg DMA2D_FLAG_TE: Transfer error flag * @retval The state of FLAG. */ #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) /** * @brief Clear the DMA2D pending flags. - * @param __HANDLE__: DMA2D handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DMA2D handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA2D_FLAG_CE: Configuration error flag * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag * @arg DMA2D_FLAG_CAE: CLUT access error flag * @arg DMA2D_FLAG_TW: Transfer Watermark flag * @arg DMA2D_FLAG_TC: Transfer complete flag - * @arg DMA2D_FLAG_TE: Transfer error flag + * @arg DMA2D_FLAG_TE: Transfer error flag * @retval None */ #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) /** * @brief Enable the specified DMA2D interrupts. - * @param __HANDLE__: DMA2D handle - * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg DMA2D_IT_CE: Configuration error interrupt mask * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask @@ -418,8 +468,8 @@ typedef struct __DMA2D_HandleTypeDef /** * @brief Disable the specified DMA2D interrupts. - * @param __HANDLE__: DMA2D handle - * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg DMA2D_IT_CE: Configuration error interrupt mask * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask @@ -433,8 +483,8 @@ typedef struct __DMA2D_HandleTypeDef /** * @brief Check whether the specified DMA2D interrupt source is enabled or not. - * @param __HANDLE__: DMA2D handle - * @param __INTERRUPT__: specifies the DMA2D interrupt source to check. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. * This parameter can be one of the following values: * @arg DMA2D_IT_CE: Configuration error interrupt mask * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask @@ -445,25 +495,30 @@ typedef struct __DMA2D_HandleTypeDef * @retval The state of INTERRUPT source. */ #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) - + /** * @} */ -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions * @{ */ /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions * @{ - */ - + */ + /* Initialization and de-initialization functions *******************************/ -HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); +HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d); void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d); void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ /** * @} @@ -473,7 +528,7 @@ void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d); /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions * @{ */ - + /* IO operation functions *******************************************************/ HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); @@ -529,94 +584,106 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); * @} */ -/* Private constants ---------------------------------------------------------*/ - +/* Private constants ---------------------------------------------------------*/ + /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants * @{ - */ + */ -/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark +/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark * @{ */ #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ /** * @} */ - + /** @defgroup DMA2D_Color_Value DMA2D Color Value * @{ */ -#define DMA2D_COLOR_VALUE ((uint32_t)0x000000FFU) /*!< Color value mask */ +#define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */ /** * @} - */ + */ /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers * @{ - */ -#define DMA2D_MAX_LAYER 2 /*!< DMA2D maximum number of layers */ + */ +#define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */ +/** + * @} + */ + +/** @defgroup DMA2D_Layers DMA2D Layers + * @{ + */ +#define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */ +#define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */ /** * @} - */ - -/** @defgroup DMA2D_Offset DMA2D Offset + */ + +/** @defgroup DMA2D_Offset DMA2D Offset * @{ */ -#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */ +#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */ /** * @} - */ - -/** @defgroup DMA2D_Size DMA2D Size + */ + +/** @defgroup DMA2D_Size DMA2D Size * @{ */ -#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D number of pixels per line */ -#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of lines */ +#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */ +#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */ /** * @} - */ - + */ + /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size * @{ */ -#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D CLUT size */ +#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */ /** * @} - */ - + */ + /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ /** @defgroup DMA2D_Private_Macros DMA2D Private Macros * @{ */ -#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= DMA2D_MAX_LAYER) +#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER)) -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT) #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \ ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG)) #else #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT */ #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) + #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) + #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \ ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \ ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \ ((INPUT_CM) == DMA2D_INPUT_A4)) + #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ ((AlphaMode) == DMA2D_COMBINE_ALPHA)) @@ -627,14 +694,16 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \ ((RB_Swap) == DMA2D_RB_SWAP)) -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) #define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \ ((LOM) == DMA2D_LOM_BYTES)) +#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ +#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) #define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \ ((BYTES_SWAP) == DMA2D_BYTES_SWAP)) +#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) @@ -651,19 +720,19 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); /** * @} - */ + */ /** * @} */ -#endif /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* DMA2D */ #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_HAL_DMA2D_H */ +#endif /* STM32L4xx_HAL_DMA2D_H */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h index 7ecf6484ab..24071abfad 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h @@ -164,32 +164,32 @@ typedef struct * @{ */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 0U /*!< Request generator Signal is EXTI0 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 1U /*!< Request generator Signal is EXTI1 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 2U /*!< Request generator Signal is EXTI2 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 3U /*!< Request generator Signal is EXTI3 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 4U /*!< Request generator Signal is EXTI4 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 5U /*!< Request generator Signal is EXTI5 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 6U /*!< Request generator Signal is EXTI6 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 7U /*!< Request generator Signal is EXTI7 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 8U /*!< Request generator Signal is EXTI8 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 9U /*!< Request generator Signal is EXTI9 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 10U /*!< Request generator Signal is EXTI10 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 11U /*!< Request generator Signal is EXTI11 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 12U /*!< Request generator Signal is EXTI12 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 13U /*!< Request generator Signal is EXTI13 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 14U /*!< Request generator Signal is EXTI14 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 15U /*!< Request generator Signal is EXTI15 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */ -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */ -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */ -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */ -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT 20U /*!< Request generator Signal is LPTIM1 OUT */ -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT 21U /*!< Request generator Signal is LPTIM2 OUT */ -#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE 22U /*!< Request generator Signal is DSI Tearing Effect */ -#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT 23U /*!< Request generator Signal is DSI End of refresh */ -#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT 24U /*!< Request generator Signal is DMA2D End of Transfer */ -#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT 25U /*!< Request generator Signal is LTDC IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI0 0U /*!< Request generator Signal is EXTI0 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI1 1U /*!< Request generator Signal is EXTI1 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI2 2U /*!< Request generator Signal is EXTI2 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI3 3U /*!< Request generator Signal is EXTI3 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI4 4U /*!< Request generator Signal is EXTI4 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI5 5U /*!< Request generator Signal is EXTI5 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI6 6U /*!< Request generator Signal is EXTI6 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI7 7U /*!< Request generator Signal is EXTI7 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI8 8U /*!< Request generator Signal is EXTI8 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI9 9U /*!< Request generator Signal is EXTI9 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI10 10U /*!< Request generator Signal is EXTI10 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI11 11U /*!< Request generator Signal is EXTI11 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI12 12U /*!< Request generator Signal is EXTI12 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI13 13U /*!< Request generator Signal is EXTI13 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI14 14U /*!< Request generator Signal is EXTI14 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI15 15U /*!< Request generator Signal is EXTI15 IT */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */ +#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 20U /*!< Request generator Signal is LPTIM1 OUT */ +#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 21U /*!< Request generator Signal is LPTIM2 OUT */ +#define HAL_DMAMUX1_REQ_GEN_DSI_TE 22U /*!< Request generator Signal is DSI Tearing Effect */ +#define HAL_DMAMUX1_REQ_GEN_DSI_EOT 23U /*!< Request generator Signal is DSI End of refresh */ +#define HAL_DMAMUX1_REQ_GEN_DMA2D_EOT 24U /*!< Request generator Signal is DMA2D End of Transfer */ +#define HAL_DMAMUX1_REQ_GEN_LTDC_IT 25U /*!< Request generator Signal is LTDC IT */ /** * @} @@ -198,10 +198,10 @@ typedef struct /** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection * @{ */ -#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT 0U /*!< block request generator events */ -#define HAL_DMAMUX_REQUEST_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */ -#define HAL_DMAMUX_REQUEST_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */ -#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */ +#define HAL_DMAMUX_REQ_GEN_NO_EVENT 0U /*!< block request generator events */ +#define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */ +#define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */ +#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */ /** * @} @@ -265,7 +265,7 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); #define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \ ((EVENT) == ENABLE)) -#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQUEST_GEN_LTDC_IT) +#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LTDC_IT) #define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32)) diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dsi.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dsi.h index 3878a97bd0..b8682c2fb0 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dsi.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dsi.h @@ -34,18 +34,17 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DSI_H -#define __STM32L4xx_HAL_DSI_H +#ifndef STM32L4xx_HAL_DSI_H +#define STM32L4xx_HAL_DSI_H #ifdef __cplusplus extern "C" { #endif +#if defined(DSI) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" -#if defined(DSI) - /** @addtogroup STM32L4xx_HAL_Driver * @{ */ @@ -316,7 +315,7 @@ typedef enum /** * @brief DSI Handle Structure definition */ -typedef struct +typedef struct __DSI_HandleTypeDef { DSI_TypeDef *Instance; /*!< Register base address */ DSI_InitTypeDef Init; /*!< DSI required parameters */ @@ -324,8 +323,41 @@ typedef struct __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */ __IO uint32_t ErrorCode; /*!< DSI Error code */ uint32_t ErrorMsk; /*!< DSI Error monitoring mask */ + +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + void (* TearingEffectCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Tearing Effect Callback */ + void (* EndOfRefreshCallback) (struct __DSI_HandleTypeDef *hdsi); /*!< DSI End Of Refresh Callback */ + void (* ErrorCallback) (struct __DSI_HandleTypeDef *hdsi); /*!< DSI Error Callback */ + + void (* MspInitCallback) (struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp Init callback */ + void (* MspDeInitCallback) (struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp DeInit callback */ + +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ + }DSI_HandleTypeDef; +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) +/** + * @brief HAL DSI Callback ID enumeration definition + */ +typedef enum +{ + HAL_DSI_MSPINIT_CB_ID = 0x00U, /*!< DSI MspInit callback ID */ + HAL_DSI_MSPDEINIT_CB_ID = 0x01U, /*!< DSI MspDeInit callback ID */ + + HAL_DSI_TEARING_EFFECT_CB_ID = 0x02U, /*!< DSI Tearing Effect Callback ID */ + HAL_DSI_ENDOF_REFRESH_CB_ID = 0x03U, /*!< DSI End Of Refresh Callback ID */ + HAL_DSI_ERROR_CB_ID = 0x04U /*!< DSI Error Callback ID */ + +}HAL_DSI_CallbackIDTypeDef; + +/** + * @brief HAL DSI Callback pointer definition + */ +typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef * hdsi); /*!< pointer to an DSI callback function */ + +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ + /* Exported constants --------------------------------------------------------*/ /** @defgroup DSI_DCS_Command DSI DCS Command * @{ @@ -816,17 +848,20 @@ typedef struct /** @defgroup DSI_Error_Data_Type DSI Error Data Type * @{ */ -#define HAL_DSI_ERROR_NONE 0U -#define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */ -#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */ -#define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */ -#define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */ -#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */ -#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */ -#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */ -#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */ -#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */ -#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */ +#define HAL_DSI_ERROR_NONE 0U +#define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */ +#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */ +#define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */ +#define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */ +#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */ +#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */ +#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */ +#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */ +#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */ +#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) +#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */ +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ /** * @} */ @@ -891,11 +926,19 @@ typedef struct * @param __HANDLE__: DSI handle * @retval None */ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) +#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_DSI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET) +#endif /*USE_HAL_DSI_REGISTER_CALLBACKS */ /** * @brief Enables the DSI host. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_ENABLE(__HANDLE__) do { \ @@ -908,7 +951,7 @@ typedef struct /** * @brief Disables the DSI host. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_DISABLE(__HANDLE__) do { \ @@ -921,7 +964,7 @@ typedef struct /** * @brief Enables the DSI wrapper. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \ @@ -934,7 +977,7 @@ typedef struct /** * @brief Disable the DSI wrapper. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \ @@ -947,7 +990,7 @@ typedef struct /** * @brief Enables the DSI PLL. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \ @@ -960,7 +1003,7 @@ typedef struct /** * @brief Disables the DSI PLL. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \ @@ -973,7 +1016,7 @@ typedef struct /** * @brief Enables the DSI regulator. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \ @@ -986,7 +1029,7 @@ typedef struct /** * @brief Disables the DSI regulator. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \ @@ -999,8 +1042,8 @@ typedef struct /** * @brief Get the DSI pending flags. - * @param __HANDLE__: DSI handle. - * @param __FLAG__: Get the specified flag. + * @param __HANDLE__ DSI handle. + * @param __FLAG__ Get the specified flag. * This parameter can be any combination of the following values: * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag @@ -1016,8 +1059,8 @@ typedef struct /** * @brief Clears the DSI pending flags. - * @param __HANDLE__: DSI handle. - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DSI handle. + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag @@ -1030,8 +1073,8 @@ typedef struct /** * @brief Enables the specified DSI interrupts. - * @param __HANDLE__: DSI handle. - * @param __INTERRUPT__: specifies the DSI interrupt sources to be enabled. + * @param __HANDLE__ DSI handle. + * @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg DSI_IT_TE : Tearing Effect Interrupt * @arg DSI_IT_ER : End of Refresh Interrupt @@ -1044,8 +1087,8 @@ typedef struct /** * @brief Disables the specified DSI interrupts. - * @param __HANDLE__: DSI handle - * @param __INTERRUPT__: specifies the DSI interrupt sources to be disabled. + * @param __HANDLE__ DSI handle + * @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg DSI_IT_TE : Tearing Effect Interrupt * @arg DSI_IT_ER : End of Refresh Interrupt @@ -1058,8 +1101,8 @@ typedef struct /** * @brief Checks whether the specified DSI interrupt source is enabled or not. - * @param __HANDLE__: DSI handle - * @param __INTERRUPT__: specifies the DSI interrupt source to check. + * @param __HANDLE__ DSI handle + * @param __INTERRUPT__ specifies the DSI interrupt source to check. * This parameter can be one of the following values: * @arg DSI_IT_TE : Tearing Effect Interrupt * @arg DSI_IT_ER : End of Refresh Interrupt @@ -1084,6 +1127,12 @@ void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi); void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi); void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID, pDSI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ + HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID); HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg); HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg); @@ -1291,6 +1340,6 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); } #endif -#endif /* __STM32L4xx_HAL_DSI_H */ +#endif /* STM32L4xx_HAL_DSI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h index c0afbbf9c7..fc6c2f2797 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h @@ -161,22 +161,22 @@ typedef struct /** @defgroup FLASH_Error FLASH Error * @{ */ -#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000) -#define HAL_FLASH_ERROR_OP ((uint32_t)0x00000001) -#define HAL_FLASH_ERROR_PROG ((uint32_t)0x00000002) -#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000004) -#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008) -#define HAL_FLASH_ERROR_SIZ ((uint32_t)0x00000010) -#define HAL_FLASH_ERROR_PGS ((uint32_t)0x00000020) -#define HAL_FLASH_ERROR_MIS ((uint32_t)0x00000040) -#define HAL_FLASH_ERROR_FAST ((uint32_t)0x00000080) -#define HAL_FLASH_ERROR_RD ((uint32_t)0x00000100) -#define HAL_FLASH_ERROR_OPTV ((uint32_t)0x00000200) -#define HAL_FLASH_ERROR_ECCD ((uint32_t)0x00000400) +#define HAL_FLASH_ERROR_NONE 0x00000000U +#define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR +#define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR +#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR +#define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR +#define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR +#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR +#define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR +#define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR +#define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR +#define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR +#define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define HAL_FLASH_ERROR_PEMPTY ((uint32_t)0x00000800) +#define HAL_FLASH_ERROR_PEMPTY FLASH_FLAG_PEMPTY #endif /** * @} @@ -535,6 +535,15 @@ typedef struct defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define FLASH_FLAG_PEMPTY FLASH_SR_PEMPTY /*!< FLASH Program empty */ +#define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ + FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ + FLASH_FLAG_OPTVERR | FLASH_FLAG_PEMPTY) +#else +#define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ + FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ + FLASH_FLAG_OPTVERR) #endif #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ @@ -695,8 +704,8 @@ typedef struct * @arg FLASH_IT_ECCC: ECC Correction Interrupt * @retval none */ -#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if((__INTERRUPT__) & FLASH_IT_ECCC) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ - if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ } while(0) /** @@ -709,8 +718,8 @@ typedef struct * @arg FLASH_IT_ECCC: ECC Correction Interrupt * @retval none */ -#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if((__INTERRUPT__) & FLASH_IT_ECCC) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ - if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ } while(0) /** @@ -734,8 +743,8 @@ typedef struct * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected * @retval The new state of FLASH_FLAG (SET or RESET). */ -#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) ? \ - (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \ + (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__))) /** @@ -758,8 +767,8 @@ typedef struct * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags * @retval None */ -#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\ - if((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\ + if(((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\ } while(0) /** * @} @@ -823,20 +832,20 @@ uint32_t HAL_FLASH_GetError(void); #define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x800 << 10) : \ - (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10)) +#define FLASH_SIZE ((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x800U << 10U) : \ + (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)) #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x200 << 10) : \ - (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10)) +#define FLASH_SIZE ((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x200U << 10U) : \ + (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)) #else -#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x400 << 10) : \ - (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10)) +#define FLASH_SIZE ((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x400U << 10U) : \ + (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)) #endif #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) +#define FLASH_BANK_SIZE (FLASH_SIZE >> 1U) #else #define FLASH_BANK_SIZE (FLASH_SIZE) #endif @@ -881,34 +890,34 @@ uint32_t HAL_FLASH_GetError(void); ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST)) #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_BASE+0x1FFFFF)) +#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE)) && ((ADDRESS) <= (FLASH_BASE+0x1FFFFFU))) #else -#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? \ - ((ADDRESS) <= FLASH_BASE+0xFFFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? \ - ((ADDRESS) <= FLASH_BASE+0x7FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? \ - ((ADDRESS) <= FLASH_BASE+0x3FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? \ - ((ADDRESS) <= FLASH_BASE+0x1FFFF) : ((ADDRESS) <= FLASH_BASE+0xFFFFF)))))) +#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE)) && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? \ + ((ADDRESS) <= (FLASH_BASE+0xFFFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? \ + ((ADDRESS) <= (FLASH_BASE+0x7FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? \ + ((ADDRESS) <= (FLASH_BASE+0x3FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U) ? \ + ((ADDRESS) <= (FLASH_BASE+0x1FFFFU)) : ((ADDRESS) <= (FLASH_BASE+0xFFFFFU))))))) #endif -#define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000) && ((ADDRESS) <= 0x1FFF73FF)) +#define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU)) -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS)) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS))) #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_FLASH_PAGE(PAGE) ((PAGE) < 256) +#define IS_FLASH_PAGE(PAGE) ((PAGE) < 256U) #elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) -#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? ((PAGE) < 256) : \ - ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 128) : \ - ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 64) : \ - ((PAGE) < 256))))) +#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? ((PAGE) < 256U) : \ + ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 128U) : \ + ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 64U) : \ + ((PAGE) < 256U))))) #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 256) : \ - ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \ - ((PAGE) < 256)))) +#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 256U) : \ + ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \ + ((PAGE) < 256U)))) #else -#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \ - ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? ((PAGE) < 64) : \ - ((PAGE) < 128)))) +#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \ + ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U) ? ((PAGE) < 64U) : \ + ((PAGE) < 128U)))) #endif #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP))) @@ -927,11 +936,11 @@ uint32_t HAL_FLASH_GetError(void); ((LEVEL) == OB_RDP_LEVEL_2)*/) #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0xFFFF) && ((TYPE) != 0)) +#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0xFFFFU) && ((TYPE) != 0U)) #elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) -#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFF) && ((TYPE) != 0)) +#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFFU) && ((TYPE) != 0U)) #else -#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x7E7F) && ((TYPE) != 0) && (((TYPE)&0x0180) == 0)) +#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x7E7FU) && ((TYPE) != 0U) && (((TYPE)&0x0180U) == 0U)) #endif #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h index e8a684f1e6..9145f6d8c6 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h @@ -54,39 +54,6 @@ /* Exported types ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ -/** - * @brief __RAM_FUNC definition - */ -#if defined ( __CC_ARM ) -/* ARM Compiler - ------------ - RAM functions are defined using the toolchain options. - Functions that are executed in RAM should reside in a separate source module. - Using the 'Options for File' dialog you can simply change the 'Code / Const' - area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the 'Options for Target' - dialog. -*/ -#define __RAM_FUNC HAL_StatusTypeDef - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- - RAM functions are defined using a specific toolchain keyword "__ramfunc". -*/ -#define __RAM_FUNC __ramfunc HAL_StatusTypeDef - -#elif defined ( __GNUC__ ) -/* GNU Compiler - ------------ - RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".RamFunc")))". -*/ -#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc"))) - -#endif - - /* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASH_RAMFUNC_Exported_Functions * @{ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gfxmmu.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gfxmmu.h index c66b42c083..72379796f7 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gfxmmu.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gfxmmu.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_GFXMMU_H -#define __STM32L4xx_HAL_GFXMMU_H +#ifndef STM32L4xx_HAL_GFXMMU_H +#define STM32L4xx_HAL_GFXMMU_H #ifdef __cplusplus extern "C" { @@ -105,12 +105,17 @@ typedef struct /** * @brief GFXMMU handle structure definition */ -typedef struct +typedef struct __GFXMMU_HandleTypeDef { GFXMMU_TypeDef *Instance; /*!< GFXMMU instance */ GFXMMU_InitTypeDef Init; /*!< GFXMMU init parameters */ HAL_GFXMMU_StateTypeDef State; /*!< GFXMMU state */ __IO uint32_t ErrorCode; /*!< GFXMMU error code */ +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) + void (*ErrorCallback) (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU error callback */ + void (*MspInitCallback) (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP init callback */ + void (*MspDeInitCallback) (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP de-init callback */ +#endif }GFXMMU_HandleTypeDef; /** @@ -132,6 +137,23 @@ typedef struct LineOffset = [(Blocks already used) - (1st visible block)]*BlockSize. */ }GFXMMU_LutLineTypeDef; +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) +/** + * @brief GFXMMU callback ID enumeration definition + */ +typedef enum +{ + HAL_GFXMMU_ERROR_CB_ID = 0x00U, /*!< GFXMMU error callback ID */ + HAL_GFXMMU_MSPINIT_CB_ID = 0x01U, /*!< GFXMMU MSP init callback ID */ + HAL_GFXMMU_MSPDEINIT_CB_ID = 0x02U /*!< GFXMMU MSP de-init callback ID */ +}HAL_GFXMMU_CallbackIDTypeDef; + +/** + * @brief GFXMMU callback pointer definition + */ +typedef void (*pGFXMMU_CallbackTypeDef)(GFXMMU_HandleTypeDef *hgfxmmu); +#endif + /** * @} */ @@ -172,6 +194,9 @@ typedef struct #define GFXMMU_ERROR_BUFFER2_OVERFLOW GFXMMU_SR_B2OF /*!< Buffer 2 overflow */ #define GFXMMU_ERROR_BUFFER3_OVERFLOW GFXMMU_SR_B3OF /*!< Buffer 3 overflow */ #define GFXMMU_ERROR_AHB_MASTER GFXMMU_SR_AMEF /*!< AHB master error */ +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) +#define GFXMMU_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */ +#endif /** * @} */ @@ -199,7 +224,15 @@ typedef struct * @param __HANDLE__ GFXMMU handle. * @retval None */ +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) +#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_GFXMMU_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GFXMMU_STATE_RESET) +#endif /** * @} @@ -219,6 +252,14 @@ HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu); HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu); void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu); void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu); +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) +/* GFXMMU callbacks register/unregister functions *****************************/ +HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu, + HAL_GFXMMU_CallbackIDTypeDef CallbackID, + pGFXMMU_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu, + HAL_GFXMMU_CallbackIDTypeDef CallbackID); +#endif /** * @} */ @@ -301,6 +342,6 @@ uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu); } #endif -#endif /* __STM32L4xx_HAL_GFXMMU_H */ +#endif /* STM32L4xx_HAL_GFXMMU_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h index 1bd90908ff..335859e30b 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h @@ -682,7 +682,7 @@ */ #define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ #define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ -#define GPIO_AF12_DSI ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#define GPIO_AF12_DSI ((uint8_t)0x0C) /* DSI Alternate Function mapping */ #define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ #define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ #define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */ @@ -716,7 +716,7 @@ /** * @} - */ + */ /** * @} @@ -804,7 +804,7 @@ * @} */ -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash.h index 77d0b7c86f..f7747aac6c 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash.h @@ -31,7 +31,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L4xx_HAL_HASH_H @@ -52,30 +52,30 @@ /** @addtogroup HASH * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup HASH_Exported_Types HASH Exported Types * @{ */ -/** - * @brief HASH Configuration Structure definition +/** + * @brief HASH Configuration Structure definition */ typedef struct -{ +{ uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit data. This parameter can be a value of @ref HASH_Data_Type. */ - + uint32_t KeySize; /*!< The key size is used only in HMAC operation. */ - + uint8_t* pKey; /*!< The key is used only in HMAC operation. */ - + } HASH_InitTypeDef; -/** - * @brief HAL State structures definition - */ +/** + * @brief HAL State structures definition + */ typedef enum { HAL_HASH_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ @@ -83,12 +83,12 @@ typedef enum HAL_HASH_STATE_BUSY = 0x02, /*!< Processing (hashing) is ongoing */ HAL_HASH_STATE_TIMEOUT = 0x06, /*!< Timeout state */ HAL_HASH_STATE_ERROR = 0x07, /*!< Error state */ - HAL_HASH_STATE_SUSPENDED = 0x08 /*!< Suspended state */ + HAL_HASH_STATE_SUSPENDED = 0x08 /*!< Suspended state */ }HAL_HASH_StateTypeDef; -/** - * @brief HAL phase structures definition - */ +/** + * @brief HAL phase structures definition + */ typedef enum { HAL_HASH_PHASE_READY = 0x01, /*!< HASH peripheral is ready to start */ @@ -101,39 +101,53 @@ typedef enum (step 3 consists in entering the outer hash function key) */ }HAL_HASH_PhaseTypeDef; -/** +/** * @brief HAL HASH mode suspend definitions */ typedef enum { HAL_HASH_SUSPEND_NONE = 0x00, /*!< HASH peripheral suspension not requested */ - HAL_HASH_SUSPEND = 0x01 /*!< HASH peripheral suspension is requested */ + HAL_HASH_SUSPEND = 0x01 /*!< HASH peripheral suspension is requested */ }HAL_HASH_SuspendTypeDef; +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) +/** + * @brief HAL HASH common Callback ID enumeration definition + */ +typedef enum +{ + HAL_HASH_MSPINIT_CB_ID = 0x00U, /*!< HASH MspInit callback ID */ + HAL_HASH_MSPDEINIT_CB_ID = 0x01U, /*!< HASH MspDeInit callback ID */ + HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */ + HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */ + HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */ +}HAL_HASH_CallbackIDTypeDef; +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ -/** - * @brief HASH Handle Structure definition - */ -typedef struct -{ + +/** + * @brief HASH Handle Structure definition + */ +typedef struct __HASH_HandleTypeDef +{ HASH_InitTypeDef Init; /*!< HASH required parameters */ - + uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */ uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */ - + uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */ - uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ + uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ uint32_t HashBuffSize; /*!< Size of buffer to be processed */ __IO uint32_t HashInCount; /*!< Counter of inputted data */ - + __IO uint32_t HashITCounter; /*!< Counter of issued interrupts */ - + __IO uint32_t HashKeyCount; /*!< Counter for Key inputted data (HMAC only) */ - + HAL_StatusTypeDef Status; /*!< HASH peripheral status */ HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */ @@ -143,15 +157,36 @@ typedef struct HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */ - - HAL_HASH_SuspendTypeDef SuspendRequest; /*!< HASH peripheral suspension request flag */ - + + HAL_HASH_SuspendTypeDef SuspendRequest; /*!< HASH peripheral suspension request flag */ + FlagStatus DigestCalculationDisable; /*!< Digest calculation phase skip (MDMAT bit control) for multi-buffers DMA-based HMAC computation */ - - __IO uint32_t NbWordsAlreadyPushed; /*!< Numbers of words already pushed in FIFO before inputting new block */ + __IO uint32_t NbWordsAlreadyPushed; /*!< Numbers of words already pushed in FIFO before inputting new block */ + + __IO uint32_t ErrorCode; /*!< HASH Error code */ + +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + void (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH input completion callback */ + + void (* DgstCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH digest computation completion callback */ + + void (* ErrorCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH error callback */ + + void (* MspInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp Init callback */ + + void (* MspDeInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp DeInit callback */ + +#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ } HASH_HandleTypeDef; +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) +/** + * @brief HAL HASH Callback pointer definition + */ +typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer to a HASH common callback functions */ +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + /** * @} */ @@ -164,7 +199,7 @@ typedef struct /** @defgroup HASH_Algo_Selection HASH algorithm selection * @{ - */ + */ #define HASH_ALGOSELECTION_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */ #define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */ #define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */ @@ -175,8 +210,8 @@ typedef struct /** @defgroup HASH_Algorithm_Mode HASH algorithm mode * @{ - */ -#define HASH_ALGOMODE_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */ + */ +#define HASH_ALGOMODE_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */ #define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */ /** * @} @@ -184,7 +219,7 @@ typedef struct /** @defgroup HASH_Data_Type HASH input data type * @{ - */ + */ #define HASH_DATATYPE_32B ((uint32_t)0x0000) /*!< 32-bit data. No swapping */ #define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */ #define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */ @@ -195,7 +230,7 @@ typedef struct /** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode HMAC key length type * @{ - */ + */ #define HASH_HMAC_KEYTYPE_SHORTKEY ((uint32_t)0x00000000) /*!< HMAC Key size is <= 64 bytes */ #define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key size is > 64 bytes */ /** @@ -204,7 +239,7 @@ typedef struct /** @defgroup HASH_flags_definition HASH flags definitions * @{ - */ + */ #define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the IP */ #define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */ #define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ @@ -213,27 +248,39 @@ typedef struct /** * @} - */ + */ /** @defgroup HASH_interrupts_definition HASH interrupts definitions * @{ - */ + */ #define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */ #define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */ /** * @} */ - + /** @defgroup HASH_alias HASH API alias * @{ */ #define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */ /** * @} - */ - - + */ + + +/** @defgroup HASH_Error_Definition HASH Error Definition + * @{ + */ +#define HAL_HASH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_HASH_ERROR_IT ((uint32_t)0x00000001U) /*!< IT-based process error */ +#define HAL_HASH_ERROR_DMA ((uint32_t)0x00000002U) /*!< DMA-based process error */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) +#define HAL_HASH_ERROR_INVALID_CALLBACK ((uint32_t)0x00000004U) /*!< Invalid Callback error */ +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ +/** + * @} + */ /** * @} @@ -247,10 +294,10 @@ typedef struct /** @brief Check whether or not the specified HASH flag is set. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: - * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer. + * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer. * @arg @ref HASH_FLAG_DCIS Digest calculation complete. * @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing. - * @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data. + * @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data. * @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data. * @retval The new state of __FLAG__ (TRUE or FALSE). */ @@ -262,7 +309,7 @@ typedef struct /** @brief Clear the specified HASH flag. * @param __FLAG__: specifies the flag to clear. * This parameter can be one of the following values: - * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer. + * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer. * @arg @ref HASH_FLAG_DCIS Digest calculation complete * @retval None */ @@ -291,7 +338,17 @@ typedef struct * @param __HANDLE__: HASH handle. * @retval None */ + +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) +#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) do{\ + (__HANDLE__)->State = HAL_HASH_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + }while(0) +#else #define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET) +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + /** @brief Reset HASH handle status. * @param __HANDLE__: HASH handle. @@ -300,11 +357,11 @@ typedef struct #define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK) /** - * @brief Enable the multi-buffer DMA transfer mode. - * @note This bit is set when hashing large files when multiple DMA transfers are needed. + * @brief Enable the multi-buffer DMA transfer mode. + * @note This bit is set when hashing large files when multiple DMA transfers are needed. * @retval None */ -#define __HAL_HASH_SET_MDMAT() SET_BIT(HASH->CR, HASH_CR_MDMAT) +#define __HAL_HASH_SET_MDMAT() SET_BIT(HASH->CR, HASH_CR_MDMAT) /** * @brief Disable the multi-buffer DMA transfer mode. @@ -325,13 +382,13 @@ typedef struct * @param __SIZE__: size in bytes of last data written in Data register. * @retval None */ -#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * ((__SIZE__) % 4)) - +#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * ((__SIZE__) % 4)) + /** * @brief Reset the HASH core. * @retval None */ -#define __HAL_HASH_INIT() SET_BIT(HASH->CR, HASH_CR_INIT) +#define __HAL_HASH_INIT() SET_BIT(HASH->CR, HASH_CR_INIT) /** * @} @@ -355,60 +412,60 @@ typedef struct * @brief Return number of words already pushed in the FIFO. * @retval Number of words already pushed in the FIFO */ -#define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8) +#define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8) /** * @brief Ensure that HASH input data type is valid. - * @param __DATATYPE__: HASH input data type. + * @param __DATATYPE__: HASH input data type. * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid) - */ + */ #define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \ ((__DATATYPE__) == HASH_DATATYPE_16B)|| \ ((__DATATYPE__) == HASH_DATATYPE_8B) || \ - ((__DATATYPE__) == HASH_DATATYPE_1B)) - - - + ((__DATATYPE__) == HASH_DATATYPE_1B)) + + + /** - * @brief Ensure that input data buffer size is valid for multi-buffer HASH + * @brief Ensure that input data buffer size is valid for multi-buffer HASH * processing in polling mode. - * @note This check is valid only for multi-buffer HASH processing in polling mode. - * @param __SIZE__: input data buffer size. + * @note This check is valid only for multi-buffer HASH processing in polling mode. + * @param __SIZE__: input data buffer size. * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid) */ #define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__) (((__SIZE__) % 4) == 0) /** - * @brief Ensure that input data buffer size is valid for multi-buffer HASH + * @brief Ensure that input data buffer size is valid for multi-buffer HASH * processing in DMA mode. - * @note This check is valid only for multi-buffer HASH processing in DMA mode. - * @param __SIZE__: input data buffer size. + * @note This check is valid only for multi-buffer HASH processing in DMA mode. + * @param __SIZE__: input data buffer size. * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid) - */ -#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == RESET) || (((__SIZE__) % 4) == 0)) + */ +#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == RESET) || (((__SIZE__) % 4) == 0)) /** - * @brief Ensure that input data buffer size is valid for multi-buffer HMAC + * @brief Ensure that input data buffer size is valid for multi-buffer HMAC * processing in DMA mode. * @note This check is valid only for multi-buffer HMAC processing in DMA mode. - * @param __HANDLE__: HASH handle. - * @param __SIZE__: input data buffer size. + * @param __HANDLE__: HASH handle. + * @param __SIZE__: input data buffer size. * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid) - */ -#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4) == 0)) + */ +#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4) == 0)) /** * @brief Ensure that handle phase is set to HASH processing. - * @param __HANDLE__: HASH handle. + * @param __HANDLE__: HASH handle. * @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing) - */ + */ #define IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS) /** * @brief Ensure that handle phase is set to HMAC processing. - * @param __HANDLE__: HASH handle. + * @param __HANDLE__: HASH handle. * @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing) - */ + */ #define IS_HMAC_PROCESSING(__HANDLE__) (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \ ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_2) || \ ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_3)) @@ -425,8 +482,8 @@ typedef struct /** @addtogroup HASH_Exported_Functions HASH Exported Functions * @{ */ - -/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions + +/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ @@ -438,12 +495,18 @@ void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash); void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash); void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash); void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + /** * @} */ -/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode +/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode * @{ */ @@ -458,7 +521,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *p * @} */ -/** @addtogroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode +/** @addtogroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode * @{ */ @@ -470,7 +533,7 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); * @} */ -/** @addtogroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode +/** @addtogroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode * @{ */ @@ -484,7 +547,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBu * @} */ -/** @addtogroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode +/** @addtogroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode * @{ */ @@ -496,7 +559,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @} */ -/** @addtogroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode +/** @addtogroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode * @{ */ @@ -507,7 +570,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @} */ -/** @addtogroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode +/** @addtogroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode * @{ */ @@ -519,7 +582,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn * @} */ -/** @addtogroup HASH_Exported_Functions_Group8 Peripheral states functions +/** @addtogroup HASH_Exported_Functions_Group8 Peripheral states functions * @{ */ @@ -531,16 +594,17 @@ void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer); void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer); void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); +uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); /** * @} */ - + /** * @} */ -/* Private functions -----------------------------------------------------------*/ +/* Private functions -----------------------------------------------------------*/ /** @addtogroup HASH_Private_Functions HASH Private Functions * @{ @@ -558,18 +622,18 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /** * @} - */ + */ /** * @} */ - + /** * @} - */ - -#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ - + */ + +#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ + #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash_ex.h index 15f825e2f9..1e34c3b1a6 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash_ex.h @@ -31,7 +31,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L4xx_HAL_HASH_EX_H @@ -52,20 +52,20 @@ /** @addtogroup HASHEx * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ - + /* Exported functions --------------------------------------------------------*/ /** @addtogroup HASHEx_Exported_Functions HASH Extended Exported Functions * @{ */ - -/** @addtogroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode + +/** @addtogroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode * @{ */ @@ -78,7 +78,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_ * @} */ -/** @addtogroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode +/** @addtogroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode * @{ */ @@ -89,7 +89,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @} */ -/** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode +/** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode * @{ */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); @@ -101,7 +101,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p * @} */ -/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode +/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode * @{ */ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); @@ -110,7 +110,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @} */ -/** @addtogroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode +/** @addtogroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode * @{ */ @@ -121,10 +121,10 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @} */ -/** @addtogroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode +/** @addtogroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode * @{ */ - + HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); @@ -154,7 +154,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 /** * @} - */ + */ /** * @} @@ -162,14 +162,14 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 /** * @} - */ + */ /** * @} */ - -#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ - + +#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ + #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hcd.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hcd.h index f59105ac3d..326994dab1 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hcd.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hcd.h @@ -31,40 +31,38 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L4xx_HAL_HCD_H #define __STM32L4xx_HAL_HCD_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_ll_usb.h" - + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ /** @addtogroup HCD * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup HCD_Exported_Types HCD Exported Types * @{ */ -/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition +/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition * @{ - */ -typedef enum + */ +typedef enum { HAL_HCD_STATE_RESET = 0x00, HAL_HCD_STATE_READY = 0x01, @@ -75,25 +73,37 @@ typedef enum typedef USB_OTG_GlobalTypeDef HCD_TypeDef; typedef USB_OTG_CfgTypeDef HCD_InitTypeDef; -typedef USB_OTG_HCTypeDef HCD_HCTypeDef ; -typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ; -typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef ; +typedef USB_OTG_HCTypeDef HCD_HCTypeDef; +typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef; +typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef; /** * @} */ -/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition +/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition * @{ */ -typedef struct +typedef struct __HCD_HandleTypeDef { - HCD_TypeDef *Instance; /*!< Register base address */ + HCD_TypeDef *Instance; /*!< Register base address */ HCD_InitTypeDef Init; /*!< HCD required parameters */ - HCD_HCTypeDef hc[15]; /*!< Host channels parameters */ + HCD_HCTypeDef hc[16]; /*!< Host channels parameters */ HAL_LockTypeDef Lock; /*!< HCD peripheral status */ __IO HCD_StateTypeDef State; /*!< HCD communication state */ - void *pData; /*!< Pointer Stack Handler */ - + __IO uint32_t ErrorCode; /*!< HCD Error code */ + void *pData; /*!< Pointer Stack Handler */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD SOF callback */ + void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Connect callback */ + void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Disconnect callback */ + void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Enable callback */ + void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Disable callback */ + void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum, + HCD_URBStateTypeDef urb_state); /*!< USB OTG HCD Host Channel Notify URB Change callback */ + + void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp Init callback */ + void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp DeInit callback */ +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } HCD_HandleTypeDef; /** * @} @@ -102,7 +112,7 @@ typedef struct /** * @} */ - + /* Exported constants --------------------------------------------------------*/ /** @defgroup HCD_Exported_Constants HCD Exported Constants * @{ @@ -111,9 +121,9 @@ typedef struct /** @defgroup HCD_Speed HCD Speed * @{ */ -#define HCD_SPEED_HIGH 0 -#define HCD_SPEED_LOW 2 -#define HCD_SPEED_FULL 3 +#define HCD_SPEED_HIGH 0U +#define HCD_SPEED_LOW 2U +#define HCD_SPEED_FULL 3U /** * @} */ @@ -121,32 +131,45 @@ typedef struct /** @defgroup HCD_PHY_Module HCD PHY Module * @{ */ -#define HCD_PHY_EMBEDDED 1 +#define HCD_PHY_ULPI 1U +#define HCD_PHY_EMBEDDED 2U +/** + * @} + */ + +/** @defgroup HCD_Error_Code_definition HCD Error Code definition + * @brief HCD Error Code definition + * @{ + */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +#define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */ +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + /** * @} */ /** * @} - */ - + */ + /* Exported macro ------------------------------------------------------------*/ /** @defgroup HCD_Exported_Macros HCD Exported Macros * @brief macros to handle interrupts and specific clock configurations * @{ */ -#define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) -#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0) +#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) -#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) -#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) -#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) -#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) -#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) +#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) +#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) +#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) +#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) +#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) /** * @} */ @@ -156,25 +179,63 @@ typedef struct * @{ */ -/* Initialization/de-initialization functions ********************************/ -/** @addtogroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions +/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd); -HAL_StatusTypeDef HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd); -HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps); - -HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, - uint8_t ch_num); - -void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); -void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, + uint8_t ch_num, + uint8_t epnum, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps); + +HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); +void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition + * @brief HAL USB OTG HCD Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */ + HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */ + HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */ + HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */ + HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */ + + HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */ + HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */ + +} HAL_HCD_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition + * @brief HAL USB OTG HCD Callback pointer definition + * @{ + */ + +typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd); /*!< pointer to a common USB OTG HCD callback function */ +typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd, + uint8_t epnum, + HCD_URBStateTypeDef urb_state); /*!< pointer to USB OTG HCD host channel callback */ +/** + * @} + */ + +HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ /** * @} */ @@ -184,22 +245,24 @@ void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); * @{ */ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, - uint8_t pipe, - uint8_t direction , - uint8_t ep_type, - uint8_t token, - uint8_t* pbuff, + uint8_t pipe, + uint8_t direction, + uint8_t ep_type, + uint8_t token, + uint8_t *pbuff, uint16_t length, uint8_t do_ping); - /* Non-Blocking mode: Interrupt */ +/* Non-Blocking mode: Interrupt */ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd); void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd); -void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, - uint8_t chnum, - HCD_URBStateTypeDef urb_state); +void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, + uint8_t chnum, + HCD_URBStateTypeDef urb_state); /** * @} */ @@ -242,6 +305,20 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); * @} */ +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup HCD_Private_Functions HCD Private Functions + * @{ + */ + /** * @} */ @@ -249,11 +326,13 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); /** * @} */ - -#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + +/** + * @} + */ + +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h index 1acdf93865..28dadb5e31 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_I2C_H -#define __STM32L4xx_HAL_I2C_H +#ifndef STM32L4xx_HAL_I2C_H +#define STM32L4xx_HAL_I2C_H #ifdef __cplusplus extern "C" { @@ -186,6 +186,11 @@ typedef enum #define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ #define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ #define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ +#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ /** * @} */ @@ -226,7 +231,54 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t ErrorCode; /*!< I2C Error code */ __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */ + + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } I2C_HandleTypeDef; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief HAL I2C Callback ID enumeration definition + */ +typedef enum +{ + HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ + HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ + HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ + HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ + HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ + HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ + HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ + HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ + HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ + + HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ + HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ + +} HAL_I2C_CallbackIDTypeDef; + +/** + * @brief HAL I2C Callback pointer definition + */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ /** * @} */ @@ -248,6 +300,13 @@ typedef struct __I2C_HandleTypeDef #define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) #define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) #define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define I2C_OTHER_FRAME (0x000000AAU) +#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U) /** * @} */ @@ -396,7 +455,15 @@ typedef struct __I2C_HandleTypeDef * @param __HANDLE__ specifies the I2C Handle. * @retval None */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) +#endif /** @brief Enable the specified I2C interrupt. * @param __HANDLE__ specifies the I2C Handle. @@ -528,6 +595,15 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ /** * @} */ @@ -568,6 +644,11 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); /** * @} */ @@ -659,7 +740,12 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ ((REQUEST) == I2C_NEXT_FRAME) || \ ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ - ((REQUEST) == I2C_LAST_FRAME)) + ((REQUEST) == I2C_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ + IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + +#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ + ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) #define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) @@ -703,6 +789,6 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #endif -#endif /* __STM32L4xx_HAL_I2C_H */ +#endif /* STM32L4xx_HAL_I2C_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h index 573d4fb563..79c6416ae5 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_I2C_EX_H -#define __STM32L4xx_HAL_I2C_EX_H +#ifndef STM32L4xx_HAL_I2C_EX_H +#define STM32L4xx_HAL_I2C_EX_H #ifdef __cplusplus extern "C" { @@ -181,6 +181,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); } #endif -#endif /* __STM32L4xx_HAL_I2C_EX_H */ +#endif /* STM32L4xx_HAL_I2C_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda.h index 5c5817af08..119e9ffbad 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda.h @@ -38,7 +38,7 @@ #define __STM32L4xx_HAL_IRDA_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -92,15 +92,15 @@ typedef struct This parameter can be a value of @ref IRDA_ClockPrescaler. */ #endif -}IRDA_InitTypeDef; +} IRDA_InitTypeDef; /** * @brief HAL IRDA State structures definition * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState. - * - gState contains IRDA state information related to global Handle management + * - gState contains IRDA state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : - * b7-b6 Error information + * b7-b6 Error information * 00 : No Error * 01 : (Not Used) * 10 : Timeout @@ -139,7 +139,7 @@ typedef enum Value is allowed for gState and RxState */ HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use Value is allowed for gState and RxState */ - HAL_IRDA_STATE_BUSY = 0x24U, /*!< an internal process is ongoing + HAL_IRDA_STATE_BUSY = 0x24U, /*!< an internal process is ongoing Value is allowed for gState only */ HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing Value is allowed for gState only */ @@ -152,21 +152,7 @@ typedef enum Value is allowed for gState only */ HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error Value is allowed for gState only */ -}HAL_IRDA_StateTypeDef; - -/** - * @brief HAL IRDA Error Code structure definition - */ -typedef enum -{ - HAL_IRDA_ERROR_NONE = 0x00U, /*!< No error */ - HAL_IRDA_ERROR_PE = 0x01U, /*!< Parity error */ - HAL_IRDA_ERROR_NE = 0x02U, /*!< Noise error */ - HAL_IRDA_ERROR_FE = 0x04U, /*!< frame error */ - HAL_IRDA_ERROR_ORE = 0x08U, /*!< Overrun error */ - HAL_IRDA_ERROR_DMA = 0x10U, /*!< DMA transfer error */ - HAL_IRDA_ERROR_BUSY = 0x20U /*!< Busy Error */ -}HAL_IRDA_ErrorTypeDef; +} HAL_IRDA_StateTypeDef; /** * @brief IRDA clock sources definition @@ -179,12 +165,12 @@ typedef enum IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ IRDA_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ IRDA_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ -}IRDA_ClockSourceTypeDef; +} IRDA_ClockSourceTypeDef; /** * @brief IRDA handle Structure definition */ -typedef struct +typedef struct __IRDA_HandleTypeDef { USART_TypeDef *Instance; /*!< USART registers base address */ @@ -210,7 +196,7 @@ typedef struct HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management + __IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management and also related to Tx operations. This parameter can be a value of @ref HAL_IRDA_StateTypeDef */ @@ -219,7 +205,57 @@ typedef struct uint32_t ErrorCode; /*!< IRDA Error code */ -}IRDA_HandleTypeDef; +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */ + + void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Complete Callback */ + + void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Half Complete Callback */ + + void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Complete Callback */ + + void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Error Callback */ + + void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Complete Callback */ + + void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */ + + void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Receive Complete Callback */ + + + void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp Init callback */ + + void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp DeInit callback */ +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + +} IRDA_HandleTypeDef; + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +/** + * @brief HAL IRDA Callback ID enumeration definition + */ +typedef enum +{ + HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< IRDA Tx Half Complete Callback ID */ + HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, /*!< IRDA Tx Complete Callback ID */ + HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< IRDA Rx Half Complete Callback ID */ + HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U, /*!< IRDA Rx Complete Callback ID */ + HAL_IRDA_ERROR_CB_ID = 0x04U, /*!< IRDA Error Callback ID */ + HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, /*!< IRDA Abort Complete Callback ID */ + HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< IRDA Abort Transmit Complete Callback ID */ + HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< IRDA Abort Receive Complete Callback ID */ + + HAL_IRDA_MSPINIT_CB_ID = 0x08U, /*!< IRDA MspInit callback ID */ + HAL_IRDA_MSPDEINIT_CB_ID = 0x09U /*!< IRDA MspDeInit callback ID */ + +} HAL_IRDA_CallbackIDTypeDef; + +/** + * @brief HAL IRDA Callback pointer definition + */ +typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer to an IRDA callback function */ + +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ /** * @brief IRDA Configuration enumeration values definition @@ -232,7 +268,7 @@ typedef enum IRDA_MODE = 0x03U, /*!< IRDA communication mode */ IRDA_PRESCALER = 0x04U, /*!< IRDA prescaling */ IRDA_POWERMODE = 0x05U /*!< IRDA power mode */ -}IRDA_ControlTypeDef; +} IRDA_ControlTypeDef; /** * @} @@ -243,6 +279,23 @@ typedef enum * @{ */ +/** @defgroup IRDA_Error_Definition IRDA Error Code Definition + * @{ + */ +#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ +#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ +#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */ +#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ +#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ +#define HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U) /*!< Busy Error */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ +/** + * @} + */ + /** @defgroup IRDA_Word_Length IRDA Word Length * @{ */ @@ -276,8 +329,8 @@ typedef enum /** @defgroup IRDA_Low_Power IRDA Low Power * @{ */ -#define IRDA_POWERMODE_NORMAL 0x00000000U /*!< IRDA normal power mode */ -#define IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP /*!< IRDA low power mode */ +#define IRDA_POWERMODE_NORMAL 0x00000000U /*!< IRDA normal power mode */ +#define IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP /*!< IRDA low power mode */ /** * @} */ @@ -285,7 +338,7 @@ typedef enum #if defined(USART_PRESC_PRESCALER) /** @defgroup IRDA_ClockPrescaler Clock Prescaler * @{ - */ + */ #define IRDA_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ #define IRDA_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ #define IRDA_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ @@ -306,8 +359,8 @@ typedef enum /** @defgroup IRDA_State IRDA State * @{ */ -#define IRDA_STATE_DISABLE 0x00000000U /*!< IRDA disabled */ -#define IRDA_STATE_ENABLE USART_CR1_UE /*!< IRDA enabled */ +#define IRDA_STATE_DISABLE 0x00000000U /*!< IRDA disabled */ +#define IRDA_STATE_ENABLE USART_CR1_UE /*!< IRDA enabled */ /** * @} */ @@ -333,8 +386,8 @@ typedef enum /** @defgroup IRDA_DMA_Tx IRDA DMA Tx * @{ */ -#define IRDA_DMA_TX_DISABLE 0x00000000U /*!< IRDA DMA TX disabled */ -#define IRDA_DMA_TX_ENABLE USART_CR3_DMAT /*!< IRDA DMA TX enabled */ +#define IRDA_DMA_TX_DISABLE 0x00000000U /*!< IRDA DMA TX disabled */ +#define IRDA_DMA_TX_ENABLE USART_CR3_DMAT /*!< IRDA DMA TX enabled */ /** * @} */ @@ -425,7 +478,7 @@ typedef enum */ #define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ #define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ -#define IRDA_CLEAR_NEF USART_ICR_NECF /*!< Noise detected Clear Flag */ +#define IRDA_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */ #define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ #define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ #define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ @@ -455,10 +508,19 @@ typedef enum * @param __HANDLE__ IRDA handle. * @retval None */ +#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1 +#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \ (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \ } while(0) +#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS */ /** @brief Flush the IRDA DR register. * @param __HANDLE__ specifies the IRDA Handle. @@ -629,13 +691,13 @@ typedef enum #define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) /** @brief Enable the IRDA one bit sample method. - * @param __HANDLE__ specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the IRDA one bit sample method. - * @param __HANDLE__ specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) @@ -657,7 +719,7 @@ typedef enum */ /* Private macros --------------------------------------------------------*/ -/** @defgroup IRDA_Private_Macros IRDA Private Macros +/** @addtogroup IRDA_Private_Macros * @{ */ @@ -717,41 +779,41 @@ typedef enum /** * @brief Ensure that IRDA frame length is valid. - * @param __LENGTH__ IRDA frame length. + * @param __LENGTH__ IRDA frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) - */ + */ #define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \ ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \ ((__LENGTH__) == IRDA_WORDLENGTH_9B)) /** * @brief Ensure that IRDA frame parity is valid. - * @param __PARITY__ IRDA frame parity. + * @param __PARITY__ IRDA frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) - */ + */ #define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \ ((__PARITY__) == IRDA_PARITY_EVEN) || \ ((__PARITY__) == IRDA_PARITY_ODD)) /** * @brief Ensure that IRDA communication mode is valid. - * @param __MODE__ IRDA communication mode. + * @param __MODE__ IRDA communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00)) + */ +#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) /** * @brief Ensure that IRDA power mode is valid. - * @param __MODE__ IRDA power mode. + * @param __MODE__ IRDA power mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ + */ #define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \ ((__MODE__) == IRDA_POWERMODE_NORMAL)) #if defined(USART_PRESC_PRESCALER) /** * @brief Ensure that IRDA clock Prescaler is valid. - * @param __CLOCKPRESCALER__ IRDA clock Prescaler value. + * @param __CLOCKPRESCALER__ IRDA clock Prescaler value. * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) */ #define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \ @@ -770,49 +832,49 @@ typedef enum /** * @brief Ensure that IRDA state is valid. - * @param __STATE__ IRDA state mode. + * @param __STATE__ IRDA state mode. * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) - */ + */ #define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \ ((__STATE__) == IRDA_STATE_ENABLE)) /** * @brief Ensure that IRDA associated UART/USART mode is valid. - * @param __MODE__: IRDA associated UART/USART mode. + * @param __MODE__ IRDA associated UART/USART mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ + */ #define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \ ((__MODE__) == IRDA_MODE_ENABLE)) /** * @brief Ensure that IRDA sampling rate is valid. - * @param __ONEBIT__ IRDA sampling rate. + * @param __ONEBIT__ IRDA sampling rate. * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) - */ + */ #define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \ ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE)) /** * @brief Ensure that IRDA DMA TX mode is valid. - * @param __DMATX__ IRDA DMA TX mode. + * @param __DMATX__ IRDA DMA TX mode. * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) - */ + */ #define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \ ((__DMATX__) == IRDA_DMA_TX_ENABLE)) /** * @brief Ensure that IRDA DMA RX mode is valid. - * @param __DMARX__ IRDA DMA RX mode. + * @param __DMARX__ IRDA DMA RX mode. * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) - */ + */ #define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \ ((__DMARX__) == IRDA_DMA_RX_ENABLE)) /** * @brief Ensure that IRDA request is valid. - * @param __PARAM__ IRDA request. + * @param __PARAM__ IRDA request. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) - */ + */ #define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \ ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \ ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST)) @@ -838,6 +900,12 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda); void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda); void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda); +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + /** * @} */ @@ -870,9 +938,9 @@ void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda); void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda); void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda); void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda); -void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda); -void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda); -void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda); +void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda); /** * @} diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda_ex.h index c7f135ba3f..c9d2fac7fe 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda_ex.h @@ -38,7 +38,7 @@ #define __STM32L4xx_HAL_IRDA_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -48,7 +48,7 @@ * @{ */ -/** @addtogroup IRDAEx +/** @defgroup IRDAEx IRDAEx * @{ */ @@ -68,9 +68,9 @@ * @param __CLOCKSOURCE__ output variable. * @retval IRDA clocking source, written in __CLOCKSOURCE__. */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) \ + || defined (STM32L496xx) || defined (STM32L4A6xx) \ + || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lptim.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lptim.h index b2130da1a3..4c87ae7f05 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lptim.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lptim.h @@ -152,7 +152,7 @@ typedef enum __HAL_LPTIM_StateTypeDef /** * @brief LPTIM handle Structure definition */ -typedef struct +typedef struct __LPTIM_HandleTypeDef { LPTIM_TypeDef *Instance; /*!< Register base address */ @@ -163,9 +163,43 @@ typedef struct HAL_LockTypeDef Lock; /*!< LPTIM locking object */ __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */ - + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp Init Callback */ + void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp DeInit Callback */ + void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare match Callback */ + void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload match Callback */ + void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< External trigger event detection Callback */ + void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare register write complete Callback */ + void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload register write complete Callback */ + void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Up-counting direction change Callback */ + void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Down-counting direction change Callback */ +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ }LPTIM_HandleTypeDef; +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL LPTIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_LPTIM_MSPINIT_CB_ID = 0x00U, /*!< LPTIM Base Msp Init Callback ID */ + HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, /*!< LPTIM Base Msp DeInit Callback ID */ + HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, /*!< Compare match Callback ID */ + HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U, /*!< Auto-reload match Callback ID */ + HAL_LPTIM_TRIGGER_CB_ID = 0x04U, /*!< External trigger event detection Callback ID */ + HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, /*!< Compare register write complete Callback ID */ + HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, /*!< Auto-reload register write complete Callback ID */ + HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< Up-counting direction change Callback ID */ + HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< Down-counting direction change Callback ID */ +} HAL_LPTIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< pointer to the LPTIM callback function */ + +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ /** * @} */ @@ -352,7 +386,15 @@ typedef struct * @param __HANDLE__: LPTIM handle * @retval None */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET) +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ /** * @brief Enable the LPTIM peripheral. @@ -557,6 +599,12 @@ void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim); void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim); void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + /* Peripheral State functions ************************************************/ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc.h index d8b6c472c3..57ec8024fe 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc.h @@ -31,17 +31,17 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_LTDC_H -#define __STM32L4xx_HAL_LTDC_H +#ifndef STM32L4xx_HAL_LTDC_H +#define STM32L4xx_HAL_LTDC_H #ifdef __cplusplus extern "C" { #endif -#if defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#if defined (LTDC) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -62,7 +62,7 @@ */ #define MAX_LAYER 2U -/** +/** * @brief LTDC color structure definition */ typedef struct @@ -73,13 +73,13 @@ typedef struct uint8_t Green; /*!< Configures the green value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ - uint8_t Red; /*!< Configures the red value. + uint8_t Red; /*!< Configures the red value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ uint8_t Reserved; /*!< Reserved 0xFF */ } LTDC_ColorTypeDef; -/** +/** * @brief LTDC Init structure definition */ typedef struct @@ -90,16 +90,16 @@ typedef struct uint32_t VSPolarity; /*!< configures the vertical synchronization polarity. This parameter can be one value of @ref LTDC_VS_POLARITY */ - uint32_t DEPolarity; /*!< configures the data enable polarity. + uint32_t DEPolarity; /*!< configures the data enable polarity. This parameter can be one of value of @ref LTDC_DE_POLARITY */ - uint32_t PCPolarity; /*!< configures the pixel clock polarity. + uint32_t PCPolarity; /*!< configures the pixel clock polarity. This parameter can be one of value of @ref LTDC_PC_POLARITY */ uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ - uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height. + uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width. @@ -108,7 +108,7 @@ typedef struct uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height. This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */ - uint32_t AccumulatedActiveW; /*!< configures the accumulated active width. + uint32_t AccumulatedActiveW; /*!< configures the accumulated active width. This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */ uint32_t AccumulatedActiveH; /*!< configures the accumulated active height. @@ -123,7 +123,7 @@ typedef struct LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */ } LTDC_InitTypeDef; -/** +/** * @brief LTDC Layer structure definition */ typedef struct @@ -140,7 +140,7 @@ typedef struct uint32_t WindowY1; /*!< Configures the Window vertical Stop Position. This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */ - uint32_t PixelFormat; /*!< Specifies the pixel format. + uint32_t PixelFormat; /*!< Specifies the pixel format. This parameter can be one of value of @ref LTDC_Pixelformat */ uint32_t Alpha; /*!< Specifies the constant alpha used for blending. @@ -149,24 +149,24 @@ typedef struct uint32_t Alpha0; /*!< Configures the default alpha value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ - uint32_t BlendingFactor1; /*!< Select the blending factor 1. + uint32_t BlendingFactor1; /*!< Select the blending factor 1. This parameter can be one of value of @ref LTDC_BlendingFactor1 */ - uint32_t BlendingFactor2; /*!< Select the blending factor 2. + uint32_t BlendingFactor2; /*!< Select the blending factor 2. This parameter can be one of value of @ref LTDC_BlendingFactor2 */ uint32_t FBStartAdress; /*!< Configures the color frame buffer address */ - uint32_t ImageWidth; /*!< Configures the color frame buffer line length. + uint32_t ImageWidth; /*!< Configures the color frame buffer line length. This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */ - uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer. + uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */ } LTDC_LayerCfgTypeDef; -/** +/** * @brief HAL LTDC State structures definition */ typedef enum @@ -178,10 +178,10 @@ typedef enum HAL_LTDC_STATE_ERROR = 0x04U /*!< LTDC state error */ }HAL_LTDC_StateTypeDef; -/** +/** * @brief LTDC handle Structure definition */ -typedef struct +typedef struct __LTDC_HandleTypeDef { LTDC_TypeDef *Instance; /*!< LTDC Register base address */ @@ -195,7 +195,41 @@ typedef struct __IO uint32_t ErrorCode; /*!< LTDC Error code */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + void (* LineEventCallback) (struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Line Event Callback */ + void (* ReloadEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Reload Event Callback */ + void (* ErrorCallback) (struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Error Callback */ + + void (* MspInitCallback) (struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp Init callback */ + void (* MspDeInitCallback) (struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp DeInit callback */ + +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + + } LTDC_HandleTypeDef; + +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL LTDC Callback ID enumeration definition + */ +typedef enum +{ + HAL_LTDC_MSPINIT_CB_ID = 0x00U, /*!< LTDC MspInit callback ID */ + HAL_LTDC_MSPDEINIT_CB_ID = 0x01U, /*!< LTDC MspDeInit callback ID */ + + HAL_LTDC_LINE_EVENT_CB_ID = 0x02U, /*!< LTDC Line Event Callback ID */ + HAL_LTDC_RELOAD_EVENT_CB_ID = 0x03U, /*!< LTDC Reload Callback ID */ + HAL_LTDC_ERROR_CB_ID = 0x04U /*!< LTDC Error Callback ID */ + +}HAL_LTDC_CallbackIDTypeDef; + +/** + * @brief HAL LTDC Callback pointer definition + */ +typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef * hltdc); /*!< pointer to an LTDC callback function */ + +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + /** * @} */ @@ -208,10 +242,13 @@ typedef struct /** @defgroup LTDC_Error_Code LTDC Error Code * @{ */ -#define HAL_LTDC_ERROR_NONE ((uint32_t)0x00000000U) /*!< LTDC No error */ -#define HAL_LTDC_ERROR_TE ((uint32_t)0x00000001U) /*!< LTDC Transfer error */ -#define HAL_LTDC_ERROR_FU ((uint32_t)0x00000002U) /*!< LTDC FIFO Underrun */ -#define HAL_LTDC_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< LTDC Timeout error */ +#define HAL_LTDC_ERROR_NONE 0x00000000U /*!< LTDC No error */ +#define HAL_LTDC_ERROR_TE 0x00000001U /*!< LTDC Transfer error */ +#define HAL_LTDC_ERROR_FU 0x00000002U /*!< LTDC FIFO Underrun */ +#define HAL_LTDC_ERROR_TIMEOUT 0x00000020U /*!< LTDC Timeout error */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +#define HAL_LTDC_ERROR_INVALID_CALLBACK 0x00000040U /*!< LTDC Invalid Callback error */ +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ /** * @} */ @@ -219,8 +256,8 @@ typedef struct /** @defgroup LTDC_Layer LTDC Layer * @{ */ -#define LTDC_LAYER_1 ((uint32_t)0x00000000U) /*!< LTDC Layer 1 */ -#define LTDC_LAYER_2 ((uint32_t)0x00000001U) /*!< LTDC Layer 2 */ +#define LTDC_LAYER_1 0x00000000U /*!< LTDC Layer 1 */ +#define LTDC_LAYER_2 0x00000001U /*!< LTDC Layer 2 */ /** * @} */ @@ -228,7 +265,7 @@ typedef struct /** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY * @{ */ -#define LTDC_HSPOLARITY_AL ((uint32_t)0x00000000U) /*!< Horizontal Synchronization is active low. */ +#define LTDC_HSPOLARITY_AL 0x00000000U /*!< Horizontal Synchronization is active low. */ #define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */ /** * @} @@ -237,16 +274,16 @@ typedef struct /** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY * @{ */ -#define LTDC_VSPOLARITY_AL ((uint32_t)0x00000000U) /*!< Vertical Synchronization is active low. */ +#define LTDC_VSPOLARITY_AL 0x00000000U /*!< Vertical Synchronization is active low. */ #define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */ /** * @} */ - + /** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY * @{ */ -#define LTDC_DEPOLARITY_AL ((uint32_t)0x00000000U) /*!< Data Enable, is active low. */ +#define LTDC_DEPOLARITY_AL 0x00000000U /*!< Data Enable, is active low. */ #define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */ /** * @} @@ -255,7 +292,7 @@ typedef struct /** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY * @{ */ -#define LTDC_PCPOLARITY_IPC ((uint32_t)0x00000000U) /*!< input pixel clock. */ +#define LTDC_PCPOLARITY_IPC 0x00000000U /*!< input pixel clock. */ #define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */ /** * @} @@ -264,7 +301,7 @@ typedef struct /** @defgroup LTDC_SYNC LTDC SYNC * @{ */ -#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16U) /*!< Horizontal synchronization width. */ +#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16U) /*!< Horizontal synchronization width. */ #define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization height. */ /** * @} @@ -273,16 +310,16 @@ typedef struct /** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR * @{ */ -#define LTDC_COLOR ((uint32_t)0x000000FFU) /*!< Color mask */ +#define LTDC_COLOR 0x000000FFU /*!< Color mask */ /** * @} */ - + /** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1 * @{ */ -#define LTDC_BLENDING_FACTOR1_CA ((uint32_t)0x00000400U) /*!< Blending factor : Cte Alpha */ -#define LTDC_BLENDING_FACTOR1_PAxCA ((uint32_t)0x00000600U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/ +#define LTDC_BLENDING_FACTOR1_CA 0x00000400U /*!< Blending factor : Cte Alpha */ +#define LTDC_BLENDING_FACTOR1_PAxCA 0x00000600U /*!< Blending factor : Cte Alpha x Pixel Alpha*/ /** * @} */ @@ -290,23 +327,23 @@ typedef struct /** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2 * @{ */ -#define LTDC_BLENDING_FACTOR2_CA ((uint32_t)0x00000005U) /*!< Blending factor : Cte Alpha */ -#define LTDC_BLENDING_FACTOR2_PAxCA ((uint32_t)0x00000007U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/ +#define LTDC_BLENDING_FACTOR2_CA 0x00000005U /*!< Blending factor : Cte Alpha */ +#define LTDC_BLENDING_FACTOR2_PAxCA 0x00000007U /*!< Blending factor : Cte Alpha x Pixel Alpha*/ /** * @} */ - + /** @defgroup LTDC_Pixelformat LTDC Pixel format * @{ */ -#define LTDC_PIXEL_FORMAT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_RGB565 ((uint32_t)0x00000002U) /*!< RGB565 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_ARGB1555 ((uint32_t)0x00000003U) /*!< ARGB1555 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_ARGB4444 ((uint32_t)0x00000004U) /*!< ARGB4444 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_L8 ((uint32_t)0x00000005U) /*!< L8 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_AL44 ((uint32_t)0x00000006U) /*!< AL44 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_AL88 ((uint32_t)0x00000007U) /*!< AL88 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */ /** * @} */ @@ -325,7 +362,7 @@ typedef struct #define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16U) /*!< LTDC Layer stop position */ #define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */ -#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */ +#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */ #define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */ /** * @} @@ -341,7 +378,7 @@ typedef struct /** * @} */ - + /** @defgroup LTDC_Flags LTDC Flags * @{ */ @@ -364,7 +401,7 @@ typedef struct /** * @} - */ + */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup LTDC_Exported_Macros LTDC Exported Macros @@ -375,7 +412,15 @@ typedef struct * @param __HANDLE__ LTDC handle * @retval None */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_LTDC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET) +#endif /*USE_HAL_LTDC_REGISTER_CALLBACKS */ /** * @brief Enable the LTDC. @@ -429,10 +474,10 @@ typedef struct * @param __HANDLE__ LTDC handle * @param __FLAG__ Get the specified flag. * This parameter can be any combination of the following values: - * @arg LTDC_FLAG_LI: Line Interrupt flag + * @arg LTDC_FLAG_LI: Line Interrupt flag * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag * @arg LTDC_FLAG_TE: Transfer Error interrupt flag - * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag + * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag * @retval The state of FLAG (SET or RESET). */ #define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) @@ -442,10 +487,10 @@ typedef struct * @param __HANDLE__ LTDC handle * @param __FLAG__ Specify the flag to clear. * This parameter can be any combination of the following values: - * @arg LTDC_FLAG_LI: Line Interrupt flag + * @arg LTDC_FLAG_LI: Line Interrupt flag * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag * @arg LTDC_FLAG_TE: Transfer Error interrupt flag - * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag + * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag * @retval None */ #define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) @@ -453,9 +498,9 @@ typedef struct /** * @brief Enables the specified LTDC interrupts. * @param __HANDLE__ LTDC handle - * @param __INTERRUPT__ Specify the LTDC interrupt sources to be enabled. + * @param __INTERRUPT__ Specify the LTDC interrupt sources to be enabled. * This parameter can be any combination of the following values: - * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_LI: Line Interrupt flag * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag * @arg LTDC_IT_TE: Transfer Error interrupt flag * @arg LTDC_IT_RR: Register Reload Interrupt Flag @@ -466,9 +511,9 @@ typedef struct /** * @brief Disables the specified LTDC interrupts. * @param __HANDLE__ LTDC handle - * @param __INTERRUPT__ Specify the LTDC interrupt sources to be disabled. + * @param __INTERRUPT__ Specify the LTDC interrupt sources to be disabled. * This parameter can be any combination of the following values: - * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_LI: Line Interrupt flag * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag * @arg LTDC_IT_TE: Transfer Error interrupt flag * @arg LTDC_IT_RR: Register Reload Interrupt Flag @@ -481,7 +526,7 @@ typedef struct * @param __HANDLE__ LTDC handle * @param __INTERRUPT__ Specify the LTDC interrupt source to check. * This parameter can be one of the following values: - * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_LI: Line Interrupt flag * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag * @arg LTDC_IT_TE: Transfer Error interrupt flag * @arg LTDC_IT_RR: Register Reload Interrupt Flag @@ -510,6 +555,13 @@ void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc); void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc); void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc); void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + /** * @} */ @@ -582,7 +634,7 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); /** @defgroup LTDC_Private_Macros LTDC Private Macros * @{ */ -#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__))))) +#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84U + (0x80U*(__LAYER__))))) #define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER) #define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH)) #define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH)) @@ -619,7 +671,7 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); #define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING)) /** * @} - */ + */ /* Private functions ---------------------------------------------------------*/ /** @defgroup LTDC_Private_Functions LTDC Private Functions @@ -632,18 +684,18 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); /** * @} - */ + */ /** * @} */ -#endif /* STM32L4R7xx || STM32L4R9xx || STM32L4R7xx || STM32L4S9xx */ +#endif /* LTDC */ #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_HAL_LTDC_H */ +#endif /* STM32L4xx_HAL_LTDC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc_ex.h index 8bc7d77d96..b1363ee02f 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc_ex.h @@ -31,17 +31,17 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_LTDC_EX_H -#define __STM32L4xx_HAL_LTDC_EX_H +#ifndef STM32L4xx_HAL_LTDC_EX_H +#define STM32L4xx_HAL_LTDC_EX_H #ifdef __cplusplus extern "C" { #endif -#if defined (STM32L4R9xx) || defined (STM32L4S9xx) +#if defined (LTDC) && defined (DSI) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -55,7 +55,7 @@ * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -70,11 +70,11 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg); /** * @} - */ - + */ + /** * @} - */ + */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -84,18 +84,18 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD /** * @} - */ + */ /** * @} */ -#endif /* STM32L4R9xx || STM32L4S9xx */ - +#endif /* LTDC && DSI */ + #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_HAL_LTDC_EX_H */ +#endif /* STM32L4xx_HAL_LTDC_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_nand.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_nand.h index 43763512a1..d225ab6d56 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_nand.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_nand.h @@ -41,9 +41,7 @@ extern "C" { #endif -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(FMC_BANK3) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_ll_fmc.h" @@ -54,69 +52,6 @@ /** @addtogroup NAND * @{ - */ - -/** @addtogroup NAND_Private_Constants - * @{ - */ - -#define NAND_DEVICE FMC_BANK3 -#define NAND_WRITE_TIMEOUT ((uint32_t)1000) - -#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */ -#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */ - -#define NAND_CMD_AREA_A ((uint8_t)0x00) -#define NAND_CMD_AREA_B ((uint8_t)0x01) -#define NAND_CMD_AREA_C ((uint8_t)0x50) -#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) - -#define NAND_CMD_WRITE0 ((uint8_t)0x80) -#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) -#define NAND_CMD_ERASE0 ((uint8_t)0x60) -#define NAND_CMD_ERASE1 ((uint8_t)0xD0) -#define NAND_CMD_READID ((uint8_t)0x90) -#define NAND_CMD_STATUS ((uint8_t)0x70) -#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) -#define NAND_CMD_RESET ((uint8_t)0xFF) - -/* NAND memory status */ -#define NAND_VALID_ADDRESS ((uint32_t)0x00000100) -#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200) -#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400) -#define NAND_BUSY ((uint32_t)0x00000000) -#define NAND_ERROR ((uint32_t)0x00000001) -#define NAND_READY ((uint32_t)0x00000040) - -/** - * @} - */ - -/** @addtogroup NAND_Private_Macros - * @{ - */ - -/** - * @brief NAND memory address computation. - * @param __ADDRESS__: NAND memory address. - * @param __HANDLE__: NAND handle. - * @retval NAND Raw address value - */ -#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) (((__ADDRESS__)->Page) + \ - (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize * ((__HANDLE__)->Info.PageSize + (__HANDLE__)->Info.SpareAreaSize)))) - -/** - * @brief NAND memory address cycling. - * @param __ADDRESS__: NAND memory address. - * @retval NAND address cycling value. - */ -#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ -#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ -#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ -#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ - -/** - * @} */ /* Exported typedef ----------------------------------------------------------*/ @@ -125,25 +60,24 @@ * @{ */ -/** +/** * @brief HAL NAND State structures definition */ typedef enum { - HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */ - HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */ - HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */ - HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */ + HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */ + HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ + HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ + HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */ }HAL_NAND_StateTypeDef; - -/** + +/** * @brief NAND Memory electronic signature Structure definition */ typedef struct { /*State = HAL_NAND_STATE_RESET) @@ -221,43 +165,55 @@ typedef struct /** @addtogroup NAND_Exported_Functions NAND Exported Functions * @{ */ - -/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions + +/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ /* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); -HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); -void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); -void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); -void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); -void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); +HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); +HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); + +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); + +HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); + +void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); +void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); +void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); +void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); /** * @} */ - -/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions + +/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions * @{ */ /* IO operation functions ****************************************************/ -HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); -HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); -HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); -uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); -uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); + +HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); + +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); + +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); + +HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); + +uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); /** * @} */ -/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions +/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions * @{ */ @@ -269,34 +225,108 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, /** * @} */ - -/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions + +/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions * @{ */ - /* NAND State functions *******************************************************/ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup NAND_Private_Constants NAND Private Constants + * @{ + */ +#define NAND_DEVICE FMC_BANK3 +#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U) + +#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */ +#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */ + +#define NAND_CMD_AREA_A ((uint8_t)0x00U) +#define NAND_CMD_AREA_B ((uint8_t)0x01U) +#define NAND_CMD_AREA_C ((uint8_t)0x50U) +#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U) + +#define NAND_CMD_WRITE0 ((uint8_t)0x80U) +#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U) +#define NAND_CMD_ERASE0 ((uint8_t)0x60U) +#define NAND_CMD_ERASE1 ((uint8_t)0xD0U) +#define NAND_CMD_READID ((uint8_t)0x90U) +#define NAND_CMD_STATUS ((uint8_t)0x70U) +#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU) +#define NAND_CMD_RESET ((uint8_t)0xFFU) + +/* NAND memory status */ +#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U) +#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U) +#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U) +#define NAND_BUSY ((uint32_t)0x00000000U) +#define NAND_ERROR ((uint32_t)0x00000001U) +#define NAND_READY ((uint32_t)0x00000040U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup NAND_Private_Macros NAND Private Macros + * @{ + */ + +/** + * @brief NAND memory address computation. + * @param __ADDRESS__ NAND memory address. + * @param __HANDLE__ NAND handle. + * @retval NAND Raw address value + */ +#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) (((__ADDRESS__)->Page) + \ + (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) + +#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) + +/** + * @brief NAND memory address cycling. + * @param __ADDRESS__ NAND memory address. + * @retval NAND address cycling value. + */ +#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ +#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ +#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ +#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ + +/** + * @brief NAND memory Columns cycling. + * @param __ADDRESS__ NAND memory address. + * @retval NAND Column address cycling value. + */ +#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */ +#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* FMC_BANK3 */ #ifdef __cplusplus } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_nor.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_nor.h index df2baca9d4..782224b5aa 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_nor.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_nor.h @@ -31,7 +31,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L4xx_HAL_NOR_H @@ -41,9 +41,7 @@ extern "C" { #endif -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(FMC_BANK1) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_ll_fmc.h" @@ -55,64 +53,6 @@ /** @addtogroup NOR * @{ - */ - -/** @addtogroup NOR_Private_Constants - * @{ - */ - -/* NOR device IDs addresses */ -#define MC_ADDRESS ((uint16_t)0x0000) -#define DEVICE_CODE1_ADDR ((uint16_t)0x0001) -#define DEVICE_CODE2_ADDR ((uint16_t)0x000E) -#define DEVICE_CODE3_ADDR ((uint16_t)0x000F) - -/* NOR CFI IDs addresses */ -#define CFI1_ADDRESS ((uint16_t)0x10) -#define CFI2_ADDRESS ((uint16_t)0x11) -#define CFI3_ADDRESS ((uint16_t)0x12) -#define CFI4_ADDRESS ((uint16_t)0x13) - -/* NOR memory data width */ -#define NOR_MEMORY_8B ((uint8_t)0x0) -#define NOR_MEMORY_16B ((uint8_t)0x1) - -/* NOR memory device read/write start address */ -#define NOR_MEMORY_ADRESS1 FMC_BANK1_1 -#define NOR_MEMORY_ADRESS2 FMC_BANK1_2 -#define NOR_MEMORY_ADRESS3 FMC_BANK1_3 -#define NOR_MEMORY_ADRESS4 FMC_BANK1_4 - -/** - * @} - */ - -/** @addtogroup NOR_Private_Macros - * @{ - */ - -/** - * @brief NOR memory address shifting. - * @param __NOR_ADDRESS: NOR base address - * @param __NOR_MEMORY_WIDTH_: NOR memory width - * @param __ADDRESS__: NOR memory address - * @retval NOR shifted address value - */ -#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ - ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ - ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \ - ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) - -/** - * @brief NOR memory write data to specified address. - * @param __ADDRESS__: NOR memory address - * @param __DATA__: Data to write - * @retval None - */ -#define NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)) - -/** - * @} */ /* Exported typedef ----------------------------------------------------------*/ @@ -120,16 +60,16 @@ * @{ */ -/** - * @brief HAL SRAM State structures definition - */ +/** + * @brief HAL SRAM State structures definition + */ typedef enum -{ - HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */ - HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */ - HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */ - HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */ - HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */ +{ + HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */ + HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */ + HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */ + HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */ + HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */ }HAL_NOR_StateTypeDef; /** @@ -137,11 +77,11 @@ typedef enum */ typedef enum { - HAL_NOR_STATUS_SUCCESS = 0, + HAL_NOR_STATUS_SUCCESS = 0U, HAL_NOR_STATUS_ONGOING, HAL_NOR_STATUS_ERROR, HAL_NOR_STATUS_TIMEOUT -}HAL_NOR_StatusTypeDef; +}HAL_NOR_StatusTypeDef; /** * @brief FMC NOR ID typedef @@ -154,10 +94,10 @@ typedef struct uint16_t Device_Code2; - uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory. - These codes can be accessed by performing read operations with specific - control signals and addresses set.They can also be accessed by issuing - an Auto Select command. */ + uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory. + These codes can be accessed by performing read operations with specific + control signals and addresses set.They can also be accessed by issuing + an Auto Select command. */ }NOR_IDTypeDef; /** @@ -165,20 +105,22 @@ typedef struct */ typedef struct { + /*!< Defines the information stored in the memory's Common flash interface + which contains a description of various electrical and timing parameters, + density information and functions supported by the memory */ + uint16_t CFI_1; uint16_t CFI_2; uint16_t CFI_3; - uint16_t CFI_4; /*!< Defines the information stored in the memory's Common flash interface - which contains a description of various electrical and timing parameters, - density information and functions supported by the memory. */ + uint16_t CFI_4; }NOR_CFITypeDef; -/** +/** * @brief NOR handle Structure definition - */ + */ typedef struct { FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ @@ -190,9 +132,7 @@ typedef struct HAL_LockTypeDef Lock; /*!< NOR locking object */ __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */ - -}NOR_HandleTypeDef; - +}NOR_HandleTypeDef; /** * @} */ @@ -202,13 +142,11 @@ typedef struct /** @defgroup NOR_Exported_Macros NOR Exported Macros * @{ */ - -/** @brief Reset NOR handle state. - * @param __HANDLE__: NOR handle +/** @brief Reset NOR handle state + * @param __HANDLE__ specifies the NOR handle. * @retval None */ #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) - /** * @} */ @@ -218,7 +156,7 @@ typedef struct * @{ */ -/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions +/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ @@ -228,12 +166,11 @@ HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout); - /** * @} */ -/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions +/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions * @{ */ @@ -249,34 +186,96 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address); HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address); HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI); - /** * @} */ - -/** @addtogroup NOR_Exported_Functions_Group3 Peripheral Control functions + +/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions * @{ */ /* NOR Control functions *****************************************************/ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor); HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); - /** * @} - */ - -/** @addtogroup NOR_Exported_Functions_Group4 Peripheral State functions + */ + +/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions * @{ */ /* NOR State functions ********************************************************/ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor); HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); +/** + * @} + */ /** * @} - */ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup NOR_Private_Constants NOR Private Constants + * @{ + */ +/* NOR device IDs addresses */ +#define MC_ADDRESS ((uint16_t)0x0000U) +#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U) +#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU) +#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU) + +/* NOR CFI IDs addresses */ +#define CFI1_ADDRESS ((uint16_t)0x61U) +#define CFI2_ADDRESS ((uint16_t)0x62U) +#define CFI3_ADDRESS ((uint16_t)0x63U) +#define CFI4_ADDRESS ((uint16_t)0x64U) + +/* NOR operation wait timeout */ +#define NOR_TMEOUT ((uint16_t)0xFFFFU) + +/* NOR memory data width */ +#define NOR_MEMORY_8B ((uint8_t)0x0U) +#define NOR_MEMORY_16B ((uint8_t)0x1U) + +/* NOR memory device read/write start address */ +#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U) +#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U) +#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U) +#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup NOR_Private_Macros NOR Private Macros + * @{ + */ +/** + * @brief NOR memory address shifting. + * @param __NOR_ADDRESS NOR base address + * @param __NOR_MEMORY_WIDTH_ NOR memory width + * @param __ADDRESS__ NOR memory address + * @retval NOR shifted address value + */ +#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ + ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ + ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \ + ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) + +/** + * @brief NOR memory write data to specified address. + * @param __ADDRESS__ NOR memory address + * @param __DATA__ Data to write + * @retval None + */ +#define NOR_WRITE(__ADDRESS__, __DATA__) do{ \ + (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \ + __DSB(); \ + } while(0) /** * @} @@ -284,15 +283,13 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres /** * @} - */ + */ /** * @} */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* FMC_BANK1 */ #ifdef __cplusplus } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp.h index d1a913d9e4..b0df3d1746 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp.h @@ -135,7 +135,7 @@ typedef enum /** * @brief OPAMP Handle Structure definition */ -typedef struct +typedef struct __OPAMP_HandleTypeDef { OPAMP_TypeDef *Instance; /*!< OPAMP instance's registers base address */ OPAMP_InitTypeDef Init; /*!< OPAMP required parameters */ @@ -143,6 +143,11 @@ typedef struct HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_OPAMP_StateTypeDef State; /*!< OPAMP communication state */ +#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) +void (* MspInitCallback) (struct __OPAMP_HandleTypeDef *hopamp); +void (* MspDeInitCallback) (struct __OPAMP_HandleTypeDef *hopamp); +#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ + } OPAMP_HandleTypeDef; /** @@ -155,6 +160,24 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef; * @} */ +#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) +/** + * @brief HAL OPAMP Callback ID enumeration definition + */ +typedef enum +{ + HAL_OPAMP_MSP_INIT_CB_ID = 0x01U, /*!< OPAMP MspInit Callback ID */ + HAL_OPAMP_MSP_DEINIT_CB_ID = 0x02U, /*!< OPAMP MspDeInit Callback ID */ + HAL_OPAMP_ALL_CB_ID = 0x03U /*!< OPAMP All ID */ +}HAL_OPAMP_CallbackIDTypeDef; + +/** + * @brief HAL OPAMP Callback pointer definition + */ +typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); +#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ + + /* Exported constants --------------------------------------------------------*/ /** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants @@ -282,7 +305,17 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef; * @param __HANDLE__: OPAMP handle. * @retval None */ +#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) +#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_OPAMP_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET) +#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ + + /** * @} @@ -395,6 +428,12 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp); */ /* Peripheral Control functions ************************************************/ +#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) +/* OPAMP callback registering/unregistering */ +HAL_StatusTypeDef HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackID, pOPAMP_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ + HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp); HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset); diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ospi.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ospi.h index 7910439c6e..eef2f741b6 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ospi.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ospi.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_OSPI_H -#define __STM32L4xx_HAL_OSPI_H +#ifndef STM32L4xx_HAL_OSPI_H +#define STM32L4xx_HAL_OSPI_H #ifdef __cplusplus extern "C" { @@ -102,7 +102,7 @@ typedef struct /** * @brief HAL OSPI Handle Structure definition */ -typedef struct +typedef struct __OSPI_HandleTypeDef { OCTOSPI_TypeDef *Instance; /* OSPI registers base address */ OSPI_InitTypeDef Init; /* OSPI initialization parameters */ @@ -113,6 +113,21 @@ typedef struct __IO uint32_t State; /* Internal state of the OSPI HAL driver */ __IO uint32_t ErrorCode; /* Error code in case of HAL driver internal error */ uint32_t Timeout; /* Timeout used for the OSPI external device access */ +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) + void (* ErrorCallback) (struct __OSPI_HandleTypeDef *hospi); + void (* AbortCpltCallback) (struct __OSPI_HandleTypeDef *hospi); + void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi); + void (* CmdCpltCallback) (struct __OSPI_HandleTypeDef *hospi); + void (* RxCpltCallback) (struct __OSPI_HandleTypeDef *hospi); + void (* TxCpltCallback) (struct __OSPI_HandleTypeDef *hospi); + void (* RxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi); + void (* TxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi); + void (* StatusMatchCallback) (struct __OSPI_HandleTypeDef *hospi); + void (* TimeOutCallback) (struct __OSPI_HandleTypeDef *hospi); + + void (* MspInitCallback) (struct __OSPI_HandleTypeDef *hospi); + void (* MspDeInitCallback) (struct __OSPI_HandleTypeDef *hospi); +#endif }OSPI_HandleTypeDef; /** @@ -245,6 +260,32 @@ typedef struct This parameter can be a value of @ref OSPIM_IOPort */ }OSPIM_CfgTypeDef; +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +/** + * @brief HAL OSPI Callback ID enumeration definition + */ +typedef enum +{ + HAL_OSPI_ERROR_CB_ID = 0x00U, /*!< OSPI Error Callback ID */ + HAL_OSPI_ABORT_CB_ID = 0x01U, /*!< OSPI Abort Callback ID */ + HAL_OSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< OSPI FIFO Threshold Callback ID */ + HAL_OSPI_CMD_CPLT_CB_ID = 0x03U, /*!< OSPI Command Complete Callback ID */ + HAL_OSPI_RX_CPLT_CB_ID = 0x04U, /*!< OSPI Rx Complete Callback ID */ + HAL_OSPI_TX_CPLT_CB_ID = 0x05U, /*!< OSPI Tx Complete Callback ID */ + HAL_OSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< OSPI Rx Half Complete Callback ID */ + HAL_OSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< OSPI Tx Half Complete Callback ID */ + HAL_OSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< OSPI Status Match Callback ID */ + HAL_OSPI_TIMEOUT_CB_ID = 0x09U, /*!< OSPI Timeout Callback ID */ + + HAL_OSPI_MSP_INIT_CB_ID = 0x0AU, /*!< OSPI MspInit Callback ID */ + HAL_OSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< OSPI MspDeInit Callback ID */ +}HAL_OSPI_CallbackIDTypeDef; + +/** + * @brief HAL OSPI Callback pointer definition + */ +typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); +#endif /** * @} */ @@ -283,6 +324,9 @@ typedef struct #define HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ #define HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */ #define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */ +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#define HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid callback error */ +#endif /** * @} */ @@ -618,7 +662,15 @@ typedef struct * @param __HANDLE__: OSPI handle. * @retval None */ +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_OSPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET) +#endif /** @brief Enable the OSPI peripheral. * @param __HANDLE__: specifies the OSPI Handle. @@ -685,7 +737,7 @@ typedef struct * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag * @retval None */ -#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) ? SET : RESET) +#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) /** @brief Clears the specified OSPI's flag status. * @param __HANDLE__: specifies the OSPI Handle. @@ -767,6 +819,11 @@ void HAL_OSPI_StatusMatchCallback (OSPI_HandleTypeDef *hospi); /* OSPI memory-mapped mode functions */ void HAL_OSPI_TimeOutCallback (OSPI_HandleTypeDef *hospi); +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +/* OSPI callback registering/unregistering */ +HAL_StatusTypeDef HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, pOSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID); +#endif /** * @} */ @@ -806,7 +863,7 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, /** @cond 0 */ -#define IS_OSPI_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) >= 1) && ((THRESHOLD) <= 32)) +#define IS_OSPI_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) >= 1U) && ((THRESHOLD) <= 32U)) #define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \ ((MODE) == HAL_OSPI_DUALQUAD_ENABLE)) @@ -815,9 +872,9 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \ ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS)) -#define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 32)) +#define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 32U)) -#define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1) && ((TIME) <= 8)) +#define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1U) && ((TIME) <= 8U)) #define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \ ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE)) @@ -831,7 +888,7 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, ((SIZE) == HAL_OSPI_WRAP_64_BYTES) || \ ((SIZE) == HAL_OSPI_WRAP_128_BYTES)) -#define IS_OSPI_CLK_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 256)) +#define IS_OSPI_CLK_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 256U)) #define IS_OSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE) || \ ((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE)) @@ -894,12 +951,12 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, ((MODE) == HAL_OSPI_DATA_4_LINES) || \ ((MODE) == HAL_OSPI_DATA_8_LINES)) -#define IS_OSPI_NUMBER_DATA(NUMBER) ((NUMBER) >= 1) +#define IS_OSPI_NUMBER_DATA(NUMBER) ((NUMBER) >= 1U) #define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \ ((MODE) == HAL_OSPI_DATA_DTR_ENABLE)) -#define IS_OSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31) +#define IS_OSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U) #define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \ ((MODE) == HAL_OSPI_DQS_ENABLE)) @@ -907,9 +964,9 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, #define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \ ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD)) -#define IS_OSPI_RW_RECOVERY_TIME(NUMBER) ((NUMBER) <= 255) +#define IS_OSPI_RW_RECOVERY_TIME(NUMBER) ((NUMBER) <= 255U) -#define IS_OSPI_ACCESS_TIME(NUMBER) ((NUMBER) <= 255) +#define IS_OSPI_ACCESS_TIME(NUMBER) ((NUMBER) <= 255U) #define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \ ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE)) @@ -926,18 +983,18 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, #define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \ ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE)) -#define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFF) +#define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU) -#define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4)) +#define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) #define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \ ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE)) -#define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF) +#define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) -#define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31) +#define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31U) -#define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1) && ((NUMBER) <= 2)) +#define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 2U)) #define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \ ((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \ @@ -963,6 +1020,6 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, } #endif -#endif /* __STM32L4xx_HAL_OSPI_H */ +#endif /* STM32L4xx_HAL_OSPI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h index 1ef9034379..1f13d6b798 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h @@ -31,42 +31,38 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L4xx_HAL_PCD_H #define __STM32L4xx_HAL_PCD_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_ll_usb.h" - + +#if defined (USB) || defined (USB_OTG_FS) || defined (USB_OTG_HS) + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ /** @addtogroup PCD * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup PCD_Exported_Types PCD Exported Types * @{ */ - /** - * @brief PCD State structure definition - */ -typedef enum +/** + * @brief PCD State structure definition + */ +typedef enum { HAL_PCD_STATE_RESET = 0x00, HAL_PCD_STATE_READY = 0x01, @@ -76,13 +72,30 @@ typedef enum } PCD_StateTypeDef; /* Device LPM suspend state */ -typedef enum +typedef enum { LPM_L0 = 0x00, /* on */ LPM_L1 = 0x01, /* LPM L1 sleep */ LPM_L2 = 0x02, /* suspend */ LPM_L3 = 0x03, /* off */ -}PCD_LPM_StateTypeDef; +} PCD_LPM_StateTypeDef; + +typedef enum +{ + PCD_LPM_L0_ACTIVE = 0x00, /* on */ + PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */ +} PCD_LPM_MsgTypeDef; + +typedef enum +{ + PCD_BCD_ERROR = 0xFF, + PCD_BCD_CONTACT_DETECTION = 0xFE, + PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, + PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC, + PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, + PCD_BCD_DISCOVERY_COMPLETED = 0x00, + +} PCD_BCD_MsgTypeDef; #if defined (USB) /** @@ -93,61 +106,81 @@ typedef enum PCD_EP_DBUF_OUT, PCD_EP_DBUF_IN, PCD_EP_DBUF_ERR, -}PCD_EP_DBUF_DIR; +} PCD_EP_DBUF_DIR; /** * @brief PCD endpoint buffer number */ -typedef enum +typedef enum { PCD_EP_NOBUF, PCD_EP_BUF0, PCD_EP_BUF1 -}PCD_EP_BUF_NUM; +} PCD_EP_BUF_NUM; #endif /* USB */ -#if defined (USB_OTG_FS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) typedef USB_OTG_GlobalTypeDef PCD_TypeDef; typedef USB_OTG_CfgTypeDef PCD_InitTypeDef; typedef USB_OTG_EPTypeDef PCD_EPTypeDef; -#endif /* USB_OTG_FS */ +#endif /* USB_OTG_FS || USB_OTG_HS */ #if defined (USB) typedef USB_TypeDef PCD_TypeDef; typedef USB_CfgTypeDef PCD_InitTypeDef; typedef USB_EPTypeDef PCD_EPTypeDef; -#endif /* USB */ +#endif /* USB */ -/** - * @brief PCD Handle Structure definition - */ -typedef struct +/** + * @brief PCD Handle Structure definition + */ +typedef struct __PCD_HandleTypeDef { - PCD_TypeDef *Instance; /*!< Register base address */ + PCD_TypeDef *Instance; /*!< Register base address */ PCD_InitTypeDef Init; /*!< PCD required parameters */ - __IO uint8_t USB_Address; /*!< USB Address: not used by USB OTG FS */ - PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */ - PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */ + __IO uint8_t USB_Address; /*!< USB Address */ + PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ HAL_LockTypeDef Lock; /*!< PCD peripheral status */ __IO PCD_StateTypeDef State; /*!< PCD communication state */ + __IO uint32_t ErrorCode; /*!< PCD Error code */ uint32_t Setup[12]; /*!< Setup packet buffer */ - PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ + PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ uint32_t BESL; - - - uint32_t lpm_active; /*!< Enable or disable the Link Power Management . - This parameter can be set to ENABLE or DISABLE */ - - uint32_t battery_charging_active; /*!< Enable or disable Battery charging. - This parameter can be set to ENABLE or DISABLE */ - void *pData; /*!< Pointer to upper stack Handler */ - + + + uint32_t lpm_active; /*!< Enable or disable the Link Power Management . + This parameter can be set to ENABLE or DISABLE */ + + uint32_t battery_charging_active; /*!< Enable or disable Battery charging. + This parameter can be set to ENABLE or DISABLE */ + void *pData; /*!< Pointer to upper stack Handler */ + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */ + void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */ + void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */ + void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */ + void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */ + void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */ + void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */ + + void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */ + void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */ + void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */ + void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */ + void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< USB OTG PCD BCD callback */ + void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */ + + void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */ + void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */ +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } PCD_HandleTypeDef; /** * @} */ - + /* Include PCD HAL Extended module */ #include "stm32l4xx_hal_pcd_ex.h" @@ -159,15 +192,21 @@ typedef struct /** @defgroup PCD_Speed PCD Speed * @{ */ -#define PCD_SPEED_FULL 1 +#if defined (USB_OTG_HS) +#define PCD_SPEED_HIGH 0U +#define PCD_SPEED_HIGH_IN_FULL 1U +#endif +#define PCD_SPEED_FULL 2U /** * @} */ - + /** @defgroup PCD_PHY_Module PCD PHY Module * @{ */ -#define PCD_PHY_EMBEDDED 1 +#define PCD_PHY_ULPI 1U +#define PCD_PHY_EMBEDDED 2U +#define PCD_PHY_UTMI 3U /** * @} */ @@ -176,66 +215,64 @@ typedef struct * @{ */ #ifndef USBD_FS_TRDT_VALUE - #define USBD_FS_TRDT_VALUE 5 -#endif /* USBD_FS_TRDT_VALUE */ +#define USBD_FS_TRDT_VALUE 5U +#endif /* USBD_HS_TRDT_VALUE */ +/** + * @} + */ + +/** @defgroup PCD_Error_Code_definition PCD Error Code definition + * @brief PCD Error Code definition + * @{ + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */ +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + /** * @} */ /** * @} - */ - + */ + /* Exported macros -----------------------------------------------------------*/ /** @defgroup PCD_Exported_Macros PCD Exported Macros * @brief macros to handle interrupts and specific clock configurations * @{ */ -#if defined (USB_OTG_FS) -#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance) - +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) + #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) -#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0) +#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \ ~(USB_OTG_PCGCCTL_STOPCLK) #define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK - -#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10) - + +#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) + #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE #define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR1 & (USB_OTG_FS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR1 = USB_OTG_FS_WAKEUP_EXTI_LINE -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do {\ - EXTI->FTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ - } while(0) - -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do {\ - EXTI->FTSR1 |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - } while(0) - -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do {\ - EXTI->RTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->FTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ - EXTI->FTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ - } while(0) - -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= USB_OTG_FS_WAKEUP_EXTI_LINE) - -#endif /* USB_OTG_FS */ +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ + do { \ + EXTI->FTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \ + EXTI->RTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE; \ + } while(0U) +#endif /* USB_OTG_FS || USB_OTG_HS */ #if defined (USB) -#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__)) @@ -244,31 +281,19 @@ typedef struct #define __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR1 & (USB_WAKEUP_EXTI_LINE) #define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR1 = USB_WAKEUP_EXTI_LINE -#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() do {\ - EXTI->FTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 |= USB_WAKEUP_EXTI_LINE;\ - } while(0) - -#define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do {\ - EXTI->FTSR1 |= (USB_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\ - } while(0) - -#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do {\ - EXTI->RTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\ - EXTI->FTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 |= USB_WAKEUP_EXTI_LINE;\ - EXTI->FTSR1 |= USB_WAKEUP_EXTI_LINE;\ - } while(0) - -#define __HAL_USB_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= USB_WAKEUP_EXTI_LINE) +#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ + do { \ + EXTI->FTSR1 &= ~(USB_WAKEUP_EXTI_LINE); \ + EXTI->RTSR1 |= USB_WAKEUP_EXTI_LINE; \ + } while(0U) #endif /* USB */ - + /** * @} */ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup PCD_Exported_Functions PCD Exported Functions * @{ */ @@ -278,9 +303,71 @@ typedef struct * @{ */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd); void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition + * @brief HAL USB OTG PCD Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */ + HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */ + HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */ + HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */ + HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */ + HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */ + HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */ + + HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */ + HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */ + +} HAL_PCD_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition + * @brief HAL USB OTG PCD Callback pointer definition + * @{ + */ + +typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */ +typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */ +typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */ +typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */ +typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */ +typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */ +typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< pointer to USB OTG PCD BCD callback */ + +/** + * @} + */ + +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ /** * @} */ @@ -290,22 +377,22 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); /** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions * @{ */ - /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); -void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd); void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd); void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); + +void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); /** * @} */ @@ -351,16 +438,28 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt * @{ */ -#if defined (USB_OTG_FS) -#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08) -#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C) -#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U +#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU +#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U + +#ifndef LL_EXTI_LINE_18 +#define LL_EXTI_LINE_18 0x00040000U +#endif + +#ifndef LL_EXTI_LINE_20 +#define LL_EXTI_LINE_20 0x00100000U +#endif -#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the USB EXTI Line */ -#endif /* USB_OTG_FS */ +#define USB_OTG_FS_WAKEUP_EXTI_LINE LL_EXTI_LINE_18 /*!< External interrupt line 17 Connected to the USB EXTI Line */ +#endif /* USB_OTG_FS || USB_OTG_HS */ #if defined (USB) -#define USB_WAKEUP_EXTI_LINE ((uint32_t)0x00020000) /*!< External interrupt line 17Connected to the USB EXTI Line */ +#ifndef LL_EXTI_LINE_18 +#define LL_EXTI_LINE_18 0x00040000U +#endif + +#define USB_WAKEUP_EXTI_LINE LL_EXTI_LINE_18 /*!< External interrupt line 17Connected to the USB EXTI Line */ #endif /* USB */ /** @@ -374,22 +473,22 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #define PCD_EP0MPS_64 DEP0CTL_MPS_64 #define PCD_EP0MPS_32 DEP0CTL_MPS_32 #define PCD_EP0MPS_16 DEP0CTL_MPS_16 -#define PCD_EP0MPS_08 DEP0CTL_MPS_8 +#define PCD_EP0MPS_08 DEP0CTL_MPS_8 /** * @} */ - + /** @defgroup PCD_ENDP PCD ENDP * @{ */ -#define PCD_ENDP0 ((uint8_t)0) -#define PCD_ENDP1 ((uint8_t)1) -#define PCD_ENDP2 ((uint8_t)2) -#define PCD_ENDP3 ((uint8_t)3) -#define PCD_ENDP4 ((uint8_t)4) -#define PCD_ENDP5 ((uint8_t)5) -#define PCD_ENDP6 ((uint8_t)6) -#define PCD_ENDP7 ((uint8_t)7) +#define PCD_ENDP0 0U +#define PCD_ENDP1 1U +#define PCD_ENDP2 2U +#define PCD_ENDP3 3U +#define PCD_ENDP4 4U +#define PCD_ENDP5 5U +#define PCD_ENDP6 6U +#define PCD_ENDP7 7U /** * @} */ @@ -397,8 +496,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** @defgroup PCD_ENDP_Kind PCD Endpoint Kind * @{ */ -#define PCD_SNG_BUF 0 -#define PCD_DBL_BUF 1 +#define PCD_SNG_BUF 0U +#define PCD_DBL_BUF 1U /** * @} */ @@ -408,161 +507,168 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); */ /* Private macros ------------------------------------------------------------*/ -/** @addtogroup PCD_Private_Macros PCD Private Macros +/** @defgroup PCD_Private_Macros PCD Private Macros * @{ */ #if defined (USB) /* SetENDPOINT */ -#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue)) +#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue)) /* GetENDPOINT */ -#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2)) +#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + ((bEpNum) * 2U))) /* ENDPOINT transfer */ #define USB_EP0StartXfer USB_EPStartXfer /** * @brief sets the type in the endpoint register(bits EP_TYPE[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wType: Endpoint Type. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wType Endpoint Type. * @retval None */ -#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) ))) +#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ + ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType)))) /** * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval Endpoint Type */ #define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD) /** * @brief free buffer used from the application realizing it to the line - toggles bit SW_BUF in the double buffered endpoint register - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param bDir: Direction + * toggles bit SW_BUF in the double buffered endpoint register + * @param USBx USB device. + * @param bEpNum, bDir * @retval None */ -#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\ -{\ - if ((bDir) == PCD_EP_DBUF_OUT)\ - { /* OUT double buffered endpoint */\ - PCD_TX_DTOG((USBx), (bEpNum));\ - }\ - else if ((bDir) == PCD_EP_DBUF_IN)\ - { /* IN double buffered endpoint */\ - PCD_RX_DTOG((USBx), (bEpNum));\ - }\ -} +#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) do { \ + if ((bDir) == 0U) \ + { \ + /* OUT double buffered endpoint */ \ + PCD_TX_DTOG((USBx), (bEpNum)); \ + } \ + else if ((bDir) == 1U) \ + { \ + /* IN double buffered endpoint */ \ + PCD_RX_DTOG((USBx), (bEpNum)); \ + } \ +} while(0) /** * @brief gets direction of the double buffered endpoint - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval EP_DBUF_OUT, EP_DBUF_IN, * EP_DBUF_ERR if the endpoint counter not yet programmed. */ -#define PCD_GET_DB_DIR(USBx, bEpNum)\ -{\ - if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\ - return(PCD_EP_DBUF_OUT);\ - else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\ - return(PCD_EP_DBUF_IN);\ - else\ - return(PCD_EP_DBUF_ERR);\ -} +#define PCD_GET_DB_DIR(USBx, bEpNum) do { \ + if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00U) != 0U) \ + { \ + return(PCD_EP_DBUF_OUT); \ + } \ + else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FFU) != 0U) \ + { \ + return(PCD_EP_DBUF_IN); \ + } \ + else \ + { \ + return(PCD_EP_DBUF_ERR); \ + } \ +} while(0) /** * @brief sets the status for tx transfer (bits STAT_TX[1:0]). - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wState: new state + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state * @retval None */ -#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\ +#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) do { \ + register uint16_t _wRegVal; \ \ - _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\ - /* toggle first bit ? */ \ - if((USB_EPTX_DTOG1 & (wState))!= 0)\ - { \ - _wRegVal ^= USB_EPTX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPTX_DTOG2 & (wState))!= 0) \ - { \ - _wRegVal ^= USB_EPTX_DTOG2; \ - } \ - PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX));\ - } /* PCD_SET_EP_TX_STATUS */ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \ + /* toggle first bit ? */ \ + if ((USB_EPTX_DTOG1 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPTX_DTOG2 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_SET_EP_TX_STATUS */ /** * @brief sets the status for rx transfer (bits STAT_TX[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wState: new state + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state * @retval None */ -#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\ - register uint16_t _wRegVal; \ +#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) do { \ + register uint16_t _wRegVal; \ \ - _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\ - /* toggle first bit ? */ \ - if((USB_EPRX_DTOG1 & (wState))!= 0) \ - { \ - _wRegVal ^= USB_EPRX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPRX_DTOG2 & (wState))!= 0) \ - { \ - _wRegVal ^= USB_EPRX_DTOG2; \ - } \ - PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \ - } /* PCD_SET_EP_RX_STATUS */ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \ + /* toggle first bit ? */ \ + if ((USB_EPRX_DTOG1 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPRX_DTOG2 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_SET_EP_RX_STATUS */ /** * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wStaterx: new state. - * @param wStatetx: new state. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wStaterx new state. + * @param wStatetx new state. * @retval None */ -#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\ - register uint32_t _wRegVal; \ +#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) do { \ + register uint16_t _wRegVal; \ \ - _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\ - /* toggle first bit ? */ \ - if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0) \ - { \ - _wRegVal ^= USB_EPRX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPRX_DTOG2 & (wStaterx))!= 0) \ - { \ - _wRegVal ^= USB_EPRX_DTOG2; \ - } \ - /* toggle first bit ? */ \ - if((USB_EPTX_DTOG1 & (wStatetx))!= 0) \ - { \ - _wRegVal ^= USB_EPTX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPTX_DTOG2 & (wStatetx))!= 0) \ - { \ - _wRegVal ^= USB_EPTX_DTOG2; \ - } \ - PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \ - } /* PCD_SET_EP_TXRX_STATUS */ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \ + /* toggle first bit ? */ \ + if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG2; \ + } \ + /* toggle first bit ? */ \ + if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG2; \ + } \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \ + } while(0) /* PCD_SET_EP_TXRX_STATUS */ /** * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] * /STAT_RX[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval status */ #define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT) @@ -570,8 +676,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief sets directly the VALID tx/rx-status into the endpoint register - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID)) @@ -579,8 +685,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief checks stall condition in an endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval TRUE = endpoint in stall condition. */ #define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \ @@ -590,19 +696,30 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief set & clear EP_KIND bit. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ -#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK)))) -#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK)))) +#define PCD_SET_EP_KIND(USBx, bEpNum) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \ + } while(0) /* PCD_SET_EP_KIND */ + +#define PCD_CLEAR_EP_KIND(USBx, bEpNum) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_CLEAR_EP_KIND */ /** * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) @@ -610,8 +727,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Sets/clears directly EP_KIND bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) @@ -619,77 +736,130 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ -#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK)) -#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK)) +#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal); \ + } while(0) /* PCD_CLEAR_RX_EP_CTR */ + +#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal); \ + } while(0) /* PCD_CLEAR_TX_EP_CTR */ /** * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ -#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK))) -#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK))) +#define PCD_RX_DTOG(USBx, bEpNum) do { \ + register uint16_t _wEPVal; \ + \ + _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \ + } while(0) /* PCD_RX_DTOG */ +#define PCD_TX_DTOG(USBx, bEpNum) do { \ + register uint16_t _wEPVal; \ + \ + _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \ + } while(0) /* PCD_TX_DTOG */ /** * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ -#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\ - { \ - PCD_RX_DTOG((USBx), (bEpNum)); \ - } -#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\ - { \ - PCD_TX_DTOG((USBx), (bEpNum)); \ - } - +#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ + \ + if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\ + { \ + PCD_RX_DTOG((USBx), (bEpNum)); \ + } \ + } while(0) /* PCD_CLEAR_RX_DTOG */ + +#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ + \ + if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\ + { \ + PCD_TX_DTOG((USBx), (bEpNum)); \ + } \ + } while(0) /* PCD_CLEAR_TX_DTOG */ + /** * @brief Sets address in an endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param bAddr: Address. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bAddr Address. * @retval None */ -#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\ - USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr)) +#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_SET_EP_ADDRESS */ +/** + * @brief Gets address in an endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) -#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8)+ ((uint32_t)(USBx) + 0x400))) -#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+2)+ ((uint32_t)(USBx) + 0x400))) -#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+4)+ ((uint32_t)(USBx) + 0x400))) -#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+6)+ ((uint32_t)(USBx) + 0x400))) - -#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\ - uint16_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \ - PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\ - } +#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) +#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) /** * @brief sets address of the tx/rx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wAddr: address to be set (must be word aligned). + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wAddr address to be set (must be word aligned). * @retval None */ -#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1)) -#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1)) +#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) do { \ + register uint16_t *_wRegVal; \ + register uint32_t _wRegBase = (uint32_t)USBx; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \ + *_wRegVal = ((wAddr) >> 1) << 1; \ +} while(0) /* PCD_SET_EP_TX_ADDRESS */ + +#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) do { \ + register uint16_t *_wRegVal; \ + register uint32_t _wRegBase = (uint32_t)USBx; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \ + *_wRegVal = ((wAddr) >> 1) << 1; \ +} while(0) /* PCD_SET_EP_RX_ADDRESS */ /** * @brief Gets address of the tx/rx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval address of the buffer. */ #define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum))) @@ -697,92 +867,116 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Sets counter of rx buffer with no. of blocks. - * @param dwReg: Register - * @param wCount: Counter. - * @param wNBlocks: no. of Blocks. + * @param pdwReg Register pointer + * @param wCount Counter. + * @param wNBlocks no. of Blocks. * @retval None */ -#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\ - (wNBlocks) = (wCount) >> 5;\ - if(((wCount) & 0x1f) == 0)\ - { \ - (wNBlocks)--;\ - } \ - *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10) | 0x8000); \ - }/* PCD_CALC_BLK32 */ - -#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\ - (wNBlocks) = (wCount) >> 1;\ - if(((wCount) & 0x1) != 0)\ - { \ - (wNBlocks)++;\ - } \ - *pdwReg = (uint16_t)((wNBlocks) << 10);\ - }/* PCD_CALC_BLK2 */ - -#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\ - uint16_t wNBlocks;\ - if((wCount) > 62) \ - { \ - PCD_CALC_BLK32((dwReg),(wCount),wNBlocks); \ - } \ - else \ - { \ - PCD_CALC_BLK2((dwReg),(wCount),wNBlocks); \ - } \ - }/* PCD_SET_EP_CNT_RX_REG */ - -#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\ - uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \ - PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\ - } +#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) do { \ + (wNBlocks) = (wCount) >> 5; \ + *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | (0x1U << 15)); \ + } while(0) /* PCD_CALC_BLK32 */ + +#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) do { \ + (wNBlocks) = (wCount) >> 1; \ + if (((wCount) & 0x1U) != 0U) \ + { \ + (wNBlocks)++; \ + } \ + *(pdwReg) = (uint16_t)((wNBlocks) << 10); \ + } while(0) /* PCD_CALC_BLK2 */ + +#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) do { \ + uint32_t wNBlocks; \ + if ((wCount) == 0U) \ + { \ + *(pdwReg) &= (uint16_t)~(0x73U << 10); \ + *(pdwReg) |= (0x1U << 15); \ + } \ + else if((wCount) < 62U) \ + { \ + PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ + } \ + else \ + { \ + PCD_CALC_BLK32((pdwReg),(wCount), wNBlocks); \ + } \ + } while(0) /* PCD_SET_EP_CNT_RX_REG */ + +#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) do { \ + register uint32_t _wRegBase = (uint32_t)(USBx); \ + uint16_t *pdwReg; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + pdwReg = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ + PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \ + } while(0) /** * @brief sets counter for the tx/rx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wCount: Counter value. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wCount Counter value. * @retval None */ -#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount)) - +#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) do { \ + register uint32_t _wRegBase = (uint32_t)(USBx); \ + uint16_t *_wRegVal; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ + *_wRegVal = (uint16_t)(wCount); \ +} while(0) + +#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) do { \ + register uint32_t _wRegBase = (uint32_t)(USBx); \ + uint16_t *_wRegVal; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ + PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \ +} while(0) /** * @brief gets counter of the tx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval Counter value */ -#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ff) -#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ff) +#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU) +#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU) /** * @brief Sets buffer 0/1 address in a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wBuf0Addr: buffer 0 address. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wBuf0Addr buffer 0 address. * @retval Counter value */ -#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));} -#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));} +#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) do { \ + PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \ + } while(0) /* PCD_SET_EP_DBUF0_ADDR */ +#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) do { \ + PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \ + } while(0) /* PCD_SET_EP_DBUF1_ADDR */ /** * @brief Sets addresses in a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @param wBuf0Addr: buffer 0 address. * @param wBuf1Addr = buffer 1 address. * @retval None */ -#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \ - PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\ - PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\ - } /* PCD_SET_EP_DBUF_ADDR */ +#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) do { \ + PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \ + PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \ + } while(0) /* PCD_SET_EP_DBUF_ADDR */ /** * @brief Gets buffer 0/1 address of a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum))) @@ -790,42 +984,59 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Gets buffer 0/1 address of a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param bDir: endpoint dir EP_DBUF_OUT = OUT - * EP_DBUF_IN = IN - * @param wCount: Counter value + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bDir endpoint dir EP_DBUF_OUT = OUT + * EP_DBUF_IN = IN + * @param wCount: Counter value * @retval None */ -#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \ - if((bDir) == PCD_EP_DBUF_OUT)\ +#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) do { \ + if ((bDir) == 0U) \ + /* OUT endpoint */ \ + { \ + PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \ + } \ + else \ + { \ + if ((bDir) == 1U) \ + { \ + /* IN endpoint */ \ + PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \ + } \ + } \ + } while(0) /* SetEPDblBuf0Count*/ + +#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) do { \ + register uint32_t _wBase = (uint32_t)(USBx); \ + uint16_t *_wEPRegVal; \ + \ + if ((bDir) == 0U) \ + { \ /* OUT endpoint */ \ - {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \ - else if((bDir) == PCD_EP_DBUF_IN)\ - /* IN endpoint */ \ - *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ - } /* SetEPDblBuf0Count*/ - -#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \ - if((bDir) == PCD_EP_DBUF_OUT)\ - {/* OUT endpoint */ \ - PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount)); \ - } \ - else if((bDir) == PCD_EP_DBUF_IN)\ - {/* IN endpoint */ \ - *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ - } \ - } /* SetEPDblBuf1Count */ - -#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\ + PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \ + } \ + else \ + { \ + if ((bDir) == 1U) \ + { \ + /* IN endpoint */ \ + _wBase += (uint32_t)(USBx)->BTABLE; \ + _wEPRegVal = (uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ + *_wEPRegVal = (uint16_t)(wCount); \ + } \ + } \ + } while(0) /* SetEPDblBuf1Count */ + +#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) do { \ PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \ PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \ - } /* PCD_SET_EP_DBUF_CNT */ + } while(0) /* PCD_SET_EP_DBUF_CNT */ /** * @brief Gets buffer 0/1 rx/tx counter for double buffering. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum))) @@ -833,19 +1044,6 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #endif /* USB */ -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) - -/** @defgroup PCD_Instance_definition PCD Instance definition - * @{ - */ -#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE -/** - * @} - */ -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx */ - /** * @} */ @@ -858,17 +1056,12 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @} */ -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* defined (USB) || defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #ifdef __cplusplus } #endif - #endif /* __STM32L4xx_HAL_PCD_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h index 14a19277b0..326dbff22b 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32l4xx_hal_pcd_ex.h * @author MCD Application Team - * @brief Header file of PCD HAL module. + * @brief Header file of PCD HAL Extension module. ****************************************************************************** * @attention * @@ -31,25 +31,21 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L4xx_HAL_PCD_EX_H #define __STM32L4xx_HAL_PCD_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" - + +#if defined (USB) || defined (USB_OTG_FS) || defined (USB_OTG_HS) + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ @@ -58,23 +54,6 @@ * @{ */ /* Exported types ------------------------------------------------------------*/ -typedef enum -{ - PCD_LPM_L0_ACTIVE = 0x00, /* on */ - PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */ -}PCD_LPM_MsgTypeDef; - -typedef enum -{ - PCD_BCD_ERROR = 0xFF, - PCD_BCD_CONTACT_DETECTION = 0xFE, - PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, - PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC, - PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, - PCD_BCD_DISCOVERY_COMPLETED = 0x00, - -}PCD_BCD_MsgTypeDef; - /* Exported constants --------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -85,13 +64,13 @@ typedef enum * @{ */ -#if defined(USB_OTG_FS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); -#endif /* USB_OTG_FS */ +#endif /* USB_OTG_FS || USB_OTG_HS */ #if defined (USB) -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress); @@ -106,25 +85,21 @@ void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ /** * @} */ -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* defined (USB) || defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #ifdef __cplusplus } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h index 948b1fe7b4..fbcfabb45d 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h @@ -30,12 +30,12 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_QSPI_H -#define __STM32L4xx_HAL_QSPI_H +#ifndef STM32L4xx_HAL_QSPI_H +#define STM32L4xx_HAL_QSPI_H #ifdef __cplusplus extern "C" { @@ -52,63 +52,63 @@ /** @addtogroup QSPI * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup QSPI_Exported_Types QSPI Exported Types * @{ */ -/** - * @brief QSPI Init structure definition +/** + * @brief QSPI Init structure definition */ typedef struct { uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. - This parameter can be a number between 0 and 255 */ + This parameter can be a number between 0 and 255 */ uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) This parameter can be a value between 1 and 16 */ - uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to + uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) This parameter can be a value of @ref QSPI_SampleShifting */ - uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits - required to address the flash memory. The flash capacity can be up to 4GB - (addressed using 32 bits) in indirect mode, but the addressable space in + uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits + required to address the flash memory. The flash capacity can be up to 4GB + (addressed using 32 bits) in indirect mode, but the addressable space in memory-mapped mode is limited to 256MB This parameter can be a number between 0 and 31 */ - uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number + uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number of clock cycles which the chip select must remain high between commands. - This parameter can be a value of @ref QSPI_ChipSelectHighTime */ + This parameter can be a value of @ref QSPI_ChipSelectHighTime */ uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. This parameter can be a value of @ref QSPI_ClockMode */ -#if defined(QUADSPI_CR_DFM) +#if defined(QUADSPI_CR_DFM) uint32_t FlashID; /* Specifies the Flash which will be used, This parameter can be a value of @ref QSPI_Flash_Select */ uint32_t DualFlash; /* Specifies the Dual Flash Mode State - This parameter can be a value of @ref QSPI_DualFlash_Mode */ + This parameter can be a value of @ref QSPI_DualFlash_Mode */ #endif }QSPI_InitTypeDef; -/** - * @brief HAL QSPI State structures definition - */ +/** + * @brief HAL QSPI State structures definition + */ typedef enum { - HAL_QSPI_STATE_RESET = 0x00, /*!< Peripheral not initialized */ - HAL_QSPI_STATE_READY = 0x01, /*!< Peripheral initialized and ready for use */ - HAL_QSPI_STATE_BUSY = 0x02, /*!< Peripheral in indirect mode and busy */ - HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12, /*!< Peripheral in indirect mode with transmission ongoing */ - HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, /*!< Peripheral in indirect mode with reception ongoing */ - HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42, /*!< Peripheral in auto polling mode ongoing */ - HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82, /*!< Peripheral in memory mapped mode ongoing */ - HAL_QSPI_STATE_ABORT = 0x08, /*!< Peripheral with abort request ongoing */ - HAL_QSPI_STATE_ERROR = 0x04 /*!< Peripheral in error */ + HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */ + HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ + HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */ + HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */ + HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */ + HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */ + HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */ + HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */ + HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */ }HAL_QSPI_StateTypeDef; -/** - * @brief QSPI Handle Structure definition - */ -typedef struct +/** + * @brief QSPI Handle Structure definition + */ +typedef struct __QSPI_HandleTypeDef { QUADSPI_TypeDef *Instance; /* QSPI registers base address */ QSPI_InitTypeDef Init; /* QSPI communication parameters */ @@ -122,11 +122,26 @@ typedef struct __IO HAL_LockTypeDef Lock; /* Locking object */ __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ __IO uint32_t ErrorCode; /* QSPI Error code */ - uint32_t Timeout; /* Timeout for the QSPI memory access */ + uint32_t Timeout; /* Timeout for the QSPI memory access */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi); + void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi); + + void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi); +#endif }QSPI_HandleTypeDef; -/** - * @brief QSPI Command structure definition +/** + * @brief QSPI Command structure definition */ typedef struct { @@ -151,25 +166,26 @@ typedef struct uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) This parameter can be a value of @ref QSPI_DataMode */ uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes) - This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length + This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length until end of memory)*/ uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase This parameter can be a value of @ref QSPI_DdrMode */ - uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of - system clock in DDR mode. Not available on STM32L4x6 devices but in future devices. + uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data + output by one half of system clock in DDR mode. + Not available on all devices. This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ uint32_t SIOOMode; /* Specifies the send instruction only once mode This parameter can be a value of @ref QSPI_SIOOMode */ }QSPI_CommandTypeDef; -/** - * @brief QSPI Auto Polling mode configuration structure definition +/** + * @brief QSPI Auto Polling mode configuration structure definition */ typedef struct { uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. This parameter can be any value between 0 and 0xFFFFFFFF */ - uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. + uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. This parameter can be any value between 0 and 0xFFFFFFFF */ uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. This parameter can be any value between 0 and 0xFFFF */ @@ -180,18 +196,44 @@ typedef struct uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. This parameter can be a value of @ref QSPI_AutomaticStop */ }QSPI_AutoPollingTypeDef; - -/** - * @brief QSPI Memory Mapped mode configuration structure definition + +/** + * @brief QSPI Memory Mapped mode configuration structure definition */ typedef struct { uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. This parameter can be any value between 0 and 0xFFFF */ - uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. + uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. This parameter can be a value of @ref QSPI_TimeOutActivation */ }QSPI_MemoryMappedTypeDef; +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) +/** + * @brief HAL QSPI Callback ID enumeration definition + */ +typedef enum +{ + HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */ + HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */ + HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */ + HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */ + HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */ + HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */ + HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< QSPI Rx Half Complete Callback ID */ + HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< QSPI Tx Half Complete Callback ID */ + HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */ + HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */ + + HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */ + HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */ +}HAL_QSPI_CallbackIDTypeDef; + +/** + * @brief HAL QSPI Callback pointer definition + */ +typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); +#endif /** * @} */ @@ -203,29 +245,32 @@ typedef struct /** @defgroup QSPI_ErrorCode QSPI Error Code * @{ - */ -#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */ -#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /*!< Transfer error */ -#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /*!< DMA transfer error */ -#define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008) /*!< Invalid parameters error */ + */ +#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ +#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ +#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ +#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) +#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */ +#endif /** * @} - */ + */ /** @defgroup QSPI_SampleShifting QSPI Sample Shifting * @{ */ -#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000) /*!State = HAL_QSPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) +#endif /** @brief Enable the QSPI peripheral. * @param __HANDLE__ : specifies the QSPI Handle. * @retval None - */ + */ #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Disable the QSPI peripheral. @@ -449,8 +502,8 @@ typedef struct #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Enable the specified QSPI interrupt. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to enable. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -463,8 +516,8 @@ typedef struct /** @brief Disable the specified QSPI interrupt. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to disable. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -476,8 +529,8 @@ typedef struct #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) /** @brief Check whether the specified QSPI interrupt source is enabled or not. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to check. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __INTERRUPT__ : specifies the QSPI interrupt source to check. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -486,12 +539,12 @@ typedef struct * @arg QSPI_IT_TE: QSPI Transfer error interrupt * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) /** * @brief Check whether the selected QSPI flag is set or not. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __FLAG__: specifies the QSPI flag to check. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __FLAG__ : specifies the QSPI flag to check. * This parameter can be one of the following values: * @arg QSPI_FLAG_BUSY: QSPI Busy flag * @arg QSPI_FLAG_TO: QSPI Timeout flag @@ -501,11 +554,11 @@ typedef struct * @arg QSPI_FLAG_TE: QSPI Transfer error flag * @retval None */ -#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) ? SET : RESET) +#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) /** @brief Clears the specified QSPI's flag status. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __FLAG__: specifies the QSPI clear register flag that needs to be set + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set * This parameter can be one of the following values: * @arg QSPI_FLAG_TO: QSPI Timeout flag * @arg QSPI_FLAG_SM: QSPI Status match flag @@ -518,16 +571,26 @@ typedef struct * @} */ -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup QSPI_Exported_Functions * @{ */ + +/** @addtogroup QSPI_Exported_Functions_Group1 + * @{ + */ /* Initialization/de-initialization functions ********************************/ HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); +/** + * @} + */ +/** @addtogroup QSPI_Exported_Functions_Group2 + * @{ + */ /* IO operation functions *****************************************************/ /* QSPI IRQ handler method */ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); @@ -567,6 +630,18 @@ void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); /* QSPI memory-mapped mode */ void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) +/* QSPI callback registering/unregistering */ +HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackID, pQSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackID); +#endif +/** + * @} + */ + +/** @addtogroup QSPI_Exported_Functions_Group3 + * @{ + */ /* Peripheral Control and State functions ************************************/ HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); @@ -575,23 +650,30 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); +#if defined(QUADSPI_CR_DFM) +HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID); +#endif +/** + * @} + */ + /** * @} */ -/* End of exported functions -------------------------------------------------*/ +/* End of exported functions -------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @defgroup QSPI_Private_Macros QSPI Private Macros -* @{ -*/ -#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF) + * @{ + */ +#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) -#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 16)) +#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 16U)) #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) -#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31)) +#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U)) #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ @@ -605,15 +687,15 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ ((CLKMODE) == QSPI_CLOCK_MODE_3)) -#if defined(QUADSPI_CR_DFM) -#define IS_QSPI_FLASH_ID(FLASH) (((FLASH) == QSPI_FLASH_ID_1) || \ - ((FLASH) == QSPI_FLASH_ID_2)) - +#if defined(QUADSPI_CR_DFM) +#define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \ + ((FLASH_ID) == QSPI_FLASH_ID_2)) + #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ ((MODE) == QSPI_DUALFLASH_DISABLE)) -#endif -#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF) +#endif +#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU) #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ @@ -625,7 +707,7 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) -#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31) +#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U) #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ @@ -650,42 +732,43 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) -#if defined(QUADSPI_CCR_DHHC) +#if defined(QUADSPI_CCR_DHHC) #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) + #else #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY)) -#endif +#endif #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) -#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) +#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) -#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4)) +#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ - ((MODE) == QSPI_MATCH_MODE_OR)) + ((MODE) == QSPI_MATCH_MODE_OR)) #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ - ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) + ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ - ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) + ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) -#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF) +#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) /** * @} -*/ +*/ /* End of private macros -----------------------------------------------------*/ /** * @} - */ + */ /** * @} - */ + */ #endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */ @@ -693,6 +776,6 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); } #endif -#endif /* __STM32L4xx_HAL_QSPI_H */ +#endif /* STM32L4xx_HAL_QSPI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h index 16aeffbb68..e2f0fa5deb 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h @@ -82,7 +82,8 @@ typedef struct This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ uint32_t PLLR; /*!< PLLR: Division for the main system clock. - User have to set the PLLR parameter correctly to not exceed max frequency 80MHZ. + User have to set the PLLR parameter correctly to not exceed max frequency 120MHZ + on STM32L4Rx/STM32L4Sx devices else 80MHz on the other devices. This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ }RCC_PLLInitTypeDef; @@ -566,7 +567,6 @@ typedef struct /* Flags in the CSR register */ #define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ -#define RCC_FLAG_RMVF ((CSR_REG_INDEX << 5U) | RCC_CSR_RMVF_Pos) /*!< Remove reset flag */ #define RCC_FLAG_FWRST ((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos) /*!< Firewall reset flag */ #define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ #define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ @@ -4318,7 +4318,6 @@ typedef struct * @arg @ref RCC_FLAG_OBLRST OBLRST reset * @arg @ref RCC_FLAG_PINRST Pin reset * @arg @ref RCC_FLAG_FWRST FIREWALL reset - * @arg @ref RCC_FLAG_RMVF Remove reset Flag * @arg @ref RCC_FLAG_SFTRST Software reset * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rng.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rng.h index d301a0dc9c..09921bdadb 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rng.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rng.h @@ -83,22 +83,53 @@ typedef enum /** * @brief RNG Handle Structure definition */ -typedef struct +typedef struct __RNG_HandleTypeDef { - RNG_TypeDef *Instance; /*!< Register base address */ + RNG_TypeDef *Instance; /*!< Register base address */ #if defined(RNG_CR_CED) - RNG_InitTypeDef Init; /*!< RNG configuration parameters */ + RNG_InitTypeDef Init; /*!< RNG configuration parameters */ #endif /* defined(RNG_CR_CED) */ - HAL_LockTypeDef Lock; /*!< RNG locking object */ + HAL_LockTypeDef Lock; /*!< RNG locking object */ + + __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */ + + __IO uint32_t ErrorCode; /*!< RNG Error code */ + + uint32_t RandomNumber; /*!< Last Generated RNG Data */ - __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< RNG Data Ready Callback */ + void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Error Callback */ - uint32_t RandomNumber; /*!< Last Generated RNG Data */ + void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp Init callback */ + void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp DeInit callback */ +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ }RNG_HandleTypeDef; +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +/** + * @brief HAL RNG Callback ID enumeration definition + */ +typedef enum +{ + HAL_RNG_ERROR_CB_ID = 0x00U, /*!< RNG Error Callback ID */ + + HAL_RNG_MSPINIT_CB_ID = 0x01U, /*!< RNG MspInit callback ID */ + HAL_RNG_MSPDEINIT_CB_ID = 0x02U /*!< RNG MspDeInit callback ID */ + +} HAL_RNG_CallbackIDTypeDef; + +/** + * @brief HAL RNG Callback pointer definition + */ +typedef void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng); /*!< pointer to a common RNG callback function */ +typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef * hrng, uint32_t random32bit); /*!< pointer to an RNG Data Ready specific callback function */ + +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + /** * @} */ @@ -139,6 +170,17 @@ typedef struct */ #endif /* defined(RNG_CR_CED) */ +/** @defgroup RNG_Error_Definition RNG Error Definition + * @{ + */ +#define HAL_RNG_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +#define HAL_RNG_ERROR_INVALID_CALLBACK ((uint32_t)0x00000001U) /*!< Invalid Callback error */ +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ +/** + * @} + */ + /** * @} */ @@ -152,7 +194,15 @@ typedef struct * @param __HANDLE__: RNG Handle * @retval None */ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_RNG_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET) +#endif /*USE_HAL_RNG_REGISTER_CALLBACKS */ /** * @brief Enable the RNG peripheral. @@ -180,7 +230,6 @@ typedef struct */ #define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) - /** * @brief Clear the selected RNG flag status. * @param __HANDLE__: RNG handle @@ -191,8 +240,6 @@ typedef struct */ #define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */ - - /** * @brief Enable the RNG interrupt. * @param __HANDLE__: RNG Handle @@ -249,6 +296,16 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng); HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng); void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng); void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + /** * @} */ @@ -272,10 +329,11 @@ void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit); */ /* Peripheral State functions **************************************************/ -/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions +/** @defgroup RNG_Exported_Functions_Group3 Peripheral State and Error functions * @{ */ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng); /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h index e8ab5d04cb..bf202c75d0 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h @@ -176,9 +176,9 @@ typedef struct }RTC_AlarmTypeDef; /** - * @brief Time Handle Structure definition + * @brief RTC Handle Structure definition */ -typedef struct +typedef struct __RTC_HandleTypeDef { RTC_TypeDef *Instance; /*!< Register base address */ @@ -188,8 +188,60 @@ typedef struct __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + void (* AlarmAEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm A Event callback */ + + void (* AlarmBEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm B Event callback */ + + void (* TimeStampEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC TimeStamp Event callback */ + + void (* WakeUpTimerEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC WakeUpTimer Event callback */ + +#if defined(RTC_TAMPER1_SUPPORT) + void (* Tamper1EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 1 Event callback */ +#endif /* RTC_TAMPER1_SUPPORT */ + + void (* Tamper2EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 2 Event callback */ + +#if defined(RTC_TAMPER3_SUPPORT) + void (* Tamper3EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 3 Event callback */ +#endif /* RTC_TAMPER3_SUPPORT */ + + void (* MspInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp Init callback */ + + void (* MspDeInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp DeInit callback */ + +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + }RTC_HandleTypeDef; +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL LPTIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00U, /*!< RTC Alarm A Event Callback ID */ + HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, /*!< RTC Alarm B Event Callback ID */ + HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, /*!< RTC TimeStamp Event Callback ID */ + HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U, /*!< RTC WakeUp Timer Event Callback ID */ +#if defined(RTC_TAMPER1_SUPPORT) + HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, /*!< RTC Tamper 1 Callback ID */ +#endif /* RTC_TAMPER1_SUPPORT */ + HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, /*!< RTC Tamper 2 Callback ID */ +#if defined(RTC_TAMPER3_SUPPORT) + HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, /*!< RTC Tamper 3 Callback ID */ +#endif /* RTC_TAMPER3_SUPPORT */ + HAL_RTC_MSPINIT_CB_ID = 0x0EU, /*!< RTC Msp Init callback ID */ + HAL_RTC_MSPDEINIT_CB_ID = 0x0FU /*!< RTC Msp DeInit callback ID */ +}HAL_RTC_CallbackIDTypeDef; + +/** + * @brief HAL RTC Callback pointer definition + */ +typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to an RTC callback function */ +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + /** * @} */ @@ -431,7 +483,15 @@ typedef struct * @param __HANDLE__: RTC handle. * @retval None */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\ + (__HANDLE__)->State = HAL_RTC_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL;\ + (__HANDLE__)->MspDeInitCallback = NULL;\ + }while(0) +#else #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ /** * @brief Disable the write protection for RTC registers. @@ -655,6 +715,13 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h index 9cd91dabba..b8a1bae50f 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h @@ -34,11 +34,11 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_SAI_H -#define __STM32L4xx_HAL_SAI_H +#ifndef STM32L4xx_HAL_SAI_H +#define STM32L4xx_HAL_SAI_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -67,7 +67,7 @@ typedef enum HAL_SAI_STATE_BUSY = 0x02U, /*!< SAI internal process is ongoing */ HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */ HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing */ -}HAL_SAI_StateTypeDef; +} HAL_SAI_StateTypeDef; /** * @brief SAI Callback prototype @@ -75,17 +75,21 @@ typedef enum typedef void (*SAIcallback)(void); #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -/** +/** @defgroup SAI_PDM_Structure_definition SAI PDM Structure definition * @brief SAI PDM Init structure definition - */ + * @{ + */ typedef struct { - FunctionalState Activation; /*!< Enable/disable PDM interface */ - uint32_t MicPairsNbr; /*!< Specifies the number of microphone pairs used. - This parameter must be a number between Min_Data = 1 and Max_Data = 3. */ - uint32_t ClockEnable; /*!< Specifies which clock must be enabled. - This parameter can be a values combination of @ref SAI_PDM_ClockEnable */ -}SAI_PdmInitTypeDef; + FunctionalState Activation; /*!< Enable/disable PDM interface */ + uint32_t MicPairsNbr; /*!< Specifies the number of microphone pairs used. + This parameter must be a number between Min_Data = 1 and Max_Data = 3. */ + uint32_t ClockEnable; /*!< Specifies which clock must be enabled. + This parameter can be a values combination of @ref SAI_PDM_ClockEnable */ +} SAI_PdmInitTypeDef; +/** + * @} + */ #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** @defgroup SAI_Init_Structure_definition SAI Init Structure definition @@ -103,29 +107,29 @@ typedef struct uint32_t SynchroExt; /*!< Specifies SAI external output synchronization, this setup is common for BlockA and BlockB This parameter can be a value of @ref SAI_Block_SyncExt - @note: If both audio blocks of same SAI are used, this parameter has - to be set to the same value for each audio block */ + @note If both audio blocks of same SAI are used, this parameter has + to be set to the same value for each audio block */ uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven. This parameter can be a value of @ref SAI_Block_Output_Drive - @note this value has to be set before enabling the audio block - but after the audio block configuration. */ + @note This value has to be set before enabling the audio block + but after the audio block configuration. */ uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not. This parameter can be a value of @ref SAI_Block_NoDivider - @note: For STM32L4Rx/STM32L4Sx devices : - If bit NOMCK in the SAI_xCR1 register is cleared, the frame length - should be aligned to a number equal to a power of 2, from 8 to 256. - If bit NOMCK in the SAI_xCR1 register is set, the frame length can - take any of the values without constraint. There is no MCLK_x clock - which can be output. - For other devices : - If bit NODIV in the SAI_xCR1 register is cleared, the frame length - should be aligned to a number equal to a power of 2, from 8 to 256. - If bit NODIV in the SAI_xCR1 register is set, the frame length can - take any of the values without constraint since the input clock of - the audio block should be equal to the bit clock. - There is no MCLK_x clock which can be output. */ + @note For STM32L4Rx/STM32L4Sx devices : + If bit NOMCK in the SAI_xCR1 register is cleared, the frame length + should be aligned to a number equal to a power of 2, from 8 to 256. + If bit NOMCK in the SAI_xCR1 register is set, the frame length can + take any of the values without constraint. There is no MCLK_x clock + which can be output. + For other devices : + If bit NODIV in the SAI_xCR1 register is cleared, the frame length + should be aligned to a number equal to a power of 2, from 8 to 256. + If bit NODIV in the SAI_xCR1 register is set, the frame length can + take any of the values without constraint since the input clock of + the audio block should be equal to the bit clock. + There is no MCLK_x clock which can be output. */ uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold. This parameter can be a value of @ref SAI_Block_Fifo_Threshold */ @@ -170,7 +174,7 @@ typedef struct uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity. This parameter can be a value of @ref SAI_Block_Clock_Strobing */ -}SAI_InitTypeDef; +} SAI_InitTypeDef; /** * @} */ @@ -184,9 +188,9 @@ typedef struct uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame. This parameter must be a number between Min_Data = 8 and Max_Data = 256. - @note: If master clock MCLK_x pin is declared as an output, the frame length - should be aligned to a number equal to power of 2 in order to keep - in an audio frame, an integer number of MCLK pulses by bit Clock. */ + @note If master clock MCLK_x pin is declared as an output, the frame length + should be aligned to a number equal to power of 2 in order to keep + in an audio frame, an integer number of MCLK pulses by bit Clock. */ uint32_t ActiveFrameLength; /*!< Specifies the Frame synchronization active level length. This Parameter specifies the length in number of bit clock (SCK + 1) @@ -202,7 +206,7 @@ typedef struct uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset. This parameter can be a value of @ref SAI_Block_FS_Offset */ -}SAI_FrameInitTypeDef; +} SAI_FrameInitTypeDef; /** * @} */ @@ -224,7 +228,7 @@ typedef struct uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated. This parameter can be a value of @ref SAI_Block_Slot_Active */ -}SAI_SlotInitTypeDef; +} SAI_SlotInitTypeDef; /** * @} */ @@ -262,17 +266,47 @@ typedef struct __SAI_HandleTypeDef __IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */ __IO uint32_t ErrorCode; /*!< SAI Error code */ -}SAI_HandleTypeDef; + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + void (*RxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive complete callback */ + void (*RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive half complete callback */ + void (*TxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit complete callback */ + void (*TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit half complete callback */ + void (*ErrorCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI error callback */ + void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP init callback */ + void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP de-init callback */ +#endif +} SAI_HandleTypeDef; /** * @} */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) +/** + * @brief SAI callback ID enumeration definition + */ +typedef enum +{ + HAL_SAI_RX_COMPLETE_CB_ID = 0x00U, /*!< SAI receive complete callback ID */ + HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SAI receive half complete callback ID */ + HAL_SAI_TX_COMPLETE_CB_ID = 0x02U, /*!< SAI transmit complete callback ID */ + HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SAI transmit half complete callback ID */ + HAL_SAI_ERROR_CB_ID = 0x04U, /*!< SAI error callback ID */ + HAL_SAI_MSPINIT_CB_ID = 0x05U, /*!< SAI MSP init callback ID */ + HAL_SAI_MSPDEINIT_CB_ID = 0x06U /*!< SAI MSP de-init callback ID */ +} HAL_SAI_CallbackIDTypeDef; + +/** + * @brief SAI callback pointer definition + */ +typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); +#endif + /** * @} */ /* Exported constants --------------------------------------------------------*/ - /** @defgroup SAI_Exported_Constants SAI Exported Constants * @{ */ @@ -280,15 +314,18 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Error_Code SAI Error Code * @{ */ -#define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001U) /*!< Overrun Error */ -#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002U) /*!< Underrun error */ -#define HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004U) /*!< Anticipated Frame synchronisation detection */ -#define HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008U) /*!< Late Frame synchronisation detection */ -#define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U) /*!< codec not ready */ -#define HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020U) /*!< Wrong clock configuration */ -#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U) /*!< Timeout error */ -#define HAL_SAI_ERROR_DMA ((uint32_t)0x00000080U) /*!< DMA error */ +#define HAL_SAI_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_SAI_ERROR_OVR 0x00000001U /*!< Overrun Error */ +#define HAL_SAI_ERROR_UDR 0x00000002U /*!< Underrun error */ +#define HAL_SAI_ERROR_AFSDET 0x00000004U /*!< Anticipated Frame synchronisation detection */ +#define HAL_SAI_ERROR_LFSDET 0x00000008U /*!< Late Frame synchronisation detection */ +#define HAL_SAI_ERROR_CNREADY 0x00000010U /*!< codec not ready */ +#define HAL_SAI_ERROR_WCKCFG 0x00000020U /*!< Wrong clock configuration */ +#define HAL_SAI_ERROR_TIMEOUT 0x00000040U /*!< Timeout error */ +#define HAL_SAI_ERROR_DMA 0x00000080U /*!< DMA error */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) +#define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */ +#endif /** * @} */ @@ -296,9 +333,9 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_SyncExt SAI External synchronisation * @{ */ -#define SAI_SYNCEXT_DISABLE 0 -#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1 -#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2 +#define SAI_SYNCEXT_DISABLE 0U +#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U +#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U /** * @} */ @@ -306,11 +343,11 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Protocol SAI Supported protocol * @{ */ -#define SAI_I2S_STANDARD 0 -#define SAI_I2S_MSBJUSTIFIED 1 -#define SAI_I2S_LSBJUSTIFIED 2 -#define SAI_PCM_LONG 3 -#define SAI_PCM_SHORT 4 +#define SAI_I2S_STANDARD 0U +#define SAI_I2S_MSBJUSTIFIED 1U +#define SAI_I2S_LSBJUSTIFIED 2U +#define SAI_PCM_LONG 3U +#define SAI_PCM_SHORT 4U /** * @} */ @@ -318,10 +355,10 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Protocol_DataSize SAI protocol data size * @{ */ -#define SAI_PROTOCOL_DATASIZE_16BIT 0 -#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1 -#define SAI_PROTOCOL_DATASIZE_24BIT 2 -#define SAI_PROTOCOL_DATASIZE_32BIT 3 +#define SAI_PROTOCOL_DATASIZE_16BIT 0U +#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U +#define SAI_PROTOCOL_DATASIZE_24BIT 2U +#define SAI_PROTOCOL_DATASIZE_32BIT 3U /** * @} */ @@ -329,16 +366,16 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Audio_Frequency SAI Audio Frequency * @{ */ -#define SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000U) -#define SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000U) -#define SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000U) -#define SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100U) -#define SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000U) -#define SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050U) -#define SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000U) -#define SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025U) -#define SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000U) -#define SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0U) +#define SAI_AUDIO_FREQUENCY_192K 192000U +#define SAI_AUDIO_FREQUENCY_96K 96000U +#define SAI_AUDIO_FREQUENCY_48K 48000U +#define SAI_AUDIO_FREQUENCY_44K 44100U +#define SAI_AUDIO_FREQUENCY_32K 32000U +#define SAI_AUDIO_FREQUENCY_22K 22050U +#define SAI_AUDIO_FREQUENCY_16K 16000U +#define SAI_AUDIO_FREQUENCY_11K 11025U +#define SAI_AUDIO_FREQUENCY_8K 8000U +#define SAI_AUDIO_FREQUENCY_MCKDIV 0U /** * @} */ @@ -347,8 +384,8 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling * @{ */ -#define SAI_MCK_OVERSAMPLING_DISABLE ((uint32_t)0x00000000U) -#define SAI_MCK_OVERSAMPLING_ENABLE ((uint32_t)SAI_xCR1_OSR) +#define SAI_MCK_OVERSAMPLING_DISABLE 0x00000000U +#define SAI_MCK_OVERSAMPLING_ENABLE SAI_xCR1_OSR /** * @} */ @@ -356,8 +393,8 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable * @{ */ -#define SAI_PDM_CLOCK1_ENABLE ((uint32_t)SAI_PDMCR_CKEN1) -#define SAI_PDM_CLOCK2_ENABLE ((uint32_t)SAI_PDMCR_CKEN2) +#define SAI_PDM_CLOCK1_ENABLE SAI_PDMCR_CKEN1 +#define SAI_PDM_CLOCK2_ENABLE SAI_PDMCR_CKEN2 /** * @} */ @@ -366,10 +403,10 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Mode SAI Block Mode * @{ */ -#define SAI_MODEMASTER_TX ((uint32_t)0x00000000U) -#define SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0) -#define SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1) -#define SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)) +#define SAI_MODEMASTER_TX 0x00000000U +#define SAI_MODEMASTER_RX SAI_xCR1_MODE_0 +#define SAI_MODESLAVE_TX SAI_xCR1_MODE_1 +#define SAI_MODESLAVE_RX (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0) /** * @} @@ -378,9 +415,9 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Protocol SAI Block Protocol * @{ */ -#define SAI_FREE_PROTOCOL ((uint32_t)0x00000000U) -#define SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0) -#define SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1) +#define SAI_FREE_PROTOCOL 0x00000000U +#define SAI_SPDIF_PROTOCOL SAI_xCR1_PRTCFG_0 +#define SAI_AC97_PROTOCOL SAI_xCR1_PRTCFG_1 /** * @} */ @@ -388,12 +425,12 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Data_Size SAI Block Data Size * @{ */ -#define SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1) -#define SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0)) -#define SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2) -#define SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0)) -#define SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1)) -#define SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)) +#define SAI_DATASIZE_8 SAI_xCR1_DS_1 +#define SAI_DATASIZE_10 (SAI_xCR1_DS_1 | SAI_xCR1_DS_0) +#define SAI_DATASIZE_16 SAI_xCR1_DS_2 +#define SAI_DATASIZE_20 (SAI_xCR1_DS_2 | SAI_xCR1_DS_0) +#define SAI_DATASIZE_24 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1) +#define SAI_DATASIZE_32 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0) /** * @} */ @@ -401,8 +438,8 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission * @{ */ -#define SAI_FIRSTBIT_MSB ((uint32_t)0x00000000U) -#define SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST) +#define SAI_FIRSTBIT_MSB 0x00000000U +#define SAI_FIRSTBIT_LSB SAI_xCR1_LSBFIRST /** * @} */ @@ -410,8 +447,8 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing * @{ */ -#define SAI_CLOCKSTROBING_FALLINGEDGE 0 -#define SAI_CLOCKSTROBING_RISINGEDGE 1 +#define SAI_CLOCKSTROBING_FALLINGEDGE 0U +#define SAI_CLOCKSTROBING_RISINGEDGE 1U /** * @} */ @@ -419,19 +456,19 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Synchronization SAI Block Synchronization * @{ */ -#define SAI_ASYNCHRONOUS 0 /*!< Asynchronous */ -#define SAI_SYNCHRONOUS 1 /*!< Synchronous with other block of same SAI */ -#define SAI_SYNCHRONOUS_EXT_SAI1 2 /*!< Synchronous with other SAI, SAI1 */ -#define SAI_SYNCHRONOUS_EXT_SAI2 3 /*!< Synchronous with other SAI, SAI2 */ +#define SAI_ASYNCHRONOUS 0U /*!< Asynchronous */ +#define SAI_SYNCHRONOUS 1U /*!< Synchronous with other block of same SAI */ +#define SAI_SYNCHRONOUS_EXT_SAI1 2U /*!< Synchronous with other SAI, SAI1 */ +#define SAI_SYNCHRONOUS_EXT_SAI2 3U /*!< Synchronous with other SAI, SAI2 */ /** * @} - */ + */ /** @defgroup SAI_Block_Output_Drive SAI Block Output Drive * @{ */ -#define SAI_OUTPUTDRIVE_DISABLE ((uint32_t)0x00000000U) -#define SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV) +#define SAI_OUTPUTDRIVE_DISABLE 0x00000000U +#define SAI_OUTPUTDRIVE_ENABLE SAI_xCR1_OUTDRIV /** * @} */ @@ -439,22 +476,21 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_NoDivider SAI Block NoDivider * @{ */ -#define SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000U) +#define SAI_MASTERDIVIDER_ENABLE 0x00000000U #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NOMCK) +#define SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NOMCK #else -#define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NODIV) +#define SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NODIV #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ - /** @defgroup SAI_Block_FS_Definition SAI Block FS Definition * @{ */ -#define SAI_FS_STARTFRAME ((uint32_t)0x00000000U) -#define SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF) +#define SAI_FS_STARTFRAME 0x00000000U +#define SAI_FS_CHANNEL_IDENTIFICATION SAI_xFRCR_FSDEF /** * @} */ @@ -462,8 +498,8 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity * @{ */ -#define SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000U) -#define SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPOL) +#define SAI_FS_ACTIVE_LOW 0x00000000U +#define SAI_FS_ACTIVE_HIGH SAI_xFRCR_FSPOL /** * @} */ @@ -471,19 +507,18 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_FS_Offset SAI Block FS Offset * @{ */ -#define SAI_FS_FIRSTBIT ((uint32_t)0x00000000U) -#define SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF) +#define SAI_FS_FIRSTBIT 0x00000000U +#define SAI_FS_BEFOREFIRSTBIT SAI_xFRCR_FSOFF /** * @} */ - - /** @defgroup SAI_Block_Slot_Size SAI Block Slot Size +/** @defgroup SAI_Block_Slot_Size SAI Block Slot Size * @{ */ -#define SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000U) -#define SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0) -#define SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1) +#define SAI_SLOTSIZE_DATASIZE 0x00000000U +#define SAI_SLOTSIZE_16B SAI_xSLOTR_SLOTSZ_0 +#define SAI_SLOTSIZE_32B SAI_xSLOTR_SLOTSZ_1 /** * @} */ @@ -491,24 +526,24 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Slot_Active SAI Block Slot Active * @{ */ -#define SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000U) -#define SAI_SLOTACTIVE_0 ((uint32_t)0x00000001U) -#define SAI_SLOTACTIVE_1 ((uint32_t)0x00000002U) -#define SAI_SLOTACTIVE_2 ((uint32_t)0x00000004U) -#define SAI_SLOTACTIVE_3 ((uint32_t)0x00000008U) -#define SAI_SLOTACTIVE_4 ((uint32_t)0x00000010U) -#define SAI_SLOTACTIVE_5 ((uint32_t)0x00000020U) -#define SAI_SLOTACTIVE_6 ((uint32_t)0x00000040U) -#define SAI_SLOTACTIVE_7 ((uint32_t)0x00000080U) -#define SAI_SLOTACTIVE_8 ((uint32_t)0x00000100U) -#define SAI_SLOTACTIVE_9 ((uint32_t)0x00000200U) -#define SAI_SLOTACTIVE_10 ((uint32_t)0x00000400U) -#define SAI_SLOTACTIVE_11 ((uint32_t)0x00000800U) -#define SAI_SLOTACTIVE_12 ((uint32_t)0x00001000U) -#define SAI_SLOTACTIVE_13 ((uint32_t)0x00002000U) -#define SAI_SLOTACTIVE_14 ((uint32_t)0x00004000U) -#define SAI_SLOTACTIVE_15 ((uint32_t)0x00008000U) -#define SAI_SLOTACTIVE_ALL ((uint32_t)0x0000FFFFU) +#define SAI_SLOT_NOTACTIVE 0x00000000U +#define SAI_SLOTACTIVE_0 0x00000001U +#define SAI_SLOTACTIVE_1 0x00000002U +#define SAI_SLOTACTIVE_2 0x00000004U +#define SAI_SLOTACTIVE_3 0x00000008U +#define SAI_SLOTACTIVE_4 0x00000010U +#define SAI_SLOTACTIVE_5 0x00000020U +#define SAI_SLOTACTIVE_6 0x00000040U +#define SAI_SLOTACTIVE_7 0x00000080U +#define SAI_SLOTACTIVE_8 0x00000100U +#define SAI_SLOTACTIVE_9 0x00000200U +#define SAI_SLOTACTIVE_10 0x00000400U +#define SAI_SLOTACTIVE_11 0x00000800U +#define SAI_SLOTACTIVE_12 0x00001000U +#define SAI_SLOTACTIVE_13 0x00002000U +#define SAI_SLOTACTIVE_14 0x00004000U +#define SAI_SLOTACTIVE_15 0x00008000U +#define SAI_SLOTACTIVE_ALL 0x0000FFFFU /** * @} */ @@ -516,8 +551,8 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode * @{ */ -#define SAI_STEREOMODE ((uint32_t)0x00000000U) -#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO) +#define SAI_STEREOMODE 0x00000000U +#define SAI_MONOMODE SAI_xCR1_MONO /** * @} */ @@ -525,8 +560,8 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_TRIState_Management SAI TRIState Management * @{ */ -#define SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000U) -#define SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS) +#define SAI_OUTPUT_NOTRELEASED 0x00000000U +#define SAI_OUTPUT_RELEASED SAI_xCR2_TRIS /** * @} */ @@ -534,11 +569,11 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold * @{ */ -#define SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000U) -#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)(SAI_xCR2_FTH_0)) -#define SAI_FIFOTHRESHOLD_HF ((uint32_t)(SAI_xCR2_FTH_1)) -#define SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)) -#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)(SAI_xCR2_FTH_2)) +#define SAI_FIFOTHRESHOLD_EMPTY 0x00000000U +#define SAI_FIFOTHRESHOLD_1QF SAI_xCR2_FTH_0 +#define SAI_FIFOTHRESHOLD_HF SAI_xCR2_FTH_1 +#define SAI_FIFOTHRESHOLD_3QF (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0) +#define SAI_FIFOTHRESHOLD_FULL SAI_xCR2_FTH_2 /** * @} */ @@ -546,11 +581,11 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode * @{ */ -#define SAI_NOCOMPANDING ((uint32_t)0x00000000U) -#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1)) -#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)) -#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL)) -#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)) +#define SAI_NOCOMPANDING 0x00000000U +#define SAI_ULAW_1CPL_COMPANDING SAI_xCR2_COMP_1 +#define SAI_ALAW_1CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0) +#define SAI_ULAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_CPL) +#define SAI_ALAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL) /** * @} */ @@ -558,8 +593,8 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Mute_Value SAI Block Mute Value * @{ */ -#define SAI_ZERO_VALUE ((uint32_t)0x00000000U) -#define SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL) +#define SAI_ZERO_VALUE 0x00000000U +#define SAI_LAST_SENT_VALUE SAI_xCR2_MUTEVAL /** * @} */ @@ -567,13 +602,13 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition * @{ */ -#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE) -#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE) -#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE) -#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE) -#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE) -#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE) -#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE) +#define SAI_IT_OVRUDR SAI_xIMR_OVRUDRIE +#define SAI_IT_MUTEDET SAI_xIMR_MUTEDETIE +#define SAI_IT_WCKCFG SAI_xIMR_WCKCFGIE +#define SAI_IT_FREQ SAI_xIMR_FREQIE +#define SAI_IT_CNRDY SAI_xIMR_CNRDYIE +#define SAI_IT_AFSDET SAI_xIMR_AFSDETIE +#define SAI_IT_LFSDET SAI_xIMR_LFSDETIE /** * @} */ @@ -581,13 +616,13 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Flags_Definition SAI Block Flags Definition * @{ */ -#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR) -#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET) -#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG) -#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ) -#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY) -#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET) -#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET) +#define SAI_FLAG_OVRUDR SAI_xSR_OVRUDR +#define SAI_FLAG_MUTEDET SAI_xSR_MUTEDET +#define SAI_FLAG_WCKCFG SAI_xSR_WCKCFG +#define SAI_FLAG_FREQ SAI_xSR_FREQ +#define SAI_FLAG_CNRDY SAI_xSR_CNRDY +#define SAI_FLAG_AFSDET SAI_xSR_AFSDET +#define SAI_FLAG_LFSDET SAI_xSR_LFSDET /** * @} */ @@ -595,12 +630,12 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level * @{ */ -#define SAI_FIFOSTATUS_EMPTY ((uint32_t)0x00000000U) -#define SAI_FIFOSTATUS_LESS1QUARTERFULL ((uint32_t)0x00010000U) -#define SAI_FIFOSTATUS_1QUARTERFULL ((uint32_t)0x00020000U) -#define SAI_FIFOSTATUS_HALFFULL ((uint32_t)0x00030000U) -#define SAI_FIFOSTATUS_3QUARTERFULL ((uint32_t)0x00040000U) -#define SAI_FIFOSTATUS_FULL ((uint32_t)0x00050000U) +#define SAI_FIFOSTATUS_EMPTY 0x00000000U +#define SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U +#define SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U +#define SAI_FIFOSTATUS_HALFFULL 0x00030000U +#define SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U +#define SAI_FIFOSTATUS_FULL 0x00050000U /** * @} */ @@ -610,19 +645,26 @@ typedef struct __SAI_HandleTypeDef */ /* Exported macro ------------------------------------------------------------*/ - /** @defgroup SAI_Exported_Macros SAI Exported Macros - * @brief macros to handle interrupts and specific configurations - * @{ - */ + * @brief macros to handle interrupts and specific configurations + * @{ + */ /** @brief Reset SAI handle state. * @param __HANDLE__ specifies the SAI Handle. * @retval None */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) +#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SAI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET) +#endif -/** @brief Enable or disable the specified SAI interrupts. +/** @brief Enable the specified SAI interrupts. * @param __HANDLE__ specifies the SAI Handle. * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: @@ -636,6 +678,20 @@ typedef struct __SAI_HandleTypeDef * @retval None */ #define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__)) + +/** @brief Disable the specified SAI interrupts. + * @param __HANDLE__ specifies the SAI Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable + * @arg SAI_IT_MUTEDET: Mute detection interrupt enable + * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable + * @arg SAI_IT_FREQ: FIFO request interrupt enable + * @arg SAI_IT_CNRDY: Codec not ready interrupt enable + * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable + * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable + * @retval None + */ #define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__))) /** @brief Check whether the specified SAI interrupt source is enabled or not. @@ -684,10 +740,19 @@ typedef struct __SAI_HandleTypeDef */ #define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__)) +/** @brief Enable SAI. + * @param __HANDLE__ specifies the SAI Handle. + * @retval None + */ #define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN) + +/** @brief Disable SAI. + * @param __HANDLE__ specifies the SAI Handle. + * @retval None + */ #define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN) - /** +/** * @} */ @@ -697,28 +762,33 @@ typedef struct __SAI_HandleTypeDef #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* Exported functions --------------------------------------------------------*/ - /** @addtogroup SAI_Exported_Functions * @{ */ /* Initialization/de-initialization functions ********************************/ - /** @addtogroup SAI_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai); -HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai); +HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai); void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai); void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai); +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) +/* SAI callbacks register/unregister functions ********************************/ +HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai, + HAL_SAI_CallbackIDTypeDef CallbackID, + pSAI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai, + HAL_SAI_CallbackIDTypeDef CallbackID); +#endif /** * @} */ /* I/O operation functions ***************************************************/ - /** @addtogroup SAI_Exported_Functions_Group2 * @{ */ @@ -813,7 +883,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); #define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \ ((PROTOCOL) == SAI_AC97_PROTOCOL) || \ - ((PROTOCOL) == SAI_SPDIF_PROTOCOL)) + ((PROTOCOL) == SAI_SPDIF_PROTOCOL)) #define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || \ ((DATASIZE) == SAI_DATASIZE_10) || \ @@ -839,10 +909,10 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); #define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \ ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE)) -#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63) +#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U) #define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \ - ((VALUE) == SAI_LAST_SENT_VALUE)) + ((VALUE) == SAI_LAST_SENT_VALUE)) #define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || \ ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \ @@ -854,7 +924,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || \ ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || \ ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || \ - ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL)) + ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL)) #define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\ ((STATE) == SAI_OUTPUT_RELEASED)) @@ -864,13 +934,13 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); #define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL) -#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16)) +#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U)) #define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \ ((SIZE) == SAI_SLOTSIZE_16B) || \ ((SIZE) == SAI_SLOTSIZE_32B)) -#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24) +#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U) #define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \ ((OFFSET) == SAI_FS_BEFOREFIRSTBIT)) @@ -883,9 +953,9 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); #define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15) -#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256)) +#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U)) -#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128)) +#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U)) /** * @} @@ -912,6 +982,6 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); } #endif -#endif /* __STM32L4xx_HAL_SAI_H */ +#endif /* STM32L4xx_HAL_SAI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai_ex.h index c262f7183f..e5dc45b00f 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai_ex.h @@ -31,21 +31,21 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_SAI_EX_H -#define __STM32L4xx_HAL_SAI_EX_H +#ifndef STM32L4xx_HAL_SAI_EX_H +#define STM32L4xx_HAL_SAI_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" - + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ @@ -55,7 +55,6 @@ */ /* Exported types ------------------------------------------------------------*/ - /** @defgroup SAIEx_Exported_Types SAIEx Exported Types * @{ */ @@ -73,7 +72,7 @@ typedef struct uint32_t RightDelay; /*!< Specifies the delay in PDM clock unit to apply on right microphone. This parameter must be a number between Min_Data = 0 and Max_Data = 7. */ -}SAIEx_PdmMicDelayParamTypeDef; +} SAIEx_PdmMicDelayParamTypeDef; /** * @} @@ -82,7 +81,6 @@ typedef struct /* Exported constants --------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ - /** @addtogroup SAIEx_Exported_Functions SAIEx Extended Exported Functions * @{ */ @@ -90,32 +88,27 @@ typedef struct /** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions * @{ */ - HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay); - /** * @} - */ + */ /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ - /** @addtogroup SAIEx_Private_Macros SAIEx Extended Private Macros * @{ */ - #define IS_SAI_PDM_MIC_DELAY(VALUE) ((VALUE) <= 7U) - /** * @} - */ + */ /** * @} - */ + */ /** * @} @@ -127,6 +120,6 @@ HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_Pdm } #endif -#endif /* __STM32L4xx_HAL_SAI_EX_H */ +#endif /* STM32L4xx_HAL_SAI_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sd.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sd.h index 9d1f59696c..c59efc746e 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sd.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sd.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_SD_H -#define __STM32L4xx_HAL_SD_H +#ifndef STM32L4xx_HAL_SD_H +#define STM32L4xx_HAL_SD_H #ifdef __cplusplus extern "C" { @@ -133,7 +133,7 @@ typedef struct /** * @brief SD handle Structure definition */ -typedef struct +typedef struct __SD_HandleTypeDef { SD_TypeDef *Instance; /*!< SD registers base address */ @@ -141,11 +141,11 @@ typedef struct HAL_LockTypeDef Lock; /*!< SD locking object */ - uint32_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */ + uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */ uint32_t TxXferSize; /*!< SD Tx Transfer size */ - uint32_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */ + uint8_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */ uint32_t RxXferSize; /*!< SD Rx Transfer size */ @@ -167,7 +167,24 @@ typedef struct uint32_t CSD[4]; /*!< SD card specific data table */ uint32_t CID[4]; /*!< SD card identification number table */ - + +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + void (* TxCpltCallback) (struct __SD_HandleTypeDef *hsd); + void (* RxCpltCallback) (struct __SD_HandleTypeDef *hsd); + void (* ErrorCallback) (struct __SD_HandleTypeDef *hsd); + void (* AbortCpltCallback) (struct __SD_HandleTypeDef *hsd); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + void (* Read_DMADblBuf0CpltCallback) (struct __SD_HandleTypeDef *hsd); + void (* Read_DMADblBuf1CpltCallback) (struct __SD_HandleTypeDef *hsd); + void (* Write_DMADblBuf0CpltCallback) (struct __SD_HandleTypeDef *hsd); + void (* Write_DMADblBuf1CpltCallback) (struct __SD_HandleTypeDef *hsd); + + void (* DriveTransceiver_1_8V_Callback) (FlagStatus status); +#endif + + void (* MspInitCallback) (struct __SD_HandleTypeDef *hsd); + void (* MspDeInitCallback) (struct __SD_HandleTypeDef *hsd); +#endif }SD_HandleTypeDef; /** @@ -208,7 +225,7 @@ typedef struct __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ __IO uint8_t Reserved3; /*!< Reserved */ __IO uint8_t ContentProtectAppli; /*!< Content protection application */ - __IO uint8_t FileFormatGrouop; /*!< File format group */ + __IO uint8_t FileFormatGroup; /*!< File format group */ __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ __IO uint8_t PermWrProtect; /*!< Permanent write protection */ __IO uint8_t TempWrProtect; /*!< Temporary write protection */ @@ -264,6 +281,41 @@ typedef struct * @} */ +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_SD_TX_CPLT_CB_ID = 0x00U, /*!< SD Tx Complete Callback ID */ + HAL_SD_RX_CPLT_CB_ID = 0x01U, /*!< SD Rx Complete Callback ID */ + HAL_SD_ERROR_CB_ID = 0x02U, /*!< SD Error Callback ID */ + HAL_SD_ABORT_CB_ID = 0x03U, /*!< SD Abort Callback ID */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID = 0x04U, /*!< SD Rx DMA Double Buffer 0 Complete Callback ID */ + HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID = 0x05U, /*!< SD Rx DMA Double Buffer 1 Complete Callback ID */ + HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID = 0x06U, /*!< SD Tx DMA Double Buffer 0 Complete Callback ID */ + HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID = 0x07U, /*!< SD Tx DMA Double Buffer 1 Complete Callback ID */ +#endif + + HAL_SD_MSP_INIT_CB_ID = 0x10U, /*!< SD MspInit Callback ID */ + HAL_SD_MSP_DEINIT_CB_ID = 0x11U /*!< SD MspDeInit Callback ID */ +}HAL_SD_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition + * @{ + */ +typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); +#endif +/** + * @} + */ +#endif /** * @} */ @@ -314,6 +366,10 @@ typedef struct #define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ #define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ #define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ + +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +#define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ +#endif /** * @} @@ -370,6 +426,19 @@ typedef struct * @brief macros to handle interrupts and specific clock configurations * @{ */ +/** @brief Reset SD handle state. + * @param __HANDLE__ : SD handle. + * @retval None + */ +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_SD_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SD_STATE_RESET) +#endif #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /** @@ -672,6 +741,17 @@ void HAL_SD_RxCpltCallback (SD_HandleTypeDef *hsd); void HAL_SD_ErrorCallback (SD_HandleTypeDef *hsd); void HAL_SD_AbortCallback (SD_HandleTypeDef *hsd); +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +/* SD callback registering/unregistering */ +HAL_StatusTypeDef HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID); + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback (SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd); +#endif +#endif + /** * @} */ @@ -798,6 +878,6 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); #endif -#endif /* __STM32L4xx_HAL_SD_H */ +#endif /* STM32L4xx_HAL_SD_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sd_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sd_ex.h index 4492c55b2f..69806a502c 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sd_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sd_ex.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_SD_EX_H -#define __STM32L4xx_HAL_SD_EX_H +#ifndef STM32L4xx_HAL_SD_EX_H +#define STM32L4xx_HAL_SD_EX_H #ifdef __cplusplus extern "C" { @@ -139,6 +139,6 @@ void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd); #endif -#endif /* __STM32L4xx_HAL_SDEx_H */ +#endif /* STM32L4xx_HAL_SDEx_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard.h index a4137f0d75..090e4c438d 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard.h @@ -38,7 +38,7 @@ #define __STM32L4xx_HAL_SMARTCARD_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -97,7 +97,7 @@ typedef struct deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */ uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler. - This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied + This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied by 2 to give the division factor of the source clock frequency */ uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */ @@ -126,7 +126,7 @@ typedef struct This parameter can be a value of @ref SMARTCARD_ClockPrescaler. */ #endif -}SMARTCARD_InitTypeDef; +} SMARTCARD_InitTypeDef; /** * @brief SMARTCARD advanced features initalization structure definition @@ -158,19 +158,19 @@ typedef struct uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. This parameter can be a value of @ref SMARTCARD_MSB_First */ - - uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when + + uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when relevant flag is available) or once guard time period has elapsed. - This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */ -}SMARTCARD_AdvFeatureInitTypeDef; + This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */ +} SMARTCARD_AdvFeatureInitTypeDef; /** * @brief HAL SMARTCARD State structures definition * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState. - * - gState contains SMARTCARD state information related to global Handle management + * - gState contains SMARTCARD state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : - * b7-b6 Error information + * b7-b6 Error information * 00 : No Error * 01 : (Not Used) * 10 : Timeout @@ -209,7 +209,7 @@ typedef enum Value is allowed for gState and RxState */ HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use Value is allowed for gState and RxState */ - HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing + HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing Value is allowed for gState only */ HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing Value is allowed for gState only */ @@ -222,21 +222,7 @@ typedef enum Value is allowed for gState only */ HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error Value is allowed for gState only */ -}HAL_SMARTCARD_StateTypeDef; - -/** - * @brief HAL SMARTCARD Error Code structure definition - */ -typedef enum -{ - HAL_SMARTCARD_ERROR_NONE = 0x00, /*!< No error */ - HAL_SMARTCARD_ERROR_PE = 0x01, /*!< Parity error */ - HAL_SMARTCARD_ERROR_NE = 0x02, /*!< Noise error */ - HAL_SMARTCARD_ERROR_FE = 0x04, /*!< frame error */ - HAL_SMARTCARD_ERROR_ORE = 0x08, /*!< Overrun error */ - HAL_SMARTCARD_ERROR_DMA = 0x10, /*!< DMA transfer error */ - HAL_SMARTCARD_ERROR_RTO = 0x20 /*!< Receiver TimeOut error */ -}HAL_SMARTCARD_ErrorTypeDef; +} HAL_SMARTCARD_StateTypeDef; /** * @brief SMARTCARD handle Structure definition @@ -262,11 +248,11 @@ typedef struct __SMARTCARD_HandleTypeDef __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */ #if defined(USART_CR1_FIFOEN) - uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ - uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ + uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. + uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value of @ref SMARTCARDEx_FIFO_mode. */ #endif @@ -280,7 +266,7 @@ typedef struct __SMARTCARD_HandleTypeDef HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management + __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management and also related to Tx operations. This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ @@ -289,20 +275,70 @@ typedef struct __SMARTCARD_HandleTypeDef uint32_t ErrorCode; /*!< SmartCard Error code */ -}SMARTCARD_HandleTypeDef; +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Tx Complete Callback */ + + void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Rx Complete Callback */ + + void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Error Callback */ + + void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Complete Callback */ + + void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Transmit Complete Callback */ + + void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Receive Complete Callback */ + + void (* RxFifoFullCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Rx Fifo Full Callback */ + + void (* TxFifoEmptyCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Tx Fifo Empty Callback */ + + + void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp Init callback */ + + void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp DeInit callback */ +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + +} SMARTCARD_HandleTypeDef; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +/** + * @brief HAL SMARTCARD Callback ID enumeration definition + */ +typedef enum +{ + HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, /*!< SMARTCARD Tx Complete Callback ID */ + HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, /*!< SMARTCARD Rx Complete Callback ID */ + HAL_SMARTCARD_ERROR_CB_ID = 0x02U, /*!< SMARTCARD Error Callback ID */ + HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U, /*!< SMARTCARD Abort Complete Callback ID */ + HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, /*!< SMARTCARD Abort Transmit Complete Callback ID */ + HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, /*!< SMARTCARD Abort Receive Complete Callback ID */ + HAL_SMARTCARD_RX_FIFO_FULL_CB_ID = 0x06U, /*!< SMARTCARD Rx Fifo Full Callback ID */ + HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID = 0x07U, /*!< SMARTCARD Tx Fifo Empty Callback ID */ + + HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, /*!< SMARTCARD MspInit callback ID */ + HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U /*!< SMARTCARD MspDeInit callback ID */ + +} HAL_SMARTCARD_CallbackIDTypeDef; + +/** + * @brief HAL SMARTCARD Callback pointer definition + */ +typedef void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard); /*!< pointer to an SMARTCARD callback function */ + +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ /** * @brief SMARTCARD clock sources */ typedef enum { - SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ - SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ - SMARTCARD_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ - SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ - SMARTCARD_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ - SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */ -}SMARTCARD_ClockSourceTypeDef; + SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ + SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ + SMARTCARD_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ + SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ + SMARTCARD_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ + SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */ +} SMARTCARD_ClockSourceTypeDef; /** * @} @@ -313,6 +349,23 @@ typedef enum * @{ */ +/** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition + * @{ + */ +#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ +#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ +#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */ +#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ +#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ +#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver TimeOut error */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ +/** + * @} + */ + /** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length * @{ */ @@ -328,8 +381,8 @@ typedef enum #define SMARTCARD_STOPBITS_1_5 USART_CR2_STOP /*!< SMARTCARD frame with 1.5 stop bits */ /** * @} - */ - + */ + /** @defgroup SMARTCARD_Parity SMARTCARD Parity * @{ */ @@ -407,7 +460,7 @@ typedef enum #if defined(USART_PRESC_PRESCALER) /** @defgroup SMARTCARD_ClockPrescaler Clock Prescaler * @{ - */ + */ #define SMARTCARD_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ #define SMARTCARD_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ #define SMARTCARD_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ @@ -519,10 +572,19 @@ typedef enum * @param __HANDLE__ SMARTCARD handle. * @retval None */ +#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1 +#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ - } while(0) + } while(0U) +#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ /** @brief Flush the Smartcard Data registers. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -532,7 +594,7 @@ typedef enum do{ \ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \ - } while(0) + } while(0U) /** @brief Clear the specified SMARTCARD pending flag. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -587,7 +649,7 @@ typedef enum * @param __HANDLE__ specifies the SMARTCARD Handle. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: - * @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available) + * @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available) * @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag * @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag * @arg @ref SMARTCARD_FLAG_BUSY Busy flag @@ -598,7 +660,7 @@ typedef enum * @arg @ref SMARTCARD_FLAG_TC Transmission complete flag * @arg @ref SMARTCARD_FLAG_RXNE Receive data register not empty flag * @arg @ref SMARTCARD_FLAG_RXFNE RXFIFO not empty flag - * @arg @ref SMARTCARD_FLAG_IDLE Idle line detection flag + * @arg @ref SMARTCARD_FLAG_IDLE Idle line detection flag * @arg @ref SMARTCARD_FLAG_ORE Overrun error flag * @arg @ref SMARTCARD_FLAG_NE Noise error flag * @arg @ref SMARTCARD_FLAG_FE Framing error flag @@ -620,10 +682,10 @@ typedef enum * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption - * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption @@ -645,10 +707,10 @@ typedef enum * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption - * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption @@ -671,10 +733,10 @@ typedef enum * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption - * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption @@ -694,10 +756,10 @@ typedef enum * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption - * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption @@ -720,10 +782,10 @@ typedef enum * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag - * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detection clear flag + * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detection clear flag * @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear Flag * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag - * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available) + * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available) * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag * @retval None @@ -742,15 +804,15 @@ typedef enum #define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) /** @brief Enable the SMARTCARD one bit sample method. - * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None - */ + */ #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the SMARTCARD one bit sample method. - * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None - */ + */ #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable the USART associated to the SMARTCARD Handle. @@ -774,13 +836,133 @@ typedef enum * @{ */ -/** @brief Check the Baud rate range. - * @note The maximum Baud Rate is derived from the maximum clock on L4 (80 MHz) +/** @brief Report the SMARTCARD clock source. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__. + */ +#if defined (STM32L432xx) || defined (STM32L442xx) +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + } while(0) +#else +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + } while(0) +#endif /* STM32L432xx || STM32L442xx */ + +/** @brief Check the Baud rate range. + * @note The maximum Baud Rate is derived from the maximum clock on L4 (120 MHz) * divided by the oversampling used on the SMARTCARD (i.e. 16). * @param __BAUDRATE__ Baud rate set by the configuration function. * @retval Test result (TRUE or FALSE) */ -#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 5000001) +#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 7500001U) /** @brief Check the block length range. * @note The maximum SMARTCARD block length is 0xFF. @@ -789,14 +971,14 @@ typedef enum */ #define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU) -/** @brief Check the receiver timeout value. +/** @brief Check the receiver timeout value. * @note The maximum SMARTCARD receiver timeout value is 0xFFFFFF. * @param __TIMEOUTVALUE__ receiver timeout value. * @retval Test result (TRUE or FALSE) */ #define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) -/** @brief Check the SMARTCARD autoretry counter value. +/** @brief Check the SMARTCARD autoretry counter value. * @note The maximum number of retransmissions is 0x7. * @param __COUNT__ number of retransmissions. * @retval Test result (TRUE or FALSE) @@ -805,51 +987,51 @@ typedef enum /** * @brief Ensure that SMARTCARD frame length is valid. - * @param __LENGTH__ SMARTCARD frame length. + * @param __LENGTH__ SMARTCARD frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) - */ + */ #define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B) /** * @brief Ensure that SMARTCARD frame number of stop bits is valid. - * @param __STOPBITS__ SMARTCARD frame number of stop bits. + * @param __STOPBITS__ SMARTCARD frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) - */ + */ #define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\ ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5)) /** * @brief Ensure that SMARTCARD frame parity is valid. - * @param __PARITY__ SMARTCARD frame parity. + * @param __PARITY__ SMARTCARD frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) - */ + */ #define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \ ((__PARITY__) == SMARTCARD_PARITY_ODD)) /** * @brief Ensure that SMARTCARD communication mode is valid. - * @param __MODE__ SMARTCARD communication mode. + * @param __MODE__ SMARTCARD communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ + */ #define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) /** * @brief Ensure that SMARTCARD frame polarity is valid. - * @param __CPOL__ SMARTCARD frame polarity. + * @param __CPOL__ SMARTCARD frame polarity. * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) - */ + */ #define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH)) /** * @brief Ensure that SMARTCARD frame phase is valid. - * @param __CPHA__ SMARTCARD frame phase. + * @param __CPHA__ SMARTCARD frame phase. * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) */ #define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE)) /** * @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid. - * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting. + * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting. * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) */ #define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \ @@ -857,7 +1039,7 @@ typedef enum /** * @brief Ensure that SMARTCARD frame sampling is valid. - * @param __ONEBIT__ SMARTCARD frame sampling. + * @param __ONEBIT__ SMARTCARD frame sampling. * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) */ #define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \ @@ -865,7 +1047,7 @@ typedef enum /** * @brief Ensure that SMARTCARD NACK transmission setting is valid. - * @param __NACK__ SMARTCARD NACK transmission setting. + * @param __NACK__ SMARTCARD NACK transmission setting. * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid) */ #define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \ @@ -873,15 +1055,16 @@ typedef enum /** * @brief Ensure that SMARTCARD receiver timeout setting is valid. - * @param __TIMEOUT__ SMARTCARD receiver timeout setting. + * @param __TIMEOUT__ SMARTCARD receiver timeout setting. * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) */ #define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \ ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE)) +#if defined(USART_PRESC_PRESCALER) /** * @brief Ensure that SMARTCARD clock Prescaler is valid. - * @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value. + * @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value. * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) */ #define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1) || \ @@ -896,42 +1079,11 @@ typedef enum ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64) || \ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256)) - -/** - * @brief Ensure that SMARTCARD FIFO mode is valid. - * @param __STATE__ SMARTCARD FIFO mode. - * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) - */ -#define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \ - ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE)) - -/** - * @brief Ensure that SMARTCARD TXFIFO threshold level is valid. - * @param __THRESHOLD__ SMARTCARD TXFIFO threshold level. - * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) - */ -#define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8)) - -/** - * @brief Ensure that SMARTCARD RXFIFO threshold level is valid. - * @param __THRESHOLD__ SMARTCARD RXFIFO threshold level. - * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) - */ -#define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8)) +#endif /** * @brief Ensure that SMARTCARD advanced features initialization is valid. - * @param __INIT__ SMARTCARD advanced features initialization. + * @param __INIT__ SMARTCARD advanced features initialization. * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT | \ @@ -945,7 +1097,7 @@ typedef enum /** * @brief Ensure that SMARTCARD frame TX inversion setting is valid. - * @param __TXINV__ SMARTCARD frame TX inversion setting. + * @param __TXINV__ SMARTCARD frame TX inversion setting. * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \ @@ -953,7 +1105,7 @@ typedef enum /** * @brief Ensure that SMARTCARD frame RX inversion setting is valid. - * @param __RXINV__ SMARTCARD frame RX inversion setting. + * @param __RXINV__ SMARTCARD frame RX inversion setting. * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \ @@ -961,7 +1113,7 @@ typedef enum /** * @brief Ensure that SMARTCARD frame data inversion setting is valid. - * @param __DATAINV__ SMARTCARD frame data inversion setting. + * @param __DATAINV__ SMARTCARD frame data inversion setting. * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \ @@ -969,7 +1121,7 @@ typedef enum /** * @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid. - * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting. + * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting. * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \ @@ -977,7 +1129,7 @@ typedef enum /** * @brief Ensure that SMARTCARD frame overrun setting is valid. - * @param __OVERRUN__ SMARTCARD frame overrun setting. + * @param __OVERRUN__ SMARTCARD frame overrun setting. * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) */ #define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \ @@ -985,7 +1137,7 @@ typedef enum /** * @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid. - * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting. + * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting. * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \ @@ -993,7 +1145,7 @@ typedef enum /** * @brief Ensure that SMARTCARD frame MSB first setting is valid. - * @param __MSBFIRST__ SMARTCARD frame MSB first setting. + * @param __MSBFIRST__ SMARTCARD frame MSB first setting. * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \ @@ -1001,7 +1153,7 @@ typedef enum /** * @brief Ensure that SMARTCARD request parameter is valid. - * @param __PARAM__ SMARTCARD request parameter. + * @param __PARAM__ SMARTCARD request parameter. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ #define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \ @@ -1030,6 +1182,12 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard); void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard); void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard); +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + /** * @} */ @@ -1057,15 +1215,14 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard); void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard); -void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard); -void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard); -void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); /** * @} */ -/* Peripheral Control functions ***********************************************/ /* Peripheral State and Error functions ***************************************/ /** @addtogroup SMARTCARD_Exported_Functions_Group4 * @{ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard_ex.h index ab37deb67a..1f246ddbcc 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard_ex.h @@ -38,7 +38,7 @@ #define __STM32L4xx_HAL_SMARTCARD_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -52,19 +52,19 @@ * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @addtogroup SMARTCARDEx_Exported_Constants SMARTCARD Extended Exported Constants * @{ */ - + /** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication * @{ */ #if defined(USART_TCBGT_SUPPORT) #define SMARTCARD_TCBGT SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */ -#endif /* USART_TCBGT_SUPPORT */ +#endif /* USART_TCBGT_SUPPORT */ #define SMARTCARD_TC SMARTCARD_IT_TC /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */ /** * @} @@ -73,7 +73,7 @@ /** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type * @{ */ -#define SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ +#define SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ #define SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ #define SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ #define SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ @@ -89,8 +89,18 @@ */ #if defined(USART_CR1_FIFOEN) +/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARDEx FIFO mode + * @brief SMARTCARD FIFO mode + * @{ + */ +#define SMARTCARD_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ + /** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARDEx TXFIFO threshold level - * @brief SMARTCARD TXFIFO level + * @brief SMARTCARD TXFIFO level * @{ */ #define SMARTCARD_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ @@ -102,9 +112,9 @@ /** * @} */ - + /** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARDEx RXFIFO threshold level - * @brief SMARTCARD RXFIFO level + * @brief SMARTCARD RXFIFO level * @{ */ #define SMARTCARD_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ @@ -158,7 +168,7 @@ /** * @} */ - + /** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition * Elements values convention: 000ZZZZZ0XXYYYYYb * - YYYYY : Interrupt source position in the XX register (5 bits) @@ -172,25 +182,25 @@ #define SMARTCARD_IT_PE 0x0028U /*!< SMARTCARD parity error interruption */ #define SMARTCARD_IT_TXE 0x0727U /*!< SMARTCARD transmit data register empty interruption */ #if defined(USART_CR1_FIFOEN) -#define SMARTCARD_IT_TXFNF 0x0727U /*!< SMARTCARD TX FIFO not full interruption */ +#define SMARTCARD_IT_TXFNF 0x0727U /*!< SMARTCARD TX FIFO not full interruption */ #endif #define SMARTCARD_IT_TC 0x0626U /*!< SMARTCARD transmission complete interruption */ #define SMARTCARD_IT_RXNE 0x0525U /*!< SMARTCARD read data register not empty interruption */ #if defined(USART_CR1_FIFOEN) -#define SMARTCARD_IT_RXFNE 0x0525U /*!< SMARTCARD RXFIFO not empty interruption */ +#define SMARTCARD_IT_RXFNE 0x0525U /*!< SMARTCARD RXFIFO not empty interruption */ #endif #define SMARTCARD_IT_IDLE 0x0424U /*!< SMARTCARD idle line detection interruption */ - + #define SMARTCARD_IT_ERR 0x0060U /*!< SMARTCARD error interruption */ #define SMARTCARD_IT_ORE 0x0300U /*!< SMARTCARD overrun error interruption */ #define SMARTCARD_IT_NE 0x0200U /*!< SMARTCARD noise error interruption */ #define SMARTCARD_IT_FE 0x0100U /*!< SMARTCARD frame error interruption */ -#define SMARTCARD_IT_EOB 0x0C3BU /*!< SMARTCARD end of block interruption */ +#define SMARTCARD_IT_EOB 0x0C3BU /*!< SMARTCARD end of block interruption */ #define SMARTCARD_IT_RTO 0x0B3AU /*!< SMARTCARD receiver timeout interruption */ #if defined(USART_TCBGT_SUPPORT) #define SMARTCARD_IT_TCBGT 0x1978U /*!< SMARTCARD transmission complete before guard time completion interruption */ -#endif +#endif /* USART_TCBGT_SUPPORT */ #if defined(USART_CR1_FIFOEN) #define SMARTCARD_IT_RXFF 0x183FU /*!< SMARTCARD RXFIFO full interruption */ @@ -201,13 +211,13 @@ /** * @} */ - + /** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags * @{ */ #define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */ #define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */ -#define SMARTCARD_CLEAR_NEF USART_ICR_NECF /*!< SMARTCARD noise detected clear flag */ +#define SMARTCARD_CLEAR_NEF USART_ICR_NECF /*!< SMARTCARD noise error detected clear flag */ #define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */ #define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */ #if defined(USART_CR1_FIFOEN) @@ -216,193 +226,53 @@ #define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */ #if defined(USART_TCBGT_SUPPORT) #define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */ -#endif +#endif /* USART_TCBGT_SUPPORT */ #define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */ #define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup SMARTCARDEx_Private_Constants SMARTCARDEx Private Constants - * @{ - */ -#if defined(USART_CR1_FIFOEN) -/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARDEx FIFO mode - * @{ - */ -#define SMARTCARD_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ -#define SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ /** * @} */ -#endif + /** * @} */ - +/* Exported macros -----------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros * @{ */ - -/** @brief Report the SMARTCARD clock source. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __CLOCKSOURCE__: output variable. - * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__. - */ -#if defined (STM32L432xx) || defined (STM32L442xx) -#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - } while(0) -#else -#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART3) \ - { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ - case RCC_USART3CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART3CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART3CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART3CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - } while(0) -#endif /* STM32L432xx || STM32L442xx */ /** @brief Set the Transmission Completion flag * @param __HANDLE__ specifies the SMARTCARD Handle. - * @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if - * AdvancedInit.TxCompletionIndication is not already filled, the latter is forced - * to SMARTCARD_TC (transmission completion indication when guard time has elapsed). + * @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if + * AdvancedInit.TxCompletionIndication is not already filled, the latter is forced + * to SMARTCARD_TC (transmission completion indication when guard time has elapsed). * @retval None */ #if defined(USART_TCBGT_SUPPORT) -#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \ - do { \ - if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \ - { \ +#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \ + do { \ + if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \ + { \ (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \ - } \ - else \ - { \ + } \ + else \ + { \ assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \ - } \ - } while(0) + } \ + } while(0U) #else #define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \ do { \ (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \ - } while(0) -#endif + } while(0U) +#endif /* USART_TCBGT_SUPPORT */ /** @brief Return the transmission completion flag. * @param __HANDLE__ specifies the SMARTCARD Handle. * @note Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag. * When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is - * reported. + * reported. * @retval Transmission completion flag */ #if defined(USART_TCBGT_SUPPORT) @@ -410,20 +280,52 @@ (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT)) #else #define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (SMARTCARD_FLAG_TC) -#endif +#endif /* USART_TCBGT_SUPPORT */ /** * @brief Ensure that SMARTCARD frame transmission completion used flag is valid. - * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag. + * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag. * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid) - */ + */ #if defined(USART_TCBGT_SUPPORT) #define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) ||\ ((__TXCOMPLETE__) == SMARTCARD_TC)) #else #define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) ((__TXCOMPLETE__) == SMARTCARD_TC) -#endif +#endif /* USART_TCBGT_SUPPORT */ + +/** + * @brief Ensure that SMARTCARD FIFO mode is valid. + * @param __STATE__ SMARTCARD FIFO mode. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \ + ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE)) + +/** + * @brief Ensure that SMARTCARD TXFIFO threshold level is valid. + * @param __THRESHOLD__ SMARTCARD TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that SMARTCARD RXFIFO threshold level is valid. + * @param __THRESHOLD__ SMARTCARD RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8)) /** * @} @@ -435,6 +337,23 @@ */ /* Initialization and de-initialization functions ****************************/ +/* IO operation methods *******************************************************/ + +/** @addtogroup SMARTCARDEx_Exported_Functions_Group1 + * @{ + */ + +/* Peripheral Control functions ***********************************************/ +void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength); +void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue); +HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ /** @addtogroup SMARTCARDEx_Exported_Functions_Group2 * @{ */ @@ -449,17 +368,11 @@ void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard); * @} */ - /** @addtogroup SMARTCARDEx_Exported_Functions_Group3 * @{ */ /* Peripheral Control functions ***********************************************/ -void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength); -void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue); -HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); -HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); - #if defined(USART_CR1_FIFOEN) HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard); HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard); diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smbus.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smbus.h index d98f977b06..c3b63d2f8f 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smbus.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smbus.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_SMBUS_H -#define __STM32L4xx_HAL_SMBUS_H +#ifndef STM32L4xx_HAL_SMBUS_H +#define STM32L4xx_HAL_SMBUS_H #ifdef __cplusplus extern "C" { @@ -136,6 +136,10 @@ typedef struct #define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ +#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ /** * @} */ @@ -144,7 +148,7 @@ typedef struct * @brief SMBUS handle Structure definition * @{ */ -typedef struct +typedef struct __SMBUS_HandleTypeDef { I2C_TypeDef *Instance; /*!< SMBUS registers base address */ @@ -166,7 +170,47 @@ typedef struct __IO uint32_t ErrorCode; /*!< SMBUS Error code */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Listen Complete callback */ + void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Error callback */ + + void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< SMBUS Slave Address Match callback */ + + void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp Init callback */ + void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp DeInit callback */ + +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } SMBUS_HandleTypeDef; + +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +/** + * @brief HAL SMBUS Callback ID enumeration definition + */ +typedef enum +{ + HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */ + HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */ + HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */ + HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */ + HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */ + HAL_SMBUS_ERROR_CB_ID = 0x05U, /*!< SMBUS Error callback ID */ + + HAL_SMBUS_MSPINIT_CB_ID = 0x06U, /*!< SMBUS Msp Init callback ID */ + HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U /*!< SMBUS Msp DeInit callback ID */ + +} HAL_SMBUS_CallbackIDTypeDef; + +/** + * @brief HAL SMBUS Callback pointer definition + */ +typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an SMBUS callback function */ +typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an SMBUS Address Match callback function */ + +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ /** * @} */ @@ -234,7 +278,7 @@ typedef struct * @} */ -/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode +/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode * @{ */ #define SMBUS_NOSTRETCH_DISABLE (0x00000000U) @@ -373,7 +417,15 @@ typedef struct * @param __HANDLE__ specifies the SMBUS Handle. * @retval None */ -#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) +#endif /** @brief Enable the specified SMBUS interrupts. * @param __HANDLE__ specifies the SMBUS Handle. @@ -590,7 +642,7 @@ typedef struct * @{ */ -/* Initialization and de-initialization functions **********************************/ +/* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); @@ -598,6 +650,14 @@ void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ /** * @} */ @@ -694,6 +754,6 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); #endif -#endif /* __STM32L4xx_HAL_SMBUS_H */ +#endif /* STM32L4xx_HAL_SMBUS_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h index 9fb6b07edc..c34a4e9918 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h @@ -163,8 +163,46 @@ typedef struct __SPI_HandleTypeDef __IO uint32_t ErrorCode; /*!< SPI Error code */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ + void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ + void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ + void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ + void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ + void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ + void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ + void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ + void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ + void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } SPI_HandleTypeDef; +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +/** + * @brief HAL SPI Callback ID enumeration definition + */ +typedef enum +{ + HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */ + HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */ + HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */ + HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */ + HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */ + HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */ + HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */ + HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */ + HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */ + HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */ + +} HAL_SPI_CallbackIDTypeDef; + +/** + * @brief HAL SPI Callback pointer definition + */ +typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ /** * @} */ @@ -185,6 +223,9 @@ typedef struct __SPI_HandleTypeDef #define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ #define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */ #define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */ +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ /** * @} */ @@ -400,7 +441,15 @@ typedef struct __SPI_HandleTypeDef * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) +#endif /** @brief Enable the specified SPI interrupts. * @param __HANDLE__ specifies the SPI Handle. @@ -708,6 +757,12 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sram.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sram.h index d26da491ff..b0f9deb515 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sram.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sram.h @@ -31,7 +31,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L4xx_HAL_SRAM_H @@ -41,9 +41,7 @@ extern "C" { #endif -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(FMC_BANK1) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_ll_fmc.h" @@ -51,47 +49,44 @@ /** @addtogroup STM32L4xx_HAL_Driver * @{ */ - /** @addtogroup SRAM * @{ - */ + */ /* Exported typedef ----------------------------------------------------------*/ /** @defgroup SRAM_Exported_Types SRAM Exported Types * @{ */ -/** - * @brief HAL SRAM State structures definition - */ +/** + * @brief HAL SRAM State structures definition + */ typedef enum { - HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */ - HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */ - HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */ - HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */ - HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */ - + HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */ + HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */ + HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */ + HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */ + HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */ }HAL_SRAM_StateTypeDef; -/** - * @brief SRAM handle Structure definition - */ +/** + * @brief SRAM handle Structure definition + */ typedef struct { - FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ - + FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ + FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ - + FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ - HAL_LockTypeDef Lock; /*!< SRAM locking object */ - + HAL_LockTypeDef Lock; /*!< SRAM locking object */ + __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ - + DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ - -}SRAM_HandleTypeDef; +}SRAM_HandleTypeDef; /** * @} @@ -104,8 +99,8 @@ typedef struct * @{ */ -/** @brief Reset SRAM handle state. - * @param __HANDLE__: SRAM handle +/** @brief Reset SRAM handle state + * @param __HANDLE__ SRAM handle * @retval None */ #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) @@ -129,9 +124,6 @@ HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); -void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); -void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); - /** * @} */ @@ -150,10 +142,13 @@ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); +void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); +void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); + /** * @} */ - + /** @addtogroup SRAM_Exported_Functions_Group3 Control functions * @{ */ @@ -170,28 +165,26 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); * @{ */ -/* SRAM Peripheral State functions ********************************************/ +/* SRAM State functions ******************************************************/ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); /** * @} - */ + */ /** * @} */ - + /** * @} - */ + */ /** * @} */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* FMC_BANK1 */ #ifdef __cplusplus } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_swpmi.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_swpmi.h index 5b1159138c..29669d233f 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_swpmi.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_swpmi.h @@ -41,10 +41,6 @@ extern "C" { #endif -#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -52,6 +48,8 @@ * @{ */ +#if defined(SWPMI1) + /** @addtogroup SWPMI * @{ */ @@ -102,36 +100,67 @@ typedef enum /** * @brief SWPMI handle Structure definition */ -typedef struct +typedef struct __SWPMI_HandleTypeDef { - SWPMI_TypeDef *Instance; /* SWPMI registers base address */ + SWPMI_TypeDef *Instance; /*!< SWPMI registers base address */ - SWPMI_InitTypeDef Init; /* SWMPI communication parameters */ + SWPMI_InitTypeDef Init; /*!< SWPMI communication parameters */ - uint32_t *pTxBuffPtr; /* Pointer to SWPMI Tx transfer Buffer */ + uint32_t *pTxBuffPtr; /*!< Pointer to SWPMI Tx transfer Buffer */ - uint32_t TxXferSize; /* SWPMI Tx Transfer size */ + uint32_t TxXferSize; /*!< SWPMI Tx Transfer size */ - uint32_t TxXferCount; /* SWPMI Tx Transfer Counter */ + uint32_t TxXferCount; /*!< SWPMI Tx Transfer Counter */ - uint32_t *pRxBuffPtr; /* Pointer to SWPMI Rx transfer Buffer */ + uint32_t *pRxBuffPtr; /*!< Pointer to SWPMI Rx transfer Buffer */ - uint32_t RxXferSize; /* SWPMI Rx Transfer size */ + uint32_t RxXferSize; /*!< SWPMI Rx Transfer size */ - uint32_t RxXferCount; /* SWPMI Rx Transfer Counter */ + uint32_t RxXferCount; /*!< SWPMI Rx Transfer Counter */ - DMA_HandleTypeDef *hdmatx; /* SWPMI Tx DMA Handle parameters */ + DMA_HandleTypeDef *hdmatx; /*!< SWPMI Tx DMA Handle parameters */ - DMA_HandleTypeDef *hdmarx; /* SWPMI Rx DMA Handle parameters */ + DMA_HandleTypeDef *hdmarx; /*!< SWPMI Rx DMA Handle parameters */ - HAL_LockTypeDef Lock; /* SWPMI object */ + HAL_LockTypeDef Lock; /*!< SWPMI object */ - __IO HAL_SWPMI_StateTypeDef State; /* SWPMI communication state */ + __IO HAL_SWPMI_StateTypeDef State; /*!< SWPMI communication state */ - __IO uint32_t ErrorCode; /* SWPMI Error code */ + __IO uint32_t ErrorCode; /*!< SWPMI Error code */ + +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + void (*RxCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive complete callback */ + void (*RxHalfCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive half complete callback */ + void (*TxCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit complete callback */ + void (*TxHalfCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit half complete callback */ + void (*ErrorCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI error callback */ + void (*MspInitCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP init callback */ + void (*MspDeInitCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP de-init callback */ +#endif }SWPMI_HandleTypeDef; +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) +/** + * @brief SWPMI callback ID enumeration definition + */ +typedef enum +{ + HAL_SWPMI_RX_COMPLETE_CB_ID = 0x00U, /*!< SWPMI receive complete callback ID */ + HAL_SWPMI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SWPMI receive half complete callback ID */ + HAL_SWPMI_TX_COMPLETE_CB_ID = 0x02U, /*!< SWPMI transmit complete callback ID */ + HAL_SWPMI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SWPMI transmit half complete callback ID */ + HAL_SWPMI_ERROR_CB_ID = 0x04U, /*!< SWPMI error callback ID */ + HAL_SWPMI_MSPINIT_CB_ID = 0x05U, /*!< SWPMI MSP init callback ID */ + HAL_SWPMI_MSPDEINIT_CB_ID = 0x06U /*!< SWPMI MSP de-init callback ID */ +}HAL_SWPMI_CallbackIDTypeDef; + +/** + * @brief SWPMI callback pointer definition + */ +typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi); +#endif + /** * @} */ @@ -145,11 +174,16 @@ typedef struct * @defgroup SWPMI_Error_Code SWPMI Error Code Bitmap * @{ */ -#define HAL_SWPMI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_SWPMI_ERROR_CRC ((uint32_t)0x00000004) /*!< frame error */ -#define HAL_SWPMI_ERROR_OVR ((uint32_t)0x00000008) /*!< Overrun error */ -#define HAL_SWPMI_ERROR_UDR ((uint32_t)0x0000000C) /*!< Underrun error */ -#define HAL_SWPMI_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */ +#define HAL_SWPMI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ +#define HAL_SWPMI_ERROR_CRC ((uint32_t)0x00000004) /*!< frame error */ +#define HAL_SWPMI_ERROR_OVR ((uint32_t)0x00000008) /*!< Overrun error */ +#define HAL_SWPMI_ERROR_UDR ((uint32_t)0x0000000C) /*!< Underrun error */ +#define HAL_SWPMI_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */ +#define HAL_SWPMI_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Transfer timeout */ +#define HAL_SWPMI_ERROR_TXBEF_TIMEOUT ((uint32_t)0x00000040) /*!< End Tx buffer timeout */ +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) +#define HAL_SWPMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100) /*!< Invalid callback error */ +#endif /** * @} */ @@ -231,123 +265,131 @@ typedef struct */ /** @brief Reset SWPMI handle state. - * @param __HANDLE__: specifies the SWPMI Handle. + * @param __HANDLE__ specifies the SWPMI Handle. * @retval None */ +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) +#define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SWPMI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SWPMI_STATE_RESET) +#endif /** * @brief Enable the SWPMI peripheral. - * @param __HANDLE__: SWPMI handle + * @param __HANDLE__ SWPMI handle * @retval None */ #define __HAL_SWPMI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT) /** * @brief Disable the SWPMI peripheral. - * @param __HANDLE__: SWPMI handle + * @param __HANDLE__ SWPMI handle * @retval None */ #define __HAL_SWPMI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT) /** @brief Check whether the specified SWPMI flag is set or not. - * @param __HANDLE__: specifies the SWPMI Handle. + * @param __HANDLE__ specifies the SWPMI Handle. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: - * @arg SWPMI_FLAG_RXBFF : Receive buffer full flag. - * @arg SWPMI_FLAG_TXBEF : Transmit buffer empty flag. - * @arg SWPMI_FLAG_RXBERF : Receive CRC error flag. - * @arg SWPMI_FLAG_RXOVRF : Receive overrun error flag. - * @arg SWPMI_FLAG_TXUNRF : Transmit underrun error flag. - * @arg SWPMI_FLAG_RXNE : Receive data register not empty. - * @arg SWPMI_FLAG_TXE : Transmit data register empty. - * @arg SWPMI_FLAG_TCF : Transfer complete flag. - * @arg SWPMI_FLAG_SRF : Slave resume flag. - * @arg SWPMI_FLAG_SUSP : SUSPEND flag. - * @arg SWPMI_FLAG_DEACTF : DEACTIVATED flag. + * @arg SWPMI_FLAG_RXBFF Receive buffer full flag. + * @arg SWPMI_FLAG_TXBEF Transmit buffer empty flag. + * @arg SWPMI_FLAG_RXBERF Receive CRC error flag. + * @arg SWPMI_FLAG_RXOVRF Receive overrun error flag. + * @arg SWPMI_FLAG_TXUNRF Transmit underrun error flag. + * @arg SWPMI_FLAG_RXNE Receive data register not empty. + * @arg SWPMI_FLAG_TXE Transmit data register empty. + * @arg SWPMI_FLAG_TCF Transfer complete flag. + * @arg SWPMI_FLAG_SRF Slave resume flag. + * @arg SWPMI_FLAG_SUSP SUSPEND flag. + * @arg SWPMI_FLAG_DEACTF DEACTIVATED flag. * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_SWPMI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__)) /** @brief Clear the specified SWPMI ISR flag. - * @param __HANDLE__: specifies the SWPMI Handle. + * @param __HANDLE__ specifies the SWPMI Handle. * @param __FLAG__: specifies the flag to clear. * This parameter can be one of the following values: - * @arg SWPMI_FLAG_RXBFF : Receive buffer full flag. - * @arg SWPMI_FLAG_TXBEF : Transmit buffer empty flag. - * @arg SWPMI_FLAG_RXBERF : Receive CRC error flag. - * @arg SWPMI_FLAG_RXOVRF : Receive overrun error flag. - * @arg SWPMI_FLAG_TXUNRF : Transmit underrun error flag. - * @arg SWPMI_FLAG_TCF : Transfer complete flag. - * @arg SWPMI_FLAG_SRF : Slave resume flag. + * @arg SWPMI_FLAG_RXBFF Receive buffer full flag. + * @arg SWPMI_FLAG_TXBEF Transmit buffer empty flag. + * @arg SWPMI_FLAG_RXBERF Receive CRC error flag. + * @arg SWPMI_FLAG_RXOVRF Receive overrun error flag. + * @arg SWPMI_FLAG_TXUNRF Transmit underrun error flag. + * @arg SWPMI_FLAG_TCF Transfer complete flag. + * @arg SWPMI_FLAG_SRF Slave resume flag. * @retval None */ #define __HAL_SWPMI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__)) /** @brief Enable the specified SWPMI interrupt. - * @param __HANDLE__: specifies the SWPMI Handle. - * @param __INTERRUPT__: specifies the SWPMI interrupt source to enable. + * @param __HANDLE__ specifies the SWPMI Handle. + * @param __INTERRUPT__ specifies the SWPMI interrupt source to enable. * This parameter can be one of the following values: - * @arg SWPMI_IT_SRIE : Slave resume interrupt. - * @arg SWPMI_IT_TCIE : Transmit complete interrupt. - * @arg SWPMI_IT_TIE : Transmit interrupt. - * @arg SWPMI_IT_RIE : Receive interrupt. - * @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt. - * @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt. - * @arg SWPMI_IT_RXBEIE : Receive CRC error interrupt. - * @arg SWPMI_IT_TXBEIE : Transmit buffer empty interrupt. - * @arg SWPMI_IT_RXBFIE : Receive buffer full interrupt. + * @arg SWPMI_IT_SRIE Slave resume interrupt. + * @arg SWPMI_IT_TCIE Transmit complete interrupt. + * @arg SWPMI_IT_TIE Transmit interrupt. + * @arg SWPMI_IT_RIE Receive interrupt. + * @arg SWPMI_IT_TXUNRIE Transmit underrun error interrupt. + * @arg SWPMI_IT_RXOVRIE Receive overrun error interrupt. + * @arg SWPMI_IT_RXBEIE Receive CRC error interrupt. + * @arg SWPMI_IT_TXBEIE Transmit buffer empty interrupt. + * @arg SWPMI_IT_RXBFIE Receive buffer full interrupt. * @retval None */ #define __HAL_SWPMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)) /** @brief Disable the specified SWPMI interrupt. - * @param __HANDLE__: specifies the SWPMI Handle. - * @param __INTERRUPT__: specifies the SWPMI interrupt source to disable. + * @param __HANDLE__ specifies the SWPMI Handle. + * @param __INTERRUPT__ specifies the SWPMI interrupt source to disable. * This parameter can be one of the following values: - * @arg SWPMI_IT_SRIE : Slave resume interrupt. - * @arg SWPMI_IT_TCIE : Transmit complete interrupt. - * @arg SWPMI_IT_TIE : Transmit interrupt. - * @arg SWPMI_IT_RIE : Receive interrupt. - * @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt. - * @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt. - * @arg SWPMI_IT_RXBEIE : Receive CRC error interrupt. - * @arg SWPMI_IT_TXBEIE : Transmit buffer empty interrupt. - * @arg SWPMI_IT_RXBFIE : Receive buffer full interrupt. + * @arg SWPMI_IT_SRIE Slave resume interrupt. + * @arg SWPMI_IT_TCIE Transmit complete interrupt. + * @arg SWPMI_IT_TIE Transmit interrupt. + * @arg SWPMI_IT_RIE Receive interrupt. + * @arg SWPMI_IT_TXUNRIE Transmit underrun error interrupt. + * @arg SWPMI_IT_RXOVRIE Receive overrun error interrupt. + * @arg SWPMI_IT_RXBEIE Receive CRC error interrupt. + * @arg SWPMI_IT_TXBEIE Transmit buffer empty interrupt. + * @arg SWPMI_IT_RXBFIE Receive buffer full interrupt. * @retval None */ #define __HAL_SWPMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)) /** @brief Check whether the specified SWPMI interrupt has occurred or not. - * @param __HANDLE__: specifies the SWPMI Handle. - * @param __IT__: specifies the SWPMI interrupt to check. + * @param __HANDLE__ specifies the SWPMI Handle. + * @param __IT__ specifies the SWPMI interrupt to check. * This parameter can be one of the following values: - * @arg SWPMI_IT_SRIE : Slave resume interrupt. - * @arg SWPMI_IT_TCIE : Transmit complete interrupt. - * @arg SWPMI_IT_TIE : Transmit interrupt. - * @arg SWPMI_IT_RIE : Receive interrupt. - * @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt. - * @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt. - * @arg SWPMI_IT_RXBERIE : Receive CRC error interrupt. - * @arg SWPMI_IT_TXBEIE : Transmit buffer empty interrupt. - * @arg SWPMI_IT_RXBFIE : Receive buffer full interrupt. + * @arg SWPMI_IT_SRIE Slave resume interrupt. + * @arg SWPMI_IT_TCIE Transmit complete interrupt. + * @arg SWPMI_IT_TIE Transmit interrupt. + * @arg SWPMI_IT_RIE Receive interrupt. + * @arg SWPMI_IT_TXUNRIE Transmit underrun error interrupt. + * @arg SWPMI_IT_RXOVRIE Receive overrun error interrupt. + * @arg SWPMI_IT_RXBERIE Receive CRC error interrupt. + * @arg SWPMI_IT_TXBEIE Transmit buffer empty interrupt. + * @arg SWPMI_IT_RXBFIE Receive buffer full interrupt. * @retval The new state of __IT__ (TRUE or FALSE). */ #define __HAL_SWPMI_GET_IT(__HANDLE__, __IT__) (READ_BIT((__HANDLE__)->Instance->ISR,(__IT__)) == (__IT__)) /** @brief Check whether the specified SWPMI interrupt source is enabled or not. - * @param __HANDLE__: specifies the SWPMI Handle. - * @param __IT__: specifies the SWPMI interrupt source to check. + * @param __HANDLE__ specifies the SWPMI Handle. + * @param __IT__ specifies the SWPMI interrupt source to check. * This parameter can be one of the following values: - * @arg SWPMI_IT_SRIE : Slave resume interrupt. - * @arg SWPMI_IT_TCIE : Transmit complete interrupt. - * @arg SWPMI_IT_TIE : Transmit interrupt. - * @arg SWPMI_IT_RIE : Receive interrupt. - * @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt. - * @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt. - * @arg SWPMI_IT_RXBERIE : Receive CRC error interrupt. - * @arg SWPMI_IT_TXBEIE : Transmit buffer empty interrupt. - * @arg SWPMI_IT_RXBFIE : Receive buffer full interrupt. + * @arg SWPMI_IT_SRIE Slave resume interrupt. + * @arg SWPMI_IT_TCIE Transmit complete interrupt. + * @arg SWPMI_IT_TIE Transmit interrupt. + * @arg SWPMI_IT_RIE Receive interrupt. + * @arg SWPMI_IT_TXUNRIE Transmit underrun error interrupt. + * @arg SWPMI_IT_RXOVRIE Receive overrun error interrupt. + * @arg SWPMI_IT_RXBERIE Receive CRC error interrupt. + * @arg SWPMI_IT_TXBEIE Transmit buffer empty interrupt. + * @arg SWPMI_IT_RXBFIE Receive buffer full interrupt. * @retval The new state of __IT__ (TRUE or FALSE). */ #define __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET) @@ -366,6 +408,15 @@ HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi); void HAL_SWPMI_MspInit(SWPMI_HandleTypeDef *hswpmi); void HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi); +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) +/* SWPMI callbacks register/unregister functions ********************************/ +HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef *hswpmi, + HAL_SWPMI_CallbackIDTypeDef CallbackID, + pSWPMI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback(SWPMI_HandleTypeDef *hswpmi, + HAL_SWPMI_CallbackIDTypeDef CallbackID); +#endif + /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout); @@ -404,7 +455,7 @@ uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi); /** @defgroup SWPMI_Private_Variables SWPMI Private Variables * @{ */ - + /** * @} */ @@ -445,14 +496,12 @@ uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi); * @} */ +#endif /* SWPMI1 */ + /** * @} */ -#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ - #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h index 9b8375ec07..e8cb420ce2 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h @@ -34,11 +34,11 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_TIM_H -#define __STM32L4xx_HAL_TIM_H +#ifndef STM32L4xx_HAL_TIM_H +#define STM32L4xx_HAL_TIM_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -81,8 +81,8 @@ typedef struct This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. - @note This parameter is valid only for TIM1 and TIM8. */ + GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. This parameter can be a value of @ref TIM_AutoReloadPreload */ @@ -104,20 +104,20 @@ typedef struct uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ + @note This parameter is valid only for timer instances supporting break feature. */ - uint32_t OCFastMode; /*!< Specifies the Fast mode state. + uint32_t OCFastMode; /*!< Specifies the Fast mode state. This parameter can be a value of @ref TIM_Output_Fast_State @note This parameter is valid only in PWM1 and PWM2 mode. */ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ + @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ + @note This parameter is valid only for timer instances supporting break feature. */ } TIM_OC_InitTypeDef; /** @@ -136,15 +136,15 @@ typedef struct uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ + @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ + @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ + @note This parameter is valid only for timer instances supporting break feature. */ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ @@ -156,14 +156,13 @@ typedef struct This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_OnePulse_InitTypeDef; - /** * @brief TIM Input Capture Configuration Structure definition */ typedef struct { - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ uint32_t ICSelection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ @@ -208,7 +207,6 @@ typedef struct This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_Encoder_InitTypeDef; - /** * @brief Clock Configuration Handle Structure definition */ @@ -220,12 +218,12 @@ typedef struct This parameter can be a value of @ref TIM_Clock_Polarity */ uint32_t ClockPrescaler; /*!< TIM clock prescaler This parameter can be a value of @ref TIM_Clock_Prescaler */ - uint32_t ClockFilter; /*!< TIM clock filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -}TIM_ClockConfigTypeDef; + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClockConfigTypeDef; /** - * @brief Clear Input Configuration Handle Structure definition + * @brief TIM Clear Input Configuration Handle Structure definition */ typedef struct { @@ -237,40 +235,42 @@ typedef struct This parameter can be a value of @ref TIM_ClearInput_Polarity */ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler This parameter can be a value of @ref TIM_ClearInput_Prescaler */ - uint32_t ClearInputFilter; /*!< TIM Clear Input filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -}TIM_ClearInputConfigTypeDef; + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClearInputConfigTypeDef; /** * @brief TIM Master configuration Structure definition * @note Advanced timers provide TRGO2 internal line which is redirected * to the ADC */ -typedef struct { +typedef struct +{ uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection - This parameter can be a value of @ref TIM_Master_Mode_Selection */ + This parameter can be a value of @ref TIM_Master_Mode_Selection */ uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection - This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ + This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ uint32_t MasterSlaveMode; /*!< Master/slave mode selection - This parameter can be a value of @ref TIM_Master_Slave_Mode */ -}TIM_MasterConfigTypeDef; + This parameter can be a value of @ref TIM_Master_Slave_Mode */ +} TIM_MasterConfigTypeDef; /** * @brief TIM Slave configuration Structure definition */ -typedef struct { - uint32_t SlaveMode; /*!< Slave mode selection - This parameter can be a value of @ref TIM_Slave_Mode */ +typedef struct +{ + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ uint32_t InputTrigger; /*!< Input Trigger source - This parameter can be a value of @ref TIM_Trigger_Selection */ + This parameter can be a value of @ref TIM_Trigger_Selection */ uint32_t TriggerPolarity; /*!< Input Trigger polarity - This parameter can be a value of @ref TIM_Trigger_Polarity */ + This parameter can be a value of @ref TIM_Trigger_Polarity */ uint32_t TriggerPrescaler; /*!< Input trigger prescaler - This parameter can be a value of @ref TIM_Trigger_Prescaler */ + This parameter can be a value of @ref TIM_Trigger_Prescaler */ uint32_t TriggerFilter; /*!< Input trigger filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -}TIM_SlaveConfigTypeDef; +} TIM_SlaveConfigTypeDef; /** * @brief TIM Break input(s) and Dead time configuration Structure definition @@ -279,28 +279,28 @@ typedef struct { */ typedef struct { - uint32_t OffStateRunMode; /*!< TIM off state in run mode - This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode - This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - uint32_t LockLevel; /*!< TIM Lock level - This parameter can be a value of @ref TIM_Lock_level */ - uint32_t DeadTime; /*!< TIM dead Time - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - uint32_t BreakState; /*!< TIM Break State - This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - uint32_t BreakPolarity; /*!< TIM Break input polarity - This parameter can be a value of @ref TIM_Break_Polarity */ - uint32_t BreakFilter; /*!< Specifies the break input filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t Break2State; /*!< TIM Break2 State - This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ - uint32_t Break2Polarity; /*!< TIM Break2 input polarity - This parameter can be a value of @ref TIM_Break2_Polarity */ - uint32_t Break2Filter; /*!< TIM break2 input filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + uint32_t OffStateRunMode; /*!< TIM off state in run mode + This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode + This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + uint32_t LockLevel; /*!< TIM Lock level + This parameter can be a value of @ref TIM_Lock_level */ + uint32_t DeadTime; /*!< TIM dead Time + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint32_t BreakState; /*!< TIM Break State + This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + uint32_t BreakPolarity; /*!< TIM Break input polarity + This parameter can be a value of @ref TIM_Break_Polarity */ + uint32_t BreakFilter; /*!< Specifies the break input filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t Break2State; /*!< TIM Break2 State + This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ + uint32_t Break2Polarity; /*!< TIM Break2 input polarity + This parameter can be a value of @ref TIM_Break2_Polarity */ + uint32_t Break2Filter; /*!< TIM break2 input filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ } TIM_BreakDeadTimeConfigTypeDef; /** @@ -308,40 +308,107 @@ typedef struct */ typedef enum { - HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ - HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ -}HAL_TIM_StateTypeDef; + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +} HAL_TIM_StateTypeDef; /** * @brief HAL Active channel structures definition */ typedef enum { - HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ - HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ - HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ - HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ - HAL_TIM_ACTIVE_CHANNEL_5 = 0x10, /*!< The active channel is 5 */ - HAL_TIM_ACTIVE_CHANNEL_6 = 0x20, /*!< The active channel is 6 */ - HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ -}HAL_TIM_ActiveChannel; + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ + HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +} HAL_TIM_ActiveChannel; /** * @brief TIM Time Base Handle Structure definition */ -typedef struct +typedef struct __TIM_HandleTypeDef { - TIM_TypeDef *Instance; /*!< Register base address */ - TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ - DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array - This array is accessed by a @ref DMA_Handle_index */ - HAL_LockTypeDef Lock; /*!< Locking object */ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ -}TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ + void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ + void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ + void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ + void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ + void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ + void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ + void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ + void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ + void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ + void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ + void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ + void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ + void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ + void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ + void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ + void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ + void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ + void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ + void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ + void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ + void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ + void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U, /*!< TIM Base MspInit Callback ID */ + HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U, /*!< TIM Base MspDeInit Callback ID */ + HAL_TIM_IC_MSPINIT_CB_ID = 0x02U, /*!< TIM IC MspInit Callback ID */ + HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U, /*!< TIM IC MspDeInit Callback ID */ + HAL_TIM_OC_MSPINIT_CB_ID = 0x04U, /*!< TIM OC MspInit Callback ID */ + HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U, /*!< TIM OC MspDeInit Callback ID */ + HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U, /*!< TIM PWM MspInit Callback ID */ + HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U, /*!< TIM PWM MspDeInit Callback ID */ + HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U, /*!< TIM One Pulse MspInit Callback ID */ + HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U, /*!< TIM One Pulse MspDeInit Callback ID */ + HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU, /*!< TIM Encoder MspInit Callback ID */ + HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU, /*!< TIM Encoder MspDeInit Callback ID */ + HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU, /*!< TIM Hall Sensor MspDeInit Callback ID */ + HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU, /*!< TIM Hall Sensor MspDeInit Callback ID */ + + HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU, /*!< TIM Period Elapsed Callback ID */ + HAL_TIM_TRIGGER_CB_ID = 0x0FU, /*!< TIM Trigger Callback ID */ + HAL_TIM_IC_CAPTURE_CB_ID = 0x10U, /*!< TIM Input Capture Callback ID */ + HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x11U, /*!< TIM Output Compare Delay Elapsed Callback ID */ + HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x12U, /*!< TIM PWM Pulse Finished Callback ID */ + HAL_TIM_ERROR_CB_ID = 0x13U, /*!< TIM Error Callback ID */ + HAL_TIM_COMMUTATION_CB_ID = 0x14U, /*!< TIM Commutation Callback ID */ + HAL_TIM_BREAK_CB_ID = 0x15U, /*!< TIM Break Callback ID */ + HAL_TIM_BREAK2_CB_ID = 0x16U /*!< TIM Break2 Callback ID */ + +} HAL_TIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} @@ -356,9 +423,9 @@ typedef struct /** @defgroup TIM_ClearInput_Source TIM Clear Input Source * @{ */ -#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) -#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002) -#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) +#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ +#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ +#define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /*!< OCREF_CLR is connected to OCREF_CLR_INT */ /** * @} */ @@ -366,37 +433,37 @@ typedef struct /** @defgroup TIM_DMA_Base_address TIM DMA Base Address * @{ */ -#define TIM_DMABASE_CR1 (0x00000000) -#define TIM_DMABASE_CR2 (0x00000001) -#define TIM_DMABASE_SMCR (0x00000002) -#define TIM_DMABASE_DIER (0x00000003) -#define TIM_DMABASE_SR (0x00000004) -#define TIM_DMABASE_EGR (0x00000005) -#define TIM_DMABASE_CCMR1 (0x00000006) -#define TIM_DMABASE_CCMR2 (0x00000007) -#define TIM_DMABASE_CCER (0x00000008) -#define TIM_DMABASE_CNT (0x00000009) -#define TIM_DMABASE_PSC (0x0000000A) -#define TIM_DMABASE_ARR (0x0000000B) -#define TIM_DMABASE_RCR (0x0000000C) -#define TIM_DMABASE_CCR1 (0x0000000D) -#define TIM_DMABASE_CCR2 (0x0000000E) -#define TIM_DMABASE_CCR3 (0x0000000F) -#define TIM_DMABASE_CCR4 (0x00000010) -#define TIM_DMABASE_BDTR (0x00000011) -#define TIM_DMABASE_DCR (0x00000012) -#define TIM_DMABASE_DMAR (0x00000013) -#define TIM_DMABASE_OR1 (0x00000014) -#define TIM_DMABASE_CCMR3 (0x00000015) -#define TIM_DMABASE_CCR5 (0x00000016) -#define TIM_DMABASE_CCR6 (0x00000017) -#define TIM_DMABASE_OR2 (0x00000018) -#define TIM_DMABASE_OR3 (0x00000019) +#define TIM_DMABASE_CR1 0x00000000U +#define TIM_DMABASE_CR2 0x00000001U +#define TIM_DMABASE_SMCR 0x00000002U +#define TIM_DMABASE_DIER 0x00000003U +#define TIM_DMABASE_SR 0x00000004U +#define TIM_DMABASE_EGR 0x00000005U +#define TIM_DMABASE_CCMR1 0x00000006U +#define TIM_DMABASE_CCMR2 0x00000007U +#define TIM_DMABASE_CCER 0x00000008U +#define TIM_DMABASE_CNT 0x00000009U +#define TIM_DMABASE_PSC 0x0000000AU +#define TIM_DMABASE_ARR 0x0000000BU +#define TIM_DMABASE_RCR 0x0000000CU +#define TIM_DMABASE_CCR1 0x0000000DU +#define TIM_DMABASE_CCR2 0x0000000EU +#define TIM_DMABASE_CCR3 0x0000000FU +#define TIM_DMABASE_CCR4 0x00000010U +#define TIM_DMABASE_BDTR 0x00000011U +#define TIM_DMABASE_DCR 0x00000012U +#define TIM_DMABASE_DMAR 0x00000013U +#define TIM_DMABASE_OR1 0x00000014U +#define TIM_DMABASE_CCMR3 0x00000015U +#define TIM_DMABASE_CCR5 0x00000016U +#define TIM_DMABASE_CCR6 0x00000017U +#define TIM_DMABASE_OR2 0x00000018U +#define TIM_DMABASE_OR3 0x00000019U /** * @} */ -/** @defgroup TIM_Event_Source TIM Extended Event Source +/** @defgroup TIM_Event_Source TIM Event Source * @{ */ #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ @@ -415,8 +482,8 @@ typedef struct /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity * @{ */ -#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ /** * @} @@ -425,8 +492,8 @@ typedef struct /** @defgroup TIM_ETR_Polarity TIM ETR Polarity * @{ */ -#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ -#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ /** * @} */ @@ -434,10 +501,10 @@ typedef struct /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler * @{ */ -#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ -#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ -#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ -#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ +#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ /** * @} */ @@ -445,11 +512,11 @@ typedef struct /** @defgroup TIM_Counter_Mode TIM Counter Mode * @{ */ -#define TIM_COUNTERMODE_UP ((uint32_t)0x0000) -#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR -#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 -#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 -#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS +#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ /** * @} */ @@ -457,45 +524,46 @@ typedef struct /** @defgroup TIM_ClockDivision TIM Clock Division * @{ */ -#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) -#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) -#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ /** * @} */ -/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload +/** @defgroup TIM_Output_Compare_State TIM Output Compare State * @{ */ -#define TIM_AUTORELOAD_PRELOAD_DISABLE ((uint32_t)0x0000) /*!< TIMx_ARR register is not buffered */ -#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */ +#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ +#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ /** * @} */ -/** @defgroup TIM_Output_Compare_State TIM Output Compare State +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload * @{ */ -#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) -#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) +#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ + /** * @} */ -/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State +/** @defgroup TIM_Output_Fast_State TIM Output Fast State * @{ */ -#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000) -#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) +#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ +#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ /** * @} */ -/** @defgroup TIM_Output_Fast_State TIM Output Fast State +/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State * @{ */ -#define TIM_OCFAST_DISABLE ((uint32_t)0x0000) -#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) +#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ +#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ /** * @} */ @@ -503,8 +571,8 @@ typedef struct /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity * @{ */ -#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) -#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) +#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ +#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ /** * @} */ @@ -512,8 +580,8 @@ typedef struct /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity * @{ */ -#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000) -#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) +#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ +#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ /** * @} */ @@ -521,8 +589,8 @@ typedef struct /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State * @{ */ -#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) -#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000) +#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ +#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ /** * @} */ @@ -530,8 +598,8 @@ typedef struct /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State * @{ */ -#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) -#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000) +#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ +#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ /** * @} */ @@ -539,9 +607,9 @@ typedef struct /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity * @{ */ -#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING -#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING -#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ /** * @} */ @@ -549,11 +617,11 @@ typedef struct /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection * @{ */ -#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively */ -#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ /** * @} */ @@ -561,10 +629,10 @@ typedef struct /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler * @{ */ -#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ -#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ -#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ -#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ +#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ /** * @} */ @@ -572,8 +640,8 @@ typedef struct /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode * @{ */ -#define TIM_OPMODE_SINGLE (TIM_CR1_OPM) -#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) +#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ /** * @} */ @@ -581,9 +649,9 @@ typedef struct /** @defgroup TIM_Encoder_Mode TIM Encoder Mode * @{ */ -#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) -#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) -#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) +#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ /** * @} */ @@ -591,14 +659,14 @@ typedef struct /** @defgroup TIM_Interrupt_definition TIM interrupt Definition * @{ */ -#define TIM_IT_UPDATE (TIM_DIER_UIE) -#define TIM_IT_CC1 (TIM_DIER_CC1IE) -#define TIM_IT_CC2 (TIM_DIER_CC2IE) -#define TIM_IT_CC3 (TIM_DIER_CC3IE) -#define TIM_IT_CC4 (TIM_DIER_CC4IE) -#define TIM_IT_COM (TIM_DIER_COMIE) -#define TIM_IT_TRIGGER (TIM_DIER_TIE) -#define TIM_IT_BREAK (TIM_DIER_BIE) +#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ +#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ +#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ +#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ +#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ +#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ +#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ +#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ /** * @} */ @@ -606,8 +674,8 @@ typedef struct /** @defgroup TIM_Commutation_Source TIM Commutation Source * @{ */ -#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) -#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000) +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ +#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ /** * @} */ @@ -615,13 +683,13 @@ typedef struct /** @defgroup TIM_DMA_sources TIM DMA Sources * @{ */ -#define TIM_DMA_UPDATE (TIM_DIER_UDE) -#define TIM_DMA_CC1 (TIM_DIER_CC1DE) -#define TIM_DMA_CC2 (TIM_DIER_CC2DE) -#define TIM_DMA_CC3 (TIM_DIER_CC3DE) -#define TIM_DMA_CC4 (TIM_DIER_CC4DE) -#define TIM_DMA_COM (TIM_DIER_COMDE) -#define TIM_DMA_TRIGGER (TIM_DIER_TDE) +#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ +#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ +#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ +#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ +#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ +#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ +#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ /** * @} */ @@ -629,22 +697,22 @@ typedef struct /** @defgroup TIM_Flag_definition TIM Flag Definition * @{ */ -#define TIM_FLAG_UPDATE (TIM_SR_UIF) -#define TIM_FLAG_CC1 (TIM_SR_CC1IF) -#define TIM_FLAG_CC2 (TIM_SR_CC2IF) -#define TIM_FLAG_CC3 (TIM_SR_CC3IF) -#define TIM_FLAG_CC4 (TIM_SR_CC4IF) -#define TIM_FLAG_CC5 (TIM_SR_CC5IF) -#define TIM_FLAG_CC6 (TIM_SR_CC6IF) -#define TIM_FLAG_COM (TIM_SR_COMIF) -#define TIM_FLAG_TRIGGER (TIM_SR_TIF) -#define TIM_FLAG_BREAK (TIM_SR_BIF) -#define TIM_FLAG_BREAK2 (TIM_SR_B2IF) -#define TIM_FLAG_SYSTEM_BREAK (TIM_SR_SBIF) -#define TIM_FLAG_CC1OF (TIM_SR_CC1OF) -#define TIM_FLAG_CC2OF (TIM_SR_CC2OF) -#define TIM_FLAG_CC3OF (TIM_SR_CC3OF) -#define TIM_FLAG_CC4OF (TIM_SR_CC4OF) +#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ +#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ +#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ +#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ +#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ +#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ +#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ +#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ +#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ +#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ +#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ +#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ /** * @} */ @@ -652,13 +720,13 @@ typedef struct /** @defgroup TIM_Channel TIM Channel * @{ */ -#define TIM_CHANNEL_1 ((uint32_t)0x0000) -#define TIM_CHANNEL_2 ((uint32_t)0x0004) -#define TIM_CHANNEL_3 ((uint32_t)0x0008) -#define TIM_CHANNEL_4 ((uint32_t)0x000C) -#define TIM_CHANNEL_5 ((uint32_t)0x0010) -#define TIM_CHANNEL_6 ((uint32_t)0x0014) -#define TIM_CHANNEL_ALL ((uint32_t)0x003C) +#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ +#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ +#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ +#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ +#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ +#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ +#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ /** * @} */ @@ -666,16 +734,16 @@ typedef struct /** @defgroup TIM_Clock_Source TIM Clock Source * @{ */ -#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) -#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) -#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) -#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) -#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) -#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) -#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ +#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ +#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ +#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ /** * @} */ @@ -683,9 +751,9 @@ typedef struct /** @defgroup TIM_Clock_Polarity TIM Clock Polarity * @{ */ -#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ /** @@ -695,10 +763,10 @@ typedef struct /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler * @{ */ -#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ -#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ -#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ /** * @} */ @@ -706,8 +774,8 @@ typedef struct /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity * @{ */ -#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ -#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ /** * @} */ @@ -715,10 +783,10 @@ typedef struct /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler * @{ */ -#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ /** * @} */ @@ -726,8 +794,8 @@ typedef struct /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state * @{ */ -#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) -#define TIM_OSSR_DISABLE ((uint32_t)0x0000) +#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ /** * @} */ @@ -735,18 +803,18 @@ typedef struct /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state * @{ */ -#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) -#define TIM_OSSI_DISABLE ((uint32_t)0x0000) +#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ /** * @} */ /** @defgroup TIM_Lock_level TIM Lock level * @{ */ -#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000) -#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) -#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) -#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) +#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ +#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ /** * @} */ @@ -754,8 +822,8 @@ typedef struct /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable * @{ */ -#define TIM_BREAK_ENABLE (TIM_BDTR_BKE) -#define TIM_BREAK_DISABLE ((uint32_t)0x0000) +#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ +#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ /** * @} */ @@ -763,8 +831,8 @@ typedef struct /** @defgroup TIM_Break_Polarity TIM Break Input Polarity * @{ */ -#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000) -#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) +#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ +#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ /** * @} */ @@ -772,8 +840,8 @@ typedef struct /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable * @{ */ -#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000) -#define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E) +#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ +#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ /** * @} */ @@ -781,8 +849,8 @@ typedef struct /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity * @{ */ -#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000) -#define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P) +#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ +#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ /** * @} */ @@ -790,8 +858,9 @@ typedef struct /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable * @{ */ -#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) -#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) +#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event + (if none of the break inputs BRK and BRK2 is active) */ /** * @} */ @@ -799,10 +868,10 @@ typedef struct /** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 * @{ */ -#define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ -#define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ -#define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ -#define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ +#define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ +#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ +#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ +#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ /** * @} */ @@ -810,14 +879,14 @@ typedef struct /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection * @{ */ -#define TIM_TRGO_RESET ((uint32_t)0x0000) -#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) -#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) -#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) -#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) -#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) +#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ +#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ +#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ +#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ /** * @} */ @@ -825,22 +894,22 @@ typedef struct /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) * @{ */ -#define TIM_TRGO2_RESET ((uint32_t)0x00000000) -#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0)) -#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2)) -#define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3)) -#define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)) -#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) +#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ /** * @} */ @@ -848,8 +917,8 @@ typedef struct /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode * @{ */ -#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) -#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) +#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ +#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ /** * @} */ @@ -857,12 +926,12 @@ typedef struct /** @defgroup TIM_Slave_Mode TIM Slave mode * @{ */ -#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) -#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2)) -#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)) -#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)) -#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)) -#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3)) +#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ +#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ +#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ +#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ +#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ +#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ /** * @} */ @@ -870,21 +939,20 @@ typedef struct /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes * @{ */ -#define TIM_OCMODE_TIMING ((uint32_t)0x0000) -#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1) -#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) -#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2) - -#define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3) -#define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) -#define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) -#define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) -#define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) +#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ +#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ +#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ +#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ +#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ +#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ +#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ +#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ +#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ /** * @} */ @@ -892,15 +960,15 @@ typedef struct /** @defgroup TIM_Trigger_Selection TIM Trigger Selection * @{ */ -#define TIM_TS_ITR0 ((uint32_t)0x0000) -#define TIM_TS_ITR1 ((uint32_t)0x0010) -#define TIM_TS_ITR2 ((uint32_t)0x0020) -#define TIM_TS_ITR3 ((uint32_t)0x0030) -#define TIM_TS_TI1F_ED ((uint32_t)0x0040) -#define TIM_TS_TI1FP1 ((uint32_t)0x0050) -#define TIM_TS_TI2FP2 ((uint32_t)0x0060) -#define TIM_TS_ETRF ((uint32_t)0x0070) -#define TIM_TS_NONE ((uint32_t)0xFFFF) +#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ +#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ +#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ /** * @} */ @@ -908,8 +976,8 @@ typedef struct /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity * @{ */ -#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ @@ -920,10 +988,10 @@ typedef struct /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler * @{ */ -#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ -#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ -#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ /** * @} */ @@ -931,8 +999,8 @@ typedef struct /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection * @{ */ -#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) -#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) +#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ +#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ /** * @} */ @@ -940,24 +1008,24 @@ typedef struct /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length * @{ */ -#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000) -#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100) -#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200) -#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300) -#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400) -#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500) -#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600) -#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700) -#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800) -#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900) -#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00) -#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00) -#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00) -#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00) -#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00) -#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00) -#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000) -#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100) +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ /** * @} */ @@ -965,13 +1033,13 @@ typedef struct /** @defgroup DMA_Handle_index TIM DMA Handle Index * @{ */ -#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ -#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ -#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ -#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ -#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ -#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */ -#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ /** * @} */ @@ -979,10 +1047,10 @@ typedef struct /** @defgroup Channel_CC_State TIM Capture/Compare Channel State * @{ */ -#define TIM_CCx_ENABLE ((uint32_t)0x0001) -#define TIM_CCx_DISABLE ((uint32_t)0x0000) -#define TIM_CCxN_ENABLE ((uint32_t)0x0004) -#define TIM_CCxN_DISABLE ((uint32_t)0x0000) +#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ +#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ +#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ +#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ /** * @} */ @@ -990,10 +1058,10 @@ typedef struct /** @defgroup TIM_Break_System TIM Break System * @{ */ -#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */ -#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ -#define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 */ -#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17 */ +#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */ +#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ +#define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 */ +#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */ /** * @} */ @@ -1012,13 +1080,33 @@ typedef struct * @param __HANDLE__ TIM handle. * @retval None */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @brief Enable the TIM peripheral. * @param __HANDLE__ TIM handle * @retval None - */ + */ #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) /** @@ -1035,9 +1123,9 @@ typedef struct */ #define __HAL_TIM_DISABLE(__HANDLE__) \ do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ { \ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ } \ @@ -1052,9 +1140,9 @@ typedef struct */ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ { \ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ } \ @@ -1085,7 +1173,6 @@ typedef struct */ #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) - /** @brief Disable the specified TIM interrupt. * @param __HANDLE__ specifies the TIM Handle. * @param __INTERRUPT__ specifies the TIM interrupt source to disable. @@ -1222,7 +1309,6 @@ mode. */ #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) - /** * @brief Set the TIM Prescaler on runtime. * @param __HANDLE__ TIM handle. @@ -1278,10 +1364,10 @@ mode. * @retval None */ #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ - do{ \ - (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ - (__HANDLE__)->Instance->CR1 |= (__CKD__); \ - (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + do{ \ + (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ } while(0) /** @@ -1335,9 +1421,9 @@ mode. */ #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ - (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) /** * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. @@ -1427,18 +1513,18 @@ mode. /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. * @param __HANDLE__ TIM handle. - * @note When the USR bit of the TIMx_CR1 register is set, only counter + * @note When the URS bit of the TIMx_CR1 register is set, only counter * overflow/underflow generates an update interrupt or DMA request (if * enabled) * @retval None */ #define __HAL_TIM_URS_ENABLE(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS)) + ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) /** * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. * @param __HANDLE__ TIM handle. - * @note When the USR bit of the TIMx_CR1 register is reset, any of the + * @note When the URS bit of the TIMx_CR1 register is reset, any of the * following events generate an update interrupt or DMA request (if * enabled): * _ Counter overflow underflow @@ -1447,7 +1533,7 @@ mode. * @retval None */ #define __HAL_TIM_URS_DISABLE(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) + ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) /** * @brief Set the TIM Capture x input polarity on runtime. @@ -1492,7 +1578,6 @@ mode. /** @defgroup TIM_Private_Macros TIM Private Macros * @{ */ - #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) @@ -1522,10 +1607,8 @@ mode. ((__BASE__) == TIM_DMABASE_OR2) || \ ((__BASE__) == TIM_DMABASE_OR3)) - #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) - #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ @@ -1613,7 +1696,7 @@ mode. ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) -#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) +#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) @@ -1623,8 +1706,7 @@ mode. ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) -#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) - +#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ ((__STATE__) == TIM_OSSR_DISABLE)) @@ -1637,7 +1719,7 @@ mode. ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ ((__LEVEL__) == TIM_LOCKLEVEL_3)) -#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xF) +#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ @@ -1655,7 +1737,7 @@ mode. #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) -#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFF) == 0x00000000)) +#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ ((__SOURCE__) == TIM_TRGO_ENABLE) || \ @@ -1695,7 +1777,7 @@ mode. ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ - ((__MODE__) == TIM_OCMODE_PWM2) || \ + ((__MODE__) == TIM_OCMODE_PWM2) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ @@ -1725,7 +1807,6 @@ mode. ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_NONE)) - #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ @@ -1737,7 +1818,7 @@ mode. ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) -#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) +#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) @@ -1761,20 +1842,23 @@ mode. ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) -#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) +#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) -#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFF) +#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) -#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ - ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ - ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR) || \ +#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR) || \ ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) +#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__HANDLE__) ((((READ_REG((__HANDLE__)->Instance->SMCR)&TIM_SMCR_SMS) == TIM_SLAVEMODE_TRIGGER) || \ + ((READ_REG((__HANDLE__)->Instance->SMCR)&TIM_SMCR_SMS) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) ? 1UL : 0UL) + #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ - ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ @@ -1784,9 +1868,9 @@ mode. #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\ - ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12)))) + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ @@ -1808,9 +1892,9 @@ mode. */ /** @addtogroup TIM_Exported_Functions_Group1 Time Base functions - * @brief Time Base functions - * @{ - */ + * @brief Time Base functions + * @{ + */ /* Time Base functions ********************************************************/ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); @@ -1830,9 +1914,9 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); */ /** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions - * @brief Time Output Compare functions - * @{ - */ + * @brief Time Output Compare functions + * @{ + */ /* Timer Output Compare functions *********************************************/ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); @@ -1852,9 +1936,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) */ /** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions - * @brief Time PWM functions - * @{ - */ + * @brief Time PWM functions + * @{ + */ /* Timer PWM functions ********************************************************/ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); @@ -1874,9 +1958,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel */ /** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions - * @brief Time Input Capture functions - * @{ - */ + * @brief Time Input Capture functions + * @{ + */ /* Timer Input Capture functions **********************************************/ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); @@ -1896,9 +1980,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) */ /** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions - * @brief Time One Pulse functions - * @{ - */ + * @brief Time One Pulse functions + * @{ + */ /* Timer One Pulse functions **************************************************/ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); @@ -1915,15 +1999,15 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out */ /** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions - * @brief Time Encoder functions - * @{ - */ + * @brief Time Encoder functions + * @{ + */ /* Timer Encoder functions ****************************************************/ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); - /* Blocking mode: Polling */ +/* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ @@ -1937,7 +2021,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha */ /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief IRQ handler management + * @brief IRQ handler management * @{ */ /* Interrupt Handler functions ***********************************************/ @@ -1947,24 +2031,24 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); */ /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions - * @brief Peripheral Control functions + * @brief Peripheral Control functions * @{ */ /* Control functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ - uint32_t *BurstBuffer, uint32_t BurstLength); + uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); @@ -1973,7 +2057,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); */ /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions + * @brief TIM Callbacks functions * @{ */ /* Callback in non blocking modes (Interrupt and DMA) *************************/ @@ -1983,14 +2067,21 @@ void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /** * @} */ /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions - * @brief Peripheral State functions - * @{ - */ + * @brief Peripheral State functions + * @{ + */ /* Peripheral State functions ************************************************/ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); @@ -2014,13 +2105,18 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); void TIM_DMAError(DMA_HandleTypeDef *hdma); void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); -void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +void TIM_ResetCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /** * @} */ @@ -2038,6 +2134,6 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat } #endif -#endif /* __STM32L4xx_HAL_TIM_H */ +#endif /* STM32L4xx_HAL_TIM_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h index 02ef6ad6ff..62e507e946 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h @@ -34,11 +34,11 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_TIM_EX_H -#define __STM32L4xx_HAL_TIM_EX_H +#ifndef STM32L4xx_HAL_TIM_EX_H +#define STM32L4xx_HAL_TIM_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -63,7 +63,6 @@ typedef struct { - uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ @@ -80,7 +79,8 @@ typedef struct /** * @brief TIM Break/Break2 input configuration */ -typedef struct { +typedef struct +{ uint32_t Source; /*!< Specifies the source of the timer break input. This parameter can be a value of @ref TIMEx_Break_Input_Source */ uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. @@ -88,7 +88,8 @@ typedef struct { uint32_t Polarity; /*!< Specifies the break input source polarity. This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity Not relevant when analog watchdog output of the DFSDM1 used as break input source */ -} TIMEx_BreakInputConfigTypeDef; +} +TIMEx_BreakInputConfigTypeDef; /** * @} @@ -103,131 +104,98 @@ typedef struct { /** @defgroup TIMEx_Remap TIM Extended Remapping * @{ */ -#define TIM_TIM1_ETR_ADC1_NONE ((uint32_t)(0x00000000)) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ -#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */ -#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1) /* !< TIM1_ETR is connected to ADC1 AWD2 */ +#define TIM_TIM1_ETR_ADC1_NONE 0x00000000U /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ +#define TIM_TIM1_ETR_ADC1_AWD1 TIM1_OR1_ETR_ADC1_RMP_0 /* !< TIM1_ETR is connected to ADC1 AWD1 */ +#define TIM_TIM1_ETR_ADC1_AWD2 TIM1_OR1_ETR_ADC1_RMP_1 /* !< TIM1_ETR is connected to ADC1 AWD2 */ #define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) -#define TIM_TIM1_ETR_ADC3_NONE ((uint32_t)(0x00000000)) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ -#define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD1 */ -#define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1) /* !< TIM1_ETR is connected to ADC3 AWD2 */ +#if defined (ADC3) +#define TIM_TIM1_ETR_ADC3_NONE 0x00000000U /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ +#define TIM_TIM1_ETR_ADC3_AWD1 TIM1_OR1_ETR_ADC3_RMP_0 /* !< TIM1_ETR is connected to ADC3 AWD1 */ +#define TIM_TIM1_ETR_ADC3_AWD2 TIM1_OR1_ETR_ADC3_RMP_1 /* !< TIM1_ETR is connected to ADC3 AWD2 */ #define TIM_TIM1_ETR_ADC3_AWD3 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD3 */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ -#define TIM_TIM1_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM1 TI1 is connected to GPIO */ -#define TIM_TIM1_TI1_COMP1 (TIM1_OR1_TI1_RMP) /* !< TIM1 TI1 is connected to COMP1 */ -#define TIM_TIM1_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM1_ETR is connected to GPIO */ -#define TIM_TIM1_ETR_COMP1 (TIM1_OR2_ETRSEL_0) /* !< TIM1_ETR is connected to COMP1 output */ -#define TIM_TIM1_ETR_COMP2 (TIM1_OR2_ETRSEL_1) /* !< TIM1_ETR is connected to COMP2 output */ - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_TIM2_ITR1_TIM8_TRGO ((uint32_t)(0x00000000)) /* !< TIM2_ITR1 is connected to TIM8_TRGO */ -#define TIM_TIM2_ITR1_OTG_FS_SOF (TIM2_OR1_ITR1_RMP) /* !< TIM2_ITR1 is connected to OTG_FS SOF */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define TIM_TIM2_ITR1_NONE ((uint32_t)(0x00000000)) /* !< No internal trigger on TIM2_ITR1 */ -#define TIM_TIM2_ITR1_USB_SOF (TIM2_OR1_ITR1_RMP) /* !< TIM2_ITR1 is connected to USB SOF */ -#endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */ - /* STM32L451xx || STM32L452xx || STM32L462xx */ -#define TIM_TIM2_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM2_ETR is connected to GPIO */ -#define TIM_TIM2_ETR_LSE (TIM2_OR1_ETR1_RMP) /* !< TIM2_ETR is connected to LSE */ -#define TIM_TIM2_ETR_COMP1 (TIM2_OR2_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 output */ -#define TIM_TIM2_ETR_COMP2 (TIM2_OR2_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 output */ -#define TIM_TIM2_TI4_GPIO ((uint32_t)(0x00000000)) /* !< TIM2 TI4 is connected to GPIO */ -#define TIM_TIM2_TI4_COMP1 (TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to COMP1 output */ -#define TIM_TIM2_TI4_COMP2 (TIM2_OR1_TI4_RMP_1) /* !< TIM2 TI4 is connected to COMP2 output */ +#endif /* ADC3 */ +#define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1 TI1 is connected to GPIO */ +#define TIM_TIM1_TI1_COMP1 TIM1_OR1_TI1_RMP /* !< TIM1 TI1 is connected to COMP1 */ +#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */ +#define TIM_TIM1_ETR_COMP1 TIM1_OR2_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */ +#define TIM_TIM1_ETR_COMP2 TIM1_OR2_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */ + +#if defined (USB_OTG_FS) +#define TIM_TIM2_ITR1_TIM8_TRGO 0x00000000U /* !< TIM2_ITR1 is connected to TIM8_TRGO */ +#define TIM_TIM2_ITR1_OTG_FS_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to OTG_FS SOF */ +#else +#if defined(STM32L471xx) +#define TIM_TIM2_ITR1_TIM8_TRGO 0x00000000U /* !< TIM2_ITR1 is connected to TIM8_TRGO */ +#define TIM_TIM2_ITR1_NONE TIM2_OR1_ITR1_RMP /* !< No internal trigger on TIM2_ITR1 */ +#else +#define TIM_TIM2_ITR1_NONE 0x00000000U /* !< No internal trigger on TIM2_ITR1 */ +#define TIM_TIM2_ITR1_USB_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to USB SOF */ +#endif /* STM32L471xx */ +#endif /* USB_OTG_FS */ +#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */ +#define TIM_TIM2_ETR_LSE TIM2_OR1_ETR1_RMP /* !< TIM2_ETR is connected to LSE */ +#define TIM_TIM2_ETR_COMP1 TIM2_OR2_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */ +#define TIM_TIM2_ETR_COMP2 TIM2_OR2_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */ +#define TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2 TI4 is connected to GPIO */ +#define TIM_TIM2_TI4_COMP1 TIM2_OR1_TI4_RMP_0 /* !< TIM2 TI4 is connected to COMP1 output */ +#define TIM_TIM2_TI4_COMP2 TIM2_OR1_TI4_RMP_1 /* !< TIM2 TI4 is connected to COMP2 output */ #define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_TIM3_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM3 TI1 is connected to GPIO */ -#define TIM_TIM3_TI1_COMP1 (TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to COMP1 output */ -#define TIM_TIM3_TI1_COMP2 (TIM3_OR1_TI1_RMP_1) /* !< TIM3 TI1 is connected to COMP2 output */ +#if defined (TIM3) +#define TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3 TI1 is connected to GPIO */ +#define TIM_TIM3_TI1_COMP1 TIM3_OR1_TI1_RMP_0 /* !< TIM3 TI1 is connected to COMP1 output */ +#define TIM_TIM3_TI1_COMP2 TIM3_OR1_TI1_RMP_1 /* !< TIM3 TI1 is connected to COMP2 output */ #define TIM_TIM3_TI1_COMP1_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */ -#define TIM_TIM3_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM3_ETR is connected to GPIO */ -#define TIM_TIM3_ETR_COMP1 (TIM3_OR2_ETRSEL_0) /* !< TIM3_ETR is connected to COMP1 output */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) -#define TIM_TIM8_ETR_ADC2_NONE ((uint32_t)(0x00000000)) /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/ -#define TIM_TIM8_ETR_ADC2_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */ -#define TIM_TIM8_ETR_ADC2_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1) /* !< TIM8_ETR is connected to ADC2 AWD2 */ +#define TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */ +#define TIM_TIM3_ETR_COMP1 TIM3_OR2_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 output */ +#endif /* TIM3 */ + +#if defined (TIM8) +#if defined(ADC2) && defined(ADC3) +#define TIM_TIM8_ETR_ADC2_NONE 0x00000000U /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/ +#define TIM_TIM8_ETR_ADC2_AWD1 TIM8_OR1_ETR_ADC2_RMP_0 /* !< TIM8_ETR is connected to ADC2 AWD1 */ +#define TIM_TIM8_ETR_ADC2_AWD2 TIM8_OR1_ETR_ADC2_RMP_1 /* !< TIM8_ETR is connected to ADC2 AWD2 */ #define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */ -#define TIM_TIM8_ETR_ADC3_NONE ((uint32_t)(0x00000000)) /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/ -#define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD1 */ -#define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1) /* !< TIM8_ETR is connected to ADC3 AWD2 */ +#define TIM_TIM8_ETR_ADC3_NONE 0x00000000U /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/ +#define TIM_TIM8_ETR_ADC3_AWD1 TIM8_OR1_ETR_ADC3_RMP_0 /* !< TIM8_ETR is connected to ADC3 AWD1 */ +#define TIM_TIM8_ETR_ADC3_AWD2 TIM8_OR1_ETR_ADC3_RMP_1 /* !< TIM8_ETR is connected to ADC3 AWD2 */ #define TIM_TIM8_ETR_ADC3_AWD3 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD3 */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_TIM8_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM8 TI1 is connected to GPIO */ -#define TIM_TIM8_TI1_COMP2 (TIM8_OR1_TI1_RMP) /* !< TIM8 TI1 is connected to COMP1 */ -#define TIM_TIM8_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM8_ETR is connected to GPIO */ -#define TIM_TIM8_ETR_COMP1 (TIM8_OR2_ETRSEL_0) /* !< TIM8_ETR is connected to COMP1 output */ -#define TIM_TIM8_ETR_COMP2 (TIM8_OR2_ETRSEL_1) /* !< TIM8_ETR is connected to COMP2 output */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#define TIM_TIM15_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM15 TI1 is connected to GPIO */ -#define TIM_TIM15_TI1_LSE (TIM15_OR1_TI1_RMP) /* !< TIM15 TI1 is connected to LSE */ -#define TIM_TIM15_ENCODERMODE_NONE ((uint32_t)(0x00000000)) /* !< No redirection */ -#define TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0) /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1) /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#endif /* ADC2 && ADC3 */ + +#define TIM_TIM8_TI1_GPIO 0x00000000U /* !< TIM8 TI1 is connected to GPIO */ +#define TIM_TIM8_TI1_COMP2 TIM8_OR1_TI1_RMP /* !< TIM8 TI1 is connected to COMP1 */ +#define TIM_TIM8_ETR_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */ +#define TIM_TIM8_ETR_COMP1 TIM8_OR2_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 output */ +#define TIM_TIM8_ETR_COMP2 TIM8_OR2_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 output */ +#endif /* TIM8 */ + +#define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15 TI1 is connected to GPIO */ +#define TIM_TIM15_TI1_LSE TIM15_OR1_TI1_RMP /* !< TIM15 TI1 is connected to LSE */ +#define TIM_TIM15_ENCODERMODE_NONE 0x00000000U /* !< No redirection */ +#define TIM_TIM15_ENCODERMODE_TIM2 TIM15_OR1_ENCODER_MODE_0 /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ +#if defined (TIM3) +#define TIM_TIM15_ENCODERMODE_TIM3 TIM15_OR1_ENCODER_MODE_1 /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ +#endif /* TIM3 */ +#if defined (TIM4) #define TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* TIM4 */ -#define TIM_TIM16_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM16 TI1 is connected to GPIO */ -#define TIM_TIM16_TI1_LSI (TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to LSI */ -#define TIM_TIM16_TI1_LSE (TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to LSE */ +#define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16 TI1 is connected to GPIO */ +#define TIM_TIM16_TI1_LSI TIM16_OR1_TI1_RMP_0 /* !< TIM16 TI1 is connected to LSI */ +#define TIM_TIM16_TI1_LSE TIM16_OR1_TI1_RMP_1 /* !< TIM16 TI1 is connected to LSE */ #define TIM_TIM16_TI1_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to RTC wakeup interrupt */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) -#define TIM_TIM16_TI1_MSI (TIM16_OR1_TI1_RMP_2) /* !< TIM16 TI1 is connected to MSI */ +#if defined (TIM16_OR1_TI1_RMP_2) +#define TIM_TIM16_TI1_MSI TIM16_OR1_TI1_RMP_2 /* !< TIM16 TI1 is connected to MSI */ #define TIM_TIM16_TI1_HSE_32 (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to HSE div 32 */ #define TIM_TIM16_TI1_MCO (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to MCO */ -#endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */ - /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L496xx || STM32L4A6xx */ - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_TIM17_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM17 TI1 is connected to GPIO */ -#define TIM_TIM17_TI1_MSI (TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MSI */ -#define TIM_TIM17_TI1_HSE_32 (TIM17_OR1_TI1_RMP_1) /* !< TIM17 TI1 is connected to HSE div 32 */ +#endif /* TIM16_OR1_TI1_RMP_2 */ + +#if defined (TIM17) +#define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17 TI1 is connected to GPIO */ +#define TIM_TIM17_TI1_MSI TIM17_OR1_TI1_RMP_0 /* !< TIM17 TI1 is connected to MSI */ +#define TIM_TIM17_TI1_HSE_32 TIM17_OR1_TI1_RMP_1 /* !< TIM17 TI1 is connected to HSE div 32 */ #define TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MCO */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* TIM17 */ /** * @} */ @@ -235,8 +203,8 @@ typedef struct { /** @defgroup TIMEx_Break_Input TIM Extended Break input * @{ */ -#define TIM_BREAKINPUT_BRK ((uint32_t)(0x00000001)) /* !< Timer break input */ -#define TIM_BREAKINPUT_BRK2 ((uint32_t)(0x00000002)) /* !< Timer break2 input */ +#define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */ +#define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */ /** * @} */ @@ -244,18 +212,12 @@ typedef struct { /** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source * @{ */ -#define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)(0x00000001)) /* !< An external source (GPIO) is connected to the BKIN pin */ -#define TIM_BREAKINPUTSOURCE_COMP1 ((uint32_t)(0x00000002)) /* !< The COMP1 output is connected to the break input */ -#define TIM_BREAKINPUTSOURCE_COMP2 ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */ +#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */ +#if defined (DFSDM1_Channel0) +#define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ +#endif /* DFSDM1_Channel0 */ /** * @} */ @@ -263,8 +225,8 @@ typedef struct { /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling * @{ */ -#define TIM_BREAKINPUTSOURCE_DISABLE ((uint32_t)(0x00000000)) /* !< Break input source is disabled */ -#define TIM_BREAKINPUTSOURCE_ENABLE ((uint32_t)(0x00000001)) /* !< Break input source is enabled */ +#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */ +#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */ /** * @} */ @@ -272,8 +234,8 @@ typedef struct { /** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity * @{ */ -#define TIM_BREAKINPUTSOURCE_POLARITY_LOW ((uint32_t)(0x00000001)) /* !< Break input source is active low */ -#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH ((uint32_t)(0x00000000)) /* !< Break input source is active_high */ +#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */ +#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */ /** * @} */ @@ -302,10 +264,7 @@ typedef struct { #define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#if defined (DFSDM1_Channel0) #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ @@ -314,15 +273,14 @@ typedef struct { #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2)) -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* DFSDM1_Channel0 */ #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) #define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) + /** * @} */ @@ -338,13 +296,13 @@ typedef struct { * @{ */ /* Timer Hall Sensor functions **********************************************/ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); - /* Blocking mode: Polling */ +/* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); /* Non-Blocking mode: Interrupt */ @@ -420,12 +378,11 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); - /** * @} */ @@ -437,6 +394,7 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) /* Extended Callback **********************************************************/ void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); /** * @} */ @@ -458,12 +416,12 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); /* Private functions----------------------------------------------------------*/ /** @defgroup TIMEx_Private_Functions TIMEx Private Functions -* @{ -*/ + * @{ + */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); /** -* @} -*/ + * @} + */ /* End of private functions --------------------------------------------------*/ /** @@ -479,6 +437,6 @@ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); #endif -#endif /* __STM32L4xx_HAL_TIM_EX_H */ +#endif /* STM32L4xx_HAL_TIM_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tsc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tsc.h index 5faeea59e9..57b5ba877b 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tsc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tsc.h @@ -38,7 +38,7 @@ #define __STM32L4xx_HAL_TSC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -57,32 +57,32 @@ * @{ */ -/** - * @brief TSC state structure definition - */ +/** + * @brief TSC state structure definition + */ typedef enum { - HAL_TSC_STATE_RESET = 0x00, /*!< TSC registers have their reset value */ - HAL_TSC_STATE_READY = 0x01, /*!< TSC registers are initialized or acquisition is completed with success */ - HAL_TSC_STATE_BUSY = 0x02, /*!< TSC initialization or acquisition is on-going */ - HAL_TSC_STATE_ERROR = 0x03 /*!< Acquisition is completed with max count error */ + HAL_TSC_STATE_RESET = 0x00U, /*!< TSC registers have their reset value */ + HAL_TSC_STATE_READY = 0x01U, /*!< TSC registers are initialized or acquisition is completed with success */ + HAL_TSC_STATE_BUSY = 0x02U, /*!< TSC initialization or acquisition is on-going */ + HAL_TSC_STATE_ERROR = 0x03U /*!< Acquisition is completed with max count error */ } HAL_TSC_StateTypeDef; -/** - * @brief TSC group status structure definition - */ +/** + * @brief TSC group status structure definition + */ typedef enum { - TSC_GROUP_ONGOING = 0x00, /*!< Acquisition on group is on-going or not started */ - TSC_GROUP_COMPLETED = 0x01 /*!< Acquisition on group is completed with success (no max count error) */ + TSC_GROUP_ONGOING = 0x00U, /*!< Acquisition on group is on-going or not started */ + TSC_GROUP_COMPLETED = 0x01U /*!< Acquisition on group is completed with success (no max count error) */ } TSC_GroupStatusTypeDef; -/** - * @brief TSC init structure definition - */ +/** + * @brief TSC init structure definition + */ typedef struct { - uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length + uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length This parameter can be a value of @ref TSC_CTPulseHL_Config */ uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length This parameter can be a value of @ref TSC_CTPulseLL_Config */ @@ -109,9 +109,9 @@ typedef struct uint32_t SamplingIOs; /*!< Sampling IOs mask */ } TSC_InitTypeDef; -/** - * @brief TSC IOs configuration structure definition - */ +/** + * @brief TSC IOs configuration structure definition + */ typedef struct { uint32_t ChannelIOs; /*!< Channel IOs mask */ @@ -119,17 +119,72 @@ typedef struct uint32_t SamplingIOs; /*!< Sampling IOs mask */ } TSC_IOConfigTypeDef; -/** - * @brief TSC handle Structure definition - */ -typedef struct +/** + * @brief TSC handle Structure definition + */ +typedef struct __TSC_HandleTypeDef { - TSC_TypeDef *Instance; /*!< Register base address */ - TSC_InitTypeDef Init; /*!< Initialization parameters */ - __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */ - HAL_LockTypeDef Lock; /*!< Lock feature */ + TSC_TypeDef *Instance; /*!< Register base address */ + TSC_InitTypeDef Init; /*!< Initialization parameters */ + __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */ + HAL_LockTypeDef Lock; /*!< Lock feature */ + __IO uint32_t ErrorCode; /*!< I2C Error code */ + +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) + void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Conversion complete callback */ + void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Error callback */ + + void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp Init callback */ + void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp DeInit callback */ + +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ } TSC_HandleTypeDef; +/** + * @brief TSC Group Index Structure definition + */ +typedef enum +{ + TSC_GROUP1_IDX = 0x00U, + TSC_GROUP2_IDX, + TSC_GROUP3_IDX, + TSC_GROUP4_IDX, +#if defined(TSC_IOCCR_G5_IO1) + TSC_GROUP5_IDX, +#endif +#if defined(TSC_IOCCR_G6_IO1) + TSC_GROUP6_IDX, +#endif +#if defined(TSC_IOCCR_G7_IO1) + TSC_GROUP7_IDX, +#endif +#if defined(TSC_IOCCR_G8_IO1) + TSC_GROUP8_IDX, +#endif + TSC_NB_OF_GROUPS +}TSC_GroupIndexTypeDef; + +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TSC Callback ID enumeration definition + */ +typedef enum +{ + HAL_TSC_CONV_COMPLETE_CB_ID = 0x00U, /*!< TSC Conversion completed callback ID */ + HAL_TSC_ERROR_CB_ID = 0x01U, /*!< TSC Error callback ID */ + + HAL_TSC_MSPINIT_CB_ID = 0x02U, /*!< TSC Msp Init callback ID */ + HAL_TSC_MSPDEINIT_CB_ID = 0x03U /*!< TSC Msp DeInit callback ID */ + +} HAL_TSC_CallbackIDTypeDef; + +/** + * @brief HAL TSC Callback pointer definition + */ +typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to an TSC callback function */ + +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ + /** * @} */ @@ -139,25 +194,37 @@ typedef struct * @{ */ +/** @defgroup TSC_Error_Code_definition TSC Error Code definition + * @brief TSC Error Code definition + * @{ + */ +#define HAL_TSC_ERROR_NONE 0x00000000U /*!< No error */ +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) +#define HAL_TSC_ERROR_INVALID_CALLBACK (0x00000001U) /*!< Invalid Callback error */ +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ +/** + * @} + */ + /** @defgroup TSC_CTPulseHL_Config CTPulse High Length * @{ */ -#define TSC_CTPH_1CYCLE ((uint32_t)((uint32_t) 0 << 28)) -#define TSC_CTPH_2CYCLES ((uint32_t)((uint32_t) 1 << 28)) -#define TSC_CTPH_3CYCLES ((uint32_t)((uint32_t) 2 << 28)) -#define TSC_CTPH_4CYCLES ((uint32_t)((uint32_t) 3 << 28)) -#define TSC_CTPH_5CYCLES ((uint32_t)((uint32_t) 4 << 28)) -#define TSC_CTPH_6CYCLES ((uint32_t)((uint32_t) 5 << 28)) -#define TSC_CTPH_7CYCLES ((uint32_t)((uint32_t) 6 << 28)) -#define TSC_CTPH_8CYCLES ((uint32_t)((uint32_t) 7 << 28)) -#define TSC_CTPH_9CYCLES ((uint32_t)((uint32_t) 8 << 28)) -#define TSC_CTPH_10CYCLES ((uint32_t)((uint32_t) 9 << 28)) -#define TSC_CTPH_11CYCLES ((uint32_t)((uint32_t)10 << 28)) -#define TSC_CTPH_12CYCLES ((uint32_t)((uint32_t)11 << 28)) -#define TSC_CTPH_13CYCLES ((uint32_t)((uint32_t)12 << 28)) -#define TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13 << 28)) -#define TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14 << 28)) -#define TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15 << 28)) +#define TSC_CTPH_1CYCLE 0x00000000U /*!< Charge transfer pulse high during 1 cycle (PGCLK) */ +#define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */ +#define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */ +#define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 4 cycles (PGCLK) */ +#define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 /*!< Charge transfer pulse high during 5 cycles (PGCLK) */ +#define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 6 cycles (PGCLK) */ +#define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 7 cycles (PGCLK) */ +#define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 8 cycles (PGCLK) */ +#define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 /*!< Charge transfer pulse high during 9 cycles (PGCLK) */ +#define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 10 cycles (PGCLK) */ +#define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 11 cycles (PGCLK) */ +#define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 12 cycles (PGCLK) */ +#define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) /*!< Charge transfer pulse high during 13 cycles (PGCLK) */ +#define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 14 cycles (PGCLK) */ +#define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 15 cycles (PGCLK) */ +#define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 16 cycles (PGCLK) */ /** * @} */ @@ -165,22 +232,22 @@ typedef struct /** @defgroup TSC_CTPulseLL_Config CTPulse Low Length * @{ */ -#define TSC_CTPL_1CYCLE ((uint32_t)((uint32_t) 0 << 24)) -#define TSC_CTPL_2CYCLES ((uint32_t)((uint32_t) 1 << 24)) -#define TSC_CTPL_3CYCLES ((uint32_t)((uint32_t) 2 << 24)) -#define TSC_CTPL_4CYCLES ((uint32_t)((uint32_t) 3 << 24)) -#define TSC_CTPL_5CYCLES ((uint32_t)((uint32_t) 4 << 24)) -#define TSC_CTPL_6CYCLES ((uint32_t)((uint32_t) 5 << 24)) -#define TSC_CTPL_7CYCLES ((uint32_t)((uint32_t) 6 << 24)) -#define TSC_CTPL_8CYCLES ((uint32_t)((uint32_t) 7 << 24)) -#define TSC_CTPL_9CYCLES ((uint32_t)((uint32_t) 8 << 24)) -#define TSC_CTPL_10CYCLES ((uint32_t)((uint32_t) 9 << 24)) -#define TSC_CTPL_11CYCLES ((uint32_t)((uint32_t)10 << 24)) -#define TSC_CTPL_12CYCLES ((uint32_t)((uint32_t)11 << 24)) -#define TSC_CTPL_13CYCLES ((uint32_t)((uint32_t)12 << 24)) -#define TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13 << 24)) -#define TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14 << 24)) -#define TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15 << 24)) +#define TSC_CTPL_1CYCLE 0x00000000U /*!< Charge transfer pulse low during 1 cycle (PGCLK) */ +#define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */ +#define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */ +#define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 4 cycles (PGCLK) */ +#define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 /*!< Charge transfer pulse low during 5 cycles (PGCLK) */ +#define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 6 cycles (PGCLK) */ +#define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 7 cycles (PGCLK) */ +#define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 8 cycles (PGCLK) */ +#define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 /*!< Charge transfer pulse low during 9 cycles (PGCLK) */ +#define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 10 cycles (PGCLK) */ +#define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 11 cycles (PGCLK) */ +#define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 12 cycles (PGCLK) */ +#define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) /*!< Charge transfer pulse low during 13 cycles (PGCLK) */ +#define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 14 cycles (PGCLK) */ +#define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 15 cycles (PGCLK) */ +#define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 16 cycles (PGCLK) */ /** * @} */ @@ -188,8 +255,8 @@ typedef struct /** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler * @{ */ -#define TSC_SS_PRESC_DIV1 ((uint32_t)0) -#define TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC) +#define TSC_SS_PRESC_DIV1 0x00000000U /*!< Spread Spectrum Prescaler Div1 */ +#define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC /*!< Spread Spectrum Prescaler Div2 */ /** * @} */ @@ -197,14 +264,14 @@ typedef struct /** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler * @{ */ -#define TSC_PG_PRESC_DIV1 ((uint32_t)(0 << 12)) -#define TSC_PG_PRESC_DIV2 ((uint32_t)(1 << 12)) -#define TSC_PG_PRESC_DIV4 ((uint32_t)(2 << 12)) -#define TSC_PG_PRESC_DIV8 ((uint32_t)(3 << 12)) -#define TSC_PG_PRESC_DIV16 ((uint32_t)(4 << 12)) -#define TSC_PG_PRESC_DIV32 ((uint32_t)(5 << 12)) -#define TSC_PG_PRESC_DIV64 ((uint32_t)(6 << 12)) -#define TSC_PG_PRESC_DIV128 ((uint32_t)(7 << 12)) +#define TSC_PG_PRESC_DIV1 0x00000000U /*!< Pulse Generator HCLK Div1 */ +#define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0 /*!< Pulse Generator HCLK Div2 */ +#define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1 /*!< Pulse Generator HCLK Div4 */ +#define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div8 */ +#define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2 /*!< Pulse Generator HCLK Div16 */ +#define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div32 */ +#define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1) /*!< Pulse Generator HCLK Div64 */ +#define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div128 */ /** * @} */ @@ -212,13 +279,13 @@ typedef struct /** @defgroup TSC_MaxCount_Value Max Count Value * @{ */ -#define TSC_MCV_255 ((uint32_t)(0 << 5)) -#define TSC_MCV_511 ((uint32_t)(1 << 5)) -#define TSC_MCV_1023 ((uint32_t)(2 << 5)) -#define TSC_MCV_2047 ((uint32_t)(3 << 5)) -#define TSC_MCV_4095 ((uint32_t)(4 << 5)) -#define TSC_MCV_8191 ((uint32_t)(5 << 5)) -#define TSC_MCV_16383 ((uint32_t)(6 << 5)) +#define TSC_MCV_255 0x00000000U /*!< 255 maximum number of charge transfer pulses */ +#define TSC_MCV_511 TSC_CR_MCV_0 /*!< 511 maximum number of charge transfer pulses */ +#define TSC_MCV_1023 TSC_CR_MCV_1 /*!< 1023 maximum number of charge transfer pulses */ +#define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0) /*!< 2047 maximum number of charge transfer pulses */ +#define TSC_MCV_4095 TSC_CR_MCV_2 /*!< 4095 maximum number of charge transfer pulses */ +#define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0) /*!< 8191 maximum number of charge transfer pulses */ +#define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1) /*!< 16383 maximum number of charge transfer pulses */ /** * @} */ @@ -226,8 +293,8 @@ typedef struct /** @defgroup TSC_IO_Default_Mode IO Default Mode * @{ */ -#define TSC_IODEF_OUT_PP_LOW ((uint32_t)0) -#define TSC_IODEF_IN_FLOAT (TSC_CR_IODEF) +#define TSC_IODEF_OUT_PP_LOW 0x00000000U /*!< I/Os are forced to output push-pull low */ +#define TSC_IODEF_IN_FLOAT TSC_CR_IODEF /*!< I/Os are in input floating */ /** * @} */ @@ -235,8 +302,8 @@ typedef struct /** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity * @{ */ -#define TSC_SYNC_POLARITY_FALLING ((uint32_t)0) -#define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL) +#define TSC_SYNC_POLARITY_FALLING 0x00000000U /*!< Falling edge only */ +#define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL /*!< Rising edge and high level */ /** * @} */ @@ -244,19 +311,8 @@ typedef struct /** @defgroup TSC_Acquisition_Mode Acquisition Mode * @{ */ -#define TSC_ACQ_MODE_NORMAL ((uint32_t)0) -#define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM) -/** - * @} - */ - -/** @defgroup TSC_IO_Mode IO Mode - * @{ - */ -#define TSC_IOMODE_UNUSED ((uint32_t)0) -#define TSC_IOMODE_CHANNEL ((uint32_t)1) -#define TSC_IOMODE_SHIELD ((uint32_t)2) -#define TSC_IOMODE_SAMPLING ((uint32_t)3) +#define TSC_ACQ_MODE_NORMAL 0x00000000U /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */ +#define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM /*!< Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) */ /** * @} */ @@ -264,8 +320,8 @@ typedef struct /** @defgroup TSC_interrupts_definition Interrupts definition * @{ */ -#define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE) -#define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE) +#define TSC_IT_EOA TSC_IER_EOAIE /*!< End of acquisition interrupt enable */ +#define TSC_IT_MCE TSC_IER_MCEIE /*!< Max count error interrupt enable */ /** * @} */ @@ -273,8 +329,8 @@ typedef struct /** @defgroup TSC_flags_definition Flags definition * @{ */ -#define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF) -#define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF) +#define TSC_FLAG_EOA TSC_ISR_EOAF /*!< End of acquisition flag */ +#define TSC_FLAG_MCE TSC_ISR_MCEF /*!< Max count error flag */ /** * @} */ @@ -282,76 +338,96 @@ typedef struct /** @defgroup TSC_Group_definition Group definition * @{ */ -#define TSC_NB_OF_GROUPS (8) - -#define TSC_GROUP1 ((uint32_t)0x00000001) -#define TSC_GROUP2 ((uint32_t)0x00000002) -#define TSC_GROUP3 ((uint32_t)0x00000004) -#define TSC_GROUP4 ((uint32_t)0x00000008) -#define TSC_GROUP5 ((uint32_t)0x00000010) -#define TSC_GROUP6 ((uint32_t)0x00000020) -#define TSC_GROUP7 ((uint32_t)0x00000040) -#define TSC_GROUP8 ((uint32_t)0x00000080) -#define TSC_ALL_GROUPS ((uint32_t)0x000000FF) - -#define TSC_GROUP1_IDX ((uint32_t)0) -#define TSC_GROUP2_IDX ((uint32_t)1) -#define TSC_GROUP3_IDX ((uint32_t)2) -#define TSC_GROUP4_IDX ((uint32_t)3) -#define TSC_GROUP5_IDX ((uint32_t)4) -#define TSC_GROUP6_IDX ((uint32_t)5) -#define TSC_GROUP7_IDX ((uint32_t)6) -#define TSC_GROUP8_IDX ((uint32_t)7) - -#define TSC_GROUP1_IO1 ((uint32_t)0x00000001) -#define TSC_GROUP1_IO2 ((uint32_t)0x00000002) -#define TSC_GROUP1_IO3 ((uint32_t)0x00000004) -#define TSC_GROUP1_IO4 ((uint32_t)0x00000008) -#define TSC_GROUP1_ALL_IOS ((uint32_t)0x0000000F) - -#define TSC_GROUP2_IO1 ((uint32_t)0x00000010) -#define TSC_GROUP2_IO2 ((uint32_t)0x00000020) -#define TSC_GROUP2_IO3 ((uint32_t)0x00000040) -#define TSC_GROUP2_IO4 ((uint32_t)0x00000080) -#define TSC_GROUP2_ALL_IOS ((uint32_t)0x000000F0) - -#define TSC_GROUP3_IO1 ((uint32_t)0x00000100) -#define TSC_GROUP3_IO2 ((uint32_t)0x00000200) -#define TSC_GROUP3_IO3 ((uint32_t)0x00000400) -#define TSC_GROUP3_IO4 ((uint32_t)0x00000800) -#define TSC_GROUP3_ALL_IOS ((uint32_t)0x00000F00) - -#define TSC_GROUP4_IO1 ((uint32_t)0x00001000) -#define TSC_GROUP4_IO2 ((uint32_t)0x00002000) -#define TSC_GROUP4_IO3 ((uint32_t)0x00004000) -#define TSC_GROUP4_IO4 ((uint32_t)0x00008000) -#define TSC_GROUP4_ALL_IOS ((uint32_t)0x0000F000) - -#define TSC_GROUP5_IO1 ((uint32_t)0x00010000) -#define TSC_GROUP5_IO2 ((uint32_t)0x00020000) -#define TSC_GROUP5_IO3 ((uint32_t)0x00040000) -#define TSC_GROUP5_IO4 ((uint32_t)0x00080000) -#define TSC_GROUP5_ALL_IOS ((uint32_t)0x000F0000) - -#define TSC_GROUP6_IO1 ((uint32_t)0x00100000) -#define TSC_GROUP6_IO2 ((uint32_t)0x00200000) -#define TSC_GROUP6_IO3 ((uint32_t)0x00400000) -#define TSC_GROUP6_IO4 ((uint32_t)0x00800000) -#define TSC_GROUP6_ALL_IOS ((uint32_t)0x00F00000) - -#define TSC_GROUP7_IO1 ((uint32_t)0x01000000) -#define TSC_GROUP7_IO2 ((uint32_t)0x02000000) -#define TSC_GROUP7_IO3 ((uint32_t)0x04000000) -#define TSC_GROUP7_IO4 ((uint32_t)0x08000000) -#define TSC_GROUP7_ALL_IOS ((uint32_t)0x0F000000) - -#define TSC_GROUP8_IO1 ((uint32_t)0x10000000) -#define TSC_GROUP8_IO2 ((uint32_t)0x20000000) -#define TSC_GROUP8_IO3 ((uint32_t)0x40000000) -#define TSC_GROUP8_IO4 ((uint32_t)0x80000000) -#define TSC_GROUP8_ALL_IOS ((uint32_t)0xF0000000) - -#define TSC_ALL_GROUPS_ALL_IOS ((uint32_t)0xFFFFFFFF) +#define TSC_GROUP1 (uint32_t)(0x1U << TSC_GROUP1_IDX) +#define TSC_GROUP2 (uint32_t)(0x1U << TSC_GROUP2_IDX) +#define TSC_GROUP3 (uint32_t)(0x1U << TSC_GROUP3_IDX) +#define TSC_GROUP4 (uint32_t)(0x1U << TSC_GROUP4_IDX) +#if defined(TSC_IOCCR_G5_IO1) +#define TSC_GROUP5 (uint32_t)(0x1U << TSC_GROUP5_IDX) +#endif +#if defined(TSC_IOCCR_G6_IO1) +#define TSC_GROUP6 (uint32_t)(0x1U << TSC_GROUP6_IDX) +#endif +#if defined(TSC_IOCCR_G7_IO1) +#define TSC_GROUP7 (uint32_t)(0x1U << TSC_GROUP7_IDX) +#endif +#if defined(TSC_IOCCR_G8_IO1) +#define TSC_GROUP8 (uint32_t)(0x1U << TSC_GROUP8_IDX) +#endif + +#define TSC_GROUPX_NOT_SUPPORTED 0xFF000000U /*!< TSC GroupX not supported */ + +#define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */ +#define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */ +#define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */ +#define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */ + +#define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */ +#define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */ +#define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */ +#define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */ + +#define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */ +#define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */ +#define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */ +#define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */ + +#define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1 /*!< TSC Group4 IO1 */ +#define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2 /*!< TSC Group4 IO2 */ +#define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3 /*!< TSC Group4 IO3 */ +#define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4 /*!< TSC Group4 IO4 */ +#if defined(TSC_IOCCR_G5_IO1) + +#define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1 /*!< TSC Group5 IO1 */ +#define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2 /*!< TSC Group5 IO2 */ +#define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3 /*!< TSC Group5 IO3 */ +#define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */ +#else + +#define TSC_GROUP5_IO1 (uint32_t)(0x00000010U | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group5 IO1 not supported */ +#define TSC_GROUP5_IO2 TSC_GROUP5_IO1 /*!< TSC Group5 IO2 not supported */ +#define TSC_GROUP5_IO3 TSC_GROUP5_IO1 /*!< TSC Group5 IO3 not supported */ +#define TSC_GROUP5_IO4 TSC_GROUP5_IO1 /*!< TSC Group5 IO4 not supported */ +#endif +#if defined(TSC_IOCCR_G6_IO1) + +#define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */ +#define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */ +#define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */ +#define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */ +#else + +#define TSC_GROUP6_IO1 (uint32_t)(0x00000020U | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group6 IO1 not supported */ +#define TSC_GROUP6_IO2 TSC_GROUP6_IO1 /*!< TSC Group6 IO2 not supported */ +#define TSC_GROUP6_IO3 TSC_GROUP6_IO1 /*!< TSC Group6 IO3 not supported */ +#define TSC_GROUP6_IO4 TSC_GROUP6_IO1 /*!< TSC Group6 IO4 not supported */ +#endif +#if defined(TSC_IOCCR_G7_IO1) + +#define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */ +#define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */ +#define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */ +#define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */ +#else + +#define TSC_GROUP7_IO1 (uint32_t)(0x00000040U | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group7 IO1 not supported */ +#define TSC_GROUP7_IO2 TSC_GROUP7_IO1 /*!< TSC Group7 IO2 not supported */ +#define TSC_GROUP7_IO3 TSC_GROUP7_IO1 /*!< TSC Group7 IO3 not supported */ +#define TSC_GROUP7_IO4 TSC_GROUP7_IO1 /*!< TSC Group7 IO4 not supported */ +#endif +#if defined(TSC_IOCCR_G8_IO1) + +#define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1 /*!< TSC Group8 IO1 */ +#define TSC_GROUP8_IO2 TSC_IOCCR_G8_IO2 /*!< TSC Group8 IO2 */ +#define TSC_GROUP8_IO3 TSC_IOCCR_G8_IO3 /*!< TSC Group8 IO3 */ +#define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4 /*!< TSC Group8 IO4 */ +#else + +#define TSC_GROUP8_IO1 (uint32_t)(0x00000080U | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group8 IO1 not supported */ +#define TSC_GROUP8_IO2 TSC_GROUP8_IO1 /*!< TSC Group8 IO2 not supported */ +#define TSC_GROUP8_IO3 TSC_GROUP8_IO1 /*!< TSC Group8 IO3 not supported */ +#define TSC_GROUP8_IO4 TSC_GROUP8_IO1 /*!< TSC Group8 IO4 not supported */ +#endif /** * @} */ @@ -367,193 +443,201 @@ typedef struct */ /** @brief Reset TSC handle state. - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ -#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) +#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_TSC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) +#endif /** * @brief Enable the TSC peripheral. - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ -#define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) +#define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) /** * @brief Disable the TSC peripheral. - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ -#define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE)) +#define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE)) /** * @brief Start acquisition. - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ -#define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) +#define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) /** * @brief Stop acquisition. - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ -#define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START)) +#define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START)) /** * @brief Set IO default mode to output push-pull low. - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ -#define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF)) +#define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF)) /** * @brief Set IO default mode to input floating. - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ -#define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) +#define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) /** * @brief Set synchronization polarity to falling edge. - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ -#define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL)) +#define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL)) /** * @brief Set synchronization polarity to rising edge and high level. - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ -#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) +#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) /** * @brief Enable TSC interrupt. - * @param __HANDLE__: TSC handle - * @param __INTERRUPT__: TSC interrupt + * @param __HANDLE__ TSC handle + * @param __INTERRUPT__ TSC interrupt * @retval None */ -#define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) +#define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) /** * @brief Disable TSC interrupt. - * @param __HANDLE__: TSC handle - * @param __INTERRUPT__: TSC interrupt + * @param __HANDLE__ TSC handle + * @param __INTERRUPT__ TSC interrupt * @retval None */ -#define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__))) +#define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__))) /** @brief Check whether the specified TSC interrupt source is enabled or not. - * @param __HANDLE__: TSC Handle - * @param __INTERRUPT__: TSC interrupt + * @param __HANDLE__ TSC Handle + * @param __INTERRUPT__ TSC interrupt * @retval SET or RESET */ -#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** * @brief Check whether the specified TSC flag is set or not. - * @param __HANDLE__: TSC handle - * @param __FLAG__: TSC flag + * @param __HANDLE__ TSC handle + * @param __FLAG__ TSC flag * @retval SET or RESET */ -#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET) +#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET) /** * @brief Clear the TSC's pending flag. - * @param __HANDLE__: TSC handle - * @param __FLAG__: TSC flag + * @param __HANDLE__ TSC handle + * @param __FLAG__ TSC flag * @retval None */ -#define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) +#define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** * @brief Enable schmitt trigger hysteresis on a group of IOs. - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ -#define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) +#define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) /** * @brief Disable schmitt trigger hysteresis on a group of IOs. - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ -#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__))) +#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__))) /** * @brief Open analog switch on a group of IOs. - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ -#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__))) +#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__))) /** * @brief Close analog switch on a group of IOs. - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__)) /** * @brief Enable a group of IOs in channel mode. - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ -#define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) +#define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) /** * @brief Disable a group of channel IOs. - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ -#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__))) +#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__))) /** * @brief Enable a group of IOs in sampling mode. - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ -#define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) +#define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) /** * @brief Disable a group of sampling IOs. - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__))) /** * @brief Enable acquisition groups. - * @param __HANDLE__: TSC handle - * @param __GX_MASK__: Groups mask + * @param __HANDLE__ TSC handle + * @param __GX_MASK__ Groups mask * @retval None */ #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__)) /** * @brief Disable acquisition groups. - * @param __HANDLE__: TSC handle - * @param __GX_MASK__: Groups mask + * @param __HANDLE__ TSC handle + * @param __GX_MASK__ Groups mask * @retval None */ #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__))) /** @brief Gets acquisition group status. - * @param __HANDLE__: TSC Handle - * @param __GX_INDEX__: Group index + * @param __HANDLE__ TSC Handle + * @param __GX_INDEX__ Group index * @retval SET or RESET */ #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ -((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) == (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) +((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) == (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) /** * @} @@ -565,83 +649,113 @@ typedef struct * @{ */ -#define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \ - ((VAL) == TSC_CTPH_2CYCLES) || \ - ((VAL) == TSC_CTPH_3CYCLES) || \ - ((VAL) == TSC_CTPH_4CYCLES) || \ - ((VAL) == TSC_CTPH_5CYCLES) || \ - ((VAL) == TSC_CTPH_6CYCLES) || \ - ((VAL) == TSC_CTPH_7CYCLES) || \ - ((VAL) == TSC_CTPH_8CYCLES) || \ - ((VAL) == TSC_CTPH_9CYCLES) || \ - ((VAL) == TSC_CTPH_10CYCLES) || \ - ((VAL) == TSC_CTPH_11CYCLES) || \ - ((VAL) == TSC_CTPH_12CYCLES) || \ - ((VAL) == TSC_CTPH_13CYCLES) || \ - ((VAL) == TSC_CTPH_14CYCLES) || \ - ((VAL) == TSC_CTPH_15CYCLES) || \ - ((VAL) == TSC_CTPH_16CYCLES)) - -#define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \ - ((VAL) == TSC_CTPL_2CYCLES) || \ - ((VAL) == TSC_CTPL_3CYCLES) || \ - ((VAL) == TSC_CTPL_4CYCLES) || \ - ((VAL) == TSC_CTPL_5CYCLES) || \ - ((VAL) == TSC_CTPL_6CYCLES) || \ - ((VAL) == TSC_CTPL_7CYCLES) || \ - ((VAL) == TSC_CTPL_8CYCLES) || \ - ((VAL) == TSC_CTPL_9CYCLES) || \ - ((VAL) == TSC_CTPL_10CYCLES) || \ - ((VAL) == TSC_CTPL_11CYCLES) || \ - ((VAL) == TSC_CTPL_12CYCLES) || \ - ((VAL) == TSC_CTPL_13CYCLES) || \ - ((VAL) == TSC_CTPL_14CYCLES) || \ - ((VAL) == TSC_CTPL_15CYCLES) || \ - ((VAL) == TSC_CTPL_16CYCLES)) - -#define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE)) - -#define IS_TSC_SSD(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < 128))) - -#define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2)) - -#define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \ - ((VAL) == TSC_PG_PRESC_DIV2) || \ - ((VAL) == TSC_PG_PRESC_DIV4) || \ - ((VAL) == TSC_PG_PRESC_DIV8) || \ - ((VAL) == TSC_PG_PRESC_DIV16) || \ - ((VAL) == TSC_PG_PRESC_DIV32) || \ - ((VAL) == TSC_PG_PRESC_DIV64) || \ - ((VAL) == TSC_PG_PRESC_DIV128)) - -#define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \ - ((VAL) == TSC_MCV_511) || \ - ((VAL) == TSC_MCV_1023) || \ - ((VAL) == TSC_MCV_2047) || \ - ((VAL) == TSC_MCV_4095) || \ - ((VAL) == TSC_MCV_8191) || \ - ((VAL) == TSC_MCV_16383)) - -#define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT)) - -#define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING)) - -#define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO)) - -#define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \ - ((VAL) == TSC_IOMODE_CHANNEL) || \ - ((VAL) == TSC_IOMODE_SHIELD) || \ - ((VAL) == TSC_IOMODE_SAMPLING)) - -#define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE)) - -#define IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < TSC_NB_OF_GROUPS))) +#define IS_TSC_CTPH(__VALUE__) (((__VALUE__) == TSC_CTPH_1CYCLE) || \ + ((__VALUE__) == TSC_CTPH_2CYCLES) || \ + ((__VALUE__) == TSC_CTPH_3CYCLES) || \ + ((__VALUE__) == TSC_CTPH_4CYCLES) || \ + ((__VALUE__) == TSC_CTPH_5CYCLES) || \ + ((__VALUE__) == TSC_CTPH_6CYCLES) || \ + ((__VALUE__) == TSC_CTPH_7CYCLES) || \ + ((__VALUE__) == TSC_CTPH_8CYCLES) || \ + ((__VALUE__) == TSC_CTPH_9CYCLES) || \ + ((__VALUE__) == TSC_CTPH_10CYCLES) || \ + ((__VALUE__) == TSC_CTPH_11CYCLES) || \ + ((__VALUE__) == TSC_CTPH_12CYCLES) || \ + ((__VALUE__) == TSC_CTPH_13CYCLES) || \ + ((__VALUE__) == TSC_CTPH_14CYCLES) || \ + ((__VALUE__) == TSC_CTPH_15CYCLES) || \ + ((__VALUE__) == TSC_CTPH_16CYCLES)) + +#define IS_TSC_CTPL(__VALUE__) (((__VALUE__) == TSC_CTPL_1CYCLE) || \ + ((__VALUE__) == TSC_CTPL_2CYCLES) || \ + ((__VALUE__) == TSC_CTPL_3CYCLES) || \ + ((__VALUE__) == TSC_CTPL_4CYCLES) || \ + ((__VALUE__) == TSC_CTPL_5CYCLES) || \ + ((__VALUE__) == TSC_CTPL_6CYCLES) || \ + ((__VALUE__) == TSC_CTPL_7CYCLES) || \ + ((__VALUE__) == TSC_CTPL_8CYCLES) || \ + ((__VALUE__) == TSC_CTPL_9CYCLES) || \ + ((__VALUE__) == TSC_CTPL_10CYCLES) || \ + ((__VALUE__) == TSC_CTPL_11CYCLES) || \ + ((__VALUE__) == TSC_CTPL_12CYCLES) || \ + ((__VALUE__) == TSC_CTPL_13CYCLES) || \ + ((__VALUE__) == TSC_CTPL_14CYCLES) || \ + ((__VALUE__) == TSC_CTPL_15CYCLES) || \ + ((__VALUE__) == TSC_CTPL_16CYCLES)) + +#define IS_TSC_SS(__VALUE__) (((__VALUE__) == DISABLE) || ((__VALUE__) == ENABLE)) + +#define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0U) || (((__VALUE__) > 0U) && ((__VALUE__) < 128U))) + +#define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2)) + +#define IS_TSC_PG_PRESC(__VALUE__) (((__VALUE__) == TSC_PG_PRESC_DIV1) || \ + ((__VALUE__) == TSC_PG_PRESC_DIV2) || \ + ((__VALUE__) == TSC_PG_PRESC_DIV4) || \ + ((__VALUE__) == TSC_PG_PRESC_DIV8) || \ + ((__VALUE__) == TSC_PG_PRESC_DIV16) || \ + ((__VALUE__) == TSC_PG_PRESC_DIV32) || \ + ((__VALUE__) == TSC_PG_PRESC_DIV64) || \ + ((__VALUE__) == TSC_PG_PRESC_DIV128)) + +#define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \ + ((__VALUE__) == TSC_MCV_511) || \ + ((__VALUE__) == TSC_MCV_1023) || \ + ((__VALUE__) == TSC_MCV_2047) || \ + ((__VALUE__) == TSC_MCV_4095) || \ + ((__VALUE__) == TSC_MCV_8191) || \ + ((__VALUE__) == TSC_MCV_16383)) + +#define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT)) + +#define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING) || ((__VALUE__) == TSC_SYNC_POLARITY_RISING)) + +#define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO)) + +#define IS_TSC_MCE_IT(__VALUE__) (((__VALUE__) == DISABLE) || ((__VALUE__) == ENABLE)) + +#define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0U) || (((__VALUE__) > 0U) && ((__VALUE__) < TSC_NB_OF_GROUPS))) + + +#define IS_TSC_GROUP(__VALUE__) ((((__VALUE__) & TSC_GROUPX_NOT_SUPPORTED) != TSC_GROUPX_NOT_SUPPORTED) && \ + ((((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\ + (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\ + (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\ + (((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\ + (((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\ + (((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\ + (((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\ + (((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\ + (((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\ + (((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\ + (((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\ + (((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\ + (((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\ + (((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\ + (((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\ + (((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\ + (((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\ + (((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\ + (((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\ + (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\ + (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\ + (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\ + (((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\ + (((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\ + (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\ + (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\ + (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\ + (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4) ||\ + (((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\ + (((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\ + (((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\ + (((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4))) /** * @} */ -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup TSC_Exported_Functions * @{ */ @@ -650,10 +764,16 @@ typedef struct * @{ */ /* Initialization and de-initialization functions *****************************/ -HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc); +HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc); HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc); -void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc); -void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc); +void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc); +void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, pTSC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ /** * @} */ @@ -662,13 +782,13 @@ void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc); * @{ */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc); -HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc); -HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc); -HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc); -HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc); -TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index); -uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index); +HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc); +HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc); +HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc); +HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc); +HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc); +TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index); +uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index); /** * @} */ @@ -677,8 +797,8 @@ uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index); * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config); -HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice); +HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config); +HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, uint32_t choice); /** * @} */ @@ -687,18 +807,18 @@ HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice); * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc); +HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc); /** * @} */ /** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks * @{ - */ + */ /******* TSC IRQHandler and Callbacks used in Interrupt mode */ -void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc); -void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc); -void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc); +void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc); +void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc); +void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc); /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h index 0c66b9384c..0ab0f454dd 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h @@ -38,7 +38,7 @@ #define __STM32L4xx_HAL_UART_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -75,7 +75,7 @@ typedef struct LPUART: ======= Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) - + where (uart/lpuart)_ker_ck_pres is the UART input clock divided by a prescaler */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. @@ -104,13 +104,13 @@ typedef struct uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ - + #if defined(USART_PRESC_PRESCALER) uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. This parameter can be a value of @ref UART_ClockPrescaler. */ #endif -}UART_InitTypeDef; +} UART_InitTypeDef; /** * @brief UART Advanced Features initalization structure definition @@ -156,10 +156,10 @@ typedef struct /** * @brief HAL UART State structures definition * @note HAL UART State value is a combination of 2 different substates: gState and RxState. - * - gState contains UART state information related to global Handle management + * - gState contains UART state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : - * b7-b6 Error information + * b7-b6 Error information * 00 : No Error * 01 : (Not Used) * 10 : Timeout @@ -198,7 +198,7 @@ typedef enum Value is allowed for gState and RxState */ HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use Value is allowed for gState and RxState */ - HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing + HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing Value is allowed for gState only */ HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing Value is allowed for gState only */ @@ -211,20 +211,7 @@ typedef enum Value is allowed for gState only */ HAL_UART_STATE_ERROR = 0xE0U /*!< Error Value is allowed for gState only */ -}HAL_UART_StateTypeDef; - -/** - * @brief HAL UART Error Code structure definition - */ -typedef enum -{ - HAL_UART_ERROR_NONE = 0x00U, /*!< No error */ - HAL_UART_ERROR_PE = 0x01U, /*!< Parity error */ - HAL_UART_ERROR_NE = 0x02U, /*!< Noise error */ - HAL_UART_ERROR_FE = 0x04U, /*!< frame error */ - HAL_UART_ERROR_ORE = 0x08U, /*!< Overrun error */ - HAL_UART_ERROR_DMA = 0x10U /*!< DMA transfer error */ -}HAL_UART_ErrorTypeDef; +} HAL_UART_StateTypeDef; /** * @brief UART clock sources definition @@ -237,7 +224,7 @@ typedef enum UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ -}UART_ClockSourceTypeDef; +} UART_ClockSourceTypeDef; /** * @brief UART handle Structure definition @@ -265,17 +252,12 @@ typedef struct __UART_HandleTypeDef uint16_t Mask; /*!< UART Rx RDR register mask */ #if defined(USART_CR1_FIFOEN) - uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ - - uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. This parameter can be a value of @ref UARTEx_FIFO_mode. */ -#endif -#if defined(USART_CR2_SLVEN) - uint32_t SlaveMode; /*!< Specifies if the UART SPI Slave mode is being used. - This parameter can be a value of @ref UARTEx_Slave_Mode. */ + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ + + uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ #endif void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ @@ -288,7 +270,7 @@ typedef struct __UART_HandleTypeDef HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management and also related to Tx operations. This parameter can be a value of @ref HAL_UART_StateTypeDef */ @@ -297,7 +279,58 @@ typedef struct __UART_HandleTypeDef __IO uint32_t ErrorCode; /*!< UART Error code */ -}UART_HandleTypeDef; +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ + void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ + void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ + void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ + void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ + void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ +#if defined(USART_CR1_FIFOEN) + void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */ + void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */ +#endif + + void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ + void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +} UART_HandleTypeDef; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL UART Callback ID enumeration definition + */ +typedef enum +{ + HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ + HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ + HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ + HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ + HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ + HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ + HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ + HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ + HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ +#if defined(USART_CR1_FIFOEN) + HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */ + HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */ +#endif + + HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ + HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ + +} HAL_UART_CallbackIDTypeDef; + +/** + * @brief HAL UART Callback pointer definition + */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** * @} @@ -308,6 +341,22 @@ typedef struct __UART_HandleTypeDef * @{ */ +/** @defgroup UART_Error_Definition UART Error Definition + * @{ + */ +#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ +#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ +#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +/** + * @} + */ + /** @defgroup UART_Stop_Bits UART Number of Stop Bits * @{ */ @@ -343,9 +392,9 @@ typedef struct __UART_HandleTypeDef /** @defgroup UART_Mode UART Transfer Mode * @{ */ -#define UART_MODE_RX USART_CR1_RE /*!< RX mode */ -#define UART_MODE_TX USART_CR1_TE /*!< TX mode */ -#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ +#define UART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define UART_MODE_TX USART_CR1_TE /*!< TX mode */ +#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ /** * @} */ @@ -380,7 +429,7 @@ typedef struct __UART_HandleTypeDef #if defined(USART_PRESC_PRESCALER) /** @defgroup UART_ClockPrescaler UART Clock Prescaler * @{ - */ + */ #define UART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ #define UART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ #define UART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ @@ -393,6 +442,7 @@ typedef struct __UART_HandleTypeDef #define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ #define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ #define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ + /** * @} */ @@ -403,7 +453,7 @@ typedef struct __UART_HandleTypeDef */ #define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */ #define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */ #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection on 0x55 frame detection */ /** * @} @@ -512,8 +562,8 @@ typedef struct __UART_HandleTypeDef /** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion * @{ */ -#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ -#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ +#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ +#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ /** * @} */ @@ -539,8 +589,8 @@ typedef struct __UART_HandleTypeDef /** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable * @{ */ -#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ -#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ +#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ +#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ /** * @} */ @@ -548,8 +598,8 @@ typedef struct __UART_HandleTypeDef /** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable * @{ */ -#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ +#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ /** * @} */ @@ -702,21 +752,21 @@ typedef struct __UART_HandleTypeDef * - ZZZZZ : Flag position in the ISR register(5bits) * @{ */ -#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ -#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ +#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ +#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ #if defined(USART_CR1_FIFOEN) -#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ +#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ #endif -#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ -#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ +#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ +#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ #if defined(USART_CR1_FIFOEN) -#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ +#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ #endif -#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ -#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ -#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ -#define UART_IT_CM 0x112EU /*!< UART character match interruption */ -#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ +#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ +#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ +#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ +#define UART_IT_CM 0x112EU /*!< UART character match interruption */ +#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ #if defined(USART_CR1_FIFOEN) #define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */ #define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ @@ -724,19 +774,19 @@ typedef struct __UART_HandleTypeDef #define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ #endif -/* Elements values convention: 000000000XXYYYYYb - - YYYYY : Interrupt source position in the XX register (5bits) +/* Elements values convention: 000000000XXYYYYYb + - YYYYY : Interrupt source position in the XX register (5bits) - XX : Interrupt source register (2bits) - 01: CR1 register - 10: CR2 register - 11: CR3 register */ -#define UART_IT_ERR 0x0060U /*!< UART error interruption */ - -/* Elements values convention: 0000ZZZZ00000000b - - ZZZZ : Flag position in the ISR register(4bits) */ -#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ -#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ -#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ +#define UART_IT_ERR 0x0060U /*!< UART error interruption */ + +/* Elements values convention: 0000ZZZZ00000000b + - ZZZZ : Flag position in the ISR register(4bits) */ +#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ +#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ +#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ /** * @} */ @@ -746,7 +796,7 @@ typedef struct __UART_HandleTypeDef */ #define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ #define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ -#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ +#define UART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */ #define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ #define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ #if defined(USART_CR1_FIFOEN) @@ -775,35 +825,45 @@ typedef struct __UART_HandleTypeDef * @param __HANDLE__ UART handle. * @retval None */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ - } while(0) + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ + /** @brief Flush the UART Data registers. * @param __HANDLE__ specifies the UART Handle. - * @retval None + * @retval None */ #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ do{ \ SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ - } while(0) + } while(0U) /** @brief Clear the specified UART pending flag. * @param __HANDLE__ specifies the UART Handle. * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: - * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag - * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag - * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag - * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag - * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag - * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag - * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag - * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag - * @arg @ref UART_CLEAR_CMF Character Match Clear Flag - * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag * @retval None */ #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) @@ -1016,15 +1076,15 @@ typedef struct __UART_HandleTypeDef #define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__)) /** @brief Enable the UART one bit sample method. - * @param __HANDLE__ specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None - */ + */ #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the UART one bit sample method. - * @param __HANDLE__ specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None - */ + */ #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) /** @brief Enable UART. @@ -1040,14 +1100,14 @@ typedef struct __UART_HandleTypeDef #define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) /** @brief Enable CTS flow control. - * @note This macro allows to enable CTS hardware flow control for a given UART instance, + * @note This macro allows to enable CTS hardware flow control for a given UART instance, * without need to call HAL_UART_Init() function. * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1055,17 +1115,17 @@ typedef struct __UART_HandleTypeDef do{ \ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ - } while(0) + } while(0U) /** @brief Disable CTS flow control. - * @note This macro allows to disable CTS hardware flow control for a given UART instance, + * @note This macro allows to disable CTS hardware flow control for a given UART instance, * without need to call HAL_UART_Init() function. * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1073,17 +1133,17 @@ typedef struct __UART_HandleTypeDef do{ \ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ - } while(0) + } while(0U) /** @brief Enable RTS flow control. - * @note This macro allows to enable RTS hardware flow control for a given UART instance, + * @note This macro allows to enable RTS hardware flow control for a given UART instance, * without need to call HAL_UART_Init() function. * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1091,17 +1151,17 @@ typedef struct __UART_HandleTypeDef do{ \ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ - } while(0) + } while(0U) /** @brief Disable RTS flow control. - * @note This macro allows to disable RTS hardware flow control for a given UART instance, + * @note This macro allows to disable RTS hardware flow control for a given UART instance, * without need to call HAL_UART_Init() function. * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1109,27 +1169,33 @@ typedef struct __UART_HandleTypeDef do{ \ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ - } while(0) + } while(0U) /** * @} */ -/* Private variables -----------------------------------------------------*/ -#if defined(USART_PRESC_PRESCALER) -/** @defgroup UART_Private_Variables UART Private Variables - * @{ - */ -static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; -/** - * @} - */ -#endif - /* Private macros --------------------------------------------------------*/ /** @defgroup UART_Private_Macros UART Private Macros * @{ */ #if defined(USART_PRESC_PRESCALER) +/** @brief Get UART clok division factor from clock prescaler value. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval UART clock division factor + */ +#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \ + (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) ? 1U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) ? 2U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) ? 4U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) ? 6U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) ? 8U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) ? 10U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) ? 12U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. @@ -1137,7 +1203,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((((uint64_t)(__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*256)) + ((__BAUD__)/2)) / (__BAUD__)) +#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)) + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ UART clock. @@ -1145,7 +1211,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2) + ((__BAUD__)/2)) / (__BAUD__)) +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U) + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. * @param __PCLK__ UART clock. @@ -1153,8 +1219,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2)) / (__BAUD__)) - +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__))) + ((__BAUD__)/2U)) / (__BAUD__)) #else /** @brief BRR division operation to set BRR register with LPUART. @@ -1162,37 +1227,41 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 * @param __BAUD__ Baud rate set by the user. * @retval Division result */ -#define UART_DIV_LPUART(__PCLK__, __BAUD__) (((((uint64_t)(__PCLK__)*256)) + ((__BAUD__)/2)) / (__BAUD__)) +#define UART_DIV_LPUART(__PCLK__, __BAUD__) (((((uint64_t)(__PCLK__)*256U)) + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ UART clock. * @param __BAUD__ Baud rate set by the user. * @retval Division result */ -#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2) + ((__BAUD__)/2)) / (__BAUD__)) +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. * @param __PCLK__ UART clock. * @param __BAUD__ Baud rate set by the user. * @retval Division result */ -#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2)) / (__BAUD__)) - -#endif /* USART_PRESC_PRESCALER */ +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__)) +#endif /** @brief Check whether or not UART instance is Low Power UART. * @param __HANDLE__ specifies the UART Handle. * @retval SET (instance is LPUART) or RESET (instance isn't LPUART) */ -#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE(__HANDLE__->Instance)) +#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance)) /** @brief Check UART Baud rate. * @param __BAUDRATE__ Baudrate specified by the user. - * The maximum Baud Rate is derived from the maximum clock on G0 (i.e. 52 MHz) + * The maximum Baud Rate is derived from the maximum clock on L4 * divided by the smallest oversampling used on the USART (i.e. 8) + * (i.e. 120 MHz on STM32L4Rx/L4Sx, 80 Mhz otherwise) * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */ -#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6500001U) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 15000001U) +#else +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001U) +#endif /** @brief Check UART assertion time. * @param __TIME__ 5-bit value assertion time. @@ -1208,7 +1277,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART frame number of stop bits is valid. - * @param __STOPBITS__ UART frame number of stop bits. + * @param __STOPBITS__ UART frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ #define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ @@ -1218,26 +1287,26 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that LPUART frame number of stop bits is valid. - * @param __STOPBITS__ LPUART frame number of stop bits. + * @param __STOPBITS__ LPUART frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) - */ + */ #define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \ ((__STOPBITS__) == UART_STOPBITS_2)) /** * @brief Ensure that UART frame parity is valid. - * @param __PARITY__ UART frame parity. + * @param __PARITY__ UART frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) - */ + */ #define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ ((__PARITY__) == UART_PARITY_EVEN) || \ ((__PARITY__) == UART_PARITY_ODD)) /** * @brief Ensure that UART hardware flow control is valid. - * @param __CONTROL__ UART hardware flow control. + * @param __CONTROL__ UART hardware flow control. * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) - */ + */ #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ (((__CONTROL__) == UART_HWCONTROL_NONE) || \ ((__CONTROL__) == UART_HWCONTROL_RTS) || \ @@ -1246,30 +1315,30 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART communication mode is valid. - * @param __MODE__ UART communication mode. + * @param __MODE__ UART communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ + */ #define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) /** * @brief Ensure that UART state is valid. - * @param __STATE__ UART state. + * @param __STATE__ UART state. * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) - */ + */ #define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ ((__STATE__) == UART_STATE_ENABLE)) /** * @brief Ensure that UART oversampling is valid. - * @param __SAMPLING__ UART oversampling. + * @param __SAMPLING__ UART oversampling. * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) - */ + */ #define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ ((__SAMPLING__) == UART_OVERSAMPLING_8)) /** * @brief Ensure that UART frame sampling is valid. - * @param __ONEBIT__ UART frame sampling. + * @param __ONEBIT__ UART frame sampling. * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) */ #define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ @@ -1277,7 +1346,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART auto Baud rate detection mode is valid. - * @param __MODE__ UART auto Baud rate detection mode. + * @param __MODE__ UART auto Baud rate detection mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ @@ -1287,7 +1356,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART receiver timeout setting is valid. - * @param __TIMEOUT__ UART receiver timeout setting. + * @param __TIMEOUT__ UART receiver timeout setting. * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) */ #define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ @@ -1295,7 +1364,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART LIN state is valid. - * @param __LIN__ UART LIN state. + * @param __LIN__ UART LIN state. * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) */ #define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ @@ -1303,7 +1372,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART LIN break detection length is valid. - * @param __LENGTH__ UART LIN break detection length. + * @param __LENGTH__ UART LIN break detection length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ @@ -1311,7 +1380,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART DMA TX state is valid. - * @param __DMATX__ UART DMA TX state. + * @param __DMATX__ UART DMA TX state. * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) */ #define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ @@ -1319,7 +1388,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART DMA RX state is valid. - * @param __DMARX__ UART DMA RX state. + * @param __DMARX__ UART DMA RX state. * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) */ #define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ @@ -1327,7 +1396,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART half-duplex state is valid. - * @param __HDSEL__ UART half-duplex state. + * @param __HDSEL__ UART half-duplex state. * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) */ #define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ @@ -1335,7 +1404,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART wake-up method is valid. - * @param __WAKEUP__ UART wake-up method . + * @param __WAKEUP__ UART wake-up method . * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) */ #define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ @@ -1343,7 +1412,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART request parameter is valid. - * @param __PARAM__ UART request parameter. + * @param __PARAM__ UART request parameter. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ #define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ @@ -1354,7 +1423,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART advanced features initialization is valid. - * @param __INIT__ UART advanced features initialization. + * @param __INIT__ UART advanced features initialization. * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) */ #define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ @@ -1369,7 +1438,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART frame TX inversion setting is valid. - * @param __TXINV__ UART frame TX inversion setting. + * @param __TXINV__ UART frame TX inversion setting. * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) */ #define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ @@ -1377,7 +1446,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART frame RX inversion setting is valid. - * @param __RXINV__ UART frame RX inversion setting. + * @param __RXINV__ UART frame RX inversion setting. * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) */ #define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ @@ -1385,7 +1454,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART frame data inversion setting is valid. - * @param __DATAINV__ UART frame data inversion setting. + * @param __DATAINV__ UART frame data inversion setting. * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) */ #define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ @@ -1393,7 +1462,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART frame RX/TX pins swap setting is valid. - * @param __SWAP__ UART frame RX/TX pins swap setting. + * @param __SWAP__ UART frame RX/TX pins swap setting. * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) */ #define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ @@ -1401,7 +1470,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART frame overrun setting is valid. - * @param __OVERRUN__ UART frame overrun setting. + * @param __OVERRUN__ UART frame overrun setting. * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) */ #define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ @@ -1409,7 +1478,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART auto Baud rate state is valid. - * @param __AUTOBAUDRATE__ UART auto Baud rate state. + * @param __AUTOBAUDRATE__ UART auto Baud rate state. * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) */ #define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ @@ -1417,7 +1486,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART DMA enabling or disabling on error setting is valid. - * @param __DMA__ UART DMA enabling or disabling on error setting. + * @param __DMA__ UART DMA enabling or disabling on error setting. * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) */ #define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ @@ -1425,7 +1494,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART frame MSB first setting is valid. - * @param __MSBFIRST__ UART frame MSB first setting. + * @param __MSBFIRST__ UART frame MSB first setting. * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) */ #define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ @@ -1433,7 +1502,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART stop mode state is valid. - * @param __STOPMODE__ UART stop mode state. + * @param __STOPMODE__ UART stop mode state. * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) */ #define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ @@ -1441,7 +1510,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART mute mode state is valid. - * @param __MUTE__ UART mute mode state. + * @param __MUTE__ UART mute mode state. * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) */ #define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ @@ -1449,7 +1518,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART wake-up selection is valid. - * @param __WAKE__ UART wake-up selection. + * @param __WAKE__ UART wake-up selection. * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) */ #define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ @@ -1458,7 +1527,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART driver enable polarity is valid. - * @param __POLARITY__ UART driver enable polarity. + * @param __POLARITY__ UART driver enable polarity. * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) */ #define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ @@ -1467,7 +1536,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 #if defined(USART_PRESC_PRESCALER) /** * @brief Ensure that UART Prescaler is valid. - * @param __CLOCKPRESCALER__ UART Prescaler value. + * @param __CLOCKPRESCALER__ UART Prescaler value. * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) */ #define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) || \ @@ -1484,32 +1553,6 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256)) #endif -#if defined(USART_CR1_FIFOEN) -/** - * @brief Ensure that UART TXFIFO threshold level is valid. - * @param __THRESHOLD__ UART TXFIFO threshold level. - * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) - */ -#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) - -/** - * @brief Ensure that UART RXFIFO threshold level is valid. - * @param __THRESHOLD__ UART RXFIFO threshold level. - * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) - */ -#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) -#endif - /** * @} */ @@ -1517,6 +1560,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /* Include UART HAL Extended module */ #include "stm32l4xx_hal_uart_ex.h" + /* Exported functions --------------------------------------------------------*/ /** @addtogroup UART_Exported_Functions UART Exported Functions * @{ @@ -1531,10 +1575,16 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); -HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); void HAL_UART_MspInit(UART_HandleTypeDef *huart); void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + /** * @} */ @@ -1567,9 +1617,9 @@ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); -void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart); -void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart); -void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart); +void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); /** * @} @@ -1586,7 +1636,6 @@ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); - /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h index d9d60e7736..6daebd17ee 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h @@ -38,7 +38,7 @@ #define __STM32L4xx_HAL_UART_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -85,36 +85,35 @@ typedef struct /** @defgroup UARTEx_Word_Length UARTEx Word Length * @{ */ -#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ -#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ -#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ +#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ +#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ +#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ /** * @} */ - + /** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length * @{ */ -#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ -#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ +#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ /** * @} */ -#if defined(USART_CR2_SLVEN) -/** @defgroup UARTEx_Slave_Select_management UARTEx Slave Select Management +#if defined(USART_CR1_FIFOEN) +/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode + * @brief UART FIFO mode * @{ */ -#define UART_NSS_HARD 0x00000000U /*!< SPI slave selection depends on NSS input pin */ -#define UART_NSS_SOFT USART_CR2_DIS_NSS /*!< SPI slave is always selected and NSS input pin is ignored */ +#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ /** * @} */ -#endif -#if defined(USART_CR1_FIFOEN) /** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level - * @brief UART TXFIFO level + * @brief UART TXFIFO threshold level * @{ */ #define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ @@ -126,9 +125,9 @@ typedef struct /** * @} */ - + /** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level - * @brief UART RXFIFO level + * @brief UART RXFIFO threshold level * @{ */ #define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ @@ -167,14 +166,13 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, * @{ */ -/* IO operation functions *****************************************************/ void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); #if defined(USART_CR1_FIFOEN) void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); #endif - + /** * @} */ @@ -187,14 +185,11 @@ void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); +#if defined(USART_CR3_UCESM) +HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart); +#endif /* USART_CR3_UCESM */ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); - -#if defined(USART_CR2_SLVEN) -HAL_StatusTypeDef HAL_UARTEx_EnableSlaveMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UARTEx_DisableSlaveMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UARTEx_ConfigNSS(UART_HandleTypeDef *huart, uint32_t NSSConfig); -#endif - #if defined(USART_CR1_FIFOEN) HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); @@ -202,7 +197,6 @@ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint3 HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); #endif - /** * @} */ @@ -211,35 +205,6 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 * @} */ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup UARTEx_Private_Constants UARTEx Private Constants - * @{ - */ -#if defined(USART_CR2_SLVEN) -/** @defgroup UARTEx_Slave_Mode UARTEx Synchronous Slave mode - * @{ - */ -#define UART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */ -#define UART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */ -/** - * @} - */ -#endif - -#if defined(USART_CR1_FIFOEN) -/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode - * @{ - */ -#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ -#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ -/** - * @} - */ -#endif -/** - * @} - */ - /* Private macros ------------------------------------------------------------*/ /** @defgroup UARTEx_Private_Macros UARTEx Private Macros * @{ @@ -250,9 +215,9 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 * @param __CLOCKSOURCE__ output variable. * @retval UART clocking source, written in __CLOCKSOURCE__. */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) \ + || defined (STM32L496xx) || defined (STM32L4A6xx) \ + || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ @@ -381,7 +346,7 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 break; \ } \ } \ - } while(0) + } while(0U) #elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ @@ -469,7 +434,7 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 break; \ } \ } \ - } while(0) + } while(0U) #elif defined (STM32L432xx) || defined (STM32L442xx) #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ @@ -536,7 +501,7 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 break; \ } \ } \ - } while(0) + } while(0U) #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ @@ -645,7 +610,7 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 break; \ } \ } \ - } while(0) + } while(0U) #endif /** @brief Report the UART mask to apply to retrieve the received data @@ -654,7 +619,7 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 * by the reception API(). * This masking operation is not carried out in the case of * DMA transfers. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. */ #define UART_MASK_COMPUTATION(__HANDLE__) \ @@ -663,41 +628,41 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 { \ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x01FF ; \ + (__HANDLE__)->Mask = 0x01FFU ; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x00FF ; \ + (__HANDLE__)->Mask = 0x00FFU ; \ } \ } \ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ { \ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x00FF ; \ + (__HANDLE__)->Mask = 0x00FFU ; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x007F ; \ + (__HANDLE__)->Mask = 0x007FU ; \ } \ } \ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ { \ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x007F ; \ + (__HANDLE__)->Mask = 0x007FU ; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x003F ; \ + (__HANDLE__)->Mask = 0x003FU ; \ } \ } \ -} while(0) +} while(0U) /** * @brief Ensure that UART frame length is valid. - * @param __LENGTH__ UART frame length. + * @param __LENGTH__ UART frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ @@ -706,46 +671,36 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 /** * @brief Ensure that UART wake-up address length is valid. - * @param __ADDRESS__ UART wake-up address length. + * @param __ADDRESS__ UART wake-up address length. * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) */ #define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) -#if defined(USART_CR2_SLVEN) -/** - * @brief Ensure that UART Negative Slave Select (NSS) pin management is valid. - * @param __NSS__ UART Negative Slave Select pin management. - * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid) - */ -#define IS_UART_NSS(__NSS__) (((__NSS__) == UART_NSS_HARD) || \ - ((__NSS__) == UART_NSS_SOFT)) -#endif - #if defined(USART_CR1_FIFOEN) /** * @brief Ensure that UART TXFIFO threshold level is valid. - * @param __THRESHOLD__ UART TXFIFO threshold level. + * @param __THRESHOLD__ UART TXFIFO threshold level. * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) */ -#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) +#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) /** - * @brief Ensure that USART RXFIFO threshold level is valid. - * @param __THRESHOLD__ USART RXFIFO threshold level. + * @brief Ensure that UART RXFIFO threshold level is valid. + * @param __THRESHOLD__ UART RXFIFO threshold level. * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) */ -#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) +#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) #endif /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart.h index c753d8dff9..47df742f8d 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart.h @@ -38,7 +38,7 @@ #define __STM32L4xx_HAL_USART_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -100,8 +100,7 @@ typedef struct uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the USART clock source. This parameter can be a value of @ref USART_ClockPrescaler. */ #endif - -}USART_InitTypeDef; +} USART_InitTypeDef; /** * @brief HAL USART State structures definition @@ -116,21 +115,7 @@ typedef enum HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */ HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ HAL_USART_STATE_ERROR = 0x04U /*!< Error */ -}HAL_USART_StateTypeDef; - -/** - * @brief HAL USART Error Code structure definition - */ -typedef enum -{ - HAL_USART_ERROR_NONE = 0x00U, /*!< No error */ - HAL_USART_ERROR_PE = 0x01U, /*!< Parity error */ - HAL_USART_ERROR_NE = 0x02U, /*!< Noise error */ - HAL_USART_ERROR_FE = 0x04U, /*!< frame error */ - HAL_USART_ERROR_ORE = 0x08U, /*!< Overrun error */ - HAL_USART_ERROR_DMA = 0x10U, /*!< DMA transfer error */ - HAL_USART_ERROR_UDR = 0x20U /*!< SPI slave underrun error */ -}HAL_USART_ErrorTypeDef; +} HAL_USART_StateTypeDef; /** * @brief USART clock sources definitions @@ -143,7 +128,7 @@ typedef enum USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ -}USART_ClockSourceTypeDef; +} USART_ClockSourceTypeDef; /** @@ -151,7 +136,7 @@ typedef enum */ typedef struct __USART_HandleTypeDef { - USART_TypeDef *Instance; /*!< USART registers base address */ + USART_TypeDef *Instance; /*!< USART registers base address */ USART_InitTypeDef Init; /*!< USART communication parameters */ @@ -173,31 +158,80 @@ typedef struct __USART_HandleTypeDef uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - - uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. - This parameter can be a value of @ref USARTEx_FIFO_mode. */ #endif #if defined(USART_CR2_SLVEN) - uint32_t SlaveMode; /*!< Specifies if the UART SPI Slave mode is being used. - This parameter can be a value of @ref USARTEx_Slave_Mode. */ + uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value + of @ref USARTEx_Slave_Mode */ +#endif + +#if defined(USART_CR1_FIFOEN) + uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value + of @ref USARTEx_FIFO_mode. */ #endif void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */ void (*TxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Tx IRQ handler */ - DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */ + DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */ - DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */ + DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */ HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_USART_StateTypeDef State; /*!< USART communication state */ + __IO HAL_USART_StateTypeDef State; /*!< USART communication state */ + + __IO uint32_t ErrorCode; /*!< USART Error code */ + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Complete Callback */ + void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Rx Complete Callback */ + void (* ErrorCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Error Callback */ + void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Abort Complete Callback */ +#if defined(USART_CR1_FIFOEN) + void (* RxFifoFullCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Fifo Full Callback */ + void (* TxFifoEmptyCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Fifo Empty Callback */ +#endif + + void (* MspInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp Init callback */ + void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp DeInit callback */ +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +} USART_HandleTypeDef; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL USART Callback ID enumeration definition + */ +typedef enum +{ + HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< USART Tx Half Complete Callback ID */ + HAL_USART_TX_COMPLETE_CB_ID = 0x01U, /*!< USART Tx Complete Callback ID */ + HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< USART Rx Half Complete Callback ID */ + HAL_USART_RX_COMPLETE_CB_ID = 0x03U, /*!< USART Rx Complete Callback ID */ + HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, /*!< USART Tx Rx Complete Callback ID */ + HAL_USART_ERROR_CB_ID = 0x05U, /*!< USART Error Callback ID */ + HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, /*!< USART Abort Complete Callback ID */ +#if defined(USART_CR1_FIFOEN) + HAL_USART_RX_FIFO_FULL_CB_ID = 0x07U, /*!< USART Rx Fifo Full Callback ID */ + HAL_USART_TX_FIFO_EMPTY_CB_ID = 0x08U, /*!< USART Tx Fifo Empty Callback ID */ +#endif + + HAL_USART_MSPINIT_CB_ID = 0x09U, /*!< USART MspInit callback ID */ + HAL_USART_MSPDEINIT_CB_ID = 0x0AU /*!< USART MspDeInit callback ID */ + +} HAL_USART_CallbackIDTypeDef; - __IO uint32_t ErrorCode; /*!< USART Error code */ +/** + * @brief HAL USART Callback pointer definition + */ +typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< pointer to an USART callback function */ -}USART_HandleTypeDef; +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ /** * @} @@ -208,13 +242,32 @@ typedef struct __USART_HandleTypeDef * @{ */ +/** @defgroup USART_Error_Definition USART Error Definition + * @{ + */ +#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ +#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ +#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */ +#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ +#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ +#if defined(USART_CR2_SLVEN) +#define HAL_USART_ERROR_UDR ((uint32_t)0x00000020U) /*!< SPI slave underrun error */ +#endif +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +/** + * @} + */ + /** @defgroup USART_Stop_Bits USART Number of Stop Bits * @{ */ #define USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< USART frame with 0.5 stop bit */ -#define USART_STOPBITS_1 0x00000000U /*!< USART frame with 1 stop bit */ -#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */ -#define USART_STOPBITS_2 USART_CR2_STOP_1 /*!< USART frame with 2 stop bits */ +#define USART_STOPBITS_1 0x00000000U /*!< USART frame with 1 stop bit */ +#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */ +#define USART_STOPBITS_2 USART_CR2_STOP_1 /*!< USART frame with 2 stop bits */ /** * @} */ @@ -231,9 +284,9 @@ typedef struct __USART_HandleTypeDef /** @defgroup USART_Mode USART Mode * @{ - */ -#define USART_MODE_RX USART_CR1_RE /*!< RX mode */ -#define USART_MODE_TX USART_CR1_TE /*!< TX mode */ + */ +#define USART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define USART_MODE_TX USART_CR1_TE /*!< TX mode */ #define USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ /** * @} @@ -287,7 +340,7 @@ typedef struct __USART_HandleTypeDef #if defined(USART_PRESC_PRESCALER) /** @defgroup USART_ClockPrescaler USART Clock Prescaler * @{ - */ + */ #define USART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ #define USART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ #define USART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ @@ -300,6 +353,7 @@ typedef struct __USART_HandleTypeDef #define USART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ #define USART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ #define USART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ + /** * @} */ @@ -324,26 +378,31 @@ typedef struct __USART_HandleTypeDef #define USART_FLAG_RXFT USART_ISR_RXFT /*!< USART RXFIFO threshold flag */ #define USART_FLAG_RXFF USART_ISR_RXFF /*!< USART RXFIFO Full flag */ #define USART_FLAG_TXFE USART_ISR_TXFE /*!< USART TXFIFO Empty flag */ -#define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */ -#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */ -#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */ -#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */ -#else -#define USART_FLAG_TXE USART_ISR_TXE /*!< USART transmit data register empty */ -#define USART_FLAG_RXNE USART_ISR_RXNE /*!< USART read data register not empty */ #endif -#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */ -#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */ -#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */ -#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */ -#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */ -#define USART_FLAG_ORE USART_ISR_ORE /*!< USART overrun error */ -#define USART_FLAG_NE USART_ISR_NE /*!< USART noise error */ -#define USART_FLAG_FE USART_ISR_FE /*!< USART frame error */ -#define USART_FLAG_PE USART_ISR_PE /*!< USART parity error */ +#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */ +#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */ +#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */ #if defined(USART_CR2_SLVEN) -#define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */ +#define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */ #endif +#if defined(USART_CR1_FIFOEN) +#define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */ +#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */ +#else +#define USART_FLAG_TXE USART_ISR_TXE /*!< USART transmit data register empty */ +#endif +#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */ +#if defined(USART_CR1_FIFOEN) +#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */ +#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */ +#else +#define USART_FLAG_RXNE USART_ISR_RXNE /*!< USART read data register not empty */ +#endif +#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */ +#define USART_FLAG_ORE USART_ISR_ORE /*!< USART overrun error */ +#define USART_FLAG_NE USART_ISR_NE /*!< USART noise error */ +#define USART_FLAG_FE USART_ISR_FE /*!< USART frame error */ +#define USART_FLAG_PE USART_ISR_PE /*!< USART parity error */ /** * @} */ @@ -360,22 +419,26 @@ typedef struct __USART_HandleTypeDef */ #define USART_IT_PE 0x0028U /*!< USART parity error interruption */ +#define USART_IT_TXE 0x0727U /*!< USART transmit data register empty interruption */ #if defined(USART_CR1_FIFOEN) #define USART_IT_TXFNF 0x0727U /*!< USART TX FIFO not full interruption */ -#define USART_IT_RXFNE 0x0525U /*!< USART RXFIFO not empty interruption */ -#define USART_IT_RXFF 0x183FU /*!< USART RXFIFO full interruption */ -#define USART_IT_TXFE 0x173EU /*!< USART TXFIFO empty interruption */ -#define USART_IT_RXFT 0x1A7CU /*!< USART RXFIFO threshold reached interruption */ -#define USART_IT_TXFT 0x1B77U /*!< USART TXFIFO threshold reached interruption */ #endif -#define USART_IT_TXE 0x0727U /*!< USART transmit data register empty interruption */ #define USART_IT_TC 0x0626U /*!< USART transmission complete interruption */ #define USART_IT_RXNE 0x0525U /*!< USART read data register not empty interruption */ +#if defined(USART_CR1_FIFOEN) +#define USART_IT_RXFNE 0x0525U /*!< USART RXFIFO not empty interruption */ +#endif #define USART_IT_IDLE 0x0424U /*!< USART idle interruption */ #define USART_IT_ERR 0x0060U /*!< USART error interruption */ #define USART_IT_ORE 0x0300U /*!< USART overrun error interruption */ #define USART_IT_NE 0x0200U /*!< USART noise error interruption */ #define USART_IT_FE 0x0100U /*!< USART frame error interruption */ +#if defined(USART_CR1_FIFOEN) +#define USART_IT_RXFF 0x183FU /*!< USART RXFIFO full interruption */ +#define USART_IT_TXFE 0x173EU /*!< USART TXFIFO empty interruption */ +#define USART_IT_RXFT 0x1A7CU /*!< USART RXFIFO threshold reached interruption */ +#define USART_IT_TXFT 0x1B77U /*!< USART TXFIFO threshold reached interruption */ +#endif /** * @} @@ -386,23 +449,23 @@ typedef struct __USART_HandleTypeDef */ #define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ #define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ -#define USART_CLEAR_NEF USART_ICR_NECF /*!< Noise detected Clear Flag */ +#define USART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */ #define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ #define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ #define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ -#if defined(USART_CR1_FIFOEN) -#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */ -#endif #if defined(USART_CR2_SLVEN) #define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */ #endif +#if defined(USART_CR1_FIFOEN) +#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */ +#endif /** * @} */ /** @defgroup USART_Interruption_Mask USART Interruption Flags Mask * @{ - */ + */ #define USART_IT_MASK 0x001FU /*!< USART interruptions flags mask */ /** * @} @@ -421,7 +484,15 @@ typedef struct __USART_HandleTypeDef * @param __HANDLE__ USART handle. * @retval None */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_USART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ /** @brief Check whether the specified USART flag is set or not. * @param __HANDLE__ specifies the USART Handle @@ -453,13 +524,13 @@ typedef struct __USART_HandleTypeDef * @param __HANDLE__ specifies the USART Handle. * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: - * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag - * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag - * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag - * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag - * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag - * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag - * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag * @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag * @retval None */ @@ -608,13 +679,13 @@ typedef struct __USART_HandleTypeDef * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt. * This parameter can be one of the following values: - * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag - * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag - * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag - * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag - * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag - * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag - * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag * @retval None */ #define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) @@ -631,15 +702,15 @@ typedef struct __USART_HandleTypeDef #define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__)) /** @brief Enable the USART one bit sample method. - * @param __HANDLE__ specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None - */ + */ #define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the USART one bit sample method. - * @param __HANDLE__ specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None - */ + */ #define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) /** @brief Enable USART. @@ -658,37 +729,44 @@ typedef struct __USART_HandleTypeDef * @} */ -/* Private variables -----------------------------------------------------*/ -#if defined(USART_PRESC_PRESCALER) -/** @defgroup USART_Private_Variables USART Private Variables - * @{ - */ -static const uint16_t USARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; -/** - * @} - */ -#endif - /* Private macros --------------------------------------------------------*/ /** @defgroup USART_Private_Macros USART Private Macros * @{ */ #if defined(USART_PRESC_PRESCALER) +/** @brief Get USART clock division factor from clock prescaler value. + * @param __CLOCKPRESCALER__ USART prescaler value. + * @retval USART clock division factor + */ +#define USART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \ + (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) ? 1U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) ? 2U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) ? 4U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) ? 6U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) ? 8U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) ? 10U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) ? 12U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U) + /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ USART clock. * @param __BAUD__ Baud rate set by the user. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USARTPrescTable[(__CLOCKPRESCALER__)])*2) + ((__BAUD__)/2)) / (__BAUD__)) +#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U) + ((__BAUD__)/2U)) / (__BAUD__)) #else /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ USART clock. * @param __BAUD__ Baud rate set by the user. * @retval Division result */ -#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2) + ((__BAUD__)/2)) / (__BAUD__)) +#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__)) #endif /** @brief Check USART Baud rate. @@ -696,16 +774,17 @@ static const uint16_t USARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, * The maximum Baud Rate is derived from the maximum clock on L4 * divided by the smallest oversampling used on the USART (i.e. 8) * (i.e. 120 MHz on STM32L4Rx/L4Sx, 80 Mhz otherwise) - * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */ + * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) + */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 15000001U) +#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 15000000U) #else -#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001U) +#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U) #endif /** * @brief Ensure that USART frame number of stop bits is valid. - * @param __STOPBITS__ USART frame number of stop bits. + * @param __STOPBITS__ USART frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ #define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \ @@ -715,53 +794,53 @@ static const uint16_t USARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, /** * @brief Ensure that USART frame parity is valid. - * @param __PARITY__ USART frame parity. + * @param __PARITY__ USART frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) - */ + */ #define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \ ((__PARITY__) == USART_PARITY_EVEN) || \ - ((__PARITY__) == USART_PARITY_ODD)) + ((__PARITY__) == USART_PARITY_ODD)) /** * @brief Ensure that USART communication mode is valid. - * @param __MODE__ USART communication mode. + * @param __MODE__ USART communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3U) == 0x00U) && ((__MODE__) != (uint32_t)0x00U)) + */ +#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) /** * @brief Ensure that USART oversampling is valid. - * @param __SAMPLING__ USART oversampling. + * @param __SAMPLING__ USART oversampling. * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) - */ + */ #define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ ((__SAMPLING__) == USART_OVERSAMPLING_8)) /** * @brief Ensure that USART clock state is valid. - * @param __CLOCK__ USART clock state. + * @param __CLOCK__ USART clock state. * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid) - */ + */ #define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \ ((__CLOCK__) == USART_CLOCK_ENABLE)) /** * @brief Ensure that USART frame polarity is valid. - * @param __CPOL__ USART frame polarity. + * @param __CPOL__ USART frame polarity. * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) - */ + */ #define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH)) /** * @brief Ensure that USART frame phase is valid. - * @param __CPHA__ USART frame phase. + * @param __CPHA__ USART frame phase. * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) */ #define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE)) /** * @brief Ensure that USART frame last bit clock pulse setting is valid. - * @param __LASTBIT__ USART frame last bit clock pulse setting. + * @param __LASTBIT__ USART frame last bit clock pulse setting. * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) */ #define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \ @@ -769,7 +848,7 @@ static const uint16_t USARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, /** * @brief Ensure that USART request parameter is valid. - * @param __PARAM__ USART request parameter. + * @param __PARAM__ USART request parameter. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ #define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \ @@ -778,7 +857,7 @@ static const uint16_t USARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, #if defined(USART_PRESC_PRESCALER) /** * @brief Ensure that USART Prescaler is valid. - * @param __CLOCKPRESCALER__ USART Prescaler value. + * @param __CLOCKPRESCALER__ USART Prescaler value. * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) */ #define IS_USART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) || \ @@ -817,6 +896,12 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart); void HAL_USART_MspInit(USART_HandleTypeDef *husart); void HAL_USART_MspDeInit(USART_HandleTypeDef *husart); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart_ex.h index 86c77acc7f..e10439ff77 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart_ex.h @@ -38,7 +38,7 @@ #define __STM32L4xx_HAL_USART_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -57,13 +57,13 @@ /** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants * @{ */ - + /** @defgroup USARTEx_Word_Length USARTEx Word Length * @{ */ -#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */ -#define USART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long USART frame */ -#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */ +#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */ +#define USART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */ /** * @} */ @@ -72,72 +72,64 @@ /** @defgroup USARTEx_Slave_Select_management USARTEx Slave Select Management * @{ */ -#define USART_NSS_HARD 0x00000000U /*!< SPI slave selection depends on NSS input pin */ -#define USART_NSS_SOFT USART_CR2_DIS_NSS /*!< SPI slave is always selected and NSS input pin is ignored */ +#define USART_NSS_HARD 0x00000000U /*!< SPI slave selection depends on NSS input pin */ +#define USART_NSS_SOFT USART_CR2_DIS_NSS /*!< SPI slave is always selected and NSS input pin is ignored */ /** * @} */ -#endif -#if defined(USART_CR1_FIFOEN) -/** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level - * @brief USART TXFIFO level - * @{ - */ -#define USART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ -#define USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ -#define USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ -#define USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ -#define USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ -#define USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ -/** - * @} - */ -/** @defgroup USARTEx_RXFIFO_threshold_level USARTEx RXFIFO threshold level - * @brief USART RXFIFO level +/** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode enable + * @brief USART SLAVE mode * @{ */ -#define USART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ -#define USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ -#define USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ -#define USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ -#define USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ -#define USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ +#define USART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */ +#define USART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */ /** * @} */ #endif +#if defined(USART_CR1_FIFOEN) +/** @defgroup USARTEx_FIFO_mode USARTEx FIFO mode + * @brief USART FIFO mode + * @{ + */ +#define USART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define USART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ /** * @} */ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup USARTEx_Private_Constants USARTEx Private Constants - * @{ - */ -#if defined(USART_CR2_SLVEN) -/** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode +/** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level + * @brief USART TXFIFO level * @{ */ -#define USART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */ -#define USART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */ +#define USART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ +#define USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ +#define USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ +#define USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ +#define USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ +#define USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ /** * @} */ -#endif -#if defined(USART_CR1_FIFOEN) -/** @defgroup USARTEx_FIFO_mode USARTEx FIFO mode +/** @defgroup USARTEx_RXFIFO_threshold_level USARTEx RXFIFO threshold level + * @brief USART RXFIFO level * @{ */ -#define USART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ -#define USART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +#define USART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ +#define USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ +#define USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ +#define USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ +#define USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ +#define USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ /** * @} */ #endif + /** * @} */ @@ -148,8 +140,8 @@ */ /** @brief Report the USART clock source. - * @param __HANDLE__: specifies the USART Handle. - * @param __CLOCKSOURCE__: output variable. + * @param __HANDLE__ specifies the USART Handle. + * @param __CLOCKSOURCE__ output variable. * @retval the USART clocking source, written in __CLOCKSOURCE__. */ #if defined (STM32L432xx) || defined (STM32L442xx) @@ -282,60 +274,77 @@ { \ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x01FF ; \ + (__HANDLE__)->Mask = 0x01FFU; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x00FF ; \ + (__HANDLE__)->Mask = 0x00FFU; \ } \ } \ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \ { \ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x00FF ; \ + (__HANDLE__)->Mask = 0x00FFU; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x007F ; \ + (__HANDLE__)->Mask = 0x007FU; \ } \ } \ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \ { \ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x007F ; \ + (__HANDLE__)->Mask = 0x007FU; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x003F ; \ + (__HANDLE__)->Mask = 0x003FU; \ } \ } \ -} while(0) +} while(0U) /** * @brief Ensure that USART frame length is valid. - * @param __LENGTH__ USART frame length. + * @param __LENGTH__ USART frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \ ((__LENGTH__) == USART_WORDLENGTH_8B) || \ ((__LENGTH__) == USART_WORDLENGTH_9B)) + #if defined(USART_CR2_SLVEN) /** * @brief Ensure that USART Negative Slave Select (NSS) pin management is valid. - * @param __NSS__ USART Negative Slave Select pin management. + * @param __NSS__ USART Negative Slave Select pin management. * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid) */ #define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HARD) || \ ((__NSS__) == USART_NSS_SOFT)) + +/** + * @brief Ensure that USART Slave Mode is valid. + * @param __STATE__ USART Slave Mode. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_USART_SLAVEMODE(__STATE__) (((__STATE__) == USART_SLAVEMODE_DISABLE ) || \ + ((__STATE__) == USART_SLAVEMODE_ENABLE)) #endif #if defined(USART_CR1_FIFOEN) +/** + * @brief Ensure that USART FIFO mode is valid. + * @param __STATE__ USART FIFO mode. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_USART_FIFO_MODE_STATE(__STATE__) (((__STATE__) == USART_FIFOMODE_DISABLE ) || \ + ((__STATE__) == USART_FIFOMODE_ENABLE)) + /** * @brief Ensure that USART TXFIFO threshold level is valid. - * @param __THRESHOLD__ USART TXFIFO threshold level. + * @param __THRESHOLD__ USART TXFIFO threshold level. * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) */ #define IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8) || \ @@ -343,11 +352,11 @@ ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2) || \ ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4) || \ ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8)) + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8)) /** * @brief Ensure that USART RXFIFO threshold level is valid. - * @param __THRESHOLD__ USART RXFIFO threshold level. + * @param __THRESHOLD__ USART RXFIFO threshold level. * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) */ #define IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8) || \ @@ -357,7 +366,6 @@ ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8) || \ ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8)) #endif - /** * @} */ @@ -391,7 +399,6 @@ HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig); #endif - #if defined(USART_CR1_FIFOEN) HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart); diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_wwdg.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_wwdg.h index b8bad9f7df..2211c8b24f 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_wwdg.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_wwdg.h @@ -58,7 +58,7 @@ * @{ */ -/** +/** * @brief WWDG Init structure definition */ typedef struct @@ -75,18 +75,40 @@ typedef struct uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not. This parameter can be a value of @ref WWDG_EWI_Mode */ -}WWDG_InitTypeDef; +} WWDG_InitTypeDef; /** * @brief WWDG handle Structure definition */ -typedef struct +typedef struct __WWDG_HandleTypeDef { - WWDG_TypeDef *Instance; /*!< Register base address */ + WWDG_TypeDef *Instance; /*!< Register base address */ + + WWDG_InitTypeDef Init; /*!< WWDG required parameters */ + +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) + void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */ - WWDG_InitTypeDef Init; /*!< WWDG required parameters */ + void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */ +#endif +} WWDG_HandleTypeDef; -}WWDG_HandleTypeDef; +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) +/** + * @brief HAL WWDG common Callback ID enumeration definition + */ +typedef enum +{ + HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */ + HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */ +}HAL_WWDG_CallbackIDTypeDef; + +/** + * @brief HAL WWDG Callback pointer definition + */ +typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer to a WWDG common callback functions */ + +#endif /** * @} */ @@ -117,10 +139,10 @@ typedef struct /** @defgroup WWDG_Prescaler WWDG Prescaler * @{ */ -#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */ -#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ -#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ -#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */ +#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */ +#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ +#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ +#define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/8 */ /** * @} */ @@ -143,9 +165,9 @@ typedef struct /** @defgroup WWDG_Private_Macros WWDG Private Macros * @{ */ -#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \ - ((__PRESCALER__) == WWDG_PRESCALER_2) || \ - ((__PRESCALER__) == WWDG_PRESCALER_4) || \ +#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \ + ((__PRESCALER__) == WWDG_PRESCALER_2) || \ + ((__PRESCALER__) == WWDG_PRESCALER_4) || \ ((__PRESCALER__) == WWDG_PRESCALER_8)) #define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W)) @@ -247,6 +269,12 @@ typedef struct /* Initialization/de-initialization functions **********************************/ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg); void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID); +#endif + /** * @} */ @@ -257,7 +285,7 @@ void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); /* I/O operation functions ******************************************************/ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg); void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg); -void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg); +void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg); /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h index be53965b2d..344a784773 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h @@ -368,9 +368,13 @@ extern "C" { #define VREFINT_CAL_VREF ( 3000U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ /* Temperature sensor */ #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature defined by TEMPSENSOR_CAL2_TEMP (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) #define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#else +#define TEMPSENSOR_CAL2_TEMP (( int32_t) 130) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#endif #define TEMPSENSOR_CAL_VREFANALOG ( 3000U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ @@ -2130,7 +2134,7 @@ typedef struct * @brief Helper macro to convert the ADC conversion data from * a resolution to another resolution. * @param __DATA__ ADC conversion data to be converted - * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted + * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted * This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B @@ -2296,7 +2300,7 @@ typedef struct * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @note ADC measurement data must correspond to a resolution of 12bits + * @note ADC measurement data must correspond to a resolution of 12 bits * (full scale digital value 4095). If not the case, the data must be * preliminarily rescaled to an equivalent resolution of 12 bits. * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). @@ -2404,6 +2408,9 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Regis #else __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) { + /* Prevent unused argument(s) compilation warning */ + (void)(Register); + /* Retrieve address of register DR */ return (uint32_t)&(ADCx->DR); } @@ -2501,12 +2508,6 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) * For ADC conversion of internal channels, * a sampling time minimum value is required. * Refer to device datasheet. - * @note On this STM32 serie, setting of this feature is conditioned to - * ADC state: - * All ADC instances of the ADC common group must be disabled. - * This check can be done with function @ref LL_ADC_IsEnabled() for each - * ADC instance or by using helper macro helper macro - * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n * CCR TSEN LL_ADC_SetCommonPathInternalCh\n * CCR VBATEN LL_ADC_SetCommonPathInternalCh @@ -3193,7 +3194,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) /** * @brief Get ADC group regular conversion trigger source internal (SW start) - or external. + * or external. * @note In case of group regular trigger source set to external trigger, * to determine which peripheral is selected as external trigger, * use function @ref LL_ADC_REG_GetTriggerSource(). @@ -3204,7 +3205,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)); + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)); } /** @@ -3938,7 +3939,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)); + return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)); } /** @@ -4552,6 +4553,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, /* because containing other bits reserved for other purpose. */ /* If parameter "TriggerSource" is set to SW start, then parameter */ /* "ExternalTriggerEdge" is discarded. */ + register uint32_t is_trigger_not_sw = (uint32_t)(TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE); MODIFY_REG(ADCx->JSQR , ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | @@ -4561,7 +4563,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, ADC_JSQR_JSQ1 | ADC_JSQR_JL , TriggerSource | - (ExternalTriggerEdge * ((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE))) | + (ExternalTriggerEdge * (is_trigger_not_sw)) | (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) | (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) | (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) | @@ -5938,7 +5940,7 @@ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)); + return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)); } /** @@ -5987,7 +5989,7 @@ __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)); + return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)); } /** @@ -6047,7 +6049,7 @@ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)); + return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)); } /** @@ -6058,7 +6060,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)); + return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)); } /** @@ -6102,7 +6104,7 @@ __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleD */ __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)); + return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)); } /** @@ -6169,7 +6171,7 @@ __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)); + return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)); } /** @@ -6180,7 +6182,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)); + return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)); } /** @@ -6352,7 +6354,7 @@ __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)); + return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)); } /** @@ -6363,7 +6365,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)); + return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)); } /** @@ -6539,7 +6541,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32 */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)); + return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)); } /** @@ -6550,7 +6552,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)); + return (uint32_t)(READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)); } /** @@ -6561,7 +6563,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)); + return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)); } /** @@ -6572,7 +6574,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)); + return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)); } /** @@ -6583,7 +6585,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)); + return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)); } /** @@ -6594,7 +6596,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)); + return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)); } /** @@ -6605,7 +6607,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)); + return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)); } /** @@ -6616,7 +6618,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)); + return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)); } /** @@ -6627,7 +6629,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); + return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); } /** @@ -6638,7 +6640,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)); + return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)); } /** @@ -6649,7 +6651,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)); + return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)); } /** @@ -6786,7 +6788,7 @@ __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)); + return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)); } /** @@ -6798,7 +6800,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)); + return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)); } /** @@ -6810,7 +6812,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)); + return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)); } /** @@ -6822,7 +6824,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_C */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)); + return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)); } /** @@ -6834,7 +6836,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_C */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)); + return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)); } /** @@ -6846,7 +6848,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_C */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)); + return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)); } /** @@ -6858,7 +6860,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_C */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)); + return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)); } /** @@ -6870,7 +6872,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_C */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)); + return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)); } /** @@ -6882,7 +6884,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_C */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)); + return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)); } /** @@ -6894,7 +6896,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)); + return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)); } /** @@ -6906,7 +6908,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)); + return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)); } /** @@ -6918,7 +6920,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)); + return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)); } /** @@ -6930,7 +6932,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)); + return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)); } /** @@ -6942,7 +6944,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)); + return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)); } /** @@ -6954,7 +6956,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)); + return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)); } /** @@ -6966,7 +6968,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)); + return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)); } /** @@ -6978,7 +6980,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)); + return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)); } /** @@ -6990,7 +6992,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)); + return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)); } /** @@ -7002,7 +7004,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)); + return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)); } /** @@ -7014,7 +7016,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)); + return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)); } /** @@ -7026,7 +7028,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)); + return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)); } /** @@ -7038,7 +7040,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)); + return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)); } #endif /* ADC_MULTIMODE_SUPPORT */ @@ -7301,7 +7303,7 @@ __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)); + return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)); } /** @@ -7313,7 +7315,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)); + return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)); } /** @@ -7325,7 +7327,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)); + return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)); } /** @@ -7337,7 +7339,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)); + return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)); } /** @@ -7349,7 +7351,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)); + return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)); } /** @@ -7361,7 +7363,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)); + return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)); } /** @@ -7373,7 +7375,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)); + return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)); } /** @@ -7385,7 +7387,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)); + return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)); } /** @@ -7397,7 +7399,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)); + return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)); } /** @@ -7409,7 +7411,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)); + return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)); } /** @@ -7421,7 +7423,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)); + return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)); } /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h index 69f123b449..0b08bfaaa2 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h @@ -4,17 +4,17 @@ * @author MCD Application Team * @brief Header file of BUS LL module. - @verbatim + @verbatim ##### RCC Limitations ##### ============================================================================== - [..] - A delay between an RCC peripheral clock enable and the effective peripheral - enabling should be taken into account in order to manage the peripheral read/write + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write from/to registers. (+) This delay depends on the peripheral mapping. (++) AHB & APB peripherals, 1 dummy read is necessary - [..] + [..] Workarounds: (#) For AHB & APB peripherals, a dummy read to the peripheral register has been inserted in each LL_{BUS}_GRP{x}_EnableClock() function. @@ -325,7 +325,7 @@ extern "C" { * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GFXMMUEN LL_AHB1_GRP1_EnableClock + * AHB1ENR GFXMMUEN LL_AHB1_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 @@ -357,7 +357,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GFXMMUEN LL_AHB1_GRP1_IsEnabledClock + * AHB1ENR GFXMMUEN LL_AHB1_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 @@ -385,7 +385,7 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GFXMMUEN LL_AHB1_GRP1_DisableClock + * AHB1ENR GFXMMUEN LL_AHB1_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 @@ -412,8 +412,8 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) * AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n * AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ForceReset + * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 @@ -441,8 +441,8 @@ __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) * AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n * AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ReleaseReset + * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ReleaseReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_comp.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_comp.h index fc2426c648..d9e204422e 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_comp.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_comp.h @@ -875,6 +875,10 @@ void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct); * @} */ +/** + * @} + */ + #endif /* COMP1 || COMP2 */ /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crc.h index 0a5ff00ec5..5ffdd64e27 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crc.h @@ -444,7 +444,7 @@ __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) #if (CRC_IDR_IDR == 0x0FFU) *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData; #else - WRITE_REG(CRCx->IDR, InData); + WRITE_REG(CRCx->IDR, InData); #endif } /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dac.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dac.h index f16bf9adae..eb45ab695f 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dac.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dac.h @@ -861,7 +861,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha } /** - * @brief Set the noise waveform generation for the selected DAC channel: + * @brief Get the noise waveform generation for the selected DAC channel: * Noise mode and parameters LFSR (linear feedback shift register). * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n * CR MAMP2 LL_DAC_GetWaveNoiseLFSR @@ -933,7 +933,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t } /** - * @brief Set the triangle waveform generation for the selected DAC channel: + * @brief Get the triangle waveform generation for the selected DAC channel: * triangle mode and amplitude. * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma2d.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma2d.h index 6c7e20a497..46a5bf41a2 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma2d.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma2d.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_DMA2D_H -#define __STM32L4xx_LL_DMA2D_H +#ifndef STM32L4xx_LL_DMA2D_H +#define STM32L4xx_LL_DMA2D_H #ifdef __cplusplus extern "C" { @@ -148,7 +148,8 @@ typedef struct #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ uint32_t LineOffset; /*!< Specifies the output line offset value. - - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF on STM32L496xx/STM32L4A6xx + - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF on devices + where the Line Offset Mode feature is available. else between Min_Data = 0x0000 and Max_Data = 0xFFFF on other devices. This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */ @@ -271,6 +272,7 @@ typedef struct - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer, - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */ + } LL_DMA2D_LayerCfgTypeDef; /** @@ -422,7 +424,7 @@ typedef struct /** @defgroup DMA2D_LL_EC_OUTPUT_SWAP_MODE Swap Mode * @{ */ -#define LL_DMA2D_SWAP_MODE_REGULAR ((uint32_t)0x00000000) /*!< Regular order */ +#define LL_DMA2D_SWAP_MODE_REGULAR 0x00000000U /*!< Regular order */ #define LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB /*!< Bytes swapped two by two */ /** * @} @@ -447,11 +449,12 @@ typedef struct * @} */ + #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) /** @defgroup DMA2D_LL_EC_LINE_OFFSET_MODE Line Offset Mode * @{ */ -#define LL_DMA2D_LINE_OFFSET_PIXELS ((uint32_t)0x00000000) /*!< Line offsets are expressed in pixels */ +#define LL_DMA2D_LINE_OFFSET_PIXELS 0x00000000U /*!< Line offsets are expressed in pixels */ #define LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM /*!< Line offsets are expressed in bytes */ /** * @} @@ -467,6 +470,7 @@ typedef struct * @} */ + /** * @} */ @@ -487,7 +491,7 @@ typedef struct * @param __VALUE__ Value to be written in the register * @retval None */ -#define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) +#define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) /** * @brief Read a value in DMA2D register. @@ -495,7 +499,7 @@ typedef struct * @param __REG__ Register to be read * @retval Register value */ -#define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +#define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) /** * @} */ @@ -532,7 +536,7 @@ __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)); + return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)); } /** @@ -569,7 +573,7 @@ __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)); + return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)); } /** @@ -594,7 +598,7 @@ __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)); + return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)); } /** @@ -723,6 +727,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx) return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI)); } + #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) /** * @brief Set DMA2D output swap mode. @@ -995,7 +1000,7 @@ __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)); + return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)); } /** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions @@ -1044,7 +1049,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)); + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)); } /** @@ -1430,7 +1435,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)); + return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)); } /** @@ -1787,7 +1792,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)); + return (uint32_t)(READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)); } /** @@ -1798,7 +1803,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)); + return (uint32_t)(READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)); } /** @@ -1809,7 +1814,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)); + return (uint32_t)(READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)); } /** @@ -1820,7 +1825,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)); + return (uint32_t)(READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)); } /** @@ -1831,7 +1836,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)); + return (uint32_t)(READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)); } /** @@ -1842,7 +1847,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)); + return (uint32_t)(READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)); } /** @@ -2059,7 +2064,7 @@ __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)); + return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)); } /** @@ -2070,7 +2075,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)); + return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)); } /** @@ -2081,7 +2086,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)); + return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)); } /** @@ -2092,7 +2097,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)); + return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)); } /** @@ -2103,7 +2108,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)); + return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)); } /** @@ -2114,7 +2119,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)); + return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)); } @@ -2163,6 +2168,6 @@ void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t Nb } #endif -#endif /* __STM32L4xx_LL_DMA2D_H */ +#endif /* STM32L4xx_LL_DMA2D_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_fmc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_fmc.h index c338614944..0ccb7677f4 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_fmc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_fmc.h @@ -48,8 +48,6 @@ extern "C" { * @{ */ -#if defined(FMC_BANK1) - /** @addtogroup FMC_LL * @{ */ @@ -57,215 +55,94 @@ extern "C" { /** @addtogroup FMC_LL_Private_Macros * @{ */ +#if defined(FMC_BANK1) -#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ - ((__BANK__) == FMC_NORSRAM_BANK2) || \ - ((__BANK__) == FMC_NORSRAM_BANK3) || \ - ((__BANK__) == FMC_NORSRAM_BANK4)) - -#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ - ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) - -#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ - ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ - ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) - -#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ - ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) - -#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ - ((__BURST__) == FMC_WRITE_BURST_ENABLE)) - -#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ - ((__SIZE__) == FMC_PAGE_SIZE_128) || \ - ((__SIZE__) == FMC_PAGE_SIZE_256) || \ - ((__SIZE__) == FMC_PAGE_SIZE_512) || \ - ((__SIZE__) == FMC_PAGE_SIZE_1024)) - -#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ - ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) - +#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ + ((__BANK__) == FMC_NORSRAM_BANK2) || \ + ((__BANK__) == FMC_NORSRAM_BANK3) || \ + ((__BANK__) == FMC_NORSRAM_BANK4)) +#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ + ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) +#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ + ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM) || \ + ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) +#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ + ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) +#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ + ((__SIZE__) == FMC_PAGE_SIZE_128) || \ + ((__SIZE__) == FMC_PAGE_SIZE_256) || \ + ((__SIZE__) == FMC_PAGE_SIZE_512) || \ + ((__SIZE__) == FMC_PAGE_SIZE_1024)) #if defined(FMC_BCR1_WFDIS) -#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ - ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) +#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ + ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) #endif /* FMC_BCR1_WFDIS */ - +#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ + ((__MODE__) == FMC_ACCESS_MODE_B) || \ + ((__MODE__) == FMC_ACCESS_MODE_C) || \ + ((__MODE__) == FMC_ACCESS_MODE_D)) #if defined(FMC_BCRx_NBLSET) -#define IS_FMC_NBLSETUP_TIME(__TIME__) ((__TIME__) <= 3) +#define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \ + ((__NBL__) == FMC_NBL_SETUPTIME_1) || \ + ((__NBL__) == FMC_NBL_SETUPTIME_2) || \ + ((__NBL__) == FMC_NBL_SETUPTIME_3)) #endif /* FMC_BCRx_NBLSET */ - -#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ - ((__MODE__) == FMC_ACCESS_MODE_B) || \ - ((__MODE__) == FMC_ACCESS_MODE_C) || \ - ((__MODE__) == FMC_ACCESS_MODE_D)) - -#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) - -#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ - ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) - -#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) - -#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ - ((__STATE__) == FMC_NAND_ECC_ENABLE)) - -#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ - ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ - ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ - ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ - ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ - ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) - -/** @defgroup FMC_TCLR_Setup_Time FMC_TCLR_Setup_Time - * @{ - */ -#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255) -/** - * @} - */ - -/** @defgroup FMC_TAR_Setup_Time FMC_TAR_Setup_Time - * @{ - */ -#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255) -/** - * @} - */ - -/** @defgroup FMC_Setup_Time FMC_Setup_Time - * @{ - */ -#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255) -/** - * @} - */ - -/** @defgroup FMC_Wait_Setup_Time FMC_Wait_Setup_Time - * @{ - */ -#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255) -/** - * @} - */ - -/** @defgroup FMC_Hold_Setup_Time FMC_Hold_Setup_Time - * @{ - */ -#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255) -/** - * @} - */ - -/** @defgroup FMC_HiZ_Setup_Time FMC_HiZ_Setup_Time - * @{ - */ -#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255) -/** - * @} - */ - -/** @defgroup FMC_NORSRAM_Device_Instance FMC NOR/SRAM Device Instance - * @{ - */ - -#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) - -/** - * @} - */ - -/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NOR/SRAM EXTENDED Device Instance - * @{ - */ - +#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ + ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) +#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ + ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) +#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ + ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) +#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ + ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) +#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ + ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) +#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ + ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) +#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ + ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) +#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) +#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ + ((__BURST__) == FMC_WRITE_BURST_ENABLE)) +#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ + ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) +#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) +#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) +#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) +#if defined(FMC_BTRx_DATAHLD) +#define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3) +#endif /* FMC_BTRx_DATAHLD */ +#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) +#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16)) +#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) -/** - * @} - */ - -/** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance - * @{ - */ -#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) -/** - * @} - */ - -#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ - ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) - -#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ - ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) - -#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ - ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) - -#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ - ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) - -#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ - ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) - -#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ - ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) - -#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ - ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) - -#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16)) - -/** @defgroup FMC_Data_Latency FMC Data Latency - * @{ - */ -#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) -/** - * @} - */ - -/** @defgroup FMC_Address_Setup_Time FMC Address Setup Time - * @{ - */ -#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) -/** - * @} - */ +#endif /* FMC_BANK1 */ +#if defined(FMC_BANK3) -/** @defgroup FMC_Address_Hold_Time FMC Address Hold Time - * @{ - */ -#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) -/** - * @} - */ +#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) +#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ + ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) +#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) +#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ + ((__STATE__) == FMC_NAND_ECC_ENABLE)) +#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) +#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255) +#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255) +#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254) +#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254) +#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254) +#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254) +#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) -/** @defgroup FMC_Data_Setup_Time FMC Data Setup Time - * @{ - */ -#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) -/** - * @} - */ - -#if defined(FMC_BTRx_DATAHLD) -/** @defgroup FMC_Data_Hold_Time - * @{ - */ -#define IS_FMC_DATAHOLD_TIME(__TIME__) ((__TIME__) <= 3) -/** - * @} - */ -#endif /* FMC_BTRx_DATAHLD */ - -/** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration - * @{ - */ -#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) -/** - * @} - */ +#endif /* FMC_BANK3 */ /** * @} @@ -273,20 +150,29 @@ extern "C" { /* Exported typedef ----------------------------------------------------------*/ -/** @defgroup FMC_NORSRAM_Exported_typedef FMC Low Layer Exported Types +/** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types * @{ */ -#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef -#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef -#define FMC_NAND_TypeDef FMC_Bank3_TypeDef +#if defined(FMC_BANK1) +#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef +#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef +#endif /* FMC_BANK1 */ +#if defined(FMC_BANK3) +#define FMC_NAND_TypeDef FMC_Bank3_TypeDef +#endif /* FMC_BANK3 */ -#define FMC_NORSRAM_DEVICE FMC_Bank1_R -#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R -#define FMC_NAND_DEVICE FMC_Bank3_R +#if defined(FMC_BANK1) +#define FMC_NORSRAM_DEVICE FMC_Bank1_R +#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R +#endif /* FMC_BANK1 */ +#if defined(FMC_BANK3) +#define FMC_NAND_DEVICE FMC_Bank3_R +#endif /* FMC_BANK3 */ +#if defined(FMC_BANK1) /** - * @brief FMC_NORSRAM Configuration Structure definition + * @brief FMC NORSRAM Configuration Structure definition */ typedef struct { @@ -345,19 +231,18 @@ typedef struct This parameter can be a value of @ref FMC_Write_FIFO. @note This Parameter is not available for STM32L47x/L48x devices. */ + uint32_t PageSize; /*!< Specifies the memory page size. + This parameter can be a value of @ref FMC_Page_Size */ + #if defined(FMC_BCRx_NBLSET) - uint32_t NBLSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the byte lane (NBL) setup time from NBLx low to Chip select NEx low. - This parameter can be a value between Min_Data = 0 and Max_Data = 3. - @note This parameter is used for SRAMs, ROMs and NOR Flash memories. */ + uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number + This parameter can be a value of @ref FMC_Byte_Lane */ #endif /* FMC_BCRx_NBLSET */ - uint32_t PageSize; /*!< Specifies the memory page size. - This parameter can be a value of @ref FMC_Page_Size */ }FMC_NORSRAM_InitTypeDef; /** - * @brief FMC_NORSRAM Timing parameters structure definition + * @brief FMC NORSRAM Timing parameters structure definition */ typedef struct { @@ -381,10 +266,7 @@ typedef struct uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure the duration of the data hold time. This parameter can be a value between Min_Data = 0 and Max_Data = 3. - @note This parameter value corresponds to x HCLK cycles for read and - x+1 HCLK cycles for write. - @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed - NOR Flash memories. */ + @note This parameter is used for used in asynchronous accesses. */ #endif /* FMC_BTRx_DATAHLD */ uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure @@ -407,11 +289,12 @@ typedef struct uint32_t AccessMode; /*!< Specifies the asynchronous access mode. This parameter can be a value of @ref FMC_Access_Mode */ - }FMC_NORSRAM_TimingTypeDef; +#endif /* FMC_BANK1 */ +#if defined(FMC_BANK3) /** - * @brief FMC_NAND Configuration Structure definition + * @brief FMC NAND Configuration Structure definition */ typedef struct { @@ -437,11 +320,10 @@ typedef struct uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ - }FMC_NAND_InitTypeDef; /** - * @brief FMC_NAND Timing parameters structure definition + * @brief FMC NAND Timing parameters structure definition */ typedef struct { @@ -449,51 +331,50 @@ typedef struct the command assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). - This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ + This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the command for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address (and data for write access) after the command de-assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the data bus is kept in HiZ after the start of a NAND-Flash write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ - + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ }FMC_NAND_PCC_TimingTypeDef; +#endif /* FMC_BANK3 */ /** * @} */ /* Exported constants --------------------------------------------------------*/ - -/** @defgroup FMC_Exported_Constants FMC Low Layer Exported Constants +/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants * @{ */ +#if defined(FMC_BANK1) -/** @defgroup FMC_NORSRAM_Exported_constants FMC NOR/SRAM Exported constants +/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller * @{ */ /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank * @{ */ -#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000) -#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002) -#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004) -#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006) - +#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U) +#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U) +#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U) +#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U) /** * @} */ @@ -501,10 +382,8 @@ typedef struct /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing * @{ */ - -#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) +#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U) #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FMC_BCRx_MUXEN) - /** * @} */ @@ -512,11 +391,9 @@ typedef struct /** @defgroup FMC_Memory_Type FMC Memory Type * @{ */ - -#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) +#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U) #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)FMC_BCRx_MTYP_0) #define FMC_MEMORY_TYPE_NOR ((uint32_t)FMC_BCRx_MTYP_1) - /** * @} */ @@ -524,11 +401,9 @@ typedef struct /** @defgroup FMC_NORSRAM_Data_Width FMC NOR/SRAM Data Width * @{ */ - -#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) +#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FMC_BCRx_MWID_0) #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FMC_BCRx_MWID_1) - /** * @} */ @@ -536,9 +411,8 @@ typedef struct /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access * @{ */ - #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FMC_BCRx_FACCEN) -#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) +#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -546,26 +420,17 @@ typedef struct /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode * @{ */ - -#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) +#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U) #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FMC_BCRx_BURSTEN) - /** * @} */ - /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity * @{ */ - -#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) +#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U) #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FMC_BCRx_WAITPOL) - -/** - * @} - */ - /** * @} */ @@ -573,10 +438,8 @@ typedef struct /** @defgroup FMC_Wait_Timing FMC Wait Timing * @{ */ - -#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) +#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U) #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)FMC_BCRx_WAITCFG) - /** * @} */ @@ -584,10 +447,8 @@ typedef struct /** @defgroup FMC_Write_Operation FMC Write Operation * @{ */ - -#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) +#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U) #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)FMC_BCRx_WREN) - /** * @} */ @@ -595,10 +456,8 @@ typedef struct /** @defgroup FMC_Wait_Signal FMC Wait Signal * @{ */ - -#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) +#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U) #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)FMC_BCRx_WAITEN) - /** * @} */ @@ -606,10 +465,8 @@ typedef struct /** @defgroup FMC_Extended_Mode FMC Extended Mode * @{ */ - -#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) +#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U) #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)FMC_BCRx_EXTMOD) - /** * @} */ @@ -617,10 +474,8 @@ typedef struct /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait * @{ */ - -#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) +#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U) #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FMC_BCRx_ASYNCWAIT) - /** * @} */ @@ -628,7 +483,7 @@ typedef struct /** @defgroup FMC_Page_Size FMC Page Size * @{ */ -#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000) +#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U) #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0) #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1) #define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1)) @@ -640,18 +495,16 @@ typedef struct /** @defgroup FMC_Write_Burst FMC Write Burst * @{ */ - -#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) +#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U) #define FMC_WRITE_BURST_ENABLE ((uint32_t)FMC_BCRx_CBURSTRW) - /** * @} */ -/** @defgroup FMC_Continous_Clock FMC Continous Clock +/** @defgroup FMC_Continous_Clock FMC Continuous Clock * @{ */ -#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000) +#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U) #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)FMC_BCR1_CCLKEN) /** * @} @@ -662,17 +515,16 @@ typedef struct * @{ */ #define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS) -#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000) +#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U) /** * @} */ - #endif /* FMC_BCR1_WFDIS */ + /** @defgroup FMC_Access_Mode FMC Access Mode * @{ */ - -#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000) +#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U) #define FMC_ACCESS_MODE_B ((uint32_t)FMC_BTRx_ACCMOD_0) #define FMC_ACCESS_MODE_C ((uint32_t)FMC_BTRx_ACCMOD_1) #define FMC_ACCESS_MODE_D ((uint32_t)(FMC_BTRx_ACCMOD_0 | FMC_BTRx_ACCMOD_1)) @@ -680,20 +532,33 @@ typedef struct /** * @} */ +#if defined(FMC_BCRx_NBLSET) +/** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup + * @{ + */ +#define FMC_NBL_SETUPTIME_0 ((uint32_t)0x00000000U) +#define FMC_NBL_SETUPTIME_1 ((uint32_t)FMC_BCRx_NBLSET_0) +#define FMC_NBL_SETUPTIME_2 ((uint32_t)FMC_BCRx_NBLSET_1) +#define FMC_NBL_SETUPTIME_3 ((uint32_t)(FMC_BCRx_NBLSET_0 | FMC_BCRx_NBLSET_1)) +/** + * @} + */ +#endif /* FMC_BCRx_NBLSET */ /** * @} */ +#endif /* FMC_BANK1 */ + +#if defined(FMC_BANK3) -/** @defgroup FMC_NAND_Controller FMC NAND and PCCARD Controller +/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller * @{ */ - /** @defgroup FMC_NAND_Bank FMC NAND Bank * @{ */ -#define FMC_NAND_BANK3 ((uint32_t)0x00000100) - +#define FMC_NAND_BANK3 ((uint32_t)0x00000100U) /** * @} */ @@ -701,9 +566,8 @@ typedef struct /** @defgroup FMC_Wait_feature FMC Wait feature * @{ */ -#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000) +#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U) #define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)FMC_PCR_PWAITEN) - /** * @} */ @@ -711,7 +575,7 @@ typedef struct /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type * @{ */ -#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FMC_PCR_PTYP) +#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FMC_PCR_PTYP) /** * @} */ @@ -719,19 +583,17 @@ typedef struct /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width * @{ */ -#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) +#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) #define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)FMC_PCR_PWID_0) - /** * @} */ -/** @defgroup FMC_ECC FMC NAND ECC +/** @defgroup FMC_ECC FMC ECC * @{ */ -#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) +#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U) #define FMC_NAND_ECC_ENABLE ((uint32_t)FMC_PCR_ECCEN) - /** * @} */ @@ -739,42 +601,46 @@ typedef struct /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size * @{ */ -#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000) +#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U) #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FMC_PCR_ECCPS_0) #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FMC_PCR_ECCPS_1) #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_1) #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FMC_PCR_ECCPS_2) #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_2) +/** + * @} + */ /** * @} */ +#endif /* FMC_BANK3 */ -/** @defgroup FMC_Interrupt_definition FMC Interrupt definition - * @brief FMC Interrupt definition + +/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition * @{ */ +#if defined(FMC_BANK3) #define FMC_IT_RISING_EDGE ((uint32_t)FMC_SR_IREN) #define FMC_IT_LEVEL ((uint32_t)FMC_SR_ILEN) #define FMC_IT_FALLING_EDGE ((uint32_t)FMC_SR_IFEN) - +#endif /* FMC_BANK3 */ /** * @} */ -/** @defgroup FMC_Flag_definition FMC Flag definition - * @brief FMC Flag definition +/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition * @{ */ +#if defined(FMC_BANK3) #define FMC_FLAG_RISING_EDGE ((uint32_t)FMC_SR_IRS) #define FMC_FLAG_LEVEL ((uint32_t)FMC_SR_ILS) #define FMC_FLAG_FALLING_EDGE ((uint32_t)FMC_SR_IFS) #define FMC_FLAG_FEMPT ((uint32_t)FMC_SR_FEMPT) - +#endif /* FMC_BANK3 */ /** * @} */ - /** * @} */ @@ -783,13 +649,13 @@ typedef struct * @} */ -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup FMC_Exported_Macros FMC Low Layer Exported Macros +/* Private macro -------------------------------------------------------------*/ +/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros * @{ */ -/** @defgroup FMC_NOR_Macros FMC NOR/SRAM Exported Macros +#if defined(FMC_BANK1) +/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros * @brief macros to handle NOR device enable/disable and read/write operations * @{ */ @@ -798,23 +664,25 @@ typedef struct * @brief Enable the NORSRAM device access. * @param __INSTANCE__ FMC_NORSRAM Instance * @param __BANK__ FMC_NORSRAM Bank - * @retval none + * @retval None */ -#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN) +#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCRx_MBKEN) /** * @brief Disable the NORSRAM device access. * @param __INSTANCE__ FMC_NORSRAM Instance * @param __BANK__ FMC_NORSRAM Bank - * @retval none + * @retval None */ -#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN) +#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCRx_MBKEN) /** * @} */ +#endif /* FMC_BANK1 */ -/** @defgroup FMC_NAND_Macros FMC NAND Macros +#if defined(FMC_BANK3) +/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros * @brief macros to handle NAND device enable/disable * @{ */ @@ -822,32 +690,29 @@ typedef struct /** * @brief Enable the NAND device access. * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank * @retval None */ -#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) +#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) /** * @brief Disable the NAND device access. * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank * @retval None */ -#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) +#define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN) /** * @} */ -/** @defgroup FMC_Interrupt FMC Interrupt - * @brief macros to handle FMC interrupts +/** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt + * @brief macros to handle NAND interrupts * @{ */ /** * @brief Enable the NAND device interrupt. - * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank + * @param __INSTANCE__ FMC_NAND instance * @param __INTERRUPT__ FMC_NAND interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_RISING_EDGE Interrupt rising edge. @@ -855,12 +720,11 @@ typedef struct * @arg FMC_IT_FALLING_EDGE Interrupt falling edge. * @retval None */ -#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR, (__INTERRUPT__)) +#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) /** * @brief Disable the NAND device interrupt. * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank * @param __INTERRUPT__ FMC_NAND interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_RISING_EDGE Interrupt rising edge. @@ -868,7 +732,7 @@ typedef struct * @arg FMC_IT_FALLING_EDGE Interrupt falling edge. * @retval None */ -#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR, (__INTERRUPT__)) +#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) /** * @brief Get flag status of the NAND device. @@ -887,7 +751,6 @@ typedef struct /** * @brief Clear flag status of the NAND device. * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank * @param __FLAG__ FMC_NAND flag * This parameter can be any combination of the following values: * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag. @@ -896,93 +759,84 @@ typedef struct * @arg FMC_FLAG_FEMPT FIFO empty flag. * @retval None */ -#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR, (__FLAG__)) +#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) /** * @} */ - +#endif /* FMC_BANK3 */ /** * @} */ -/* Exported functions --------------------------------------------------------*/ +/** + * @} + */ -/** @addtogroup FMC_LL_Exported_Functions +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions * @{ */ -/** @addtogroup FMC_NORSRAM +#if defined(FMC_BANK1) +/** @defgroup FMC_LL_NORSRAM NOR SRAM * @{ */ - -/** @addtogroup FMC_NORSRAM_Group1 +/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions * @{ */ - -/* FMC_NORSRAM Controller functions ******************************************/ -/* Initialization/de-initialization functions */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init); HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); - /** * @} */ -/** @addtogroup FMC_NORSRAM_Group2 +/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions * @{ */ - -/* FMC_NORSRAM Control functions */ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); - /** * @} */ - /** * @} */ +#endif /* FMC_BANK1 */ -/** @addtogroup FMC_NAND +#if defined(FMC_BANK3) +/** @defgroup FMC_LL_NAND NAND * @{ */ - -/* FMC_NAND Controller functions **********************************************/ -/* Initialization/de-initialization functions */ -/** @addtogroup FMC_NAND_Exported_Functions_Group1 +/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions * @{ */ - HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); - /** * @} */ -/* FMC_NAND Control functions */ -/** @addtogroup FMC_NAND_Exported_Functions_Group2 +/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions * @{ */ - HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); - /** * @} */ - /** * @} */ +#endif /* FMC_BANK3 */ + + /** * @} @@ -992,8 +846,6 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u * @} */ -#endif /* FMC_BANK1 */ - /** * @} */ @@ -1005,4 +857,3 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u #endif /* __STM32L4xx_LL_FMC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_i2c.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_i2c.h index 9c21e423cc..24ed3bc019 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_i2c.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_i2c.h @@ -594,7 +594,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction) { - register uint32_t data_reg_addr = 0U; + register uint32_t data_reg_addr; if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT) { @@ -1097,7 +1097,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) * @retval None */ __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, - uint32_t TimeoutB) + uint32_t TimeoutB) { MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB, TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos)); @@ -2104,11 +2104,11 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) * @retval None */ __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, - uint32_t TransferSize, uint32_t EndMode, uint32_t Request) + uint32_t TransferSize, uint32_t EndMode, uint32_t Request) { MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, - SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request); + SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request); } /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lptim.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lptim.h index 59e60013d3..38eca67b59 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lptim.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lptim.h @@ -1030,7 +1030,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) } /** - * @brief Inform application whether a autoreload match interrupt has occured. + * @brief Inform application whether a autoreload match interrupt has occurred. * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lpuart.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lpuart.h index 0176ba7f4f..0c31281bb5 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lpuart.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lpuart.h @@ -169,7 +169,7 @@ typedef struct */ #define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */ #define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */ -#define LL_LPUART_ICR_NCF USART_ICR_NCF /*!< Noise detected flag */ +#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected flag */ #define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ #define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ #if defined(USART_CR1_FIFOEN) @@ -488,15 +488,14 @@ typedef struct * @arg @ref LL_LPUART_PRESCALER_DIV64 * @arg @ref LL_LPUART_PRESCALER_DIV128 * @arg @ref LL_LPUART_PRESCALER_DIV256 - * @param __PRESCALER__ Prescaler value @endif * @param __BAUDRATE__ Baud Rate value to achieve * @retval LPUARTDIV value to be used for BRR register filling */ #if defined(USART_PRESC_PRESCALER) -#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(__PRESCALER__)]))*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK) +#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(__PRESCALER__)]))*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) #else -#define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK) +#define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) #endif /** @@ -725,6 +724,43 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx) return (READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)); } +#if defined(USART_CR3_UCESM) +/** + * @brief LPUART Clock enabled in STOP Mode + * @note When this function is called, LPUART Clock is enabled while in STOP mode + * @rmtoll CR3 UCESM LL_LPUART_EnableClockInStopMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableClockInStopMode(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_UCESM); +} + +/** + * @brief LPUART clock disabled in STOP Mode + * @note When this function is called, LPUART Clock is disabled while in STOP mode + * @rmtoll CR3 UCESM LL_LPUART_DisableClockInStopMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableClockInStopMode(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_UCESM); +} + +/** + * @brief Indicate if LPUART clock is enabled in STOP Mode + * @rmtoll CR3 UCESM LL_LPUART_IsClockEnabledInStopMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsClockEnabledInStopMode(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM)); +} + +#endif /* USART_CR3_UCESM */ /** * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx @@ -948,7 +984,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue) { - MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, PrescalerValue); + MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue); } /** @@ -1409,7 +1445,7 @@ __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t Peri #endif { #if defined(USART_PRESC_PRESCALER) - LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate); + LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, (uint16_t)PrescalerValue, BaudRate); #else LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate); #endif @@ -1448,7 +1484,7 @@ __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t register uint32_t lpuartdiv = 0x0U; register uint32_t brrresult = 0x0U; #if defined(USART_PRESC_PRESCALER) - register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[PrescalerValue])); + register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue])); #endif lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK; @@ -1684,7 +1720,6 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE @@ -1724,7 +1759,6 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF @@ -1852,7 +1886,6 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Check if the LPUART TX FIFO Empty Flag is set or not * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE @@ -1922,13 +1955,13 @@ __STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx) /** * @brief Clear Noise detected Flag - * @rmtoll ICR NCF LL_LPUART_ClearFlag_NE + * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx) { - WRITE_REG(LPUARTx->ICR, USART_ICR_NCF); + WRITE_REG(LPUARTx->ICR, USART_ICR_NECF); } /** @@ -1954,7 +1987,6 @@ __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Clear TX FIFO Empty Flag * @rmtoll ICR TXFECF LL_LPUART_ClearFlag_TXFE @@ -2031,7 +2063,6 @@ __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE @@ -2071,7 +2102,6 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF @@ -2122,7 +2152,6 @@ __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Enable TX FIFO Empty Interrupt * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE @@ -2184,7 +2213,6 @@ __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Enable TX FIFO Threshold Interrupt * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT @@ -2220,7 +2248,6 @@ __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE @@ -2260,7 +2287,6 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF @@ -2311,7 +2337,6 @@ __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Disable TX FIFO Empty Interrupt * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE @@ -2373,7 +2398,6 @@ __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Disable TX FIFO Threshold Interrupt * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT @@ -2409,7 +2433,6 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE @@ -2449,7 +2472,6 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF @@ -2498,8 +2520,8 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx) { return (READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)); } -#if defined(USART_CR1_FIFOEN) +#if defined(USART_CR1_FIFOEN) /** * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE @@ -2557,7 +2579,6 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT @@ -2705,12 +2726,12 @@ __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32 if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT) { /* return address of TDR register */ - data_reg_addr = (uint32_t) &(LPUARTx->TDR); + data_reg_addr = (uint32_t) & (LPUARTx->TDR); } else { /* return address of RDR register */ - data_reg_addr = (uint32_t) &(LPUARTx->RDR); + data_reg_addr = (uint32_t) & (LPUARTx->RDR); } return data_reg_addr; diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h index 4501451d96..bf732f43d6 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h @@ -153,6 +153,14 @@ typedef struct #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ #endif /* HSI48_VALUE */ #endif /* RCC_HSI48_SUPPORT */ + +#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) +#define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */ +#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ + +#if !defined (EXTERNAL_SAI2_CLOCK_VALUE) +#define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz */ +#endif /* EXTERNAL_SAI2_CLOCK_VALUE */ /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rtc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rtc.h index 496279b3db..98f992311e 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rtc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rtc.h @@ -1158,10 +1158,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) */ __STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU)); - return (uint32_t)((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)); + return ((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos); } /** @@ -1196,10 +1193,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) */ __STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)); - return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)); + return ((READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)))>> RTC_TR_MNU_Pos); } /** @@ -1234,10 +1228,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) */ __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)); - return (uint32_t)((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)); + return ((READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU))) >> RTC_TR_SU_Pos); } /** @@ -1430,10 +1421,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) */ __STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU)); - return (uint32_t)((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)); + return ((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos); } /** @@ -1526,10 +1514,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) */ __STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU)); - return (uint32_t)((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)); + return ((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU)))>> RTC_DR_MU_Pos); } /** @@ -1559,10 +1544,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) */ __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU)); - return (uint32_t)((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)); + return ((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos); } /** @@ -1759,10 +1741,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day) */ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU)); - return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_ALRMAR_DT_Pos) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos)); + return ((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos); } /** @@ -1854,10 +1833,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) */ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU)); - return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_ALRMAR_HT_Pos) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_ALRMAR_HU_Pos)); + return ((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos); } /** @@ -1885,10 +1861,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) */ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)); - return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_ALRMAR_MNT_Pos) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_ALRMAR_MNU_Pos)); + return ((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos); } /** @@ -1916,10 +1889,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) */ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); - return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_ALRMAR_ST_Pos) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_ALRMAR_SU_Pos)); + return ((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos); } /** @@ -2137,10 +2107,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) */ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU)); - return (uint32_t)((((temp & RTC_ALRMBR_DT) >> RTC_ALRMBR_DT_Pos) << 4U) | ((temp & RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos)); + return ((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos); } /** @@ -2232,10 +2199,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) */ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU)); - return (uint32_t)((((temp & RTC_ALRMBR_HT) >> RTC_ALRMBR_HT_Pos) << 4U) | ((temp & RTC_ALRMBR_HU) >> RTC_ALRMBR_HU_Pos)); + return ((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos); } /** @@ -2263,10 +2227,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) */ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)); - return (uint32_t)((((temp & RTC_ALRMBR_MNT) >> RTC_ALRMBR_MNT_Pos) << 4U) | ((temp & RTC_ALRMBR_MNU) >> RTC_ALRMBR_MNU_Pos)); + return ((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos); } /** @@ -2294,10 +2255,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) */ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU)); - return (uint32_t)((((temp & RTC_ALRMBR_ST) >> RTC_ALRMBR_ST_Pos) << 4U) | ((temp & RTC_ALRMBR_SU) >> RTC_ALRMBR_SU_Pos)); + return ((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos); } /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_sdmmc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_sdmmc.h index 90681500f5..d7579e2389 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_sdmmc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_sdmmc.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_SDMMC_H -#define __STM32L4xx_LL_SDMMC_H +#ifndef STM32L4xx_LL_SDMMC_H +#define STM32L4xx_LL_SDMMC_H #ifdef __cplusplus extern "C" { @@ -421,9 +421,9 @@ typedef struct */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */ -#define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400) +#define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400U) #else -#define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF) +#define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFFU) #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} @@ -447,7 +447,7 @@ typedef struct /** @defgroup SDMMC_LL_Command_Index Command Index * @{ */ -#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40) +#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U) /** * @} */ @@ -525,7 +525,7 @@ typedef struct /** @defgroup SDMMC_LL_Data_Length Data Lenght * @{ */ -#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) +#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) /** * @} */ @@ -946,7 +946,7 @@ typedef struct * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO * @retval The new state of SDMMC_FLAG (SET or RESET). */ -#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET) +#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) /** @@ -1229,6 +1229,6 @@ uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); } #endif -#endif /* __STM32L4xx_LL_SDMMC_H */ +#endif /* STM32L4xx_LL_SDMMC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_spi.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_spi.h index 78527055bd..a7cf4d52bd 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_spi.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_spi.h @@ -397,7 +397,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)); + return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); } /** @@ -738,7 +738,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)); + return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); } /** @@ -902,7 +902,7 @@ __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)); + return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL); } /** @@ -921,7 +921,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)); + return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); } /** @@ -932,7 +932,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)); + return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); } /** @@ -943,7 +943,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)); + return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); } /** @@ -954,7 +954,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)); + return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); } /** @@ -965,7 +965,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)); + return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); } /** @@ -983,7 +983,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)); + return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); } /** @@ -994,7 +994,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)); + return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); } /** @@ -1170,7 +1170,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)); + return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); } /** @@ -1181,7 +1181,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)); + return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); } /** @@ -1192,7 +1192,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)); + return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); } /** @@ -1233,7 +1233,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)); + return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); } /** @@ -1266,7 +1266,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)); + return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); } /** @@ -1373,7 +1373,12 @@ __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) */ __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) { +#if defined (__GNUC__) + __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR); + *spidr = TxData; +#else *((__IO uint8_t *)&SPIx->DR) = TxData; +#endif } /** @@ -1385,7 +1390,12 @@ __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) */ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) { +#if defined (__GNUC__) + __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR); + *spidr = TxData; +#else *((__IO uint16_t *)&SPIx->DR) = TxData; +#endif } /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_swpmi.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_swpmi.h index b953e9b766..6bef2dfa2c 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_swpmi.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_swpmi.h @@ -48,7 +48,7 @@ extern "C" { * @{ */ -#if defined (SWPMI1) +#if defined(SWPMI1) /** @defgroup SWPMI_LL SWPMI * @{ @@ -1154,7 +1154,7 @@ void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct); * @} */ -#endif /* defined (SWPMI1) */ +#endif /* SWPMI1 */ /** * @} diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_tim.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_tim.h index 1f3565961e..45a01baeb5 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_tim.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_tim.h @@ -127,14 +127,13 @@ static const uint8_t SHIFT_TAB_OISx[] = * @} */ - /* Private constants ---------------------------------------------------------*/ /** @defgroup TIM_LL_Private_Constants TIM Private Constants * @{ */ /* Defines used for the bit position in the register and perform offsets */ -#define TIM_POSITION_BRK_SOURCE POSITION_VAL(Source) +#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FU) /* Generic bit definitions for TIMx_OR2 register */ #define TIMx_OR2_BKINE TIM1_OR2_BKINE /*!< BRK BKIN input enable */ @@ -726,7 +725,7 @@ typedef struct #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!TIMx_CCRy else active.*/ #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/ @@ -782,7 +781,7 @@ typedef struct /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler * @{ */ -#define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */ +#define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */ #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */ #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */ #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */ @@ -1058,7 +1057,9 @@ typedef struct #define LL_TIM_BKIN_SOURCE_BKIN TIM1_OR2_BKINE /*!< BKIN input from AF controller */ #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_OR2_BKCMP1E /*!< internal signal: COMP1 output */ #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_OR2_BKCMP2E /*!< internal signal: COMP2 output */ +#if defined(DFSDM1_Channel0) #define LL_TIM_BKIN_SOURCE_DF1BK TIM1_OR2_BKDF1BK0E /*!< internal signal: DFSDM1 break output */ +#endif /* DFSDM1_Channel0 */ /** * @} */ @@ -1066,7 +1067,7 @@ typedef struct /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY * @{ */ -#define LL_TIM_BKIN_POLARITY_LOW TIM1_OR2_BKINP /*!< BRK BKIN input is active low */ +#define LL_TIM_BKIN_POLARITY_LOW TIM1_OR2_BKINP /*!< BRK BKIN input is active low */ #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */ /** * @} @@ -1322,7 +1323,7 @@ typedef struct * @param __VALUE__ Value to be written in the register * @retval None */ -#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) +#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) /** * @brief Read a value in TIM register. @@ -1330,7 +1331,7 @@ typedef struct * @param __REG__ Register to be read * @retval Register value */ -#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) /** * @} */ @@ -1475,7 +1476,7 @@ __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)); + return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); } /** @@ -1508,7 +1509,7 @@ __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET); + return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); } /** @@ -1578,7 +1579,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) * check whether or not the counter mode selection feature is supported * by a timer instance. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction + * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n * CR1 CMS LL_TIM_SetCounterMode @@ -1593,7 +1594,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) { - MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode); + MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); } /** @@ -1635,7 +1636,7 @@ __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) { - CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); + CLEAR_BIT(TIMx->CR1,TIM_CR1_ARPE); } /** @@ -1646,7 +1647,7 @@ __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)); + return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); } /** @@ -2013,7 +2014,7 @@ __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channe */ __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) { - return (READ_BIT(TIMx->CCER, Channels) == (Channels)); + return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); } /** @@ -2357,7 +2358,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Cha register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; - return (READ_BIT(*pReg, bitfield) == bitfield); + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } /** @@ -2433,7 +2434,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; - return (READ_BIT(*pReg, bitfield) == bitfield); + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } /** @@ -2518,7 +2519,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Ch register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; - return (READ_BIT(*pReg, bitfield) == bitfield); + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } /** @@ -3062,7 +3063,7 @@ __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)); + return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); } /** @@ -3173,7 +3174,7 @@ __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)); + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); } /** @@ -3353,7 +3354,7 @@ __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)); + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); } /** @@ -3598,7 +3599,7 @@ __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)); + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); } /** @@ -3641,7 +3642,7 @@ __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)); + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); } /** @@ -3670,7 +3671,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) { register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); - SET_BIT(*pReg , Source); + SET_BIT(*pReg, Source); } /** @@ -3729,7 +3730,7 @@ __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint3 uint32_t Polarity) { register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); - MODIFY_REG(*pReg, (TIMx_OR2_BKINP << (TIM_POSITION_BRK_SOURCE)) , (Polarity << (TIM_POSITION_BRK_SOURCE))); + MODIFY_REG(*pReg, (TIMx_OR2_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE)); } /** * @} @@ -3793,7 +3794,7 @@ __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint3 */ __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) { - MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength); + MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); } /** @@ -4036,7 +4037,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)); + return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); } /** @@ -4058,7 +4059,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)); + return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); } /** @@ -4080,7 +4081,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)); + return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); } /** @@ -4102,7 +4103,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)); + return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); } /** @@ -4124,7 +4125,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)); + return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); } /** @@ -4146,7 +4147,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)); + return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); } /** @@ -4168,7 +4169,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)); + return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); } /** @@ -4190,7 +4191,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)); + return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); } /** @@ -4212,7 +4213,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)); + return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); } /** @@ -4234,7 +4235,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)); + return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); } /** @@ -4256,7 +4257,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)); + return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); } /** @@ -4278,7 +4279,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)); + return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); } /** @@ -4300,7 +4301,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)); + return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); } /** @@ -4322,7 +4323,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)); + return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); } /** @@ -4344,7 +4345,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)); + return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); } /** @@ -4366,7 +4367,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)); + return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); } /** @@ -4406,7 +4407,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); } /** @@ -4439,7 +4440,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); } /** @@ -4472,7 +4473,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); } /** @@ -4505,7 +4506,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); } /** @@ -4538,7 +4539,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); } /** @@ -4571,7 +4572,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); } /** @@ -4604,7 +4605,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); } /** @@ -4637,7 +4638,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); } /** @@ -4677,7 +4678,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); } /** @@ -4710,7 +4711,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); } /** @@ -4743,7 +4744,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); } /** @@ -4776,7 +4777,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); } /** @@ -4809,7 +4810,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); } /** @@ -4842,7 +4843,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); } /** @@ -4875,7 +4876,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); } /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h index d69431a77c..e1232c9e21 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h @@ -115,8 +115,8 @@ typedef struct This parameter can be a value of @ref USART_LL_EC_PRESCALER. This feature can be modified afterwards using unitary function @ref LL_USART_SetPrescaler().*/ - #endif + uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/ @@ -202,7 +202,7 @@ typedef struct */ #define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */ #define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */ -#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise detected flag */ +#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected flag */ #define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ #define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ #if defined(USART_CR1_FIFOEN) @@ -630,15 +630,14 @@ typedef struct * @arg @ref LL_USART_PRESCALER_DIV64 * @arg @ref LL_USART_PRESCALER_DIV128 * @arg @ref LL_USART_PRESCALER_DIV256 - * @param __PRESCALER__ Prescaler value @endif * @param __BAUDRATE__ Baud rate value to achieve * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case */ #if defined(USART_PRESC_PRESCALER) -#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)]))*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U) + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) #else -#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U) + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) #endif /** @@ -659,15 +658,14 @@ typedef struct * @arg @ref LL_USART_PRESCALER_DIV64 * @arg @ref LL_USART_PRESCALER_DIV128 * @arg @ref LL_USART_PRESCALER_DIV256 - * @param __PRESCALER__ Prescaler value @endif * @param __BAUDRATE__ Baud rate value to achieve * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case */ #if defined(USART_PRESC_PRESCALER) -#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)])) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)])) + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) #else -#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) #endif /** @@ -725,7 +723,6 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief FIFO Mode Enable * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -914,6 +911,43 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx) return (READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)); } +#if defined(USART_CR3_UCESM) +/** + * @brief USART Clock enabled in STOP Mode + * @note When this function is called, USART Clock is enabled while in STOP mode + * @rmtoll CR3 UCESM LL_USART_EnableClockInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableClockInStopMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_UCESM); +} + +/** + * @brief USART clock disabled in STOP Mode + * @note When this function is called, USART Clock is disabled while in STOP mode + * @rmtoll CR3 UCESM LL_USART_DisableClockInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableClockInStopMode(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_UCESM); +} + +/** + * @brief Indicate if USART clock is enabled in STOP Mode + * @rmtoll CR3 UCESM LL_USART_IsClockEnabledInStopMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsClockEnabledInStopMode(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM)); +} + +#endif /* USART_CR3_UCESM */ /** * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) * @rmtoll CR1 RE LL_USART_EnableDirectionRx @@ -1267,7 +1301,6 @@ __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, } #if defined(USART_PRESC_PRESCALER) - /** * @brief Configure Clock source prescaler for baudrate generator and oversampling * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -1291,7 +1324,7 @@ __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, */ __STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) { - MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, PrescalerValue); + MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue); } /** @@ -1962,7 +1995,7 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph if (OverSampling == LL_USART_OVERSAMPLING_8) { #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, PrescalerValue, BaudRate)); + usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint16_t)PrescalerValue, BaudRate)); #else usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); #endif @@ -1973,7 +2006,7 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph else { #if defined(USART_PRESC_PRESCALER) - USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, PrescalerValue, BaudRate)); + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint16_t)PrescalerValue, BaudRate)); #else USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); #endif @@ -2017,7 +2050,7 @@ __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t Pe register uint32_t usartdiv = 0x0U; register uint32_t brrresult = 0x0U; #if defined(USART_PRESC_PRESCALER) - register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (uint32_t)(USART_PRESCALER_TAB[PrescalerValue])); + register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (uint32_t)(USART_PRESCALER_TAB[(uint16_t)PrescalerValue])); #endif usartdiv = USARTx->BRR; @@ -2184,7 +2217,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) { - MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue); + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); } /** @@ -2331,7 +2364,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USAR */ __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) { - MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue); + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); } /** @@ -2429,7 +2462,6 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) */ #if defined(USART_CR2_SLVEN) - /** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature * @{ */ @@ -2441,7 +2473,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval None */ -__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef* USARTx) +__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx) { SET_BIT(USARTx->CR2, USART_CR2_SLVEN); } @@ -2454,7 +2486,7 @@ __STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef* USARTx) * @param USARTx USART Instance * @retval None */ -__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef* USARTx) +__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx) { CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN); } @@ -2467,7 +2499,7 @@ __STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef* USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef* USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)); } @@ -2482,7 +2514,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef* USARTx) * @param USARTx USART Instance * @retval None */ -__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef* USARTx) +__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx) { CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS); } @@ -2496,7 +2528,7 @@ __STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef* USARTx) * @param USARTx USART Instance * @retval None */ -__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef* USARTx) +__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx) { SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS); } @@ -2509,7 +2541,7 @@ __STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef* USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef* USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)); } @@ -3066,7 +3098,6 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE @@ -3108,7 +3139,6 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF @@ -3202,7 +3232,6 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx) } #if defined(USART_CR2_SLVEN) - /** * @brief Check if the SPI Slave Underrun error flag is set or not * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not @@ -3215,8 +3244,8 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx) { return (READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)); } -#endif +#endif /** * @brief Check if the USART Auto-Baud Rate Error Flag is set or not * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not @@ -3323,7 +3352,6 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Check if the USART TX FIFO Empty Flag is set or not * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -3352,7 +3380,6 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx) #endif #if defined(USART_TCBGT_SUPPORT) - /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not @@ -3367,7 +3394,6 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx) #endif #if defined(USART_CR1_FIFOEN) - /** * @brief Check if the USART TX FIFO Threshold Flag is set or not * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -3418,14 +3444,14 @@ __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) } /** - * @brief Clear Noise detected Flag - * @rmtoll ICR NCF LL_USART_ClearFlag_NE + * @brief Clear Noise Error detected Flag + * @rmtoll ICR NECF LL_USART_ClearFlag_NE * @param USARTx USART Instance * @retval None */ __STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) { - WRITE_REG(USARTx->ICR, USART_ICR_NCF); + WRITE_REG(USARTx->ICR, USART_ICR_NECF); } /** @@ -3451,7 +3477,6 @@ __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Clear TX FIFO Empty Flag * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -3478,7 +3503,6 @@ __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) } #if defined(USART_TCBGT_SUPPORT) - /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** * @brief Clear Smartcard Transmission Complete Before Guard Time Flag @@ -3543,7 +3567,6 @@ __STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) } #if defined(USART_CR2_SLVEN) - /** * @brief Clear SPI Slave Underrun Flag * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not @@ -3556,8 +3579,8 @@ __STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx) { WRITE_REG(USARTx->ICR, USART_ICR_UDRCF); } -#endif +#endif /** * @brief Clear Character Match Flag * @rmtoll ICR CMCF LL_USART_ClearFlag_CM @@ -3602,7 +3625,6 @@ __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE @@ -3644,7 +3666,6 @@ __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF @@ -3721,7 +3742,6 @@ __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Enable TX FIFO Empty Interrupt * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -3802,7 +3822,6 @@ __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Enable TX FIFO Threshold Interrupt * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -3818,7 +3837,6 @@ __STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx) #endif #if defined(USART_TCBGT_SUPPORT) - /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt @@ -3835,7 +3853,6 @@ __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) #endif #if defined(USART_CR1_FIFOEN) - /** * @brief Enable RX FIFO Threshold Interrupt * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -3862,7 +3879,6 @@ __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE @@ -3904,7 +3920,6 @@ __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF @@ -3981,7 +3996,6 @@ __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Disable TX FIFO Empty Interrupt * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -4064,7 +4078,6 @@ __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Disable TX FIFO Threshold Interrupt * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -4096,7 +4109,6 @@ __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) #endif #if defined(USART_CR1_FIFOEN) - /** * @brief Disable RX FIFO Threshold Interrupt * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -4123,7 +4135,6 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE @@ -4165,7 +4176,6 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF @@ -4242,7 +4252,6 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -4321,7 +4330,6 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -4337,7 +4345,6 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx) #endif #if defined(USART_TCBGT_SUPPORT) - /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled. @@ -4354,7 +4361,6 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx) #endif #if defined(USART_CR1_FIFOEN) - /** * @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -4493,12 +4499,12 @@ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) { /* return address of TDR register */ - data_reg_addr = (uint32_t) &(USARTx->TDR); + data_reg_addr = (uint32_t) & (USARTx->TDR); } else { /* return address of RDR register */ - data_reg_addr = (uint32_t) &(USARTx->RDR); + data_reg_addr = (uint32_t) & (USARTx->RDR); } return data_reg_addr; @@ -4628,8 +4634,6 @@ __STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) @else * @brief Request a Transmit data flush @endif - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush * @param USARTx USART Instance * @retval None diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h index 3dea361f1b..b899396fda 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32l4xx_ll_usb.h * @author MCD Application Team - * @brief Header file of USB Core HAL module. + * @brief Header file of USB Low Layer HAL module. ****************************************************************************** * @attention * @@ -31,234 +31,224 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L4xx_LL_USB_H #define __STM32L4xx_LL_USB_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" -/** @addtogroup STM32L4xx_HAL +#if defined (USB) || defined (USB_OTG_FS) || defined (USB_OTG_HS) + +/** @addtogroup STM32L4xx_HAL_Driver * @{ */ -/** @addtogroup USB_Core +/** @addtogroup USB_LL * @{ - */ + */ + +/* Exported types ------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ +/** + * @brief USB Mode definition + */ +typedef enum +{ + USB_DEVICE_MODE = 0, + USB_HOST_MODE = 1, + USB_DRD_MODE = 2 +} USB_ModeTypeDef; -/** - * @brief USB Mode definition - */ -typedef enum +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief URB States definition + */ +typedef enum { - USB_DEVICE_MODE = 0, - USB_HOST_MODE = 1, - USB_DRD_MODE = 2 - -}USB_ModeTypeDef; - -#if defined (USB_OTG_FS) -/** - * @brief URB States definition - */ -typedef enum { URB_IDLE = 0, URB_DONE, URB_NOTREADY, URB_NYET, URB_ERROR, URB_STALL - -}USB_OTG_URBStateTypeDef; +} USB_OTG_URBStateTypeDef; -/** - * @brief Host channel States definition - */ -typedef enum { +/** + * @brief Host channel States definition + */ +typedef enum +{ HC_IDLE = 0, HC_XFRC, HC_HALTED, HC_NAK, HC_NYET, HC_STALL, - HC_XACTERR, - HC_BBLERR, + HC_XACTERR, + HC_BBLERR, HC_DATATGLERR - -}USB_OTG_HCStateTypeDef; +} USB_OTG_HCStateTypeDef; -/** - * @brief PCD Initialization Structure definition +/** + * @brief USB OTG Initialization Structure definition */ typedef struct { uint32_t dev_endpoints; /*!< Device Endpoints number. - This parameter depends on the used USB core. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + This parameter depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + uint32_t Host_channels; /*!< Host Channels number. - This parameter Depends on the used USB core. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + This parameter Depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref USB_Core_Speed_ */ - - uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA. */ + This parameter can be any value of @ref USB_Core_Speed_ */ + + uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */ + + uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. + This parameter can be any value of @ref USB_EP0_MPS_ */ - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. - This parameter can be any value of @ref USB_EP0_MPS_ */ - uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref USB_Core_PHY_ */ - - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - - uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ - - uint32_t lpm_enable; /*!< Enable or disable Battery charging. */ - - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ - - uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ - - uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ - - uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ - -}USB_OTG_CfgTypeDef; + This parameter can be any value of @ref USB_Core_PHY_ */ + + uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + + uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ + + uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ + + uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + + uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ + + uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ + + uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ +} USB_OTG_CfgTypeDef; typedef struct { uint8_t num; /*!< Endpoint number - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + uint8_t is_in; /*!< Endpoint direction - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + uint8_t is_stall; /*!< Endpoint stall condition - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + uint8_t type; /*!< Endpoint type - This parameter can be any value of @ref USB_EP_Type_ */ - + This parameter can be any value of @ref USB_EP_Type_ */ + uint8_t data_pid_start; /*!< Initial data PID This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t even_odd_frame; /*!< IFrame parity This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint16_t tx_fifo_num; /*!< Transmission FIFO number This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + uint32_t maxpacket; /*!< Endpoint Max packet size This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ - + uint32_t xfer_len; /*!< Current transfer length */ - - uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ -}USB_OTG_EPTypeDef; + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ +} USB_OTG_EPTypeDef; typedef struct { uint8_t dev_addr ; /*!< USB device address. - This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ + This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ uint8_t ch_num; /*!< Host channel number. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + uint8_t ep_num; /*!< Endpoint number. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + uint8_t ep_is_in; /*!< Endpoint direction - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + uint8_t speed; /*!< USB Host speed. This parameter can be any value of @ref USB_Core_Speed_ */ - + uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ - + uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */ uint8_t ep_type; /*!< Endpoint Type. This parameter can be any value of @ref USB_EP_Type_ */ - + uint16_t max_packet; /*!< Endpoint Max packet size. This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - + uint8_t data_pid; /*!< Initial data PID. This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ - + uint32_t xfer_len; /*!< Current transfer length. */ - + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ - + uint8_t toggle_in; /*!< IN transfer current toggle flag. This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t toggle_out; /*!< OUT transfer current toggle flag This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ - + uint32_t ErrCnt; /*!< Host channel error count.*/ - - USB_OTG_URBStateTypeDef urb_state; /*!< URB state. - This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ - - USB_OTG_HCStateTypeDef state; /*!< Host Channel state. - This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ - -}USB_OTG_HCTypeDef; -#endif /* USB_OTG_FS */ + + USB_OTG_URBStateTypeDef urb_state; /*!< URB state. + This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ + + USB_OTG_HCStateTypeDef state; /*!< Host Channel state. + This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ +} USB_OTG_HCTypeDef; +#endif /* defined USB_OTG_FS || USB_OTG_HS */ #if defined (USB) -/** - * @brief USB Initialization Structure definition +/** + * @brief USB Initialization Structure definition */ typedef struct { uint32_t dev_endpoints; /*!< Device Endpoints number. - This parameter depends on the used USB core. + This parameter depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + uint32_t speed; /*!< USB Core speed. This parameter can be any value of @ref USB_Core_Speed */ - - uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA. */ - - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. + + uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. This parameter can be any value of @ref USB_EP0_MPS */ - + uint32_t phy_itface; /*!< Select the used PHY interface. This parameter can be any value of @ref USB_Core_PHY */ - + uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - + uint32_t low_power_enable; /*!< Enable or disable Low Power mode */ - + uint32_t lpm_enable; /*!< Enable or disable Battery charging. */ - + uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ } USB_CfgTypeDef; @@ -266,39 +256,42 @@ typedef struct { uint8_t num; /*!< Endpoint number This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + uint8_t is_in; /*!< Endpoint direction This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t is_stall; /*!< Endpoint stall condition This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t type; /*!< Endpoint type This parameter can be any value of @ref USB_EP_Type */ - + + uint8_t data_pid_start; /*!< Initial data PID + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + uint16_t pmaadress; /*!< PMA Address This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - + uint16_t pmaaddr0; /*!< PMA Address0 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - + uint16_t pmaaddr1; /*!< PMA Address1 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - + uint8_t doublebuffer; /*!< Double buffer enable This parameter can be 0 or 1 */ - - uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral + + uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral This parameter is added to ensure compatibility across USB peripherals */ - + uint32_t maxpacket; /*!< Endpoint Max packet size This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - + uint32_t xfer_len; /*!< Current transfer length */ - + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ } USB_EPTypeDef; @@ -309,284 +302,292 @@ typedef struct /** @defgroup PCD_Exported_Constants PCD Exported Constants * @{ */ -#if defined (USB_OTG_FS) + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** @defgroup USB_Core_Mode_ USB Core Mode * @{ */ -#define USB_OTG_MODE_DEVICE 0 -#define USB_OTG_MODE_HOST 1 -#define USB_OTG_MODE_DRD 2 +#define USB_OTG_MODE_DEVICE 0U +#define USB_OTG_MODE_HOST 1U +#define USB_OTG_MODE_DRD 2U /** * @} */ -/** @defgroup USB_Core_Speed_ USB Core Speed +/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed * @{ - */ -#define USB_OTG_SPEED_HIGH 0 -#define USB_OTG_SPEED_HIGH_IN_FULL 1 -#define USB_OTG_SPEED_LOW 2 -#define USB_OTG_SPEED_FULL 3 + */ +#define USB_OTG_SPEED_LOW 2U +#define USB_OTG_SPEED_FULL 3U /** * @} */ - -/** @defgroup USB_Core_PHY_ USB Core PHY + +/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY * @{ - */ -#define USB_OTG_EMBEDDED_PHY 1 + */ +#define USB_OTG_ULPI_PHY 1U +#define USB_OTG_EMBEDDED_PHY 2U /** * @} */ - -/** @defgroup USB_Core_MPS_ USB Core MPS + +/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS * @{ */ -#define USB_OTG_FS_MAX_PACKET_SIZE 64 -#define USB_OTG_MAX_EP0_SIZE 64 +#define USB_OTG_FS_MAX_PACKET_SIZE 64U +#define USB_OTG_MAX_EP0_SIZE 64U /** * @} */ -/** @defgroup USB_Core_Phy_Frequency_ USB Core Phy Frequency +/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency * @{ */ -#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0 << 1) -#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1 << 1) -#define DSTS_ENUMSPD_LS_PHY_6MHZ (2 << 1) -#define DSTS_ENUMSPD_FS_PHY_48MHZ (3 << 1) +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) +#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << 1) +#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) /** * @} */ - -/** @defgroup USB_CORE_Frame_Interval_ USB CORE Frame Interval + +/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval * @{ - */ -#define DCFG_FRAME_INTERVAL_80 0 -#define DCFG_FRAME_INTERVAL_85 1 -#define DCFG_FRAME_INTERVAL_90 2 -#define DCFG_FRAME_INTERVAL_95 3 + */ +#define DCFG_FRAME_INTERVAL_80 0U +#define DCFG_FRAME_INTERVAL_85 1U +#define DCFG_FRAME_INTERVAL_90 2U +#define DCFG_FRAME_INTERVAL_95 3U /** * @} */ -/** @defgroup USB_EP0_MPS_ USB EP0 MPS +/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ -#define DEP0CTL_MPS_64 0 -#define DEP0CTL_MPS_32 1 -#define DEP0CTL_MPS_16 2 -#define DEP0CTL_MPS_8 3 +#define DEP0CTL_MPS_64 0U +#define DEP0CTL_MPS_32 1U +#define DEP0CTL_MPS_16 2U +#define DEP0CTL_MPS_8 3U /** * @} */ -/** @defgroup USB_EP_Speed_ USB EP Speed +/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed * @{ */ -#define EP_SPEED_LOW 0 -#define EP_SPEED_FULL 1 -#define EP_SPEED_HIGH 2 +#define EP_SPEED_LOW 0U +#define EP_SPEED_FULL 1U +#define EP_SPEED_HIGH 2U /** * @} */ -/** @defgroup USB_EP_Type_ USB EP Type +/** @defgroup USB_LL_EP_Type USB Low Layer EP Type * @{ */ -#define EP_TYPE_CTRL 0 -#define EP_TYPE_ISOC 1 -#define EP_TYPE_BULK 2 -#define EP_TYPE_INTR 3 -#define EP_TYPE_MSK 3 +#define EP_TYPE_CTRL 0U +#define EP_TYPE_ISOC 1U +#define EP_TYPE_BULK 2U +#define EP_TYPE_INTR 3U +#define EP_TYPE_MSK 3U /** * @} */ -/** @defgroup USB_STS_Defines_ USB STS Defines +/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines * @{ */ -#define STS_GOUT_NAK 1 -#define STS_DATA_UPDT 2 -#define STS_XFER_COMP 3 -#define STS_SETUP_COMP 4 -#define STS_SETUP_UPDT 6 +#define STS_GOUT_NAK 1U +#define STS_DATA_UPDT 2U +#define STS_XFER_COMP 3U +#define STS_SETUP_COMP 4U +#define STS_SETUP_UPDT 6U /** * @} */ -/** @defgroup HCFG_SPEED_Defines_ HCFG SPEED Defines +/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines * @{ - */ -#define HCFG_30_60_MHZ 0 -#define HCFG_48_MHZ 1 -#define HCFG_6_MHZ 2 + */ +#define HCFG_30_60_MHZ 0U +#define HCFG_48_MHZ 1U +#define HCFG_6_MHZ 2U /** * @} */ - -/** @defgroup HPRT0_PRTSPD_SPEED_Defines_ HPRT0 PRTSPD SPEED Defines + +/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines * @{ - */ -#define HPRT0_PRTSPD_HIGH_SPEED 0 -#define HPRT0_PRTSPD_FULL_SPEED 1 -#define HPRT0_PRTSPD_LOW_SPEED 2 + */ +#define HPRT0_PRTSPD_HIGH_SPEED 0U +#define HPRT0_PRTSPD_FULL_SPEED 1U +#define HPRT0_PRTSPD_LOW_SPEED 2U /** * @} - */ - -#define HCCHAR_CTRL 0 -#define HCCHAR_ISOC 1 -#define HCCHAR_BULK 2 -#define HCCHAR_INTR 3 - -#define HC_PID_DATA0 0 -#define HC_PID_DATA2 1 -#define HC_PID_DATA1 2 -#define HC_PID_SETUP 3 - -#define GRXSTS_PKTSTS_IN 2 -#define GRXSTS_PKTSTS_IN_XFER_COMP 3 -#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5 -#define GRXSTS_PKTSTS_CH_HALTED 7 - -#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE) -#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE) - -#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE)) -#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE)) -#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE)) -#define USBx_DFIFO(i) *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE) - -#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE)) -#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE)) - -#endif /* USB_OTG_FS */ - -#if defined (USB) + */ + +#define HCCHAR_CTRL 0U +#define HCCHAR_ISOC 1U +#define HCCHAR_BULK 2U +#define HCCHAR_INTR 3U + +#define HC_PID_DATA0 0U +#define HC_PID_DATA2 1U +#define HC_PID_DATA1 2U +#define HC_PID_SETUP 3U + +#define GRXSTS_PKTSTS_IN 2U +#define GRXSTS_PKTSTS_IN_XFER_COMP 3U +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U +#define GRXSTS_PKTSTS_CH_HALTED 7U + +#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) +#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) + +#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE)) +#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) +#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) +#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE)) + +#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE)) +#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) +#endif /* USB_OTG_FS || USB_OTG_HS */ + +#if defined (USB) /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ -#define DEP0CTL_MPS_64 0 -#define DEP0CTL_MPS_32 1 -#define DEP0CTL_MPS_16 2 -#define DEP0CTL_MPS_8 3 +#define DEP0CTL_MPS_64 0U +#define DEP0CTL_MPS_32 1U +#define DEP0CTL_MPS_16 2U +#define DEP0CTL_MPS_8 3U /** * @} - */ + */ /** @defgroup USB_LL_EP_Type USB Low Layer EP Type * @{ */ -#define EP_TYPE_CTRL 0 -#define EP_TYPE_ISOC 1 -#define EP_TYPE_BULK 2 -#define EP_TYPE_INTR 3 -#define EP_TYPE_MSK 3 +#define EP_TYPE_CTRL 0U +#define EP_TYPE_ISOC 1U +#define EP_TYPE_BULK 2U +#define EP_TYPE_INTR 3U +#define EP_TYPE_MSK 3U /** * @} - */ + */ -#define BTABLE_ADDRESS (0x000) +#define BTABLE_ADDRESS 0x000U +#define PMA_ACCESS 1U #endif /* USB */ - /** * @} */ /* Exported macro ------------------------------------------------------------*/ -#if defined (USB_OTG_FS) +/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) #define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) #define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) - + #define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) -#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) -#endif /* USB_OTG_FS */ +#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) +#endif /* USB_OTG_FS || USB_OTG_HS */ +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ -#if defined (USB_OTG_FS) +/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init); HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init); HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_ModeTypeDef mode); -HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed); -HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num ); +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode); +HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed); +HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma); -HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma); -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma); -void * USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); -HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address); -HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len); +void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); +HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address); +HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup); +HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup); uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx); uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum); -uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum); -void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); - -HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); -HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq); +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); + +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq); HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state); -uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps); -HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma); -uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num); -HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num); +HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state); +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, + uint8_t ch_num, + uint8_t epnum, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps); +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc); +uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); +HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); -#endif /* USB_OTG_FS */ +#endif /* USB_OTG_FS || USB_OTG_HS */ #if defined (USB) HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef Init); HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef Init); HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx); -HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode); -HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx , uint8_t speed); -HAL_StatusTypeDef USB_FlushRxFifo (USB_TypeDef *USBx); -HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num ); +HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode); +HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed); +HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx); +HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num); HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep ,uint8_t dma); +HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep); HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len); -void * USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len); -HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx , USB_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx , USB_EPTypeDef *ep); -HAL_StatusTypeDef USB_SetDevAddress (USB_TypeDef *USBx, uint8_t address); -HAL_StatusTypeDef USB_DevConnect (USB_TypeDef *USBx); -HAL_StatusTypeDef USB_DevDisconnect (USB_TypeDef *USBx); +void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len); +HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep); +HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address); +HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx); +HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx); HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx); -HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t dma, uint8_t *psetup); -uint32_t USB_ReadInterrupts (USB_TypeDef *USBx); -uint32_t USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx); -uint32_t USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum); -uint32_t USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx); -uint32_t USB_ReadDevInEPInterrupt (USB_TypeDef *USBx , uint8_t epnum); -void USB_ClearInterrupts (USB_TypeDef *USBx, uint32_t interrupt); +HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup); +uint32_t USB_ReadInterrupts(USB_TypeDef *USBx); +uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx); +uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum); +uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx); +uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum); +void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt); HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx); @@ -595,18 +596,22 @@ void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui #endif /* USB */ /** * @} - */ + */ /** * @} */ -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (USB) || defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_wwdg.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_wwdg.h index b6b18e97e5..a352d3a860 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_wwdg.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_wwdg.h @@ -49,30 +49,25 @@ extern "C" { */ #if defined (WWDG) - /** @defgroup WWDG_LL WWDG * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ - /* Private constants ---------------------------------------------------------*/ - /* Private macros ------------------------------------------------------------*/ - /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants * @{ */ - /** @defgroup WWDG_LL_EC_IT IT Defines * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions * @{ */ -#define LL_WWDG_CFR_EWI WWDG_CFR_EWI +#define LL_WWDG_CFR_EWI WWDG_CFR_EWI /** * @} */ @@ -80,10 +75,10 @@ extern "C" { /** @defgroup WWDG_LL_EC_PRESCALER PRESCALER * @{ */ -#define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */ -#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ -#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ -#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */ +#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */ +#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ +#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ +#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */ /** * @} */ @@ -119,7 +114,6 @@ extern "C" { * @} */ - /** * @} */ @@ -155,7 +149,7 @@ __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx) */ __STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx) { - return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)); + return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL); } /** @@ -182,7 +176,7 @@ __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter) */ __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx) { - return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T)); + return (READ_BIT(WWDGx->CR, WWDG_CR_T)); } /** @@ -215,7 +209,7 @@ __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescale */ __STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx) { - return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB)); + return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB)); } /** @@ -247,7 +241,7 @@ __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window) */ __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) { - return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W)); + return (READ_BIT(WWDGx->CFR, WWDG_CFR_W)); } /** @@ -268,7 +262,7 @@ __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) */ __STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx) { - return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)); + return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL); } /** @@ -310,7 +304,7 @@ __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx) */ __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) { - return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)); + return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL); } /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html index 241e2f0aa0..9bb389971b 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html @@ -665,7 +665,43 @@

        Update History

        -

        V1.8.2 +

        V1.8.3 +/ 22-May-2018

        +

        Main +Changes

        +
        • Maintenance Release of HAL and Low Layer drivers
        • Add support of HAL callback registration feature
          • The feature disabled by default is available for the following HAL drivers:
            • ADC, +CAN, COMP, CRYP, DAC, DCMI, DFSDM, DMA2D, DSI, GFXMMU, HASH, HCD, I2C, +IRDA, LPTIM, LTDC, OPAMP, OSPI, PCD, QSPI, RNG, RTC, SAI, SD, +SMARTCARD, SMBUS, SPI, SWPMI, TIM, TSC, UART, USART and WWDG
          • The feature may be enabled individually per HAL PPP driver by setting the corresponding definition USE_HAL_PPP_REGISTER_CALLBACKS to  1U in stm32l4xx_hal_conf.h project configuration file (template file stm32l4xx_hal_conf_template.h available from  Drivers/STM32L4xx_HAL_Driver/Inc)
          • Once +enabled, the user application may resort to HAL_PPP_RegisterCallback() +to register specific callback function(s) and unregister it(them) with +HAL_PPP_UnRegisterCallback().
        • MISRAC-2012 corrections
        +

           

        HAL Drivers changes

        +
        • HAL generic driver
          • stm32l4xx_hal_conf_template.h update to add callback registration feature support (disabled by default)
          • stm32l4xx_hal_def.h: UNUSED() macro update for g++ compilation
        • HAL ADC driver
          • Fix to enable ADC internal channels (VrefInt, temperature sensor and Vbat) without being too restrictive
          • Update internal ADC calibration timeout value
          • Add callback registration feature
            • Add HAL_ADC_RegisterCallback() and HAL_ADC_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_ADC_CallbackIDTypeDef enumerated typedef
        • HAL CAN driver
          • Add callback registration feature
            • Add HAL_CAN_RegisterCallback() and HAL_CAN_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_CAN_CallbackIDTypeDef enumerated typedef
        • HAL COMP driver
          • Add callback registration feature
            • Add HAL_COMP_RegisterCallback() and HAL_COMP_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_COMP_CallbackIDTypeDef enumerated typedef
        • HAL CRYP driver
          • Add callback registration feature
            • Add HAL_CRYP_RegisterCallback() and HAL_CRYP_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_CRYP_CallbackIDTypeDef enumerated typedef
        • HAL DAC driver
          • Add callback registration feature
            • Add HAL_DAC_RegisterCallback() and HAL_DAC_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_DAC_CallbackIDTypeDef enumerated typedef
        • HAL DCMI driver
          • Add callback registration feature
            • Add HAL_DCMI_RegisterCallback() and HAL_DCMI_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_DCMI_CallbackIDTypeDef enumerated typedef
        • HAL DFSDM driver
          • Add callback registration feature
            • Add HAL_DFSDM_Channel_RegisterCallback(), HAL_DFSDM_Channel_UnRegisterCallback(), HAL_DFSDM_Filter_RegisterCallback(), HAL_DFSDM_Filter_UnRegisterCallback(), HAL_DFSDM_Filter_RegisterAwdCallback() and HAL_DFSDM_Filter_UnRegisterAwdCallback() APIs
            • Add callback identifiers in HAL_DFSDM_Channel_CallbackIDTypeDef and HAL_DFSDM_Filter_CallbackIDTypeDef enumerated typedef
        • HAL DM2D driver
          • Add callback registration feature
            • Add HAL_DMA2D_RegisterCallback() and HAL_DMA2D_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_DMA2D_CallbackIDTypeDef enumerated typedef
        • HAL DSI driver
          • Add callback registration feature
            • Add HAL_DSI_RegisterCallback() and HAL_DSI_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_DSI_CallbackIDTypeDef enumerated typedef
        • HAL GFXMMU driver
          • Add callback registration feature
            • Add HAL_GFXMMU_RegisterCallback() and HAL_GFXMMU_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_GFXMMU_CallbackIDTypeDef enumerated typedef
        • HAL HASH driver
          • Add callback registration feature
            • Add HAL_HASH_RegisterCallback() and HAL_HASH_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_HASH_CallbackIDTypeDef enumerated typedef
        • HAL HCD driver
          • Add new user notification callbacks
            • HAL_HCD_PortEnabled_Callback() and HAL_HCD_PortDisabled_Callback()
          • Add callback registration feature
            • Add HAL_HCD_RegisterCallback(), HAL_HCD_UnRegisterCallback(), +HAL_HCD_RegisterHC_NotifyURBChangeCallback() and +HAL_HCD_UnRegisterHC_NotifyURBChangeCallback() APIs
            • Add callback identifiers in HAL_HCD_CallbackIDTypeDef enumerated typedef
        • HAL I2C driver
          • I2C slave enhancement when master sends RESTART instead of STOP
            • Add +HAL_I2C_Master_Sequential_Transmit_DMA(), +HAL_I2C_Master_Sequential_Receive_DMA(), +HAL_I2C_Slave_Sequential_Transmit_DMA() and +HAL_I2C_Slave_Sequential_Receive_DMA() APIs
          • Add callback registration feature
            • Add HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), HAL_I2C_RegisterAddrCallback() and HAL_I2C_UnRegisterAddrCallback() APIs
            • Add callback identifiers in HAL_I2C_CallbackIDTypeDef enumerated typedef
        • HAL IRDA driver
          • Add callback registration feature
            • Add HAL_IRDA_RegisterCallback() and HAL_IRDA_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_IRDA_CallbackIDTypeDef enumerated typedef
        • HAL LPTIM driver
          • Add callback registration feature
            • Add HAL_LPTIM_RegisterCallback() and HAL_LPTIM_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_LPTIM_CallbackIDTypeDef enumerated typedef
        • HAL LTDC driver
          • Add callback registration feature
            • Add HAL_LTDC_RegisterCallback() and HAL_LTDC_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_LTDC_CallbackIDTypeDef enumerated typedef
        • HAL NAND driver
          • Add new configuration API HAL_NAND_ConfigDevice()
          • Add new APIs for 8-bit and 16-bit accesses
            • HAL_NAND_Read_Page_8b(), HAL_NAND_Write_Page_8b(), HAL_NAND_Read_SpareArea_8b() and HAL_NAND_Write_SpareArea_8b()
            • HAL_NAND_Read_Page_16b(), HAL_NAND_Write_Page_16b(), HAL_NAND_Read_SpareArea_16b() and HAL_NAND_Write_SpareArea_16b()
        • HAL OPAMP driver
          • Add callback registration feature
            • Add HAL_OPAMP_RegisterCallback() and HAL_OPAMP_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_OPAMP_CallbackIDTypeDef enumerated typedef
        • HAL OSPI driver
          • Add callback registration feature
            • Add HAL_OSPI_RegisterCallback() and HAL_OSPI_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_OSPI_CallbackIDTypeDef enumerated typedef
        • HAL PCD driver
          • Fix USB double buffer issue in PCD_SET_EP_DBUF1_CNT() macro
          • Add callback registration feature
            • Add HAL_PCD_RegisterCallback(), HAL_PCD_UnRegisterCallback(), +HAL_PCD_RegisterDataOutStageCallback(), +HAL_PCD_UnRegisterDataOutStageCallback(), +HAL_PCD_RegisterDataInStageCallback(), +HAL_PCD_UnRegisterDataInStageCallback(), +HAL_PCD_RegisterIsoOutIncpltCallback(), +HAL_PCD_UnRegisterIsoOutIncpltCallback(), +HAL_PCD_RegisterIsoInIncpltCallback(), +HAL_PCD_UnRegisterIsoInIncpltCallback(), HAL_PCD_RegisterBcdCallback(), +HAL_PCD_UnRegisterBcdCallback(), HAL_PCD_RegisterLpmCallback() and +HAL_PCD_UnRegisterLpmCallback() APIs
            • Add callback identifiers in HAL_PCD_CallbackIDTypeDef enumerated typedef
        • HAL QSPI driver
          • Fix HAL_QSPI_Receive_IT() to avoid early clear of TE and TC flags
          • Add callback registration feature
            • Add HAL_QSPI_RegisterCallback() and HAL_QSPI_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_QSPI_CallbackIDTypeDef enumerated typedef
        • HAL RCC driver
          • Fix +HAL_RCCEx_GetPeriphCLKFreq() for all peripheral clock frequency +derivated from PLLSAI1 and PLLSAI2 when PLLSAI1M and PLLSAI2M dividers +are present
        • HAL RNG driver
          • Add callback registration feature
            • Add HAL_RNG_RegisterCallback(), HAL_RNG_UnRegisterCallback(), HAL_RNG_RegisterReadyDataCallback() and HAL_RNG_UnRegisterReadyDataCallback() APIs
            • Add callback identifiers in HAL_RNG_CallbackIDTypeDef enumerated typedef
        • HAL RTC driver
          • Add callback registration feature
            • Add HAL_RTC_RegisterCallback() and HAL_RTC_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_RTC_CallbackIDTypeDef enumerated typedef
        • HAL SAI driver
          • Add callback registration feature
            • Add HAL_SAI_RegisterCallback() and HAL_SAI_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_SAI_CallbackIDTypeDef enumerated typedef
        • HAL SMBUS driver
          • Add callback registration feature
            • Add HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), HAL_SMBUS_RegisterAddrCallback() and HAL_SMBUS_UnRegisterAddrCallback() APIs
            • Add callback identifiers in HAL_SMBUS_CallbackIDTypeDef enumerated typedef
        • HAL SD driver
          • Fix DMA write issue
          • Fix to send the "Stop transfer" command only in case of multiple read or write operations
          • Fix typo in FileFormatGroup field of HAL_SD_CardCSDTypedef
          • Add callback registration feature
            • Add HAL_SD_RegisterCallback(), HAL_SD_UnRegisterCallback(), HAL_SD_RegisterTransceiverCallback() and HAL_SD_UnRegisterTransceiverCallback APIs
            • Add callback identifiers in HAL_SD_CallbackIDTypeDef enumerated typedef
        • HAL SMARTCARD driver
          • Add callback registration feature
            • Add HAL_SMARTCARD_RegisterCallback() and HAL_SMARTCARD_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_SMARTCARD_CallbackIDTypeDef enumerated typedef
        • HAL SPI driver
          • Add callback registration feature
            • Add HAL_SPI_RegisterCallback() and HAL_SPI_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_SPI_CallbackIDTypeDef enumerated typedef
        • HAL SWPMI driver
          • Fix in HWL_SWPMI_EnableLoopback() to enable entering loopback mode after SWPMI initialization
          • Add callback registration feature
            • Add HAL_SWPMI_RegisterCallback() and HAL_SWPMI_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_SWPMI_CallbackIDTypeDef enumerated typedef
        • HAL TIM driver
          • Add callback registration feature
            • Add HAL_TIM_RegisterCallback() and HAL_TIM_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_TIM_CallbackIDTypeDef enumerated typedef
        • HAL TSC driver
          • Add callback registration feature
            • Add HAL_TSC_RegisterCallback() and HAL_TSC_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_TSC_CallbackIDTypeDef enumerated typedef
        • HAL UART driver
          • Add wakeup capability from Stop mode when clocked by LSE
            • Add HAL_UARTEx_EnableClockStopMode() and HAL_UARTEx_DisableClockStopMode() APIs
          • Remove the following APIs since only applicable to HAL USART and not HAL UART
            • HAL_UARTEx_EnableSlaveMode(), HAL_UARTEx_DisableSlaveMode() and HAL_UARTEx_ConfigNSS()
          • Add callback registration feature
            • Add HAL_UART_RegisterCallback() and HAL_UART_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_UART_CallbackIDTypeDef enumerated typedef
        • HAL USART driver
          • Add callback registration feature
            • Add HAL_USART_RegisterCallback() and HAL_USART_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_USART_CallbackIDTypeDef enumerated typedef
        • HAL WWDG driver
          • Add callback registration feature
            • Add HAL_WWDG_RegisterCallback() and HAL_WWDG_UnRegisterCallback() APIs
            • Add callback identifiers in HAL_WWDG_CallbackIDTypeDef enumerated typedef

        LL Drivers changes

        +
        • LL ADC driver
          • Fix temperature sensor calibration factor value for STM32L4 devices other than STM32L47x/L48x
        • LL LPUART driver
          • Add wakeup capability from Stop mode when clocked by LSE
            • Add LL_LPUART_EnableClockInStopMode(), LL_LPUART_DisableClockInStopMode() and LL_LPUART_IsClockEnabledInStopMode() APIs
        • LL RTC driver
          • Code +optimization done in LL_RTC_TIME_GetHour(), LL_RTC_TIME_GetMinute(), +LL_RTC_TIME_GetSecond(), LL_RTC_DATE_GetYear(), LL_RTC_DATE_GetMonth(), +LL_RTC_DATE_GetDay(), LL_RTC_ALMA_GetDay(), LL_RTC_ALMA_GetHour(), +LL_RTC_ALMA_GetMinute(), LL_RTC_ALMA_GetSecond(), LL_RTC_ALMB_GetDay(), LL_RTC_ALMB_GetHour(), LL_RTC_ALMB_GetMinute() and LL_RTC_ALMB_GetSecond() APIs
        • LL SPI driver
          • Fix GCC warnings in LL_SPI_TransmitData8() and LL_SPI_TransmitData16()
        • LL USART driver
          • Rename LL_USART_ICR_NCF flag to LL_USART_ICR_NECF
          • Add wakeup capability from Stop mode when clocked by LSE
            • Add LL_USART_EnableClockInStopMode(), LL_USART_DisableClockInStopMode() and LL_USART_IsClockEnabledInStopMode() APIs

        V1.8.2 / 22-December-2017

        Main Changes

        diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c index 92ba628bd0..27702e3ee8 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c @@ -69,7 +69,7 @@ */ #define __STM32L4xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32L4xx_HAL_VERSION_SUB1 (0x08) /*!< [23:16] sub1 version */ -#define __STM32L4xx_HAL_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ +#define __STM32L4xx_HAL_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ #define __STM32L4xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L4xx_HAL_VERSION ((__STM32L4xx_HAL_VERSION_MAIN << 24)\ |(__STM32L4xx_HAL_VERSION_SUB1 << 16)\ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c index e1d039daa1..a7543d8b73 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c @@ -210,8 +210,81 @@ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) [..] + + *** Callback registration *** + ============================================= + [..] + + The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_ADC_RegisterCallback() + to register an interrupt callback. + [..] + + Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: + (+) ConvCpltCallback : ADC conversion complete callback + (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + (+) ErrorCallback : ADC error callback + (+) InjectedConvCpltCallback : ADC group injected conversion complete callback + (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback + (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback + (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback + (+) EndOfSamplingCallback : ADC end of sampling callback + (+) MspInitCallback : ADC Msp Init callback + (+) MspDeInitCallback : ADC Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + + Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default + weak function. + [..] + + @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) ConvCpltCallback : ADC conversion complete callback + (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + (+) ErrorCallback : ADC error callback + (+) InjectedConvCpltCallback : ADC group injected conversion complete callback + (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback + (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback + (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback + (+) EndOfSamplingCallback : ADC end of sampling callback + (+) MspInitCallback : ADC Msp Init callback + (+) MspDeInitCallback : ADC Msp DeInit callback + [..] + + By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when + these callbacks are null (not registered beforehand). + [..] + + If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + + Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + [..] + + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() + or @ref HAL_ADC_Init() function. + [..] + + When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. - @endverbatim + @endverbatim ****************************************************************************** * @attention * @@ -269,30 +342,22 @@ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */ -/* Delay to wait before setting ADEN once ADCAL has been reset - must be at least 4 ADC clock cycles. - Assuming lowest ADC clock (140 KHz according to DS), this - 4 ADC clock cycles duration is equal to - 4 / 140,000 = 0.028 ms. - ADC_ENABLE_TIMEOUT set to 2 is a margin large enough to ensure - the 4 ADC clock cycles have elapsed while waiting for ADRDY - to become 1 */ - #define ADC_ENABLE_TIMEOUT ((uint32_t) 2) /*!< ADC enable time-out value */ - #define ADC_DISABLE_TIMEOUT ((uint32_t) 2) /*!< ADC disable time-out value */ - +/* Timeout values for ADC operations (enable settling time, */ +/* disable settling time, ...). */ +/* Values defined to be higher than worst cases: low clock frequency, */ +/* maximum prescalers. */ +#define ADC_ENABLE_TIMEOUT ((uint32_t) 2) /*!< ADC enable time-out value */ +#define ADC_DISABLE_TIMEOUT ((uint32_t) 2) /*!< ADC disable time-out value */ /* Timeout to wait for current conversion on going to be completed. */ /* Timeout fixed to longest ADC conversion possible, for 1 channel: */ /* - maximum sampling time (640.5 adc_clk) */ /* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */ -/* - ADC clock with prescaler 256 */ -/* (from asynchronous clock, assuming clock frequency same as CPU for */ -/* this calculation) */ +/* - System clock / ADC clock <= 4096 (hypothesis of maximum clock ratio) */ /* - ADC oversampling ratio 256 */ -/* Calculation: 653 * 256 * 256 = 42795008 CPU clock cycles max */ +/* Calculation: 653 * 4096 * 256 CPU clock cycles max */ /* Unit: cycles of CPU clock. */ -#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 42795008) /*!< ADC conversion completion time-out value */ - +#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 653U * 4096U * 256U) /*!< ADC conversion completion time-out value */ /** @@ -396,8 +461,29 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* - Initialization of ADC MSP */ if(hadc->State == HAL_ADC_STATE_RESET) { +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + /* Init the ADC Callback settings */ + hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ + hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ + hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ + hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ + hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */ + hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */ + hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */ + hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */ + hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */ + + if (hadc->MspInitCallback == NULL) + { + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hadc->MspInitCallback(hadc); +#else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); @@ -777,8 +863,19 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) the clock will reset all ADCs. */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + if (hadc->MspDeInitCallback == NULL) + { + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: RCC clock, NVIC */ + hadc->MspDeInitCallback(hadc); +#else + /* DeInit the low level hardware: RCC clock, NVIC */ HAL_ADC_MspDeInit(hadc); - +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); @@ -828,6 +925,250 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) */ } +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User ADC Callback + * To be used instead of the weak predefined callback + * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID + * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID + * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if ((hadc->State & HAL_ADC_STATE_READY) != 0) + { + switch (CallbackID) + { + case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + hadc->ConvCpltCallback = pCallback; + break; + + case HAL_ADC_CONVERSION_HALF_CB_ID : + hadc->ConvHalfCpltCallback = pCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + hadc->LevelOutOfWindowCallback = pCallback; + break; + + case HAL_ADC_ERROR_CB_ID : + hadc->ErrorCallback = pCallback; + break; + + case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : + hadc->InjectedConvCpltCallback = pCallback; + break; + + case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : + hadc->InjectedQueueOverflowCallback = pCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : + hadc->LevelOutOfWindow2Callback = pCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : + hadc->LevelOutOfWindow3Callback = pCallback; + break; + + case HAL_ADC_END_OF_SAMPLING_CB_ID : + hadc->EndOfSamplingCallback = pCallback; + break; + + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = pCallback; + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_ADC_STATE_RESET == hadc->State) + { + switch (CallbackID) + { + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = pCallback; + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a ADC Callback + * ADC callback is redirected to the weak predefined callback + * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID + * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID + * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if ((hadc->State & HAL_ADC_STATE_READY) != 0) + { + switch (CallbackID) + { + case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; + break; + + case HAL_ADC_CONVERSION_HALF_CB_ID : + hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; + break; + + case HAL_ADC_ERROR_CB_ID : + hadc->ErrorCallback = HAL_ADC_ErrorCallback; + break; + + case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : + hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; + break; + + case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : + hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : + hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : + hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; + break; + + case HAL_ADC_END_OF_SAMPLING_CB_ID : + hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; + break; + + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_ADC_STATE_RESET == hadc->State) + { + switch (CallbackID) + { + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + /** * @} */ @@ -1798,7 +2139,11 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) } /* End Of Sampling callback */ - HAL_ADCEx_EndOfSamplingCallback(hadc); +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->EndOfSamplingCallback(hadc); +#else + HAL_ADCEx_EndOfSamplingCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP ); @@ -1876,7 +2221,11 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* to determine if conversion has been triggered from EOC or EOS, */ /* possibility to use: */ /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else HAL_ADC_ConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear regular group conversion flag */ /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ @@ -1964,7 +2313,11 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether interruption has been triggered by end of conversion or end of sequence. */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->InjectedConvCpltCallback(hadc); +#else HAL_ADCEx_InjectedConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS); @@ -1977,7 +2330,12 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); /* Level out of window 1 callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindowCallback(hadc); +#else HAL_ADC_LevelOutOfWindowCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); } @@ -1989,7 +2347,12 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); /* Level out of window 2 callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindow2Callback(hadc); +#else HAL_ADCEx_LevelOutOfWindow2Callback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); } @@ -2001,7 +2364,12 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); /* Level out of window 3 callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindow3Callback(hadc); +#else HAL_ADCEx_LevelOutOfWindow3Callback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); } @@ -2055,7 +2423,11 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* flag OVR is reset. */ /* Therefore, old ADC conversion data can be retrieved in */ /* function "HAL_ADC_ErrorCallback()". */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /* Clear ADC overrun flag */ @@ -2074,8 +2446,12 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* Clear the Injected context queue overflow flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); - /* Error callback */ + /* Injected context queue overflow callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->InjectedQueueOverflowCallback(hadc); +#else HAL_ADCEx_InjectedQueueOverflowCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } } @@ -2312,7 +2688,6 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ - /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ if (ADC_IS_ENABLE(hadc) == RESET) { /* Set mode single-ended or differential input of the selected ADC channel */ @@ -2325,71 +2700,56 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL(__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) + 1), sConfig->SamplingTime); } - /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ - /* If internal channel selected, enable dedicated internal buffers and */ - /* paths. */ - /* Note: these internal measurement paths can be disabled using */ - /* HAL_ADC_DeInit(). */ - - /* Configuration of common ADC parameters */ - /* If the requested internal measurement path has already been enabled, */ - /* bypass the configuration processing. */ - if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && - ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0U)) || - ( (sConfig->Channel == ADC_CHANNEL_VBAT) && - ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VBAT) == 0U)) || - ( (sConfig->Channel == ADC_CHANNEL_VREFINT) && - ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VREFINT) == 0U)) - ) - { - /* Configuration of common ADC parameters (continuation) */ + } - /* Software is allowed to change common parameters only when all ADCs */ - /* of the common group are disabled. */ - if ((ADC_IS_ENABLE(hadc) == RESET) && - (ADC_ANY_OTHER_ENABLED(hadc) == RESET) ) + /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ + /* If internal channel selected, enable dedicated internal buffers and */ + /* paths. */ + /* Note: these internal measurement paths can be disabled using */ + /* HAL_ADC_DeInit(). */ + + /* Configuration of common ADC parameters */ + /* If the requested internal measurement path has already been enabled, */ + /* bypass the configuration processing. */ + if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && + ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0U)) || + ( (sConfig->Channel == ADC_CHANNEL_VBAT) && + ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VBAT) == 0U)) || + ( (sConfig->Channel == ADC_CHANNEL_VREFINT) && + ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VREFINT) == 0U)) + ) + { + /* Configuration of common ADC parameters (continuation) */ + + if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + { + if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) { - if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) - { - if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) - { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); - - /* Delay for temperature sensor stabilization time */ - /* Wait loop initialization and execution */ - /* Note: Variable divided by 2 to compensate partially */ - /* CPU processing cycles. */ - wait_loop_index = (LL_ADC_DELAY_TEMPSENSOR_STAB_US * (SystemCoreClock / (1000000 * 2))); - while(wait_loop_index != 0) - { - wait_loop_index--; - } - } - } - else if (sConfig->Channel == ADC_CHANNEL_VBAT) - { - if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) - { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); - } - } - else if (sConfig->Channel == ADC_CHANNEL_VREFINT) + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); + + /* Delay for temperature sensor stabilization time */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles. */ + wait_loop_index = (LL_ADC_DELAY_TEMPSENSOR_STAB_US * (SystemCoreClock / (1000000 * 2))); + while(wait_loop_index != 0) { - if (ADC_VREFINT_INSTANCE(hadc)) - { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); - } + wait_loop_index--; } } - /* If the requested internal measurement path has already been */ - /* enabled and other ADC of the common group are enabled, internal */ - /* measurement paths cannot be enabled. */ - else + } + else if (sConfig->Channel == ADC_CHANNEL_VBAT) + { + if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); + } + } + else if (sConfig->Channel == ADC_CHANNEL_VREFINT) + { + if (ADC_VREFINT_INSTANCE(hadc)) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - tmp_hal_status = HAL_ERROR; + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); } } } @@ -3005,14 +3365,22 @@ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) } /* Conversion complete callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else HAL_ADC_ConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } else /* DMA and-or internal error occurred */ { if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) { /* Call HAL ADC Error Callback function */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } else { @@ -3033,7 +3401,11 @@ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* Half conversion callback */ - HAL_ADC_ConvHalfCpltCallback(hadc); +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvHalfCpltCallback(hadc); +#else + HAL_ADC_ConvHalfCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /** @@ -3053,7 +3425,11 @@ void ADC_DMAError(DMA_HandleTypeDef *hdma) SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); /* Error callback */ - HAL_ADC_ErrorCallback(hadc); +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c index b3d24b0a43..f1baf9b8da 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c @@ -82,14 +82,13 @@ once the ADC is enabled */ /* Fixed timeout value for ADC calibration. */ -/* Values defined to be higher than worst cases: low clock frequency, */ -/* maximum prescalers. */ -/* Ex of profile low frequency : f_ADC at 0.14 MHz (minimum value */ -/* according to Data sheet), calibration_time MAX = 112 / f_ADC */ -/* 112 / 140,000 = 0.8 ms */ -/* At maximum CPU speed (80 MHz), this means */ -/* 0.8 ms * 80 MHz = 64000 CPU cycles */ -#define ADC_CALIBRATION_TIMEOUT (64000U) /*!< ADC calibration time-out value */ +/* Values defined to be higher than worst cases: maximum ratio between ADC */ +/* and CPU clock frequencies. */ +/* Example of profile low frequency : ADC frequency at 31.25kHz (ADC clock */ +/* source PLL SAI 8MHz, ADC clock prescaler 256), CPU frequency 80MHz. */ +/* Calibration time max = 116 / fADC (refer to datasheet) */ +/* = 296 960 CPU cycles */ +#define ADC_CALIBRATION_TIMEOUT (296960U) /*!< ADC calibration time-out value (unit: CPU cycles) */ /** * @} @@ -1060,6 +1059,10 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); + /* Prevent unused argument(s) compilation warning if no assert_param check */ + /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */ + UNUSED(hadc); + /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); @@ -1920,7 +1923,6 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ - /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ if (ADC_IS_ENABLE(hadc) == RESET) { /* Set mode single-ended or differential input of the selected ADC channel */ @@ -1933,71 +1935,54 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL(__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) + 1), sConfigInjected->InjectedSamplingTime); } - /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */ - /* internal measurement paths enable: If internal channel selected, */ - /* enable dedicated internal buffers and path. */ - /* Note: these internal measurement paths can be disabled using */ - /* HAL_ADC_DeInit(). */ + } - /* Configuration of common ADC parameters */ - /* If the requested internal measurement path has already been enabled, */ - /* bypass the configuration processing. */ - if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && - ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0U)) || - ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && - ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VBAT) == 0U)) || - ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && - ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VREFINT) == 0U)) - ) + /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */ + /* internal measurement paths enable: If internal channel selected, */ + /* enable dedicated internal buffers and path. */ + /* Note: these internal measurement paths can be disabled using */ + /* HAL_ADC_DeInit(). */ + + /* Configuration of common ADC parameters */ + /* If the requested internal measurement path has already been enabled, */ + /* bypass the configuration processing. */ + if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && + ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0U)) || + ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && + ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VBAT) == 0U)) || + ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && + ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VREFINT) == 0U)) + ) + { + if (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) { - /* Configuration of common ADC parameters (continuation) */ - /* Software is allowed to change common parameters only when all ADCs */ - /* of the common group are disabled. */ - if ((ADC_IS_ENABLE(hadc) == RESET) && - (ADC_ANY_OTHER_ENABLED(hadc) == RESET) ) + if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) { - if (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); + + /* Delay for temperature sensor stabilization time */ + /* Compute number of CPU cycles to wait for */ + wait_loop_index = (LL_ADC_DELAY_TEMPSENSOR_STAB_US * (SystemCoreClock / 1000000)); + while(wait_loop_index != 0) { - if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) - { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); - - /* Delay for temperature sensor stabilization time */ - /* Compute number of CPU cycles to wait for */ - wait_loop_index = (LL_ADC_DELAY_TEMPSENSOR_STAB_US * (SystemCoreClock / 1000000)); - while(wait_loop_index != 0) - { - wait_loop_index--; - } - } - } - else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) - { - if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) - { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); - } - } - else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) - { - if (ADC_VREFINT_INSTANCE(hadc)) - { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); - } + wait_loop_index--; } } - /* If the requested internal measurement path has already been enabled */ - /* and other ADC of the common group are enabled, internal */ - /* measurement paths cannot be enabled. */ - else + } + else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) + { + if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - tmp_hal_status = HAL_ERROR; + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); + } + } + else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) + { + if (ADC_VREFINT_INSTANCE(hadc)) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); } } - } /* Process unlocked */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c index d628cef4cc..6bedd0c3e1 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c @@ -126,6 +126,74 @@ (++) When a start of Rx CAN frame is detected by the CAN peripheral, if automatic wake up mode is enabled. + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_CAN_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function @ref HAL_CAN_RegisterCallback() to register an interrupt callback. + + Function @ref HAL_CAN_RegisterCallback() allows to register following callbacks: + (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. + (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. + (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. + (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. + (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. + (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. + (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. + (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. + (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. + (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. + (+) SleepCallback : Sleep Callback. + (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : CAN MspInit. + (+) MspDeInitCallback : CAN MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_CAN_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. + (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. + (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. + (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. + (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. + (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. + (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. + (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. + (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. + (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. + (+) SleepCallback : Sleep Callback. + (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : CAN MspInit. + (+) MspDeInitCallback : CAN MspDeInit. + + By default, after the @ref HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET, + all callbacks are set to the corresponding weak functions: + example @ref HAL_CAN_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit() only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_CAN_RegisterCallback() before calling @ref HAL_CAN_DeInit() + or @ref HAL_CAN_Init() function. + + When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + @endverbatim ****************************************************************************** * @attention @@ -221,7 +289,7 @@ */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { - uint32_t tickstart = 0U; + uint32_t tickstart; /* Check CAN handle */ if (hcan == NULL) @@ -243,11 +311,40 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + if (hcan->State == HAL_CAN_STATE_RESET) + { + /* Reset callbacks to legacy functions */ + hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; /* Legacy weak RxFifo0MsgPendingCallback */ + hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; /* Legacy weak RxFifo0FullCallback */ + hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; /* Legacy weak RxFifo1MsgPendingCallback */ + hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; /* Legacy weak RxFifo1FullCallback */ + hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */ + hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */ + hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */ + hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; /* Legacy weak TxMailbox0AbortCallback */ + hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; /* Legacy weak TxMailbox1AbortCallback */ + hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; /* Legacy weak TxMailbox2AbortCallback */ + hcan->SleepCallback = HAL_CAN_SleepCallback; /* Legacy weak SleepCallback */ + hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; /* Legacy weak WakeUpFromRxMsgCallback */ + hcan->ErrorCallback = HAL_CAN_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hcan->MspInitCallback == NULL) + { + hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware: CLOCK, NVIC */ + hcan->MspInitCallback(hcan); + } + +#else if (hcan->State == HAL_CAN_STATE_RESET) { /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); } +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); @@ -256,7 +353,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) tickstart = HAL_GetTick(); /* Check Sleep mode leave acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { @@ -277,7 +374,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) tickstart = HAL_GetTick(); /* Wait initialisation acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET) + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { @@ -387,10 +484,21 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); /* Stop the CAN module */ - HAL_CAN_Stop(hcan); + (void)HAL_CAN_Stop(hcan); + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + if (hcan->MspDeInitCallback == NULL) + { + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; /* Legacy weak MspDeInit */ + } + /* DeInit the low level hardware: CLOCK, NVIC */ + hcan->MspDeInitCallback(hcan); + +#else /* DeInit the low level hardware: CLOCK, NVIC */ HAL_CAN_MspDeInit(hcan); +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ /* Reset the CAN peripheral */ SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); @@ -437,6 +545,284 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) */ } +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +/** + * @brief Register a CAN CallBack. + * To be used instead of the weak predefined callback + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for CAN module + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID + * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID + * @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID + * @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID + * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID + * @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID + * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan)) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (hcan->State == HAL_CAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : + hcan->TxMailbox0CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : + hcan->TxMailbox1CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : + hcan->TxMailbox2CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : + hcan->TxMailbox0AbortCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : + hcan->TxMailbox1AbortCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : + hcan->TxMailbox2AbortCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : + hcan->RxFifo0MsgPendingCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO0_FULL_CB_ID : + hcan->RxFifo0FullCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : + hcan->RxFifo1MsgPendingCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO1_FULL_CB_ID : + hcan->RxFifo1FullCallback = pCallback; + break; + + case HAL_CAN_SLEEP_CB_ID : + hcan->SleepCallback = pCallback; + break; + + case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : + hcan->WakeUpFromRxMsgCallback = pCallback; + break; + + case HAL_CAN_ERROR_CB_ID : + hcan->ErrorCallback = pCallback; + break; + + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = pCallback; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcan->State == HAL_CAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = pCallback; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a CAN CallBack. + * CAN callabck is redirected to the weak predefined callback + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for CAN module + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID + * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID + * @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID + * @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID + * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID + * @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID + * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hcan->State == HAL_CAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : + hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : + hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : + hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : + hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; + break; + + case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : + hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; + break; + + case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : + hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; + break; + + case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : + hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; + break; + + case HAL_CAN_RX_FIFO0_FULL_CB_ID : + hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; + break; + + case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : + hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; + break; + + case HAL_CAN_RX_FIFO1_FULL_CB_ID : + hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; + break; + + case HAL_CAN_SLEEP_CB_ID : + hcan->SleepCallback = HAL_CAN_SleepCallback; + break; + + case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : + hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; + break; + + case HAL_CAN_ERROR_CB_ID : + hcan->ErrorCallback = HAL_CAN_ErrorCallback; + break; + + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = HAL_CAN_MspInit; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcan->State == HAL_CAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = HAL_CAN_MspInit; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /** * @} @@ -467,11 +853,12 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) { - uint32_t filternbrbitpos = 0U; + uint32_t filternbrbitpos; CAN_TypeDef *can_ip = hcan->Instance; + HAL_CAN_StateTypeDef state = hcan->State; - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Check the parameters */ assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh)); @@ -481,7 +868,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); + assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); #if defined(CAN2) /* CAN1 and CAN2 are dual instances with 28 common filters banks */ @@ -508,7 +895,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe #endif /* Convert filter number into bit position */ - filternbrbitpos = (1U) << sFilterConfig->FilterBank; + filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); /* Filter Deactivation */ CLEAR_BIT(can_ip->FA1R, filternbrbitpos); @@ -573,7 +960,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe } /* Filter activation */ - if (sFilterConfig->FilterActivation == ENABLE) + if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) { SET_BIT(can_ip->FA1R, filternbrbitpos); } @@ -632,7 +1019,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe */ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { - uint32_t tickstart = 0U; + uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_READY) { @@ -646,7 +1033,7 @@ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) tickstart = HAL_GetTick(); /* Wait the acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_INAK) != RESET) + while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) @@ -684,7 +1071,7 @@ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) */ HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) { - uint32_t tickstart = 0U; + uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_LISTENING) { @@ -695,7 +1082,7 @@ HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) tickstart = HAL_GetTick(); /* Wait the acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET) + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) @@ -739,8 +1126,10 @@ HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) */ HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) { - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Request Sleep mode */ SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); @@ -770,9 +1159,10 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) { __IO uint32_t count = 0; uint32_t timeout = 1000000U; + HAL_CAN_StateTypeDef state = hcan->State; - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Wake up request */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); @@ -780,8 +1170,11 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) /* Wait sleep mode is exited */ do { + /* Increment counter */ + count++; + /* Check if timeout is reached */ - if (++count > timeout) + if (count > timeout) { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; @@ -789,7 +1182,7 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) return HAL_ERROR; } } - while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET); + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U); /* Return function status */ return HAL_OK; @@ -814,12 +1207,13 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan) { uint32_t status = 0U; + HAL_CAN_StateTypeDef state = hcan->State; - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Check Sleep mode */ - if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) { status = 1U; } @@ -844,6 +1238,8 @@ uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan) HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox) { uint32_t transmitmailbox; + HAL_CAN_StateTypeDef state = hcan->State; + uint32_t tsr = READ_REG(hcan->Instance->TSR); /* Check the parameters */ assert_param(IS_CAN_IDTYPE(pHeader->IDE)); @@ -859,19 +1255,28 @@ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderType } assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Check that all the Tx mailboxes are not full */ - if (((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) || - ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) || - ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET)) + if (((tsr & CAN_TSR_TME0) != 0U) || + ((tsr & CAN_TSR_TME1) != 0U) || + ((tsr & CAN_TSR_TME2) != 0U)) { /* Select an empty transmit mailbox */ - transmitmailbox = (hcan->Instance->TSR & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; + transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; + + /* Check transmit mailbox value */ + if (transmitmailbox > 2U) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL; + + return HAL_ERROR; + } /* Store the Tx mailbox */ - *pTxMailbox = 1U << transmitmailbox; + *pTxMailbox = (uint32_t)1 << transmitmailbox; /* Set up the Id */ if (pHeader->IDE == CAN_ID_STD) @@ -940,28 +1345,30 @@ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderType */ HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) { + HAL_CAN_StateTypeDef state = hcan->State; + /* Check function parameters */ assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Check Tx Mailbox 0 */ - if ((TxMailboxes & CAN_TX_MAILBOX0) != RESET) + if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U) { /* Add cancellation request for Tx Mailbox 0 */ SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0); } /* Check Tx Mailbox 1 */ - if ((TxMailboxes & CAN_TX_MAILBOX1) != RESET) + if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U) { /* Add cancellation request for Tx Mailbox 1 */ SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1); } /* Check Tx Mailbox 2 */ - if ((TxMailboxes & CAN_TX_MAILBOX2) != RESET) + if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U) { /* Add cancellation request for Tx Mailbox 2 */ SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2); @@ -988,24 +1395,25 @@ HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMai uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) { uint32_t freelevel = 0U; + HAL_CAN_StateTypeDef state = hcan->State; - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Check Tx Mailbox 0 status */ - if ((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) + if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) { freelevel++; } /* Check Tx Mailbox 1 status */ - if ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) + if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) { freelevel++; } /* Check Tx Mailbox 2 status */ - if ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET) + if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) { freelevel++; } @@ -1030,12 +1438,13 @@ uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) { uint32_t status = 0U; + HAL_CAN_StateTypeDef state = hcan->State; /* Check function parameters */ assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Check pending transmission request on the selected Tx Mailboxes */ if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos)) @@ -1062,12 +1471,13 @@ uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox) { uint32_t timestamp = 0U; uint32_t transmitmailbox; + HAL_CAN_StateTypeDef state = hcan->State; /* Check function parameters */ assert_param(IS_CAN_TX_MAILBOX(TxMailbox)); - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Select the Tx mailbox */ transmitmailbox = POSITION_VAL(TxMailbox); @@ -1093,16 +1503,18 @@ uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox) */ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) { + HAL_CAN_StateTypeDef state = hcan->State; + assert_param(IS_CAN_RX_FIFO(RxFifo)); - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Check the Rx FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ { /* Check that the Rx FIFO 0 is not empty */ - if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == RESET) + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; @@ -1110,10 +1522,10 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, return HAL_ERROR; } } - else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */ + else /* Rx element is assigned to Rx FIFO 1 */ { /* Check that the Rx FIFO 1 is not empty */ - if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == RESET) + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; @@ -1138,14 +1550,14 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; /* Get the data */ - aData[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos; - aData[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos; - aData[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos; - aData[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos; - aData[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos; - aData[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos; - aData[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos; - aData[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos; + aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); + aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); + aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); + aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); + aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); + aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); + aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); + aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); /* Release the FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ @@ -1153,7 +1565,7 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, /* Release RX FIFO 0 */ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); } - else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */ + else /* Rx element is assigned to Rx FIFO 1 */ { /* Release RX FIFO 1 */ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); @@ -1182,12 +1594,13 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo) { uint32_t filllevel = 0U; + HAL_CAN_StateTypeDef state = hcan->State; /* Check function parameters */ assert_param(IS_CAN_RX_FIFO(RxFifo)); - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { if (RxFifo == CAN_RX_FIFO0) { @@ -1233,11 +1646,13 @@ uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo) */ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) { + HAL_CAN_StateTypeDef state = hcan->State; + /* Check function parameters */ assert_param(IS_CAN_IT(ActiveITs)); - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Enable the selected interrupts */ __HAL_CAN_ENABLE_IT(hcan, ActiveITs); @@ -1264,11 +1679,13 @@ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t */ HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs) { + HAL_CAN_StateTypeDef state = hcan->State; + /* Check function parameters */ assert_param(IS_CAN_IT(InactiveITs)); - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Disable the selected interrupts */ __HAL_CAN_DISABLE_IT(hcan, InactiveITs); @@ -1302,28 +1719,33 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) uint32_t esrflags = READ_REG(hcan->Instance->ESR); /* Transmit Mailbox empty interrupt management *****************************/ - if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != RESET) + if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) { /* Transmit Mailbox 0 management *****************************************/ - if ((tsrflags & CAN_TSR_RQCP0) != RESET) + if ((tsrflags & CAN_TSR_RQCP0) != 0U) { /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); - if ((tsrflags & CAN_TSR_TXOK0) != RESET) + if ((tsrflags & CAN_TSR_TXOK0) != 0U) { /* Transmission Mailbox 0 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox0CompleteCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { - if ((tsrflags & CAN_TSR_ALST0) != RESET) + if ((tsrflags & CAN_TSR_ALST0) != 0U) { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST0; } - else if ((tsrflags & CAN_TSR_TERR0) != RESET) + else if ((tsrflags & CAN_TSR_TERR0) != 0U) { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR0; @@ -1331,32 +1753,42 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) else { /* Transmission Mailbox 0 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox0AbortCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } } /* Transmit Mailbox 1 management *****************************************/ - if ((tsrflags & CAN_TSR_RQCP1) != RESET) + if ((tsrflags & CAN_TSR_RQCP1) != 0U) { /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); - if ((tsrflags & CAN_TSR_TXOK1) != RESET) + if ((tsrflags & CAN_TSR_TXOK1) != 0U) { /* Transmission Mailbox 1 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox1CompleteCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { - if ((tsrflags & CAN_TSR_ALST1) != RESET) + if ((tsrflags & CAN_TSR_ALST1) != 0U) { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST1; } - else if ((tsrflags & CAN_TSR_TERR1) != RESET) + else if ((tsrflags & CAN_TSR_TERR1) != 0U) { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR1; @@ -1364,32 +1796,42 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) else { /* Transmission Mailbox 1 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox1AbortCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } } /* Transmit Mailbox 2 management *****************************************/ - if ((tsrflags & CAN_TSR_RQCP2) != RESET) + if ((tsrflags & CAN_TSR_RQCP2) != 0U) { /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); - if ((tsrflags & CAN_TSR_TXOK2) != RESET) + if ((tsrflags & CAN_TSR_TXOK2) != 0U) { /* Transmission Mailbox 2 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox2CompleteCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { - if ((tsrflags & CAN_TSR_ALST2) != RESET) + if ((tsrflags & CAN_TSR_ALST2) != 0U) { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST2; } - else if ((tsrflags & CAN_TSR_TERR2) != RESET) + else if ((tsrflags & CAN_TSR_TERR2) != 0U) { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR2; @@ -1397,17 +1839,22 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) else { /* Transmission Mailbox 2 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox2AbortCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } } } /* Receive FIFO 0 overrun interrupt management *****************************/ - if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != RESET) + if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) { - if ((rf0rflags & CAN_RF0R_FOVR0) != RESET) + if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) { /* Set CAN error code to Rx Fifo 0 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV0; @@ -1418,35 +1865,45 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) } /* Receive FIFO 0 full interrupt management ********************************/ - if ((interrupts & CAN_IT_RX_FIFO0_FULL) != RESET) + if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) { - if ((rf0rflags & CAN_RF0R_FULL0) != RESET) + if ((rf0rflags & CAN_RF0R_FULL0) != 0U) { /* Clear FIFO 0 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); /* Receive FIFO 0 full Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo0FullCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0FullCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 0 message pending interrupt management *********************/ - if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != RESET) + if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) { /* Check if message is still pending */ - if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != RESET) + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) { /* Receive FIFO 0 mesage pending Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo0MsgPendingCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0MsgPendingCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 overrun interrupt management *****************************/ - if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != RESET) + if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) { - if ((rf1rflags & CAN_RF1R_FOVR1) != RESET) + if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) { /* Set CAN error code to Rx Fifo 1 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV1; @@ -1457,67 +1914,87 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) } /* Receive FIFO 1 full interrupt management ********************************/ - if ((interrupts & CAN_IT_RX_FIFO1_FULL) != RESET) + if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) { - if ((rf1rflags & CAN_RF1R_FULL1) != RESET) + if ((rf1rflags & CAN_RF1R_FULL1) != 0U) { /* Clear FIFO 1 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); /* Receive FIFO 1 full Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo1FullCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1FullCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 message pending interrupt management *********************/ - if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != RESET) + if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) { /* Check if message is still pending */ - if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != RESET) + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) { /* Receive FIFO 1 mesage pending Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo1MsgPendingCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1MsgPendingCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Sleep interrupt management *********************************************/ - if ((interrupts & CAN_IT_SLEEP_ACK) != RESET) + if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) { - if ((msrflags & CAN_MSR_SLAKI) != RESET) + if ((msrflags & CAN_MSR_SLAKI) != 0U) { /* Clear Sleep interrupt Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); /* Sleep Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->SleepCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_SleepCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* WakeUp interrupt management *********************************************/ - if ((interrupts & CAN_IT_WAKEUP) != RESET) + if ((interrupts & CAN_IT_WAKEUP) != 0U) { - if ((msrflags & CAN_MSR_WKUI) != RESET) + if ((msrflags & CAN_MSR_WKUI) != 0U) { /* Clear WakeUp Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); /* WakeUp Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->WakeUpFromRxMsgCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_WakeUpFromRxMsgCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Error interrupts management *********************************************/ - if ((interrupts & CAN_IT_ERROR) != RESET) + if ((interrupts & CAN_IT_ERROR) != 0U) { - if ((msrflags & CAN_MSR_ERRI) != RESET) + if ((msrflags & CAN_MSR_ERRI) != 0U) { /* Check Error Warning Flag */ - if (((interrupts & CAN_IT_ERROR_WARNING) != RESET) && - ((esrflags & CAN_ESR_EWGF) != RESET)) + if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && + ((esrflags & CAN_ESR_EWGF) != 0U)) { /* Set CAN error code to Error Warning */ errorcode |= HAL_CAN_ERROR_EWG; @@ -1526,8 +2003,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) } /* Check Error Passive Flag */ - if (((interrupts & CAN_IT_ERROR_PASSIVE) != RESET) && - ((esrflags & CAN_ESR_EPVF) != RESET)) + if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && + ((esrflags & CAN_ESR_EPVF) != 0U)) { /* Set CAN error code to Error Passive */ errorcode |= HAL_CAN_ERROR_EPV; @@ -1536,8 +2013,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) } /* Check Bus-off Flag */ - if (((interrupts & CAN_IT_BUSOFF) != RESET) && - ((esrflags & CAN_ESR_BOFF) != RESET)) + if (((interrupts & CAN_IT_BUSOFF) != 0U) && + ((esrflags & CAN_ESR_BOFF) != 0U)) { /* Set CAN error code to Bus-Off */ errorcode |= HAL_CAN_ERROR_BOF; @@ -1546,8 +2023,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) } /* Check Last Error Code Flag */ - if (((interrupts & CAN_IT_LAST_ERROR_CODE) != RESET) && - ((esrflags & CAN_ESR_LEC) != RESET)) + if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && + ((esrflags & CAN_ESR_LEC) != 0U)) { switch (esrflags & CAN_ESR_LEC) { @@ -1595,8 +2072,13 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) hcan->ErrorCode |= errorcode; /* Call Error callback function */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->ErrorCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } @@ -1881,21 +2363,25 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan) { HAL_CAN_StateTypeDef state = hcan->State; - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Check sleep mode acknowledge flag */ - if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) { /* Sleep mode is active */ state = HAL_CAN_STATE_SLEEP_ACTIVE; } /* Check sleep mode request flag */ - else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != RESET) + else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U) { /* Sleep mode request is pending */ state = HAL_CAN_STATE_SLEEP_PENDING; } + else + { + /* Neither sleep mode request nor sleep mode acknowledge */ + } } /* Return CAN state */ @@ -1923,9 +2409,10 @@ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan) { HAL_StatusTypeDef status = HAL_OK; + HAL_CAN_StateTypeDef state = hcan->State; - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Reset CAN error code */ hcan->ErrorCode = 0U; diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_comp.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_comp.c index 7321c094b3..62cbea9361 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_comp.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_comp.c @@ -85,6 +85,63 @@ (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function. The only way to unlock the comparator is a device hardware reset. + *** Callback registration *** + ============================================= + [..] + + The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1, + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_COMP_RegisterCallback() + to register an interrupt callback. + [..] + + Function @ref HAL_COMP_RegisterCallback() allows to register following callbacks: + (+) TriggerCallback : callback for COMP trigger. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + + Use function @ref HAL_COMP_UnRegisterCallback to reset a callback to the default + weak function. + [..] + + @ref HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TriggerCallback : callback for COMP trigger. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + + By default, after the @ref HAL_COMP_Init() and when the state is @ref HAL_COMP_STATE_RESET + all callbacks are set to the corresponding weak functions: + example @ref HAL_COMP_TriggerCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit() only when + these callbacks are null (not registered beforehand). + [..] + + If MspInit or MspDeInit are not null, the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + + Callbacks can be registered/unregistered in @ref HAL_COMP_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in @ref HAL_COMP_STATE_READY or @ref HAL_COMP_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + [..] + + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_COMP_RegisterCallback() before calling @ref HAL_COMP_DeInit() + or @ref HAL_COMP_Init() function. + [..] + + When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + @endverbatim ****************************************************************************** @@ -149,14 +206,14 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" -#ifdef HAL_COMP_MODULE_ENABLED - -#if defined (COMP1) || defined (COMP2) - /** @addtogroup STM32L4xx_HAL_Driver * @{ */ +#ifdef HAL_COMP_MODULE_ENABLED + +#if defined (COMP1) || defined (COMP2) + /** @defgroup COMP COMP * @brief COMP HAL module driver * @{ @@ -248,6 +305,9 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) /* Allocate lock resource and initialize it */ hcomp->Lock = HAL_UNLOCKED; + /* Set COMP error code to none */ + COMP_CLEAR_ERRORCODE(hcomp); + /* Init SYSCFG and the low level hardware to access comparators */ /* Note: HAL_COMP_Init() calls __HAL_RCC_SYSCFG_CLK_ENABLE() */ /* to enable internal control clock of the comparators. */ @@ -259,8 +319,21 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) /* in "HAL_COMP_MspInit()". */ __HAL_RCC_SYSCFG_CLK_ENABLE(); +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) + /* Init the COMP Callback settings */ + hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */ + + if (hcomp->MspInitCallback == NULL) + { + hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hcomp->MspInitCallback(hcomp); +#else /* Init the low level hardware */ HAL_COMP_MspInit(hcomp); +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ } /* Memorize voltage scaler state before initialization */ @@ -415,8 +488,18 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) /* Set COMP_CSR register to reset value */ WRITE_REG(hcomp->Instance->CSR, 0x00000000U); - /* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */ +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) + if (hcomp->MspDeInitCallback == NULL) + { + hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, RCC clock, NVIC */ + hcomp->MspDeInitCallback(hcomp); +#else + /* DeInit the low level hardware: GPIO, RCC clock, NVIC */ HAL_COMP_MspDeInit(hcomp); +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ /* Set HAL COMP handle state */ hcomp->State = HAL_COMP_STATE_RESET; @@ -458,6 +541,166 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) */ } +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User COMP Callback + * To be used instead of the weak predefined callback + * @param hcomp Pointer to a COMP_HandleTypeDef structure that contains + * the configuration information for the specified COMP. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID + * @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_COMP_STATE_READY == hcomp->State) + { + switch (CallbackID) + { + case HAL_COMP_TRIGGER_CB_ID : + hcomp->TriggerCallback = pCallback; + break; + + case HAL_COMP_MSPINIT_CB_ID : + hcomp->MspInitCallback = pCallback; + break; + + case HAL_COMP_MSPDEINIT_CB_ID : + hcomp->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_COMP_STATE_RESET == hcomp->State) + { + switch (CallbackID) + { + case HAL_COMP_MSPINIT_CB_ID : + hcomp->MspInitCallback = pCallback; + break; + + case HAL_COMP_MSPDEINIT_CB_ID : + hcomp->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a COMP Callback + * COMP callback is redirected to the weak predefined callback + * @param hcomp Pointer to a COMP_HandleTypeDef structure that contains + * the configuration information for the specified COMP. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID + * @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_COMP_STATE_READY == hcomp->State) + { + switch (CallbackID) + { + case HAL_COMP_TRIGGER_CB_ID : + hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */ + break; + + case HAL_COMP_MSPINIT_CB_ID : + hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_COMP_MSPDEINIT_CB_ID : + hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_COMP_STATE_RESET == hcomp->State) + { + switch (CallbackID) + { + case HAL_COMP_MSPINIT_CB_ID : + hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_COMP_MSPDEINIT_CB_ID : + hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + /** * @} */ @@ -593,7 +836,11 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) } /* COMP trigger user callback */ +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) + hcomp->TriggerCallback(hcomp); +#else HAL_COMP_TriggerCallback(hcomp); +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ } } @@ -679,7 +926,7 @@ uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) } /** - * @brief Comparator callback. + * @brief Comparator trigger callback. * @param hcomp COMP handle * @retval None */ @@ -733,8 +980,17 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) } /** - * @} + * @brief Return the COMP error code. + * @param hcomp COMP handle + * @retval COMP error code */ +uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp) +{ + /* Check the parameters */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + return hcomp->ErrorCode; +} /** * @} @@ -752,4 +1008,8 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) #endif /* HAL_COMP_MODULE_ENABLED */ +/** + * @} + */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c index bc77a5efb0..7d7289c373 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c @@ -4,7 +4,7 @@ * @author MCD Application Team * @brief CRC HAL module driver. * This file provides firmware functions to manage the following - * functionalities of the CRC peripheral: + * functionalities of the Cyclic Redundancy Check (CRC) peripheral: * + Initialization and de-initialization functions * + Peripheral Control functions * + Peripheral State functions @@ -113,13 +113,13 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3 /** * @brief Initialize the CRC according to the specified * parameters in the CRC_InitTypeDef and create the associated handle. - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { /* Check the CRC handle allocation */ - if(hcrc == NULL) + if (hcrc == NULL) { return HAL_ERROR; } @@ -127,11 +127,10 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); - if(hcrc->State == HAL_CRC_STATE_RESET) + if (hcrc->State == HAL_CRC_STATE_RESET) { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); } @@ -190,13 +189,13 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) /** * @brief DeInitialize the CRC peripheral. - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) { /* Check the CRC handle allocation */ - if(hcrc == NULL) + if (hcrc == NULL) { return HAL_ERROR; } @@ -205,7 +204,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); /* Check the CRC peripheral state */ - if(hcrc->State == HAL_CRC_STATE_BUSY) + if (hcrc->State == HAL_CRC_STATE_BUSY) { return HAL_BUSY; } @@ -217,7 +216,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) __HAL_CRC_DR_RESET(hcrc); /* Reset IDR register content */ - CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ; + CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR); /* DeInit the low level hardware */ HAL_CRC_MspDeInit(hcrc); @@ -234,7 +233,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) /** * @brief Initializes the CRC MSP. - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval None */ __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) @@ -249,7 +248,7 @@ __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) /** * @brief DeInitialize the CRC MSP. - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval None */ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) @@ -275,7 +274,7 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) =============================================================================== [..] This section provides functions allowing to: (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer - using the combination of the previous CRC value and the new one + using combination of the previous CRC value and the new one. [..] or @@ -289,10 +288,10 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) /** * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer * starting with the previously computed CRC as initialization value. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer, exact input data format is + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer, exact input data format is * provided by hcrc->InputDataFormat. - * @param BufferLength: input data buffer length (number of bytes if pBuffer + * @param BufferLength input data buffer length (number of bytes if pBuffer * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, * number of words if pBuffer type is * uint32_t). * @note By default, the API expects a uint32_t pointer as input buffer parameter. @@ -303,8 +302,8 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) */ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { - uint32_t index = 0; /* CRC input data buffer index */ - uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */ + uint32_t index; /* CRC input data buffer index */ + uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ /* Process locked */ __HAL_LOCK(hcrc); @@ -316,7 +315,7 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ { case CRC_INPUTDATA_FORMAT_WORDS: /* Enter Data to the CRC calculator */ - for(index = 0; index < BufferLength; index++) + for (index = 0U; index < BufferLength; index++) { hcrc->Instance->DR = pBuffer[index]; } @@ -324,13 +323,12 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ break; case CRC_INPUTDATA_FORMAT_BYTES: - temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength); + temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); break; case CRC_INPUTDATA_FORMAT_HALFWORDS: - temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength); + temp = CRC_Handle_16(hcrc, (uint16_t *)pBuffer, BufferLength); break; - default: break; } @@ -345,14 +343,13 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ return temp; } - /** * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer * starting with hcrc->Instance->INIT as initialization value. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer, exact input data format is + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer, exact input data format is * provided by hcrc->InputDataFormat. - * @param BufferLength: input data buffer length (number of bytes if pBuffer + * @param BufferLength input data buffer length (number of bytes if pBuffer * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, * number of words if pBuffer type is * uint32_t). * @note By default, the API expects a uint32_t pointer as input buffer parameter. @@ -363,8 +360,8 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ */ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { - uint32_t index = 0; /* CRC input data buffer index */ - uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */ + uint32_t index; /* CRC input data buffer index */ + uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ /* Process locked */ __HAL_LOCK(hcrc); @@ -380,7 +377,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t { case CRC_INPUTDATA_FORMAT_WORDS: /* Enter 32-bit input data to the CRC calculator */ - for(index = 0; index < BufferLength; index++) + for (index = 0U; index < BufferLength; index++) { hcrc->Instance->DR = pBuffer[index]; } @@ -389,12 +386,12 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t case CRC_INPUTDATA_FORMAT_BYTES: /* Specific 8-bit input data handling */ - temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength); + temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); break; case CRC_INPUTDATA_FORMAT_HALFWORDS: /* Specific 16-bit input data handling */ - temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength); + temp = CRC_Handle_16(hcrc, (uint16_t *)pBuffer, BufferLength); break; default: @@ -431,7 +428,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t /** * @brief Return the CRC handle state. - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval HAL state */ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) @@ -448,84 +445,85 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) * @} */ -/** @defgroup CRC_Private_Functions CRC Private Functions +/** @addtogroup CRC_Private_Functions * @{ */ /** * @brief Enter 8-bit input data to the CRC calculator. * Specific data handling to optimize processing time. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer - * @param BufferLength: input data buffer length + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) { - uint32_t i = 0; /* input data buffer index */ + uint32_t i; /* input data buffer index */ uint16_t data; __IO uint16_t *pReg; - /* Processing time optimization: 4 bytes are entered in a row with a single word write, - * last bytes must be carefully fed to the CRC calculator to ensure a correct type - * handling by the IP */ - for(i = 0; i < (BufferLength/4); i++) - { - hcrc->Instance->DR = ((uint32_t)pBuffer[4*i]<<24) | ((uint32_t)pBuffer[4*i+1]<<16) | ((uint32_t)pBuffer[4*i+2]<<8) | (uint32_t)pBuffer[4*i+3]; - } - /* last bytes specific handling */ - if ((BufferLength%4) != 0) - { - if (BufferLength%4 == 1) - { - *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4*i]; - } - if (BufferLength%4 == 2) - { - data = (uint16_t)(pBuffer[4*i]<<8) | (uint16_t)pBuffer[4*i+1]; - pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); - *pReg = data; - } - if (BufferLength%4 == 3) - { - data = (uint16_t)(pBuffer[4*i]<<8) | (uint16_t)pBuffer[4*i+1]; - pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); - *pReg = data; - - *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4*i+2]; - } - } + /* Processing time optimization: 4 bytes are entered in a row with a single word write, + * last bytes must be carefully fed to the CRC calculator to ensure a correct type + * handling by the IP */ + for (i = 0U; i < (BufferLength / 4U); i++) + { + hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ + ((uint32_t)pBuffer[4U * i + 1U] << 16U) | \ + ((uint32_t)pBuffer[4U * i + 2U] << 8U) | \ + (uint32_t)pBuffer[4U * i + 3U]; + } + /* last bytes specific handling */ + if ((BufferLength % 4U) != 0U) + { + if (BufferLength % 4U == 1U) + { + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; + } + if (BufferLength % 4U == 2U) + { + data = (uint16_t)(pBuffer[4U * i] << 8U) | (uint16_t)pBuffer[4U * i + 1U]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); + *pReg = data; + } + if (BufferLength % 4U == 3U) + { + data = (uint16_t)(pBuffer[4U * i] << 8U) | (uint16_t)pBuffer[4U * i + 1U]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); + *pReg = data; + + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i + 2U]; + } + } /* Return the CRC computed value */ return hcrc->Instance->DR; } - - /** * @brief Enter 16-bit input data to the CRC calculator. * Specific data handling to optimize processing time. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer - * @param BufferLength: input data buffer length + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) { - uint32_t i = 0; /* input data buffer index */ + uint32_t i; /* input data buffer index */ __IO uint16_t *pReg; /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure * a correct type handling by the IP */ - for(i = 0; i < (BufferLength/2); i++) + for (i = 0U; i < (BufferLength / 2U); i++) { - hcrc->Instance->DR = ((uint32_t)pBuffer[2*i]<<16) | (uint32_t)pBuffer[2*i+1]; + hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[2U * i + 1U]; } - if ((BufferLength%2) != 0) + if ((BufferLength % 2U) != 0U) { pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); - *pReg = pBuffer[2*i]; + *pReg = pBuffer[2U * i]; } /* Return the CRC computed value */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c index bb03643fc8..88ad1de311 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c @@ -3,9 +3,9 @@ * @file stm32l4xx_hal_crc_ex.c * @author MCD Application Team * @brief Extended CRC HAL module driver. - * This file provides firmware functions to manage the extended - * functionalities of the CRC peripheral. - * + * This file provides firmware functions to manage the extended + * functionalities of the CRC peripheral. + * @verbatim ================================================================================ ##### How to use this driver ##### @@ -42,7 +42,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -73,7 +73,7 @@ /** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions * @brief Extended Initialization and Configuration functions. * -@verbatim +@verbatim =============================================================================== ##### Extended configuration functions ##### =============================================================================== @@ -81,7 +81,7 @@ (+) Configure the generating polynomial (+) Configure the input data inversion (+) Configure the output data inversion - + @endverbatim * @{ */ @@ -89,123 +89,129 @@ /** * @brief Initialize the CRC polynomial if different from default one. - * @param hcrc: CRC handle - * @param Pol: CRC generating polynomial (7, 8, 16 or 32-bit long). + * @param hcrc CRC handle + * @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long). * This parameter is written in normal representation, e.g. - * @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 - * @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021 - * @param PolyLength: CRC polynomial length. + * @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 + * @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021 + * @param PolyLength CRC polynomial length. * This parameter can be one of the following values: * @arg @ref CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7) * @arg @ref CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8) * @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16) - * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32) + * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32) * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) { - uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */ + HAL_StatusTypeDef status = HAL_OK; + uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */ /* Check the parameters */ assert_param(IS_CRC_POL_LENGTH(PolyLength)); - + /* check polynomial definition vs polynomial size: * polynomial length must be aligned with polynomial - * definition. HAL_ERROR is reported if Pol degree is + * definition. HAL_ERROR is reported if Pol degree is * larger than that indicated by PolyLength. * Look for MSB position: msb will contain the degree of * the second to the largest polynomial member. E.g., for * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ - while (((Pol & (1U << msb)) == 0) && (msb-- > 0)) {} + while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << msb)) == 0U)) + { + } switch (PolyLength) { case CRC_POLYLENGTH_7B: - if (msb >= HAL_CRC_LENGTH_7B) + if (msb >= HAL_CRC_LENGTH_7B) { - return HAL_ERROR; + status = HAL_ERROR; } break; case CRC_POLYLENGTH_8B: if (msb >= HAL_CRC_LENGTH_8B) { - return HAL_ERROR; - } + status = HAL_ERROR; + } break; case CRC_POLYLENGTH_16B: if (msb >= HAL_CRC_LENGTH_16B) { - return HAL_ERROR; - } + status = HAL_ERROR; + } break; + case CRC_POLYLENGTH_32B: /* no polynomial definition vs. polynomial length issue possible */ - break; + break; default: - return HAL_ERROR; + status = HAL_ERROR; + break; } + if (status == HAL_OK) + { + /* set generating polynomial */ + WRITE_REG(hcrc->Instance->POL, Pol); - /* set generating polynomial */ - WRITE_REG(hcrc->Instance->POL, Pol); - - /* set generating polynomial size */ - MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); - + /* set generating polynomial size */ + MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); + } /* Return function status */ - return HAL_OK; + return status; } /** * @brief Set the Reverse Input data mode. - * @param hcrc: CRC handle - * @param InputReverseMode: Input Data inversion mode. + * @param hcrc CRC handle + * @param InputReverseMode Input Data inversion mode. * This parameter can be one of the following values: * @arg @ref CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value) * @arg @ref CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal * @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal - * @arg @ref CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal + * @arg @ref CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode) -{ +{ /* Check the parameters */ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode)); - + /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; /* set input data inversion mode */ - MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode); /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; - + /* Return function status */ return HAL_OK; } /** * @brief Set the Reverse Output data mode. - * @param hcrc: CRC handle - * @param OutputReverseMode: Output Data inversion mode. + * @param hcrc CRC handle + * @param OutputReverseMode Output Data inversion mode. * This parameter can be one of the following values: * @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value) - * @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD) + * @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD) * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode) { /* Check the parameters */ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode)); - + /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; /* set output data inversion mode */ - MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode); - + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode); + /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; - + /* Return function status */ return HAL_OK; } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp.c index 6d58944e4c..ff83ce4d7c 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp.c @@ -3,21 +3,21 @@ * @file stm32l4xx_hal_cryp.c * @author MCD Application Team * @brief CRYP HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Cryptography (CRYP) peripheral: * + Initialization and de-initialization functions * + Processing functions using polling mode * + Processing functions using interrupt mode * + Processing functions using DMA mode * + Peripheral State functions - * + * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] The CRYP HAL driver can be used as follows: - + (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit(): (++) Enable the CRYP interface clock using __HAL_RCC_AES_CLK_ENABLE() (++) In case of using interrupts (e.g. HAL_CRYP_AES_IT()) @@ -25,7 +25,7 @@ (+++) Enable the AES IRQ handler using HAL_NVIC_EnableIRQ() (+++) In AES IRQ handler, call HAL_CRYP_IRQHandler() (++) In case of using DMA to control data transfer (e.g. HAL_CRYPEx_AES_DMA()) - (+++) Enable the DMA2 interface clock using + (+++) Enable the DMA2 interface clock using __HAL_RCC_DMA2_CLK_ENABLE() (+++) Configure and enable two DMA channels one for managing data transfer from memory to peripheral (input channel) and another channel for managing data @@ -36,14 +36,14 @@ interrupt on the two DMA channels. The output channel should have higher priority than the input channel. Resort to HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() - + (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures: (++) The data type: 1-bit, 8-bit, 16-bit and 32-bit (++) The AES operating mode (encryption, key derivation and/or decryption) - (++) The AES chaining mode (ECB, CBC, CTR, GCM, GMAC, CMAC when applicable, CCM when applicable) + (++) The AES chaining mode (ECB, CBC, CTR, GCM, GMAC, CMAC when applicable, CCM when applicable) (++) The encryption/decryption key if so required (++) The initialization vector or nonce if applicable (not used in ECB mode). - + (#)Three processing (encryption/decryption) functions are available: (++) Polling mode: encryption and decryption APIs are blocking functions i.e. they process the data and wait till the processing is finished @@ -51,9 +51,60 @@ i.e. they process the data under interrupt (++) DMA mode: encryption and decryption APIs are not blocking functions i.e. the data transfer is ensured by DMA - + (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. + *** Callback registration *** + =================================== + [..] + (#) The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use function @ref HAL_CRYP_RegisterCallback() to register a user callback. + + (#) Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks: + (+) InCpltCallback : callback for input DMA transfer completion. + (+) OutCpltCallback : callback for output DMA transfer completion. + (+) CompCpltCallback : callback for computation completion. + (+) ErrorCallback : callback for error. + (+) MspInitCallback : CRYP MspInit. + (+) MspDeInitCallback : CRYP MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + (#) Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) InCpltCallback : callback for input DMA transfer completion. + (+) OutCpltCallback : callback for output DMA transfer completion. + (+) CompCpltCallback : callback for computation completion. + (+) ErrorCallback : callback for error. + (+) MspInitCallback : CRYP MspInit. + (+) MspDeInitCallback : CRYP MspDeInit. + + (#) By default, after the @ref HAL_CRYP_Init and if the state is HAL_CRYP_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions: + examples @ref HAL_CRYP_InCpltCallback(), @ref HAL_CRYP_ErrorCallback() + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_CRYP_Init + and @ref HAL_CRYP_DeInit only when these callbacks are null (not registered beforehand) + If not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init and @ref HAL_CRYP_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_CRYP_RegisterCallback before calling @ref HAL_CRYP_DeInit + or @ref HAL_�CRYP_Init function. + + When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + @endverbatim ****************************************************************************** * @attention @@ -82,15 +133,15 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" #ifdef HAL_CRYP_MODULE_ENABLED -#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(AES) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -127,92 +178,92 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp); * @{ */ -/** @defgroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions - * @brief Initialization and Configuration functions. +/** @defgroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions + * @brief Initialization and Configuration functions. * -@verbatim +@verbatim ============================================================================== ##### Initialization and deinitialization functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Initialize the CRYP according to the specified parameters + (+) Initialize the CRYP according to the specified parameters in the CRYP_InitTypeDef and creates the associated handle (+) DeInitialize the CRYP peripheral (+) Initialize the CRYP MSP (MCU Specific Package) (+) De-Initialize the CRYP MSP - + [..] (@) Specific care must be taken to format the key and the Initialization Vector IV! - - [..] If the key is defined as a 128-bit long array key[127..0] = {b127 ... b0} where - b127 is the MSB and b0 the LSB, the key must be stored in MCU memory + + [..] If the key is defined as a 128-bit long array key[127..0] = {b127 ... b0} where + b127 is the MSB and b0 the LSB, the key must be stored in MCU memory (+) as a sequence of words where the MSB word comes first (occupies the - lowest memory address) + lowest memory address) (+) where each word is byte-swapped: (++) address n+0 : 0b b103 .. b96 b111 .. b104 b119 .. b112 b127 .. b120 (++) address n+4 : 0b b71 .. b64 b79 .. b72 b87 .. b80 b95 .. b88 (++) address n+8 : 0b b39 .. b32 b47 .. b40 b55 .. b48 b63 .. b56 - (++) address n+C : 0b b7 .. b0 b15 .. b8 b23 .. b16 b31 .. b24 + (++) address n+C : 0b b7 .. b0 b15 .. b8 b23 .. b16 b31 .. b24 [..] Hereafter, another illustration when considering a 128-bit long key made of 16 bytes {B15..B0}. - The 4 32-bit words that make the key must be stored as follows in MCU memory: + The 4 32-bit words that make the key must be stored as follows in MCU memory: (+) address n+0 : 0x B12 B13 B14 B15 (+) address n+4 : 0x B8 B9 B10 B11 (+) address n+8 : 0x B4 B5 B6 B7 - (+) address n+C : 0x B0 B1 B2 B3 - [..] which leads to the expected setting - (+) AES_KEYR3 = 0x B15 B14 B13 B12 - (+) AES_KEYR2 = 0x B11 B10 B9 B8 - (+) AES_KEYR1 = 0x B7 B6 B5 B4 - (+) AES_KEYR0 = 0x B3 B2 B1 B0 - - [..] Same format must be applied for a 256-bit long key made of 32 bytes {B31..B0}. + (+) address n+C : 0x B0 B1 B2 B3 + [..] which leads to the expected setting + (+) AES_KEYR3 = 0x B15 B14 B13 B12 + (+) AES_KEYR2 = 0x B11 B10 B9 B8 + (+) AES_KEYR1 = 0x B7 B6 B5 B4 + (+) AES_KEYR0 = 0x B3 B2 B1 B0 + + [..] Same format must be applied for a 256-bit long key made of 32 bytes {B31..B0}. The 8 32-bit words that make the key must be stored as follows in MCU memory: (+) address n+00 : 0x B28 B29 B30 B31 (+) address n+04 : 0x B24 B25 B26 B27 (+) address n+08 : 0x B20 B21 B22 B23 - (+) address n+0C : 0x B16 B17 B18 B19 + (+) address n+0C : 0x B16 B17 B18 B19 (+) address n+10 : 0x B12 B13 B14 B15 (+) address n+14 : 0x B8 B9 B10 B11 (+) address n+18 : 0x B4 B5 B6 B7 - (+) address n+1C : 0x B0 B1 B2 B3 - [..] which leads to the expected setting - (+) AES_KEYR7 = 0x B31 B30 B29 B28 - (+) AES_KEYR6 = 0x B27 B26 B25 B24 - (+) AES_KEYR5 = 0x B23 B22 B21 B20 - (+) AES_KEYR4 = 0x B19 B18 B17 B16 - (+) AES_KEYR3 = 0x B15 B14 B13 B12 - (+) AES_KEYR2 = 0x B11 B10 B9 B8 - (+) AES_KEYR1 = 0x B7 B6 B5 B4 - (+) AES_KEYR0 = 0x B3 B2 B1 B0 - - [..] Initialization Vector IV (4 32-bit words) format must follow the same as - that of a 128-bit long key. - - [..] - + (+) address n+1C : 0x B0 B1 B2 B3 + [..] which leads to the expected setting + (+) AES_KEYR7 = 0x B31 B30 B29 B28 + (+) AES_KEYR6 = 0x B27 B26 B25 B24 + (+) AES_KEYR5 = 0x B23 B22 B21 B20 + (+) AES_KEYR4 = 0x B19 B18 B17 B16 + (+) AES_KEYR3 = 0x B15 B14 B13 B12 + (+) AES_KEYR2 = 0x B11 B10 B9 B8 + (+) AES_KEYR1 = 0x B7 B6 B5 B4 + (+) AES_KEYR0 = 0x B3 B2 B1 B0 + + [..] Initialization Vector IV (4 32-bit words) format must follow the same as + that of a 128-bit long key. + + [..] + @endverbatim * @{ */ /** * @brief Initialize the CRYP according to the specified - * parameters in the CRYP_InitTypeDef and initialize the associated handle. - * @note Specific care must be taken to format the key and the Initialization Vector IV - * stored in the MCU memory before calling HAL_CRYP_Init(). Refer to explanations - * hereabove. + * parameters in the CRYP_InitTypeDef and initialize the associated handle. + * @note Specific care must be taken to format the key and the Initialization Vector IV + * stored in the MCU memory before calling HAL_CRYP_Init(). Refer to explanations + * hereabove. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) -{ +{ /* Check the CRYP handle allocation */ if(hcryp == NULL) { return HAL_ERROR; } - + /* Check the instance */ assert_param(IS_AES_ALL_INSTANCE(hcryp->Instance)); - + /* Check the parameters */ assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize)); assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType)); @@ -223,42 +274,62 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) assert_param(IS_CRYP_CHAINMODE(hcryp->Init.ChainingMode)); } assert_param(IS_CRYP_WRITE(hcryp->Init.KeyWriteFlag)); - + /*========================================================*/ /* Check the proper operating/chaining modes combinations */ - /*========================================================*/ + /*========================================================*/ /* Check the proper chaining when the operating mode is key derivation and decryption */ #if defined(AES_CR_NPBLB) if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT) &&\ ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CTR) \ || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) \ || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM))) -#else +#else if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT) &&\ ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CTR) \ || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) \ || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))) -#endif +#endif { return HAL_ERROR; - } - /* Check that key derivation is not set in CMAC mode or CCM mode when applicable */ + } + /* Check that key derivation is not set in CMAC mode or CCM mode when applicable */ #if defined(AES_CR_NPBLB) - if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) + if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) && (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM)) -#else - if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) +#else + if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) && (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)) -#endif +#endif { return HAL_ERROR; } - - + + /*================*/ /* Initialization */ - /*================*/ + /*================*/ /* Initialization start */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + if (hcryp->State == HAL_CRYP_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcryp->Lock = HAL_UNLOCKED; + + /* Reset Callback pointers in HAL_CRYP_STATE_RESET only */ + hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak (surcharged) input DMA transfer completion callback */ + hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak (surcharged) output DMA transfer completion callback */ + hcryp->CompCpltCallback = HAL_CRYPEx_ComputationCpltCallback; /* Legacy weak (surcharged) computation completion callback */ + hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak (surcharged) error callback */ + if(hcryp->MspInitCallback == NULL) + { + hcryp->MspInitCallback = HAL_CRYP_MspInit; + } + + /* Init the low level hardware */ + hcryp->MspInitCallback(hcryp); + } +#else if(hcryp->State == HAL_CRYP_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -267,33 +338,34 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) /* Init the low level hardware */ HAL_CRYP_MspInit(hcryp); } - +#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ + /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - + hcryp->State = HAL_CRYP_STATE_BUSY; + /* Disable the Peripheral */ __HAL_CRYP_DISABLE(hcryp); - + /*=============================================================*/ - /* AES initialization common to all operating modes */ + /* AES initialization common to all operating modes */ /*=============================================================*/ /* Set the Key size selection */ MODIFY_REG(hcryp->Instance->CR, AES_CR_KEYSIZE, hcryp->Init.KeySize); - + /* Set the default CRYP phase when this parameter is not used. Phase is updated below in case of GCM/GMAC(/CMAC)(/CCM) setting. */ hcryp->Phase = HAL_CRYP_PHASE_NOT_USED; - - + + /*=============================================================*/ - /* Carry on the initialization based on the AES operating mode */ + /* Carry on the initialization based on the AES operating mode */ /*=============================================================*/ - /* Key derivation */ + /* Key derivation */ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) { MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_ALGOMODE_KEYDERIVATION); - + /* Configure the Key registers */ if (CRYP_SetKey(hcryp) != HAL_OK) { @@ -302,46 +374,46 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) } else /* Encryption / Decryption (with or without key derivation) / authentication */ - { -#if !defined(AES_CR_NPBLB) + { +#if !defined(AES_CR_NPBLB) /* Set data type, operating and chaining modes. In case of GCM or GMAC, data type is forced to 0b00 */ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) { - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_MODE|AES_CR_CHMOD, hcryp->Init.OperatingMode|hcryp->Init.ChainingMode); + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_MODE|AES_CR_CHMOD, hcryp->Init.OperatingMode|hcryp->Init.ChainingMode); } else -#endif +#endif { MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_MODE|AES_CR_CHMOD, hcryp->Init.DataType|hcryp->Init.OperatingMode|hcryp->Init.ChainingMode); } - - /* Specify the encryption/decryption phase in case of Galois counter mode (GCM), + + /* Specify the encryption/decryption phase in case of Galois counter mode (GCM), Galois message authentication code (GMAC), cipher message authentication code (CMAC) when applicable or Counter with Cipher Mode (CCM) when applicable */ -#if defined(AES_CR_NPBLB) +#if defined(AES_CR_NPBLB) if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM)) #else if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)) -#endif +#endif { MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, hcryp->Init.GCMCMACPhase); hcryp->Phase = HAL_CRYP_PHASE_START; } - + /* Configure the Key registers if no need to bypass this step */ if (hcryp->Init.KeyWriteFlag == CRYP_KEY_WRITE_ENABLE) { if (CRYP_SetKey(hcryp) != HAL_OK) { return HAL_ERROR; - } + } } - + /* If applicable, configure the Initialization Vector */ if (hcryp->Init.ChainingMode != CRYP_CHAINMODE_AES_ECB) { @@ -351,34 +423,34 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) } } } - -#if defined(AES_CR_NPBLB) + +#if defined(AES_CR_NPBLB) /* Clear NPBLB field */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB); -#endif +#endif /* Reset CrypInCount and CrypOutCount */ hcryp->CrypInCount = 0; hcryp->CrypOutCount = 0; - + /* Reset ErrorCode field */ hcryp->ErrorCode = HAL_CRYP_ERROR_NONE; - + /* Reset Mode suspension request */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; - + /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; - + /* Enable the Peripheral */ __HAL_CRYP_ENABLE(hcryp); - + /* Return function status */ return HAL_OK; } /** - * @brief DeInitialize the CRYP peripheral. + * @brief DeInitialize the CRYP peripheral. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status @@ -390,29 +462,39 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) { return HAL_ERROR; } - + /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; - + /* Set the default CRYP phase */ hcryp->Phase = HAL_CRYP_PHASE_READY; - + /* Reset CrypInCount and CrypOutCount */ hcryp->CrypInCount = 0; hcryp->CrypOutCount = 0; - + /* Disable the CRYP Peripheral Clock */ __HAL_CRYP_DISABLE(hcryp); - + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + if(hcryp->MspDeInitCallback == NULL) + { + hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; + } + + /* DeInit the low level hardware */ + hcryp->MspDeInitCallback(hcryp); +#else /* DeInit the low level hardware: CLOCK, NVIC.*/ HAL_CRYP_MspDeInit(hcryp); - +#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ + /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_RESET; - + /* Release Lock */ __HAL_UNLOCK(hcryp); - + /* Return function status */ return HAL_OK; } @@ -453,13 +535,13 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) * @} */ -/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions - * @brief Processing functions. +/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions + * @brief Processing functions. * -@verbatim +@verbatim ============================================================================== ##### AES processing functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: (+) Encrypt plaintext using AES algorithm in different chaining modes (+) Decrypt cyphertext using AES algorithm in different chaining modes @@ -471,8 +553,8 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) @endverbatim * @{ */ - - + + /** * @brief Encrypt pPlainData in AES ECB encryption mode. The cypher data are available in pCypherData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains @@ -480,9 +562,9 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param Timeout: Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -502,7 +584,7 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout); } - + /** * @brief Encrypt pPlainData in AES CBC encryption mode with key derivation. The cypher data are available in pCypherData. @@ -513,11 +595,11 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP * @param pCypherData: Pointer to the cyphertext buffer * @param Timeout: Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) -{ +{ /* Re-initialize AES IP with proper parameters */ if (HAL_CRYP_DeInit(hcryp) != HAL_OK) { @@ -530,7 +612,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP { return HAL_ERROR; } - + return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout); } @@ -542,9 +624,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param Timeout: Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -566,16 +648,16 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP } /** - * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation, + * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation, * the decyphered data are available in pPlainData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param Timeout: Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -597,16 +679,16 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC } /** - * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation, + * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation, * the decyphered data are available in pPlainData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param Timeout: Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -623,12 +705,12 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC { return HAL_ERROR; } - + return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout); } /** - * @brief Decrypt pCypherData in AES CTR decryption mode, + * @brief Decrypt pCypherData in AES CTR decryption mode, * the decyphered data are available in pPlainData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module @@ -637,7 +719,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC * @param pPlainData: Pointer to the plaintext buffer * @param Timeout: Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -653,8 +735,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC if (HAL_CRYP_Init(hcryp) != HAL_OK) { return HAL_ERROR; - } - + } + return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout); } @@ -667,7 +749,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pCypherData: Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -683,21 +765,21 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t if (HAL_CRYP_Init(hcryp) != HAL_OK) { return HAL_ERROR; - } - + } + return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData); } /** * @brief Encrypt pPlainData in AES CBC encryption mode using Interrupt, - * the cypher data are available in pCypherData. + * the cypher data are available in pCypherData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pCypherData: Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -714,21 +796,21 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t { return HAL_ERROR; } - + return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData); } - + /** * @brief Encrypt pPlainData in AES CTR encryption mode using Interrupt, - * the cypher data are available in pCypherData. + * the cypher data are available in pCypherData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pCypherData: Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -745,20 +827,20 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t { return HAL_ERROR; } - + return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData); } /** * @brief Decrypt pCypherData in AES ECB decryption mode using Interrupt, - * the decyphered data are available in pPlainData. + * the decyphered data are available in pPlainData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pPlainData: Pointer to the plaintext buffer. * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -775,20 +857,20 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t { return HAL_ERROR; } - + return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData); } /** * @brief Decrypt pCypherData in AES CBC decryption mode using Interrupt, - * the decyphered data are available in pPlainData. + * the decyphered data are available in pPlainData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pPlainData: Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -805,20 +887,20 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t { return HAL_ERROR; } - + return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData); } /** * @brief Decrypt pCypherData in AES CTR decryption mode using Interrupt, - * the decyphered data are available in pPlainData. + * the decyphered data are available in pPlainData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pPlainData: Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -834,14 +916,14 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t if (HAL_CRYP_Init(hcryp) != HAL_OK) { return HAL_ERROR; - } - + } + return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData); } /** * @brief Encrypt pPlainData in AES ECB encryption mode using DMA, - * the cypher data are available in pCypherData. + * the cypher data are available in pCypherData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer @@ -849,7 +931,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t * @param pCypherData: Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). - * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -866,15 +948,15 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t { return HAL_ERROR; } - + return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData); } - - + + /** * @brief Encrypt pPlainData in AES CBC encryption mode using DMA, - * the cypher data are available in pCypherData. + * the cypher data are available in pCypherData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer @@ -882,7 +964,7 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t * @param pCypherData: Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). - * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -899,13 +981,13 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t { return HAL_ERROR; } - + return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData); } /** * @brief Encrypt pPlainData in AES CTR encryption mode using DMA, - * the cypher data are available in pCypherData. + * the cypher data are available in pCypherData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer @@ -913,7 +995,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t * @param pCypherData: Pointer to the cyphertext buffer. * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). - * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -936,15 +1018,15 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Decrypt pCypherData in AES ECB decryption mode using DMA, - * the decyphered data are available in pPlainData. + * the decyphered data are available in pPlainData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pPlainData: Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). - * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). + * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -961,13 +1043,13 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t { return HAL_ERROR; } - + return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData); } /** * @brief Decrypt pCypherData in AES CBC decryption mode using DMA, - * the decyphered data are available in pPlainData. + * the decyphered data are available in pPlainData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer @@ -975,7 +1057,7 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t * @param pPlainData: Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). - * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -992,21 +1074,21 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t { return HAL_ERROR; } - + return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData); } /** * @brief Decrypt pCypherData in AES CTR decryption mode using DMA, - * the decyphered data are available in pPlainData. + * the decyphered data are available in pPlainData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pPlainData: Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). - * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). + * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -1022,8 +1104,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t if (HAL_CRYP_Init(hcryp) != HAL_OK) { return HAL_ERROR; - } - + } + return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData); } @@ -1032,13 +1114,13 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t * @} */ -/** @defgroup CRYP_Exported_Functions_Group3 Callback functions - * @brief Callback functions. +/** @defgroup CRYP_Exported_Functions_Group3 Callback functions + * @brief Callback functions. * -@verbatim +@verbatim ============================================================================== ##### Callback functions ##### - ============================================================================== + ============================================================================== [..] This section provides Interruption and DMA callback functions: (+) DMA Input data transfer complete (+) DMA Output data transfer complete @@ -1096,17 +1178,206 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) */ } +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User CRYP Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hcryp CRYP handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_CRYP_INPUTCPLT_CB_ID CRYP input DMA transfer completion Callback ID + * @arg @ref HAL_CRYP_OUTPUTCPLT_CB_ID CRYP output DMA transfer completion Callback ID + * @arg @ref HAL_CRYP_COMPCPLT_CB_ID CRYP computation completion Callback ID + * @arg @ref HAL_CRYP_ERROR_CB_ID CRYP error callback ID + * @arg @ref HAL_CRYP_MSPINIT_CB_ID CRYP MspDeInit callback ID + * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID CRYP MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hcryp); + + if(HAL_CRYP_STATE_READY == hcryp->State) + { + switch (CallbackID) + { + case HAL_CRYP_INPUTCPLT_CB_ID : + hcryp->InCpltCallback = pCallback; + break; + + case HAL_CRYP_OUTPUTCPLT_CB_ID : + hcryp->OutCpltCallback = pCallback; + break; + + case HAL_CRYP_COMPCPLT_CB_ID : + hcryp->CompCpltCallback = pCallback; + break; + + case HAL_CRYP_ERROR_CB_ID : + hcryp->ErrorCallback = pCallback; + break; + + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = pCallback; + break; + + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_CRYP_STATE_RESET == hcryp->State) + { + switch (CallbackID) + { + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = pCallback; + break; + + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hcryp); + return status; +} + +/** + * @brief Unregister a CRYP Callback + * CRYP Callback is redirected to the weak (surcharged) predefined callback + * @param hcryp CRYP handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_CRYP_INPUTCPLT_CB_ID CRYP input DMA transfer completion Callback ID + * @arg @ref HAL_CRYP_OUTPUTCPLT_CB_ID CRYP output DMA transfer completion Callback ID + * @arg @ref HAL_CRYP_COMPCPLT_CB_ID CRYP computation completion Callback ID + * @arg @ref HAL_CRYP_ERROR_CB_ID CRYP error callback ID + * @arg @ref HAL_CRYP_MSPINIT_CB_ID CRYP MspDeInit callback ID + * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID CRYP MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID) +{ +HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hcryp); + + if(HAL_CRYP_STATE_READY == hcryp->State) + { + switch (CallbackID) + { + case HAL_CRYP_INPUTCPLT_CB_ID : + hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak (surcharged) input DMA transfer completion callback */ + break; + + case HAL_CRYP_OUTPUTCPLT_CB_ID : + hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak (surcharged) output DMA transfer completion callback */ + break; + + case HAL_CRYP_COMPCPLT_CB_ID : + hcryp->CompCpltCallback = HAL_CRYPEx_ComputationCpltCallback; /* Legacy weak (surcharged) computation completion callback */ + break; + + case HAL_CRYP_ERROR_CB_ID : + hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak (surcharged) error callback */ + break; + + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak (surcharged) Msp DeInit */ + break; + + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; + + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_CRYP_STATE_RESET == hcryp->State) + { + switch (CallbackID) + { + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; + + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; + + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hcryp); + return status; +} +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + /** * @} */ -/** @defgroup CRYP_Exported_Functions_Group4 CRYP IRQ handler +/** @defgroup CRYP_Exported_Functions_Group4 CRYP IRQ handler * @brief AES IRQ handler. * -@verbatim +@verbatim ============================================================================== ##### AES IRQ handler management ##### - ============================================================================== + ============================================================================== [..] This section provides AES IRQ handler function. @endverbatim @@ -1136,39 +1407,43 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) hcryp->ErrorCode |= HAL_CRYP_READ_ERROR; hcryp->State = HAL_CRYP_STATE_ERROR; } - + /* If an error has been reported */ if (hcryp->State == HAL_CRYP_STATE_ERROR) - { + { /* Disable Error and Computation Complete Interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); /* Clear all Interrupt flags */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR|CRYP_CCF_CLEAR); - + /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - + __HAL_UNLOCK(hcryp); + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->ErrorCallback(hcryp); +#else HAL_CRYP_ErrorCallback(hcryp); - - return; +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + + return; } } - - /* Check if computation complete interrupt is enabled + + /* Check if computation complete interrupt is enabled and if the computation complete flag is raised */ if((__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET) && (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET)) - { + { #if defined(AES_CR_NPBLB) if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM)) -#else +#else if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)) -#endif +#endif { - /* To ensure proper suspension requests management, CCF flag - is reset in CRYP_AES_Auth_IT() according to the current + /* To ensure proper suspension requests management, CCF flag + is reset in CRYP_AES_Auth_IT() according to the current phase under handling */ CRYP_AES_Auth_IT(hcryp); } @@ -1185,13 +1460,13 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) * @} */ -/** @defgroup CRYP_Exported_Functions_Group5 Peripheral State functions - * @brief Peripheral State functions. +/** @defgroup CRYP_Exported_Functions_Group5 Peripheral State functions + * @brief Peripheral State functions. * -@verbatim +@verbatim ============================================================================== ##### Peripheral State functions ##### - ============================================================================== + ============================================================================== [..] This subsection permits to get in run-time the status of the peripheral. @@ -1215,7 +1490,7 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp) * @brief Return the CRYP peripheral error. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @note The returned error is a bit-map combination of possible errors + * @note The returned error is a bit-map combination of possible errors * @retval Error bit-map */ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp) @@ -1237,23 +1512,23 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp) /** - * @brief Write the Key in KeyRx registers. + * @brief Write the Key in KeyRx registers. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ static HAL_StatusTypeDef CRYP_SetKey(CRYP_HandleTypeDef *hcryp) -{ +{ uint32_t keyaddr = 0x0; - + if ((uint32_t)(hcryp->Init.pKey == NULL)) { return HAL_ERROR; } - - + + keyaddr = (uint32_t)(hcryp->Init.pKey); - + if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B) { hcryp->Instance->KEYR7 = __REV(*(uint32_t*)(keyaddr)); @@ -1263,22 +1538,22 @@ static HAL_StatusTypeDef CRYP_SetKey(CRYP_HandleTypeDef *hcryp) hcryp->Instance->KEYR5 = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; hcryp->Instance->KEYR4 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - } - + keyaddr+=4; + } + hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; - hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr)); - + hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr)); + return HAL_OK; } /** - * @brief Write the InitVector/InitCounter in IVRx registers. + * @brief Write the InitVector/InitCounter in IVRx registers. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None @@ -1286,13 +1561,13 @@ static HAL_StatusTypeDef CRYP_SetKey(CRYP_HandleTypeDef *hcryp) static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp) { uint32_t ivaddr = 0x0; - + #if !defined(AES_CR_NPBLB) if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) { hcryp->Instance->IVR3 = 0; hcryp->Instance->IVR2 = 0; - hcryp->Instance->IVR1 = 0; + hcryp->Instance->IVR1 = 0; hcryp->Instance->IVR0 = 0; } else @@ -1301,10 +1576,10 @@ static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp) if (hcryp->Init.pInitVect == NULL) { return HAL_ERROR; - } - + } + ivaddr = (uint32_t)(hcryp->Init.pInitVect); - + hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr)); ivaddr+=4; hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr)); @@ -1318,7 +1593,7 @@ static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp) -/** +/** * @brief Handle CRYP block input/output data handling under interruption. * @note The function is called under interruption only, once * interruptions have been enabled by HAL_CRYPEx_AES_IT(). @@ -1329,12 +1604,12 @@ static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp) static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) { uint32_t inputaddr = 0; - uint32_t outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; + uint32_t outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; if(hcryp->State == HAL_CRYP_STATE_BUSY) { if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION) - { + { /* Read the last available output block from the Data Output Register */ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; outputaddr+=4; @@ -1345,13 +1620,13 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; hcryp->pCrypOutBuffPtr += 16; hcryp->CrypOutCount -= 16; - + } else { /* Read the derived key from the Key registers */ if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B) - { + { *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR7); outputaddr+=4; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR6); @@ -1361,7 +1636,7 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR4); outputaddr+=4; } - + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR3); outputaddr+=4; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR2); @@ -1370,7 +1645,7 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) outputaddr+=4; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR0); } - + /* In case of ciphering or deciphering, check if all output text has been retrieved; In case of key derivation, stop right there */ if ((hcryp->CrypOutCount == 0) || (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)) @@ -1379,13 +1654,17 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + /* Call computation complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->CompCpltCallback(hcryp); +#else HAL_CRYPEx_ComputationCpltCallback(hcryp); - +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + return HAL_OK; } /* If suspension flag has been raised, suspend processing */ @@ -1393,26 +1672,26 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) { /* reset ModeSuspend */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; - + /* Disable Computation Complete Flag and Errors Interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_SUSPENDED; - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + return HAL_OK; } else /* Process the rest of input data */ { /* Get the Intput data address */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - + /* Increment/decrement instance pointer/counter */ hcryp->pCrypInBuffPtr += 16; hcryp->CrypInCount -= 16; - + /* Write the next input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; @@ -1421,16 +1700,16 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - - return HAL_OK; + + return HAL_OK; } } else { - return HAL_BUSY; + return HAL_BUSY; } } - + @@ -1447,8 +1726,8 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) /** * @} */ - -#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */ + +#endif /* AES */ #endif /* HAL_CRYP_MODULE_ENABLED */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp_ex.c index 8501e7cdeb..5fb87be580 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp_ex.c @@ -4,8 +4,8 @@ * @author MCD Application Team * @brief CRYPEx HAL module driver. * This file provides firmware functions to manage the extended - * functionalities of the Cryptography (CRYP) peripheral. - * + * functionalities of the Cryptography (CRYP) peripheral. + * ****************************************************************************** * @attention * @@ -33,15 +33,15 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" #ifdef HAL_CRYP_MODULE_ENABLED -#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(AES) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -100,13 +100,13 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_ */ -/** @defgroup CRYPEx_Exported_Functions_Group1 Extended callback function - * @brief Extended callback functions. +/** @defgroup CRYPEx_Exported_Functions_Group1 Extended callback function + * @brief Extended callback functions. * -@verbatim +@verbatim =============================================================================== ##### Extended callback functions ##### - =============================================================================== + =============================================================================== [..] This section provides callback function: (+) Computation completed. @@ -128,20 +128,20 @@ __weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp) /* NOTE : This function should not be modified; when the callback is needed, the HAL_CRYPEx_ComputationCpltCallback can be implemented in the user file - */ + */ } /** * @} */ -/** @defgroup CRYPEx_Exported_Functions_Group2 AES extended processing functions - * @brief Extended processing functions. +/** @defgroup CRYPEx_Exported_Functions_Group2 AES extended processing functions + * @brief Extended processing functions. * -@verbatim +@verbatim ============================================================================== ##### AES extended processing functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: (+) Encrypt plaintext or decrypt cipher text using AES algorithm in different chaining modes. Functions are generic (handles ECB, CBC and CTR and all modes) and are only differentiated @@ -149,14 +149,14 @@ __weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp) (++) Polling mode (++) Interrupt mode (++) DMA mode - (+) Generate and authentication tag in addition to encrypt/decrypt a plain/cipher text using AES + (+) Generate and authentication tag in addition to encrypt/decrypt a plain/cipher text using AES algorithm in different chaining modes. - Functions are generic (handles GCM, GMAC, CMAC and CCM when applicable) and process only one phase - so that steps can be skipped if so required. Functions are only differentiated based on the processing type. + Functions are generic (handles GCM, GMAC, CMAC and CCM when applicable) and process only one phase + so that steps can be skipped if so required. Functions are only differentiated based on the processing type. Three processing types are available: (++) Polling mode (++) Interrupt mode - (++) DMA mode + (++) DMA mode @endverbatim * @{ @@ -164,19 +164,19 @@ __weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp) /** * @brief Carry out in polling mode the ciphering or deciphering operation according to - * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and + * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and * chaining modes ECB, CBC and CTR are managed by this function in polling mode. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption * or key derivation+decryption. - * Parameter is meaningless in case of key derivation. + * Parameter is meaningless in case of key derivation. * @param Size: Length of the input data buffer in bytes, must be a multiple of 16. - * Parameter is meaningless in case of key derivation. - * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of + * Parameter is meaningless in case of key derivation. + * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of * decryption/key derivation+decryption, or pointer to the derivative keys in - * case of key derivation only. - * @param Timeout: Specify Timeout value + * case of key derivation only. + * @param Timeout: Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout) @@ -187,7 +187,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, /* Check parameters setting */ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) { - if (pOutputData == NULL) + if (pOutputData == NULL) { return HAL_ERROR; } @@ -199,13 +199,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, return HAL_ERROR; } } - + /* Process Locked */ __HAL_LOCK(hcryp); - + /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; - + /* Call CRYP_ReadKey() API if the operating mode is set to key derivation, CRYP_ProcessData() otherwise */ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) @@ -213,7 +213,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, if(CRYP_ReadKey(hcryp, pOutputData, Timeout) != HAL_OK) { return HAL_TIMEOUT; - } + } } else { @@ -222,17 +222,17 @@ HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, return HAL_TIMEOUT; } } - + /* If the state has not been set to SUSPENDED, set it to READY, otherwise keep it as it is */ if (hcryp->State != HAL_CRYP_STATE_SUSPENDED) { hcryp->State = HAL_CRYP_STATE_READY; } - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + return HAL_OK; } else @@ -245,30 +245,30 @@ HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, /** * @brief Carry out in interrupt mode the ciphering or deciphering operation according to - * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and + * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and * chaining modes ECB, CBC and CTR are managed by this function in interrupt mode. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption * or key derivation+decryption. - * Parameter is meaningless in case of key derivation. + * Parameter is meaningless in case of key derivation. * @param Size: Length of the input data buffer in bytes, must be a multiple of 16. - * Parameter is meaningless in case of key derivation. - * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of - * decryption/key derivation+decryption, or pointer to the derivative keys in - * case of key derivation only. + * Parameter is meaningless in case of key derivation. + * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of + * decryption/key derivation+decryption, or pointer to the derivative keys in + * case of key derivation only. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData) { uint32_t inputaddr = 0; - + if(hcryp->State == HAL_CRYP_STATE_READY) { /* Check parameters setting */ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) { - if (pOutputData == NULL) + if (pOutputData == NULL) { return HAL_ERROR; } @@ -282,7 +282,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputD } /* Process Locked */ __HAL_LOCK(hcryp); - + /* If operating mode is not limited to key derivation only, get the buffers addresses and sizes */ if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION) @@ -299,24 +299,24 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputD (will point at derivated key) */ hcryp->pCrypOutBuffPtr = pOutputData; } - + /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + /* Enable Computation Complete Flag and Error Interrupts */ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); - - - /* If operating mode is key derivation only, the input data have + + + /* If operating mode is key derivation only, the input data have already been entered during the initialization process. For - the other operating modes, they are fed to the CRYP hardware + the other operating modes, they are fed to the CRYP hardware block at this point. */ if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION) { - /* Initiate the processing under interrupt in entering + /* Initiate the processing under interrupt in entering the first input data */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; /* Increment/decrement instance pointer/counter */ @@ -331,18 +331,18 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputD inputaddr+=4; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); } - + /* Return function status */ return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } - - - + + + /** @@ -351,30 +351,30 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputD * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption - * or key derivation+decryption. + * or key derivation+decryption. * @param Size: Length of the input data buffer in bytes, must be a multiple of 16. - * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of + * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of * decryption/key derivation+decryption. - * @note Chaining modes ECB, CBC and CTR are managed by this function in DMA mode. - * @note Supported operating modes are encryption, decryption and key derivation with decryption. - * @note No DMA channel is provided for key derivation only and therefore, access to AES_KEYRx - * registers must be done by software. - * @note This API is not applicable to key derivation only; for such a mode, access to AES_KEYRx + * @note Chaining modes ECB, CBC and CTR are managed by this function in DMA mode. + * @note Supported operating modes are encryption, decryption and key derivation with decryption. + * @note No DMA channel is provided for key derivation only and therefore, access to AES_KEYRx + * registers must be done by software. + * @note This API is not applicable to key derivation only; for such a mode, access to AES_KEYRx * registers must be done by software thru HAL_CRYPEx_AES() or HAL_CRYPEx_AES_IT() APIs. - * @note pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * @note pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData) { uint32_t inputaddr = 0; uint32_t outputaddr = 0; - + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Check parameters setting */ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) { - /* no DMA channel is provided for key derivation operating mode, + /* no DMA channel is provided for key derivation operating mode, access to AES_KEYRx registers must be done by software */ return HAL_ERROR; } @@ -385,64 +385,64 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInput return HAL_ERROR; } } - - + + /* Process Locked */ __HAL_LOCK(hcryp); - + inputaddr = (uint32_t)pInputData; outputaddr = (uint32_t)pOutputData; - + /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set the input and output addresses and start DMA transfer */ + + /* Set the input and output addresses and start DMA transfer */ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + /* Return function status */ return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } - + /** - * @brief Carry out in polling mode the authentication tag generation as well as the ciphering or deciphering - * operation according to hcryp->Init structure fields. + * @brief Carry out in polling mode the authentication tag generation as well as the ciphering or deciphering + * operation according to hcryp->Init structure fields. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: - * - pointer to payload data in GCM or CCM payload phase, + * @param pInputData: + * - pointer to payload data in GCM or CCM payload phase, * - pointer to B0 block in CMAC header phase, - * - pointer to C block in CMAC final phase. - * - Parameter is meaningless in case of GCM/GMAC/CCM init, header and final phases. - * @param Size: + * - pointer to C block in CMAC final phase. + * - Parameter is meaningless in case of GCM/GMAC/CCM init, header and final phases. + * @param Size: * - length of the input payload data buffer in bytes in GCM or CCM payload phase, * - length of B0 block (in bytes) in CMAC header phase, * - length of C block (in bytes) in CMAC final phase. - * - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases. - * - Parameter is meaningless in case of CCM final phase. - * - Parameter is message length in bytes in case of GCM final phase. - * - Parameter must be set to zero in case of GMAC final phase. - * @param pOutputData: - * - pointer to plain or cipher text in GCM/CCM payload phase, + * - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases. + * - Parameter is meaningless in case of CCM final phase. + * - Parameter is message length in bytes in case of GCM final phase. + * - Parameter must be set to zero in case of GMAC final phase. + * @param pOutputData: + * - pointer to plain or cipher text in GCM/CCM payload phase, * - pointer to authentication tag in GCM/GMAC/CCM/CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases. - * - Parameter is meaningless in case of CMAC header phase. - * @param Timeout: Specify Timeout value + * - Parameter is meaningless in case of CMAC header phase. + * @param Timeout: Specify Timeout value * @note Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC, CMAC and CCM when the latter is applicable. - * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes - * can be skipped by the user if so required. + * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes + * can be skipped by the user if so required. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout) @@ -451,12 +451,12 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput uint32_t inputaddr = 0; uint32_t outputaddr = 0; uint32_t tagaddr = 0; - uint64_t headerlength = 0; + uint64_t headerlength = 0; uint64_t inputlength = 0; - uint64_t payloadlength = 0; + uint64_t payloadlength = 0; uint32_t difflength = 0; - uint32_t addhoc_process = 0; - + uint32_t addhoc_process = 0; + if (hcryp->State == HAL_CRYP_STATE_READY) { /* input/output parameters check */ @@ -469,9 +469,9 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput } #if defined(AES_CR_NPBLB) if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM) -#else +#else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) -#endif +#endif { /* In case of CMAC or CCM (when applicable) header phase resumption, we can have pInputData = NULL and Size = 0 */ if (((pInputData != NULL) && (Size == 0)) || ((pInputData == NULL) && (Size != 0))) @@ -481,7 +481,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput } } else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) - { + { if (((pInputData == NULL) && (Size != 0)) || \ ((pInputData != NULL) && (Size == 0)) || \ ((pInputData != NULL) && (Size != 0) && (pOutputData == NULL))) @@ -495,37 +495,37 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput { return HAL_ERROR; } -#if !defined(AES_CR_NPBLB) +#if !defined(AES_CR_NPBLB) if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL)) { return HAL_ERROR; } -#endif +#endif } - - + + /* Process Locked */ __HAL_LOCK(hcryp); - + /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; - + /*==============================================*/ /* GCM/GMAC (or CCM when applicable) init phase */ /*==============================================*/ - /* In case of init phase, the input data (Key and Initialization Vector) have + /* In case of init phase, the input data (Key and Initialization Vector) have already been entered during the initialization process. Therefore, the API just waits for the CCF flag to be set. */ if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE) { /* just wait for hash computation */ - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } - + /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); /* Mark that the initialization phase is over */ @@ -535,30 +535,30 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput /* GCM/GMAC or (CCM / CMAC when applicable) header phase */ /*=======================================================*/ else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) - { -#if !defined(AES_CR_NPBLB) + { +#if !defined(AES_CR_NPBLB) /* Set header phase; for GCM or GMAC, set data-byte at this point */ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) { MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_HEADER_PHASE|hcryp->Init.DataType); } else -#endif +#endif { MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_HEADER_PHASE); } - + /* Enable the Peripheral */ __HAL_CRYP_ENABLE(hcryp); - -#if !defined(AES_CR_NPBLB) + +#if !defined(AES_CR_NPBLB) /* in case of CMAC, enter B0 block in header phase, before the header itself. */ /* If Size = 0 (possible case of resumption after CMAC header phase suspension), skip these steps and go directly to header buffer feeding to the HW */ if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (Size != 0)) { - inputaddr = (uint32_t)pInputData; - + inputaddr = (uint32_t)pInputData; + for( ; (index < Size); index += 16) { /* Write the Input block in the Data Input register */ @@ -570,19 +570,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput inputaddr+=4; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + + if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); /* If the suspension flag has been raised and if the processing is not about - to end, suspend processing */ - if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < Size)) + to end, suspend processing */ + if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < Size)) { /* reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; @@ -590,30 +590,30 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput hcryp->State = HAL_CRYP_STATE_SUSPENDED; /* Mark that the header phase is over */ hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED; - + /* Save current reading and writing locations of Input and Output buffers */ hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; - /* Save the total number of bytes (B blocks + header) that remain to be + /* Save the total number of bytes (B blocks + header) that remain to be processed at this point */ hcryp->CrypInCount = hcryp->Init.HeaderSize + Size - (index+16); - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + return HAL_OK; - } - } /* for(index=0; (index < Size); index += 16) */ + } + } /* for(index=0; (index < Size); index += 16) */ } -#endif /* !defined(AES_CR_NPBLB) */ - - /* Enter header */ - inputaddr = (uint32_t)hcryp->Init.Header; +#endif /* !defined(AES_CR_NPBLB) */ + + /* Enter header */ + inputaddr = (uint32_t)hcryp->Init.Header; /* Local variable headerlength is a number of bytes multiple of 128 bits, remaining header data (if any) are handled after this loop */ - headerlength = (((hcryp->Init.HeaderSize)/16)*16) ; + headerlength = (((hcryp->Init.HeaderSize)/16)*16) ; if ((hcryp->Init.HeaderSize % 16) != 0) { - difflength = (uint32_t) (hcryp->Init.HeaderSize - headerlength); + difflength = (uint32_t) (hcryp->Init.HeaderSize - headerlength); } for(index=0; index < headerlength; index += 16) { @@ -626,19 +626,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput inputaddr+=4; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + + if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* If the suspension flag has been raised and if the processing is not about - to end, suspend processing */ - if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < headerlength)) + to end, suspend processing */ + if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < headerlength)) { /* reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; @@ -646,26 +646,26 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput hcryp->State = HAL_CRYP_STATE_SUSPENDED; /* Mark that the header phase is over */ hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED; - + /* Save current reading and writing locations of Input and Output buffers */ hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; /* Save the total number of bytes that remain to be processed at this point */ hcryp->CrypInCount = hcryp->Init.HeaderSize - (index+16); - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + return HAL_OK; - } + } } - + /* Case header length is not a multiple of 16 bytes */ if (difflength != 0) { hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; - CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON); - } - + CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON); + } + /* Mark that the header phase is over */ hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; } @@ -674,18 +674,18 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput /*============================================*/ else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) { - + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PAYLOAD_PHASE); - + /* if the header phase has been bypassed, AES must be enabled again */ if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER) { - __HAL_CRYP_ENABLE(hcryp); + __HAL_CRYP_ENABLE(hcryp); } - + inputaddr = (uint32_t)pInputData; outputaddr = (uint32_t)pOutputData; - + /* Enter payload */ /* Specific handling to manage payload last block size less than 128 bits */ if ((Size % 16) != 0) @@ -696,10 +696,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput } else { - payloadlength = Size; + payloadlength = Size; } - - /* Feed payload */ + + /* Feed payload */ for( ; index < payloadlength; index += 16) { /* Write the Input block in the Data Input register */ @@ -711,18 +711,18 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput inputaddr+=4; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + + if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } - + /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - /* Retrieve output data: read the output block + + /* Retrieve output data: read the output block from the Data Output Register */ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; outputaddr+=4; @@ -732,83 +732,83 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput outputaddr+=4; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; outputaddr+=4; - + /* If the suspension flag has been raised and if the processing is not about - to end, suspend processing */ + to end, suspend processing */ if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < payloadlength)) { /* no flag waiting under IRQ handling */ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) { /* Ensure that Busy flag is reset */ - if(CRYP_WaitOnBusyFlagReset(hcryp, CRYP_BUSY_TIMEOUTVALUE) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + if(CRYP_WaitOnBusyFlagReset(hcryp, CRYP_BUSY_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } - } + } /* reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_SUSPENDED; /* Mark that the header phase is over */ hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED; - + /* Save current reading and writing locations of Input and Output buffers */ hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr; hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; /* Save the number of bytes that remain to be processed at this point */ - hcryp->CrypInCount = Size - (index+16); - + hcryp->CrypInCount = Size - (index+16); + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + return HAL_OK; - } - + } + } - - /* Additional processing to manage GCM(/CCM) encryption and decryption cases when + + /* Additional processing to manage GCM(/CCM) encryption and decryption cases when payload last block size less than 128 bits */ if (addhoc_process == 1) { - + hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; - hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr; - CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON); - + hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr; + CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON); + } /* (addhoc_process == 1) */ - + /* Mark that the payload phase is over */ - hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; + hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; } /*==================================*/ /* GCM/GMAC/CCM or CMAC final phase */ /*==================================*/ else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE) - { + { tagaddr = (uint32_t)pOutputData; - -#if defined(AES_CR_NPBLB) + +#if defined(AES_CR_NPBLB) /* By default, clear NPBLB field */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB); -#endif - +#endif + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE); - + /* if the header and payload phases have been bypassed, AES must be enabled again */ if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER) { - __HAL_CRYP_ENABLE(hcryp); + __HAL_CRYP_ENABLE(hcryp); } - + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) { headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */ - inputlength = Size * 8; /* input length in bits */ - -#if !defined(AES_CR_NPBLB) + inputlength = Size * 8; /* input length in bits */ + +#if !defined(AES_CR_NPBLB) if(hcryp->Init.DataType == CRYP_DATATYPE_1B) { hcryp->Instance->DINR = __RBIT((headerlength)>>32); @@ -822,13 +822,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput hcryp->Instance->DINR = __REV(headerlength); hcryp->Instance->DINR = __REV((inputlength)>>32); hcryp->Instance->DINR = __REV(inputlength); - } + } else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) { hcryp->Instance->DINR = __ROR((headerlength)>>32, 16); hcryp->Instance->DINR = __ROR(headerlength, 16); hcryp->Instance->DINR = __ROR((inputlength)>>32, 16); - hcryp->Instance->DINR = __ROR(inputlength, 16); + hcryp->Instance->DINR = __ROR(inputlength, 16); } else if(hcryp->Init.DataType == CRYP_DATATYPE_32B) { @@ -837,15 +837,15 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput hcryp->Instance->DINR = (uint32_t)(inputlength>>32); hcryp->Instance->DINR = (uint32_t)(inputlength); } -#else +#else hcryp->Instance->DINR = (uint32_t)(headerlength>>32); hcryp->Instance->DINR = (uint32_t)(headerlength); hcryp->Instance->DINR = (uint32_t)(inputlength>>32); hcryp->Instance->DINR = (uint32_t)(inputlength); -#endif +#endif } -#if !defined(AES_CR_NPBLB) - else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) +#if !defined(AES_CR_NPBLB) + else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) { inputaddr = (uint32_t)pInputData; /* Enter the last block made of a 128-bit value formatted @@ -858,12 +858,12 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput inputaddr+=4; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); } -#endif - - - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; +#endif + + + if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } @@ -875,8 +875,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput tagaddr+=4; *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; tagaddr+=4; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - + *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; + /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -890,17 +890,17 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput /*=================================================*/ else { - hcryp->State = HAL_CRYP_STATE_ERROR; - __HAL_UNLOCK(hcryp); + hcryp->State = HAL_CRYP_STATE_ERROR; + __HAL_UNLOCK(hcryp); return HAL_ERROR; } - + /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + return HAL_OK; } else @@ -913,31 +913,31 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput /** - * @brief Carry out in interrupt mode the authentication tag generation as well as the ciphering or deciphering - * operation according to hcryp->Init structure fields. + * @brief Carry out in interrupt mode the authentication tag generation as well as the ciphering or deciphering + * operation according to hcryp->Init structure fields. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: - * - pointer to payload data in GCM or CCM payload phase, + * @param pInputData: + * - pointer to payload data in GCM or CCM payload phase, * - pointer to B0 block in CMAC header phase, - * - pointer to C block in CMAC final phase. - * - Parameter is meaningless in case of GCM/GMAC/CCM init, header and final phases. - * @param Size: + * - pointer to C block in CMAC final phase. + * - Parameter is meaningless in case of GCM/GMAC/CCM init, header and final phases. + * @param Size: * - length of the input payload data buffer in bytes in GCM or CCM payload phase, * - length of B0 block (in bytes) in CMAC header phase, * - length of C block (in bytes) in CMAC final phase. - * - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases. - * - Parameter is meaningless in case of CCM final phase. - * - Parameter is message length in bytes in case of GCM final phase. - * - Parameter must be set to zero in case of GMAC final phase. - * @param pOutputData: - * - pointer to plain or cipher text in GCM/CCM payload phase, + * - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases. + * - Parameter is meaningless in case of CCM final phase. + * - Parameter is message length in bytes in case of GCM final phase. + * - Parameter must be set to zero in case of GMAC final phase. + * @param pOutputData: + * - pointer to plain or cipher text in GCM/CCM payload phase, * - pointer to authentication tag in GCM/GMAC/CCM/CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases. - * - Parameter is meaningless in case of CMAC header phase. + * - Parameter is meaningless in case of CMAC header phase. * @note Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC and CMAC. - * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes - * can be skipped by the user if so required. + * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes + * can be skipped by the user if so required. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData) @@ -947,15 +947,15 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn uint64_t headerlength = 0; uint64_t inputlength = 0; uint32_t index = 0; - uint32_t addhoc_process = 0; + uint32_t addhoc_process = 0; uint32_t difflength = 0; uint32_t difflengthmod4 = 0; uint32_t mask[4][3] = { {0xFF000000, 0xFFFF0000, 0xFFFFFF00}, /* 32-bit data */ {0x0000FF00, 0x0000FFFF, 0xFF00FFFF}, /* 16-bit data */ {0x000000FF, 0x0000FFFF, 0x00FFFFFF}, /* 8-bit data */ {0x000000FF, 0x0000FFFF, 0x00FFFFFF}}; /* Bit data */ - uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos; - + uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos; + if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -967,21 +967,21 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn { return HAL_ERROR; } -#if defined(AES_CR_NPBLB) +#if defined(AES_CR_NPBLB) if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM) -#else +#else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) -#endif +#endif { /* In case of CMAC or CCM header phase resumption, we can have pInputData = NULL and Size = 0 */ if (((pInputData != NULL) && (Size == 0)) || ((pInputData == NULL) && (Size != 0))) { return HAL_ERROR; } - } + } } else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) - { + { if ((pInputData != NULL) && (Size != 0) && (pOutputData == NULL)) { return HAL_ERROR; @@ -993,24 +993,24 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn { return HAL_ERROR; } -#if !defined(AES_CR_NPBLB) - if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL)) +#if !defined(AES_CR_NPBLB) + if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL)) { return HAL_ERROR; } #endif } - - + + /* Process Locked */ __HAL_LOCK(hcryp); - + /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + /* Enable Computation Complete Flag and Error Interrupts */ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); @@ -1020,27 +1020,27 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn /* GCM/GMAC (or CCM when applicable) init phase */ /*==============================================*/ if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE) - { - /* In case of init phase, the input data (Key and Initialization Vector) have + { + /* In case of init phase, the input data (Key and Initialization Vector) have already been entered during the initialization process. Therefore, the software just waits for the CCF interrupt to be raised and which will be handled by CRYP_AES_Auth_IT() API. */ } /*===================================*/ /* GCM/GMAC/CCM or CMAC header phase */ - /*===================================*/ + /*===================================*/ else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) { - -#if defined(AES_CR_NPBLB) + +#if defined(AES_CR_NPBLB) if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM) -#else +#else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) -#endif +#endif { /* In case of CMAC, B blocks are first entered, before the header. Therefore, B blocks and the header are entered back-to-back - as if it was only one single block. + as if it was only one single block. However, in case of resumption after suspension, if all the B blocks have been entered (in that case, Size = 0), only the remainder of the non-processed header bytes are entered. */ @@ -1060,55 +1060,55 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn /* Get the header addresses and sizes */ hcryp->CrypInCount = hcryp->Init.HeaderSize; hcryp->pCrypInBuffPtr = hcryp->Init.Header; - } - + } + inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; -#if !defined(AES_CR_NPBLB) +#if !defined(AES_CR_NPBLB) /* Set header phase; for GCM or GMAC, set data-byte at this point */ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) { MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_HEADER_PHASE|hcryp->Init.DataType); } else -#endif +#endif { MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_HEADER_PHASE); } - + /* Enable the Peripheral */ __HAL_CRYP_ENABLE(hcryp); - + /* Increment/decrement instance pointer/counter */ if (hcryp->CrypInCount == 0) { /* Case of no header */ - hcryp->State = HAL_CRYP_STATE_READY; + hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the header phase is over */ - hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; - return HAL_OK; + hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; + return HAL_OK; } else if (hcryp->CrypInCount < 16) { hcryp->CrypInCount = 0; - addhoc_process = 1; + addhoc_process = 1; difflength = (uint32_t) (hcryp->Init.HeaderSize); - difflengthmod4 = difflength%4; + difflengthmod4 = difflength%4; } else { hcryp->pCrypInBuffPtr += 16; hcryp->CrypInCount -= 16; } - - -#if defined(AES_CR_NPBLB) + + +#if defined(AES_CR_NPBLB) if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM) -#else +#else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) -#endif - { +#endif + { if (hcryp->CrypInCount == hcryp->Init.HeaderSize) { /* All B blocks will have been entered after the next @@ -1116,13 +1116,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn the next iteration */ hcryp->pCrypInBuffPtr = hcryp->Init.Header; } - } - + } + /* Enter header first block to initiate the process in the Data Input register */ if (addhoc_process == 0) - { - /* Header has size equal or larger than 128 bits */ + { + /* Header has size equal or larger than 128 bits */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); @@ -1133,7 +1133,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn } else { - /* Header has size less than 128 bits */ + /* Header has size less than 128 bits */ /* Enter complete words when possible */ for( ; index < (difflength/4); index ++) { @@ -1141,18 +1141,18 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; } - /* Enter incomplete word padded with zeroes if applicable + /* Enter incomplete word padded with zeroes if applicable (case of header length not a multiple of 32-bits) */ if (difflengthmod4 != 0) - { + { hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); - } + } /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */ - for(index=0; index < (4 - ((difflength+3)/4)); index ++) + for(index=0; index < (4 - ((difflength+3)/4)); index ++) { hcryp->Instance->DINR = 0; - } - + } + } } /*============================================*/ @@ -1164,66 +1164,66 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn hcryp->CrypInCount = Size; hcryp->pCrypInBuffPtr = pInputData; hcryp->pCrypOutBuffPtr = pOutputData; - hcryp->CrypOutCount = Size; - + hcryp->CrypOutCount = Size; + inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PAYLOAD_PHASE); - + /* if the header phase has been bypassed, AES must be enabled again */ if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER) { - __HAL_CRYP_ENABLE(hcryp); + __HAL_CRYP_ENABLE(hcryp); } - + /* No payload case */ if (pInputData == NULL) { - hcryp->State = HAL_CRYP_STATE_READY; + hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the header phase is over */ - hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; + hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; /* Process Unlocked */ __HAL_UNLOCK(hcryp); - - return HAL_OK; - } - + + return HAL_OK; + } + /* Specific handling to manage payload size less than 128 bits */ if (Size < 16) { difflength = (uint32_t) (Size); -#if defined(AES_CR_NPBLB) +#if defined(AES_CR_NPBLB) /* In case of GCM encryption or CCM decryption, specify the number of padding bytes in last block of payload */ if (READ_BIT(hcryp->Instance->CR, AES_CR_GCMPH) == CRYP_PAYLOAD_PHASE) { if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC) - && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT)) + && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT)) || ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM) && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT))) { - /* Set NPBLB field in writing the number of padding bytes + /* Set NPBLB field in writing the number of padding bytes for the last block of payload */ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, (16 - difflength) << AES_POSITION_CR_NPBLB); } } #else - /* Software workaround applied to GCM encryption only */ + /* Software workaround applied to GCM encryption only */ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) { - /* Change the mode configured in CHMOD bits of CR register to select CTR mode */ + /* Change the mode configured in CHMOD bits of CR register to select CTR mode */ __HAL_CRYP_SET_CHAININGMODE(hcryp, CRYP_CHAINMODE_AES_CTR); - } -#endif + } +#endif - /* Set hcryp->CrypInCount to 0 (no more data to enter) */ - hcryp->CrypInCount = 0; + /* Set hcryp->CrypInCount to 0 (no more data to enter) */ + hcryp->CrypInCount = 0; - /* Insert the last block (which size is inferior to 128 bits) padded with zeroes, - to have a complete block of 128 bits */ - difflengthmod4 = difflength%4; - /* Insert the last block (which size is inferior to 128 bits) padded with zeroes + /* Insert the last block (which size is inferior to 128 bits) padded with zeroes, + to have a complete block of 128 bits */ + difflengthmod4 = difflength%4; + /* Insert the last block (which size is inferior to 128 bits) padded with zeroes to have a complete block of 128 bits */ for(index=0; index < (difflength/4); index ++) { @@ -1233,21 +1233,21 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn } /* If required, manage input data size not multiple of 32 bits */ if (difflengthmod4 != 0) - { + { hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); - } + } /* Wrap-up in padding with zero-words if applicable */ - for(index=0; index < (4 - ((difflength+3)/4)); index ++) + for(index=0; index < (4 - ((difflength+3)/4)); index ++) { hcryp->Instance->DINR = 0; - } + } } else - { + { /* Increment/decrement instance pointer/counter */ hcryp->pCrypInBuffPtr += 16; hcryp->CrypInCount -= 16; - + /* Enter payload first block to initiate the process in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); @@ -1265,28 +1265,28 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE) { hcryp->pCrypOutBuffPtr = pOutputData; - -#if defined(AES_CR_NPBLB) + +#if defined(AES_CR_NPBLB) /* By default, clear NPBLB field */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB); -#endif - +#endif + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE); - + /* if the header and payload phases have been bypassed, AES must be enabled again */ if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER) { - __HAL_CRYP_ENABLE(hcryp); + __HAL_CRYP_ENABLE(hcryp); } - + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) - { + { headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */ - inputlength = Size * 8; /* Input length in bits */ + inputlength = Size * 8; /* Input length in bits */ /* Write the number of bits in the header on 64 bits followed by the number of bits in the payload on 64 bits as well */ - -#if !defined(AES_CR_NPBLB) + +#if !defined(AES_CR_NPBLB) if(hcryp->Init.DataType == CRYP_DATATYPE_1B) { hcryp->Instance->DINR = __RBIT((headerlength)>>32); @@ -1306,7 +1306,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn hcryp->Instance->DINR = __ROR((headerlength)>>32, 16); hcryp->Instance->DINR = __ROR(headerlength, 16); hcryp->Instance->DINR = __ROR((inputlength)>>32, 16); - hcryp->Instance->DINR = __ROR(inputlength, 16); + hcryp->Instance->DINR = __ROR(inputlength, 16); } else if(hcryp->Init.DataType == CRYP_DATATYPE_32B) { @@ -1320,9 +1320,9 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn hcryp->Instance->DINR = (uint32_t)(headerlength); hcryp->Instance->DINR = (uint32_t)(inputlength>>32); hcryp->Instance->DINR = (uint32_t)(inputlength); -#endif +#endif } -#if !defined(AES_CR_NPBLB) +#if !defined(AES_CR_NPBLB) else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) { inputaddr = (uint32_t)pInputData; @@ -1336,17 +1336,17 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn inputaddr+=4; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); } -#endif +#endif } /*=================================================*/ /* case incorrect hcryp->Init.GCMCMACPhase setting */ /*=================================================*/ else { - hcryp->State = HAL_CRYP_STATE_ERROR; + hcryp->State = HAL_CRYP_STATE_ERROR; return HAL_ERROR; } - + return HAL_OK; } else @@ -1359,32 +1359,32 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn /** - * @brief Carry out in DMA mode the authentication tag generation as well as the ciphering or deciphering - * operation according to hcryp->Init structure fields. + * @brief Carry out in DMA mode the authentication tag generation as well as the ciphering or deciphering + * operation according to hcryp->Init structure fields. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: - * - pointer to payload data in GCM or CCM payload phase, + * @param pInputData: + * - pointer to payload data in GCM or CCM payload phase, * - pointer to B0 block in CMAC header phase, - * - pointer to C block in CMAC final phase. - * - Parameter is meaningless in case of GCM/GMAC/CCM init, header and final phases. - * @param Size: + * - pointer to C block in CMAC final phase. + * - Parameter is meaningless in case of GCM/GMAC/CCM init, header and final phases. + * @param Size: * - length of the input payload data buffer in bytes in GCM or CCM payload phase, * - length of B0 block (in bytes) in CMAC header phase, * - length of C block (in bytes) in CMAC final phase. - * - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases. - * - Parameter is meaningless in case of CCM final phase. - * - Parameter is message length in bytes in case of GCM final phase. - * - Parameter must be set to zero in case of GMAC final phase. - * @param pOutputData: - * - pointer to plain or cipher text in GCM/CCM payload phase, + * - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases. + * - Parameter is meaningless in case of CCM final phase. + * - Parameter is message length in bytes in case of GCM final phase. + * - Parameter must be set to zero in case of GMAC final phase. + * @param pOutputData: + * - pointer to plain or cipher text in GCM/CCM payload phase, * - pointer to authentication tag in GCM/GMAC/CCM/CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases. - * - Parameter is meaningless in case of CMAC header phase. + * - Parameter is meaningless in case of CMAC header phase. * @note Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC and CMAC. - * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes + * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes * can be skipped by the user if so required. - * @note pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * @note pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData) @@ -1395,8 +1395,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI uint64_t headerlength = 0; uint64_t inputlength = 0; uint64_t payloadlength = 0; - - + + if (hcryp->State == HAL_CRYP_STATE_READY) { /* input/output parameters check */ @@ -1406,7 +1406,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI { return HAL_ERROR; } -#if defined(AES_CR_NPBLB) +#if defined(AES_CR_NPBLB) if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM) { /* In case of CMAC or CCM header phase resumption, we can have pInputData = NULL and Size = 0 */ @@ -1414,19 +1414,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI { return HAL_ERROR; } - } -#else - if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) + } +#else + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) { if ((pInputData == NULL) || (Size == 0)) { return HAL_ERROR; } } -#endif +#endif } else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) - { + { if ((pInputData != NULL) && (Size != 0) && (pOutputData == NULL)) { return HAL_ERROR; @@ -1438,38 +1438,38 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI { return HAL_ERROR; } -#if !defined(AES_CR_NPBLB) +#if !defined(AES_CR_NPBLB) if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL)) { return HAL_ERROR; } #endif } - - + + /* Process Locked */ __HAL_LOCK(hcryp); - + /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; - + /*==============================================*/ /* GCM/GMAC (or CCM when applicable) init phase */ /*==============================================*/ - /* In case of init phase, the input data (Key and Initialization Vector) have + /* In case of init phase, the input data (Key and Initialization Vector) have already been entered during the initialization process. No DMA transfer is - required at that point therefore, the software just waits for the CCF flag + required at that point therefore, the software just waits for the CCF flag to be raised. */ if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE) { /* just wait for hash computation */ - if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } - + /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); /* Mark that the initialization phase is over */ @@ -1478,25 +1478,25 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI } /*====================================*/ /* GCM/GMAC/ CCM or CMAC header phase */ - /*====================================*/ + /*====================================*/ else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) - { -#if !defined(AES_CR_NPBLB) + { +#if !defined(AES_CR_NPBLB) /* Set header phase; for GCM or GMAC, set data-byte at this point */ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) { MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_HEADER_PHASE|hcryp->Init.DataType); } else -#endif +#endif { MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_HEADER_PHASE); } - + /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); - -#if !defined(AES_CR_NPBLB) + +#if !defined(AES_CR_NPBLB) /* enter first B0 block in polling mode (no DMA transfer for B0) */ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) { @@ -1508,68 +1508,68 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - - if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + + if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } -#endif - +#endif + /* No header case */ if (hcryp->Init.Header == NULL) { - hcryp->State = HAL_CRYP_STATE_READY; + hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the header phase is over */ - hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; + hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; /* Process Unlocked */ __HAL_UNLOCK(hcryp); - - return HAL_OK; + + return HAL_OK; } - + inputaddr = (uint32_t)hcryp->Init.Header; if ((hcryp->Init.HeaderSize % 16) != 0) { - if (hcryp->Init.HeaderSize < 16) - { - hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; - CRYP_Padding(hcryp, (uint32_t) (hcryp->Init.HeaderSize), CRYP_POLLING_OFF); - - hcryp->State = HAL_CRYP_STATE_READY; + if (hcryp->Init.HeaderSize < 16) + { + hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; + CRYP_Padding(hcryp, (uint32_t) (hcryp->Init.HeaderSize), CRYP_POLLING_OFF); + + hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the header phase is over */ - hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; - - /* CCF flag indicating header phase AES processing completion + hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; + + /* CCF flag indicating header phase AES processing completion will be checked at the start of the next phase: - payload phase (GCM / CCM when applicable) - - final phase (GMAC or CMAC when applicable). */ + - final phase (GMAC or CMAC when applicable). */ } else { /* Local variable headerlength is a number of bytes multiple of 128 bits, remaining header data (if any) are handled after this loop */ - headerlength = (((hcryp->Init.HeaderSize)/16)*16) ; + headerlength = (((hcryp->Init.HeaderSize)/16)*16) ; /* Store the ending transfer point */ hcryp->pCrypInBuffPtr = hcryp->Init.Header + headerlength; hcryp->CrypInCount = (uint32_t)(hcryp->Init.HeaderSize - headerlength); /* remainder */ - - /* Set the input and output addresses and start DMA transfer */ + + /* Set the input and output addresses and start DMA transfer */ /* (incomplete DMA transfer, will be wrapped up after completion of the first one (initiated here) with data padding */ CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, headerlength, 0); - } + } } else { hcryp->CrypInCount = 0; - /* Set the input address and start DMA transfer */ - CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, hcryp->Init.HeaderSize, 0); + /* Set the input address and start DMA transfer */ + CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, hcryp->Init.HeaderSize, 0); } } /*============================================*/ @@ -1577,16 +1577,16 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI /*============================================*/ else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) { - /* Coming from header phase, wait for CCF flag to be raised + /* Coming from header phase, wait for CCF flag to be raised if header present and fed to the IP in the previous phase */ if (hcryp->Init.Header != NULL) - { - if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + { + if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; - } + } } else { @@ -1594,109 +1594,113 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI __HAL_CRYP_ENABLE(hcryp); } /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PAYLOAD_PHASE); - + /* No payload case */ if (pInputData == NULL) { - hcryp->State = HAL_CRYP_STATE_READY; + hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the header phase is over */ - hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; + hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; /* Process Unlocked */ __HAL_UNLOCK(hcryp); - - return HAL_OK; + + return HAL_OK; } - - - /* Specific handling to manage payload size less than 128 bits */ + + + /* Specific handling to manage payload size less than 128 bits */ if ((Size % 16) != 0) { inputaddr = (uint32_t)pInputData; - outputaddr = (uint32_t)pOutputData; + outputaddr = (uint32_t)pOutputData; if (Size < 16) { /* Block is now entered in polling mode, no actual gain in resorting to DMA */ hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr; - - CRYP_Padding(hcryp, (uint32_t)Size, CRYP_POLLING_ON); - + + CRYP_Padding(hcryp, (uint32_t)Size, CRYP_POLLING_ON); + /* Change the CRYP state to ready */ hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the payload phase is over */ - hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; - + hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; + /* Call output data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->OutCpltCallback(hcryp); +#else HAL_CRYP_OutCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } else { - payloadlength = (Size/16) * 16; - + payloadlength = (Size/16) * 16; + /* Store the ending transfer points */ hcryp->pCrypInBuffPtr = pInputData + payloadlength; hcryp->pCrypOutBuffPtr = pOutputData + payloadlength; hcryp->CrypInCount = (uint32_t)(Size - payloadlength); /* remainder */ - - /* Set the input and output addresses and start DMA transfer */ - /* (incomplete DMA transfer, will be wrapped up with data padding + + /* Set the input and output addresses and start DMA transfer */ + /* (incomplete DMA transfer, will be wrapped up with data padding after completion of the one initiated here) */ - CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, payloadlength, outputaddr); + CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, payloadlength, outputaddr); } } else - { - hcryp->CrypInCount = 0; + { + hcryp->CrypInCount = 0; inputaddr = (uint32_t)pInputData; outputaddr = (uint32_t)pOutputData; - - /* Set the input and output addresses and start DMA transfer */ - CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - } + + /* Set the input and output addresses and start DMA transfer */ + CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); + } } /*==================================*/ /* GCM/GMAC/CCM or CMAC final phase */ /*==================================*/ else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE) { - /* If coming from header phase (GMAC or CMAC case when applicable), + /* If coming from header phase (GMAC or CMAC case when applicable), wait for CCF flag to be raised */ if (READ_BIT(hcryp->Instance->CR, AES_CR_GCMPH) == CRYP_HEADER_PHASE) - { - if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + { + if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - } - + } + tagaddr = (uint32_t)pOutputData; -#if defined(AES_CR_NPBLB) +#if defined(AES_CR_NPBLB) /* By default, clear NPBLB field */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB); -#endif +#endif MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE); - + /* if the header and payload phases have been bypassed, AES must be enabled again */ if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER) { - __HAL_CRYP_ENABLE(hcryp); + __HAL_CRYP_ENABLE(hcryp); } - + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) { headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */ - inputlength = Size * 8; /* input length in bits */ + inputlength = Size * 8; /* input length in bits */ /* Write the number of bits in the header on 64 bits followed by the number of bits in the payload on 64 bits as well */ -#if !defined(AES_CR_NPBLB) +#if !defined(AES_CR_NPBLB) if(hcryp->Init.DataType == CRYP_DATATYPE_1B) { hcryp->Instance->DINR = __RBIT((headerlength)>>32); @@ -1716,7 +1720,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI hcryp->Instance->DINR = __ROR((headerlength)>>32, 16); hcryp->Instance->DINR = __ROR(headerlength, 16); hcryp->Instance->DINR = __ROR((inputlength)>>32, 16); - hcryp->Instance->DINR = __ROR(inputlength, 16); + hcryp->Instance->DINR = __ROR(inputlength, 16); } else if(hcryp->Init.DataType == CRYP_DATATYPE_32B) { @@ -1730,13 +1734,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI hcryp->Instance->DINR = (uint32_t)(headerlength); hcryp->Instance->DINR = (uint32_t)(inputlength>>32); hcryp->Instance->DINR = (uint32_t)(inputlength); -#endif +#endif } -#if !defined(AES_CR_NPBLB) +#if !defined(AES_CR_NPBLB) else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) { __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - + inputaddr = (uint32_t)pInputData; /* Enter the last block made of a 128-bit value formatted from the original B0 packet. */ @@ -1748,13 +1752,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI inputaddr+=4; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); } -#endif - - /* No DMA transfer is required at that point therefore, the software +#endif + + /* No DMA transfer is required at that point therefore, the software just waits for the CCF flag to be raised. */ - if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } @@ -1767,10 +1771,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; tagaddr+=4; *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - + /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Mark that the final phase is over */ hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER; hcryp->State = HAL_CRYP_STATE_READY; @@ -1784,13 +1788,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI else { hcryp->State = HAL_CRYP_STATE_ERROR; - __HAL_UNLOCK(hcryp); + __HAL_UNLOCK(hcryp); return HAL_ERROR; - } - + } + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + return HAL_OK; } else @@ -1803,18 +1807,18 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI * @} */ -/** @defgroup CRYPEx_Exported_Functions_Group3 AES suspension/resumption functions - * @brief Extended processing functions. +/** @defgroup CRYPEx_Exported_Functions_Group3 AES suspension/resumption functions + * @brief Extended processing functions. * -@verbatim +@verbatim ============================================================================== ##### AES extended suspension and resumption functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: (+) save in memory the Initialization Vector, the Key registers, the Control register or the Suspend registers when a process is suspended by a higher priority message (+) write back in CRYP hardware block the saved values listed above when the suspended - lower priority message processing is resumed. + lower priority message processing is resumed. @endverbatim * @{ @@ -1822,20 +1826,20 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI /** - * @brief In case of message processing suspension, read the Initialization Vector. + * @brief In case of message processing suspension, read the Initialization Vector. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. + * the configuration information for CRYP module. * @param Output: Pointer to the buffer containing the saved Initialization Vector. * @note This value has to be stored for reuse by writing the AES_IVRx registers * as soon as the interrupted processing has to be resumed. - * Applicable to all chaining modes. - * @note AES must be disabled when reading or resetting the IV values. + * Applicable to all chaining modes. + * @note AES must be disabled when reading or resetting the IV values. * @retval None */ void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output) { uint32_t outputaddr = (uint32_t)Output; - + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR3); outputaddr+=4; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR2); @@ -1849,17 +1853,17 @@ void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output) * @brief In case of message processing resumption, rewrite the Initialization * Vector in the AES_IVRx registers. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. + * the configuration information for CRYP module. * @param Input: Pointer to the buffer containing the saved Initialization Vector to - * write back in the CRYP hardware block. - * @note Applicable to all chaining modes. - * @note AES must be disabled when reading or resetting the IV values. + * write back in the CRYP hardware block. + * @note Applicable to all chaining modes. + * @note AES must be disabled when reading or resetting the IV values. * @retval None */ void HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input) { uint32_t ivaddr = (uint32_t)Input; - + hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr)); ivaddr+=4; hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr)); @@ -1871,36 +1875,40 @@ void HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input) /** - * @brief In case of message GCM/GMAC (CCM/CMAC when applicable) processing suspension, + * @brief In case of message GCM/GMAC (CCM/CMAC when applicable) processing suspension, * read the Suspend Registers. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. + * the configuration information for CRYP module. * @param Output: Pointer to the buffer containing the saved Suspend Registers. * @note These values have to be stored for reuse by writing back the AES_SUSPxR registers - * as soon as the interrupted processing has to be resumed. + * as soon as the interrupted processing has to be resumed. * @retval None */ void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output) { uint32_t outputaddr = (uint32_t)Output; - + /* In case of GCM payload phase encryption, check that suspension can be carried out */ if (READ_BIT(hcryp->Instance->CR, (AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_PAYLOAD_PHASE|CRYP_ALGOMODE_ENCRYPT)) { /* Ensure that Busy flag is reset */ - if(CRYP_WaitOnBusyFlagReset(hcryp, CRYP_BUSY_TIMEOUTVALUE) != HAL_OK) - { + if(CRYP_WaitOnBusyFlagReset(hcryp, CRYP_BUSY_TIMEOUTVALUE) != HAL_OK) + { hcryp->ErrorCode |= HAL_CRYP_BUSY_ERROR; hcryp->State = HAL_CRYP_STATE_ERROR; - + /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - + __HAL_UNLOCK(hcryp); + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->ErrorCallback(hcryp); +#else HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ return ; } - } - + } + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP7R); outputaddr+=4; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP6R); @@ -1913,24 +1921,24 @@ void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output outputaddr+=4; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP2R); outputaddr+=4; - *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP1R); + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP1R); outputaddr+=4; - *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP0R); + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP0R); } /** * @brief In case of message GCM/GMAC (CCM/CMAC when applicable) processing resumption, rewrite the Suspend * Registers in the AES_SUSPxR registers. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. + * the configuration information for CRYP module. * @param Input: Pointer to the buffer containing the saved suspend registers to - * write back in the CRYP hardware block. + * write back in the CRYP hardware block. * @retval None */ void HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input) { uint32_t ivaddr = (uint32_t)Input; - + hcryp->Instance->SUSP7R = __REV(*(uint32_t*)(ivaddr)); ivaddr+=4; hcryp->Instance->SUSP6R = __REV(*(uint32_t*)(ivaddr)); @@ -1945,24 +1953,24 @@ void HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input ivaddr+=4; hcryp->Instance->SUSP1R = __REV(*(uint32_t*)(ivaddr)); ivaddr+=4; - hcryp->Instance->SUSP0R = __REV(*(uint32_t*)(ivaddr)); + hcryp->Instance->SUSP0R = __REV(*(uint32_t*)(ivaddr)); } /** * @brief In case of message GCM/GMAC (CCM/CMAC when applicable) processing suspension, read the Key Registers. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. - * @param Output: Pointer to the buffer containing the saved Key Registers. + * the configuration information for CRYP module. + * @param Output: Pointer to the buffer containing the saved Key Registers. * @param KeySize: Indicates the key size (128 or 256 bits). * @note These values have to be stored for reuse by writing back the AES_KEYRx registers - * as soon as the interrupted processing has to be resumed. + * as soon as the interrupted processing has to be resumed. * @retval None */ void HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t KeySize) { uint32_t keyaddr = (uint32_t)Output; - + if (KeySize == CRYP_KEYSIZE_256B) { *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR7); @@ -1972,32 +1980,32 @@ void HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, ui *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR5); keyaddr+=4; *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR4); - keyaddr+=4; - } - + keyaddr+=4; + } + *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR3); keyaddr+=4; *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR2); keyaddr+=4; *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR1); keyaddr+=4; - *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR0); + *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR0); } /** * @brief In case of message GCM/GMAC (CCM/CMAC when applicable) processing resumption, rewrite the Key * Registers in the AES_KEYRx registers. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. + * the configuration information for CRYP module. * @param Input: Pointer to the buffer containing the saved key registers to - * write back in the CRYP hardware block. - * @param KeySize: Indicates the key size (128 or 256 bits) + * write back in the CRYP hardware block. + * @param KeySize: Indicates the key size (128 or 256 bits) * @retval None */ void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize) -{ +{ uint32_t keyaddr = (uint32_t)Input; - + if (KeySize == CRYP_KEYSIZE_256B) { hcryp->Instance->KEYR7 = __REV(*(uint32_t*)(keyaddr)); @@ -2007,46 +2015,46 @@ void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, ui hcryp->Instance->KEYR5 = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; hcryp->Instance->KEYR4 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - } - + keyaddr+=4; + } + hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; - hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr)); + hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr)); } /** * @brief In case of message GCM/GMAC (CCM/CMAC when applicable) processing suspension, read the Control Register. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. + * the configuration information for CRYP module. * @param Output: Pointer to the buffer containing the saved Control Register. * @note This values has to be stored for reuse by writing back the AES_CR register - * as soon as the interrupted processing has to be resumed. + * as soon as the interrupted processing has to be resumed. * @retval None */ void HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output) { - *(uint32_t*)(Output) = hcryp->Instance->CR; + *(uint32_t*)(Output) = hcryp->Instance->CR; } /** * @brief In case of message GCM/GMAC (CCM/CMAC when applicable) processing resumption, rewrite the Control * Registers in the AES_CR register. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. + * the configuration information for CRYP module. * @param Input: Pointer to the buffer containing the saved Control Register to - * write back in the CRYP hardware block. + * write back in the CRYP hardware block. * @retval None */ void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input) -{ +{ hcryp->Instance->CR = *(uint32_t*)(Input); - /* At the same time, set handle state back to READY to be able to resume the AES calculations + /* At the same time, set handle state back to READY to be able to resume the AES calculations without the processing APIs returning HAL_BUSY when called. */ hcryp->State = HAL_CRYP_STATE_READY; } @@ -2054,15 +2062,15 @@ void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input) /** * @brief Request CRYP processing suspension when in polling or interruption mode. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. - * @note Set the handle field SuspendRequest to the appropriate value so that - * the on-going CRYP processing is suspended as soon as the required + * the configuration information for CRYP module. + * @note Set the handle field SuspendRequest to the appropriate value so that + * the on-going CRYP processing is suspended as soon as the required * conditions are met. - * @note It is advised not to suspend the CRYP processing when the DMA controller - * is managing the data transfer + * @note It is advised not to suspend the CRYP processing when the DMA controller + * is managing the data transfer * @retval None */ -void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp) +void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp) { /* Set Handle Suspend Request field */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND; @@ -2086,48 +2094,52 @@ void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp) * @note Specific setting of hcryp fields are required only * in the case of header phase where no output data DMA * transfer is on-going (only input data transfer is enabled - * in such a case). + * in such a case). * @param hdma: DMA handle. * @retval None */ -static void CRYP_Authentication_DMAInCplt(DMA_HandleTypeDef *hdma) +static void CRYP_Authentication_DMAInCplt(DMA_HandleTypeDef *hdma) { uint32_t difflength = 0; - + CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - + /* Disable the DMA transfer for input request */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) - { - + { + if (hcryp->CrypInCount != 0) { /* Last block is now entered in polling mode, no actual gain in resorting to DMA */ difflength = hcryp->CrypInCount; hcryp->CrypInCount = 0; - - CRYP_Padding(hcryp, difflength, CRYP_POLLING_OFF); + + CRYP_Padding(hcryp, difflength, CRYP_POLLING_OFF); } - hcryp->State = HAL_CRYP_STATE_READY; + hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the header phase is over */ hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; } - /* CCF flag indicating header phase AES processing completion + /* CCF flag indicating header phase AES processing completion will be checked at the start of the next phase: - payload phase (GCM or CCM when applicable) - final phase (GMAC or CMAC). This allows to avoid the Wait on Flag within the IRQ handling. */ - + /* Call input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->InCpltCallback(hcryp); +#else HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } /** * @brief DMA CRYP Output Data process complete callback * for GCM, GMAC, CCM or CMAC chaining modes. - * @note This callback is called only in the payload phase. + * @note This callback is called only in the payload phase. * @param hdma: DMA handle. * @retval None */ @@ -2135,30 +2147,34 @@ static void CRYP_Authentication_DMAOutCplt(DMA_HandleTypeDef *hdma) { uint32_t difflength = 0; CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - + /* Disable the DMA transfer for output request */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - + /* Initiate additional transfer to wrap-up data feeding to the IP */ if (hcryp->CrypInCount != 0) { /* Last block is now entered in polling mode, no actual gain in resorting to DMA */ difflength = hcryp->CrypInCount; hcryp->CrypInCount = 0; - - CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON); - } - + + CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON); + } + /* Change the CRYP state to ready */ hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the payload phase is over */ - hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; - + hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; + /* Call output data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->OutCpltCallback(hcryp); +#else HAL_CRYP_OutCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } /** @@ -2170,21 +2186,25 @@ static void CRYP_Authentication_DMAOutCplt(DMA_HandleTypeDef *hdma) static void CRYP_Authentication_DMAError(DMA_HandleTypeDef *hdma) { CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - + hcryp->State= HAL_CRYP_STATE_ERROR; hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR; +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->ErrorCallback(hcryp); +#else HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ /* Clear Error Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR); } -/** +/** * @brief Handle CRYP block input/output data handling under interruption - * for GCM, GMAC, CCM or CMAC chaining modes. + * for GCM, GMAC, CCM or CMAC chaining modes. * @note The function is called under interruption only, once - * interruptions have been enabled by HAL_CRYPEx_AES_Auth_IT(). + * interruptions have been enabled by HAL_CRYPEx_AES_Auth_IT(). * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status @@ -2192,23 +2212,23 @@ static void CRYP_Authentication_DMAError(DMA_HandleTypeDef *hdma) HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) { uint32_t inputaddr = 0x0; - uint32_t outputaddr = 0x0; + uint32_t outputaddr = 0x0; uint32_t index = 0x0; - uint32_t addhoc_process = 0; + uint32_t addhoc_process = 0; uint32_t difflength = 0; uint32_t difflengthmod4 = 0; uint32_t mask[4][3] = { {0xFF000000, 0xFFFF0000, 0xFFFFFF00}, /* 32-bit data */ {0x0000FF00, 0x0000FFFF, 0xFF00FFFF}, /* 16-bit data */ {0x000000FF, 0x0000FFFF, 0x00FFFFFF}, /* 8-bit data */ {0x000000FF, 0x0000FFFF, 0x00FFFFFF}}; /* Bit data */ - uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos; - uint32_t intermediate_data[4] = {0}; - + uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos; + uint32_t intermediate_data[4] = {0}; + if(hcryp->State == HAL_CRYP_STATE_BUSY) { /*===========================*/ /* GCM/GMAC(/CCM) init phase */ - /*===========================*/ + /*===========================*/ if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE) { /* Clear Computation Complete Flag */ @@ -2217,19 +2237,23 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; - + /* Mark that the initialization phase is over */ hcryp->Phase = HAL_CRYP_PHASE_INIT_OVER; - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); /* Call computation complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->CompCpltCallback(hcryp); +#else HAL_CRYPEx_ComputationCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ return HAL_OK; } /*========================================*/ /* GCM/GMAC (or CCM or CMAC) header phase */ - /*========================================*/ + /*========================================*/ else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) { /* Check if all input header data have been entered */ @@ -2243,13 +2267,17 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the header phase is over */ hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + /* Call computation complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->CompCpltCallback(hcryp); +#else HAL_CRYPEx_ComputationCpltCallback(hcryp); - +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + return HAL_OK; } /* If suspension flag has been raised, suspend processing */ @@ -2257,7 +2285,7 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) { /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - + /* reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; /* Disable Computation Complete Flag and Errors Interrupts */ @@ -2266,39 +2294,39 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) hcryp->State = HAL_CRYP_STATE_SUSPENDED; /* Mark that the header phase is suspended */ hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED; - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + return HAL_OK; - } + } else /* Carry on feeding input data to the CRYP hardware block */ { /* Clear Computation Complete Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); /* Get the last Input data address */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - + /* Increment/decrement instance pointer/counter */ if (hcryp->CrypInCount < 16) { - difflength = hcryp->CrypInCount; + difflength = hcryp->CrypInCount; hcryp->CrypInCount = 0; - addhoc_process = 1; - difflengthmod4 = difflength%4; + addhoc_process = 1; + difflengthmod4 = difflength%4; } else { hcryp->pCrypInBuffPtr += 16; hcryp->CrypInCount -= 16; - } - -#if defined(AES_CR_NPBLB) + } + +#if defined(AES_CR_NPBLB) if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM) -#else +#else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) -#endif - { +#endif + { if (hcryp->CrypInCount == hcryp->Init.HeaderSize) { /* All B blocks will have been entered after the next @@ -2306,11 +2334,11 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) the next iteration */ hcryp->pCrypInBuffPtr = hcryp->Init.Header; } - } - + } + /* Write the Input block in the Data Input register */ if (addhoc_process == 0) - { + { hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); @@ -2321,7 +2349,7 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) } else { - /* Header remainder has size less than 128 bits */ + /* Header remainder has size less than 128 bits */ /* Enter complete words when possible */ for( ; index < (difflength/4); index ++) { @@ -2329,118 +2357,122 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; } - /* Enter incomplete word padded with zeroes if applicable + /* Enter incomplete word padded with zeroes if applicable (case of header length not a multiple of 32-bits) */ if (difflengthmod4 != 0) - { + { hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); - } + } /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */ - for(index=0; index < (4 - ((difflength+3)/4)); index ++) + for(index=0; index < (4 - ((difflength+3)/4)); index ++) { hcryp->Instance->DINR = 0; - } + } } - - return HAL_OK; + + return HAL_OK; } } /*=======================*/ /* GCM/CCM payload phase */ - /*=======================*/ + /*=======================*/ else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) { /* Get the last output data address */ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - + /* Specific handling to manage payload size less than 128 bits when GCM (or CCM when applicable) encryption or decryption is selected. Check here if the last block output data are read */ -#if defined(AES_CR_NPBLB) +#if defined(AES_CR_NPBLB) if ((hcryp->CrypOutCount < 16) && \ (hcryp->CrypOutCount > 0)) -#else +#else if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) && \ (hcryp->CrypOutCount < 16) && \ (hcryp->CrypOutCount > 0)) -#endif +#endif { addhoc_process = 1; difflength = hcryp->CrypOutCount; - difflengthmod4 = difflength%4; - hcryp->CrypOutCount = 0; /* mark that no more output data will be needed */ + difflengthmod4 = difflength%4; + hcryp->CrypOutCount = 0; /* mark that no more output data will be needed */ /* Retrieve intermediate data */ for(index=0; index < 4; index ++) { - intermediate_data[index] = hcryp->Instance->DOUTR; - } + intermediate_data[index] = hcryp->Instance->DOUTR; + } /* Retrieve last words of cyphered data */ /* First, retrieve complete output words */ for(index=0; index < (difflength/4); index ++) { *(uint32_t*)(outputaddr) = intermediate_data[index]; - outputaddr+=4; - } + outputaddr+=4; + } /* Next, retrieve partial output word if applicable; - at the same time, start masking intermediate data + at the same time, start masking intermediate data with a mask of zeros of same size than the padding - applied to the last block of payload */ + applied to the last block of payload */ if (difflengthmod4 != 0) { intermediate_data[difflength/4] &= mask[mask_index][difflengthmod4-1]; - *(uint32_t*)(outputaddr) = intermediate_data[difflength/4]; - } - -#if !defined(AES_CR_NPBLB) + *(uint32_t*)(outputaddr) = intermediate_data[difflength/4]; + } + +#if !defined(AES_CR_NPBLB) if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) - { + { /* Change again CHMOD configuration to GCM mode */ - __HAL_CRYP_SET_CHAININGMODE(hcryp, CRYP_CHAINMODE_AES_GCM_GMAC); - + __HAL_CRYP_SET_CHAININGMODE(hcryp, CRYP_CHAINMODE_AES_GCM_GMAC); + /* Select FINAL phase */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE); - + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE); + /* Before inserting the intermediate data, carry on masking operation with a mask of zeros of same size than the padding applied to the last block of payload */ - for(index=0; index < (4 - ((difflength+3)/4)); index ++) + for(index=0; index < (4 - ((difflength+3)/4)); index ++) { intermediate_data[(difflength+3)/4+index] = 0; - } - + } + /* Insert intermediate data to trigger an additional DOUTR reading round */ /* Clear Computation Complete Flag before entering new block */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); for(index=0; index < 4; index ++) { - hcryp->Instance->DINR = intermediate_data[index]; + hcryp->Instance->DINR = intermediate_data[index]; } } else -#endif +#endif { /* Payload phase is now over */ /* Clear Computation Complete Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); /* Disable Computation Complete Flag and Errors Interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the payload phase is over */ hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + /* Call computation complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->CompCpltCallback(hcryp); +#else HAL_CRYPEx_ComputationCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } return HAL_OK; } - else - { + else + { if (hcryp->CrypOutCount != 0) - { - /* Usual case (different than GCM/CCM last block < 128 bits ciphering) */ + { + /* Usual case (different than GCM/CCM last block < 128 bits ciphering) */ /* Retrieve the last block available from the CRYP hardware block: read the output block from the Data Output Register */ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; @@ -2450,49 +2482,53 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; outputaddr+=4; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - + /* Increment/decrement instance pointer/counter */ hcryp->pCrypOutBuffPtr += 16; - hcryp->CrypOutCount -= 16; + hcryp->CrypOutCount -= 16; } -#if !defined(AES_CR_NPBLB) +#if !defined(AES_CR_NPBLB) else - { + { /* Software work-around: additional DOUTR reading round to discard the data */ for(index=0; index < 4; index ++) { - intermediate_data[index] = hcryp->Instance->DOUTR; - } + intermediate_data[index] = hcryp->Instance->DOUTR; + } } -#endif - } - +#endif + } + /* Check if all output text has been retrieved */ if (hcryp->CrypOutCount == 0) { /* Clear Computation Complete Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); /* Disable Computation Complete Flag and Errors Interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the payload phase is over */ hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + /* Call computation complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->CompCpltCallback(hcryp); +#else HAL_CRYPEx_ComputationCpltCallback(hcryp); - +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + return HAL_OK; } /* If suspension flag has been raised, suspend processing */ else if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND) - { + { /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - + /* reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; /* Disable Computation Complete Flag and Errors Interrupts */ @@ -2501,49 +2537,49 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) hcryp->State = HAL_CRYP_STATE_SUSPENDED; /* Mark that the payload phase is suspended */ hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_SUSPENDED; - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + return HAL_OK; - } + } else /* Output data are still expected, carry on feeding the CRYP hardware block with input data */ { /* Clear Computation Complete Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); /* Get the last Input data address */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - + /* Usual input data feeding case */ if (hcryp->CrypInCount < 16) { difflength = (uint32_t) (hcryp->CrypInCount); difflengthmod4 = difflength%4; - hcryp->CrypInCount = 0; - -#if defined(AES_CR_NPBLB) + hcryp->CrypInCount = 0; + +#if defined(AES_CR_NPBLB) /* In case of GCM encryption or CCM decryption, specify the number of padding bytes in last block of payload */ if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC) - && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT)) + && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT)) || ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM) && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT))) { - /* Set NPBLB field in writing the number of padding bytes + /* Set NPBLB field in writing the number of padding bytes for the last block of payload */ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, (16 - difflength) << AES_POSITION_CR_NPBLB); } -#else - /* Software workaround applied to GCM encryption only */ +#else + /* Software workaround applied to GCM encryption only */ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) { - /* Change the mode configured in CHMOD bits of CR register to select CTR mode */ + /* Change the mode configured in CHMOD bits of CR register to select CTR mode */ __HAL_CRYP_SET_CHAININGMODE(hcryp, CRYP_CHAINMODE_AES_CTR); - } -#endif - - /* Insert the last block (which size is inferior to 128 bits) padded with zeroes + } +#endif + + /* Insert the last block (which size is inferior to 128 bits) padded with zeroes to have a complete block of 128 bits */ for(index=0; index < (difflength/4); index ++) { @@ -2553,21 +2589,21 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) } /* If required, manage input data size not multiple of 32 bits */ if (difflengthmod4 != 0) - { + { hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); - } + } /* Wrap-up in padding with zero-words if applicable */ - for(index=0; index < (4 - ((difflength+3)/4)); index ++) + for(index=0; index < (4 - ((difflength+3)/4)); index ++) { hcryp->Instance->DINR = 0; - } - + } + } else { hcryp->pCrypInBuffPtr += 16; hcryp->CrypInCount -= 16; - + /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; @@ -2575,24 +2611,24 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) inputaddr+=4; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - } - - - return HAL_OK; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + } + + + return HAL_OK; } } /*=======================================*/ /* GCM/GMAC (or CCM or CMAC) final phase */ - /*=======================================*/ + /*=======================================*/ else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE) { /* Clear Computation Complete Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Get the last output data address */ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - + /* Retrieve the last expected data from the CRYP hardware block: read the output block from the Data Output Register */ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; @@ -2602,50 +2638,54 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; outputaddr+=4; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - + /* Disable Computation Complete Flag and Errors Interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the header phase is over */ hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER; - + /* Disable the Peripheral */ __HAL_CRYP_DISABLE(hcryp); /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + /* Call computation complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->CompCpltCallback(hcryp); +#else HAL_CRYPEx_ComputationCpltCallback(hcryp); - +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + return HAL_OK; } else { /* Clear Computation Complete Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - hcryp->State = HAL_CRYP_STATE_ERROR; - __HAL_UNLOCK(hcryp); - return HAL_ERROR; + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + hcryp->State = HAL_CRYP_STATE_ERROR; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } } else { - return HAL_BUSY; - } + return HAL_BUSY; + } } - - - -/** + + + +/** * @brief Set the DMA configuration and start the DMA transfer - * for GCM, GMAC, CCM or CMAC chaining modes. + * for GCM, GMAC, CCM or CMAC chaining modes. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. * @param inputaddr: Address of the Input buffer. * @param Size: Size of the Input buffer un bytes, must be a multiple of 16. * @param outputaddr: Address of the Output buffer, null pointer when no output DMA stream - * has to be configured. + * has to be configured. * @retval None */ static void CRYP_Authentication_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr) @@ -2655,34 +2695,34 @@ static void CRYP_Authentication_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t hcryp->hdmain->XferCpltCallback = CRYP_Authentication_DMAInCplt; /* Set the DMA error callback */ hcryp->hdmain->XferErrorCallback = CRYP_Authentication_DMAError; - - if (outputaddr != 0) - { + + if (outputaddr != 0) + { /* Set the output CRYP DMA transfer complete callback */ hcryp->hdmaout->XferCpltCallback = CRYP_Authentication_DMAOutCplt; /* Set the DMA error callback */ hcryp->hdmaout->XferErrorCallback = CRYP_Authentication_DMAError; } - + /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); - + /* Enable the DMA input stream */ HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4); - + /* Enable the DMA input request */ SET_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); - - if (outputaddr != 0) - { + + if (outputaddr != 0) + { /* Enable the DMA output stream */ HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4); - + /* Enable the DMA output request */ SET_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN); } -} +} @@ -2693,7 +2733,7 @@ static void CRYP_Authentication_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t * @param Input: Pointer to the Input buffer. * @param Ilength: Length of the Input buffer in bytes, must be a multiple of 16. * @param Output: Pointer to the returned buffer. - * @param Timeout: Specify Timeout value. + * @param Timeout: Specify Timeout value. * @retval HAL status */ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) @@ -2701,7 +2741,7 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In uint32_t index = 0; uint32_t inputaddr = (uint32_t)Input; uint32_t outputaddr = (uint32_t)Output; - + for(index=0; (index < Ilength); index += 16) { @@ -2714,18 +2754,18 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In inputaddr+=4; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - + /* Wait for CCF flag to be raised */ - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } - + /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - + /* Read the Output block from the Data Output Register */ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; outputaddr+=4; @@ -2735,27 +2775,27 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In outputaddr+=4; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; outputaddr+=4; - + /* If the suspension flag has been raised and if the processing is not about to end, suspend processing */ if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < Ilength)) { /* Reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; - + /* Save current reading and writing locations of Input and Output buffers */ hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr; hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; /* Save the number of bytes that remain to be processed at this point */ hcryp->CrypInCount = Ilength - (index+16); - + /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_SUSPENDED; - + return HAL_OK; } - - + + } /* Return function status */ return HAL_OK; @@ -2772,26 +2812,26 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. * @param Output: Pointer to the returned buffer. - * @param Timeout: Specify Timeout value. + * @param Timeout: Specify Timeout value. * @retval HAL status */ static HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t Timeout) { uint32_t outputaddr = (uint32_t)Output; - - /* Wait for CCF flag to be raised */ - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + + /* Wait for CCF flag to be raised */ + if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - + /* Read the derivative key from the AES_KEYRx registers */ if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B) - { + { *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR7); outputaddr+=4; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR6); @@ -2801,7 +2841,7 @@ static HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR4); outputaddr+=4; } - + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR3); outputaddr+=4; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR2); @@ -2810,7 +2850,7 @@ static HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output outputaddr+=4; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR0); - + /* Return function status */ return HAL_OK; } @@ -2830,7 +2870,7 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt; /* Set the DMA error callback */ hcryp->hdmain->XferErrorCallback = CRYP_DMAError; - + /* Set the CRYP DMA transfer complete callback */ hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt; /* Set the DMA error callback */ @@ -2844,7 +2884,7 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin /* Enable In and Out DMA requests */ SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN)); - + /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); } @@ -2853,57 +2893,57 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin /** * @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. + * the configuration information for CRYP module. * @param Timeout: Timeout duration. * @retval HAL status */ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { uint32_t tickstart = 0; - + /* Get timeout */ tickstart = HAL_GetTick(); - + while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) - { + { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { if((HAL_GetTick() - tickstart ) > Timeout) - { + { return HAL_TIMEOUT; } } } - return HAL_OK; + return HAL_OK; } /** - * @brief Wait for Busy Flag to be reset during a GCM payload encryption process suspension. + * @brief Wait for Busy Flag to be reset during a GCM payload encryption process suspension. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. + * the configuration information for CRYP module. * @param Timeout: Timeout duration. * @retval HAL status */ static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { uint32_t tickstart = 0; - + /* Get timeout */ tickstart = HAL_GetTick(); - + while(HAL_IS_BIT_SET(hcryp->Instance->SR, AES_SR_BUSY)) - { + { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { if((HAL_GetTick() - tickstart ) > Timeout) - { + { return HAL_TIMEOUT; } } } - return HAL_OK; + return HAL_OK; } @@ -2912,15 +2952,19 @@ static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uin * @param hdma: DMA handle. * @retval None */ -static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) +static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) { CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - + /* Disable the DMA transfer for input request */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); - + /* Call input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->InCpltCallback(hcryp); +#else HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } /** @@ -2929,89 +2973,97 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) * @retval None */ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) -{ +{ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - + /* Disable the DMA transfer for output request */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - + /* Disable CRYP */ __HAL_CRYP_DISABLE(hcryp); - + /* Change the CRYP state to ready */ hcryp->State = HAL_CRYP_STATE_READY; - + /* Call output data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->OutCpltCallback(hcryp); +#else HAL_CRYP_OutCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } /** - * @brief DMA CRYP communication error callback. + * @brief DMA CRYP communication error callback. * @param hdma: DMA handle. * @retval None */ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) { CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - + hcryp->State= HAL_CRYP_STATE_ERROR; - hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR; + hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR; +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->ErrorCallback(hcryp); +#else HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ /* Clear Error Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR); } /** - * @brief Last header or payload block padding when size is not a multiple of 128 bits. + * @brief Last header or payload block padding when size is not a multiple of 128 bits. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. + * the configuration information for CRYP module. * @param difflength: size remainder after having fed all complete 128-bit blocks. * @param polling: specifies whether or not polling on CCF must be done after having - * entered a complete block. + * entered a complete block. * @retval None */ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_t polling) { uint32_t index = 0; uint32_t difflengthmod4 = difflength%4; - uint32_t inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - uint32_t outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; + uint32_t inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + uint32_t outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; uint32_t mask[4][3] = { {0xFF000000, 0xFFFF0000, 0xFFFFFF00}, /* 32-bit data */ {0x0000FF00, 0x0000FFFF, 0xFF00FFFF}, /* 16-bit data */ {0x000000FF, 0x0000FFFF, 0x00FFFFFF}, /* 8-bit data */ {0x000000FF, 0x0000FFFF, 0x00FFFFFF}}; /* Bit data */ - uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos; - + uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos; + uint32_t intermediate_data[4] = {0}; - -#if defined(AES_CR_NPBLB) + +#if defined(AES_CR_NPBLB) /* In case of GCM encryption or CCM decryption, specify the number of padding bytes in last block of payload */ if (READ_BIT(hcryp->Instance->CR,AES_CR_GCMPH) == CRYP_PAYLOAD_PHASE) { if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC) - && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT)) + && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT)) || ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM) && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT))) { - /* Set NPBLB field in writing the number of padding bytes + /* Set NPBLB field in writing the number of padding bytes for the last block of payload */ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, (16 - difflength) << AES_POSITION_CR_NPBLB); } } #else /* Software workaround applied to GCM encryption only */ - if ((hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) && + if ((hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) && (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)) { - /* Change the mode configured in CHMOD bits of CR register to select CTR mode */ + /* Change the mode configured in CHMOD bits of CR register to select CTR mode */ __HAL_CRYP_SET_CHAININGMODE(hcryp, CRYP_CHAINMODE_AES_CTR); - } -#endif - + } +#endif + /* Wrap-up entering header or payload data */ /* Enter complete words when possible */ for(index=0; index < (difflength/4); index ++) @@ -3020,26 +3072,30 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; } - /* Enter incomplete word padded with zeroes if applicable + /* Enter incomplete word padded with zeroes if applicable (case of header length not a multiple of 32-bits) */ if (difflengthmod4 != 0) - { + { hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); - } + } /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */ - for(index=0; index < (4 - ((difflength+3)/4)); index ++) + for(index=0; index < (4 - ((difflength+3)/4)); index ++) { hcryp->Instance->DINR = 0; - } + } if (polling == CRYP_POLLING_ON) { - if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->ErrorCallback(hcryp); +#else HAL_CRYP_ErrorCallback(hcryp); - } +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -3048,71 +3104,71 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_ /* if payload */ if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) { - + /* Retrieve intermediate data */ for(index=0; index < 4; index ++) { - intermediate_data[index] = hcryp->Instance->DOUTR; - } + intermediate_data[index] = hcryp->Instance->DOUTR; + } /* Retrieve last words of cyphered data */ /* First, retrieve complete output words */ for(index=0; index < (difflength/4); index ++) { *(uint32_t*)(outputaddr) = intermediate_data[index]; - outputaddr+=4; - } + outputaddr+=4; + } /* Next, retrieve partial output word if applicable; - at the same time, start masking intermediate data + at the same time, start masking intermediate data with a mask of zeros of same size than the padding - applied to the last block of payload */ + applied to the last block of payload */ if (difflengthmod4 != 0) { intermediate_data[difflength/4] &= mask[mask_index][difflengthmod4-1]; - *(uint32_t*)(outputaddr) = intermediate_data[difflength/4]; - } - - -#if !defined(AES_CR_NPBLB) + *(uint32_t*)(outputaddr) = intermediate_data[difflength/4]; + } + + +#if !defined(AES_CR_NPBLB) /* Software workaround applied to GCM encryption only, - applicable for AES IP v2 version (where NPBLB is not defined) */ + applicable for AES IP v2 version (where NPBLB is not defined) */ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) { /* Change again CHMOD configuration to GCM mode */ - __HAL_CRYP_SET_CHAININGMODE(hcryp, CRYP_CHAINMODE_AES_GCM_GMAC); - + __HAL_CRYP_SET_CHAININGMODE(hcryp, CRYP_CHAINMODE_AES_GCM_GMAC); + /* Select FINAL phase */ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE); - + /* Before inserting the intermediate data, carry on masking operation with a mask of zeros of same size than the padding applied to the last block of payload */ - for(index=0; index < (4 - ((difflength+3)/4)); index ++) + for(index=0; index < (4 - ((difflength+3)/4)); index ++) { intermediate_data[(difflength+3)/4+index] = 0; - } + } /* Insert intermediate data */ for(index=0; index < 4; index ++) { - hcryp->Instance->DINR = intermediate_data[index]; - } - - /* Wait for completion, and read data on DOUT. This data is to discard. */ - if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + hcryp->Instance->DINR = intermediate_data[index]; + } + + /* Wait for completion, and read data on DOUT. This data is to discard. */ + if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); HAL_CRYP_ErrorCallback(hcryp); - } - - /* Read data to discard */ + } + + /* Read data to discard */ /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); for(index=0; index < 4; index ++) { - intermediate_data[index] = hcryp->Instance->DOUTR; - } + intermediate_data[index] = hcryp->Instance->DOUTR; + } } /* if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) */ -#endif /* !defined(AES_CR_NPBLB) */ +#endif /* !defined(AES_CR_NPBLB) */ } /* if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) */ } @@ -3129,7 +3185,7 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_ * @} */ -#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */ +#endif /* AES */ #endif /* HAL_CRYP_MODULE_ENABLED */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c index 73fb2c5d2a..ece455a744 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c @@ -3,148 +3,148 @@ * @file stm32l4xx_hal_dac.c * @author MCD Application Team * @brief DAC HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral Control functions - * + Peripheral State and Errors functions - * + * + Peripheral State and Errors functions * - @verbatim + * + @verbatim ============================================================================== ##### DAC Peripheral features ##### ============================================================================== - [..] + [..] *** DAC Channels *** - ==================== - [..] - STM32L4 devices integrate one or two 12-bit Digital Analog Converters + ==================== + [..] + STM32L4 devices integrate one or two 12-bit Digital Analog Converters (i.e. one or 2 channel(s)) 1 channel : STM32L451xx STM32L452xx STM32L462xx 2 channels: STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx - STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx - STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx + STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx + STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx When 2 channels are available, the 2 converters (i.e. channel1 & channel2) can be used independently or simultaneously (dual mode): - (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip + (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip peripherals (ex. OPAMPs, comparators). - (#) Whenever present, DAC channel2 with DAC_OUT2 (PA5) as output + (#) Whenever present, DAC channel2 with DAC_OUT2 (PA5) as output or connected to on-chip peripherals (ex. OPAMPs, comparators). - + *** DAC Triggers *** ==================== [..] Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE - and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. - [..] + and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. + [..] Digital to Analog conversion can be triggered by: (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9. The used pin (GPIOx_PIN_9) must be configured in input mode. - - (#) Timers TRGO: TIM2, TIM3, TIM4, TIM5, TIM6 and TIM7 + + (#) Timers TRGO: TIM2, TIM3, TIM4, TIM5, TIM6 and TIM7 (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T3_TRGO...) - + (#) Software using DAC_TRIGGER_SOFTWARE - + *** DAC Buffer mode feature *** - =============================== - [..] - Each DAC channel integrates an output buffer that can be used to + =============================== + [..] + Each DAC channel integrates an output buffer that can be used to reduce the output impedance, and to drive external loads directly without having to add an external operational amplifier. - To enable, the output buffer use + To enable, the output buffer use sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; - [..] - (@) Refer to the device datasheet for more details about output + [..] + (@) Refer to the device datasheet for more details about output impedance value with and without output buffer. *** DAC connect feature *** - =============================== - [..] - Each DAC channel can be connected internally. + =============================== + [..] + Each DAC channel can be connected internally. To connect, use sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE; - + *** GPIO configurations guidelines *** ===================== - [..] - When a DAC channel is used (ex channel1 on PA4) and the other is not + [..] + When a DAC channel is used (ex channel1 on PA4) and the other is not (ex channel2 on PA5 is configured in Analog and disabled). Channel1 may disturb channel2 as coupling effect. Note that there is no coupling on channel2 as soon as channel2 is turned on. Coupling on adjacent channel could be avoided as follows: - when unused PA5 is configured as INPUT PULL-UP or DOWN. - PA5 is configured in ANALOG just before it is turned on. - + when unused PA5 is configured as INPUT PULL-UP or DOWN. + PA5 is configured in ANALOG just before it is turned on. + *** DAC Sample and Hold feature *** ======================== - [..] - For each converter, 2 modes are supported: normal mode and + [..] + For each converter, 2 modes are supported: normal mode and "sample and hold" mode (i.e. low power mode). - In the sample and hold mode, the DAC core converts data, then holds the - converted voltage on a capacitor. When not converting, the DAC cores and - buffer are completely turned off between samples and the DAC output is - tri-stated, therefore reducing the overall power consumption. A new + In the sample and hold mode, the DAC core converts data, then holds the + converted voltage on a capacitor. When not converting, the DAC cores and + buffer are completely turned off between samples and the DAC output is + tri-stated, therefore reducing the overall power consumption. A new stabilization period is needed before each new conversion. The sample and hold allow setting internal or external voltage @ - low power consumption cost (output value can be at any given rate either + low power consumption cost (output value can be at any given rate either by CPU or DMA). - The Sample and hold block and registers uses either LSI & run in - several power modes: run mode, sleep mode, low power run, low power sleep + The Sample and hold block and registers uses either LSI & run in + several power modes: run mode, sleep mode, low power run, low power sleep mode & stop1 mode. - + Low power stop1 mode allows only static conversion. - - To enable Sample and Hold mode + + To enable Sample and Hold mode Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI & RCC_LSI_ON parameters. Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE; & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime, DAC_HoldTime & DAC_RefreshTime; - + *** DAC calibration feature *** - =================================== - [..] - (#) The 2 converters (channel1 & channel2) provide calibration capabilities. + =================================== + [..] + (#) The 2 converters (channel1 & channel2) provide calibration capabilities. (++) Calibration aims at correcting some offset of output buffer. - (++) The DAC uses either factory calibration settings OR user defined + (++) The DAC uses either factory calibration settings OR user defined calibration (trimming) settings (i.e. trimming mode). - (++) The user defined settings can be figured out using self calibration + (++) The user defined settings can be figured out using self calibration handled by HAL_DACEx_SelfCalibrate. (++) HAL_DACEx_SelfCalibrate: (+++) Runs automatically the calibration. (+++) Enables the user trimming mode - (+++) Updates a structure with trimming values with fresh calibration - results. - The user may store the calibration results for larger - (ex monitoring the trimming as a function of temperature + (+++) Updates a structure with trimming values with fresh calibration + results. + The user may store the calibration results for larger + (ex monitoring the trimming as a function of temperature for instance) *** DAC wave generation feature *** - =================================== - [..] + =================================== + [..] Both DAC channels can be used to generate - (#) Noise wave + (#) Noise wave (#) Triangle wave - + *** DAC data format *** ======================= - [..] + [..] The DAC data format can be: (#) 8-bit right alignment using DAC_ALIGN_8B_R (#) 12-bit left alignment using DAC_ALIGN_12B_L (#) 12-bit right alignment using DAC_ALIGN_12B_R - - *** DAC data value to voltage correspondence *** - ================================================ - [..] + + *** DAC data value to voltage correspondence *** + ================================================ + [..] The analog output voltage on each DAC channel pin is determined by the following equation: [..] @@ -155,26 +155,26 @@ [..] e.g. To set DAC_OUT1 to 0.7V, use (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V - + *** DMA requests *** ===================== [..] - A DMA1 request can be generated when an external trigger (but not a software trigger) - occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA(). - DMA requests are mapped as following: + A DMA1 request can be generated when an external trigger (but not a software trigger) + occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA(). + DMA requests are mapped as following: (#) DAC channel1: mapped either on - (++) DMA1 request 6 channel3 + (++) DMA1 request 6 channel3 (++) or DMA2 request channel4 which must be already configured (#) DAC channel2 (whenever present): mapped either on - (++) DMA1 request 5 channel4 - (++) or DMA2 request 3 channel5 which must be already configured + (++) DMA1 request 5 channel4 + (++) or DMA2 request 3 channel5 which must be already configured [..] - (@) For Dual mode and specific signal (Triangle and noise) generation please - refer to Extended Features Driver description - + (@) For Dual mode and specific signal (Triangle and noise) generation please + refer to Extended Features Driver description + ##### How to use this driver ##### ============================================================================== - [..] + [..] (+) DAC APB clock must be enabled to get write access to DAC registers using HAL_DAC_Init() (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode. @@ -183,52 +183,110 @@ *** Calibration mode IO operation *** ====================================== - [..] + [..] (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset() - (+) Run the calibration using HAL_DACEx_SelfCalibrate() + (+) Run the calibration using HAL_DACEx_SelfCalibrate() (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming() *** Polling mode IO operation *** ================================= - [..] - (+) Start the DAC peripheral using HAL_DAC_Start() + [..] + (+) Start the DAC peripheral using HAL_DAC_Start() (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function. (+) Stop the DAC peripheral using HAL_DAC_Stop() - - *** DMA mode IO operation *** + + *** DMA mode IO operation *** ============================== - [..] - (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length + [..] + (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length of data to be transferred at each end of conversion - (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() - function is executed and user can add his own code by customization of function pointer + (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() + function is executed and user can add his own code by customization of function pointer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() - (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() - function is executed and user can add his own code by customization of function pointer + (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() + function is executed and user can add his own code by customization of function pointer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() - (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can + (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler. - HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() - function is executed and user can add his own code by customization of function pointer + HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() + function is executed and user can add his own code by customization of function pointer HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1() (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA() - + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. + (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. + (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. + (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1. + (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2. + (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2. + (+) ErrorCallbackCh2 : callback when an error occurs on Ch2. + (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2. + (+) MspInitCallback : DAC MspInit. + (+) MspDeInitCallback : DAC MspdeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. + (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. + (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. + (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1. + (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2. + (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2. + (+) ErrorCallbackCh2 : callback when an error occurs on Ch2. + (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2. + (+) MspInitCallback : DAC MspInit. + (+) MspDeInitCallback : DAC MspdeInit. + (+) All Callbacks + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init + and @ref HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit + or @ref HAL_DAC_Init function. + + When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + + *** DAC HAL driver macros list *** - ============================================= + ============================================= [..] Below the list of most used macros in DAC HAL driver. - + (+) __HAL_DAC_ENABLE : Enable the DAC peripheral (+) __HAL_DAC_DISABLE : Disable the DAC peripheral (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status - + [..] - (@) You can refer to the DAC HAL driver header file for more useful macros - - @endverbatim + (@) You can refer to the DAC HAL driver header file for more useful macros + + @endverbatim ****************************************************************************** * @attention * @@ -257,7 +315,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ @@ -268,9 +326,9 @@ */ /** @defgroup DAC DAC - * @brief DAC driver modules + * @brief DAC driver modules * @{ - */ + */ #ifdef HAL_DAC_MODULE_ENABLED @@ -284,7 +342,7 @@ #define HFSEL_ENABLE_THRESHOLD_80MHZ ((uint32_t)80000000) /* 80 mHz */ /** * @} - */ + */ /* Private macro -------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -295,7 +353,7 @@ */ static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); -static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); +static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); /** * @} */ @@ -305,17 +363,17 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); * @{ */ -/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Initialize and configure the DAC. - (+) De-initialize the DAC. - + (+) Initialize and configure the DAC. + (+) De-initialize the DAC. + @endverbatim * @{ */ @@ -328,7 +386,7 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) -{ +{ /* Check DAC handle */ if(hdac == NULL) { @@ -336,25 +394,52 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) } /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); - + if(hdac->State == HAL_DAC_STATE_RESET) - { + { +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + /* Init the DAC Callback settings */ + hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; + hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; + hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; + hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; + + hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; + hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; + hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; + hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; + + if(hdac->MspInitCallback == NULL) + { + hdac->MspInitCallback = HAL_DAC_MspInit; + } + if(hdac->MspDeInitCallback == NULL) + { + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + } +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + /* Allocate lock resource and initialize it */ hdac->Lock = HAL_UNLOCKED; +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + /* Init the low level hardware */ + hdac->MspInitCallback(hdac); +#else /* Init the low level hardware */ HAL_DAC_MspInit(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } - + /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_BUSY; - + /* Set DAC error code to none */ hdac->ErrorCode = HAL_DAC_ERROR_NONE; - + /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -370,7 +455,7 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) /* Check DAC handle */ if(hdac == NULL) { - return HAL_ERROR; + return HAL_ERROR; } /* Check the parameters */ @@ -379,8 +464,18 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + if(hdac->MspDeInitCallback == NULL) + { + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + } + /* DeInit the low level hardware */ + hdac->MspDeInitCallback(hdac); + +#else /* DeInit the low level hardware */ HAL_DAC_MspDeInit(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /* Set DAC error code to none */ hdac->ErrorCode = HAL_DAC_ERROR_NONE; @@ -402,19 +497,19 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) * @retval None */ __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) -{ +{ /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_MspInit could be implemented in the user file - */ + */ } /** * @brief DeInitialize the DAC MSP. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. + * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) @@ -424,7 +519,7 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_MspDeInit could be implemented in the user file - */ + */ } /** @@ -432,19 +527,19 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) */ /** @defgroup DAC_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions + * @brief IO operation functions * -@verbatim +@verbatim ============================================================================== ##### IO operation functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: (+) Start conversion. (+) Stop conversion. (+) Start conversion and enable DMA transfer. (+) Stop conversion and disable DMA transfer. (+) Get result of conversion. - + @endverbatim * @{ */ @@ -453,7 +548,7 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) * @brief Enables DAC and starts conversion of channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (when supported) @@ -463,13 +558,13 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); - + /* Process locked */ __HAL_LOCK(hdac); - + /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; - + /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); @@ -515,9 +610,9 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); } } -#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ - /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ - +#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ + /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) /* Check if software trigger enabled */ @@ -529,45 +624,45 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) #endif /* STM32L451xx STM32L452xx STM32L462xx */ /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hdac); - + /* Return function status */ return HAL_OK; } - + /** * @brief Disables DAC and stop conversion of channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); - + /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, Channel); - + /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; - + /* Return function status */ return HAL_OK; } -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) /** * @brief Enables DAC and starts conversion of channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @param pData: The destination peripheral Buffer address. @@ -582,29 +677,29 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel) HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) { uint32_t tmpreg = 0; - + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); - + /* Process locked */ __HAL_LOCK(hdac); - + /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; - + /* Set the DMA transfer complete callback for channel1 */ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; - + /* Set the DMA half transfer complete callback for channel1 */ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; - + /* Set the DMA error callback for channel1 */ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; - + /* Enable the selected DAC channel1 DMA request */ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); - + /* Case of use of channel 1 */ switch(Alignment) { @@ -622,35 +717,35 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u break; default: break; - } - + } + /* Enable the DMA channel */ /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); - + /* Enable the DMA channel */ HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); - + /* Process Unlocked */ __HAL_UNLOCK(hdac); /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); - + /* Return function status */ return HAL_OK; } -#endif /* STM32L451xx STM32L452xx STM32L462xx */ +#endif /* STM32L451xx STM32L452xx STM32L462xx */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) - + /** * @brief Enables DAC and starts conversion of channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -666,31 +761,31 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) { uint32_t tmpreg = 0; - + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); - + /* Process locked */ __HAL_LOCK(hdac); - + /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; - + if(Channel == DAC_CHANNEL_1) { /* Set the DMA transfer complete callback for channel1 */ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; - + /* Set the DMA half transfer complete callback for channel1 */ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; - + /* Set the DMA error callback for channel1 */ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; - + /* Enable the selected DAC channel1 DMA request */ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); - + /* Case of use of channel 1 */ switch(Alignment) { @@ -714,16 +809,16 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u { /* Set the DMA transfer complete callback for channel2 */ hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2; - + /* Set the DMA half transfer complete callback for channel2 */ hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2; - + /* Set the DMA error callback for channel2 */ hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2; - + /* Enable the selected DAC channel2 DMA request */ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); - + /* Case of use of channel 2 */ switch(Alignment) { @@ -743,31 +838,31 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u break; } } - + /* Enable the DMA channel */ if(Channel == DAC_CHANNEL_1) { /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); - + /* Enable the DMA channel */ HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); - } + } else { /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2); - + /* Enable the DMA channel */ HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); } - + /* Process Unlocked */ __HAL_UNLOCK(hdac); /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); - + /* Return function status */ return HAL_OK; } @@ -779,25 +874,25 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u * @brief Disables DAC and stop conversion of channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); - + /* Disable the selected DAC channel DMA request */ hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel); - + /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, Channel); - + /* Disable the DMA channel */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ @@ -807,7 +902,7 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) { /* Disable the DMA channel */ status = HAL_DMA_Abort(hdac->DMA_Handle1); - + /* Disable the DAC DMA underrun interrupt */ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1); } @@ -815,7 +910,7 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) { /* Disable the DMA channel */ status = HAL_DMA_Abort(hdac->DMA_Handle2); - + /* Disable the DAC DMA underrun interrupt */ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2); } @@ -826,11 +921,11 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) /* Disable the DMA channel */ status = HAL_DMA_Abort(hdac->DMA_Handle1); - + /* Disable the DAC DMA underrun interrupt */ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1); -#endif /* STM32L451xx STM32L452xx STM32L462xx */ - +#endif /* STM32L451xx STM32L452xx STM32L462xx */ + /* Check if DMA Channel effectively disabled */ if (status != HAL_OK) { @@ -842,7 +937,7 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; } - + /* Return function status */ return status; } @@ -854,7 +949,7 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Handles DAC interrupt request * This function uses the interruption of DMA - * underrun. + * underrun. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None @@ -862,24 +957,28 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) { if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1)) - { + { /* Check underrun flag of DAC channel 1 */ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; - + /* Set DAC error code to chanel1 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1); - + /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1); - + /* Disable the selected DAC channel1 DMA request */ CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); - - /* Error callback */ + + /* Error callback */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->DMAUnderrunCallbackCh1(hdac); +#else HAL_DAC_DMAUnderrunCallbackCh1(hdac); +#endif } } #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ @@ -887,23 +986,27 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2)) { - /* Check underrun flag of DAC channel 1 */ + /* Check underrun flag of DAC channel 2 */ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2)) { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; - + /* Set DAC error code to channel2 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2); - + /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2); - + /* Disable the selected DAC channel1 DMA request */ CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); - - /* Error callback */ + + /* Error callback */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->DMAUnderrunCallbackCh2(hdac); +#else HAL_DACEx_DMAUnderrunCallbackCh2(hdac); +#endif } } #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ @@ -915,10 +1018,10 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) * @brief Set the specified data holding register value for DAC channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected * @param Alignment: Specifies the data alignment. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected @@ -928,15 +1031,15 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) -{ +{ __IO uint32_t tmp = 0; - + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)hdac->Instance; + + tmp = (uint32_t)hdac->Instance; if(Channel == DAC_CHANNEL_1) { tmp += DAC_DHR12R1_ALIGNMENT(Alignment); @@ -948,13 +1051,13 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui /* Set the DAC channel selected data holding register */ *(__IO uint32_t *) tmp = Data; - + /* Return function status */ return HAL_OK; } /** - * @brief Conversion complete callback in non-blocking mode for Channel1 + * @brief Conversion complete callback in non-blocking mode for Channel1 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None @@ -970,7 +1073,7 @@ __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) } /** - * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1 + * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None @@ -1020,18 +1123,18 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) /** * @} */ - + /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions + * @brief Peripheral Control functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral Control functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: - (+) Configure channels. + (+) Configure channels. (+) Set the specified data holding register value for DAC channel. - + @endverbatim * @{ */ @@ -1040,7 +1143,7 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) * @brief Returns the last data output value of the selected DAC channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -1050,11 +1153,14 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); - + /* Returns the DAC channel data output register value */ #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Channel); + return hdac->Instance->DOR1; -#endif /* STM32L451xx STM32L452xx STM32L462xx */ +#endif /* STM32L451xx STM32L452xx STM32L462xx */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ @@ -1077,7 +1183,7 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param sConfig: DAC configuration structure. - * @param Channel: The selected DAC channel. + * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (Whenever present) @@ -1089,11 +1195,11 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf uint32_t tickstart = 0; #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) uint32_t hclkfreq = 0; -#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ - - /* Check the DAC parameters */ +#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ + + /* Check the DAC parameters */ #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) - assert_param(IS_DAC_HIGH_FREQUENCY_MODE(sConfig->DAC_HighFrequency)); + assert_param(IS_DAC_HIGH_FREQUENCY_MODE(sConfig->DAC_HighFrequency)); #endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); @@ -1101,32 +1207,32 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming)); if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER) { - assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue)); + assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue)); } assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold)); if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE) { assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime)); assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)); - assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); + assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } assert_param(IS_DAC_CHANNEL(Channel)); - + /* Process locked */ __HAL_LOCK(hdac); - + /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; - + if(sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) - /* Sample on old configuration */ + /* Sample on old configuration */ { /* SampleTime */ if (Channel == DAC_CHANNEL_1) { /* Get timeout */ tickstart = HAL_GetTick(); - + /* SHSR1 can be written when BWST1 equals RESET */ while (((hdac->Instance->SR) & DAC_SR_BWST1)!= RESET) { @@ -1145,7 +1251,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf HAL_Delay(1); hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; } -#if !defined (STM32L451xx) & !defined (STM32L452xx) & !defined (STM32L462xx) +#if !defined (STM32L451xx) & !defined (STM32L452xx) & !defined (STM32L462xx) else /* Channel 2 */ { /* SHSR2 can be written when BWST2 equals RESET */ @@ -1167,14 +1273,14 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf HAL_Delay(1); hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; } -#endif /* STM32L451xx STM32L452xx STM32L462xx */ - +#endif /* STM32L451xx STM32L452xx STM32L462xx */ + /* HoldTime */ MODIFY_REG (hdac->Instance->SHHR, DAC_SHHR_THOLD1<DAC_SampleAndHoldConfig.DAC_HoldTime)<Instance->SHRR, DAC_SHRR_TREFRESH1<DAC_SampleAndHoldConfig.DAC_RefreshTime)<DAC_UserTrimming == DAC_TRIMMING_USER) /* USER TRIMMING */ { @@ -1191,25 +1297,25 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf } /* else factory trimming is used (factory setting are available at reset)*/ /* SW Nothing has nothing to do */ - + /* Get the DAC MCR value */ tmpreg1 = hdac->Instance->MCR; /* Clear DAC_MCR_MODE2_0, DAC_MCR_MODE2_1 and DAC_MCR_MODE2_2 bits */ - tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << Channel); + tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << Channel); /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | sConfig->DAC_ConnectOnChipPeripheral); /* Calculate MCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << Channel; /* Write to DAC MCR */ hdac->Instance->MCR = tmpreg1; - + /* DAC in normal operating mode hence clear DAC_CR_CENx bit */ CLEAR_BIT (hdac->Instance->CR, DAC_CR_CEN1 << Channel); - + /* Get the DAC CR value */ tmpreg1 = hdac->Instance->CR; /* Clear TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << Channel); + tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << Channel); /* Configure for the selected DAC channel: trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ tmpreg2 = (sConfig->DAC_Trigger); @@ -1220,7 +1326,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf { tmpreg1 |= DAC_CR_HFSEL; } - else + else { if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE == sConfig->DAC_HighFrequency) { @@ -1229,8 +1335,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf else /* Automatic selection */ { hclkfreq = HAL_RCC_GetHCLKFreq(); - if (hclkfreq > HFSEL_ENABLE_THRESHOLD_80MHZ) - { + if (hclkfreq > HFSEL_ENABLE_THRESHOLD_80MHZ) + { /* High frequency enable when HCLK frequency higher than 80 */ tmpreg1 |= DAC_CR_HFSEL; } @@ -1241,41 +1347,263 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf } } } - -#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ + +#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; - + /* Disable wave generation */ hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel); - + /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hdac); - + /* Return function status */ return HAL_OK; } +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User DAC Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hdac DAC handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID + * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID + * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID + * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID + * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID + * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID + * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID + * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID + * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID + * @arg @ref HAL_DAC_MSP_INIT_CB_ID DAC MSP Init Callback ID + * @arg @ref HAL_DAC_MSP_DEINIT_CB_ID DAC MSP DeInit Callback ID + * + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdac); + + if(hdac->State == HAL_DAC_STATE_READY) + { + switch (CallbackID) + { + case HAL_DAC_CH1_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh1 = pCallback; + break; + case HAL_DAC_CH1_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh1 = pCallback; + break; + case HAL_DAC_CH1_ERROR_ID : + hdac->ErrorCallbackCh1 = pCallback; + break; + case HAL_DAC_CH1_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh1 = pCallback; + break; + case HAL_DAC_CH2_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh2 = pCallback; + break; + case HAL_DAC_CH2_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh2 = pCallback; + break; + case HAL_DAC_CH2_ERROR_ID : + hdac->ErrorCallbackCh2 = pCallback; + break; + case HAL_DAC_CH2_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh2 = pCallback; + break; + case HAL_DAC_MSP_INIT_CB_ID : + hdac->MspInitCallback = pCallback; + break; + case HAL_DAC_MSP_DEINIT_CB_ID : + hdac->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hdac->State == HAL_DAC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DAC_MSP_INIT_CB_ID : + hdac->MspInitCallback = pCallback; + break; + case HAL_DAC_MSP_DEINIT_CB_ID : + hdac->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdac); + return status; +} + +/** + * @brief Unregister a User DAC Callback + * DAC Callback is redirected to the weak (surcharged) predefined callback + * @param hdac DAC handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 tranfer Complete Callback ID + * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID + * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID + * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID + * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID + * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID + * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID + * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID + * @arg @ref HAL_DAC_MSP_INIT_CB_ID DAC MSP Init Callback ID + * @arg @ref HAL_DAC_MSP_DEINIT_CB_ID DAC MSP DeInit Callback ID + * @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks + * @retval status + */ +HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdac); + + if(hdac->State == HAL_DAC_STATE_READY) + { + switch (CallbackID) + { + case HAL_DAC_CH1_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; + break; + case HAL_DAC_CH1_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; + break; + case HAL_DAC_CH1_ERROR_ID : + hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; + break; + case HAL_DAC_CH1_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; + break; + case HAL_DAC_CH2_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; + break; + case HAL_DAC_CH2_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; + break; + case HAL_DAC_CH2_ERROR_ID : + hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; + break; + case HAL_DAC_CH2_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; + break; + case HAL_DAC_MSP_INIT_CB_ID : + hdac->MspInitCallback = HAL_DAC_MspInit; + break; + case HAL_DAC_MSP_DEINIT_CB_ID : + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + break; + case HAL_DAC_ALL_CB_ID : + hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; + hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; + hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; + hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; + hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; + hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; + hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; + hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; + hdac->MspInitCallback = HAL_DAC_MspInit; + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hdac->State == HAL_DAC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DAC_MSP_INIT_CB_ID : + hdac->MspInitCallback = HAL_DAC_MspInit; + break; + case HAL_DAC_MSP_DEINIT_CB_ID : + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdac); + return status; +} +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + /** * @} */ /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions + * @brief Peripheral State and Errors functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral State and Errors functions ##### - ============================================================================== + ============================================================================== [..] This subsection provides functions allowing to (+) Check the DAC state. (+) Check the DAC Errors. - + @endverbatim * @{ */ @@ -1317,48 +1645,61 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) */ /** - * @brief DMA conversion complete callback. + * @brief DMA conversion complete callback. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) +static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) { DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - HAL_DAC_ConvCpltCallbackCh1(hdac); - + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ConvCpltCallbackCh1(hdac); +#else + HAL_DAC_ConvCpltCallbackCh1(hdac); +#endif + hdac->State= HAL_DAC_STATE_READY; } /** - * @brief DMA half transfer complete callback. + * @brief DMA half transfer complete callback. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) +static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) { - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Conversion complete callback */ - HAL_DAC_ConvHalfCpltCallbackCh1(hdac); + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Conversion complete callback */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ConvHalfCpltCallbackCh1(hdac); +#else + HAL_DAC_ConvHalfCpltCallbackCh1(hdac); +#endif } /** - * @brief DMA error callback + * @brief DMA error callback * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) +static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) { DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + /* Set DAC error code to DMA error */ hdac->ErrorCode |= HAL_DAC_ERROR_DMA; - - HAL_DAC_ErrorCallbackCh1(hdac); - + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ErrorCallbackCh1(hdac); +#else + HAL_DAC_ErrorCallbackCh1(hdac); +#endif + hdac->State= HAL_DAC_STATE_READY; } @@ -1368,6 +1709,7 @@ static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) #endif /* HAL_DAC_MODULE_ENABLED */ + /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c index ab95630e43..79c8e2a405 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c @@ -3,28 +3,28 @@ * @file stm32l4xx_hal_dac_ex.c * @author MCD Application Team * @brief DAC HAL module driver. - * This file provides firmware functions to manage the extended - * functionalities of the DAC peripheral. - * + * This file provides firmware functions to manage the extended + * functionalities of the DAC peripheral. * - @verbatim + * + @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== - [..] + [..] (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) : Use HAL_DACEx_DualGetValue() to get digital data to be converted and use - HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2. + HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2. (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal. (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal. (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel. (+) HAL_DACEx_SetUserTrimming to set user trimming value. - (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting - after reset, user setting if HAL_DACEx_SetUserTrimming have been used + (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting + after reset, user setting if HAL_DACEx_SetUserTrimming have been used at least one time after reset). - @endverbatim + @endverbatim ****************************************************************************** * @attention * @@ -53,7 +53,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ @@ -66,7 +66,7 @@ /** @defgroup DACEx DACEx * @brief DAC Extended HAL module driver * @{ - */ + */ #ifdef HAL_DAC_MODULE_ENABLED @@ -76,18 +76,18 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ - + /** @defgroup DACEx_Exported_Functions DACEx Exported Functions * @{ */ /** @defgroup DACEx_Exported_Functions_Group2 IO operation functions - * @brief Extended IO operation functions + * @brief Extended IO operation functions * -@verbatim +@verbatim ============================================================================== ##### Extended features functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: (+) Start conversion. (+) Stop conversion. @@ -95,7 +95,7 @@ (+) Stop conversion and disable DMA transfer. (+) Get result of conversion. (+) Get result of dual mode conversion. - + @endverbatim * @{ */ @@ -104,10 +104,10 @@ * @brief Enable or disable the selected DAC channel wave generation. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * DAC_CHANNEL_1 / DAC_CHANNEL_2 - * @param Amplitude: Select max triangle amplitude. + * @param Amplitude: Select max triangle amplitude. * This parameter can be one of the following values: * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 @@ -120,30 +120,30 @@ * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511 * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023 * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047 - * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095 + * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095 * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude) -{ +{ /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); - + /* Process locked */ __HAL_LOCK(hdac); - + /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; - + /* Enable the triangle wave generation for the selected DAC channel */ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<State = HAL_DAC_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hdac); - + /* Return function status */ return HAL_OK; } @@ -151,47 +151,47 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32 /** * @brief Enable or disable the selected DAC channel wave generation. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * DAC_CHANNEL_1 / DAC_CHANNEL_2 - * @param Amplitude: Unmask DAC channel LFSR for noise wave generation. - * This parameter can be one of the following values: + * @param Amplitude: Unmask DAC channel LFSR for noise wave generation. + * This parameter can be one of the following values: * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation - * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude) -{ +{ /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); - + /* Process locked */ __HAL_LOCK(hdac); - + /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; - + /* Enable the noise wave generation for the selected DAC channel */ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<State = HAL_DAC_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hdac); - + /* Return function status */ return HAL_OK; } @@ -216,30 +216,30 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2) -{ +{ uint32_t data = 0, tmp = 0; - + /* Check the parameters */ assert_param(IS_DAC_ALIGN(Alignment)); assert_param(IS_DAC_DATA(Data1)); assert_param(IS_DAC_DATA(Data2)); - + /* Calculate and set dual DAC data holding register value */ if (Alignment == DAC_ALIGN_8B_R) { - data = ((uint32_t)Data2 << 8) | Data1; + data = ((uint32_t)Data2 << 8) | Data1; } else { data = ((uint32_t)Data2 << 16) | Data1; } - + tmp = (uint32_t)hdac->Instance; tmp += DAC_DHR12RD_ALIGNMENT(Alignment); /* Set the dual DAC selected data holding register */ *(__IO uint32_t *)tmp = data; - + /* Return function status */ return HAL_OK; } @@ -261,7 +261,7 @@ __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac) } /** - * @brief Conversion half DMA transfer callback in non-blocking mode for Channel2. + * @brief Conversion half DMA transfer callback in non-blocking mode for Channel2. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None @@ -316,7 +316,7 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param sConfig: DAC channel configuration structure. - * @param Channel: The selected DAC channel. + * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -326,19 +326,19 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) -{ +{ HAL_StatusTypeDef status = HAL_OK; - + __IO uint32_t tmp = 0; uint32_t trimmingvalue = 0; uint32_t delta; - + /* store/restore channel configuration structure purpose */ uint32_t oldmodeconfiguration = 0; - + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); - + /* Check the DAC handle allocation */ /* Check if DAC running */ if((hdac == NULL) || (hdac->State == HAL_DAC_STATE_BUSY)) @@ -349,19 +349,19 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelC { /* Process locked */ __HAL_LOCK(hdac); - + /* Store configuration */ oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << Channel)); - + /* Disable the selected DAC channel */ CLEAR_BIT ((hdac->Instance->CR), (DAC_CR_EN1 << Channel)); - + /* Set mode in MCR for calibration */ MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), 0); - + /* Set DAC Channel1 DHR register to the middle value */ - tmp = (uint32_t)hdac->Instance; - + tmp = (uint32_t)hdac->Instance; + #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) @@ -376,30 +376,30 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelC #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R); #endif /* STM32L451xx STM32L452xx STM32L462xx */ *(__IO uint32_t *) tmp = 0x0800; - + /* Enable the selected DAC channel calibration */ /* i.e. set DAC_CR_CENx bit */ SET_BIT ((hdac->Instance->CR), (DAC_CR_CEN1 << Channel)); - - /* Init trimming counter */ + + /* Init trimming counter */ /* Medium value */ - trimmingvalue = 16; + trimmingvalue = 16; delta = 8; - while (delta != 0) + while (delta != 0) { /* Set candidate trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<Instance->SR & (DAC_SR_CAL_FLAG1<>= 1; } - + /* Still need to check if right calibration is current value or one step below */ /* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1 */ /* Set candidate trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<Instance->SR & (DAC_SR_CAL_FLAG1<Instance->CCR, (DAC_CCR_OTRIM1<Instance->CR), (DAC_CR_CEN1 << Channel)); - + sConfig->DAC_TrimmingValue = trimmingvalue; sConfig->DAC_UserTrimming = DAC_TRIMMING_USER; - + /* Restore configuration */ MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), oldmodeconfiguration); - + /* Process unlocked */ __HAL_UNLOCK(hdac); } - + return status; } @@ -450,7 +450,7 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelC * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param sConfig: DAC configuration structure updated with new DAC trimming value. - * @param Channel: The selected DAC channel. + * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -459,13 +459,13 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelC */ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue) -{ +{ HAL_StatusTypeDef status = HAL_OK; - + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue)); - + /* Check the DAC handle allocation */ if(hdac == NULL) { @@ -475,14 +475,14 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_Channe { /* Process locked */ __HAL_LOCK(hdac); - + /* Set new trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<DAC_UserTrimming = DAC_TRIMMING_USER; sConfig->DAC_TrimmingValue = NewTrimmingValue; - + /* Process unlocked */ __HAL_UNLOCK(hdac); } @@ -492,18 +492,18 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_Channe /** * @brief Return the DAC trimming value. * @param hdac : DAC handle - * @param Channel: The selected DAC channel. + * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval Trimming value : range: 0->31 - * + * */ uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel) { uint32_t trimmingvalue = 0; - + /* Check the DAC handle allocation */ /* And not in Reset state */ if((hdac == NULL) || (hdac->State == HAL_DAC_STATE_RESET)) @@ -517,7 +517,7 @@ uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel) /* Retrieve trimming */ trimmingvalue = ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << Channel)) >> Channel); - } + } return trimmingvalue; } @@ -527,19 +527,19 @@ uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel) #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) /** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions - * @brief Extended Peripheral Control functions + * @brief Extended Peripheral Control functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral Control functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: - (+) Configure channels. + (+) Configure channels. (+) Set the specified data holding register value for DAC channel. - + @endverbatim * @{ */ @@ -553,11 +553,11 @@ uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel) uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) { uint32_t tmp = 0; - + tmp |= hdac->Instance->DOR1; tmp |= hdac->Instance->DOR2 << 16; - + /* Returns the DAC channel data output register value */ return tmp; } @@ -566,7 +566,7 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) * @} */ -#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ +#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ @@ -576,7 +576,7 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) /* Private functions ---------------------------------------------------------*/ /** @defgroup DACEx_Private_Functions DACEx private functions @@ -585,31 +585,40 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) */ /** - * @brief DMA conversion complete callback. + * @brief DMA conversion complete callback. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) +void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) { DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - HAL_DACEx_ConvCpltCallbackCh2(hdac); - + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ConvCpltCallbackCh2(hdac); +#else + HAL_DACEx_ConvCpltCallbackCh2(hdac); +#endif + hdac->State= HAL_DAC_STATE_READY; } /** - * @brief DMA half transfer complete callback. + * @brief DMA half transfer complete callback. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) +void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) { - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Conversion complete callback */ - HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Conversion complete callback */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ConvHalfCpltCallbackCh2(hdac); +#else + HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); +#endif } /** @@ -618,15 +627,18 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) * the configuration information for the specified DMA module. * @retval None */ -void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) +void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) { DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + /* Set DAC error code to DMA error */ hdac->ErrorCode |= HAL_DAC_ERROR_DMA; - - HAL_DACEx_ErrorCallbackCh2(hdac); - + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ErrorCallbackCh2(hdac); +#else + HAL_DACEx_ErrorCallbackCh2(hdac); +#endif hdac->State= HAL_DAC_STATE_READY; } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dcmi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dcmi.c index 3a20f84485..c4c1734b24 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dcmi.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dcmi.c @@ -3,97 +3,146 @@ * @file stm32l4xx_hal_dcmi.c * @author MCD Application Team * @brief DCMI HAL module driver - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Digital Camera Interface (DCMI) peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Error functions - * - @verbatim + * + Peripheral Control functions + * + Peripheral State and Error functions + * + @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] - The sequence below describes how to use this driver to capture an image + The sequence below describes how to use this driver to capture images from a camera module connected to the DCMI Interface. This sequence does not take into account the configuration of the camera module, which should be made before configuring and enabling - the DCMI. + the DCMI to capture images. (#) Program the required configuration through the following parameters: horizontal and vertical polarity, pixel clock polarity, capture rate, synchronization mode, frame delimiter codes, data width, byte and line selection using HAL_DCMI_Init() function. - + (#) Optionally select JPEG mode; in that case, only the polarity - and the capture mode parameters need to be set. - + and the capture mode parameters need to be set. + (#) Capture mode can be either snapshot or continuous mode. - + (#) Configure the DMA_Handle to transfer data from DCMI DR register to the destination memory buffer. - + -@- In snapshot mode, the interface transfers a single frame through DMA. In continuous mode, the DMA must be set in circular mode to ensure a continuous - flow of images data samples. + flow of images data samples. (#) Program the transfer configuration through the following parameters: - DCMI mode, destination memory buffer address and data length then + DCMI mode, destination memory buffer address and data length then enable capture using HAL_DCMI_Start_DMA() function. - + (#) Whether in continuous or snapshot mode, data length parameter must be equal to the frame size. - - (#) When the frame size is unknown beforehand (e.g. JPEG case), data length must - be large enough to ensure the capture of a frame. - - (#) If the frame size is larger than the maximum DMA transfer length (i.e. 65535), + + (#) When the frame size is unknown beforehand (e.g. JPEG case), data length must + be large enough to ensure the capture of a frame. + + (#) If the frame size is larger than the maximum DMA transfer length (i.e. 65535), (++) the DMA must be configured in circular mode, either for snapshot or continuous - capture mode, + capture mode, (++) during capture, the driver copies the image data samples from DCMI DR register - at the end of the final destination buffer used as a work buffer, - (++) at each DMA half (respectively complete) transfer interrupt, the first - (resp. second) half of the work buffer is copied to the final destination thru + at the end of the final destination buffer used as a work buffer, + (++) at each DMA half (respectively complete) transfer interrupt, the first + (resp. second) half of the work buffer is copied to the final destination thru a second DMA channel. - (++) Parameters of this second DMA channel are contained in the memory to memory DMA - handle "DMAM2M_Handle", itself field of the DCMI handle structure. - (++) This memory to memory transfer has length half that of the work buffer and is - carried out in normal mode (not in circular mode). + (++) Parameters of this second DMA channel are contained in the memory to memory DMA + handle "DMAM2M_Handle", itself field of the DCMI handle structure. + (++) This memory to memory transfer has length half that of the work buffer and is + carried out in normal mode (not in circular mode). - (#) Optionally, configure and enable the CROP feature to select a - rectangular window from the received image using HAL_DCMI_ConfigCrop() + (#) Optionally, configure and enable the CROP feature to select a + rectangular window from the received image using HAL_DCMI_ConfigCrop() and HAL_DCMI_EnableCrop() functions. Use HAL_DCMI_DisableCrop() to disable this feature. (#) The capture can be stopped with HAL_DCMI_Stop() function. (#) To control the DCMI state, use the function HAL_DCMI_GetState(). - - (#) To read the DCMI error code, use the function HAL_DCMI_GetError(). - + + (#) To read the DCMI error code, use the function HAL_DCMI_GetError(). + [..] (@) When the frame size is less than the maximum DMA transfer length (i.e. 65535) and when in snapshot mode, user must make sure the FRAME interrupt is disabled. This allows to avoid corner cases where the FRAME interrupt might be triggered before the DMA transfer completion interrupt. In this specific configuration, - the driver checks the FRAME capture flag after the DMA transfer end and calls - HAL_DCMI_FrameEventCallback() if the flag is set. + the driver checks the FRAME capture flag after the DMA transfer end and calls + HAL_DCMI_FrameEventCallback() if the flag is set. *** DCMI HAL driver macros list *** - ============================================= + ============================================= [..] Below the list of most used macros in DCMI HAL driver. - + (+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral. (+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral. (+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags. (+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags. (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts. (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts. - (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred - and that the interruption is enabled at the same time. - + (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not. + + *** Callback registration *** + ============================= + + The compilation define USE_HAL_DCMI_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use functions @ref HAL_DCMI_RegisterCallback() to register a user callback. + + Function @ref HAL_DCMI_RegisterCallback() allows to register following callbacks: + (+) FrameEventCallback : DCMI Frame Event. + (+) VsyncEventCallback : DCMI Vsync Event. + (+) LineEventCallback : DCMI Line Event. + (+) ErrorCallback : DCMI error. + (+) MspInitCallback : DCMI MspInit. + (+) MspDeInitCallback : DCMI MspDeInit. + This function takes as parameters the HAL peripheral handle, the callback ID + and a pointer to the user callback function. + + Use function @ref HAL_DCMI_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_DCMI_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the callback ID. + This function allows to reset following callbacks: + (+) FrameEventCallback : DCMI Frame Event. + (+) VsyncEventCallback : DCMI Vsync Event. + (+) LineEventCallback : DCMI Line Event. + (+) ErrorCallback : DCMI error. + (+) MspInitCallback : DCMI MspInit. + (+) MspDeInitCallback : DCMI MspDeInit. + + By default, after the @ref HAL_DCMI_Init and if the state is HAL_DCMI_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions: + examples @ref FrameEventCallback(), @ref HAL_DCMI_ErrorCallback(). + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_DCMI_Init + and @ref HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_DCMI_Init and @ref HAL_DCMI_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_DCMI_RegisterCallback before calling @ref HAL_DCMI_DeInit + or @ref HAL_DCMI_Init function. + + When the compilation define USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + @endverbatim ****************************************************************************** * @attention @@ -123,15 +172,13 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" #ifdef HAL_DCMI_MODULE_ENABLED - -#if defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined (DCMI) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -149,39 +196,22 @@ /** @defgroup DCMI_Stop_TimeOut DCMI Stop TimeOut * @{ - */ -#define DCMI_TIMEOUT_STOP ((uint32_t)1000) /*!< 1s */ -/** - * @} */ - -/** @defgroup DCMI_Shifts DCMI Shifts - * @{ - */ -#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)POSITION_VAL(DCMI_CWSIZE_VLINE) /*!< Required left shift to set crop window vertical line count */ -#define DCMI_POSITION_CWSTRT_VST (uint32_t)POSITION_VAL(DCMI_CWSTRT_VST) /*!< Required left shift to set crop window vertical start line count */ - -#define DCMI_POSITION_ESCR_LSC (uint32_t)POSITION_VAL(DCMI_ESCR_LSC) /*!< Required left shift to set line start delimiter */ -#define DCMI_POSITION_ESCR_LEC (uint32_t)POSITION_VAL(DCMI_ESCR_LEC) /*!< Required left shift to set line end delimiter */ -#define DCMI_POSITION_ESCR_FEC (uint32_t)POSITION_VAL(DCMI_ESCR_FEC) /*!< Required left shift to set frame end delimiter */ - -#define DCMI_POSITION_ESUR_LSU (uint32_t)POSITION_VAL(DCMI_ESUR_LSU) /*!< Required left shift to set line start delimiter unmask */ -#define DCMI_POSITION_ESUR_LEU (uint32_t)POSITION_VAL(DCMI_ESUR_LEU) /*!< Required left shift to set line end delimiter unmask */ -#define DCMI_POSITION_ESUR_FEU (uint32_t)POSITION_VAL(DCMI_ESUR_FEU) /*!< Required left shift to set frame end delimiter unmask */ +#define DCMI_TIMEOUT_STOP ((uint32_t)1000U) /*!< 1s */ /** * @} */ - -#define NPRIME 16 + +#define NPRIME 16 /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -uint32_t PrimeArray[NPRIME] = { 1, 2, 3, 5, - 7, 11, 13, 17, - 19, 23, 29, 31, +uint32_t PrimeArray[NPRIME] = { 1, 2, 3, 5, + 7, 11, 13, 17, + 19, 23, 29, 31, 37, 41, 43, 47}; /* Private function prototypes -----------------------------------------------*/ /** @addtogroup DCMI_Private_Functions DCMI Private Functions @@ -203,38 +233,38 @@ static uint32_t DCMI_TransferSize(uint32_t InputSize); /** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and Configuration functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the DCMI - (+) De-initialize the DCMI + (+) De-initialize the DCMI @endverbatim * @{ */ - + /** * @brief Initialize the DCMI according to the specified * parameters in the DCMI_InitTypeDef and create the associated handle. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @note By default, all interruptions are enabled (line end, frame end, overrun, - * VSYNC and embedded synchronization error interrupts). + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @note By default, all interruptions are enabled (line end, frame end, overrun, + * VSYNC and embedded synchronization error interrupts). * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) -{ +{ /* Check the DCMI peripheral state */ if(hdcmi == NULL) { return HAL_ERROR; } - + /* Check function parameters */ assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance)); - assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode)); + assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode)); assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity)); assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity)); assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity)); @@ -246,27 +276,44 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart)); assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode)); assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart)); - + if(hdcmi->State == HAL_DCMI_STATE_RESET) { /* Allocate lock resource and initialize it */ hdcmi->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ + + /* Init the DCMI Callback settings */ +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) + hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */ + hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */ + hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */ + hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */ + + if(hdcmi->MspInitCallback == NULL) + { + /* Legacy weak MspInit Callback */ + hdcmi->MspInitCallback = HAL_DCMI_MspInit; + } + /* Initialize the low level hardware (MSP) */ + hdcmi->MspInitCallback(hdcmi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_DCMI_MspInit(hdcmi); - } - +#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */ + } + /* Change the DCMI state */ - hdcmi->State = HAL_DCMI_STATE_BUSY; - + hdcmi->State = HAL_DCMI_STATE_BUSY; + /* Disable DCMI IP before setting the configuration register */ - __HAL_DCMI_DISABLE(hdcmi); - + __HAL_DCMI_DISABLE(hdcmi); + if (hdcmi->Init.ExtendedDataMode != DCMI_EXTEND_DATA_8B) { - /* Byte select mode must be programmed to the reset value if the extended mode + /* Byte select mode must be programmed to the reset value if the extended mode is not set to 8-bit data capture on every pixel clock */ - hdcmi->Init.ByteSelectMode = DCMI_BSM_ALL; - } + hdcmi->Init.ByteSelectMode = DCMI_BSM_ALL; + } /* Set DCMI parameters */ hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |\ @@ -284,14 +331,14 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED) { hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SynchroCode.FrameStartCode) |\ - ((uint32_t)hdcmi->Init.SynchroCode.LineStartCode << DCMI_POSITION_ESCR_LSC)|\ - ((uint32_t)hdcmi->Init.SynchroCode.LineEndCode << DCMI_POSITION_ESCR_LEC) |\ - ((uint32_t)hdcmi->Init.SynchroCode.FrameEndCode << DCMI_POSITION_ESCR_FEC)); + ((uint32_t)hdcmi->Init.SynchroCode.LineStartCode << DCMI_ESCR_LSC_Pos)|\ + ((uint32_t)hdcmi->Init.SynchroCode.LineEndCode << DCMI_ESCR_LEC_Pos) |\ + ((uint32_t)hdcmi->Init.SynchroCode.FrameEndCode << DCMI_ESCR_FEC_Pos)); } /* By default, enable all interrupts. The user may disable the unwanted ones - in resorting to __HAL_DCMI_DISABLE_IT() macro before invoking HAL_DCMI_Start_DMA(). - Enabled interruptions are + in resorting to __HAL_DCMI_DISABLE_IT() macro before invoking HAL_DCMI_Start_DMA(). + Enabled interruptions are - end of line - end of frame - data reception overrun @@ -301,7 +348,7 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) /* Update error code */ hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE; - + /* Initialize the DCMI state*/ hdcmi->State = HAL_DCMI_STATE_READY; @@ -309,10 +356,10 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) } /** - * @brief De-initialize the DCMI peripheral, reset control registers to + * @brief De-initialize the DCMI peripheral, reset control registers to * their default values. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi) @@ -323,16 +370,25 @@ HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi) { if (HAL_DCMI_Stop(hdcmi) != HAL_OK) { - /* Issue when stopping DCMI IP */ + /* Issue when stopping DCMI IP */ return HAL_ERROR; } } - - /* DeInit the DCMI low level hardware */ - HAL_DCMI_MspDeInit(hdcmi); - + /* Reset DCMI control register */ - hdcmi->Instance->CR = 0; + hdcmi->Instance->CR = 0; + +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) + if(hdcmi->MspDeInitCallback == NULL) + { + hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit; + } + /* De-Initialize the low level hardware (MSP) */ + hdcmi->MspDeInitCallback(hdcmi); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_DCMI_MspDeInit(hdcmi); +#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */ /* Update error code */ hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE; @@ -348,31 +404,31 @@ HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi) /** * @brief Initialize the DCMI MSP. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. * @retval None */ __weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdcmi); - + /* NOTE : This function should not be modified; when the callback is needed, the HAL_DCMI_MspInit() callback can be implemented in the user file - */ + */ } /** * @brief De-initialize the DCMI MSP. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. * @retval None */ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdcmi); - + /* NOTE : This function should not be modified; when the callback is needed, the HAL_DCMI_MspDeInit() callback can be implemented in the user file */ @@ -382,65 +438,65 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi) * @} */ -/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions +/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: - (+) Configure destination address and data length, + (+) Configure destination address and data length, enable DCMI DMA request and DCMI capture. (+) Stop DCMI capture. (+) Handle DCMI interrupt request. - + [..] A set of callbacks is provided: (+) HAL_DCMI_ErrorCallback() (+) HAL_DCMI_LineEventCallback() (+) HAL_DCMI_VsyncEventCallback() (+) HAL_DCMI_FrameEventCallback() - + @endverbatim * @{ */ /** - * @brief Enable DCMI capture in DMA mode. - * @param hdcmi: Pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @param DCMI_Mode: DCMI capture mode snapshot or continuous grab. - * @param pData: The destination memory buffer address. - * @param Length: The length of capture to be transferred (in 32-bit words). + * @brief Enable DCMI capture in DMA mode. + * @param hdcmi Pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @param DCMI_Mode DCMI capture mode snapshot or continuous grab. + * @param pData The destination memory buffer address. + * @param Length The length of capture to be transferred (in 32-bit words). * @note In case of length larger than 65535 (0xFFFF is the DMA maximum transfer length), * the API uses the end of the destination buffer as a work area: HAL_DCMI_Start_DMA() * initiates a circular DMA transfer from DCMI DR to the ad-hoc work buffer and each * half and complete transfer interrupt triggers a copy from the work buffer to - * the final destination pData thru a second DMA channel. - * @note Following HAL_DCMI_Init() call, all interruptions are enabled (line end, + * the final destination pData thru a second DMA channel. + * @note Following HAL_DCMI_Init() call, all interruptions are enabled (line end, * frame end, overrun, VSYNC and embedded synchronization error interrupts). * User can disable unwanted interrupts thru __HAL_DCMI_DISABLE_IT() macro - * before invoking HAL_DCMI_Start_DMA(). - * @note For length less than 0xFFFF (DMA maximum transfer length) and in snapshot mode, + * before invoking HAL_DCMI_Start_DMA(). + * @note For length less than 0xFFFF (DMA maximum transfer length) and in snapshot mode, * frame interrupt is disabled before DMA transfer. FRAME capture flag is checked - * in DCMI_DMAXferCplt callback at the end of the DMA transfer. If flag is set, - * HAL_DCMI_FrameEventCallback() API is called. + * in DCMI_DMAXferCplt callback at the end of the DMA transfer. If flag is set, + * HAL_DCMI_FrameEventCallback() API is called. * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length) { - uint32_t circular_copy_length = 0; - + uint32_t circular_copy_length = 0; + /* Check capture parameter */ assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode)); /* Process Locked */ __HAL_LOCK(hdcmi); - + /* Lock the DCMI peripheral state */ hdcmi->State = HAL_DCMI_STATE_BUSY; - + /* Configure the DCMI Mode and enable the DCMI IP at the same time */ MODIFY_REG(hdcmi->Instance->CR, (DCMI_CR_CM|DCMI_CR_ENABLE), (DCMI_Mode|DCMI_CR_ENABLE)); @@ -450,7 +506,10 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo /* Set the DMA error callback */ hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError; - if(Length <= 0xFFFF) + /* Set the dma abort callback */ + hdcmi->DMA_Handle->XferAbortCallback = NULL; + + if(Length <= 0xFFFF) { hdcmi->XferCount = 0; /* Mark as direct transfer from DCMI_DR register to final destination buffer */ @@ -459,74 +518,74 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo { /* Update error code */ hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA; - + /* Set state back to Ready */ hdcmi->State = HAL_DCMI_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hdcmi); - + return HAL_ERROR; - } + } } else /* Capture length is longer than DMA maximum transfer size */ - { + { /* Set DMA in circular mode */ hdcmi->DMA_Handle->Init.Mode = DMA_CIRCULAR; - + /* Set the DMA half transfer complete callback */ hdcmi->DMA_Handle->XferHalfCpltCallback = DCMI_DMAHalfXferCplt; - + /* Initialize transfer parameters */ hdcmi->XferSize = Length; /* Store the complete transfer length in DCMI handle */ hdcmi->pBuffPtr = pData; /* Final destination buffer pointer */ - + circular_copy_length = DCMI_TransferSize(Length); /* Check if issue in intermediate length computation */ - if (circular_copy_length == 0) + if (circular_copy_length == 0) { /* Set state back to Ready */ hdcmi->State = HAL_DCMI_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hdcmi); - - return HAL_ERROR; - } - + + return HAL_ERROR; + } + /* Store the number of half - intermediate buffer copies needed */ - hdcmi->XferCount = 2 * ((Length / circular_copy_length) - 1); + hdcmi->XferCount = 2 * ((Length / circular_copy_length) - 1); /* Store the half-buffer copy length */ - hdcmi->HalfCopyLength = circular_copy_length / 2; - - /* DCMI DR samples in circular mode will be copied - at the end of the final buffer. + hdcmi->HalfCopyLength = circular_copy_length / 2; + + /* DCMI DR samples in circular mode will be copied + at the end of the final buffer. Now compute the circular buffer start address. */ - /* Start by pointing at the final buffer */ + /* Start by pointing at the final buffer */ hdcmi->pCircularBuffer = pData; /* Update pCircularBuffer in "moving" at the end of the final - buffer, don't forger to convert in bytes to compute exact address */ - hdcmi->pCircularBuffer += 4 * (((Length / circular_copy_length) - 1) * circular_copy_length); - - /* Initiate the circular DMA transfer from DCMI IP to final buffer end */ + buffer, don't forger to convert in bytes to compute exact address */ + hdcmi->pCircularBuffer += 4 * (((Length / circular_copy_length) - 1) * circular_copy_length); + + /* Initiate the circular DMA transfer from DCMI IP to final buffer end */ if ( HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)hdcmi->pCircularBuffer, circular_copy_length) != HAL_OK) - { + { /* Update error code */ hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA; - + /* Set state back to Ready */ hdcmi->State = HAL_DCMI_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hdcmi); - + return HAL_ERROR; - } + } } /* Enable Capture */ - SET_BIT(hdcmi->Instance->CR, DCMI_CR_CAPTURE); + SET_BIT(hdcmi->Instance->CR, DCMI_CR_CAPTURE); /* Release Lock */ __HAL_UNLOCK(hdcmi); @@ -536,14 +595,15 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo } /** - * @brief Disable DCMI capture in DMA mode. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval HAL status + * @brief Disable DCMI capture in DMA mode. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) { uint32_t tickstart = 0; + HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hdcmi); @@ -552,7 +612,7 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) hdcmi->State = HAL_DCMI_STATE_BUSY; /* Disable Capture */ - CLEAR_BIT(hdcmi->Instance->CR, DCMI_CR_CAPTURE); + CLEAR_BIT(hdcmi->Instance->CR, DCMI_CR_CAPTURE); /* Get tick */ tickstart = HAL_GetTick(); @@ -561,23 +621,18 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0) { if((HAL_GetTick() - tickstart ) > DCMI_TIMEOUT_STOP) - { + { /* Update error code */ hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT; - - /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - - return HAL_TIMEOUT; + + status = HAL_TIMEOUT; + break; } } - + /* Disable the DMA */ HAL_DMA_Abort(hdcmi->DMA_Handle); - + /* Disable DCMI IP */ __HAL_DCMI_DISABLE(hdcmi); @@ -588,14 +643,14 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) __HAL_UNLOCK(hdcmi); /* Return function status */ - return HAL_OK; + return status; } /** - * @brief Suspend DCMI capture. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval HAL status + * @brief Suspend DCMI capture. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi) { @@ -610,7 +665,7 @@ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi) hdcmi->State = HAL_DCMI_STATE_SUSPENDED; /* Disable Capture */ - CLEAR_BIT(hdcmi->Instance->CR, DCMI_CR_CAPTURE); + CLEAR_BIT(hdcmi->Instance->CR, DCMI_CR_CAPTURE); /* Get tick */ tickstart = HAL_GetTick(); @@ -619,16 +674,16 @@ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi) while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0) { if((HAL_GetTick() - tickstart ) > DCMI_TIMEOUT_STOP) - { + { /* Update error code */ hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT; - + /* Change DCMI state */ hdcmi->State = HAL_DCMI_STATE_READY; - + /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - + __HAL_UNLOCK(hdcmi); + return HAL_TIMEOUT; } } @@ -636,16 +691,16 @@ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi) /* Process Unlocked */ __HAL_UNLOCK(hdcmi); - + /* Return function status */ return HAL_OK; } /** - * @brief Resume DCMI capture. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval HAL status + * @brief Resume DCMI capture. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi) { @@ -657,7 +712,7 @@ HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi) /* Change DCMI state */ hdcmi->State = HAL_DCMI_STATE_BUSY; - /* Enable Capture */ + /* Enable Capture */ SET_BIT(hdcmi->Instance->CR, DCMI_CR_CAPTURE); } @@ -669,16 +724,16 @@ HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi) /** * @brief Handle DCMI interrupt request. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for the DCMI. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for the DCMI. * @retval None */ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi) -{ +{ uint32_t misflags = READ_REG(hdcmi->Instance->MISR); - + /* Synchronization error interrupt management *******************************/ - if ((misflags & DCMI_MIS_ERR_MIS) != RESET) + if ((misflags & DCMI_MIS_ERR_MIS) != RESET) { /* Clear the Synchronization error flag */ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI); @@ -686,82 +741,94 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi) /* Update error code */ hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC; } - + /* Overflow interrupt management ********************************************/ - if ((misflags & DCMI_MIS_OVR_MIS) != RESET) + if ((misflags & DCMI_MIS_OVR_MIS) != RESET) { /* Clear the Overflow flag */ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI); /* Update error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR; + hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR; } - + if (hdcmi->ErrorCode != HAL_DCMI_ERROR_NONE) { /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_READY; + hdcmi->State = HAL_DCMI_STATE_READY; /* Set the overflow callback */ hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError; - + /* Abort the DMA Transfer */ HAL_DMA_Abort_IT(hdcmi->DMA_Handle); - - /* Error Callback */ - HAL_DCMI_ErrorCallback(hdcmi); } - + /* Line Interrupt management ************************************************/ - if ((misflags & DCMI_MIS_LINE_MIS) != RESET) + if ((misflags & DCMI_MIS_LINE_MIS) != RESET) { - /* Clear the Line interrupt flag */ + /* Clear the Line interrupt flag */ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI); - /* Line interrupt Callback */ + /* Line interrupt Event Callback */ +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) + /*Call registered DCMI line event callback*/ + hdcmi->LineEventCallback(hdcmi); +#else HAL_DCMI_LineEventCallback(hdcmi); +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ } - + /* VSYNC interrupt management ***********************************************/ - if ((misflags & DCMI_MIS_VSYNC_MIS) != RESET) + if ((misflags & DCMI_MIS_VSYNC_MIS) != RESET) { /* Clear the VSYNC flag */ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI); - /* VSYNC Callback */ + /* VSYNC Event Callback */ +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) + /*Call registered DCMI vsync event callback*/ + hdcmi->VsyncEventCallback(hdcmi); +#else HAL_DCMI_VsyncEventCallback(hdcmi); +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ } - + /* End of Frame interrupt management ****************************************/ - if ((misflags & DCMI_MIS_FRAME_MIS) != RESET) + if ((misflags & DCMI_MIS_FRAME_MIS) != RESET) { /* Disable the Line interrupt when using snapshot mode */ if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT) { __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE|DCMI_IT_VSYNC|DCMI_IT_ERR|DCMI_IT_OVR); /* Change the DCMI state */ - hdcmi->State = HAL_DCMI_STATE_READY; + hdcmi->State = HAL_DCMI_STATE_READY; } /* Clear the End of Frame flag */ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI); - /* End of Frame Callback */ + /* Frame Event Callback */ +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) + /*Call registered DCMI frame event callback*/ + hdcmi->FrameEventCallback(hdcmi); +#else HAL_DCMI_FrameEventCallback(hdcmi); +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ } } /** * @brief Error DCMI callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. * @retval None */ __weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdcmi); - + /* NOTE : This function should not be modified; when the callback is needed, the HAL_DCMI_ErrorCallback() callback can be implemented in the user file. */ @@ -769,15 +836,15 @@ __weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi) /** * @brief Line Event callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. * @retval None */ __weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdcmi); - + /* NOTE : This function should not be modified; when the callback is needed, the HAL_DCMI_LineEventCallback() callback can be implemented in the user file. */ @@ -785,15 +852,15 @@ __weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi) /** * @brief VSYNC Event callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. * @retval None */ __weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdcmi); - + /* NOTE : This function should not be modified; when the callback is needed, the HAL_DCMI_VsyncEventCallback() callback can be implemented in the user file. */ @@ -801,15 +868,15 @@ __weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi) /** * @brief Frame Event callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. * @retval None */ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdcmi); - + /* NOTE : This function should not be modified; when the callback is needed, the HAL_DCMI_FrameEventCallback() callback can be implemented in the user file. */ @@ -820,17 +887,17 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi) /** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions + * @brief Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Configure the crop feature. (+) Enable/Disable the crop feature. - (+) Configure the synchronization delimiters unmasks. - (+) Enable/Disable user-specified DCMI interrupts. + (+) Configure the synchronization delimiters unmasks. + (+) Enable/Disable user-specified DCMI interrupts. @endverbatim * @{ @@ -838,15 +905,15 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi) /** * @brief Configure the DCMI crop window coordinates. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @param X0: DCMI window crop window X offset (number of pixels clocks to count before the capture). - * @param Y0: DCMI window crop window Y offset (image capture starts with this line number, previous - * line data are ignored). - * @param XSize: DCMI crop window horizontal size (in number of pixels per line). - * @param YSize: DCMI crop window vertical size (in lines count). - * @note For all the parameters, the actual value is the input data + 1 (e.g. YSize = 0x0 means 1 line, - * YSize = 0x1 means 2 lines, ...) + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @param X0 DCMI window crop window X offset (number of pixels clocks to count before the capture). + * @param Y0 DCMI window crop window Y offset (image capture starts with this line number, previous + * line data are ignored). + * @param XSize DCMI crop window horizontal size (in number of pixels per line). + * @param YSize DCMI crop window vertical size (in lines count). + * @note For all the parameters, the actual value is the input data + 1 (e.g. YSize = 0x0 means 1 line, + * YSize = 0x1 means 2 lines, ...) * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize) @@ -856,7 +923,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui assert_param(IS_DCMI_WINDOW_HEIGHT(Y0)); assert_param(IS_DCMI_WINDOW_COORDINATE(XSize)); assert_param(IS_DCMI_WINDOW_COORDINATE(YSize)); - + /* Process Locked */ __HAL_LOCK(hdcmi); @@ -864,8 +931,8 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui hdcmi->State = HAL_DCMI_STATE_BUSY; /* Configure CROP */ - MODIFY_REG(hdcmi->Instance->CWSIZER, (DCMI_CWSIZE_VLINE|DCMI_CWSIZE_CAPCNT), (XSize | (YSize << DCMI_POSITION_CWSIZE_VLINE))); - MODIFY_REG(hdcmi->Instance->CWSTRTR, (DCMI_CWSTRT_VST|DCMI_CWSTRT_HOFFCNT), (X0 | (Y0 << DCMI_POSITION_CWSTRT_VST))); + MODIFY_REG(hdcmi->Instance->CWSIZER, (DCMI_CWSIZE_VLINE|DCMI_CWSIZE_CAPCNT), (XSize | (YSize << DCMI_CWSIZE_VLINE_Pos))); + MODIFY_REG(hdcmi->Instance->CWSTRTR, (DCMI_CWSTRT_VST|DCMI_CWSTRT_HOFFCNT), (X0 | (Y0 << DCMI_CWSTRT_VST_Pos))); /* Initialize the DCMI state*/ hdcmi->State = HAL_DCMI_STATE_READY; @@ -878,8 +945,8 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui /** * @brief Disable the crop feature. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi) @@ -894,18 +961,18 @@ HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi) CLEAR_BIT(hdcmi->Instance->CR, DCMI_CR_CROP); /* Change the DCMI state*/ - hdcmi->State = HAL_DCMI_STATE_READY; + hdcmi->State = HAL_DCMI_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdcmi); - return HAL_OK; + return HAL_OK; } /** * @brief Enable the crop feature. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi) @@ -917,7 +984,7 @@ HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi) hdcmi->State = HAL_DCMI_STATE_BUSY; /* Enable DCMI Crop feature */ - SET_BIT(hdcmi->Instance->CR, DCMI_CR_CROP); + SET_BIT(hdcmi->Instance->CR, DCMI_CR_CROP); /* Change the DCMI state*/ hdcmi->State = HAL_DCMI_STATE_READY; @@ -925,15 +992,15 @@ HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi) /* Process Unlocked */ __HAL_UNLOCK(hdcmi); - return HAL_OK; + return HAL_OK; } /** * @brief Set embedded synchronization delimiters unmasks. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @param SyncUnmask: pointer to a DCMI_SyncUnmaskTypeDef structure that contains - * the embedded synchronization delimiters unmasks. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @param SyncUnmask pointer to a DCMI_SyncUnmaskTypeDef structure that contains + * the embedded synchronization delimiters unmasks. * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask) @@ -946,9 +1013,9 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_Syn /* Write DCMI embedded synchronization unmask register */ hdcmi->Instance->ESUR = (((uint32_t)SyncUnmask->FrameStartUnmask) |\ - ((uint32_t)SyncUnmask->LineStartUnmask << DCMI_POSITION_ESUR_LSU)|\ - ((uint32_t)SyncUnmask->LineEndUnmask << DCMI_POSITION_ESUR_LEU)|\ - ((uint32_t)SyncUnmask->FrameEndUnmask << DCMI_POSITION_ESUR_FEU)); + ((uint32_t)SyncUnmask->LineStartUnmask << DCMI_ESUR_LSU_Pos)|\ + ((uint32_t)SyncUnmask->LineEndUnmask << DCMI_ESUR_LEU_Pos)|\ + ((uint32_t)SyncUnmask->FrameEndUnmask << DCMI_ESUR_FEU_Pos)); /* Change the DCMI state*/ hdcmi->State = HAL_DCMI_STATE_READY; @@ -956,7 +1023,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_Syn /* Process Unlocked */ __HAL_UNLOCK(hdcmi); - return HAL_OK; + return HAL_OK; } @@ -967,38 +1034,38 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_Syn */ /** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions + * @brief Peripheral State functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State and Errors functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides functions allowing to (+) Check the DCMI state. - (+) Get the specific DCMI error flag. + (+) Get the specific DCMI error flag. @endverbatim * @{ - */ + */ /** * @brief Return the DCMI state. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. * @retval HAL state */ -HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi) +HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi) { return hdcmi->State; } /** -* @brief Return the DCMI error code. -* @param hdcmi : pointer to a DCMI_HandleTypeDef structure that contains + * @brief Return the DCMI error code. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. -* @retval DCMI Error Code -*/ + * @retval DCMI Error Code + */ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi) { return hdcmi->ErrorCode; @@ -1007,72 +1074,242 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi) /** * @} */ - + +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) +/** + * @brief DCMI Callback registering + * @param hdcmi dcmi handle + * @param CallbackID dcmi Callback ID + * @param pCallback pointer to dcmi Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* update the error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + else + { + if(hdcmi->State == HAL_DCMI_STATE_READY) + { + switch (CallbackID) + { + case HAL_DCMI_FRAME_EVENT_CB_ID : + hdcmi->FrameEventCallback = pCallback; + break; + + case HAL_DCMI_VSYNC_EVENT_CB_ID : + hdcmi->VsyncEventCallback = pCallback; + break; + + case HAL_DCMI_LINE_EVENT_CB_ID : + hdcmi->LineEventCallback = pCallback; + break; + + case HAL_DCMI_ERROR_CB_ID : + hdcmi->ErrorCallback = pCallback; + break; + + case HAL_DCMI_MSPINIT_CB_ID : + hdcmi->MspInitCallback = pCallback; + break; + + case HAL_DCMI_MSPDEINIT_CB_ID : + hdcmi->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if(hdcmi->State == HAL_DCMI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DCMI_MSPINIT_CB_ID : + hdcmi->MspInitCallback = pCallback; + break; + + case HAL_DCMI_MSPDEINIT_CB_ID : + hdcmi->MspDeInitCallback = pCallback; + break; + + default : + /* update the error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief DCMI Callback Unregistering + * @param hdcmi dcmi handle + * @param CallbackID dcmi Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(hdcmi->State == HAL_DCMI_STATE_READY) + { + switch (CallbackID) + { + case HAL_DCMI_FRAME_EVENT_CB_ID : + hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */ + break; + + case HAL_DCMI_VSYNC_EVENT_CB_ID : + hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */ + break; + + case HAL_DCMI_LINE_EVENT_CB_ID : + hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */ + break; + + case HAL_DCMI_ERROR_CB_ID : + hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_DCMI_MSPINIT_CB_ID : + hdcmi->MspInitCallback = HAL_DCMI_MspInit; + break; + + case HAL_DCMI_MSPDEINIT_CB_ID : + hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit; + break; + + default : + /* update the error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(hdcmi->State == HAL_DCMI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DCMI_MSPINIT_CB_ID : + hdcmi->MspInitCallback = HAL_DCMI_MspInit; + break; + + case HAL_DCMI_MSPDEINIT_CB_ID : + hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit; + break; + + default : + /* update the error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ + /** * @} - */ - + */ + /* Private functions ---------------------------------------------------------*/ /** @defgroup DCMI_Private_Functions DCMI Private Functions * @{ */ - - /** - * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @note When the size of the frame being captured by the DCMI peripheral is - * larger than 0xFFFF (DMA maximum transfer length), this API initiates - * another DMA transfer to copy the second half of the work buffer - * associated to the DCMI handle to the final destination buffer. + +/** + * @brief DMA conversion complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @note When the size of the frame being captured by the DCMI peripheral is + * larger than 0xFFFF (DMA maximum transfer length), this API initiates + * another DMA transfer to copy the second half of the work buffer + * associated to the DCMI handle to the final destination buffer. * @retval None */ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma) { uint32_t loop_length = 0; /* transfer length */ uint32_t * tmpBuffer_Dest = NULL; - uint32_t * tmpBuffer_Orig = NULL; - + uint32_t * tmpBuffer_Orig = NULL; + DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; if(hdcmi->XferCount != 0) { - /* Manage second half buffer copy in case of big transfer */ - + /* Manage second half buffer copy in case of big transfer */ + /* Decrement half-copies counter */ - hdcmi->XferCount--; - + hdcmi->XferCount--; + /* Point at DCMI final destination */ - tmpBuffer_Dest = (uint32_t *)hdcmi->pBuffPtr; - + tmpBuffer_Dest = (uint32_t *)hdcmi->pBuffPtr; + /* Point at DCMI circular buffer mid-location */ - tmpBuffer_Orig = (uint32_t *)hdcmi->pCircularBuffer; - tmpBuffer_Orig += hdcmi->HalfCopyLength; - + tmpBuffer_Orig = (uint32_t *)hdcmi->pCircularBuffer; + tmpBuffer_Orig += hdcmi->HalfCopyLength; + /* copy half the buffer size */ loop_length = hdcmi->HalfCopyLength; - + /* Save next entry to write at next half DMA transfer interruption */ hdcmi->pBuffPtr += (uint32_t) loop_length*4; - hdcmi->XferSize -= hdcmi->HalfCopyLength; - + hdcmi->XferSize -= hdcmi->HalfCopyLength; + /* Data copy from work buffer to final destination buffer */ /* Enable the DMA Channel */ if (HAL_DMA_Start_IT(hdcmi->DMAM2M_Handle, (uint32_t) tmpBuffer_Orig, (uint32_t) tmpBuffer_Dest, loop_length) != HAL_OK) { /* Update error code */ hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA; - + /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_READY; - + hdcmi->State = HAL_DCMI_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hdcmi); - /* Error Callback */ - HAL_DCMI_ErrorCallback(hdcmi); - } + /* DCMI error Callback */ +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) + /*Call registered DCMI error callback*/ + hdcmi->ErrorCallback(hdcmi); +#else + HAL_DCMI_ErrorCallback(hdcmi); +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ + } } else { @@ -1084,64 +1321,69 @@ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma) { /* Clear the End of Frame flag */ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI); - + /* When snapshot mode, disable Vsync, Error and Overrun interrupts */ if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT) - { + { /* Disable the Vsync, Error and Overrun interrupts */ __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR); - + hdcmi->State = HAL_DCMI_STATE_READY; - + /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); + __HAL_UNLOCK(hdcmi); } - - /* FRAME Callback */ + + /* Frame Event Callback */ +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) + /*Call registered DCMI frame event callback*/ + hdcmi->FrameEventCallback(hdcmi); +#else HAL_DCMI_FrameEventCallback(hdcmi); - } +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ + } } } } - /** - * @brief DMA Half Transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @note When the size of the frame being captured by the DCMI peripheral is - * larger than 0xFFFF (DMA maximum transfer length), this API initiates - * another DMA transfer to copy the first half of the work buffer - * associated to the DCMI handle to the final destination buffer. +/** + * @brief DMA Half Transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @note When the size of the frame being captured by the DCMI peripheral is + * larger than 0xFFFF (DMA maximum transfer length), this API initiates + * another DMA transfer to copy the first half of the work buffer + * associated to the DCMI handle to the final destination buffer. * @retval None */ static void DCMI_DMAHalfXferCplt(DMA_HandleTypeDef *hdma) { uint32_t loop_length = 0; /* transfer length */ uint32_t * tmpBuffer_Dest = NULL; - uint32_t * tmpBuffer_Orig = NULL; - + uint32_t * tmpBuffer_Orig = NULL; + DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + if(hdcmi->XferCount != 0) { - /* Manage first half buffer copy in case of big transfer */ - + /* Manage first half buffer copy in case of big transfer */ + /* Decrement half-copies counter */ - hdcmi->XferCount--; - + hdcmi->XferCount--; + /* Point at DCMI final destination */ - tmpBuffer_Dest = (uint32_t *)hdcmi->pBuffPtr; - + tmpBuffer_Dest = (uint32_t *)hdcmi->pBuffPtr; + /* Point at DCMI circular buffer start */ - tmpBuffer_Orig = (uint32_t *)hdcmi->pCircularBuffer; - + tmpBuffer_Orig = (uint32_t *)hdcmi->pCircularBuffer; + /* copy half the buffer size */ loop_length = hdcmi->HalfCopyLength; - + /* Save next entry to write at next DMA transfer interruption */ hdcmi->pBuffPtr += (uint32_t) loop_length*4; - hdcmi->XferSize -= hdcmi->HalfCopyLength; + hdcmi->XferSize -= hdcmi->HalfCopyLength; /* Data copy from work buffer to final destination buffer */ /* Enable the DMA Channel */ @@ -1149,37 +1391,47 @@ static void DCMI_DMAHalfXferCplt(DMA_HandleTypeDef *hdma) { /* Update error code */ hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA; - + /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_READY; - + hdcmi->State = HAL_DCMI_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hdcmi); - /* Error Callback */ - HAL_DCMI_ErrorCallback(hdcmi); - } + /* DCMI error Callback */ +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) + /*Call registered DCMI error callback*/ + hdcmi->ErrorCallback(hdcmi); +#else + HAL_DCMI_ErrorCallback(hdcmi); +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ + } } } /** - * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief DMA error callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void DCMI_DMAError(DMA_HandleTypeDef *hdma) { - DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Update error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA; - - /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_READY; + DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Error Callback */ - HAL_DCMI_ErrorCallback(hdcmi); + /* Update error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA; + + /* Change DCMI state */ + hdcmi->State = HAL_DCMI_STATE_READY; + + /* DCMI error Callback */ +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) + /*Call registered DCMI error callback*/ + hdcmi->ErrorCallback(hdcmi); +#else + HAL_DCMI_ErrorCallback(hdcmi); +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ } /** @@ -1188,21 +1440,21 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma) * the tranfer from DCMI DR register to the final output buffer is carried out by a sequence * of intermediate sub-copies to temporary buffers of size less than 0xFFFF. * To optimize the number of DMA transfers, the API computes the temporary buffer - * size so that the latter is an even number less than 0xFFFF, that divides the final - * buffer size and is as high as possible. The API implements a sub-optimum solution for - * complexity's sake. - * @note InputSize MUST be even. - * @param InputSize: full buffer size (in 32-bit words) + * size so that the latter is an even number less than 0xFFFF, that divides the final + * buffer size and is as high as possible. The API implements a sub-optimum solution for + * complexity's sake. + * @note InputSize MUST be even. + * @param InputSize full buffer size (in 32-bit words) * @retval Transfer size (in 32-bit words) */ static uint32_t DCMI_TransferSize(uint32_t InputSize) -{ +{ uint32_t j = 1; uint32_t temp = InputSize; uint32_t aPrime[NPRIME] = {0}; uint32_t output = 2; /* Want a result which is an even number */ - + /* Develop InputSize in product of prime numbers */ while (j < NPRIME) @@ -1213,12 +1465,12 @@ static uint32_t DCMI_TransferSize(uint32_t InputSize) } while ((temp % PrimeArray[j]) == 0) { - aPrime[j]++; - temp /= PrimeArray[j]; + aPrime[j]++; + temp /= PrimeArray[j]; } j++; - } - + } + /* Search for the biggest even divisor less or equal to 0xFFFE = 65534 */ aPrime[1] -= 1; /* output is initialized to 2, so don't count dividor 2 twice */ @@ -1226,7 +1478,7 @@ static uint32_t DCMI_TransferSize(uint32_t InputSize) but in an acceptable time. */ j = NPRIME-1; while ((j > 0) && (output <= 0xFFFE)) - { + { while (aPrime[j] >0) { if (output * PrimeArray[j] > 0xFFFE) @@ -1235,19 +1487,19 @@ static uint32_t DCMI_TransferSize(uint32_t InputSize) } else { - output *= PrimeArray[j]; + output *= PrimeArray[j]; aPrime[j]--; } } j--; } - - - + + + return output; } - + /** * @} */ @@ -1260,9 +1512,7 @@ static uint32_t DCMI_TransferSize(uint32_t InputSize) * @} */ -#endif /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - +#endif /* DCMI */ #endif /* HAL_DCMI_MODULE_ENABLED */ - + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c index 4222a406d4..4bc3103159 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32l4xx_hal_dfsdm.c * @author MCD Application Team - * @brief This file provides firmware functions to manage the following + * @brief This file provides firmware functions to manage the following * functionalities of the Digital Filter for Sigma-Delta Modulators * (DFSDM) peripherals: * + Initialization and configuration of channels and filters @@ -15,7 +15,7 @@ * + Extremes detector feature * + Clock absence detector feature * + Break generation on analog watchdog or short-circuit event - * + * @verbatim ============================================================================== ##### How to use this driver ##### @@ -32,7 +32,7 @@ (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). (#) Configure the output clock, input, serial interface, analog watchdog, - offset and data right bit shift parameters for this channel using the + offset and data right bit shift parameters for this channel using the HAL_DFSDM_ChannelInit() function. *** Channel clock absence detector *** @@ -46,36 +46,36 @@ clock absence is detected. (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or HAL_DFSDM_ChannelCkabStop_IT(). - (#) Please note that the same mode (polling or interrupt) has to be used + (#) Please note that the same mode (polling or interrupt) has to be used for all channels because the channels are sharing the same interrupt. (#) Please note also that in interrupt mode, if clock absence detector is stopped for one channel, interrupt will be disabled for all channels. *** Channel short circuit detector *** ====================================== - [..] + [..] (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or or HAL_DFSDM_ChannelScdStart_IT(). (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short circuit. - (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if + (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if short circuit is detected. (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or or HAL_DFSDM_ChannelScdStop_IT(). - (#) Please note that the same mode (polling or interrupt) has to be used + (#) Please note that the same mode (polling or interrupt) has to be used for all channels because the channels are sharing the same interrupt. (#) Please note also that in interrupt mode, if short circuit detector is stopped for one channel, interrupt will be disabled for all channels. *** Channel analog watchdog value *** ===================================== - [..] + [..] (#) Get analog watchdog filter value of a channel using HAL_DFSDM_ChannelGetAwdValue(). *** Channel offset value *** ===================================== - [..] + [..] (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset(). *** Filter initialization *** @@ -94,21 +94,21 @@ *** Filter regular channel conversion *** ========================================= - [..] + [..] (#) Select regular channel and enable/disable continuous mode using HAL_DFSDM_FilterConfigRegChannel(). (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(), HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or HAL_DFSDM_FilterRegularMsbStart_DMA(). - (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect + (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect the end of regular conversion. (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called at the end of regular conversion. - (#) Get value of regular conversion and corresponding channel using + (#) Get value of regular conversion and corresponding channel using HAL_DFSDM_FilterGetRegularValue(). - (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and + (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the - half transfer and at the transfer complete. Please note that + half transfer and at the transfer complete. Please note that HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA circular mode. (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(), @@ -121,15 +121,15 @@ (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(), HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or HAL_DFSDM_FilterInjectedMsbStart_DMA(). - (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect + (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect the end of injected conversion. (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called at the end of injected conversion. - (#) Get value of injected conversion and corresponding channel using + (#) Get value of injected conversion and corresponding channel using HAL_DFSDM_FilterGetInjectedValue(). - (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and + (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the - half transfer and at the transfer complete. Please note that + half transfer and at the transfer complete. Please note that HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA circular mode. (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(), @@ -155,6 +155,86 @@ [..] (#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue(). + *** Callback registration *** + ============================= + + The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use functions @ref HAL_DFSDM_Channel_RegisterCallback(), + @ref HAL_DFSDM_Filter_RegisterCallback() or + @ref HAL_DFSDM_Filter_RegisterAwdCallback() to register a user callback. + + Function @ref HAL_DFSDM_Channel_RegisterCallback() allows to register + following callbacks: + (+) CkabCallback : DFSDM channel clock absence detection callback. + (+) ScdCallback : DFSDM channel short circuit detection callback. + (+) MspInitCallback : DFSDM channel MSP init callback. + (+) MspDeInitCallback : DFSDM channel MSP de-init callback. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Function @ref HAL_DFSDM_Filter_RegisterCallback() allows to register + following callbacks: + (+) RegConvCpltCallback : DFSDM filter regular conversion complete callback. + (+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback. + (+) InjConvCpltCallback : DFSDM filter injected conversion complete callback. + (+) InjConvHalfCpltCallback : DFSDM filter half injected conversion complete callback. + (+) ErrorCallback : DFSDM filter error callback. + (+) MspInitCallback : DFSDM filter MSP init callback. + (+) MspDeInitCallback : DFSDM filter MSP de-init callback. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + For specific DFSDM filter analog watchdog callback use dedicated register callback: + @ref HAL_DFSDM_Filter_RegisterAwdCallback(). + + Use functions @ref HAL_DFSDM_Channel_UnRegisterCallback() or + @ref HAL_DFSDM_Filter_UnRegisterCallback() to reset a callback to the default + weak function. + + @ref HAL_DFSDM_Channel_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) CkabCallback : DFSDM channel clock absence detection callback. + (+) ScdCallback : DFSDM channel short circuit detection callback. + (+) MspInitCallback : DFSDM channel MSP init callback. + (+) MspDeInitCallback : DFSDM channel MSP de-init callback. + + @ref HAL_DFSDM_Filter_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) RegConvCpltCallback : DFSDM filter regular conversion complete callback. + (+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback. + (+) InjConvCpltCallback : DFSDM filter injected conversion complete callback. + (+) InjConvHalfCpltCallback : DFSDM filter half injected conversion complete callback. + (+) ErrorCallback : DFSDM filter error callback. + (+) MspInitCallback : DFSDM filter MSP init callback. + (+) MspDeInitCallback : DFSDM filter MSP de-init callback. + + For specific DFSDM filter analog watchdog callback use dedicated unregister callback: + @ref HAL_DFSDM_Filter_UnRegisterAwdCallback(). + + By default, after the call of init function and if the state is RESET + all callbacks are reset to the corresponding legacy weak functions: + examples @ref HAL_DFSDM_ChannelScdCallback(), @ref HAL_DFSDM_FilterErrorCallback(). + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak functions in the init and de-init only when these + callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the init and de-init keep and use + the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the init/de-init. + In that case first register the MspInit/MspDeInit user callbacks using + @ref HAL_DFSDM_Channel_RegisterCallback() or + @ref HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function. + + When The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak callbacks are used. + @endverbatim ****************************************************************************** * @attention @@ -202,7 +282,7 @@ /** @defgroup DFSDM DFSDM * @brief DFSDM HAL driver module * @{ - */ + */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -227,8 +307,8 @@ /** @defgroup DFSDM_Private_Variables DFSDM Private Variables * @{ */ -__IO uint32_t v_dfsdm1ChannelCounter = 0; -DFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL}; +static __IO uint32_t v_dfsdm1ChannelCounter = 0; +static DFSDM_Channel_HandleTypeDef *a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL}; /** * @} */ @@ -238,11 +318,11 @@ DFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NUL * @{ */ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels); -static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance); +static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance); static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); -static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); -static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); +static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma); static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma); static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma); @@ -258,7 +338,7 @@ static void DFSDM_DMAError(DMA_HandleTypeDef *hdma); */ /** @defgroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions - * @brief Channel initialization and de-initialization functions + * @brief Channel initialization and de-initialization functions * @verbatim ============================================================================== @@ -280,7 +360,7 @@ static void DFSDM_DMAError(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { /* Check DFSDM Channel handle */ - if(hdfsdm_channel == NULL) + if (hdfsdm_channel == NULL) { return HAL_ERROR; } @@ -297,72 +377,85 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling)); assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset)); assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift)); - + /* Check that channel has not been already initialized */ - if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL) + if (a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL) { return HAL_ERROR; } - + +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + /* Reset callback pointers to the weak predefined callbacks */ + hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback; + hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback; + + /* Call MSP init function */ + if (hdfsdm_channel->MspInitCallback == NULL) + { + hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit; + } + hdfsdm_channel->MspInitCallback(hdfsdm_channel); +#else /* Call MSP init function */ HAL_DFSDM_ChannelMspInit(hdfsdm_channel); - +#endif + /* Update the channel counter */ v_dfsdm1ChannelCounter++; - + /* Configure output serial clock and enable global DFSDM interface only for first channel */ - if(v_dfsdm1ChannelCounter == 1) + if (v_dfsdm1ChannelCounter == 1U) { assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection)); /* Set the output serial clock source */ DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC); DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection; - + /* Reset clock divider */ DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV); - if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE) + if (hdfsdm_channel->Init.OutputClock.Activation == ENABLE) { assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider)); /* Set the output clock divider */ - DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1) << + DFSDM1_Channel0->CHCFGR1 |= (uint32_t)((hdfsdm_channel->Init.OutputClock.Divider - 1U) << DFSDM_CHCFGR1_CKOUTDIV_Pos); } - + /* enable the DFSDM global interface */ DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN; } - + /* Set channel input parameters */ - hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX | + hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX | DFSDM_CHCFGR1_CHINSEL); - hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer | - hdfsdm_channel->Init.Input.DataPacking | + hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer | + hdfsdm_channel->Init.Input.DataPacking | hdfsdm_channel->Init.Input.Pins); - + /* Set serial interface parameters */ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL); - hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type | + hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type | hdfsdm_channel->Init.SerialInterface.SpiClock); - + /* Set analog watchdog parameters */ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR); - hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder | - ((hdfsdm_channel->Init.Awd.Oversampling - 1) << DFSDM_CHAWSCDR_AWFOSR_Pos)); + hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder | + ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos)); /* Set channel offset and right bit shift */ hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS); - hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) | + hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) | (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos)); /* Enable DFSDM channel */ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN; - + /* Set DFSDM Channel to ready state */ hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY; /* Store channel handle in DFSDM channel handle table */ a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel; - + return HAL_OK; } @@ -374,34 +467,42 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { /* Check DFSDM Channel handle */ - if(hdfsdm_channel == NULL) + if (hdfsdm_channel == NULL) { return HAL_ERROR; } /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - + /* Check that channel has not been already deinitialized */ - if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL) + if (a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL) { return HAL_ERROR; } /* Disable the DFSDM channel */ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN); - + /* Update the channel counter */ v_dfsdm1ChannelCounter--; - + /* Disable global DFSDM at deinit of last channel */ - if(v_dfsdm1ChannelCounter == 0) + if (v_dfsdm1ChannelCounter == 0U) { DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN); } /* Call MSP deinit function */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + if (hdfsdm_channel->MspDeInitCallback == NULL) + { + hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit; + } + hdfsdm_channel->MspDeInitCallback(hdfsdm_channel); +#else HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel); +#endif /* Set DFSDM Channel in reset state */ hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET; @@ -421,7 +522,7 @@ __weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel { /* Prevent unused argument(s) compilation warning */ UNUSED(hdfsdm_channel); - + /* NOTE : This function should not be modified, when the function is needed, the HAL_DFSDM_ChannelMspInit could be implemented in the user file. */ @@ -436,12 +537,150 @@ __weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chann { /* Prevent unused argument(s) compilation warning */ UNUSED(hdfsdm_channel); - + /* NOTE : This function should not be modified, when the function is needed, the HAL_DFSDM_ChannelMspDeInit could be implemented in the user file. */ } +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a user DFSDM channel callback + * to be used instead of the weak predefined callback. + * @param hdfsdm_channel DFSDM channel handle. + * @param CallbackID ID of the callback to be registered. + * This parameter can be one of the following values: + * @arg @ref HAL_DFSDM_CHANNEL_CKAB_CB_ID clock absence detection callback ID. + * @arg @ref HAL_DFSDM_CHANNEL_SCD_CB_ID short circuit detection callback ID. + * @arg @ref HAL_DFSDM_CHANNEL_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID MSP de-init callback ID. + * @param pCallback pointer to the callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, + HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID, + pDFSDM_Channel_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* update return status */ + status = HAL_ERROR; + } + else + { + if (HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State) + { + switch (CallbackID) + { + case HAL_DFSDM_CHANNEL_CKAB_CB_ID : + hdfsdm_channel->CkabCallback = pCallback; + break; + case HAL_DFSDM_CHANNEL_SCD_CB_ID : + hdfsdm_channel->ScdCallback = pCallback; + break; + case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID : + hdfsdm_channel->MspInitCallback = pCallback; + break; + case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID : + hdfsdm_channel->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State) + { + switch (CallbackID) + { + case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID : + hdfsdm_channel->MspInitCallback = pCallback; + break; + case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID : + hdfsdm_channel->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief Unregister a user DFSDM channel callback. + * DFSDM channel callback is redirected to the weak predefined callback. + * @param hdfsdm_channel DFSDM channel handle. + * @param CallbackID ID of the callback to be unregistered. + * This parameter can be one of the following values: + * @arg @ref HAL_DFSDM_CHANNEL_CKAB_CB_ID clock absence detection callback ID. + * @arg @ref HAL_DFSDM_CHANNEL_SCD_CB_ID short circuit detection callback ID. + * @arg @ref HAL_DFSDM_CHANNEL_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID MSP de-init callback ID. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, + HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State) + { + switch (CallbackID) + { + case HAL_DFSDM_CHANNEL_CKAB_CB_ID : + hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback; + break; + case HAL_DFSDM_CHANNEL_SCD_CB_ID : + hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback; + break; + case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID : + hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit; + break; + case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID : + hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State) + { + switch (CallbackID) + { + case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID : + hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit; + break; + case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID : + hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + return status; +} +#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ + /** * @} */ @@ -479,9 +718,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - + /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { /* Return error status */ status = HAL_ERROR; @@ -495,12 +734,12 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm tickstart = HAL_GetTick(); /* Clear clock absence flag */ - while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1) != 0) + while ((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U) { - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); + DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Check the Timeout */ - if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) + if ((HAL_GetTick() - tickstart) > DFSDM_CKAB_TIMEOUT) { /* Set timeout status */ status = HAL_TIMEOUT; @@ -508,7 +747,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm } } - if(status == HAL_OK) + if (status == HAL_OK) { /* Start clock absence detection */ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN; @@ -524,17 +763,17 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm * @param Timeout Timeout value in milliseconds. * @retval HAL status */ -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout) { uint32_t tickstart; uint32_t channel; - + /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { /* Return error status */ return HAL_ERROR; @@ -543,27 +782,27 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs { /* Get channel number from channel instance */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - + /* Get timeout */ tickstart = HAL_GetTick(); /* Wait clock absence detection */ - while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1) == 0) + while ((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) == 0U) { /* Check the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Return timeout status */ return HAL_TIMEOUT; } } } - + /* Clear clock absence detection flag */ - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); - + DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); + /* Return function status */ return HAL_OK; } @@ -581,9 +820,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_ /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - + /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { /* Return error status */ status = HAL_ERROR; @@ -592,10 +831,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_ { /* Stop clock absence detection */ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN); - + /* Clear clock absence flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); + DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); } /* Return function status */ return status; @@ -618,9 +857,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdf /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - + /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { /* Return error status */ status = HAL_ERROR; @@ -634,12 +873,12 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdf tickstart = HAL_GetTick(); /* Clear clock absence flag */ - while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1) != 0) + while ((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U) { - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); + DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Check the Timeout */ - if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) + if ((HAL_GetTick() - tickstart) > DFSDM_CKAB_TIMEOUT) { /* Set timeout status */ status = HAL_TIMEOUT; @@ -647,7 +886,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdf } } - if(status == HAL_OK) + if (status == HAL_OK) { /* Activate clock absence detection interrupt */ DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_CKABIE; @@ -661,7 +900,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdf } /** - * @brief Clock absence detection callback. + * @brief Clock absence detection callback. * @param hdfsdm_channel DFSDM channel handle. * @retval None */ @@ -669,7 +908,7 @@ __weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_ch { /* Prevent unused argument(s) compilation warning */ UNUSED(hdfsdm_channel); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DFSDM_ChannelCkabCallback could be implemented in the user file */ @@ -688,9 +927,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfs /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - + /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { /* Return error status */ status = HAL_ERROR; @@ -699,10 +938,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfs { /* Stop clock absence detection */ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN); - + /* Clear clock absence flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); + DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Disable clock absence detection interrupt */ DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE); @@ -731,9 +970,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold)); assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal)); - + /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { /* Return error status */ status = HAL_ERROR; @@ -743,8 +982,8 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_ /* Configure threshold and break signals */ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT); hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \ - Threshold); - + Threshold); + /* Start short circuit detection */ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN; } @@ -758,17 +997,17 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_ * @param Timeout Timeout value in milliseconds. * @retval HAL status */ -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout) { uint32_t tickstart; uint32_t channel; - + /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { /* Return error status */ return HAL_ERROR; @@ -777,27 +1016,27 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd { /* Get channel number from channel instance */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - + /* Get timeout */ tickstart = HAL_GetTick(); /* Wait short circuit detection */ - while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0) + while (((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0U) { /* Check the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Return timeout status */ return HAL_TIMEOUT; } } } - + /* Clear short circuit detection flag */ - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); - + DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); + /* Return function status */ return HAL_OK; } @@ -815,9 +1054,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_c /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - + /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { /* Return error status */ status = HAL_ERROR; @@ -826,10 +1065,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_c { /* Stop short circuit detection */ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN); - + /* Clear short circuit detection flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); + DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); } /* Return function status */ return status; @@ -855,9 +1094,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold)); assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal)); - + /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { /* Return error status */ status = HAL_ERROR; @@ -870,8 +1109,8 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs /* Configure threshold and break signals */ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT); hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \ - Threshold); - + Threshold); + /* Start short circuit detection */ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN; } @@ -880,7 +1119,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs } /** - * @brief Short circuit detection callback. + * @brief Short circuit detection callback. * @param hdfsdm_channel DFSDM channel handle. * @retval None */ @@ -888,7 +1127,7 @@ __weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_cha { /* Prevent unused argument(s) compilation warning */ UNUSED(hdfsdm_channel); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DFSDM_ChannelScdCallback could be implemented in the user file */ @@ -907,9 +1146,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - + /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { /* Return error status */ status = HAL_ERROR; @@ -918,10 +1157,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd { /* Stop short circuit detection */ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN); - + /* Clear short circuit detection flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); + DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); /* Disable short circuit detection interrupt */ DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE); @@ -955,9 +1194,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdf /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset)); - + /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { /* Return error status */ status = HAL_ERROR; @@ -1005,7 +1244,7 @@ HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTyp */ /** @defgroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions - * @brief Filter initialization and de-initialization functions + * @brief Filter initialization and de-initialization functions * @verbatim ============================================================================== @@ -1027,7 +1266,7 @@ HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTyp HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { /* Check DFSDM Channel handle */ - if(hdfsdm_filter == NULL) + if (hdfsdm_filter == NULL) { return HAL_ERROR; } @@ -1045,9 +1284,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling)); /* Check parameters compatibility */ - if((hdfsdm_filter->Instance == DFSDM1_Filter0) && - ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) || - (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER))) + if ((hdfsdm_filter->Instance == DFSDM1_Filter0) && + ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) || + (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER))) { return HAL_ERROR; } @@ -1057,13 +1296,30 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter hdfsdm_filter->InjectedChannelsNbr = 1; hdfsdm_filter->InjConvRemaining = 1; hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_NONE; - + +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + /* Reset callback pointers to the weak predefined callbacks */ + hdfsdm_filter->AwdCallback = HAL_DFSDM_FilterAwdCallback; + hdfsdm_filter->RegConvCpltCallback = HAL_DFSDM_FilterRegConvCpltCallback; + hdfsdm_filter->RegConvHalfCpltCallback = HAL_DFSDM_FilterRegConvHalfCpltCallback; + hdfsdm_filter->InjConvCpltCallback = HAL_DFSDM_FilterInjConvCpltCallback; + hdfsdm_filter->InjConvHalfCpltCallback = HAL_DFSDM_FilterInjConvHalfCpltCallback; + hdfsdm_filter->ErrorCallback = HAL_DFSDM_FilterErrorCallback; + + /* Call MSP init function */ + if (hdfsdm_filter->MspInitCallback == NULL) + { + hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit; + } + hdfsdm_filter->MspInitCallback(hdfsdm_filter); +#else /* Call MSP init function */ HAL_DFSDM_FilterMspInit(hdfsdm_filter); +#endif /* Set regular parameters */ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC); - if(hdfsdm_filter->Init.RegularParam.FastMode == ENABLE) + if (hdfsdm_filter->Init.RegularParam.FastMode == ENABLE) { hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_FAST; } @@ -1072,7 +1328,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_FAST); } - if(hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE) + if (hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE) { hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RDMAEN; } @@ -1083,14 +1339,14 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter /* Set injected parameters */ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC | DFSDM_FLTCR1_JEXTEN | DFSDM_FLTCR1_JEXTSEL); - if(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER) + if (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER) { assert_param(IS_DFSDM_FILTER_EXT_TRIG(hdfsdm_filter->Init.InjectedParam.ExtTrigger)); assert_param(IS_DFSDM_FILTER_EXT_TRIG_EDGE(hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge)); hdfsdm_filter->Instance->FLTCR1 |= (hdfsdm_filter->Init.InjectedParam.ExtTrigger); } - if(hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE) + if (hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE) { hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSCAN; } @@ -1099,7 +1355,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN); } - if(hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE) + if (hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE) { hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JDMAEN; } @@ -1107,25 +1363,25 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter { hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN); } - + /* Set filter parameters */ hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR); hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder | - ((hdfsdm_filter->Init.FilterParam.Oversampling - 1) << DFSDM_FLTFCR_FOSR_Pos) | - (hdfsdm_filter->Init.FilterParam.IntOversampling - 1)); + ((hdfsdm_filter->Init.FilterParam.Oversampling - 1U) << DFSDM_FLTFCR_FOSR_Pos) | + (hdfsdm_filter->Init.FilterParam.IntOversampling - 1U)); /* Store regular and injected triggers and injected scan mode*/ hdfsdm_filter->RegularTrigger = hdfsdm_filter->Init.RegularParam.Trigger; hdfsdm_filter->InjectedTrigger = hdfsdm_filter->Init.InjectedParam.Trigger; hdfsdm_filter->ExtTriggerEdge = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge; hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode; - + /* Enable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; /* Set DFSDM filter to ready state */ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY; - + return HAL_OK; } @@ -1137,19 +1393,27 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { /* Check DFSDM filter handle */ - if(hdfsdm_filter == NULL) + if (hdfsdm_filter == NULL) { return HAL_ERROR; } /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - + /* Disable the DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); - + /* Call MSP deinit function */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + if (hdfsdm_filter->MspDeInitCallback == NULL) + { + hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit; + } + hdfsdm_filter->MspDeInitCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterMspDeInit(hdfsdm_filter); +#endif /* Set DFSDM filter in reset state */ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET; @@ -1166,7 +1430,7 @@ __weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdfsdm_filter); - + /* NOTE : This function should not be modified, when the function is needed, the HAL_DFSDM_FilterMspInit could be implemented in the user file. */ @@ -1181,12 +1445,248 @@ __weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdfsdm_filter); - + /* NOTE : This function should not be modified, when the function is needed, the HAL_DFSDM_FilterMspDeInit could be implemented in the user file. */ } +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a user DFSDM filter callback + * to be used instead of the weak predefined callback. + * @param hdfsdm_filter DFSDM filter handle. + * @param CallbackID ID of the callback to be registered. + * This parameter can be one of the following values: + * @arg @ref HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID regular conversion complete callback ID. + * @arg @ref HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID half regular conversion complete callback ID. + * @arg @ref HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID injected conversion complete callback ID. + * @arg @ref HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID half injected conversion complete callback ID. + * @arg @ref HAL_DFSDM_FILTER_ERROR_CB_ID error callback ID. + * @arg @ref HAL_DFSDM_FILTER_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_DFSDM_FILTER_MSPDEINIT_CB_ID MSP de-init callback ID. + * @param pCallback pointer to the callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID, + pDFSDM_Filter_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* update the error code */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + else + { + if (HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State) + { + switch (CallbackID) + { + case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID : + hdfsdm_filter->RegConvCpltCallback = pCallback; + break; + case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID : + hdfsdm_filter->RegConvHalfCpltCallback = pCallback; + break; + case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID : + hdfsdm_filter->InjConvCpltCallback = pCallback; + break; + case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID : + hdfsdm_filter->InjConvHalfCpltCallback = pCallback; + break; + case HAL_DFSDM_FILTER_ERROR_CB_ID : + hdfsdm_filter->ErrorCallback = pCallback; + break; + case HAL_DFSDM_FILTER_MSPINIT_CB_ID : + hdfsdm_filter->MspInitCallback = pCallback; + break; + case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID : + hdfsdm_filter->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State) + { + switch (CallbackID) + { + case HAL_DFSDM_FILTER_MSPINIT_CB_ID : + hdfsdm_filter->MspInitCallback = pCallback; + break; + case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID : + hdfsdm_filter->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief Unregister a user DFSDM filter callback. + * DFSDM filter callback is redirected to the weak predefined callback. + * @param hdfsdm_filter DFSDM filter handle. + * @param CallbackID ID of the callback to be unregistered. + * This parameter can be one of the following values: + * @arg @ref HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID regular conversion complete callback ID. + * @arg @ref HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID half regular conversion complete callback ID. + * @arg @ref HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID injected conversion complete callback ID. + * @arg @ref HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID half injected conversion complete callback ID. + * @arg @ref HAL_DFSDM_FILTER_ERROR_CB_ID error callback ID. + * @arg @ref HAL_DFSDM_FILTER_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_DFSDM_FILTER_MSPDEINIT_CB_ID MSP de-init callback ID. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State) + { + switch (CallbackID) + { + case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID : + hdfsdm_filter->RegConvCpltCallback = HAL_DFSDM_FilterRegConvCpltCallback; + break; + case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID : + hdfsdm_filter->RegConvHalfCpltCallback = HAL_DFSDM_FilterRegConvHalfCpltCallback; + break; + case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID : + hdfsdm_filter->InjConvCpltCallback = HAL_DFSDM_FilterInjConvCpltCallback; + break; + case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID : + hdfsdm_filter->InjConvHalfCpltCallback = HAL_DFSDM_FilterInjConvHalfCpltCallback; + break; + case HAL_DFSDM_FILTER_ERROR_CB_ID : + hdfsdm_filter->ErrorCallback = HAL_DFSDM_FilterErrorCallback; + break; + case HAL_DFSDM_FILTER_MSPINIT_CB_ID : + hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit; + break; + case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID : + hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit; + break; + default : + /* update the error code */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State) + { + switch (CallbackID) + { + case HAL_DFSDM_FILTER_MSPINIT_CB_ID : + hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit; + break; + case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID : + hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit; + break; + default : + /* update the error code */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + return status; +} + +/** + * @brief Register a user DFSDM filter analog watchdog callback + * to be used instead of the weak predefined callback. + * @param hdfsdm_filter DFSDM filter handle. + * @param pCallback pointer to the DFSDM filter analog watchdog callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + pDFSDM_Filter_AwdCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* update the error code */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + else + { + if (HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State) + { + hdfsdm_filter->AwdCallback = pCallback; + } + else + { + /* update the error code */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief Unregister a user DFSDM filter analog watchdog callback. + * DFSDM filter AWD callback is redirected to the weak predefined callback. + * @param hdfsdm_filter DFSDM filter handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State) + { + hdfsdm_filter->AwdCallback = HAL_DFSDM_FilterAwdCallback; + } + else + { + /* update the error code */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + return status; +} +#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ + /** * @} */ @@ -1220,30 +1720,30 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *h uint32_t ContinuousMode) { HAL_StatusTypeDef status = HAL_OK; - + /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel)); assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode)); - + /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR)) + if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR)) { /* Configure channel and continuous mode for regular conversion */ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT); - if(ContinuousMode == DFSDM_CONTINUOUS_CONV_ON) + if (ContinuousMode == DFSDM_CONTINUOUS_CONV_ON) { - hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) (((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) | - DFSDM_FLTCR1_RCONT); + hdfsdm_filter->Instance->FLTCR1 |= (uint32_t)(((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) | + DFSDM_FLTCR1_RCONT); } else { - hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) ((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET); + hdfsdm_filter->Instance->FLTCR1 |= (uint32_t)((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET); } /* Store continuous mode information */ hdfsdm_filter->RegularContMode = ContinuousMode; - } + } else { status = HAL_ERROR; @@ -1268,18 +1768,18 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *h /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel)); - + /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR)) + if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR)) { /* Configure channel for injected conversion */ - hdfsdm_filter->Instance->FLTJCHGR = (uint32_t) (Channel & DFSDM_LSB_MASK); + hdfsdm_filter->Instance->FLTJCHGR = (uint32_t)(Channel & DFSDM_LSB_MASK); /* Store number of injected channels */ hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel); /* Update number of injected channels remaining */ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; + hdfsdm_filter->InjectedChannelsNbr : 1U; } else { @@ -1325,7 +1825,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *h /** * @brief This function allows to start regular conversion in polling mode. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if injected conversion is ongoing. * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status @@ -1338,8 +1838,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsd assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) + if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) { /* Start regular conversion */ DFSDM_RegConvStart(hdfsdm_filter); @@ -1368,8 +1868,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDe assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { /* Return error status */ return HAL_ERROR; @@ -1377,15 +1877,15 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDe else { /* Get timeout */ - tickstart = HAL_GetTick(); + tickstart = HAL_GetTick(); /* Wait end of regular conversion */ - while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF) + while ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF) { /* Check the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Return timeout status */ return HAL_TIMEOUT; @@ -1393,18 +1893,22 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDe } } /* Check if overrun occurs */ - if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF) + if ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF) { /* Update error code and call error callback */ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN; +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->ErrorCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); +#endif /* Clear regular overrun flag */ hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF; } /* Update DFSDM filter state only if not continuous conversion and SW trigger */ - if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) + if ((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ + (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) { hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \ HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ; @@ -1428,8 +1932,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { /* Return error status */ status = HAL_ERROR; @@ -1445,7 +1949,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm /** * @brief This function allows to start regular conversion in interrupt mode. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if injected conversion is ongoing. * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status @@ -1458,12 +1962,12 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hd assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) + if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) { /* Enable interrupts for regular conversions */ hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE); - + /* Start regular conversion */ DFSDM_RegConvStart(hdfsdm_filter); } @@ -1489,8 +1993,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdf assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { /* Return error status */ status = HAL_ERROR; @@ -1499,7 +2003,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdf { /* Disable interrupts for regular conversions */ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE); - + /* Stop regular conversion */ DFSDM_RegConvStop(hdfsdm_filter); } @@ -1509,7 +2013,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdf /** * @brief This function allows to start regular conversion in DMA mode. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if injected conversion is ongoing. * Please note that data on buffer will contain signed regular conversion * value on 24 most significant bits and corresponding channel on 3 least @@ -1529,42 +2033,42 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *h assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check destination address and length */ - if((pData == NULL) || (Length == 0)) + if ((pData == NULL) || (Length == 0U)) { status = HAL_ERROR; } /* Check that DMA is enabled for regular conversion */ - else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN) + else if ((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN) { status = HAL_ERROR; } /* Check parameters compatibility */ - else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \ - (Length != 1)) + else if ((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ + (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \ + (Length != 1U)) { status = HAL_ERROR; } - else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR)) + else if ((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ + (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR)) { status = HAL_ERROR; } /* Check DFSDM filter state */ - else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) + else if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) { /* Set callbacks on DMA handler */ hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt; hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError; - hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\ + hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ? \ DFSDM_DMARegularHalfConvCplt : NULL; - + /* Start DMA in interrupt mode */ - if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \ - (uint32_t) pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \ + (uint32_t) pData, Length) != HAL_OK) { /* Set DFSDM filter in error state */ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; @@ -1587,7 +2091,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *h /** * @brief This function allows to start regular conversion in DMA mode and to get * only the 16 most significant bits of conversion. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if injected conversion is ongoing. * Please note that data on buffer will contain signed 16 most significant * bits of regular conversion. @@ -1606,42 +2110,42 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check destination address and length */ - if((pData == NULL) || (Length == 0)) + if ((pData == NULL) || (Length == 0U)) { status = HAL_ERROR; } /* Check that DMA is enabled for regular conversion */ - else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN) + else if ((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN) { status = HAL_ERROR; } /* Check parameters compatibility */ - else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \ - (Length != 1)) + else if ((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ + (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \ + (Length != 1U)) { status = HAL_ERROR; } - else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR)) + else if ((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ + (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR)) { status = HAL_ERROR; } /* Check DFSDM filter state */ - else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) + else if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) { /* Set callbacks on DMA handler */ hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt; hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError; - hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\ + hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ? \ DFSDM_DMARegularHalfConvCplt : NULL; - + /* Start DMA in interrupt mode */ - if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2, \ - (uint32_t) pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2U, \ + (uint32_t) pData, Length) != HAL_OK) { /* Set DFSDM filter in error state */ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; @@ -1675,8 +2179,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hd assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { /* Return error status */ status = HAL_ERROR; @@ -1684,7 +2188,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hd else { /* Stop current DMA transfer */ - if(HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK) + if (HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK) { /* Set DFSDM filter in error state */ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; @@ -1709,19 +2213,22 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hd int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { - uint32_t reg = 0; - int32_t value = 0; - + uint32_t reg; + int32_t value; + /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(Channel != NULL); + assert_param(Channel != (void *)0); /* Get value of data register for regular channel */ reg = hdfsdm_filter->Instance->FLTRDATAR; - + /* Extract channel and regular conversion value */ *Channel = (reg & DFSDM_FLTRDATAR_RDATACH); - value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_RDATA_Pos); + /* Regular conversion value is a signed value located on 24 MSB of register */ + /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */ + reg &= DFSDM_FLTRDATAR_RDATA; + value = ((int32_t)reg) / 256; /* return regular conversion value */ return value; @@ -1729,7 +2236,7 @@ int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filte /** * @brief This function allows to start injected conversion in polling mode. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if regular conversion is ongoing. * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status @@ -1742,8 +2249,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfs assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) + if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) { /* Start injected conversion */ DFSDM_InjConvStart(hdfsdm_filter); @@ -1772,8 +2279,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDe assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { /* Return error status */ return HAL_ERROR; @@ -1781,15 +2288,15 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDe else { /* Get timeout */ - tickstart = HAL_GetTick(); + tickstart = HAL_GetTick(); /* Wait end of injected conversions */ - while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF) + while ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF) { /* Check the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Return timeout status */ return HAL_TIMEOUT; @@ -1797,11 +2304,15 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDe } } /* Check if overrun occurs */ - if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF) + if ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF) { /* Update error code and call error callback */ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN; +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->ErrorCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); +#endif /* Clear injected overrun flag */ hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF; @@ -1809,18 +2320,18 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDe /* Update remaining injected conversions */ hdfsdm_filter->InjConvRemaining--; - if(hdfsdm_filter->InjConvRemaining == 0) + if (hdfsdm_filter->InjConvRemaining == 0U) { /* Update DFSDM filter state only if trigger is software */ - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) + if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) { hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \ HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG; } - + /* end of injected sequence, reset the value */ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; + hdfsdm_filter->InjectedChannelsNbr : 1U; } /* Return function status */ @@ -1842,8 +2353,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsd assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { /* Return error status */ status = HAL_ERROR; @@ -1859,7 +2370,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsd /** * @brief This function allows to start injected conversion in interrupt mode. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if regular conversion is ongoing. * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status @@ -1872,12 +2383,12 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *h assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) + if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) { /* Enable interrupts for injected conversions */ hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE); - + /* Start injected conversion */ DFSDM_InjConvStart(hdfsdm_filter); } @@ -1903,8 +2414,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hd assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { /* Return error status */ status = HAL_ERROR; @@ -1913,7 +2424,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hd { /* Disable interrupts for injected conversions */ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE); - + /* Stop injected conversion */ DFSDM_InjConvStop(hdfsdm_filter); } @@ -1923,7 +2434,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hd /** * @brief This function allows to start injected conversion in DMA mode. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if regular conversion is ongoing. * Please note that data on buffer will contain signed injected conversion * value on 24 most significant bits and corresponding channel on 3 least @@ -1943,40 +2454,40 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef * assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check destination address and length */ - if((pData == NULL) || (Length == 0)) + if ((pData == NULL) || (Length == 0U)) { status = HAL_ERROR; } /* Check that DMA is enabled for injected conversion */ - else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN) + else if ((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN) { status = HAL_ERROR; } /* Check parameters compatibility */ - else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \ - (Length > hdfsdm_filter->InjConvRemaining)) + else if ((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \ + (Length > hdfsdm_filter->InjConvRemaining)) { status = HAL_ERROR; } - else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR)) + else if ((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR)) { status = HAL_ERROR; } /* Check DFSDM filter state */ - else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) + else if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) { /* Set callbacks on DMA handler */ hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt; hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError; - hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\ + hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ? \ DFSDM_DMAInjectedHalfConvCplt : NULL; - + /* Start DMA in interrupt mode */ - if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \ - (uint32_t) pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \ + (uint32_t) pData, Length) != HAL_OK) { /* Set DFSDM filter in error state */ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; @@ -1999,7 +2510,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef * /** * @brief This function allows to start injected conversion in DMA mode and to get * only the 16 most significant bits of conversion. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if regular conversion is ongoing. * Please note that data on buffer will contain signed 16 most significant * bits of injected conversion. @@ -2018,40 +2529,40 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDe assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check destination address and length */ - if((pData == NULL) || (Length == 0)) + if ((pData == NULL) || (Length == 0U)) { status = HAL_ERROR; } /* Check that DMA is enabled for injected conversion */ - else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN) + else if ((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN) { status = HAL_ERROR; } /* Check parameters compatibility */ - else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \ - (Length > hdfsdm_filter->InjConvRemaining)) + else if ((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \ + (Length > hdfsdm_filter->InjConvRemaining)) { status = HAL_ERROR; } - else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR)) + else if ((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR)) { status = HAL_ERROR; } /* Check DFSDM filter state */ - else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) + else if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) { /* Set callbacks on DMA handler */ hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt; hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError; - hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\ + hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ? \ DFSDM_DMAInjectedHalfConvCplt : NULL; - + /* Start DMA in interrupt mode */ - if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2, \ - (uint32_t) pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2U, \ + (uint32_t) pData, Length) != HAL_OK) { /* Set DFSDM filter in error state */ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; @@ -2085,8 +2596,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *h assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { /* Return error status */ status = HAL_ERROR; @@ -2094,7 +2605,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *h else { /* Stop current DMA transfer */ - if(HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK) + if (HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK) { /* Set DFSDM filter in error state */ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; @@ -2116,22 +2627,25 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *h * @param Channel Corresponding channel of injected conversion. * @retval Injected conversion value */ -int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, +int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { - uint32_t reg = 0; - int32_t value = 0; - + uint32_t reg; + int32_t value; + /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(Channel != NULL); + assert_param(Channel != (void *)0); /* Get value of data register for injected channel */ reg = hdfsdm_filter->Instance->FLTJDATAR; - + /* Extract channel and injected conversion value */ *Channel = (reg & DFSDM_FLTJDATAR_JDATACH); - value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_JDATA_Pos); + /* Injected conversion value is a signed value located on 24 MSB of register */ + /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */ + reg &= DFSDM_FLTJDATAR_JDATA; + value = ((int32_t)reg) / 256; /* return regular conversion value */ return value; @@ -2156,10 +2670,10 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfs assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold)); assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal)); assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal)); - + /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) + if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) { /* Return error status */ status = HAL_ERROR; @@ -2173,10 +2687,10 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfs /* Set thresholds and break signals */ hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH); hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_AWHT_Pos) | \ - awdParam->HighBreakSignal); + awdParam->HighBreakSignal); hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL); hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_AWLT_Pos) | \ - awdParam->LowBreakSignal); + awdParam->LowBreakSignal); /* Set channels and interrupt for analog watchdog */ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH); @@ -2198,10 +2712,10 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_ /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - + /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) + if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) { /* Return error status */ status = HAL_ERROR; @@ -2213,7 +2727,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_ /* Clear all analog watchdog flags */ hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF); - + /* Reset thresholds and break signals */ hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH); hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL); @@ -2240,10 +2754,10 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_fi /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel)); - + /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) + if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) { /* Return error status */ status = HAL_ERROR; @@ -2252,7 +2766,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_fi { /* Set channels for extreme detector */ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH); - hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos); + hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos); } /* Return function status */ return status; @@ -2271,10 +2785,10 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_fil /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - + /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) + if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) { /* Return error status */ status = HAL_ERROR; @@ -2286,7 +2800,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_fil /* Clear extreme detector values */ reg1 = hdfsdm_filter->Instance->FLTEXMAX; - reg2 = hdfsdm_filter->Instance->FLTEXMIN; + reg2 = hdfsdm_filter->Instance->FLTEXMIN; UNUSED(reg1); /* To avoid GCC warning */ UNUSED(reg2); /* To avoid GCC warning */ } @@ -2304,19 +2818,22 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_fil int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { - uint32_t reg = 0; - int32_t value = 0; - + uint32_t reg; + int32_t value; + /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(Channel != NULL); + assert_param(Channel != (void *)0); /* Get value of extreme detector maximum register */ reg = hdfsdm_filter->Instance->FLTEXMAX; - + /* Extract channel and extreme detector maximum value */ *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH); - value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_EXMAX_Pos); + /* Extreme detector maximum value is a signed value located on 24 MSB of register */ + /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */ + reg &= DFSDM_FLTEXMAX_EXMAX; + value = ((int32_t)reg) / 256; /* return extreme detector maximum value */ return value; @@ -2332,19 +2849,22 @@ int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { - uint32_t reg = 0; - int32_t value = 0; - + uint32_t reg; + int32_t value; + /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(Channel != NULL); + assert_param(Channel != (void *)0); /* Get value of extreme detector minimum register */ reg = hdfsdm_filter->Instance->FLTEXMIN; - + /* Extract channel and extreme detector minimum value */ *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH); - value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_EXMIN_Pos); + /* Extreme detector minimum value is a signed value located on 24 MSB of register */ + /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */ + reg &= DFSDM_FLTEXMIN_EXMIN; + value = ((int32_t)reg) / 256; /* return extreme detector minimum value */ return value; @@ -2358,15 +2878,15 @@ int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter */ uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { - uint32_t reg = 0; - uint32_t value = 0; - + uint32_t reg; + uint32_t value; + /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Get value of conversion timer register */ reg = hdfsdm_filter->Instance->FLTCNVTIMR; - + /* Extract conversion time value */ value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_CNVCNT_Pos); @@ -2381,9 +2901,13 @@ uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_fil */ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { + /* Get FTLISR and FLTCR2 register values */ + const uint32_t temp_fltisr = hdfsdm_filter->Instance->FLTISR; + const uint32_t temp_fltcr2 = hdfsdm_filter->Instance->FLTCR2; + /* Check if overrun occurs during regular conversion */ - if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_ROVRIE) != 0)) + if (((temp_fltisr & DFSDM_FLTISR_ROVRF) != 0U) && \ + ((temp_fltcr2 & DFSDM_FLTCR2_ROVRIE) != 0U)) { /* Clear regular overrun flag */ hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF; @@ -2392,11 +2916,15 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN; /* Call error callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->ErrorCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); +#endif } /* Check if overrun occurs during injected conversion */ - else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JOVRIE) != 0)) + else if (((temp_fltisr & DFSDM_FLTISR_JOVRF) != 0U) && \ + ((temp_fltcr2 & DFSDM_FLTCR2_JOVRIE) != 0U)) { /* Clear injected overrun flag */ hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF; @@ -2405,18 +2933,26 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN; /* Call error callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->ErrorCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); +#endif } /* Check if end of regular conversion */ - else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_REOCIE) != 0)) + else if (((temp_fltisr & DFSDM_FLTISR_REOCF) != 0U) && \ + ((temp_fltcr2 & DFSDM_FLTCR2_REOCIE) != 0U)) { /* Call regular conversion complete callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter); +#endif /* End of conversion if mode is not continuous and software trigger */ - if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) + if ((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ + (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) { /* Disable interrupts for regular conversions */ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE); @@ -2427,18 +2963,22 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) } } /* Check if end of injected conversion */ - else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JEOCIE) != 0)) + else if (((temp_fltisr & DFSDM_FLTISR_JEOCF) != 0U) && \ + ((temp_fltcr2 & DFSDM_FLTCR2_JEOCIE) != 0U)) { /* Call injected conversion complete callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter); +#endif /* Update remaining injected conversions */ hdfsdm_filter->InjConvRemaining--; - if(hdfsdm_filter->InjConvRemaining == 0) + if (hdfsdm_filter->InjConvRemaining == 0U) { /* End of conversion if trigger is software */ - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) + if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) { /* Disable interrupts for injected conversions */ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE); @@ -2449,60 +2989,68 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) } /* end of injected sequence, reset the value */ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; + hdfsdm_filter->InjectedChannelsNbr : 1U; } } /* Check if analog watchdog occurs */ - else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_AWDF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_AWDIE) != 0)) + else if (((temp_fltisr & DFSDM_FLTISR_AWDF) != 0U) && \ + ((temp_fltcr2 & DFSDM_FLTCR2_AWDIE) != 0U)) { - uint32_t reg = 0; - uint32_t threshold = 0; + uint32_t reg; + uint32_t threshold; uint32_t channel = 0; - + /* Get channel and threshold */ reg = hdfsdm_filter->Instance->FLTAWSR; - threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD; - if(threshold == DFSDM_AWD_HIGH_THRESHOLD) + threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0U) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD; + if (threshold == DFSDM_AWD_HIGH_THRESHOLD) { reg = reg >> DFSDM_FLTAWSR_AWHTF_Pos; } - while((reg & 1) == 0) + while (((reg & 1U) == 0U) && (channel < (DFSDM1_CHANNEL_NUMBER - 1U))) { channel++; reg = reg >> 1; } /* Clear analog watchdog flag */ hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \ - (1 << (DFSDM_FLTAWSR_AWHTF_Pos + channel)) : \ - (1 << channel); + (1UL << (DFSDM_FLTAWSR_AWHTF_Pos + channel)) : \ + (1UL << channel); /* Call analog watchdog callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->AwdCallback(hdfsdm_filter, channel, threshold); +#else HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold); +#endif } /* Check if clock absence occurs */ - else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \ - ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0)) + else if ((hdfsdm_filter->Instance == DFSDM1_Filter0) && \ + ((temp_fltisr & DFSDM_FLTISR_CKABF) != 0U) && \ + ((temp_fltcr2 & DFSDM_FLTCR2_CKABIE) != 0U)) { - uint32_t reg = 0; + uint32_t reg; uint32_t channel = 0; - + reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos); - while(channel < DFSDM1_CHANNEL_NUMBER) + while (channel < DFSDM1_CHANNEL_NUMBER) { /* Check if flag is set and corresponding channel is enabled */ - if(((reg & 1) != 0) && (a_dfsdm1ChannelHandle[channel] != NULL)) + if (((reg & 1U) != 0U) && (a_dfsdm1ChannelHandle[channel] != NULL)) { /* Check clock absence has been enabled for this channel */ - if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0) + if ((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0U) { /* Clear clock absence flag */ - hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); + hdfsdm_filter->Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Call clock absence callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + a_dfsdm1ChannelHandle[channel]->CkabCallback(a_dfsdm1ChannelHandle[channel]); +#else HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]); +#endif } } channel++; @@ -2510,31 +3058,35 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) } } /* Check if short circuit detection occurs */ - else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \ - ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0)) + else if ((hdfsdm_filter->Instance == DFSDM1_Filter0) && \ + ((temp_fltisr & DFSDM_FLTISR_SCDF) != 0U) && \ + ((temp_fltcr2 & DFSDM_FLTCR2_SCDIE) != 0U)) { - uint32_t reg = 0; + uint32_t reg; uint32_t channel = 0; - + /* Get channel */ reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos); - while((reg & 1) == 0) + while (((reg & 1U) == 0U) && (channel < (DFSDM1_CHANNEL_NUMBER - 1U))) { channel++; reg = reg >> 1; } - + /* Clear short circuit detection flag */ - hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); + hdfsdm_filter->Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); /* Call short circuit detection callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + a_dfsdm1ChannelHandle[channel]->ScdCallback(a_dfsdm1ChannelHandle[channel]); +#else HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]); +#endif } } /** - * @brief Regular conversion complete callback. + * @brief Regular conversion complete callback. * @note In interrupt mode, user has to read conversion value in this function * using HAL_DFSDM_FilterGetRegularValue. * @param hdfsdm_filter DFSDM filter handle. @@ -2544,14 +3096,14 @@ __weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfs { /* Prevent unused argument(s) compilation warning */ UNUSED(hdfsdm_filter); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DFSDM_FilterRegConvCpltCallback could be implemented in the user file. */ } /** - * @brief Half regular conversion complete callback. + * @brief Half regular conversion complete callback. * @param hdfsdm_filter DFSDM filter handle. * @retval None */ @@ -2559,14 +3111,14 @@ __weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef * { /* Prevent unused argument(s) compilation warning */ UNUSED(hdfsdm_filter); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DFSDM_FilterRegConvHalfCpltCallback could be implemented in the user file. */ } /** - * @brief Injected conversion complete callback. + * @brief Injected conversion complete callback. * @note In interrupt mode, user has to read conversion value in this function * using HAL_DFSDM_FilterGetInjectedValue. * @param hdfsdm_filter DFSDM filter handle. @@ -2576,14 +3128,14 @@ __weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfs { /* Prevent unused argument(s) compilation warning */ UNUSED(hdfsdm_filter); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DFSDM_FilterInjConvCpltCallback could be implemented in the user file. */ } /** - * @brief Half injected conversion complete callback. + * @brief Half injected conversion complete callback. * @param hdfsdm_filter DFSDM filter handle. * @retval None */ @@ -2591,14 +3143,14 @@ __weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef * { /* Prevent unused argument(s) compilation warning */ UNUSED(hdfsdm_filter); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DFSDM_FilterInjConvHalfCpltCallback could be implemented in the user file. */ } /** - * @brief Filter analog watchdog callback. + * @brief Filter analog watchdog callback. * @param hdfsdm_filter DFSDM filter handle. * @param Channel Corresponding channel. * @param Threshold Low or high threshold has been reached. @@ -2611,14 +3163,14 @@ __weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filte UNUSED(hdfsdm_filter); UNUSED(Channel); UNUSED(Threshold); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DFSDM_FilterAwdCallback could be implemented in the user file. */ } /** - * @brief Error callback. + * @brief Error callback. * @param hdfsdm_filter DFSDM filter handle. * @retval None */ @@ -2626,7 +3178,7 @@ __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_fil { /* Prevent unused argument(s) compilation warning */ UNUSED(hdfsdm_filter); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DFSDM_FilterErrorCallback could be implemented in the user file. */ @@ -2686,76 +3238,96 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) */ /** - * @brief DMA half transfer complete callback for regular conversion. + * @brief DMA half transfer complete callback for regular conversion. * @param hdma DMA handle. * @retval None */ -static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma) +static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma) { /* Get DFSDM filter handle */ - DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; + DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Call regular half conversion complete callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->RegConvHalfCpltCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter); +#endif } /** - * @brief DMA transfer complete callback for regular conversion. + * @brief DMA transfer complete callback for regular conversion. * @param hdma DMA handle. * @retval None */ -static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma) +static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma) { /* Get DFSDM filter handle */ - DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; + DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Call regular conversion complete callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter); +#endif } /** - * @brief DMA half transfer complete callback for injected conversion. + * @brief DMA half transfer complete callback for injected conversion. * @param hdma DMA handle. * @retval None */ -static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma) +static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma) { /* Get DFSDM filter handle */ - DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; + DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Call injected half conversion complete callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->InjConvHalfCpltCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter); +#endif } /** - * @brief DMA transfer complete callback for injected conversion. + * @brief DMA transfer complete callback for injected conversion. * @param hdma DMA handle. * @retval None */ -static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma) +static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma) { /* Get DFSDM filter handle */ - DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; + DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Call injected conversion complete callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter); +#endif } /** - * @brief DMA error callback. + * @brief DMA error callback. * @param hdma DMA handle. * @retval None */ -static void DFSDM_DMAError(DMA_HandleTypeDef *hdma) +static void DFSDM_DMAError(DMA_HandleTypeDef *hdma) { /* Get DFSDM filter handle */ - DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; + DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Update error code */ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA; /* Call error callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->ErrorCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); +#endif } /** @@ -2767,16 +3339,16 @@ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels) { uint32_t nbChannels = 0; uint32_t tmp; - + /* Get the number of channels from bitfield */ - tmp = (uint32_t) (Channels & DFSDM_LSB_MASK); - while(tmp != 0) + tmp = (uint32_t)(Channels & DFSDM_LSB_MASK); + while (tmp != 0U) { - if((tmp & 1) != 0) + if ((tmp & 1U) != 0U) { nbChannels++; } - tmp = (uint32_t) (tmp >> 1); + tmp = (uint32_t)(tmp >> 1); } return nbChannels; } @@ -2786,47 +3358,51 @@ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels) * @param Instance DFSDM channel instance. * @retval Channel number. */ -static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance) +static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance) { - uint32_t channel = 0xFF; - + uint32_t channel; + /* Get channel from instance */ - if(Instance == DFSDM1_Channel0) + if (Instance == DFSDM1_Channel0) { channel = 0; } - else if(Instance == DFSDM1_Channel1) + else if (Instance == DFSDM1_Channel1) { channel = 1; } - else if(Instance == DFSDM1_Channel2) + else if (Instance == DFSDM1_Channel2) { channel = 2; } - else if(Instance == DFSDM1_Channel3) + else if (Instance == DFSDM1_Channel3) { channel = 3; } #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ defined(STM32L496xx) || defined(STM32L4A6xx) || \ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - else if(Instance == DFSDM1_Channel4) + else if (Instance == DFSDM1_Channel4) { channel = 4; } - else if(Instance == DFSDM1_Channel5) + else if (Instance == DFSDM1_Channel5) { channel = 5; } - else if(Instance == DFSDM1_Channel6) + else if (Instance == DFSDM1_Channel6) { channel = 6; } - else if(Instance == DFSDM1_Channel7) + else if (Instance == DFSDM1_Channel7) { channel = 7; } #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + else + { + channel = 0; + } return channel; } @@ -2836,10 +3412,10 @@ static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance) * @param hdfsdm_filter DFSDM filter handle. * @retval None */ -static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) +static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { /* Check regular trigger */ - if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) + if (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) { /* Software start of regular conversion */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART; @@ -2848,28 +3424,28 @@ static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) { /* Disable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); - + /* Set RSYNC bit in DFSDM_FLTCR1 register */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC; /* Enable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; - + /* If injected conversion was in progress, restart it */ - if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) + if (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) { - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) + if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) { hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART; } /* Update remaining injected conversions */ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; + hdfsdm_filter->InjectedChannelsNbr : 1U; } } /* Update DFSDM filter state */ hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \ - HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ; + HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ; } /** @@ -2877,35 +3453,35 @@ static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) * @param hdfsdm_filter DFSDM filter handle. * @retval None */ -static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) +static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { /* Disable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); /* If regular trigger was synchronous, reset RSYNC bit in DFSDM_FLTCR1 register */ - if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER) + if (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER) { hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC); } /* Enable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; - + /* If injected conversion was in progress, restart it */ - if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) + if (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) { - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) + if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) { hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART; } /* Update remaining injected conversions */ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; + hdfsdm_filter->InjectedChannelsNbr : 1U; } - + /* Update DFSDM filter state */ hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \ - HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ; + HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ; } /** @@ -2913,10 +3489,10 @@ static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) * @param hdfsdm_filter DFSDM filter handle. * @retval None */ -static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) +static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { /* Check injected trigger */ - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) + if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) { /* Software start of injected conversion */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART; @@ -2925,8 +3501,8 @@ static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) { /* Disable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); - - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER) + + if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER) { /* Set JSYNC bit in DFSDM_FLTCR1 register */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSYNC; @@ -2936,13 +3512,13 @@ static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) /* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */ hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge; } - + /* Enable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; /* If regular conversion was in progress, restart it */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \ - (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) + if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \ + (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) { hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART; } @@ -2957,39 +3533,43 @@ static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) * @param hdfsdm_filter DFSDM filter handle. * @retval None */ -static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) +static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { /* Disable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); /* If injected trigger was synchronous, reset JSYNC bit in DFSDM_FLTCR1 register */ - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER) + if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER) { hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC); } - else if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER) + else if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER) { /* Reset JEXTEN[1:0] bits in DFSDM_FLTCR1 register */ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN); } + else + { + /* Nothing to do */ + } /* Enable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; - + /* If regular conversion was in progress, restart it */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \ - (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) + if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \ + (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) { hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART; } /* Update remaining injected conversions */ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; + hdfsdm_filter->InjectedChannelsNbr : 1U; /* Update DFSDM filter state */ hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \ - HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG; + HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG; } /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm_ex.c index 5539eb14f4..20bff16318 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm_ex.c @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32l4xx_hal_dfsdm_ex.c * @author MCD Application Team - * @brief DFSDM Extended HAL module driver. + * @brief DFSDM Extended HAL module driver. * This file provides firmware functions to manage the following * functionality of the DFSDM Peripheral Controller: * + Set and get pulses skipping on channel. @@ -35,7 +35,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -88,12 +88,12 @@ HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue) { HAL_StatusTypeDef status = HAL_OK; - + /* Check pulses value */ assert_param(IS_DFSDM_CHANNEL_SKIPPING_VALUE(PulsesValue)); - + /* Check DFSDM channel state */ - if(hdfsdm_channel->State == HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State == HAL_DFSDM_CHANNEL_STATE_READY) { /* Set new value of pulses skipping */ hdfsdm_channel->Instance->CHDLYR = (PulsesValue & DFSDM_CHDLYR_PLSSKP); @@ -114,9 +114,9 @@ HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeD HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue) { HAL_StatusTypeDef status = HAL_OK; - + /* Check DFSDM channel state */ - if(hdfsdm_channel->State == HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State == HAL_DFSDM_CHANNEL_STATE_READY) { /* Get value of remaining pulses to be skipped */ *PulsesValue = (hdfsdm_channel->Instance->CHDLYR & DFSDM_CHDLYR_PLSSKP); diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c index d71b37c743..1179234ee6 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c @@ -66,7 +66,7 @@ (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. - (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. [..] (@) You can refer to the DMA HAL driver header file for more useful macros @@ -162,13 +162,13 @@ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); /** * @brief Initialize the DMA according to the specified * parameters in the DMA_InitTypeDef and initialize the associated handle. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { - uint32_t tmp = 0; + uint32_t tmp; /* Check the DMA handle allocation */ if(hdma == NULL) @@ -241,7 +241,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - if(((hdma->Init.Request > 0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + if(((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask @@ -271,18 +271,18 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) if (DMA1 == hdma->DmaBaseAddress) { /* Reset request selection for DMA1 Channelx */ - DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex); + DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU)); /* Configure request selection for DMA1 Channelx */ - DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex)); + DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU)); } else /* DMA2 */ { /* Reset request selection for DMA2 Channelx */ - DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex); + DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU)); /* Configure request selection for DMA2 Channelx */ - DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex)); + DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU)); } } @@ -290,12 +290,6 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */ /* STM32L496xx || STM32L4A6xx */ - /* Clean callbacks */ - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; @@ -310,7 +304,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /** * @brief DeInitialize the DMA peripheral. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ @@ -347,7 +341,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) hdma->Instance->CCR = 0; /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex)); + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); #if !defined (DMAMUX1) @@ -355,12 +349,12 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) if (DMA1 == hdma->DmaBaseAddress) { /* DMA1 */ - DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex)); + DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU)); } else { /* DMA2 */ - DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex)); + DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU)); } #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */ /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */ @@ -380,7 +374,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; /* Reset Request generator parameters if any */ - if(((hdma->Init.Request > 0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + if(((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask @@ -400,6 +394,12 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) #endif /* DMAMUX1 */ + /* Clean callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; @@ -437,11 +437,11 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) /** * @brief Start the DMA Transfer. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) @@ -480,11 +480,11 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui /** * @brief Start the DMA Transfer with interrupt enabled. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) @@ -556,7 +556,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, /** * @brief Abort the DMA Transfer. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ @@ -582,7 +582,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) __HAL_DMA_DISABLE(hdma); /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); #if defined(DMAMUX1) /* Clear the DMAMUX synchro overrun flag */ @@ -611,7 +611,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) /** * @brief Aborts the DMA Transfer in Interrupt mode. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ @@ -639,7 +639,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; @@ -656,7 +656,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) #else /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); #endif /* DMAMUX1 */ /* Change the DMA state */ @@ -676,16 +676,16 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) /** * @brief Polling for transfer complete. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param CompleteLevel: Specifies the DMA level complete. - * @param Timeout: Timeout duration. + * @param CompleteLevel Specifies the DMA level complete. + * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) { uint32_t temp; - uint32_t tickstart = 0; + uint32_t tickstart; if(HAL_DMA_STATE_BUSY != hdma->State) { @@ -696,7 +696,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level } /* Polling mode not supported in circular mode */ - if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) + if (0U != (hdma->Instance->CCR & DMA_CCR_CIRC)) { hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; return HAL_ERROR; @@ -706,25 +706,25 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level if (HAL_DMA_FULL_TRANSFER == CompleteLevel) { /* Transfer Complete flag */ - temp = DMA_FLAG_TC1 << hdma->ChannelIndex; + temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU); } else { /* Half Transfer Complete flag */ - temp = DMA_FLAG_HT1 << hdma->ChannelIndex; + temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU); } /* Get tick */ tickstart = HAL_GetTick(); - while(RESET == (hdma->DmaBaseAddress->ISR & temp)) + while(0U == (hdma->DmaBaseAddress->ISR & temp)) { - if((RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))) + if((0U != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1cU))))) { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; @@ -740,7 +740,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; @@ -788,7 +788,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level if(HAL_DMA_FULL_TRANSFER == CompleteLevel) { /* Clear the transfer complete flag */ - hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << hdma->ChannelIndex); + hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1cU)); /* The selected Channelx EN bit is cleared (DMA is disabled and all transfers are complete) */ @@ -797,7 +797,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level else { /* Clear the half transfer complete flag */ - hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << hdma->ChannelIndex); + hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU)); } /* Process unlocked */ @@ -808,7 +808,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level /** * @brief Handle DMA interrupt request. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ @@ -818,16 +818,16 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) uint32_t source_it = hdma->Instance->CCR; /* Half Transfer Complete Interrupt management ******************************/ - if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT))) + if ((0U != (flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_HT))) { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); } /* Clear the half transfer complete flag */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_HTIF1 << hdma->ChannelIndex); + hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1cU); /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ @@ -840,9 +840,9 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) } /* Transfer Complete Interrupt management ***********************************/ - else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC))) + else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TC))) { - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); @@ -851,7 +851,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) hdma->State = HAL_DMA_STATE_READY; } /* Clear the transfer complete flag */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << hdma->ChannelIndex); + hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1cU)); /* Process Unlocked */ __HAL_UNLOCK(hdma); @@ -864,7 +864,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) } /* Transfer Error Interrupt management **************************************/ - else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) + else if ((0U != (flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TE))) { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ @@ -872,7 +872,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; @@ -889,16 +889,20 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) hdma->XferErrorCallback(hdma); } } + else + { + /* Nothing To Do */ + } return; } /** * @brief Register callbacks - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param CallbackID: User Callback identifer + * @param CallbackID User Callback identifer * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @param pCallback: pointer to private callbacsk function which has pointer to + * @param pCallback pointer to private callbacsk function which has pointer to * a DMA_HandleTypeDef structure as parameter. * @retval HAL status */ @@ -947,9 +951,9 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call /** * @brief UnRegister callbacks - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param CallbackID: User Callback identifer + * @param CallbackID User Callback identifer * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @retval HAL status */ @@ -1027,7 +1031,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca /** * @brief Return the DMA hande state. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL state */ @@ -1062,11 +1066,11 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) /** * @brief Sets the DMA Transfer parameter. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) @@ -1083,12 +1087,12 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t #endif /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; - /* Peripheral to Memory */ + /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) { /* Configure DMA Channel destination address */ @@ -1097,7 +1101,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; } - /* Memory to Peripheral */ + /* Peripheral to Memory */ else { /* Configure DMA Channel source address */ @@ -1112,13 +1116,13 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t /** * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { - uint32_t channel_number = 0; + uint32_t channel_number; DMAMUX_Channel_TypeDef *DMAMUX1_ChannelBase; /* check if instance is not outside the DMA channel range */ @@ -1132,15 +1136,15 @@ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) /* DMA2 */ DMAMUX1_ChannelBase = DMAMUX1_Channel7; } - channel_number = (((uint32_t)hdma->Instance & 0xFF) - 8) / 20; - hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_ChannelBase + (hdma->ChannelIndex >> 2) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0)); + channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; + hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_ChannelBase + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0))); hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; - hdma->DMAmuxChannelStatusMask = 1U << channel_number; + hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1cU); } /** * @brief Updates the DMA handle with the DMAMUX request generator params - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ @@ -1154,7 +1158,9 @@ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; - hdma->DMAmuxRequestGenStatusMask = 1U << (request - 1U); + /* here "Request" is either DMA_REQUEST_GENERATOR0 to 4, i.e. <= 4*/ + hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U); + } #endif /* DMAMUX1 */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c index a7e3f2f4ce..b12985c4e5 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c @@ -3,95 +3,148 @@ * @file stm32l4xx_hal_dma2d.c * @author MCD Application Team * @brief DMA2D HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the DMA2D peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State and Errors functions * - @verbatim + @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] - (#) Program the required configuration through the following parameters: - the transfer mode, the output color mode and the output offset using + (#) Program the required configuration through the following parameters: + the transfer mode, the output color mode and the output offset using HAL_DMA2D_Init() function. - (#) Program the required configuration through the following parameters: + (#) Program the required configuration through the following parameters: the input color mode, the input color, the input alpha value, the alpha mode, - the red/blue swap mode, the inverted alpha mode and the input offset using + the red/blue swap mode, the inverted alpha mode and the input offset using HAL_DMA2D_ConfigLayer() function for foreground or/and background layer. - + *** Polling mode IO operation *** - ================================= - [..] - (#) Configure pdata parameter (explained hereafter), destination and data length - and enable the transfer using HAL_DMA2D_Start(). + ================================= + [..] + (#) Configure pdata parameter (explained hereafter), destination and data length + and enable the transfer using HAL_DMA2D_Start(). (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage user can specify the value of timeout according to his end application. - - *** Interrupt mode IO operation *** + + *** Interrupt mode IO operation *** =================================== - [..] - (#) Configure pdata parameter, destination and data length and enable - the transfer using HAL_DMA2D_Start_IT(). + [..] + (#) Configure pdata parameter, destination and data length and enable + the transfer using HAL_DMA2D_Start_IT(). (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine. - (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can - add his own function by customization of function pointer XferCpltCallback (member - of DMA2D handle structure). - (#) In case of error, the HAL_DMA2D_IRQHandler() function calls the callback - XferErrorCallback. + (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback (member + of DMA2D handle structure). + (#) In case of error, the HAL_DMA2D_IRQHandler() function calls the callback + XferErrorCallback. -@- In Register-to-Memory transfer mode, pdata parameter is the register color, in Memory-to-memory or Memory-to-Memory with pixel format conversion pdata is the source address. - -@- Configure the foreground source address, the background source address, - the destination and data length then Enable the transfer using + -@- Configure the foreground source address, the background source address, + the destination and data length then Enable the transfer using HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT() in interrupt mode. - + -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions are used if the memory to memory with blending transfer mode is selected. - + (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode. (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent(). - - (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two + + (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime() and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or - HAL_DMA2D_DisableDeadTime(). - + HAL_DMA2D_DisableDeadTime(). + (#) The transfer can be suspended, resumed and aborted using the following functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort(). - + (#) The CLUT loading can be suspended, resumed and aborted using the following - functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(), - HAL_DMA2D_CLUTLoading_Abort(). - - (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState(). - - (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError(). + functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(), + HAL_DMA2D_CLUTLoading_Abort(). + + (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState(). + + (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError(). *** DMA2D HAL driver macros list *** - ============================================= + ============================================= [..] Below the list of most used macros in DMA2D HAL driver : - + (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral. (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags. (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags. (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts. (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts. - (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not. - - [..] + (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not. + + *** Callback registration *** + =================================== + [..] + (#) The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use function @ref HAL_DMA2D_RegisterCallback() to register a user callback. + + (#) Function @ref HAL_DMA2D_RegisterCallback() allows to register following callbacks: + (+) XferCpltCallback : callback for transfer complete. + (+) XferErrorCallback : callback for transfer error. + (+) LineEventCallback : callback for line event. + (+) CLUTLoadingCpltCallback : callback for CLUT loading completion. + (+) MspInitCallback : DMA2D MspInit. + (+) MspDeInitCallback : DMA2D MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) XferCpltCallback : callback for transfer complete. + (+) XferErrorCallback : callback for transfer error. + (+) LineEventCallback : callback for line event. + (+) CLUTLoadingCpltCallback : callback for CLUT loading completion. + (+) MspInitCallback : DMA2D MspInit. + (+) MspDeInitCallback : DMA2D MspDeInit. + + (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions: + examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback() + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init + and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand) + If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + Exception as well for Transfer Completion and Transfer Error callbacks that are not defined + as weak (surcharged) functions. They must be defined by the user to be resorted to. + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_DMA2D_RegisterCallback before calling @ref HAL_DMA2D_DeInit + or @ref HAL_DMA2D_Init function. + + When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + [..] (@) You can refer to the DMA2D HAL driver header file for more useful macros - + @endverbatim ****************************************************************************** * @attention @@ -121,15 +174,13 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" #ifdef HAL_DMA2D_MODULE_ENABLED - -#if defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined (DMA2D) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -145,42 +196,12 @@ /** @defgroup DMA2D_Private_Constants DMA2D Private Constants * @{ */ - -/** @defgroup DMA2D_TimeOut DMA2D Time Out - * @{ - */ -#define DMA2D_TIMEOUT_ABORT ((uint32_t)1000) /*!< 1s */ -#define DMA2D_TIMEOUT_SUSPEND ((uint32_t)1000) /*!< 1s */ -/** - * @} - */ -/** @defgroup DMA2D_Shifts DMA2D Shifts +/** @defgroup DMA2D_TimeOut DMA2D Time Out * @{ - */ -#define DMA2D_POSITION_FGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS) /*!< Required left shift to set foreground CLUT size */ -#define DMA2D_POSITION_BGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS) /*!< Required left shift to set background CLUT size */ - -#define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM) /*!< Required left shift to set foreground CLUT color mode */ -#define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM) /*!< Required left shift to set background CLUT color mode */ - -#define DMA2D_POSITION_OPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_OPFCCR_AI) /*!< Required left shift to set output alpha inversion */ -#define DMA2D_POSITION_FGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AI) /*!< Required left shift to set foreground alpha inversion */ -#define DMA2D_POSITION_BGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AI) /*!< Required left shift to set background alpha inversion */ - -#define DMA2D_POSITION_OPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_OPFCCR_RBS) /*!< Required left shift to set output Red/Blue swap */ -#define DMA2D_POSITION_FGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_RBS) /*!< Required left shift to set foreground Red/Blue swap */ -#define DMA2D_POSITION_BGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_RBS) /*!< Required left shift to set background Red/Blue swap */ - -#define DMA2D_POSITION_AMTCR_DT (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT) /*!< Required left shift to set deadtime value */ - -#define DMA2D_POSITION_FGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM) /*!< Required left shift to set foreground alpha mode */ -#define DMA2D_POSITION_BGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM) /*!< Required left shift to set background alpha mode */ - -#define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA) /*!< Required left shift to set foreground alpha value */ -#define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA) /*!< Required left shift to set background alpha value */ - -#define DMA2D_POSITION_NLR_PL (uint32_t)POSITION_VAL(DMA2D_NLR_PL) /*!< Required left shift to set pixels per lines value */ + */ +#define DMA2D_TIMEOUT_ABORT (1000U) /*!< 1s */ +#define DMA2D_TIMEOUT_SUSPEND (1000U) /*!< 1s */ /** * @} */ @@ -210,27 +231,27 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ /** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and Configuration functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the DMA2D - (+) De-initialize the DMA2D + (+) De-initialize the DMA2D @endverbatim * @{ */ - + /** * @brief Initialize the DMA2D according to the specified * parameters in the DMA2D_InitTypeDef and create the associated handle. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) -{ +{ /* Check the DMA2D peripheral state */ if(hdma2d == NULL) { @@ -242,11 +263,30 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode)); assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode)); assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset)); -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->Init.AlphaInverted)); + assert_param(IS_DMA2D_RB_SWAP(hdma2d->Init.RedBlueSwap)); +#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) assert_param(IS_DMA2D_LOM_MODE(hdma2d->Init.LineOffsetMode)); +#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ +#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) assert_param(IS_DMA2D_BYTES_SWAP(hdma2d->Init.BytesSwap)); -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ + +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) + if (hdma2d->State == HAL_DMA2D_STATE_RESET) + { + /* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */ + hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback; + hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback; + if(hdma2d->MspInitCallback == NULL) + { + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; + } + /* Init the low level hardware */ + hdma2d->MspInitCallback(hdma2d); + } +#else if(hdma2d->State == HAL_DMA2D_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -254,30 +294,30 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) /* Init the low level hardware */ HAL_DMA2D_MspInit(hdma2d); } - +#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ + /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; + hdma2d->State = HAL_DMA2D_STATE_BUSY; /* DMA2D CR register configuration -------------------------------------------*/ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE | DMA2D_CR_LOM, hdma2d->Init.Mode | hdma2d->Init.LineOffsetMode); #else MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode); -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ /* DMA2D OPFCCR register configuration ---------------------------------------*/ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB, hdma2d->Init.ColorMode | hdma2d->Init.BytesSwap); #else MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode); -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ + + /* DMA2D OOR register configuration ------------------------------------------*/ + MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset); + /* DMA2D OPFCCR AI and RBS fields setting (Output Alpha Inversion)*/ + MODIFY_REG(hdma2d->Instance->OPFCCR,(DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos))); - /* DMA2D OOR register configuration ------------------------------------------*/ - MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset); - - /* DMA2D OPFCCR RBS and AI fields setting */ - MODIFY_REG(hdma2d->Instance->OPFCCR, (DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), \ - ((hdma2d->Init.AlphaInverted << DMA2D_POSITION_OPFCCR_AI)|(hdma2d->Init.RedBlueSwap << DMA2D_POSITION_OPFCCR_RBS))); /* Update error code */ hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; @@ -291,20 +331,20 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) /** * @brief Deinitializes the DMA2D peripheral registers to their default reset * values. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) { - + /* Check the DMA2D peripheral state */ if(hdma2d == NULL) { return HAL_ERROR; } - + /* Before aborting any DMA2D transfer or CLUT loading, check first whether or not DMA2D clock is enabled */ if (__HAL_RCC_DMA2D_IS_CLK_ENABLED()) @@ -314,7 +354,7 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) { if (HAL_DMA2D_Abort(hdma2d) != HAL_OK) { - /* Issue when aborting DMA2D transfer */ + /* Issue when aborting DMA2D transfer */ return HAL_ERROR; } } @@ -322,10 +362,10 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) { /* Abort background CLUT loading if any */ if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START) - { - if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0) != HAL_OK) + { + if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK) { - /* Issue when aborting background CLUT loading */ + /* Issue when aborting background CLUT loading */ return HAL_ERROR; } } @@ -334,43 +374,55 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) /* Abort foreground CLUT loading if any */ if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START) { - if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1) != HAL_OK) + if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK) { - /* Issue when aborting foreground CLUT loading */ + /* Issue when aborting foreground CLUT loading */ return HAL_ERROR; - } + } } } } } - + /* Reset DMA2D control registers*/ - hdma2d->Instance->CR = 0; - hdma2d->Instance->IFCR = 0x3F; - hdma2d->Instance->FGOR = 0; - hdma2d->Instance->BGOR = 0; - hdma2d->Instance->FGPFCCR = 0; - hdma2d->Instance->BGPFCCR = 0; - hdma2d->Instance->OPFCCR = 0; + hdma2d->Instance->CR = 0U; + hdma2d->Instance->IFCR = 0x3FU; + hdma2d->Instance->FGOR = 0U; + hdma2d->Instance->BGOR = 0U; + hdma2d->Instance->FGPFCCR = 0U; + hdma2d->Instance->BGPFCCR = 0U; + hdma2d->Instance->OPFCCR = 0U; + +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) + + if(hdma2d->MspDeInitCallback == NULL) + { + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; + } + + /* DeInit the low level hardware */ + hdma2d->MspDeInitCallback(hdma2d); +#else /* Carry on with de-initialization of low level hardware */ HAL_DMA2D_MspDeInit(hdma2d); - +#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ + /* Update error code */ hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; - + /* Initialize the DMA2D state*/ hdma2d->State = HAL_DMA2D_STATE_RESET; - + /* Release Lock */ __HAL_UNLOCK(hdma2d); - + return HAL_OK; } /** * @brief Initializes the DMA2D MSP. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ @@ -386,7 +438,7 @@ __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) /** * @brief DeInitializes the DMA2D MSP. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ @@ -400,57 +452,248 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) */ } +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User DMA2D Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hdma2d DMA2D handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID + * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID + * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID + * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID + * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID + * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID + * @retval status + */ +HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hdma2d); + + if(HAL_DMA2D_STATE_READY == hdma2d->State) + { + switch (CallbackID) + { + case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID : + hdma2d->XferCpltCallback = pCallback; + break; + + case HAL_DMA2D_TRANSFERERROR_CB_ID : + hdma2d->XferErrorCallback = pCallback; + break; + + case HAL_DMA2D_LINEEVENT_CB_ID : + hdma2d->LineEventCallback = pCallback; + break; + + case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID : + hdma2d->CLUTLoadingCpltCallback = pCallback; + break; + + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = pCallback; + break; + + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_DMA2D_STATE_RESET == hdma2d->State) + { + switch (CallbackID) + { + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = pCallback; + break; + + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma2d); + return status; +} + +/** + * @brief Unregister a DMA2D Callback + * DMA2D Callback is redirected to the weak (surcharged) predefined callback + * @param hdma2d DMA2D handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID + * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID + * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID + * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID + * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID + * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID + * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID + * @retval status + */ +HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID) +{ +HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma2d); + + if(HAL_DMA2D_STATE_READY == hdma2d->State) + { + switch (CallbackID) + { + case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID : + hdma2d->XferCpltCallback = NULL; + break; + + case HAL_DMA2D_TRANSFERERROR_CB_ID : + hdma2d->XferErrorCallback = NULL; + break; + + case HAL_DMA2D_LINEEVENT_CB_ID : + hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback; + break; + + case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID : + hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback; + break; + + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; + + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; + + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_DMA2D_STATE_RESET == hdma2d->State) + { + switch (CallbackID) + { + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; + + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; + + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma2d); + return status; +} +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ + /** * @} */ /** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions + * @brief IO operation functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: - (+) Configure the pdata, destination address and data size then + (+) Configure the pdata, destination address and data size then start the DMA2D transfer. - (+) Configure the source for foreground and background, destination address + (+) Configure the source for foreground and background, destination address and data size then start a MultiBuffer DMA2D transfer. - (+) Configure the pdata, destination address and data size then + (+) Configure the pdata, destination address and data size then start the DMA2D transfer with interrupt. - (+) Configure the source for foreground and background, destination address + (+) Configure the source for foreground and background, destination address and data size then start a MultiBuffer DMA2D transfer with interrupt. (+) Abort DMA2D transfer. (+) Suspend DMA2D transfer. - (+) Resume DMA2D transfer. - (+) Enable CLUT transfer. + (+) Resume DMA2D transfer. + (+) Enable CLUT transfer. (+) Configure CLUT loading then start transfer in polling mode. (+) Configure CLUT loading then start transfer in interrupt mode. (+) Abort DMA2D CLUT loading. (+) Suspend DMA2D CLUT loading. - (+) Resume DMA2D CLUT loading. + (+) Resume DMA2D CLUT loading. (+) Poll for transfer complete. (+) handle DMA2D interrupt request. (+) Transfer watermark callback. (+) CLUT Transfer Complete callback. - - + + @endverbatim * @{ */ /** * @brief Start the DMA2D Transfer. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param pdata: Configure the source memory Buffer address if - * Memory-to-Memory or Memory-to-Memory with pixel format - * conversion mode is selected, or configure + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param pdata Configure the source memory Buffer address if + * Memory-to-Memory or Memory-to-Memory with pixel format + * conversion mode is selected, or configure * the color value if Register-to-Memory mode is selected. - * @param DstAddress: The destination memory Buffer address. - * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). - * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) @@ -458,13 +701,13 @@ HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, u /* Check the parameters */ assert_param(IS_DMA2D_LINE(Height)); assert_param(IS_DMA2D_PIXEL(Width)); - + /* Process locked */ __HAL_LOCK(hdma2d); /* Change DMA2D peripheral state */ hdma2d->State = HAL_DMA2D_STATE_BUSY; - + /* Configure the source, destination address and the data size */ DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height); @@ -476,15 +719,15 @@ HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, u /** * @brief Start the DMA2D Transfer with interrupt enabled. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param pdata: Configure the source memory Buffer address if - * the Memory-to-Memory or Memory-to-Memory with pixel format - * conversion mode is selected, or configure + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param pdata Configure the source memory Buffer address if + * the Memory-to-Memory or Memory-to-Memory with pixel format + * conversion mode is selected, or configure * the color value if Register-to-Memory mode is selected. - * @param DstAddress: The destination memory Buffer address. - * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). - * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) @@ -513,26 +756,26 @@ HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata /** * @brief Start the multi-source DMA2D Transfer. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param SrcAddress1: The source memory Buffer address for the foreground layer. - * @param SrcAddress2: The source memory Buffer address for the background layer. - * @param DstAddress: The destination memory Buffer address. - * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). - * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param SrcAddress1 The source memory Buffer address for the foreground layer. + * @param SrcAddress2 The source memory Buffer address for the background layer. + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) { /* Check the parameters */ assert_param(IS_DMA2D_LINE(Height)); - assert_param(IS_DMA2D_PIXEL(Width)); - + assert_param(IS_DMA2D_PIXEL(Width)); + /* Process locked */ __HAL_LOCK(hdma2d); /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; + hdma2d->State = HAL_DMA2D_STATE_BUSY; /* Configure DMA2D Stream source2 address */ WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2); @@ -548,13 +791,13 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t /** * @brief Start the multi-source DMA2D Transfer with interrupt enabled. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param SrcAddress1: The source memory Buffer address for the foreground layer. - * @param SrcAddress2: The source memory Buffer address for the background layer. - * @param DstAddress: The destination memory Buffer address. - * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). - * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param SrcAddress1 The source memory Buffer address for the foreground layer. + * @param SrcAddress2 The source memory Buffer address for the background layer. + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) @@ -562,22 +805,22 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32 /* Check the parameters */ assert_param(IS_DMA2D_LINE(Height)); assert_param(IS_DMA2D_PIXEL(Width)); - + /* Process locked */ __HAL_LOCK(hdma2d); /* Change DMA2D peripheral state */ hdma2d->State = HAL_DMA2D_STATE_BUSY; - + /* Configure DMA2D Stream source2 address */ WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2); /* Configure the source, destination address and the data size */ DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height); - + /* Enable the transfer complete, transfer error and configuration error interrupts */ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); - + /* Enable the Peripheral */ __HAL_DMA2D_ENABLE(hdma2d); @@ -586,66 +829,66 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32 /** * @brief Abort the DMA2D Transfer. - * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Abort the DMA2D transfer */ /* START bit is reset to make sure not to set it again, in the event the HW clears it - between the register read and the register write by the CPU (writing 0 has no - effect on START bitvalue). */ + between the register read and the register write by the CPU (writing 0 has no + effect on START bitvalue) */ MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT); /* Get tick */ tickstart = HAL_GetTick(); /* Check if the DMA2D is effectively disabled */ - while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET) + while((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) { if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - + /* Change the DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; - + /* Process Unlocked */ __HAL_UNLOCK(hdma2d); - + return HAL_TIMEOUT; } } /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); /* Change the DMA2D state*/ hdma2d->State = HAL_DMA2D_STATE_READY; - + /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); + __HAL_UNLOCK(hdma2d); return HAL_OK; } /** * @brief Suspend the DMA2D Transfer. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Suspend the DMA2D transfer */ /* START bit is reset to make sure not to set it again, in the event the HW clears it - between the register read and the register write by the CPU (writing 0 has no + between the register read and the register write by the CPU (writing 0 has no effect on START bitvalue). */ MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP); @@ -653,29 +896,28 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) tickstart = HAL_GetTick(); /* Check if the DMA2D is effectively suspended */ - while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \ - && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)) + while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START) { if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - + /* Change the DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; - + return HAL_TIMEOUT; } } - + /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ - if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET) - { + if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) + { hdma2d->State = HAL_DMA2D_STATE_SUSPEND; } else { - /* Make sure SUSP bit is cleared since it is meaningless + /* Make sure SUSP bit is cleared since it is meaningless when no tranfer is on-going */ CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); } @@ -685,8 +927,8 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) /** * @brief Resume the DMA2D Transfer. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) @@ -700,9 +942,9 @@ HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) /* Resume the DMA2D transfer */ /* START bit is reset to make sure not to set it again, in the event the HW clears it - between the register read and the register write by the CPU (writing 0 has no + between the register read and the register write by the CPU (writing 0 has no effect on START bitvalue). */ - CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START)); + CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START)); return HAL_OK; } @@ -710,25 +952,25 @@ HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) /** * @brief Enable the DMA2D CLUT Transfer. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: - * 0(background) / 1(foreground) + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) -{ +{ /* Check the parameters */ assert_param(IS_DMA2D_LAYER(LayerIdx)); - + /* Process locked */ __HAL_LOCK(hdma2d); - + /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - if(LayerIdx == 0) + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + if(LayerIdx == DMA2D_BACKGROUND_LAYER) { /* Enable the background CLUT loading */ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); @@ -736,47 +978,47 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay else { /* Enable the foreground CLUT loading */ - SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); + SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); } - + return HAL_OK; } /** * @brief Start DMA2D CLUT Loading. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains * the configuration information for the color look up table. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: - * 0(background) / 1(foreground) - * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT(). + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT(). * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) { /* Check the parameters */ - assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_LAYER(LayerIdx)); assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); - + /* Process locked */ __HAL_LOCK(hdma2d); - + /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - + hdma2d->State = HAL_DMA2D_STATE_BUSY; + /* Configure the CLUT of the background DMA2D layer */ - if(LayerIdx == 0) + if(LayerIdx == DMA2D_BACKGROUND_LAYER) { /* Write background CLUT memory address */ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); - + /* Write background CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM))); + MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); /* Enable the CLUT loading for the background */ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); @@ -786,54 +1028,54 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgT { /* Write foreground CLUT memory address */ WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); - + /* Write foreground CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM))); - + MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); + /* Enable the CLUT loading for the foreground */ - SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); + SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); } - + return HAL_OK; } /** * @brief Start DMA2D CLUT Loading with interrupt enabled. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains * the configuration information for the color look up table. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: - * 0(background) / 1(foreground) + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) { /* Check the parameters */ - assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_LAYER(LayerIdx)); assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); - + /* Process locked */ __HAL_LOCK(hdma2d); - + /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - + hdma2d->State = HAL_DMA2D_STATE_BUSY; + /* Configure the CLUT of the background DMA2D layer */ - if(LayerIdx == 0) + if(LayerIdx == DMA2D_BACKGROUND_LAYER) { /* Write background CLUT memory address */ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); - + /* Write background CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM))); - + MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); + /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); /* Enable the CLUT loading for the background */ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); @@ -843,42 +1085,40 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTC { /* Write foreground CLUT memory address */ WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); - + /* Write foreground CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM))); - + MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); + /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); - + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); + /* Enable the CLUT loading for the foreground */ - SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); + SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); } - + return HAL_OK; } /** * @brief Abort the DMA2D CLUT loading. - * @param hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: - * 0(background) / 1(foreground) + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) { - uint32_t tickstart = 0; - __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ - uint32_t mask = DMA2D_BGPFCCR_START; /* by default, set to background constant */ - + uint32_t tickstart; + const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ /* Abort the CLUT loading */ SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT); - - /* If foreground CLUT loading is considered, update local variables */ - if(LayerIdx == 1) + + /* If foreground CLUT loading is considered, update local variables */ + if(LayerIdx == DMA2D_FOREGROUND_LAYER) { reg = &(hdma2d->Instance->FGPFCCR); } @@ -886,31 +1126,31 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint3 /* Get tick */ tickstart = HAL_GetTick(); - - /* Check if the CLUT loading is aborted */ - while((*reg & mask) != RESET) + + /* Check if the CLUT loading is aborted */ + while((*reg & DMA2D_BGPFCCR_START) != 0U) { if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - + /* Change the DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; - + /* Process Unlocked */ __HAL_UNLOCK(hdma2d); - + return HAL_TIMEOUT; } } /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); - + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); + /* Change the DMA2D state*/ hdma2d->State = HAL_DMA2D_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hdma2d); @@ -919,98 +1159,104 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint3 /** * @brief Suspend the DMA2D CLUT loading. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: - * 0(background) / 1(foreground) + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) { - uint32_t tickstart = 0; - __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ - uint32_t mask = DMA2D_BGPFCCR_START; /* by default, set to background constant */ - + uint32_t tickstart; + uint32_t loadsuspended; + const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ /* Suspend the CLUT loading */ - SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); - - /* If foreground CLUT loading is considered, update local variables */ - if(LayerIdx == 1) + SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); + + /* If foreground CLUT loading is considered, update local variables */ + if(LayerIdx == DMA2D_FOREGROUND_LAYER) { reg = &(hdma2d->Instance->FGPFCCR); - } + } /* Get tick */ tickstart = HAL_GetTick(); - + /* Check if the CLUT loading is suspended */ - while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \ - && ((*reg & mask) == mask)) + loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/ + loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */ + while (loadsuspended == 0UL) { if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - + /* Change the DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; - + return HAL_TIMEOUT; } + loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/ + loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */ } - + /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ - if ((*reg & mask) != RESET) - { + if ((*reg & DMA2D_BGPFCCR_START) != 0U) + { hdma2d->State = HAL_DMA2D_STATE_SUSPEND; } else { - /* Make sure SUSP bit is cleared since it is meaningless + /* Make sure SUSP bit is cleared since it is meaningless when no tranfer is on-going */ CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); - } + } return HAL_OK; } /** * @brief Resume the DMA2D CLUT loading. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: - * 0(background) / 1(foreground) + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) { /* Check the SUSP and START bits for background or foreground CLUT loading */ - if(LayerIdx == 0) - { + if(LayerIdx == DMA2D_BACKGROUND_LAYER) + { /* Background CLUT loading suspension check */ - if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) - && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)) + if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) { + if((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START) + { /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ hdma2d->State = HAL_DMA2D_STATE_BUSY; } } + } else { /* Foreground CLUT loading suspension check */ - if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) - && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)) + if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) { + if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START) + { /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ hdma2d->State = HAL_DMA2D_STATE_BUSY; - } + } + } } /* Resume the CLUT loading */ - CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); + CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); return HAL_OK; } @@ -1019,34 +1265,35 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint /** * @brief Polling for transfer complete or CLUT loading. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param Timeout: Timeout duration + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout) { - uint32_t tickstart = 0; - __IO uint32_t isrflags = 0x0; + uint32_t tickstart; + uint32_t layer_start; + __IO uint32_t isrflags = 0x0U; /* Polling for DMA2D transfer */ - if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET) + if((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) { /* Get tick */ tickstart = HAL_GetTick(); - while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET) + while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U) { - isrflags = READ_REG(hdma2d->Instance->ISR); - if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET) + isrflags = READ_REG(hdma2d->Instance->ISR); + if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U) { - if ((isrflags & DMA2D_FLAG_CE) != RESET) + if ((isrflags & DMA2D_FLAG_CE) != 0U) { - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; } - if ((isrflags & DMA2D_FLAG_TE) != RESET) + if ((isrflags & DMA2D_FLAG_TE) != 0U) { - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; } /* Clear the transfer and configuration error flags */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE); @@ -1056,116 +1303,117 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_ /* Process unlocked */ __HAL_UNLOCK(hdma2d); - + return HAL_ERROR; } /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; /* Change the DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; - + /* Process unlocked */ __HAL_UNLOCK(hdma2d); - + return HAL_TIMEOUT; } - } + } } } /* Polling for CLUT loading (foreground or background) */ - if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET) || - ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET)) + layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START; + layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START; + if (layer_start != 0U) { /* Get tick */ tickstart = HAL_GetTick(); - - while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET) + + while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U) { - isrflags = READ_REG(hdma2d->Instance->ISR); - if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET) - { - if ((isrflags & DMA2D_FLAG_CAE) != RESET) + isrflags = READ_REG(hdma2d->Instance->ISR); + if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U) + { + if ((isrflags & DMA2D_FLAG_CAE) != 0U) { - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; - } - if ((isrflags & DMA2D_FLAG_CE) != RESET) + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; + } + if ((isrflags & DMA2D_FLAG_CE) != 0U) { - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; } - if ((isrflags & DMA2D_FLAG_TE) != RESET) + if ((isrflags & DMA2D_FLAG_TE) != 0U) { - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; } /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE); - + /* Change DMA2D state */ hdma2d->State= HAL_DMA2D_STATE_ERROR; - + /* Process unlocked */ __HAL_UNLOCK(hdma2d); - - return HAL_ERROR; - } + + return HAL_ERROR; + } /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - + /* Change the DMA2D state */ hdma2d->State= HAL_DMA2D_STATE_TIMEOUT; - + /* Process unlocked */ __HAL_UNLOCK(hdma2d); - + return HAL_TIMEOUT; } - } + } } } /* Clear the transfer complete and CLUT loading flags */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC); - + /* Change DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hdma2d); - + return HAL_OK; } /** * @brief Handle DMA2D interrupt request. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. * @retval HAL status */ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) { uint32_t isrflags = READ_REG(hdma2d->Instance->ISR); uint32_t crflags = READ_REG(hdma2d->Instance->CR); - + /* Transfer Error Interrupt management ***************************************/ - if ((isrflags & DMA2D_FLAG_TE) != RESET) + if ((isrflags & DMA2D_FLAG_TE) != 0U) { - if ((crflags & DMA2D_IT_TE) != RESET) + if ((crflags & DMA2D_IT_TE) != 0U) { /* Disable the transfer Error interrupt */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE); + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE); /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; - + /* Clear the transfer error flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE); @@ -1173,8 +1421,8 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) hdma2d->State = HAL_DMA2D_STATE_ERROR; /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - + __HAL_UNLOCK(hdma2d); + if(hdma2d->XferErrorCallback != NULL) { /* Transfer error Callback */ @@ -1183,25 +1431,25 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) } } /* Configuration Error Interrupt management **********************************/ - if ((isrflags & DMA2D_FLAG_CE) != RESET) + if ((isrflags & DMA2D_FLAG_CE) != 0U) { - if ((crflags & DMA2D_IT_CE) != RESET) - { + if ((crflags & DMA2D_IT_CE) != 0U) + { /* Disable the Configuration Error interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE); - + /* Clear the Configuration error flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE); /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; - + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; + /* Change DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_ERROR; /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - + __HAL_UNLOCK(hdma2d); + if(hdma2d->XferErrorCallback != NULL) { /* Transfer error Callback */ @@ -1210,104 +1458,113 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) } } /* CLUT access Error Interrupt management ***********************************/ - if ((isrflags & DMA2D_FLAG_CAE) != RESET) + if ((isrflags & DMA2D_FLAG_CAE) != 0U) { - if ((crflags & DMA2D_IT_CAE) != RESET) - { + if ((crflags & DMA2D_IT_CAE) != 0U) + { /* Disable the CLUT access error interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE); - + /* Clear the CLUT access error flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE); /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; - + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; + /* Change DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_ERROR; /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - + __HAL_UNLOCK(hdma2d); + if(hdma2d->XferErrorCallback != NULL) { /* Transfer error Callback */ hdma2d->XferErrorCallback(hdma2d); } } - } + } /* Transfer watermark Interrupt management **********************************/ - if ((isrflags & DMA2D_FLAG_TW) != RESET) + if ((isrflags & DMA2D_FLAG_TW) != 0U) { - if ((crflags & DMA2D_IT_TW) != RESET) - { + if ((crflags & DMA2D_IT_TW) != 0U) + { /* Disable the transfer watermark interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW); - - /* Clear the transfer watermark flag */ + + /* Clear the transfer watermark flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW); /* Transfer watermark Callback */ +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) + hdma2d->LineEventCallback(hdma2d); +#else HAL_DMA2D_LineEventCallback(hdma2d); +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ + } - } + } /* Transfer Complete Interrupt management ************************************/ - if ((isrflags & DMA2D_FLAG_TC) != RESET) + if ((isrflags & DMA2D_FLAG_TC) != 0U) { - if ((crflags & DMA2D_IT_TC) != RESET) - { + if ((crflags & DMA2D_IT_TC) != 0U) + { /* Disable the transfer complete interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC); - - /* Clear the transfer complete flag */ + + /* Clear the transfer complete flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC); /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; - + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; + /* Change DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_READY; - + /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - + __HAL_UNLOCK(hdma2d); + if(hdma2d->XferCpltCallback != NULL) { /* Transfer complete Callback */ hdma2d->XferCpltCallback(hdma2d); - } + } } } /* CLUT Transfer Complete Interrupt management ******************************/ - if ((isrflags & DMA2D_FLAG_CTC) != RESET) + if ((isrflags & DMA2D_FLAG_CTC) != 0U) { - if ((crflags & DMA2D_IT_CTC) != RESET) - { + if ((crflags & DMA2D_IT_CTC) != 0U) + { /* Disable the CLUT transfer complete interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC); - - /* Clear the CLUT transfer complete flag */ + + /* Clear the CLUT transfer complete flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC); /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; - + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; + /* Change DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_READY; - + /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - + __HAL_UNLOCK(hdma2d); + /* CLUT Transfer complete Callback */ - HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d); +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) + hdma2d->CLUTLoadingCpltCallback(hdma2d); +#else + HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d); +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ } - } - + } + } /** * @brief Transfer watermark callback. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ @@ -1315,7 +1572,7 @@ __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdma2d); - + /* NOTE : This function should not be modified; when the callback is needed, the HAL_DMA2D_LineEventCallback can be implemented in the user file. */ @@ -1323,7 +1580,7 @@ __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d) /** * @brief CLUT Transfer Complete callback. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ @@ -1331,30 +1588,30 @@ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdma2d); - + /* NOTE : This function should not be modified; when the callback is needed, the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file. */ -} +} /** * @} */ /** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions + * @brief Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Configure the DMA2D foreground or background layer parameters. (+) Configure the DMA2D CLUT transfer. (+) Configure the line watermark (+) Configure the dead time value. - (+) Enable or disable the dead time value functionality. - + (+) Enable or disable the dead time value functionality. + @endverbatim * @{ @@ -1363,163 +1620,156 @@ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) /** * @brief Configure the DMA2D Layer according to the specified * parameters in the DMA2D_HandleTypeDef. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: - * 0(background) / 1(foreground) + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) -{ - DMA2D_LayerCfgTypeDef *LayerCfg = &hdma2d->LayerCfg[LayerIdx]; - uint32_t tmp = 0; - +{ + DMA2D_LayerCfgTypeDef *pLayerCfg; + uint32_t regMask, regValue; + /* Check the parameters */ - assert_param(IS_DMA2D_LAYER(LayerIdx)); - assert_param(IS_DMA2D_OFFSET(LayerCfg->InputOffset)); + assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset)); if(hdma2d->Init.Mode != DMA2D_R2M) - { - assert_param(IS_DMA2D_INPUT_COLOR_MODE(LayerCfg->InputColorMode)); + { + assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode)); if(hdma2d->Init.Mode != DMA2D_M2M) { - assert_param(IS_DMA2D_ALPHA_MODE(LayerCfg->AlphaMode)); + assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode)); } } - assert_param(IS_DMA2D_ALPHA_INVERTED(LayerCfg->AlphaInverted)); - assert_param(IS_DMA2D_RB_SWAP(LayerCfg->RedBlueSwap)); - + assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted)); + assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap)); + /* Process locked */ __HAL_LOCK(hdma2d); - + /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + pLayerCfg = &hdma2d->LayerCfg[LayerIdx]; + + /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */ + regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) |\ + (pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos); + regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS); + + + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) + { + regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA); + } + else + { + regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos); + } + /* Configure the background DMA2D layer */ - if(LayerIdx == 0) + if(LayerIdx == DMA2D_BACKGROUND_LAYER) { - /* DMA2D BGPFCR register configuration -----------------------------------*/ - /* Prepare the value to be written to the BGPFCCR register */ - if ((LayerCfg->InputColorMode == DMA2D_INPUT_A4) || (LayerCfg->InputColorMode == DMA2D_INPUT_A8)) - { - tmp = (LayerCfg->InputColorMode | (LayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | (LayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA)); - } - else + /* Write DMA2D BGPFCCR register */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue); + + /* DMA2D BGOR register configuration -------------------------------------*/ + WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset); + + /* DMA2D BGCOLR register configuration -------------------------------------*/ + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) { - tmp = (LayerCfg->InputColorMode | (LayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | (LayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA)); + WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED)); } - - /* Write DMA2D BGPFCCR register */ - MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS), \ - (tmp | (LayerCfg->AlphaInverted << DMA2D_POSITION_BGPFCCR_AI) |(LayerCfg->RedBlueSwap << DMA2D_POSITION_BGPFCCR_RBS))); - - - /* DMA2D BGOR register configuration -------------------------------------*/ - WRITE_REG(hdma2d->Instance->BGOR, LayerCfg->InputOffset); - - /* DMA2D BGCOLR register configuration -------------------------------------*/ - if ((LayerCfg->InputColorMode == DMA2D_INPUT_A4) || (LayerCfg->InputColorMode == DMA2D_INPUT_A8)) - { - WRITE_REG(hdma2d->Instance->BGCOLR, LayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED)); - } } /* Configure the foreground DMA2D layer */ else { - /* DMA2D FGPFCR register configuration -----------------------------------*/ - /* Prepare the value to be written to the FGPFCCR register */ - if ((LayerCfg->InputColorMode == DMA2D_INPUT_A4) || (LayerCfg->InputColorMode == DMA2D_INPUT_A8)) - { - tmp = (LayerCfg->InputColorMode | (LayerCfg->AlphaMode << DMA2D_POSITION_FGPFCCR_AM) | (LayerCfg->InputAlpha & DMA2D_FGPFCCR_ALPHA)); - } - else - { - tmp = (LayerCfg->InputColorMode | (LayerCfg->AlphaMode << DMA2D_POSITION_FGPFCCR_AM) | (LayerCfg->InputAlpha << DMA2D_POSITION_FGPFCCR_ALPHA)); - } - - /* Write DMA2D FGPFCCR register */ - MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CM | DMA2D_FGPFCCR_AM | DMA2D_FGPFCCR_ALPHA | DMA2D_FGPFCCR_AI | DMA2D_FGPFCCR_RBS), \ - (tmp | (LayerCfg->AlphaInverted << DMA2D_POSITION_FGPFCCR_AI) |(LayerCfg->RedBlueSwap << DMA2D_POSITION_FGPFCCR_RBS))); - + + /* Write DMA2D FGPFCCR register */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue); + /* DMA2D FGOR register configuration -------------------------------------*/ - WRITE_REG(hdma2d->Instance->FGOR, LayerCfg->InputOffset); - - /* DMA2D FGCOLR register configuration -------------------------------------*/ - if ((LayerCfg->InputColorMode == DMA2D_INPUT_A4) || (LayerCfg->InputColorMode == DMA2D_INPUT_A8)) + WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset); + + /* DMA2D FGCOLR register configuration -------------------------------------*/ + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) { - WRITE_REG(hdma2d->Instance->FGCOLR, LayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED)); - } - } + WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED)); + } + } /* Initialize the DMA2D state*/ hdma2d->State = HAL_DMA2D_STATE_READY; - + /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - + __HAL_UNLOCK(hdma2d); + return HAL_OK; } /** * @brief Configure the DMA2D CLUT Transfer. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains * the configuration information for the color look up table. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: - * 0(background) / 1(foreground) + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) { /* Check the parameters */ - assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_LAYER(LayerIdx)); assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); - + /* Process locked */ __HAL_LOCK(hdma2d); - + /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - + hdma2d->State = HAL_DMA2D_STATE_BUSY; + /* Configure the CLUT of the background DMA2D layer */ - if(LayerIdx == 0) + if(LayerIdx == DMA2D_BACKGROUND_LAYER) { /* Write background CLUT memory address */ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); - + /* Write background CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM))); + MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); } /* Configure the CLUT of the foreground DMA2D layer */ else { /* Write foreground CLUT memory address */ WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); - + /* Write foreground CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM))); + MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); } - + /* Set the DMA2D state to Ready*/ hdma2d->State = HAL_DMA2D_STATE_READY; - + /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - + __HAL_UNLOCK(hdma2d); + return HAL_OK; } /** * @brief Configure the line watermark. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param Line: Line Watermark configuration (maximum 16-bit long value expected). + * @param Line Line Watermark configuration (maximum 16-bit long value expected). * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt. * @note The transfer watermark interrupt is disabled once it has occurred. * @retval HAL status @@ -1529,38 +1779,38 @@ HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32 { /* Check the parameters */ assert_param(IS_DMA2D_LINEWATERMARK(Line)); - + if (Line > DMA2D_LWR_LW) { - return HAL_ERROR; + return HAL_ERROR; } else - { + { /* Process locked */ __HAL_LOCK(hdma2d); - + /* Change DMA2D peripheral state */ hdma2d->State = HAL_DMA2D_STATE_BUSY; - + /* Sets the Line watermark configuration */ WRITE_REG(hdma2d->Instance->LWR, Line); - + /* Enable the Line interrupt */ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW); - + /* Initialize the DMA2D state*/ hdma2d->State = HAL_DMA2D_STATE_READY; - + /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - + __HAL_UNLOCK(hdma2d); + return HAL_OK; - } + } } /** * @brief Enable DMA2D dead time feature. - * @param hdma2d: DMA2D handle. + * @param hdma2d DMA2D handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d) @@ -1583,7 +1833,7 @@ HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d) /** * @brief Disable DMA2D dead time feature. - * @param hdma2d: DMA2D handle. + * @param hdma2d DMA2D handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d) @@ -1606,21 +1856,21 @@ HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d) /** * @brief Configure dead time. - * @note The dead time value represents the guaranteed minimum number of cycles between + * @note The dead time value represents the guaranteed minimum number of cycles between * two consecutive transactions on the AHB bus. - * @param hdma2d: DMA2D handle. - * @param DeadTime: dead time value. + * @param hdma2d DMA2D handle. + * @param DeadTime dead time value. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime) { /* Process Locked */ - __HAL_LOCK(hdma2d); - + __HAL_LOCK(hdma2d); + hdma2d->State = HAL_DMA2D_STATE_BUSY; /* Set DMA2D_AMTCR DT field */ - MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT)); + MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_AMTCR_DT_Pos)); hdma2d->State = HAL_DMA2D_STATE_READY; @@ -1633,38 +1883,38 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t /** * @} */ - + /** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions - * @brief Peripheral State functions + * @brief Peripheral State functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State and Errors functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides functions allowing to : + This subsection provides functions allowing to: (+) Get the DMA2D state - (+) Get the DMA2D error code + (+) Get the DMA2D error code @endverbatim * @{ - */ + */ /** * @brief Return the DMA2D state - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. * @retval HAL state */ HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d) -{ +{ return hdma2d->State; } /** * @brief Return the DMA2D error code - * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for DMA2D. * @retval DMA2D Error Code */ @@ -1676,10 +1926,10 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d) /** * @} */ - + /** * @} - */ + */ /** @defgroup DMA2D_Private_Functions DMA2D Private Functions @@ -1688,36 +1938,36 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d) /** * @brief Set the DMA2D transfer parameters. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the specified DMA2D. - * @param pdata: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param Width: The width of data to be transferred from source to destination. - * @param Height: The height of data to be transferred from source to destination. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the specified DMA2D. + * @param pdata The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param Width The width of data to be transferred from source to destination. + * @param Height The height of data to be transferred from source to destination. * @retval HAL status */ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) -{ - uint32_t tmp = 0; - uint32_t tmp1 = 0; - uint32_t tmp2 = 0; - uint32_t tmp3 = 0; - uint32_t tmp4 = 0; - +{ + uint32_t tmp; + uint32_t tmp1; + uint32_t tmp2; + uint32_t tmp3; + uint32_t tmp4; + /* Configure DMA2D data size */ - MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_POSITION_NLR_PL))); - + MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos))); + /* Configure DMA2D destination address */ WRITE_REG(hdma2d->Instance->OMAR, DstAddress); - + /* Register to memory DMA2D mode selected */ if (hdma2d->Init.Mode == DMA2D_R2M) - { + { tmp1 = pdata & DMA2D_OCOLR_ALPHA_1; tmp2 = pdata & DMA2D_OCOLR_RED_1; tmp3 = pdata & DMA2D_OCOLR_GREEN_1; tmp4 = pdata & DMA2D_OCOLR_BLUE_1; - + /* Prepare the value to be written to the OCOLR register according to the color mode */ if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888) { @@ -1725,45 +1975,45 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ } else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888) { - tmp = (tmp3 | tmp2 | tmp4); + tmp = (tmp3 | tmp2 | tmp4); } else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565) { - tmp2 = (tmp2 >> 19); - tmp3 = (tmp3 >> 10); - tmp4 = (tmp4 >> 3 ); - tmp = ((tmp3 << 5) | (tmp2 << 11) | tmp4); + tmp2 = (tmp2 >> 19U); + tmp3 = (tmp3 >> 10U); + tmp4 = (tmp4 >> 3U ); + tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4); } else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555) - { - tmp1 = (tmp1 >> 31); - tmp2 = (tmp2 >> 19); - tmp3 = (tmp3 >> 11); - tmp4 = (tmp4 >> 3 ); - tmp = ((tmp3 << 5) | (tmp2 << 10) | (tmp1 << 15) | tmp4); - } + { + tmp1 = (tmp1 >> 31U); + tmp2 = (tmp2 >> 19U); + tmp3 = (tmp3 >> 11U); + tmp4 = (tmp4 >> 3U ); + tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4); + } else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */ { - tmp1 = (tmp1 >> 28); - tmp2 = (tmp2 >> 20); - tmp3 = (tmp3 >> 12); - tmp4 = (tmp4 >> 4 ); - tmp = ((tmp3 << 4) | (tmp2 << 8) | (tmp1 << 12) | tmp4); - } + tmp1 = (tmp1 >> 28U); + tmp2 = (tmp2 >> 20U); + tmp3 = (tmp3 >> 12U); + tmp4 = (tmp4 >> 4U ); + tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4); + } /* Write to DMA2D OCOLR register */ - WRITE_REG(hdma2d->Instance->OCOLR, tmp); - } + WRITE_REG(hdma2d->Instance->OCOLR, tmp); + } else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */ { /* Configure DMA2D source address */ - WRITE_REG(hdma2d->Instance->FGMAR, pdata); + WRITE_REG(hdma2d->Instance->FGMAR, pdata); } } /** * @} */ - + /** * @} */ @@ -1771,10 +2021,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ /** * @} */ - -#endif /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - +#endif /* DMA2D */ #endif /* HAL_DMA2D_MODULE_ENABLED */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c index 74c09430ef..586d786124 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c @@ -175,9 +175,9 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, /* Process Locked */ __HAL_LOCK(hdma); - /* Set the request generator new parameters*/ + /* Set the request generator new parameters */ hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \ - ((pRequestGeneratorConfig->RequestNumber - 1U) << POSITION_VAL(DMAMUX_RGxCR_GNBREQ))| \ + ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \ pRequestGeneratorConfig->Polarity; /* Process UnLocked */ __HAL_UNLOCK(hdma); diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dsi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dsi.c index 7a0f644432..4d66ea56ed 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dsi.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dsi.c @@ -9,6 +9,110 @@ * + IO operation functions * + Peripheral Control functions * + Peripheral State and Errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Use @ref HAL_DSI_Init() function to initialize the DSI Host IP and program the required + PLL parameters, number of lanes and TX Escape clock divider. + (#) Use @ref HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted + command mode. + (#) When operating in video mode , use @ref HAL_DSI_ConfigVideoMode() to configure the DSI host. + (#) Function @ref HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode. + (#) To configure the DSI PHY timings parameters, use function @ref HAL_DSI_ConfigPhyTimer(). + (#) The DSI Host can be started/stopped using respectively functions @ref HAL_DSI_Start() and @ref HAL_DSI_Stop(). + Functions @ref HAL_DSI_ShortWrite(), @ref HAL_DSI_LongWrite() and @ref HAL_DSI_Read() allows respectively + to write DSI short packets, long packets and to read DSI packets. + + (#) The DSI Host Offers two Low power modes : + (+) Low Power Mode on data lanes only: Only DSI data lanes are shut down. + It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPMData() + and @ref HAL_DSI_ExitULPMData() + + (+) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes. + It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPM() + and @ref HAL_DSI_ExitULPM() + + (#) User can select the DSI errors to be reported/monitored using function @ref HAL_DSI_ConfigErrorMonitor() + When an error occurs, the callback @ref HAL_DSI_ErrorCallback() is asserted and then user can retrieve + the error code by calling function @ref HAL_DSI_GetError() + + (#) To control DSI state you can use the following function: HAL_DSI_GetState() + + *** DSI HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DSI HAL driver. + + (+) __HAL_DSI_ENABLE: Enable the DSI Host. + (+) __HAL_DSI_DISABLE: Disable the DSI Host. + (+) __HAL_DSI_WRAPPER_ENABLE: Enables the DSI wrapper. + (+) __HAL_DSI_WRAPPER_DISABLE: Disable the DSI wrapper. + (+) __HAL_DSI_PLL_ENABLE: Enables the DSI PLL. + (+) __HAL_DSI_PLL_DISABLE: Disables the DSI PLL. + (+) __HAL_DSI_REG_ENABLE: Enables the DSI regulator. + (+) __HAL_DSI_REG_DISABLE: Disables the DSI regulator. + (+) __HAL_DSI_GET_FLAG: Get the DSI pending flags. + (+) __HAL_DSI_CLEAR_FLAG: Clears the DSI pending flags. + (+) __HAL_DSI_ENABLE_IT: Enables the specified DSI interrupts. + (+) __HAL_DSI_DISABLE_IT: Disables the specified DSI interrupts. + (+) __HAL_DSI_GET_IT_SOURCE: Checks whether the specified DSI interrupt source is enabled or not. + + + + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_DSI_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function @ref HAL_DSI_RegisterCallback() to register a callback. + + Function @ref HAL_DSI_RegisterCallback() allows to register following callbacks: + (+) TearingEffectCallback : DSI Tearing Effect Callback. + (+) EndOfRefreshCallback : DSI End Of Refresh Callback. + (+) ErrorCallback : DSI Error Callback + (+) MspInitCallback : DSI MspInit. + (+) MspDeInitCallback : DSI MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_DSI_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TearingEffectCallback : DSI Tearing Effect Callback. + (+) EndOfRefreshCallback : DSI End Of Refresh Callback. + (+) ErrorCallback : DSI Error Callback + (+) MspInitCallback : DSI MspInit. + (+) MspDeInitCallback : DSI MspDeInit. + + By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_DSI_TearingEffectCallback(), @ref HAL_DSI_EndOfRefreshCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the HAL_DSI_Init/ @ref HAL_DSI_DeInit only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the @ref HAL_DSI_Init/ @ref HAL_DSI_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_DSI_RegisterCallback() before calling @ref HAL_DSI_DeInit + or HAL_DSI_Init function. + + When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + [..] + (@) You can refer to the DSI HAL driver header file for more useful macros + + @endverbatim ****************************************************************************** * @attention * @@ -87,16 +191,16 @@ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32 /* Private functions ---------------------------------------------------------*/ /** * @brief Generic DSI packet header configuration - * @param DSIx: Pointer to DSI register base - * @param ChannelID: Virtual channel ID of the header packet - * @param DataType: Packet data type of the header packet + * @param DSIx Pointer to DSI register base + * @param ChannelID Virtual channel ID of the header packet + * @param DataType Packet data type of the header packet * This parameter can be any value of : * @ref DSI_SHORT_WRITE_PKT_Data_Type * or @ref DSI_LONG_WRITE_PKT_Data_Type * or @ref DSI_SHORT_READ_PKT_Data_Type * or DSI_MAX_RETURN_PKT_SIZE - * @param Data0: Word count LSB - * @param Data1: Word count MSB + * @param Data0 Word count LSB + * @param Data1 Word count MSB * @retval None */ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, @@ -132,10 +236,10 @@ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, /** * @brief Initializes the DSI according to the specified * parameters in the DSI_InitTypeDef and create the associated handle. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param PLLInit: pointer to a DSI_PLLInitTypeDef structure that contains - * the PLL Clock structure definition for the DSI. + * @param PLLInit pointer to a DSI_PLLInitTypeDef structure that contains + * the PLL Clock structure definition for the DSI. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit) @@ -157,11 +261,28 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl)); assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes)); +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + if(hdsi->State == HAL_DSI_STATE_RESET) + { + /* Reset the DSI callback to the legacy weak callbacks */ + hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */ + hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */ + hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */ + + if(hdsi->MspInitCallback == NULL) + { + hdsi->MspInitCallback = HAL_DSI_MspInit; + } + /* Initialize the low level hardware */ + hdsi->MspInitCallback(hdsi); + } +#else if(hdsi->State == HAL_DSI_STATE_RESET) { /* Initialize the low level hardware */ HAL_DSI_MspInit(hdsi); } +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ /* Change DSI peripheral state */ hdsi->State = HAL_DSI_STATE_BUSY; @@ -175,7 +296,7 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI tickstart = HAL_GetTick(); /* Wait until the regulator is ready */ - while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET) + while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == 0U) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) @@ -195,7 +316,7 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI tickstart = HAL_GetTick(); /* Wait for the lock of the PLL */ - while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET) + while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) @@ -227,7 +348,7 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */ /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */ tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U; - unitIntervalx4 = (4000000U * tempIDF * (1U << PLLInit->PLLODF)) / ((HSE_VALUE/1000U) * PLLInit->PLLNDIV); + unitIntervalx4 = (4000000U * tempIDF * ((1UL << PLLInit->PLLODF))) / ((HSE_VALUE/1000U) * PLLInit->PLLNDIV); /* Set the bit period in high-speed mode */ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4; @@ -252,7 +373,7 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI /** * @brief De-initializes the DSI peripheral registers to their default reset * values. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -282,8 +403,17 @@ HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi) /* Disable the regulator */ __HAL_DSI_REG_DISABLE(hdsi); +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + if(hdsi->MspDeInitCallback == NULL) + { + hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; + } + /* DeInit the low level hardware */ + hdsi->MspDeInitCallback(hdsi); +#else /* DeInit the low level hardware */ HAL_DSI_MspDeInit(hdsi); +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ /* Initialise the error code */ hdsi->ErrorCode = HAL_DSI_ERROR_NONE; @@ -299,9 +429,9 @@ HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi) /** * @brief Enable the error monitor flags - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ActiveErrors: indicates which error interrupts will be enabled. + * @param ActiveErrors indicates which error interrupts will be enabled. * This parameter can be any combination of @ref DSI_Error_Data_Type. * @retval HAL status */ @@ -316,61 +446,61 @@ HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t A /* Store active errors to the handle */ hdsi->ErrorMsk = ActiveErrors; - if((ActiveErrors & HAL_DSI_ERROR_ACK) != RESET) + if((ActiveErrors & HAL_DSI_ERROR_ACK) != 0U) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK; } - if((ActiveErrors & HAL_DSI_ERROR_PHY) != RESET) + if((ActiveErrors & HAL_DSI_ERROR_PHY) != 0U) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK; } - if((ActiveErrors & HAL_DSI_ERROR_TX) != RESET) + if((ActiveErrors & HAL_DSI_ERROR_TX) != 0U) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK; } - if((ActiveErrors & HAL_DSI_ERROR_RX) != RESET) + if((ActiveErrors & HAL_DSI_ERROR_RX) != 0U) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK; } - if((ActiveErrors & HAL_DSI_ERROR_ECC) != RESET) + if((ActiveErrors & HAL_DSI_ERROR_ECC) != 0U) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK; } - if((ActiveErrors & HAL_DSI_ERROR_CRC) != RESET) + if((ActiveErrors & HAL_DSI_ERROR_CRC) != 0U) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK; } - if((ActiveErrors & HAL_DSI_ERROR_PSE) != RESET) + if((ActiveErrors & HAL_DSI_ERROR_PSE) != 0U) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK; } - if((ActiveErrors & HAL_DSI_ERROR_EOT) != RESET) + if((ActiveErrors & HAL_DSI_ERROR_EOT) != 0U) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK; } - if((ActiveErrors & HAL_DSI_ERROR_OVF) != RESET) + if((ActiveErrors & HAL_DSI_ERROR_OVF) != 0U) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK; } - if((ActiveErrors & HAL_DSI_ERROR_GEN) != RESET) + if((ActiveErrors & HAL_DSI_ERROR_GEN) != 0U) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK; @@ -384,7 +514,7 @@ HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t A /** * @brief Initializes the DSI MSP. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ @@ -399,7 +529,7 @@ __weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi) /** * @brief De-initializes the DSI MSP. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ @@ -412,6 +542,188 @@ __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi) */ } +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User DSI Callback + * To be used instead of the weak predefined callback + * @param hdsi dsi handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID + * @arg @ref HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID + * @arg @ref HAL_DSI_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_DSI_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID, pDSI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hdsi); + + if(hdsi->State == HAL_DSI_STATE_READY) + { + switch (CallbackID) + { + case HAL_DSI_TEARING_EFFECT_CB_ID : + hdsi->TearingEffectCallback = pCallback; + break; + + case HAL_DSI_ENDOF_REFRESH_CB_ID : + hdsi->EndOfRefreshCallback = pCallback; + break; + + case HAL_DSI_ERROR_CB_ID : + hdsi->ErrorCallback = pCallback; + break; + + case HAL_DSI_MSPINIT_CB_ID : + hdsi->MspInitCallback = pCallback; + break; + + case HAL_DSI_MSPDEINIT_CB_ID : + hdsi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if(hdsi->State == HAL_DSI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DSI_MSPINIT_CB_ID : + hdsi->MspInitCallback = pCallback; + break; + + case HAL_DSI_MSPDEINIT_CB_ID : + hdsi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdsi); + + return status; +} + +/** + * @brief Unregister a DSI Callback + * DSI callabck is redirected to the weak predefined callback + * @param hdsi dsi handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID + * @arg @ref HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID + * @arg @ref HAL_DSI_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_DSI_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdsi); + + if(hdsi->State == HAL_DSI_STATE_READY) + { + switch (CallbackID) + { + case HAL_DSI_TEARING_EFFECT_CB_ID : + hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */ + break; + + case HAL_DSI_ENDOF_REFRESH_CB_ID : + hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */ + break; + + case HAL_DSI_ERROR_CB_ID : + hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_DSI_MSPINIT_CB_ID : + hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */ + break; + + case HAL_DSI_MSPDEINIT_CB_ID : + hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if(hdsi->State == HAL_DSI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DSI_MSPINIT_CB_ID : + hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */ + break; + + case HAL_DSI_MSPDEINIT_CB_ID : + hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdsi); + + return status; +} +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ + /** * @} */ @@ -431,7 +743,7 @@ __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi) */ /** * @brief Handles DSI interrupt request. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -440,28 +752,40 @@ void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi) uint32_t ErrorStatus0, ErrorStatus1; /* Tearing Effect Interrupt management ***************************************/ - if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET) + if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != 0U) { - if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET) + if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != 0U) { /* Clear the Tearing Effect Interrupt Flag */ __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE); /* Tearing Effect Callback */ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + /*Call registered Tearing Effect callback */ + hdsi->TearingEffectCallback(hdsi); +#else + /*Call legacy Tearing Effect callback*/ HAL_DSI_TearingEffectCallback(hdsi); +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ } } /* End of Refresh Interrupt management ***************************************/ - if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET) + if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != 0U) { - if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET) + if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != 0U) { /* Clear the End of Refresh Interrupt Flag */ __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER); /* End of Refresh Callback */ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + /*Call registered End of refresh callback */ + hdsi->EndOfRefreshCallback(hdsi); +#else + /*Call Legacy End of refresh callback */ HAL_DSI_EndOfRefreshCallback(hdsi); +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ } } @@ -473,52 +797,52 @@ void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi) ErrorStatus1 = hdsi->Instance->ISR[1U]; ErrorStatus1 &= hdsi->Instance->IER[1U]; - if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != RESET) + if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != 0U) { hdsi->ErrorCode |= HAL_DSI_ERROR_ACK; } - if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != RESET) + if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != 0U) { hdsi->ErrorCode |= HAL_DSI_ERROR_PHY; } - if((ErrorStatus1 & DSI_ERROR_TX_MASK) != RESET) + if((ErrorStatus1 & DSI_ERROR_TX_MASK) != 0U) { hdsi->ErrorCode |= HAL_DSI_ERROR_TX; } - if((ErrorStatus1 & DSI_ERROR_RX_MASK) != RESET) + if((ErrorStatus1 & DSI_ERROR_RX_MASK) != 0U) { hdsi->ErrorCode |= HAL_DSI_ERROR_RX; } - if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != RESET) + if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != 0U) { hdsi->ErrorCode |= HAL_DSI_ERROR_ECC; } - if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != RESET) + if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != 0U) { hdsi->ErrorCode |= HAL_DSI_ERROR_CRC; } - if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != RESET) + if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != 0U) { hdsi->ErrorCode |= HAL_DSI_ERROR_PSE; } - if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != RESET) + if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != 0U) { hdsi->ErrorCode |= HAL_DSI_ERROR_EOT; } - if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != RESET) + if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != 0U) { hdsi->ErrorCode |= HAL_DSI_ERROR_OVF; } - if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != RESET) + if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != 0U) { hdsi->ErrorCode |= HAL_DSI_ERROR_GEN; } @@ -526,15 +850,21 @@ void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi) /* Check only selected errors */ if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE) { - /* DSI error interrupt user callback */ + /* DSI error interrupt callback */ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + /*Call registered Error callback */ + hdsi->ErrorCallback(hdsi); +#else + /*Call Legacy Error callback */ HAL_DSI_ErrorCallback(hdsi); +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ } } } /** * @brief Tearing Effect DSI callback. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ @@ -549,7 +879,7 @@ __weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi) /** * @brief End of Refresh DSI callback. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ @@ -564,7 +894,7 @@ __weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi) /** * @brief Operation Error DSI callback. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ @@ -623,9 +953,9 @@ __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi) /** * @brief Configure the Generic interface read-back Virtual Channel ID. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param VirtualChannelID: Virtual channel ID + * @param VirtualChannelID Virtual channel ID * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID) @@ -645,10 +975,10 @@ HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t Virtu /** * @brief Select video mode and configure the corresponding parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains - * the DSI video mode configuration parameters + * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains + * the DSI video mode configuration parameters * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg) @@ -795,9 +1125,9 @@ HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTyp /** * @brief Select adapted command mode and configure the corresponding parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains + * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains * the DSI command mode configuration parameters * @retval HAL status */ @@ -865,9 +1195,9 @@ HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_ /** * @brief Configure command transmission mode: High-speed or Low-power * and enable/disable acknowledge request after packet transmission - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains + * @param LPCmd pointer to a DSI_LPCmdTypeDef structure that contains * the DSI command transmission mode configuration parameters * @retval HAL status */ @@ -928,9 +1258,9 @@ HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDe /** * @brief Configure the flow control parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param FlowControl: flow control feature(s) to be enabled. + * @param FlowControl flow control feature(s) to be enabled. * This parameter can be any combination of @ref DSI_FlowControl. * @retval HAL status */ @@ -954,9 +1284,9 @@ HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t Fl /** * @brief Configure the DSI PHY timer parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param PhyTimers: DSI_PHY_TimerTypeDef structure that contains + * @param PhyTimers DSI_PHY_TimerTypeDef structure that contains * the DSI PHY timing parameters * @retval HAL status */ @@ -998,9 +1328,9 @@ HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerT /** * @brief Configure the DSI HOST timeout parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains + * @param HostTimeouts DSI_HOST_TimeoutTypeDef structure that contains * the DSI host timeout parameters * @retval HAL status */ @@ -1053,7 +1383,7 @@ HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_T /** * @brief Start the DSI module - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1076,7 +1406,7 @@ HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi) /** * @brief Stop the DSI module - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1099,7 +1429,7 @@ HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi) /** * @brief Refresh the display in command mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1119,9 +1449,9 @@ HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi) /** * @brief Controls the display color mode in Video mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ColorMode: Color mode (full or 8-colors). + * @param ColorMode Color mode (full or 8-colors). * This parameter can be any value of @ref DSI_Color_Mode * @retval HAL status */ @@ -1145,9 +1475,9 @@ HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode) /** * @brief Control the display shutdown in Video mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Shutdown: Shut-down (Display-ON or Display-OFF). + * @param Shutdown Shut-down (Display-ON or Display-OFF). * This parameter can be any value of @ref DSI_ShutDown * @retval HAL status */ @@ -1171,15 +1501,15 @@ HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown) /** * @brief write short DCS or short Generic command - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ChannelID: Virtual channel ID. - * @param Mode: DSI short packet data type. + * @param ChannelID Virtual channel ID. + * @param Mode DSI short packet data type. * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type. - * @param Param1: DSC command or first generic parameter. + * @param Param1 DSC command or first generic parameter. * This parameter can be any value of @ref DSI_DCS_Command or a * generic command code. - * @param Param2: DSC parameter or second generic parameter. + * @param Param2 DSC parameter or second generic parameter. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, @@ -1227,16 +1557,16 @@ HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, /** * @brief write long DCS or long Generic command - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ChannelID: Virtual channel ID. - * @param Mode: DSI long packet data type. + * @param ChannelID Virtual channel ID. + * @param Mode DSI long packet data type. * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type. - * @param NbParams: Number of parameters. - * @param Param1: DSC command or first generic parameter. + * @param NbParams Number of parameters. + * @param Param1 DSC command or first generic parameter. * This parameter can be any value of @ref DSI_DCS_Command or a * generic command code - * @param ParametersTable: Pointer to parameter values table. + * @param ParametersTable Pointer to parameter values table. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, @@ -1261,7 +1591,7 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, tickstart = HAL_GetTick(); /* Wait for Command FIFO Empty */ - while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET) + while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) @@ -1315,15 +1645,15 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, /** * @brief Read command (DCS or generic) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ChannelNbr: Virtual channel ID - * @param Array: pointer to a buffer to store the payload of a read back operation. - * @param Size: Data size to be read (in byte). - * @param Mode: DSI read packet data type. + * @param ChannelNbr Virtual channel ID + * @param Array pointer to a buffer to store the payload of a read back operation. + * @param Size Data size to be read (in byte). + * @param Mode DSI read packet data type. * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type. - * @param DCSCmd: DCS get/read command. - * @param ParametersTable: Pointer to parameter values table. + * @param DCSCmd DCS get/read command. + * @param ParametersTable Pointer to parameter values table. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, @@ -1337,6 +1667,9 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, uint32_t tickstart; uint8_t* pdata = Array; uint32_t datasize = Size; + uint32_t fifoword; + uint32_t nbbytes; + uint32_t count; /* Process locked */ __HAL_LOCK(hdsi); @@ -1384,45 +1717,19 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, /* Get tick */ tickstart = HAL_GetTick(); - /* Check that the payload read FIFO is not empty */ - while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - - /* Get the first byte */ - *((uint32_t *)pdata) = (hdsi->Instance->GPDR); - if (datasize > 4U) - { - datasize -= 4U; - pdata += 4U; - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Get the remaining bytes if any */ - while(((int)(datasize)) > 0U) + /* If DSI fifo is not empty, read requested bytes */ + while(((int)(datasize)) > 0) { if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U) { - *((uint32_t *)pdata) = (hdsi->Instance->GPDR); - datasize -= 4U; - pdata += 4U; + fifoword = hdsi->Instance->GPDR; + nbbytes = (datasize < 4U) ? datasize : 4U; + + for(count = 0U; count < nbbytes; count++) + { + *pdata++ = (uint8_t)(fifoword >> (8U*count)); + datasize--; + } } /* Check for the Timeout */ @@ -1444,7 +1751,7 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, /** * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running * (only data lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1464,7 +1771,7 @@ HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi) /* Wait until the D-PHY active lanes enter into ULPM */ if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) { - while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET) + while((hdsi->Instance->PSR & DSI_PSR_UAN0) != 0U) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) @@ -1478,7 +1785,7 @@ HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi) } else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) { - while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET) + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != 0U) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) @@ -1507,7 +1814,7 @@ HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi) /** * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running * (only data lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1576,7 +1883,7 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) /** * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off * (both data and clock lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1602,7 +1909,7 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) /* Wait until all active lanes exit ULPM */ if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) { - while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET) + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != 0U) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) @@ -1616,7 +1923,7 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) } else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) { - while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET) + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != 0U) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) @@ -1648,7 +1955,7 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) /** * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off * (both data and clock lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1666,7 +1973,7 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) tickstart = HAL_GetTick(); /* Wait for the lock of the PLL */ - while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET) + while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) @@ -1741,13 +2048,13 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) /** * @brief Start test pattern generation - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Mode: Pattern generator mode + * @param Mode Pattern generator mode * This parameter can be one of the following values: * 0 : Color bars (horizontal or vertical) * 1 : BER pattern (vertical only) - * @param Orientation: Pattern generator orientation + * @param Orientation Pattern generator orientation * This parameter can be one of the following values: * 0 : Vertical color bars * 1 : Horizontal color bars @@ -1773,7 +2080,7 @@ HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_ /** * @brief Stop test pattern generation - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1793,13 +2100,13 @@ HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi) /** * @brief Set Slew-Rate And Delay Tuning - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param CommDelay: Communication delay to be adjusted. + * @param CommDelay Communication delay to be adjusted. * This parameter can be any value of @ref DSI_Communication_Delay - * @param Lane: select between clock or data lanes. + * @param Lane select between clock or data lanes. * This parameter can be any value of @ref DSI_Lane_Group - * @param Value: Custom value of the slew-rate or delay + * @param Value Custom value of the slew-rate or delay * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value) @@ -1888,9 +2195,9 @@ HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uin /** * @brief Low-Power Reception Filter Tuning - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Frequency: cutoff frequency of low-pass filter at the input of LPRX + * @param Frequency cutoff frequency of low-pass filter at the input of LPRX * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency) @@ -1911,9 +2218,9 @@ HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t /** * @brief Activate an additional current path on all lanes to meet the SDDTx parameter * defined in the MIPI D-PHY specification - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State) @@ -1936,13 +2243,13 @@ HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State) /** * @brief Custom lane pins configuration - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param CustomLane: Function to be applyed on selected lane. + * @param CustomLane Function to be applyed on selected lane. * This parameter can be any value of @ref DSI_CustomLane - * @param Lane: select between clock or data lane 0 or data lane 1. + * @param Lane select between clock or data lane 0 or data lane 1. * This parameter can be any value of @ref DSI_Lane_Select - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State) @@ -2023,12 +2330,12 @@ HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint /** * @brief Set custom timing for the PHY - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Timing: PHY timing to be adjusted. + * @param Timing PHY timing to be adjusted. * This parameter can be any value of @ref DSI_PHY_Timing - * @param State: ENABLE or DISABLE - * @param Value: Custom value of the timing + * @param State ENABLE or DISABLE + * @param Value Custom value of the timing * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value) @@ -2171,11 +2478,11 @@ HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing /** * @brief Force the Clock/Data Lane in TX Stop Mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Lane: select between clock or data lanes. + * @param Lane select between clock or data lanes. * This parameter can be any value of @ref DSI_Lane_Group - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State) @@ -2215,9 +2522,9 @@ HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane /** * @brief Force LP Receiver in Low-Power Mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State) @@ -2240,9 +2547,9 @@ HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalSta /** * @brief Force Data Lanes in RX Mode after a BTA - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State) @@ -2265,9 +2572,9 @@ HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, Functional /** * @brief Enable a pull-down on the lanes to prevent from floating states when unused - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State) @@ -2290,9 +2597,9 @@ HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState S /** * @brief Switch off the contention detection on data lanes - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State) @@ -2335,7 +2642,7 @@ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, Fun /** * @brief Return the DSI state - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL state */ @@ -2346,7 +2653,7 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi) /** * @brief Return the DSI error code - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval DSI Error Code */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c index 3ec430f2a7..4947e050ae 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c @@ -3,23 +3,23 @@ * @file stm32l4xx_hal_flash.c * @author MCD Application Team * @brief FLASH HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: * + Program operations functions - * + Memory Control functions + * + Memory Control functions * + Peripheral Errors functions - * - @verbatim + * + @verbatim ============================================================================== ##### FLASH peripheral features ##### ============================================================================== - - [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses - to the Flash memory. It implements the erase and program Flash memory operations + + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. - + [..] The Flash memory interface accelerates code execution with a system of instruction - prefetch and cache lines. + prefetch and cache lines. [..] The FLASH main features are: (+) Flash memory read operations @@ -31,36 +31,36 @@ (+) 8 cache lines of 4*64 bits on D-Code (+) Error code correction (ECC) : Data in flash are 72-bits word (8 bits added per double word) - - + + ##### How to use this driver ##### ============================================================================== - [..] - This driver provides functions and macros to configure and program the FLASH - memory of all STM32L4xx devices. - - (#) Flash Memory IO Programming functions: - (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32L4xx devices. + + (#) Flash Memory IO Programming functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and HAL_FLASH_Lock() functions (++) Program functions: double word and fast program (full row programming) (++) There Two modes of programming : (+++) Polling mode using HAL_FLASH_Program() function (+++) Interrupt mode using HAL_FLASH_Program_IT() function - - (#) Interrupts and flags management functions : + + (#) Interrupts and flags management functions : (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() (++) Callback functions are called when the flash operations are finished : HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise HAL_FLASH_OperationErrorCallback() - (++) Get error flag status by calling HAL_GetError() - + (++) Get error flag status by calling HAL_GetError() + (#) Option bytes management functions : (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and HAL_FLASH_OB_Lock() functions (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function. In this case, a reset is generated - - [..] + + [..] In addition to these functions, this driver includes a set of macros allowing to handle the following operations: (+) Set the latency @@ -70,8 +70,8 @@ (+) Enable/Disable the Flash power-down during low-power run and sleep modes (+) Enable/Disable the Flash interrupts (+) Monitor the Flash flags status - - @endverbatim + + @endverbatim ****************************************************************************** * @attention * @@ -119,9 +119,9 @@ /* Private typedef -----------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define FLASH_NB_DOUBLE_WORDS_IN_ROW 64 +#define FLASH_NB_DOUBLE_WORDS_IN_ROW 64 #else -#define FLASH_NB_DOUBLE_WORDS_IN_ROW 32 +#define FLASH_NB_DOUBLE_WORDS_IN_ROW 32 #endif /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -129,9 +129,17 @@ * @{ */ /** - * @brief Variable used for Program/Erase sectors under interruption + * @brief Variable used for Program/Erase sectors under interruption */ -FLASH_ProcessTypeDef pFlash; +extern FLASH_ProcessTypeDef pFlash; +FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \ + .ErrorCode = HAL_FLASH_ERROR_NONE, \ + .ProcedureOnGoing = FLASH_PROC_NONE, \ + .Address = 0U, \ + .Bank = FLASH_BANK_1, \ + .Page = 0U, \ + .NbPagesToErase = 0U, \ + .CacheToReactivate = FLASH_CACHE_DISABLED}; /** * @} */ @@ -143,7 +151,6 @@ FLASH_ProcessTypeDef pFlash; HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); extern void FLASH_PageErase(uint32_t Page, uint32_t Banks); extern void FLASH_FlushCaches(void); -static void FLASH_SetErrorCode(void); static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress); /** @@ -155,37 +162,37 @@ static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress); * @{ */ -/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions - * @brief Programming operation functions +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions * -@verbatim +@verbatim =============================================================================== ##### Programming operation functions ##### =============================================================================== [..] - This subsection provides a set of functions allowing to manage the FLASH + This subsection provides a set of functions allowing to manage the FLASH program operations. - + @endverbatim * @{ */ - + /** * @brief Program double word or fast program of a row at a specified address. * @param TypeProgram: Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program * @param Address: specifies the address to be programmed. * @param Data: specifies the data to be programmed - * This parameter is the data for the double word program and the address where + * This parameter is the data for the double word program and the address where * are stored the data for the row fast program - * + * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; uint32_t prog_bit = 0; - + /* Process Locked */ __HAL_LOCK(&pFlash); @@ -194,13 +201,13 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - + if(status == HAL_OK) { pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Deactivate the data cache if they are activated to avoid data misbehavior */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) + if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); @@ -221,19 +228,23 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint { /* Fast program a 32 row double-word (64-bit) at a specified address */ FLASH_Program_Fast(Address, (uint32_t)Data); - + /* If it is the last row, the bit will be cleared at the end of the operation */ if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST) { prog_bit = FLASH_CR_FSTPG; } } + else + { + /* Nothing to do */ + } /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - + /* If the program operation is completed, disable the PG or FSTPG Bit */ - if (prog_bit != 0) + if (prog_bit != 0U) { CLEAR_BIT(FLASH->CR, prog_bit); } @@ -245,7 +256,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint /* Process Unlocked */ __HAL_UNLOCK(&pFlash); - return status; + return status; } /** @@ -254,9 +265,9 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint * This parameter can be a value of @ref FLASH_Type_Program * @param Address: specifies the address to be programmed. * @param Data: specifies the data to be programmed - * This parameter is the data for the double word program and the address where + * This parameter is the data for the double word program and the address where * are stored the data for the row fast program - * + * * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) @@ -272,7 +283,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Deactivate the data cache if they are activated to avoid data misbehavior */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) + if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); @@ -293,7 +304,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; } pFlash.Address = Address; - + /* Enable End of Operation and Error interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR); @@ -307,8 +318,12 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u /* Fast program a 32 row double-word (64-bit) at a specified address */ FLASH_Program_Fast(Address, (uint32_t)Data); } + else + { + /* Nothing to do */ + } - return status; + return status; } /** @@ -318,6 +333,8 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u void HAL_FLASH_IRQHandler(void) { uint32_t tmp_page; + uint32_t error; + FLASH_ProcedureTypeDef procedure; /* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit */ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB)); @@ -326,7 +343,7 @@ void HAL_FLASH_IRQHandler(void) defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) CLEAR_BIT(FLASH->CR, FLASH_CR_MER2); #endif - + /* Disable the FSTPG Bit only if it is the last row programmed */ if(pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST) { @@ -334,46 +351,46 @@ void HAL_FLASH_IRQHandler(void) } /* Check FLASH operation error flags */ - if((__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) || -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY))) -#else - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD))) -#endif + error = (FLASH->SR & FLASH_FLAG_SR_ERRORS); + error |= (FLASH->ECCR & FLASH_FLAG_ECCC); + + if (error !=0U) { /*Save the error code*/ - FLASH_SetErrorCode(); - + pFlash.ErrorCode |= error; + + /* Clear error programming flags */ + __HAL_FLASH_CLEAR_FLAG(error); + /* Flush the caches to be sure of the data consistency */ FLASH_FlushCaches() ; /* FLASH error interrupt user callback */ - if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE) + procedure = pFlash.ProcedureOnGoing; + if(procedure == FLASH_PROC_PAGE_ERASE) { HAL_FLASH_OperationErrorCallback(pFlash.Page); } - else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASS_ERASE) + else if(procedure == FLASH_PROC_MASS_ERASE) { HAL_FLASH_OperationErrorCallback(pFlash.Bank); } - else if((pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM) || - (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST)) + else if((procedure == FLASH_PROC_PROGRAM) || + (procedure == FLASH_PROC_PROGRAM_LAST)) { HAL_FLASH_OperationErrorCallback(pFlash.Address); } + else + { + /* Nothing to do */ + } /*Stop the procedure ongoing*/ pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } /* Check FLASH End of Operation flag */ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != 0U) { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); @@ -384,7 +401,7 @@ void HAL_FLASH_IRQHandler(void) pFlash.NbPagesToErase--; /* Check if there are still pages to erase*/ - if(pFlash.NbPagesToErase != 0) + if(pFlash.NbPagesToErase != 0U) { /* Indicate user which page has been erased*/ HAL_FLASH_EndOfOperationCallback(pFlash.Page); @@ -398,12 +415,12 @@ void HAL_FLASH_IRQHandler(void) { /* No more pages to Erase */ /* Reset Address and stop Erase pages procedure */ - pFlash.Page = 0xFFFFFFFF; + pFlash.Page = 0xFFFFFFFFU; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; /* Flush the caches to be sure of the data consistency */ FLASH_FlushCaches() ; - + /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(pFlash.Page); } @@ -413,19 +430,24 @@ void HAL_FLASH_IRQHandler(void) /* Flush the caches to be sure of the data consistency */ FLASH_FlushCaches() ; - if(pFlash.ProcedureOnGoing == FLASH_PROC_MASS_ERASE) + procedure = pFlash.ProcedureOnGoing; + if(procedure == FLASH_PROC_MASS_ERASE) { /* MassErase ended. Return the selected bank */ /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(pFlash.Bank); } - else if((pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM) || - (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST)) + else if((procedure == FLASH_PROC_PROGRAM) || + (procedure == FLASH_PROC_PROGRAM_LAST)) { /* Program ended. Return the selected address */ /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(pFlash.Address); } + else + { + /* Nothing to do */ + } /*Clear the procedure ongoing*/ pFlash.ProcedureOnGoing = FLASH_PROC_NONE; @@ -446,7 +468,7 @@ void HAL_FLASH_IRQHandler(void) * @brief FLASH end of operation interrupt callback. * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure * Mass Erase: Bank number which has been requested to erase - * Page Erase: Page which has been erased + * Page Erase: Page which has been erased * (if 0xFFFFFFFF, it means that all the selected pages have been erased) * Program: Address which was selected for data program * @retval None @@ -458,7 +480,7 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) /* NOTE : This function should not be modified, when the callback is needed, the HAL_FLASH_EndOfOperationCallback could be implemented in the user file - */ + */ } /** @@ -476,22 +498,22 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) /* NOTE : This function should not be modified, when the callback is needed, the HAL_FLASH_OperationErrorCallback could be implemented in the user file - */ + */ } /** * @} - */ + */ -/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions - * @brief Management functions +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief Management functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the FLASH + This subsection provides a set of functions allowing to control the FLASH memory operations. @endverbatim @@ -506,19 +528,19 @@ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { HAL_StatusTypeDef status = HAL_OK; - if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) { /* Authorize the FLASH Registers access */ WRITE_REG(FLASH->KEYR, FLASH_KEY1); WRITE_REG(FLASH->KEYR, FLASH_KEY2); /* Verify Flash is unlocked */ - if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) { status = HAL_ERROR; } } - + return status; } @@ -530,8 +552,8 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void) { /* Set the LOCK Bit to lock the FLASH Registers access */ SET_BIT(FLASH->CR, FLASH_CR_LOCK); - - return HAL_OK; + + return HAL_OK; } /** @@ -540,7 +562,7 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void) */ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) { - if(READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != RESET) + if(READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U) { /* Authorizes the Option Byte register programming */ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); @@ -549,21 +571,21 @@ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) else { return HAL_ERROR; - } - - return HAL_OK; + } + + return HAL_OK; } /** * @brief Lock the FLASH Option Bytes Registers access. - * @retval HAL Status + * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) { /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK); - - return HAL_OK; + + return HAL_OK; } /** @@ -573,23 +595,23 @@ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) { /* Set the bit to force the option byte reloading */ - SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); + SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); /* Wait for last operation to be completed */ - return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); + return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); } /** * @} */ -/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral Errors functions +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral Errors functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Errors functions ##### - =============================================================================== + =============================================================================== [..] This subsection permits to get in run-time Errors of the FLASH peripheral. @@ -601,12 +623,12 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) * @brief Get the specific FLASH error flag. * @retval FLASH_ErrorCode: The returned value can be: * @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP) - * @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag - * @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag + * @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag + * @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag * @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag * @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag - * @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag - * @arg HAL_FLASH_ERROR_NONE: No error set + * @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag + * @arg HAL_FLASH_ERROR_NONE: No error set * @arg HAL_FLASH_ERROR_OP: FLASH Operation error * @arg HAL_FLASH_ERROR_PROG: FLASH Programming error * @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error @@ -621,13 +643,13 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) * @arg HAL_FLASH_ERROR_ECCD: FLASH two ECC errors have been detected */ uint32_t HAL_FLASH_GetError(void) -{ +{ return pFlash.ErrorCode; } /** * @} - */ + */ /** * @} @@ -649,36 +671,32 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ - + uint32_t tickstart = HAL_GetTick(); - - while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) - { + uint32_t error; + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) + { if(Timeout != HAL_MAX_DELAY) { if((HAL_GetTick() - tickstart) >= Timeout) { return HAL_TIMEOUT; } - } + } } - - if((__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) || -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY))) -#else - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD))) -#endif + + error = (FLASH->SR & FLASH_FLAG_SR_ERRORS); + error |= (FLASH->ECCR & FLASH_FLAG_ECCD); + + if(error != 0u) { /*Save the error code*/ - FLASH_SetErrorCode(); - + pFlash.ErrorCode |= error; + + /* Clear error programming flags */ + __HAL_FLASH_CLEAR_FLAG(error); + return HAL_ERROR; } @@ -688,86 +706,11 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); } - + /* If there is an error flag set */ - return HAL_OK; + return HAL_OK; } -/** - * @brief Set the specific FLASH error flag. - * @retval None - */ -static void FLASH_SetErrorCode(void) -{ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_OP; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_SIZ; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_MIS; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_FAST; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_ECCD; - } - -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PEMPTY; - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PEMPTY); - } -#endif - - /* Clear error programming flags */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); -} - /** * @brief Program double-word (64-bit) at a specified address. * @param Address: specifies the address to be programmed. @@ -781,10 +724,10 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) /* Set PG bit */ SET_BIT(FLASH->CR, FLASH_CR_PG); - + /* Program the double word */ *(__IO uint32_t*)Address = (uint32_t)Data; - *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32); + *(__IO uint32_t*)(Address+4U) = (uint32_t)(Data >> 32); } /** @@ -804,15 +747,18 @@ static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress) /* Set FSTPG bit */ SET_BIT(FLASH->CR, FLASH_CR_FSTPG); - + /* Disable interrupts to avoid any interruption during the loop */ __disable_irq(); - + /* Program the double word of the row */ do { - *dest_addr++ = *src_addr++; - } while (--row_index != 0); + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + row_index--; + } while (row_index != 0U); /* Re-enable the interrupts */ __enable_irq(); diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c index 97c1364ab3..01826406ff 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c @@ -153,8 +153,8 @@ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PC */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) { - HAL_StatusTypeDef status = HAL_ERROR; - uint32_t page_index = 0; + HAL_StatusTypeDef status; + uint32_t page_index; /* Process Locked */ __HAL_LOCK(&pFlash); @@ -170,12 +170,12 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Deactivate the cache if they are activated to avoid data misbehavior */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET) + if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) { /* Disable instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); - if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) + if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); @@ -186,7 +186,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED; } } - else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) + else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); @@ -218,7 +218,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t else { /*Initialization of PageError variable*/ - *PageError = 0xFFFFFFFF; + *PageError = 0xFFFFFFFFU; for(page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++) { @@ -269,12 +269,12 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Deactivate the cache if they are activated to avoid data misbehavior */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET) + if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) { /* Disable instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); - if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) + if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); @@ -285,7 +285,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED; } } - else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) + else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); @@ -341,7 +341,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Write protection configuration */ - if((pOBInit->OptionType & OPTIONBYTE_WRP) != RESET) + if((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U) { /* Configure of Write protection on the selected area */ if(FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset) != HAL_OK) @@ -352,7 +352,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) } /* Read protection configuration */ - if((pOBInit->OptionType & OPTIONBYTE_RDP) != RESET) + if((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U) { /* Configure the Read protection level */ if(FLASH_OB_RDPConfig(pOBInit->RDPLevel) != HAL_OK) @@ -362,7 +362,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) } /* User Configuration */ - if((pOBInit->OptionType & OPTIONBYTE_USER) != RESET) + if((pOBInit->OptionType & OPTIONBYTE_USER) != 0U) { /* Configure the user option bytes */ if(FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig) != HAL_OK) @@ -372,7 +372,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) } /* PCROP Configuration */ - if((pOBInit->OptionType & OPTIONBYTE_PCROP) != RESET) + if((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U) { if (pOBInit->PCROPStartAddr != pOBInit->PCROPEndAddr) { @@ -472,7 +472,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) */ HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Process Locked */ __HAL_LOCK(&pFlash); @@ -536,14 +536,14 @@ HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE) static void FLASH_MassErase(uint32_t Banks) { #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != RESET) + if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != 0U) #endif { /* Check the parameters */ assert_param(IS_FLASH_BANK(Banks)); /* Set the Mass Erase Bit for the bank 1 if requested */ - if((Banks & FLASH_BANK_1) != RESET) + if((Banks & FLASH_BANK_1) != 0U) { SET_BIT(FLASH->CR, FLASH_CR_MER1); } @@ -552,7 +552,7 @@ static void FLASH_MassErase(uint32_t Banks) defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* Set the Mass Erase Bit for the bank 2 if requested */ - if((Banks & FLASH_BANK_2) != RESET) + if((Banks & FLASH_BANK_2) != 0U) { SET_BIT(FLASH->CR, FLASH_CR_MER2); } @@ -588,7 +588,7 @@ void FLASH_PageErase(uint32_t Page, uint32_t Banks) defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if(READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == RESET) + if(READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U) { CLEAR_BIT(FLASH->CR, FLASH_CR_BKER); } @@ -597,7 +597,7 @@ void FLASH_PageErase(uint32_t Page, uint32_t Banks) { assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks)); - if((Banks & FLASH_BANK_1) != RESET) + if((Banks & FLASH_BANK_1) != 0U) { CLEAR_BIT(FLASH->CR, FLASH_CR_BKER); } @@ -606,10 +606,13 @@ void FLASH_PageErase(uint32_t Page, uint32_t Banks) SET_BIT(FLASH->CR, FLASH_CR_BKER); } } +#else + /* Prevent unused argument(s) compilation warning */ + UNUSED(Banks); #endif /* Proceed to erase the page */ - MODIFY_REG(FLASH->CR, FLASH_CR_PNB, (Page << POSITION_VAL(FLASH_CR_PNB))); + MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((Page & 0xFFU) << FLASH_CR_PNB_Pos)); SET_BIT(FLASH->CR, FLASH_CR_PER); SET_BIT(FLASH->CR, FLASH_CR_STRT); } @@ -620,9 +623,11 @@ void FLASH_PageErase(uint32_t Page, uint32_t Banks) */ void FLASH_FlushCaches(void) { + FLASH_CacheTypeDef cache = pFlash.CacheToReactivate; + /* Flush instruction cache */ - if((pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_ENABLED) || - (pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_DCACHE_ENABLED)) + if((cache == FLASH_CACHE_ICACHE_ENABLED) || + (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED)) { /* Reset instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_RESET(); @@ -631,8 +636,8 @@ void FLASH_FlushCaches(void) } /* Flush data cache */ - if((pFlash.CacheToReactivate == FLASH_CACHE_DCACHE_ENABLED) || - (pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_DCACHE_ENABLED)) + if((cache == FLASH_CACHE_DCACHE_ENABLED) || + (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED)) { /* Reset data cache */ __HAL_FLASH_DATA_CACHE_RESET(); @@ -673,7 +678,7 @@ void FLASH_FlushCaches(void) */ static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check the parameters */ assert_param(IS_OB_WRPAREA(WRPArea)); @@ -710,6 +715,10 @@ static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartO (WRPStartOffset | (WRDPEndOffset << 16))); } #endif + else + { + /* Nothing to do */ + } /* Set OPTSTRT Bit */ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); @@ -744,7 +753,7 @@ static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartO */ static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check the parameters */ assert_param(IS_OB_RDP_LEVEL(RDPLevel)); @@ -790,7 +799,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon { uint32_t optr_reg_val = 0; uint32_t optr_reg_mask = 0; - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check the parameters */ assert_param(IS_OB_USER_TYPE(UserType)); @@ -800,7 +809,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon if(status == HAL_OK) { - if((UserType & OB_USER_BOR_LEV) != RESET) + if((UserType & OB_USER_BOR_LEV) != 0U) { /* BOR level option byte should be modified */ assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV)); @@ -810,7 +819,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon optr_reg_mask |= FLASH_OPTR_BOR_LEV; } - if((UserType & OB_USER_nRST_STOP) != RESET) + if((UserType & OB_USER_nRST_STOP) != 0U) { /* nRST_STOP option byte should be modified */ assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP)); @@ -820,7 +829,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon optr_reg_mask |= FLASH_OPTR_nRST_STOP; } - if((UserType & OB_USER_nRST_STDBY) != RESET) + if((UserType & OB_USER_nRST_STDBY) != 0U) { /* nRST_STDBY option byte should be modified */ assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY)); @@ -830,7 +839,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon optr_reg_mask |= FLASH_OPTR_nRST_STDBY; } - if((UserType & OB_USER_nRST_SHDW) != RESET) + if((UserType & OB_USER_nRST_SHDW) != 0U) { /* nRST_SHDW option byte should be modified */ assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW)); @@ -840,7 +849,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon optr_reg_mask |= FLASH_OPTR_nRST_SHDW; } - if((UserType & OB_USER_IWDG_SW) != RESET) + if((UserType & OB_USER_IWDG_SW) != 0U) { /* IWDG_SW option byte should be modified */ assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW)); @@ -850,7 +859,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon optr_reg_mask |= FLASH_OPTR_IWDG_SW; } - if((UserType & OB_USER_IWDG_STOP) != RESET) + if((UserType & OB_USER_IWDG_STOP) != 0U) { /* IWDG_STOP option byte should be modified */ assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP)); @@ -860,7 +869,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon optr_reg_mask |= FLASH_OPTR_IWDG_STOP; } - if((UserType & OB_USER_IWDG_STDBY) != RESET) + if((UserType & OB_USER_IWDG_STDBY) != 0U) { /* IWDG_STDBY option byte should be modified */ assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY)); @@ -870,7 +879,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon optr_reg_mask |= FLASH_OPTR_IWDG_STDBY; } - if((UserType & OB_USER_WWDG_SW) != RESET) + if((UserType & OB_USER_WWDG_SW) != 0U) { /* WWDG_SW option byte should be modified */ assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW)); @@ -883,7 +892,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if((UserType & OB_USER_BFB2) != RESET) + if((UserType & OB_USER_BFB2) != 0U) { /* BFB2 option byte should be modified */ assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2)); @@ -893,7 +902,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon optr_reg_mask |= FLASH_OPTR_BFB2; } - if((UserType & OB_USER_DUALBANK) != RESET) + if((UserType & OB_USER_DUALBANK) != 0U) { #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* DUALBANK option byte should be modified */ @@ -913,7 +922,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon } #endif - if((UserType & OB_USER_nBOOT1) != RESET) + if((UserType & OB_USER_nBOOT1) != 0U) { /* nBOOT1 option byte should be modified */ assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1)); @@ -923,7 +932,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon optr_reg_mask |= FLASH_OPTR_nBOOT1; } - if((UserType & OB_USER_SRAM2_PE) != RESET) + if((UserType & OB_USER_SRAM2_PE) != 0U) { /* SRAM2_PE option byte should be modified */ assert_param(IS_OB_USER_SRAM2_PARITY(UserConfig & FLASH_OPTR_SRAM2_PE)); @@ -933,7 +942,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon optr_reg_mask |= FLASH_OPTR_SRAM2_PE; } - if((UserType & OB_USER_SRAM2_RST) != RESET) + if((UserType & OB_USER_SRAM2_RST) != 0U) { /* SRAM2_RST option byte should be modified */ assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST)); @@ -947,7 +956,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if((UserType & OB_USER_nSWBOOT0) != RESET) + if((UserType & OB_USER_nSWBOOT0) != 0U) { /* nSWBOOT0 option byte should be modified */ assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0)); @@ -957,7 +966,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon optr_reg_mask |= FLASH_OPTR_nSWBOOT0; } - if((UserType & OB_USER_nBOOT0) != RESET) + if((UserType & OB_USER_nBOOT0) != 0U) { /* nBOOT0 option byte should be modified */ assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0)); @@ -1006,8 +1015,8 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon */ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr) { - HAL_StatusTypeDef status = HAL_OK; - uint32_t reg_value = 0; + HAL_StatusTypeDef status; + uint32_t reg_value; uint32_t bank1_addr; #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) || \ @@ -1030,7 +1039,7 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCR defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* Get the information about the bank swapping */ - if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0) + if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U) { bank1_addr = FLASH_BASE; bank2_addr = FLASH_BASE + FLASH_BANK_SIZE; @@ -1045,7 +1054,7 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCR #endif #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == RESET) + if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U) { /* Configure the Proprietary code readout protection */ if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1) @@ -1064,6 +1073,10 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCR reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4); MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value); } + else + { + /* Nothing to do */ + } } else #endif @@ -1089,6 +1102,10 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCR MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value); } #endif + else + { + /* Nothing to do */ + } } MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP, (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP)); @@ -1151,6 +1168,10 @@ static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_ *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> 16); } #endif + else + { + /* Nothing to do */ + } } /** @@ -1163,8 +1184,9 @@ static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_ */ static uint32_t FLASH_OB_GetRDP(void) { - if ((READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_0) && - (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_2)) + uint32_t rdp_level = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP); + + if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2)) { return (OB_RDP_LEVEL_1); } @@ -1211,7 +1233,7 @@ static uint32_t FLASH_OB_GetUser(void) */ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr) { - uint32_t reg_value = 0; + uint32_t reg_value; uint32_t bank1_addr; #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) || \ @@ -1223,7 +1245,7 @@ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* Get the information about the bank swapping */ - if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0) + if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U) { bank1_addr = FLASH_BASE; bank2_addr = FLASH_BASE + FLASH_BANK_SIZE; @@ -1238,7 +1260,7 @@ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, #endif #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == RESET) + if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U) { if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1) { @@ -1256,6 +1278,10 @@ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END); *PCROPEndAddr = (reg_value << 4) + FLASH_BASE; } + else + { + /* Nothing to do */ + } } else #endif @@ -1280,6 +1306,10 @@ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, *PCROPEndAddr = (reg_value << 3) + bank2_addr; } #endif + else + { + /* Nothing to do */ + } } *PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP); diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c index 9bedb7c50b..4b9791f502 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c @@ -164,7 +164,7 @@ __RAM_FUNC HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig) /* Disable Flash prefetch */ __HAL_FLASH_PREFETCH_BUFFER_DISABLE(); - if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET) + if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) { /* Disable Flash instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); @@ -173,7 +173,7 @@ __RAM_FUNC HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig) __HAL_FLASH_INSTRUCTION_CACHE_RESET(); } - if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) + if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable Flash data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); @@ -184,32 +184,32 @@ __RAM_FUNC HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig) /* Disable WRP zone 1 of 1st bank if needed */ reg = FLASH->WRP1AR; - if (((reg & FLASH_WRP1AR_WRP1A_STRT) >> POSITION_VAL(FLASH_WRP1AR_WRP1A_STRT)) <= - ((reg & FLASH_WRP1AR_WRP1A_END) >> POSITION_VAL(FLASH_WRP1AR_WRP1A_END))) + if (((reg & FLASH_WRP1AR_WRP1A_STRT) >> FLASH_WRP1AR_WRP1A_STRT_Pos) <= + ((reg & FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos)) { MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), FLASH_WRP1AR_WRP1A_STRT); } /* Disable WRP zone 2 of 1st bank if needed */ reg = FLASH->WRP1BR; - if (((reg & FLASH_WRP1BR_WRP1B_STRT) >> POSITION_VAL(FLASH_WRP1BR_WRP1B_STRT)) <= - ((reg & FLASH_WRP1BR_WRP1B_END) >> POSITION_VAL(FLASH_WRP1BR_WRP1B_END))) + if (((reg & FLASH_WRP1BR_WRP1B_STRT) >> FLASH_WRP1BR_WRP1B_STRT_Pos) <= + ((reg & FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos)) { MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), FLASH_WRP1BR_WRP1B_STRT); } /* Disable WRP zone 1 of 2nd bank if needed */ reg = FLASH->WRP2AR; - if (((reg & FLASH_WRP2AR_WRP2A_STRT) >> POSITION_VAL(FLASH_WRP2AR_WRP2A_STRT)) <= - ((reg & FLASH_WRP2AR_WRP2A_END) >> POSITION_VAL(FLASH_WRP2AR_WRP2A_END))) + if (((reg & FLASH_WRP2AR_WRP2A_STRT) >> FLASH_WRP2AR_WRP2A_STRT_Pos) <= + ((reg & FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos)) { MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), FLASH_WRP2AR_WRP2A_STRT); } /* Disable WRP zone 2 of 2nd bank if needed */ reg = FLASH->WRP2BR; - if (((reg & FLASH_WRP2BR_WRP2B_STRT) >> POSITION_VAL(FLASH_WRP2BR_WRP2B_STRT)) <= - ((reg & FLASH_WRP2BR_WRP2B_END) >> POSITION_VAL(FLASH_WRP2BR_WRP2B_END))) + if (((reg & FLASH_WRP2BR_WRP2B_STRT) >> FLASH_WRP2BR_WRP2B_STRT_Pos) <= + ((reg & FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos)) { MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), FLASH_WRP2BR_WRP2B_STRT); } @@ -222,13 +222,14 @@ __RAM_FUNC HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig) /* Wait for last operation to be completed */ /* 8 is the number of required instruction cycles for the below loop statement (timeout expressed in ms) */ - count = FLASH_TIMEOUT_VALUE * (SystemCoreClock / 8 / 1000); + count = FLASH_TIMEOUT_VALUE * (SystemCoreClock / 8U / 1000U); do { - if (count-- == 0) + if (count == 0U) { break; } + count--; } while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET); /* If the option byte program operation is completed, disable the OPTSTRT Bit */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gfxmmu.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gfxmmu.c index d4a65ac215..9e1798ea06 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gfxmmu.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gfxmmu.c @@ -53,6 +53,50 @@ HAL_NVIC_DisableIRQ(). (#) De-initialize GFXMMU using the HAL_GFXMMU_DeInit() function. + *** Callback registration *** + ============================= + + The compilation define USE_HAL_GFXMMU_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use functions @ref HAL_GFXMMU_RegisterCallback() to register a user callback. + + Function @ref HAL_GFXMMU_RegisterCallback() allows to register following callbacks: + (+) ErrorCallback : GFXMMU error. + (+) MspInitCallback : GFXMMU MspInit. + (+) MspDeInitCallback : GFXMMU MspDeInit. + This function takes as parameters the HAL peripheral handle, the callback ID + and a pointer to the user callback function. + + Use function @ref HAL_GFXMMU_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_GFXMMU_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the callback ID. + This function allows to reset following callbacks: + (+) ErrorCallback : GFXMMU error. + (+) MspInitCallback : GFXMMU MspInit. + (+) MspDeInitCallback : GFXMMU MspDeInit. + + By default, after the @ref HAL_GFXMMU_Init and if the state is HAL_GFXMMU_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions: + examples @ref HAL_GFXMMU_ErrorCallback(). + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_GFXMMU_Init + and @ref HAL_GFXMMU_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_GFXMMU_Init and @ref HAL_GFXMMU_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_GFXMMU_RegisterCallback before calling @ref HAL_GFXMMU_DeInit + or @ref HAL_GFXMMU_Init function. + + When the compilation define USE_HAL_GFXMMU_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + @endverbatim ****************************************************************************** * @attention @@ -150,8 +194,20 @@ HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu) assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf3Address)); assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.Interrupts.Activation)); +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) + /* Reset callback pointers to the weak predefined callbacks */ + hgfxmmu->ErrorCallback = HAL_GFXMMU_ErrorCallback; + + /* Call GFXMMU MSP init function */ + if(hgfxmmu->MspInitCallback == NULL) + { + hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit; + } + hgfxmmu->MspInitCallback(hgfxmmu); +#else /* Call GFXMMU MSP init function */ HAL_GFXMMU_MspInit(hgfxmmu); +#endif /* Configure blocks per line and interrupts parameters on GFXMMU_CR register */ hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0OIE | GFXMMU_CR_B1OIE | GFXMMU_CR_B2OIE | GFXMMU_CR_B3OIE | @@ -206,7 +262,15 @@ HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu) GFXMMU_CR_AMEIE); /* Call GFXMMU MSP de-init function */ +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) + if(hgfxmmu->MspDeInitCallback == NULL) + { + hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit; + } + hgfxmmu->MspDeInitCallback(hgfxmmu); +#else HAL_GFXMMU_MspDeInit(hgfxmmu); +#endif /* Set GFXMMU to reset state */ hgfxmmu->State = HAL_GFXMMU_STATE_RESET; @@ -245,6 +309,150 @@ __weak void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu) */ } +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) +/** + * @brief Register a user GFXMMU callback + * to be used instead of the weak predefined callback. + * @param hgfxmmu GFXMMU handle. + * @param CallbackID ID of the callback to be registered. + * This parameter can be one of the following values: + * @arg @ref HAL_GFXMMU_ERROR_CB_ID error callback ID. + * @arg @ref HAL_GFXMMU_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_GFXMMU_MSPDEINIT_CB_ID MSP de-init callback ID. + * @param pCallback pointer to the callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu, + HAL_GFXMMU_CallbackIDTypeDef CallbackID, + pGFXMMU_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + else + { + if(HAL_GFXMMU_STATE_READY == hgfxmmu->State) + { + switch (CallbackID) + { + case HAL_GFXMMU_ERROR_CB_ID : + hgfxmmu->ErrorCallback = pCallback; + break; + case HAL_GFXMMU_MSPINIT_CB_ID : + hgfxmmu->MspInitCallback = pCallback; + break; + case HAL_GFXMMU_MSPDEINIT_CB_ID : + hgfxmmu->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_GFXMMU_STATE_RESET == hgfxmmu->State) + { + switch (CallbackID) + { + case HAL_GFXMMU_MSPINIT_CB_ID : + hgfxmmu->MspInitCallback = pCallback; + break; + case HAL_GFXMMU_MSPDEINIT_CB_ID : + hgfxmmu->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief Unregister a user GFXMMU callback. + * GFXMMU callback is redirected to the weak predefined callback. + * @param hgfxmmu GFXMMU handle. + * @param CallbackID ID of the callback to be unregistered. + * This parameter can be one of the following values: + * @arg @ref HAL_GFXMMU_ERROR_CB_ID error callback ID. + * @arg @ref HAL_GFXMMU_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_GFXMMU_MSPDEINIT_CB_ID MSP de-init callback ID. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu, + HAL_GFXMMU_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(HAL_GFXMMU_STATE_READY == hgfxmmu->State) + { + switch (CallbackID) + { + case HAL_GFXMMU_ERROR_CB_ID : + hgfxmmu->ErrorCallback = HAL_GFXMMU_ErrorCallback; + break; + case HAL_GFXMMU_MSPINIT_CB_ID : + hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit; + break; + case HAL_GFXMMU_MSPDEINIT_CB_ID : + hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit; + break; + default : + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_GFXMMU_STATE_RESET == hgfxmmu->State) + { + switch (CallbackID) + { + case HAL_GFXMMU_MSPINIT_CB_ID : + hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit; + break; + case HAL_GFXMMU_MSPDEINIT_CB_ID : + hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit; + break; + default : + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + return status; +} +#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */ + /** * @} */ @@ -403,7 +611,7 @@ HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU *((uint32_t *)lutxl_address) = (lutLine->LineStatus | (lutLine->FirstVisibleBlock << GFXMMU_LUTXL_FVB_OFFSET) | (lutLine->LastVisibleBlock << GFXMMU_LUTXL_LVB_OFFSET)); - *((uint32_t *)lutxh_address) = lutLine->LineOffset; + *((uint32_t *)lutxh_address) = (uint32_t) lutLine->LineOffset; } else { @@ -473,7 +681,11 @@ void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu) hgfxmmu->ErrorCode |= error; /* Call GFXMMU error callback */ +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) + hgfxmmu->ErrorCallback(hgfxmmu); +#else HAL_GFXMMU_ErrorCallback(hgfxmmu); +#endif } } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash.c index 32faf8a668..f2e95930af 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash.c @@ -3,22 +3,22 @@ * @file stm32l4xx_hal_hash.c * @author MCD Application Team * @brief HASH HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the HASH peripheral: * + Initialization and de-initialization methods * + HASH or HMAC processing in polling mode * + HASH or HMAC processing in interrupt mode * + HASH or HMAC processing in DMA mode * + Peripheral State methods - * + HASH or HMAC processing suspension/resumption - * + * + HASH or HMAC processing suspension/resumption + * @verbatim =============================================================================== ##### How to use this driver ##### =============================================================================== [..] The HASH HAL driver can be used as follows: - + (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit(): (##) Enable the HASH interface clock using __HASH_CLK_ENABLE() (##) When resorting to interrupt-based APIs (e.g. HAL_HASH_xxx_Start_IT()) @@ -26,7 +26,7 @@ (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ() (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler() API (##) When resorting to DMA-based APIs (e.g. HAL_HASH_xxx_Start_DMA()) - (+++) Enable the DMAx interface clock using + (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE() (+++) Configure and enable one DMA stream to manage data transfer from memory to peripheral (input stream). Managing data transfer from @@ -35,13 +35,13 @@ using __HAL_LINKDMA() (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Stream: use - HAL_NVIC_SetPriority() and + HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() - + (#)Initialize the HASH HAL using HAL_HASH_Init(). This function: (##) resorts to HAL_HASH_MspInit() for low-level initialization, (##) configures the data type: 1-bit, 8-bit, 16-bit or 32-bit. - + (#)Three processing schemes are available: (##) Polling mode: processing APIs are blocking functions i.e. they process the data and wait till the digest computation is finished, @@ -51,57 +51,105 @@ e.g. HAL_HASH_xxx_Start_IT() for HASH or HAL_HMAC_xxx_Start_IT() for HMAC (##) DMA mode: processing APIs are not blocking functions and the CPU is not used for data transfer i.e. the data transfer is ensured by DMA, - e.g. HAL_HASH_xxx_Start_DMA() for HASH or HAL_HMAC_xxx_Start_DMA() - for HMAC. Note that in DMA mode, a call to HAL_HASH_xxx_Finish() + e.g. HAL_HASH_xxx_Start_DMA() for HASH or HAL_HMAC_xxx_Start_DMA() + for HMAC. Note that in DMA mode, a call to HAL_HASH_xxx_Finish() is then required to retrieve the digest. - - (#)When the processing function is called after HAL_HASH_Init(), the HASH peripheral is + + (#)When the processing function is called after HAL_HASH_Init(), the HASH peripheral is initialized and processes the buffer fed in input. When the input data have all been fed to the IP, the digest computation can start. - - (#)Multi-buffer processing is possible in polling and DMA mode. - (##) In polling mode, only multi-buffer HASH processing is possible. + + (#)Multi-buffer processing is possible in polling and DMA mode. + (##) In polling mode, only multi-buffer HASH processing is possible. API HAL_HASH_xxx_Accumulate() must be called for each input buffer, except for the last one. - User must resort to HAL_HASH_xxx_Start() to enter the last one and retrieve as + User must resort to HAL_HASH_xxx_Start() to enter the last one and retrieve as well the computed digest. - + (##) In DMA mode, multi-buffer HASH and HMAC processing are possible. (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro. From that point, each buffer can be fed to the IP thru HAL_HASH_xxx_Start_DMA() API. Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT() macro then wrap-up the HASH processing in feeding the last input buffer thru the - same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to + same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to API HAL_HASH_xxx_Finish(). - - (+++) HMAC processing (requires to resort to extended functions): + + (+++) HMAC processing (requires to resort to extended functions): after initialization, the key and the first input buffer are entered in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and starts step 2. The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this point, the HMAC processing is still carrying out step 2. - Then, step 2 for the last input buffer and step 3 are carried out by a single call + Then, step 2 for the last input buffer and step 3 are carried out by a single call to HAL_HMACEx_xxx_Step2_3_DMA(). - + The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish(). - - - (#)Context swapping. - (##) Two APIs are available to suspend HASH or HMAC processing: + + + (#)Context swapping. + (##) Two APIs are available to suspend HASH or HMAC processing: (+++) HAL_HASH_SwFeed_ProcessSuspend() when data are entered by software (polling or IT mode), - (+++) HAL_HASH_DMAFeed_ProcessSuspend() when data are entered by DMA. - + (+++) HAL_HASH_DMAFeed_ProcessSuspend() when data are entered by DMA. + (##) When HASH or HMAC processing is suspended, HAL_HASH_ContextSaving() allows to save in memory the IP context. This context can be restored afterwards to resume the HASH processing thanks to HAL_HASH_ContextRestoring(). - + (##) Once the HASH IP has been restored to the same configuration as that at suspension time, processing can be restarted with the same API call (same API, same handle, - same parameters) as done before the suspension. Relevant parameters to restart at - the proper location are internally saved in the HASH handle. - + same parameters) as done before the suspension. Relevant parameters to restart at + the proper location are internally saved in the HASH handle. + (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral. + *** Callback registration *** + =================================== + [..] + (#) The compilation define USE_HAL_HASH_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use function @ref HAL_HASH_RegisterCallback() to register a user callback. + + (#) Function @ref HAL_HASH_RegisterCallback() allows to register following callbacks: + (+) InCpltCallback : callback for input completion. + (+) DgstCpltCallback : callback for digest computation completion. + (+) ErrorCallback : callback for error. + (+) MspInitCallback : HASH MspInit. + (+) MspDeInitCallback : HASH MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + (#) Use function @ref HAL_HASH_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) InCpltCallback : callback for input completion. + (+) DgstCpltCallback : callback for digest computation completion. + (+) ErrorCallback : callback for error. + (+) MspInitCallback : HASH MspInit. + (+) MspDeInitCallback : HASH MspDeInit. + + (#) By default, after the @ref HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions: + examples @ref HAL_HASH_InCpltCallback(), @ref HAL_HASH_DgstCpltCallback() + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_HASH_Init + and @ref HAL_HASH_DeInit only when these callbacks are null (not registered beforehand) + If not, MspInit or MspDeInit are not null, the @ref HAL_HASH_Init and @ref HAL_HASH_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_HASH_RegisterCallback before calling @ref HAL_HASH_DeInit + or @ref HAL_HASH_Init function. + + When The compilation define USE_HAL_HASH_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + @endverbatim ****************************************************************************** * @attention @@ -130,8 +178,8 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -154,40 +202,40 @@ /** @defgroup HASH_Private_Constants HASH Private Constants * @{ */ - -/** @defgroup HASH_Digest_Calculation_Status HASH Digest Calculation Status + +/** @defgroup HASH_Digest_Calculation_Status HASH Digest Calculation Status * @{ - */ -#define HASH_DIGEST_CALCULATION_NOT_STARTED ((uint32_t)0x00000000) /*!< DCAL not set after input data written in DIN register */ + */ +#define HASH_DIGEST_CALCULATION_NOT_STARTED ((uint32_t)0x00000000) /*!< DCAL not set after input data written in DIN register */ #define HASH_DIGEST_CALCULATION_STARTED ((uint32_t)0x00000001) /*!< DCAL set after input data written in DIN register */ /** * @} - */ + */ -/** @defgroup HASH_Number_Of_CSR_Registers HASH Number of Context Swap Registers +/** @defgroup HASH_Number_Of_CSR_Registers HASH Number of Context Swap Registers * @{ - */ -#define HASH_NUMBER_OF_CSR_REGISTERS 54 /*!< Number of Context Swap Registers */ + */ +#define HASH_NUMBER_OF_CSR_REGISTERS 54 /*!< Number of Context Swap Registers */ /** * @} - */ - -/** @defgroup HASH_TimeOut_Value HASH TimeOut Value + */ + +/** @defgroup HASH_TimeOut_Value HASH TimeOut Value * @{ - */ + */ #define HASH_TIMEOUTVALUE 1000 /*!< Time-out value */ /** * @} */ - -/** @defgroup HASH_DMA_Suspension_Words_Limit HASH DMA suspension words limit + +/** @defgroup HASH_DMA_Suspension_Words_Limit HASH DMA suspension words limit * @{ - */ + */ #define HASH_DMA_SUSPENSION_WORDS_LIMIT 20 /*!< Number of words below which DMA suspension is aborted */ /** * @} - */ - + */ + /** * @} */ @@ -197,7 +245,7 @@ /* Private function prototypes -----------------------------------------------*/ /** @defgroup HASH_Private_Functions HASH Private Functions * @{ - */ + */ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma); static void HASH_DMAError(DMA_HandleTypeDef *hdma); static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size); @@ -214,28 +262,28 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim * @{ */ -/** @defgroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization, configuration and call-back functions. +/** @defgroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization, configuration and call-back functions. * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Initialize the HASH according to the specified parameters + (+) Initialize the HASH according to the specified parameters in the HASH_InitTypeDef and create the associated handle (+) DeInitialize the HASH peripheral (+) Initialize the HASH MCU Specific Package (MSP) (+) DeInitialize the HASH MSP - + [..] This section provides as well call back functions definitions for user code to manage: - (+) Input data transfer to IP completion + (+) Input data transfer to IP completion (+) Calculated digest retrieval completion - (+) Error management - - - + (+) Error management + + + @endverbatim * @{ */ @@ -244,11 +292,11 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim * @brief Initialize the HASH according to the specified parameters in the HASH_HandleTypeDef and create the associated handle. * @note Only MDMAT and DATATYPE bits of HASH IP are set by HAL_HASH_Init(), - * other configuration bits are set by HASH or HMAC processing APIs. - * @note MDMAT bit is systematically reset by HAL_HASH_Init(). To set it for - * multi-buffer HASH processing, user needs to resort to + * other configuration bits are set by HASH or HMAC processing APIs. + * @note MDMAT bit is systematically reset by HAL_HASH_Init(). To set it for + * multi-buffer HASH processing, user needs to resort to * __HAL_HASH_SET_MDMAT() macro. For HMAC multi-buffer processing, the - * relevant APIs manage themselves the MDMAT bit. + * relevant APIs manage themselves the MDMAT bit. * @param hhash: HASH handle * @retval HAL status */ @@ -256,13 +304,32 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) { /* Check the parameters */ assert_param(IS_HASH_DATATYPE(hhash->Init.DataType)); - + /* Check the hash handle allocation */ if(hhash == NULL) { return HAL_ERROR; } - + +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + if (hhash->State == HAL_HASH_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hhash->Lock = HAL_UNLOCKED; + + /* Reset Callback pointers in HAL_HASH_STATE_RESET only */ + hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */ + hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */ + hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */ + if(hhash->MspInitCallback == NULL) + { + hhash->MspInitCallback = HAL_HASH_MspInit; + } + + /* Init the low level hardware */ + hhash->MspInitCallback(hhash); + } +#else if(hhash->State == HAL_HASH_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -270,8 +337,9 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) /* Init the low level hardware */ HAL_HASH_MspInit(hhash); - } - + } +#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ + /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; @@ -283,56 +351,73 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) /* Reset digest calculation bridle (MDMAT bit control) */ hhash->DigestCalculationDisable = RESET; /* Set phase to READY */ - hhash->Phase = HAL_HASH_PHASE_READY; - + hhash->Phase = HAL_HASH_PHASE_READY; + /* Set the data type and reset MDMAT bit */ MODIFY_REG(HASH->CR, HASH_CR_DATATYPE|HASH_CR_MDMAT, hhash->Init.DataType); - + /* Reset HASH handle status */ hhash->Status = HAL_OK; - + /* Set the HASH state to Ready */ hhash->State = HAL_HASH_STATE_READY; - + + /* Initialise the error code */ + hhash->ErrorCode = HAL_HASH_ERROR_NONE; + /* Return function status */ return HAL_OK; } /** - * @brief DeInitialize the HASH peripheral. + * @brief DeInitialize the HASH peripheral. * @param hhash: HASH handle. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash) -{ +{ /* Check the HASH handle allocation */ if(hhash == NULL) { return HAL_ERROR; } - + /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; - + /* Set the default HASH phase */ hhash->Phase = HAL_HASH_PHASE_READY; - + /* Reset HashInCount, HashITCounter and HashBuffSize */ hhash->HashInCount = 0; hhash->HashBuffSize = 0; hhash->HashITCounter = 0; /* Reset digest calculation bridle (MDMAT bit control) */ - hhash->DigestCalculationDisable = RESET; - - /* DeInit the low level hardware: CLOCK, NVIC.*/ + hhash->DigestCalculationDisable = RESET; + +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + if(hhash->MspDeInitCallback == NULL) + { + hhash->MspDeInitCallback = HAL_HASH_MspDeInit; + } + + /* DeInit the low level hardware */ + hhash->MspDeInitCallback(hhash); +#else + /* DeInit the low level hardware: CLOCK, NVIC */ HAL_HASH_MspDeInit(hhash); - +#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ + + /* Reset HASH handle status */ - hhash->Status = HAL_OK; - + hhash->Status = HAL_OK; + /* Set the HASH state to Ready */ hhash->State = HAL_HASH_STATE_RESET; - + + /* Initialise the error code */ + hhash->ErrorCode = HAL_HASH_ERROR_NONE; + /* Return function status */ return HAL_OK; } @@ -369,12 +454,12 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) /** * @brief Input data transfer complete call back. - * @note HAL_HASH_InCpltCallback() is called when the complete input message + * @note HAL_HASH_InCpltCallback() is called when the complete input message * has been fed to the IP. This API is invoked only when input data are - * entered under interruption or thru DMA. - * @note In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set), - * HAL_HASH_InCpltCallback() is called at the end of each buffer feeding - * to the IP. + * entered under interruption or thru DMA. + * @note In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set), + * HAL_HASH_InCpltCallback() is called at the end of each buffer feeding + * to the IP. * @param hhash: HASH handle. * @retval None */ @@ -389,8 +474,8 @@ __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash) } /** - * @brief Digest computation complete call back. - * @note HAL_HASH_DgstCpltCallback() is used under interruption, is not + * @brief Digest computation complete call back. + * @note HAL_HASH_DgstCpltCallback() is used under interruption, is not * relevant with DMA. * @param hhash: HASH handle. * @retval None @@ -404,7 +489,7 @@ __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash) HAL_HASH_DgstCpltCallback() can be implemented in the user file. */ } - + /** * @brief Error callback. * @note Code user can resort to hhash->Status (HAL_ERROR, HAL_TIMEOUT,...) @@ -422,33 +507,211 @@ __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash) */ } +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User HASH Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hhash HASH handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID + * @arg @ref HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID + * @arg @ref HAL_HASH_ERROR_CB_ID HASH error Callback ID + * @arg @ref HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID + * @arg @ref HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hhash); + + if(HAL_HASH_STATE_READY == hhash->State) + { + switch (CallbackID) + { + case HAL_HASH_INPUTCPLT_CB_ID : + hhash->InCpltCallback = pCallback; + break; + + case HAL_HASH_DGSTCPLT_CB_ID : + hhash->DgstCpltCallback = pCallback; + break; + + case HAL_HASH_ERROR_CB_ID : + hhash->ErrorCallback = pCallback; + break; + + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = pCallback; + break; + + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_HASH_STATE_RESET == hhash->State) + { + switch (CallbackID) + { + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = pCallback; + break; + + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhash); + return status; +} + +/** + * @brief Unregister a HASH Callback + * HASH Callback is redirected to the weak (surcharged) predefined callback + * @param hhash HASH handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID + * @arg @ref HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID + * @arg @ref HAL_HASH_ERROR_CB_ID HASH error Callback ID + * @arg @ref HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID + * @arg @ref HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID) +{ +HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hhash); + + if(HAL_HASH_STATE_READY == hhash->State) + { + switch (CallbackID) + { + case HAL_HASH_INPUTCPLT_CB_ID : + hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */ + break; + + case HAL_HASH_DGSTCPLT_CB_ID : + hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */ + break; + + case HAL_HASH_ERROR_CB_ID : + hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */ + break; + + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; + + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; + + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_HASH_STATE_RESET == hhash->State) + { + switch (CallbackID) + { + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; + + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; + + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhash); + return status; +} +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ /** * @} */ -/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode - * @brief HASH processing functions using polling mode. +/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode + * @brief HASH processing functions using polling mode. * -@verbatim +@verbatim =============================================================================== ##### Polling mode HASH processing functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in polling mode the hash value using one of the following algorithms: (+) MD5 - (++) HAL_HASH_MD5_Start() - (++) HAL_HASH_MD5_Accumulate() + (++) HAL_HASH_MD5_Start() + (++) HAL_HASH_MD5_Accumulate() (+) SHA1 - (++) HAL_HASH_SHA1_Start() - (++) HAL_HASH_SHA1_Accumulate() - + (++) HAL_HASH_SHA1_Start() + (++) HAL_HASH_SHA1_Accumulate() + [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start(). - + [..] In case of multi-buffer HASH processing (a single digest is computed while several buffers are fed to the IP), the user can resort to successive calls to HAL_HASH_xxx_Accumulate() and wrap-up the digest computation by a call - to HAL_HASH_xxx_Start(). + to HAL_HASH_xxx_Start(). @endverbatim * @{ @@ -456,54 +719,54 @@ __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash) /** * @brief Initialize the HASH peripheral in MD5 mode, next process pInBuffer then - * read the computed digest. + * read the computed digest. * @note Digest is available in pOutBuffer. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes. - * @param Timeout: Timeout value + * @param Timeout: Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) { - return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); + return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); } /** - * @brief If not already done, initialize the HASH peripheral in MD5 mode then + * @brief If not already done, initialize the HASH peripheral in MD5 mode then * processes pInBuffer. - * @note Consecutive calls to HAL_HASH_MD5_Accumulate() can be used to feed + * @note Consecutive calls to HAL_HASH_MD5_Accumulate() can be used to feed * several input buffers back-to-back to the IP that will yield a single - * HASH signature once all buffers have been entered. Wrap-up of input - * buffers feeding and retrieval of digest is done by a call to - * HAL_HASH_MD5_Start(). + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASH_MD5_Start(). * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the IP has already been initialized. + * the IP has already been initialized. * @note Digest is not retrieved by this API, user must resort to HAL_HASH_MD5_Start() * to read it, feeding at the same time the last input buffer to the IP. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the * HASH digest computation is corrupted. Only HAL_HASH_MD5_Start() is able - * to manage the ending buffer with a length in bytes not a multiple of 4. + * to manage the ending buffer with a length in bytes not a multiple of 4. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ +{ return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5); } /** * @brief Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then - * read the computed digest. + * read the computed digest. * @note Digest is available in pOutBuffer. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes. - * @param Timeout: Timeout value + * @param Timeout: Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -512,20 +775,20 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf } /** - * @brief If not already done, initialize the HASH peripheral in SHA1 mode then + * @brief If not already done, initialize the HASH peripheral in SHA1 mode then * processes pInBuffer. - * @note Consecutive calls to HAL_HASH_SHA1_Accumulate() can be used to feed + * @note Consecutive calls to HAL_HASH_SHA1_Accumulate() can be used to feed * several input buffers back-to-back to the IP that will yield a single - * HASH signature once all buffers have been entered. Wrap-up of input - * buffers feeding and retrieval of digest is done by a call to - * HAL_HASH_SHA1_Start(). + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASH_SHA1_Start(). * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the IP has already been initialized. + * the IP has already been initialized. * @note Digest is not retrieved by this API, user must resort to HAL_HASH_SHA1_Start() * to read it, feeding at the same time the last input buffer to the IP. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the * HASH digest computation is corrupted. Only HAL_HASH_SHA1_Start() is able - * to manage the ending buffer with a length in bytes not a multiple of 4. + * to manage the ending buffer with a length in bytes not a multiple of 4. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes, must be a multiple of 4. @@ -542,24 +805,24 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *p */ /** @defgroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode - * @brief HASH processing functions using interrupt mode. + * @brief HASH processing functions using interrupt mode. * -@verbatim +@verbatim =============================================================================== ##### Interruption mode HASH processing functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in interrupt mode the hash value using one of the following algorithms: (+) MD5 - (++) HAL_HASH_MD5_Start_IT() + (++) HAL_HASH_MD5_Start_IT() (+) SHA1 (++) HAL_HASH_SHA1_Start_IT() - + [..] API HAL_HASH_IRQHandler() manages each HASH interruption. - + [..] Note that HAL_HASH_IRQHandler() manages as well HASH IP interruptions when in HMAC processing mode. - + @endverbatim * @{ @@ -567,30 +830,30 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *p /** * @brief Initialize the HASH peripheral in MD5 mode, next process pInBuffer then - * read the computed digest in interruption mode. + * read the computed digest in interruption mode. * @note Digest is available in pOutBuffer. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) -{ +{ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5); } /** * @brief Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then - * read the computed digest in interruption mode. + * read the computed digest in interruption mode. * @note Digest is available in pOutBuffer. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1); @@ -599,10 +862,10 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn /** * @brief Handle HASH interrupt request. * @param hhash: HASH handle. - * @note HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well. + * @note HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well. * @note In case of error reported during the HASH interruption processing, * HAL_HASH_ErrorCallback() API is called so that user code can - * manage the error. The error type is available in hhash->Status field. + * manage the error. The error type is available in hhash->Status field. * @retval None */ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) @@ -610,7 +873,12 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) hhash->Status = HASH_IT(hhash); if (hhash->Status != HAL_OK) { - HAL_HASH_ErrorCallback(hhash); + hhash->ErrorCode |= HAL_HASH_ERROR_IT; +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->ErrorCallback(hhash); +#else + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ /* After error handling by code user, reset HASH handle HAL status */ hhash->Status = HAL_OK; } @@ -621,30 +889,30 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) */ /** @defgroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode - * @brief HASH processing functions using DMA mode. + * @brief HASH processing functions using DMA mode. * -@verbatim +@verbatim =============================================================================== ##### DMA mode HASH processing functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in DMA mode the hash value using one of the following algorithms: (+) MD5 - (++) HAL_HASH_MD5_Start_DMA() - (++) HAL_HASH_MD5_Finish() + (++) HAL_HASH_MD5_Start_DMA() + (++) HAL_HASH_MD5_Finish() (+) SHA1 (++) HAL_HASH_SHA1_Start_DMA() (++) HAL_HASH_SHA1_Finish() - + [..] When resorting to DMA mode to enter the data in the IP, user must resort - to HAL_HASH_xxx_Start_DMA() then read the resulting digest with - HAL_HASH_xxx_Finish(). - + to HAL_HASH_xxx_Start_DMA() then read the resulting digest with + HAL_HASH_xxx_Finish(). + [..] In case of multi-buffer HASH processing, MDMAT bit must first be set before - the successive calls to HAL_HASH_xxx_Start_DMA(). Then, MDMAT bit needs to be + the successive calls to HAL_HASH_xxx_Start_DMA(). Then, MDMAT bit needs to be reset before the last call to HAL_HASH_xxx_Start_DMA(). Digest is finally - retrieved thanks to HAL_HASH_xxx_Finish(). - + retrieved thanks to HAL_HASH_xxx_Finish(). + @endverbatim * @{ @@ -652,47 +920,47 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) /** * @brief Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer - * to feed the input buffer to the IP. + * to feed the input buffer to the IP. * @note Once the DMA transfer is finished, HAL_HASH_MD5_Finish() API must - * be called to retrieve the computed digest. + * be called to retrieve the computed digest. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); +{ + return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } /** * @brief Return the computed digest in MD5 mode. * @note The API waits for DCIS to be set then reads the computed digest. * @note HAL_HASH_MD5_Finish() can be used as well to retrieve the digest in - * HMAC MD5 mode. + * HMAC MD5 mode. * @param hhash: HASH handle. * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes. - * @param Timeout: Timeout value. + * @param Timeout: Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) { - return HASH_Finish(hhash, pOutBuffer, Timeout); + return HASH_Finish(hhash, pOutBuffer, Timeout); } /** * @brief Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer - * to feed the input buffer to the IP. + * to feed the input buffer to the IP. * @note Once the DMA transfer is finished, HAL_HASH_SHA1_Finish() API must - * be called to retrieve the computed digest. + * be called to retrieve the computed digest. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { - return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); + return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -700,15 +968,15 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI * @brief Return the computed digest in SHA1 mode. * @note The API waits for DCIS to be set then reads the computed digest. * @note HAL_HASH_SHA1_Finish() can be used as well to retrieve the digest in - * HMAC SHA1 mode. + * HMAC SHA1 mode. * @param hhash: HASH handle. * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes. - * @param Timeout: Timeout value. + * @param Timeout: Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) -{ - return HASH_Finish(hhash, pOutBuffer, Timeout); +{ + return HASH_Finish(hhash, pOutBuffer, Timeout); } /** @@ -716,18 +984,18 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutB */ /** @defgroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode - * @brief HMAC processing functions using polling mode. + * @brief HMAC processing functions using polling mode. * -@verbatim +@verbatim =============================================================================== ##### Polling mode HMAC processing functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in polling mode the HMAC value using one of the following algorithms: (+) MD5 - (++) HAL_HMAC_MD5_Start() + (++) HAL_HMAC_MD5_Start() (+) SHA1 - (++) HAL_HMAC_SHA1_Start() + (++) HAL_HMAC_SHA1_Start() @endverbatim @@ -736,15 +1004,15 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutB /** * @brief Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then - * read the computed digest. + * read the computed digest. * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes. - * @param Timeout: Timeout value. + * @param Timeout: Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -754,103 +1022,103 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff /** * @brief Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then - * read the computed digest. + * read the computed digest. * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes. - * @param Timeout: Timeout value. + * @param Timeout: Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) -{ +{ return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); } /** * @} */ - - + + /** @defgroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode - * @brief HMAC processing functions using interrupt mode. + * @brief HMAC processing functions using interrupt mode. * -@verbatim +@verbatim =============================================================================== ##### Interrupt mode HMAC processing functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in interrupt mode the HMAC value using one of the following algorithms: (+) MD5 - (++) HAL_HMAC_MD5_Start_IT() + (++) HAL_HMAC_MD5_Start_IT() (+) SHA1 - (++) HAL_HMAC_SHA1_Start_IT() + (++) HAL_HMAC_SHA1_Start_IT() @endverbatim * @{ - */ - + */ + /** * @brief Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then - * read the computed digest in interrupt mode. + * read the computed digest in interrupt mode. * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) -{ +{ return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); -} +} /** * @brief Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then - * read the computed digest in interrupt mode. + * read the computed digest in interrupt mode. * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) -{ +{ return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); -} - +} + /** * @} */ - - + + /** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode - * @brief HMAC processing functions using DMA modes. + * @brief HMAC processing functions using DMA modes. * -@verbatim +@verbatim =============================================================================== ##### DMA mode HMAC processing functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in DMA mode the HMAC value using one of the following algorithms: (+) MD5 - (++) HAL_HMAC_MD5_Start_DMA() + (++) HAL_HMAC_MD5_Start_DMA() (+) SHA1 - (++) HAL_HMAC_SHA1_Start_DMA() - - [..] When resorting to DMA mode to enter the data in the IP for HMAC processing, - user must resort to HAL_HMAC_xxx_Start_DMA() then read the resulting digest - with HAL_HASH_xxx_Finish(). + (++) HAL_HMAC_SHA1_Start_DMA() + + [..] When resorting to DMA mode to enter the data in the IP for HMAC processing, + user must resort to HAL_HMAC_xxx_Start_DMA() then read the resulting digest + with HAL_HASH_xxx_Finish(). @endverbatim * @{ @@ -858,24 +1126,24 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn /** - * @brief Initialize the HASH peripheral in HMAC MD5 mode then initiate the required - * DMA transfers to feed the key and the input buffer to the IP. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASH_MD5_Finish() API must be called to retrieve + * @brief Initialize the HASH peripheral in HMAC MD5 mode then initiate the required + * DMA transfers to feed the key and the input buffer to the IP. + * @note Once the DMA transfers are finished (indicated by hhash->State set back + * to HAL_HASH_STATE_READY), HAL_HASH_MD5_Finish() API must be called to retrieve * the computed digest. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note If MDMAT bit is set before calling this function (multi-buffer - * HASH processing case), the input buffer size (in bytes) must be + * HASH processing case), the input buffer size (in bytes) must be * a multiple of 4 otherwise, the HASH digest computation is corrupted. * For the processing of the last buffer of the thread, MDMAT bit must - * be reset and the buffer length (in bytes) doesn't have to be a - * multiple of 4. + * be reset and the buffer length (in bytes) doesn't have to be a + * multiple of 4. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); @@ -883,24 +1151,24 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn /** - * @brief Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required - * DMA transfers to feed the key and the input buffer to the IP. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASH_SHA1_Finish() API must be called to retrieve + * @brief Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required + * DMA transfers to feed the key and the input buffer to the IP. + * @note Once the DMA transfers are finished (indicated by hhash->State set back + * to HAL_HASH_STATE_READY), HAL_HASH_SHA1_Finish() API must be called to retrieve * the computed digest. - * @note Same key is used for the inner and the outer hash functions; pointer to key and + * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note If MDMAT bit is set before calling this function (multi-buffer - * HASH processing case), the input buffer size (in bytes) must be + * HASH processing case), the input buffer size (in bytes) must be * a multiple of 4 otherwise, the HASH digest computation is corrupted. * For the processing of the last buffer of the thread, MDMAT bit must - * be reset and the buffer length (in bytes) doesn't have to be a - * multiple of 4. + * be reset and the buffer length (in bytes) doesn't have to be a + * multiple of 4. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); @@ -910,33 +1178,33 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI * @} */ -/** @defgroup HASH_Exported_Functions_Group8 Peripheral states functions - * @brief Peripheral State functions. +/** @defgroup HASH_Exported_Functions_Group8 Peripheral states functions + * @brief Peripheral State functions. * -@verbatim +@verbatim =============================================================================== ##### Peripheral State methods ##### - =============================================================================== + =============================================================================== [..] - This section permits to get in run-time the state and the peripheral handle + This section permits to get in run-time the state and the peripheral handle status of the peripheral: - (+) HAL_HASH_GetState() + (+) HAL_HASH_GetState() (+) HAL_HASH_GetStatus() - + [..] Additionally, this subsection provides functions allowing to save and restore - the HASH or HMAC processing context in case of calculation suspension: - (+) HAL_HASH_ContextSaving() - (+) HAL_HASH_ContextRestoring() - + the HASH or HMAC processing context in case of calculation suspension: + (+) HAL_HASH_ContextSaving() + (+) HAL_HASH_ContextRestoring() + [..] This subsection provides functions allowing to suspend the HASH processing (+) when input are fed to the IP by software - (++) HAL_HASH_SwFeed_ProcessSuspend() - (+) when input are fed to the IP by DMA - (++) HAL_HASH_DMAFeed_ProcessSuspend() - - + (++) HAL_HASH_SwFeed_ProcessSuspend() + (+) when input are fed to the IP by DMA + (++) HAL_HASH_DMAFeed_ProcessSuspend() + + @endverbatim * @{ @@ -944,7 +1212,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief Return the HASH handle state. - * @note The API yields the current state of the handle (BUSY, READY,...). + * @note The API yields the current state of the handle (BUSY, READY,...). * @param hhash: HASH handle. * @retval HAL HASH state */ @@ -957,10 +1225,10 @@ HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash) /** * @brief Return the HASH HAL status. * @note The API yields the HAL status of the handle: it is the result of the - * latest HASH processing and allows to report any issue (e.g. HAL_TIMEOUT). + * latest HASH processing and allows to report any issue (e.g. HAL_TIMEOUT). * @param hhash: HASH handle. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash) { return hhash->Status; @@ -968,15 +1236,15 @@ HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash) /** * @brief Save the HASH context in case of processing suspension. - * @param hhash: HASH handle. - * @param pMemBuffer: pointer to the memory buffer where the HASH context - * is saved. + * @param hhash: HASH handle. + * @param pMemBuffer: pointer to the memory buffer where the HASH context + * is saved. * @note The IMR, STR, CR then all the CSR registers are saved - * in that order. Only the r/w bits are read to be restored later on. - * @note By default, all the context swap registers (there are - * HASH_NUMBER_OF_CSR_REGISTERS of those) are saved. + * in that order. Only the r/w bits are read to be restored later on. + * @note By default, all the context swap registers (there are + * HASH_NUMBER_OF_CSR_REGISTERS of those) are saved. * @note pMemBuffer points to a buffer allocated by the user. The buffer size - * must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long. + * must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long. * @retval None */ void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer) @@ -986,37 +1254,37 @@ void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer) uint32_t i = 0; /* Prevent unused argument(s) compilation warning */ - UNUSED(hhash); - + UNUSED(hhash); + /* Save IMR register content */ *(uint32_t*)(mem_ptr) = READ_BIT(HASH->IMR,HASH_IT_DINI|HASH_IT_DCI); - mem_ptr+=4; + mem_ptr+=4; /* Save STR register content */ *(uint32_t*)(mem_ptr) = READ_BIT(HASH->STR,HASH_STR_NBLW); mem_ptr+=4; - /* Save CR register content */ + /* Save CR register content */ *(uint32_t*)(mem_ptr) = READ_BIT(HASH->CR,HASH_CR_DMAE|HASH_CR_DATATYPE|HASH_CR_MODE|HASH_CR_ALGO|HASH_CR_LKEY|HASH_CR_MDMAT); - mem_ptr+=4; + mem_ptr+=4; /* By default, save all CSRs registers */ for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0; i--) { *(uint32_t*)(mem_ptr) = *(uint32_t*)(csr_ptr); mem_ptr+=4; csr_ptr+=4; - } + } } /** * @brief Restore the HASH context in case of processing resumption. - * @param hhash: HASH handle. - * @param pMemBuffer: pointer to the memory buffer where the HASH context - * is stored. + * @param hhash: HASH handle. + * @param pMemBuffer: pointer to the memory buffer where the HASH context + * is stored. * @note The IMR, STR, CR then all the CSR registers are restored - * in that order. Only the r/w bits are restored. + * in that order. Only the r/w bits are restored. * @note By default, all the context swap registers (HASH_NUMBER_OF_CSR_REGISTERS * of those) are restored (all of them have been saved by default - * beforehand). + * beforehand). * @retval None */ void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer) @@ -1024,42 +1292,42 @@ void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer) uint32_t mem_ptr = (uint32_t)pMemBuffer; uint32_t csr_ptr = (uint32_t)HASH->CSR; uint32_t i = 0; - + /* Prevent unused argument(s) compilation warning */ - UNUSED(hhash); + UNUSED(hhash); /* Restore IMR register content */ - WRITE_REG(HASH->IMR, (*(uint32_t*)(mem_ptr))); - mem_ptr+=4; + WRITE_REG(HASH->IMR, (*(uint32_t*)(mem_ptr))); + mem_ptr+=4; /* Restore STR register content */ - WRITE_REG(HASH->STR, (*(uint32_t*)(mem_ptr))); + WRITE_REG(HASH->STR, (*(uint32_t*)(mem_ptr))); + mem_ptr+=4; + /* Restore CR register content */ + WRITE_REG(HASH->CR, (*(uint32_t*)(mem_ptr))); mem_ptr+=4; - /* Restore CR register content */ - WRITE_REG(HASH->CR, (*(uint32_t*)(mem_ptr))); - mem_ptr+=4; - + /* Reset the HASH processor before restoring the Context - Swap Registers (CSR) */ - __HAL_HASH_INIT(); - + Swap Registers (CSR) */ + __HAL_HASH_INIT(); + /* By default, restore all CSR registers */ for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0; i--) { - WRITE_REG((*(uint32_t*)(csr_ptr)), (*(uint32_t*)(mem_ptr))); + WRITE_REG((*(uint32_t*)(csr_ptr)), (*(uint32_t*)(mem_ptr))); mem_ptr+=4; csr_ptr+=4; - } + } } /** * @brief Initiate HASH processing suspension when in polling or interruption mode. * @param hhash: HASH handle. - * @note Set the handle field SuspendRequest to the appropriate value so that - * the on-going HASH processing is suspended as soon as the required + * @note Set the handle field SuspendRequest to the appropriate value so that + * the on-going HASH processing is suspended as soon as the required * conditions are met. Note that the actual suspension is carried out * by the functions HASH_WriteData() in polling mode and HASH_IT() in - * interruption mode. + * interruption mode. * @retval None */ void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) @@ -1071,32 +1339,32 @@ void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) /** * @brief Suspend the HASH processing when in DMA mode. * @param hhash: HASH handle. - * @note When suspension attempt occurs at the very end of a DMA transfer and - * all the data have already been entered in the IP, hhash->State is - * set to HAL_HASH_STATE_READY and the API returns HAL_ERROR. It is - * recommended to wrap-up the processing in reading the digest as usual. + * @note When suspension attempt occurs at the very end of a DMA transfer and + * all the data have already been entered in the IP, hhash->State is + * set to HAL_HASH_STATE_READY and the API returns HAL_ERROR. It is + * recommended to wrap-up the processing in reading the digest as usual. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) { uint32_t tmp_remaining_DMATransferSize_inWords = 0x0; uint32_t tmp_initial_DMATransferSize_inWords = 0x0; - uint32_t tmp_words_already_pushed = 0x0; - + uint32_t tmp_words_already_pushed = 0x0; + if (hhash->State == HAL_HASH_STATE_READY) { return HAL_ERROR; } else - { - + { + /* Make sure there is enough time to suspend the processing */ tmp_remaining_DMATransferSize_inWords = hhash->hdmain->Instance->CNDTR; if (tmp_remaining_DMATransferSize_inWords <= HASH_DMA_SUSPENSION_WORDS_LIMIT) { /* No suspension attempted since almost to the end of the transferred data. */ /* Best option for user code is to wrap up low priority message hashing */ - return HAL_ERROR; + return HAL_ERROR; } /* Wait for DMAS to be reset */ @@ -1104,57 +1372,57 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) { return HAL_TIMEOUT; } - + if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET) { return HAL_ERROR; } - + /* Wait for DMAS to be set */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, RESET, HASH_TIMEOUTVALUE) != HAL_OK) { return HAL_TIMEOUT; - } - + } + /* Disable DMA channel */ - HAL_DMA_Abort(hhash->hdmain); - + HAL_DMA_Abort(hhash->hdmain); + /* Clear DMAE bit */ CLEAR_BIT(HASH->CR,HASH_CR_DMAE); - + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) { return HAL_TIMEOUT; } - + if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET) { return HAL_ERROR; - } - + } + /* At this point, DMA interface is disabled and no transfer is on-going */ /* Retrieve from the DMA handle how many words remain to be written */ tmp_remaining_DMATransferSize_inWords = hhash->hdmain->Instance->CNDTR; if (tmp_remaining_DMATransferSize_inWords == 0) { - /* All the DMA transfer is actually done. Suspension occurred at the very end - of the transfer. Either the digest computation is about to start (HASH case) + /* All the DMA transfer is actually done. Suspension occurred at the very end + of the transfer. Either the digest computation is about to start (HASH case) or processing is about to move from one step to another (HMAC case). In both cases, the processing can't be suspended at this point. It is safer to - - retrieve the low priority block digest before starting the high + - retrieve the low priority block digest before starting the high priority block processing (HASH case) - - re-attempt a new suspension (HMAC case) - */ + - re-attempt a new suspension (HMAC case) + */ return HAL_ERROR; } else { - + /* Compute how many words were supposed to be transferred by DMA */ tmp_initial_DMATransferSize_inWords = (hhash->HashInCount%4 ? (hhash->HashInCount+3)/4: hhash->HashInCount/4); - + /* If discrepancy between the number of words reported by DMA IP and the numbers of words entered as reported by HASH IP, correct it */ /* tmp_words_already_pushed reflects the number of words that were already pushed before @@ -1162,44 +1430,53 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) tmp_words_already_pushed = hhash->NbWordsAlreadyPushed; if ((tmp_words_already_pushed + tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) %16 != HASH_NBW_PUSHED()) { - tmp_remaining_DMATransferSize_inWords--; /* one less word to be transferred again */ + tmp_remaining_DMATransferSize_inWords--; /* one less word to be transferred again */ } - + /* Accordingly, update the input pointer that points at the next word to be transferred to the IP by DMA */ hhash->pHashInBuffPtr += 4 * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ; - + /* And store in HashInCount the remaining size to transfer (in bytes) */ - hhash->HashInCount = 4 * tmp_remaining_DMATransferSize_inWords; - + hhash->HashInCount = 4 * tmp_remaining_DMATransferSize_inWords; + } - - /* Set State as suspended */ - hhash->State = HAL_HASH_STATE_SUSPENDED; - + + /* Set State as suspended */ + hhash->State = HAL_HASH_STATE_SUSPENDED; + return HAL_OK; - + } } - +/** + * @brief Return the HASH handle error code. + * @param hhash: pointer to a HASH_HandleTypeDef structure. + * @retval HASH Error Code +*/ +uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash) +{ + /* Return HASH Error Code */ + return hhash->ErrorCode; +} /** * @} */ - - + + /** * @} */ /** @defgroup HASH_Private_Functions HASH Private Functions * @{ - */ + */ /** - * @brief DMA HASH Input Data transfer completion callback. + * @brief DMA HASH Input Data transfer completion callback. * @param hdma: DMA handle. * @note In case of HMAC processing, HASH_DMAXferCplt() initiates - * the next DMA transfer for the following HMAC step. + * the next DMA transfer for the following HMAC step. * @retval None */ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) @@ -1207,42 +1484,51 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; uint32_t inputaddr = 0x0; uint32_t buffersize = 0x0; - + if (hhash->State != HAL_HASH_STATE_SUSPENDED) { - + /* Disable the DMA transfer */ CLEAR_BIT(HASH->CR, HASH_CR_DMAE); if (READ_BIT(HASH->CR, HASH_CR_MODE) == RESET) { /* If no HMAC processing, input data transfer is now over */ - + /* Change the HASH state to ready */ hhash->State = HAL_HASH_STATE_READY; - + /* Call Input data transfer complete call back */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->InCpltCallback(hhash); +#else HAL_HASH_InCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + } else { /* HMAC processing: depending on the current HMAC step and whether or not multi-buffer processing is on-going, the next step is initiated and MDMAT bit is set. */ - + if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3) { /* This is the end of HMAC processing */ - + /* Change the HASH state to ready */ hhash->State = HAL_HASH_STATE_READY; - - /* Call Input data transfer complete call back - (note that the last DMA transfer was that of the key + + /* Call Input data transfer complete call back + (note that the last DMA transfer was that of the key for the outer HASH operation). */ - HAL_HASH_InCpltCallback(hhash); - +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->InCpltCallback(hhash); +#else + HAL_HASH_InCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + return; } else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) @@ -1250,19 +1536,19 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) inputaddr = (uint32_t)hhash->pHashMsgBuffPtr; /* DMA transfer start address */ buffersize = hhash->HashBuffSize; /* DMA transfer size (in bytes) */ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; /* Move phase from Step 1 to Step 2 */ - + /* In case of suspension request, save the new starting parameters */ hhash->HashInCount = hhash->HashBuffSize; /* Initial DMA transfer size (in bytes) */ hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr ; /* DMA transfer start address */ hhash->NbWordsAlreadyPushed = 0; /* Reset number of words already pushed */ - - /* Check whether or not digest calculation must be disabled (in case of multi-buffer HMAC processing) */ + + /* Check whether or not digest calculation must be disabled (in case of multi-buffer HMAC processing) */ if (hhash->DigestCalculationDisable != RESET) { - /* Digest calculation is disabled: Step 2 must start with MDMAT bit set, + /* Digest calculation is disabled: Step 2 must start with MDMAT bit set, no digest calculation will be triggered at the end of the input buffer feeding to the IP */ - __HAL_HASH_SET_MDMAT(); + __HAL_HASH_SET_MDMAT(); } } else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2) @@ -1275,33 +1561,37 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) Phase remains in Step 2, MDMAT remains set at this point. Change the HASH state to ready and call Input data transfer complete call back. */ hhash->State = HAL_HASH_STATE_READY; - HAL_HASH_InCpltCallback(hhash); - return ; +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->InCpltCallback(hhash); +#else + HAL_HASH_InCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + return ; } else { /* Digest calculation is not disabled (case of single buffer input or last buffer of multi-buffer HMAC processing) */ - inputaddr = (uint32_t)hhash->Init.pKey; /* DMA transfer start address */ + inputaddr = (uint32_t)hhash->Init.pKey; /* DMA transfer start address */ buffersize = hhash->Init.KeySize; /* DMA transfer size (in bytes) */ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; /* Move phase from Step 2 to Step 3 */ /* In case of suspension request, save the new starting parameters */ hhash->HashInCount = hhash->Init.KeySize; /* Initial size for second DMA transfer (input data) */ - hhash->pHashInBuffPtr = hhash->Init.pKey ; /* address passed to DMA, now entering data message */ - + hhash->pHashInBuffPtr = hhash->Init.pKey ; /* address passed to DMA, now entering data message */ + hhash->NbWordsAlreadyPushed = 0; /* Reset number of words already pushed */ } } /* Configure the Number of valid bits in last word of the message */ __HAL_HASH_SET_NBVALIDBITS(buffersize); - - + + /* Set the HASH DMA transfert completion call back */ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; - + /* Enable the DMA In DMA Stream */ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4)); - + /* Enable DMA requests */ SET_BIT(HASH->CR, HASH_CR_DMAE); } @@ -1311,28 +1601,33 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA HASH communication error callback. + * @brief DMA HASH communication error callback. * @param hdma: DMA handle. * @note HASH_DMAError() callback invokes HAL_HASH_ErrorCallback() that - * can contain user code to manage the error. + * can contain user code to manage the error. * @retval None */ static void HASH_DMAError(DMA_HandleTypeDef *hdma) { HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - if (hhash->State != HAL_HASH_STATE_SUSPENDED) + + if (hhash->State != HAL_HASH_STATE_SUSPENDED) { - /* Set HASH state to ready to prevent any blocking issue in user code - present in HAL_HASH_ErrorCallback() */ - hhash->State= HAL_HASH_STATE_READY; - /* Set HASH handle status to error */ - hhash->Status = HAL_ERROR; - HAL_HASH_ErrorCallback(hhash); - /* After error handling by code user, reset HASH handle HAL status */ - hhash->Status = HAL_OK; - - } + hhash->ErrorCode |= HAL_HASH_ERROR_DMA; + /* Set HASH state to ready to prevent any blocking issue in user code + present in HAL_HASH_ErrorCallback() */ + hhash->State= HAL_HASH_STATE_READY; + /* Set HASH handle status to error */ + hhash->Status = HAL_ERROR; +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->ErrorCallback(hhash); +#else + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + /* After error handling by code user, reset HASH handle HAL status */ + hhash->Status = HAL_OK; + + } } /** @@ -1343,33 +1638,33 @@ static void HASH_DMAError(DMA_HandleTypeDef *hdma) * @note HASH_WriteData() regularly reads hhash->SuspendRequest to check whether * or not the HASH processing must be suspended. If this is the case, the * processing is suspended when possible and the IP feeding point reached at - * suspension time is stored in the handle for resumption later on. + * suspension time is stored in the handle for resumption later on. * @retval HAL status */ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { uint32_t buffercounter; __IO uint32_t inputaddr = (uint32_t) pInBuffer; - + for(buffercounter = 0; buffercounter < Size; buffercounter+=4) { /* Write input data 4 bytes at a time */ HASH->DIN = *(uint32_t*)inputaddr; inputaddr+=4; - + /* If the suspension flag has been raised and if the processing is not about to end, suspend processing */ if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4) < Size)) { - /* Wait for DINIS = 1, which occurs when 16 32-bit locations are free + /* Wait for DINIS = 1, which occurs when 16 32-bit locations are free in the input buffer */ - if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) + if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) { /* Reset SuspendRequest */ hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE; - + /* Depending whether the key or the input data were fed to the IP, the feeding point - reached at suspension time is not saved in the same handle fields */ + reached at suspension time is not saved in the same handle fields */ if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)) { /* Save current reading and writing locations of Input and Output buffers */ @@ -1382,7 +1677,7 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB /* Save current reading and writing locations of Input and Output buffers */ hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr; /* Save the number of bytes that remain to be processed at this point */ - hhash->HashKeyCount = Size - (buffercounter + 4); + hhash->HashKeyCount = Size - (buffercounter + 4); } else { @@ -1391,17 +1686,17 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB __HAL_UNLOCK(hhash); return HAL_ERROR; } - + /* Set the HASH state to Suspended and exit to stop entering data */ hhash->State = HAL_HASH_STATE_SUSPENDED; - + return HAL_OK; } /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) */ } /* if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4) < Size)) */ } /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4) */ - + /* At this point, all the data have been entered to the IP: exit */ - return HAL_OK; + return HAL_OK; } /** @@ -1413,7 +1708,7 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) { uint32_t msgdigest = (uint32_t)pMsgDigest; - + switch(Size) { /* Read the message digest */ @@ -1468,7 +1763,7 @@ static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]); msgdigest+=4; *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]); - break; + break; default: break; } @@ -1483,7 +1778,7 @@ static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) * @param Status: the Flag status (SET or RESET). * @param Timeout: Timeout duration. * @retval HAL status - */ + */ static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); @@ -1543,13 +1838,13 @@ static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, * @note HASH_IT() regularly reads hhash->SuspendRequest to check whether * or not the HASH processing must be suspended. If this is the case, the * processing is suspended when possible and the IP feeding point reached at - * suspension time is stored in the handle for resumption later on. + * suspension time is stored in the handle for resumption later on. * @retval HAL status */ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) { if (hhash->State == HAL_HASH_STATE_BUSY) - { + { /* ITCounter must not be equal to 0 at this point. Report an error if this is the case. */ if(hhash->HashITCounter == 0) { @@ -1557,42 +1852,46 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); /* HASH state set back to Ready to prevent any issue in user code present in HAL_HASH_ErrorCallback() */ - hhash->State = HAL_HASH_STATE_READY; + hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; } else if (hhash->HashITCounter == 1) { - /* This is the first call to HASH_IT, the first input data are about to be + /* This is the first call to HASH_IT, the first input data are about to be entered in the IP. A specific processing is carried out at this point to - start-up the processing. */ + start-up the processing. */ hhash->HashITCounter = 2; } else { /* Cruise speed reached, HashITCounter remains equal to 3 until the end of - the HASH processing or the end of the current step for HMAC processing. */ + the HASH processing or the end of the current step for HMAC processing. */ hhash->HashITCounter = 3; } - + /* If digest is ready */ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS)) { /* Read the digest */ HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH()); - + /* Disable Interrupts */ __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); /* Change the HASH state */ hhash->State = HAL_HASH_STATE_READY; /* Call digest computation complete call back */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->DgstCpltCallback(hhash); +#else HAL_HASH_DgstCpltCallback(hhash); - +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + return HAL_OK; - } + } /* If IP ready to accept new data */ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) - { + { /* If the suspension flag has been raised and if the processing is not about to end, suspend processing */ @@ -1600,33 +1899,37 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) { /* Disable Interrupts */ __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); - + /* Reset SuspendRequest */ - hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE; - + hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE; + /* Change the HASH state */ hhash->State = HAL_HASH_STATE_SUSPENDED; - + return HAL_OK; - } - + } + /* Enter input data in the IP thru HASH_Write_Block_Data() call and - check whether the digest calculation has been triggered */ + check whether the digest calculation has been triggered */ if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED) { - /* Call Input data transfer complete call back + /* Call Input data transfer complete call back (called at the end of each step for HMAC) */ - HAL_HASH_InCpltCallback(hhash); - +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->InCpltCallback(hhash); +#else + HAL_HASH_InCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) { /* Wait until IP is not busy anymore */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) { /* Disable Interrupts */ - __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); + __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); return HAL_TIMEOUT; - } + } /* Initialization start for HMAC STEP 2 */ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; /* Move phase from Step 1 to Step 2 */ __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize); /* Set NBLW for the input message */ @@ -1634,29 +1937,29 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr; /* Set the input data address */ hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start of a new phase */ __HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */ - } + } else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2) { /* Wait until IP is not busy anymore */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) { /* Disable Interrupts */ - __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); + __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); return HAL_TIMEOUT; - } + } /* Initialization start for HMAC STEP 3 */ - hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; /* Move phase from Step 2 to Step 3 */ - __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); /* Set NBLW for the key */ - hhash->HashInCount = hhash->Init.KeySize; /* Set the key size (in bytes) */ - hhash->pHashInBuffPtr = hhash->Init.pKey; /* Set the key address */ + hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; /* Move phase from Step 2 to Step 3 */ + __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); /* Set NBLW for the key */ + hhash->HashInCount = hhash->Init.KeySize; /* Set the key size (in bytes) */ + hhash->pHashInBuffPtr = hhash->Init.pKey; /* Set the key address */ hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start of a new phase */ - __HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */ + __HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */ } } /* if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED) */ } /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))*/ /* Return function status */ - return HAL_OK; + return HAL_OK; } else { @@ -1668,16 +1971,16 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) /** * @brief Write a block of data in HASH IP in interruption mode. * @param hhash: HASH handle. - * @note HASH_Write_Block_Data() is called under interruption by HASH_IT(). + * @note HASH_Write_Block_Data() is called under interruption by HASH_IT(). * @retval HAL status */ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) { uint32_t inputaddr; uint32_t buffercounter; - uint32_t inputcounter; + uint32_t inputcounter; uint32_t ret = HASH_DIGEST_CALCULATION_NOT_STARTED; - + /* If there are more than 64 bytes remaining to be entered */ if(hhash->HashInCount > 64) { @@ -1721,8 +2024,8 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) else { /* 64 or less bytes remain to be entered. This is the last - data entering round. */ - + data entering round. */ + /* Get the buffer address */ inputaddr = (uint32_t)hhash->pHashInBuffPtr; /* Get the buffer counter */ @@ -1739,14 +2042,14 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) /* Start the Digest calculation */ __HAL_HASH_START_DIGEST(); /* Return indication that digest calculation has started: - this return value triggers the call to Input data transfer + this return value triggers the call to Input data transfer complete call back as well as the proper transition from - one step to another in HMAC mode. */ - ret = HASH_DIGEST_CALCULATION_STARTED; + one step to another in HMAC mode. */ + ret = HASH_DIGEST_CALCULATION_STARTED; /* Reset buffer counter */ hhash->HashInCount = 0; } - + /* Return whether or digest calculation has started */ return ret; } @@ -1754,9 +2057,9 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) /** * @brief HMAC processing in polling mode. * @param hhash: HASH handle. - * @param Timeout: Timeout value. + * @param Timeout: Timeout value. * @retval HAL status - */ + */ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout) { /* Ensure first that Phase is correct */ @@ -1764,53 +2067,53 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim { /* Change the HASH state */ hhash->State = HAL_HASH_STATE_READY; - + /* Process Unlock */ __HAL_UNLOCK(hhash); - + /* Return function status */ return HAL_ERROR; } - + /* HMAC Step 1 processing */ if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) { /************************** STEP 1 ******************************************/ /* Configure the Number of valid bits in last word of the message */ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - + /* Write input buffer in Data register */ if ((hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount)) != HAL_OK) { return hhash->Status; } - + /* Check whether or not key entering process has been suspended */ if (hhash->State == HAL_HASH_STATE_SUSPENDED) { /* Process Unlocked */ __HAL_UNLOCK(hhash); - + /* Stop right there and return function status */ return HAL_OK; - } - + } + /* No processing suspension at this point: set DCAL bit. */ __HAL_HASH_START_DIGEST(); - + /* Wait for BUSY flag to be cleared */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - + /* Move from Step 1 to Step 2 */ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; - + } - + /* HMAC Step 2 processing. - After phase check, HMAC_Processing() may + After phase check, HMAC_Processing() may - directly start up from this point in resumption case if the same Step 2 processing was suspended previously - or fall through from the Step 1 processing carried out hereabove */ @@ -1819,88 +2122,88 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim /************************** STEP 2 ******************************************/ /* Configure the Number of valid bits in last word of the message */ __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize); - + /* Write input buffer in Data register */ if ((hhash->Status = HASH_WriteData(hhash, hhash->pHashInBuffPtr, hhash->HashInCount)) != HAL_OK) { return hhash->Status; - } - + } + /* Check whether or not data entering process has been suspended */ if (hhash->State == HAL_HASH_STATE_SUSPENDED) { /* Process Unlocked */ __HAL_UNLOCK(hhash); - + /* Stop right there and return function status */ return HAL_OK; - } - + } + /* No processing suspension at this point: set DCAL bit. */ __HAL_HASH_START_DIGEST(); - + /* Wait for BUSY flag to be cleared */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK) { return HAL_TIMEOUT; - } - - /* Move from Step 2 to Step 3 */ - hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; + } + + /* Move from Step 2 to Step 3 */ + hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; /* In case Step 1 phase was suspended then resumed, set again Key input buffers and size before moving to next step */ hhash->pHashKeyBuffPtr = hhash->Init.pKey; hhash->HashKeyCount = hhash->Init.KeySize; } - - + + /* HMAC Step 3 processing. - After phase check, HMAC_Processing() may + After phase check, HMAC_Processing() may - directly start up from this point in resumption case if the same Step 3 processing was suspended previously - or fall through from the Step 2 processing carried out hereabove */ if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3) - { + { /************************** STEP 3 ******************************************/ /* Configure the Number of valid bits in last word of the message */ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - + /* Write input buffer in Data register */ if ((hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount)) != HAL_OK) { return hhash->Status; - } - + } + /* Check whether or not key entering process has been suspended */ if (hhash->State == HAL_HASH_STATE_SUSPENDED) { /* Process Unlocked */ __HAL_UNLOCK(hhash); - + /* Stop right there and return function status */ return HAL_OK; - } - + } + /* No processing suspension at this point: start the Digest calculation. */ __HAL_HASH_START_DIGEST(); - + /* Wait for DCIS flag to be set */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; - } - + } + /* Read the message digest */ HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH()); - } - + } + /* Change the HASH state */ hhash->State = HAL_HASH_STATE_READY; - + /* Process Unlock */ __HAL_UNLOCK(hhash); - + /* Return function status */ return HAL_OK; } @@ -1908,14 +2211,14 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim /** * @brief Initialize the HASH peripheral, next process pInBuffer then - * read the computed digest. + * read the computed digest. * @note Digest is available in pOutBuffer. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. - * @param Timeout: Timeout value. - * @param Algorithm: HASH algorithm. + * @param Timeout: Timeout value. + * @param Algorithm: HASH algorithm. * @retval HAL status */ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm) @@ -1931,102 +2234,102 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; - } + } /* Process Locked */ __HAL_LOCK(hhash); - + /* Check if initialization phase has not been already performed */ if(hhash->Phase == HAL_HASH_PHASE_READY) { /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; - + /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); - + MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); + /* Configure the number of valid bits in last word of the message */ __HAL_HASH_SET_NBVALIDBITS(Size); - - /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as + + /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ - + /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; + hhash->Phase = HAL_HASH_PHASE_PROCESS; } - else if (hhash->Phase == HAL_HASH_PHASE_PROCESS) + else if (hhash->Phase == HAL_HASH_PHASE_PROCESS) { /* if the IP has already been initialized, two cases are possible */ - + /* Process resumption time ... */ if (hhash->State == HAL_HASH_STATE_SUSPENDED) { - /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set + /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set to the API input parameters but to those saved beforehand by HASH_WriteData() when the processing was suspended */ pInBuffer_tmp = hhash->pHashInBuffPtr; Size_tmp = hhash->HashInCount; } /* ... or multi-buffer HASH processing end */ - else + else { - /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as - input parameters of HASH_WriteData() */ + /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as + input parameters of HASH_WriteData() */ pInBuffer_tmp = pInBuffer; - Size_tmp = Size; - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); + Size_tmp = Size; + /* Configure the number of valid bits in last word of the message */ + __HAL_HASH_SET_NBVALIDBITS(Size); } /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; + hhash->State = HAL_HASH_STATE_BUSY; } else { /* Phase error */ hhash->State = HAL_HASH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hhash); - + /* Return function status */ - return HAL_ERROR; + return HAL_ERROR; } - - + + /* Write input buffer in Data register */ if ((hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp)) != HAL_OK) { return hhash->Status; - } - + } + /* If the process has not been suspended, carry on to digest calculation */ if (hhash->State != HAL_HASH_STATE_SUSPENDED) - { + { /* Start the Digest calculation */ __HAL_HASH_START_DIGEST(); - + /* Wait for DCIS flag to be set */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - + /* Read the message digest */ HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH()); - + /* Change the HASH state */ hhash->State = HAL_HASH_STATE_READY; - + } - + /* Process Unlocked */ __HAL_UNLOCK(hhash); - + /* Return function status */ return HAL_OK; - + } else { @@ -2036,120 +2339,120 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint /** - * @brief If not already done, initialize the HASH peripheral then + * @brief If not already done, initialize the HASH peripheral then * processes pInBuffer. * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the IP has already been initialized. + * the IP has already been initialized. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. + * HASH digest computation is corrupted. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes, must be a multiple of 4. - * @param Algorithm: HASH algorithm. + * @param Algorithm: HASH algorithm. * @retval HAL status */ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) { uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ uint32_t Size_tmp = 0x0; /* input data size (in bytes), input parameter of HASH_WriteData() */ - + /* Make sure the input buffer size (in bytes) is a multiple of 4 */ assert_param(IS_HASH_POLLING_MULTIBUFFER_SIZE(Size)); - - + + /* Initiate HASH processing in case of start or resumption */ - if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED)) + if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ if ((pInBuffer == NULL) || (Size == 0)) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; - } - + } + /* Process Locked */ __HAL_LOCK(hhash); - + /* If resuming the HASH processing */ if (hhash->State == HAL_HASH_STATE_SUSPENDED) { /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; - - /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set + + /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set to the API input parameters but to those saved beforehand by HASH_WriteData() when the processing was suspended */ pInBuffer_tmp = hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */ Size_tmp = hhash->HashInCount; /* Size_tmp contains the input data size in bytes */ - + } - else + else { /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as - input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ - Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ - + hhash->State = HAL_HASH_STATE_BUSY; + + /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as + input parameters of HASH_WriteData() */ + pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ + Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ + /* Check if initialization phase has already be performed */ if(hhash->Phase == HAL_HASH_PHASE_READY) { /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); } - + /* Set the phase */ hhash->Phase = HAL_HASH_PHASE_PROCESS; - - } - + + } + /* Write input buffer in Data register */ if ((hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp)) != HAL_OK) { return hhash->Status; - } - + } + /* If the process has not been suspended, move the state to Ready */ if (hhash->State != HAL_HASH_STATE_SUSPENDED) { /* Change the HASH state */ hhash->State = HAL_HASH_STATE_READY; } - + /* Process Unlocked */ __HAL_UNLOCK(hhash); - + /* Return function status */ - return HAL_OK; - + return HAL_OK; + } else { return HAL_BUSY; } - - + + } /** * @brief Initialize the HASH peripheral, next process pInBuffer then - * read the computed digest in interruption mode. + * read the computed digest in interruption mode. * @note Digest is available in pOutBuffer. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. - * @param Algorithm: HASH algorithm. + * @param Algorithm: HASH algorithm. * @retval HAL status - */ + */ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm) { - + /* If State is ready or suspended, start or resume IT-based HASH processing */ - if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED)) + if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ if ((pInBuffer == NULL) || (Size == 0) || (pOutBuffer == NULL)) @@ -2157,47 +2460,47 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; } - + /* Process Locked */ - __HAL_LOCK(hhash); - + __HAL_LOCK(hhash); + /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; - + /* Initialize IT counter */ hhash->HashITCounter = 1; - + /* Check if initialization phase has already be performed */ if(hhash->Phase == HAL_HASH_PHASE_READY) { /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); - + MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); + /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - + __HAL_HASH_SET_NBVALIDBITS(Size); + hhash->HashInCount = Size; /* Counter used to keep track of number of data - to be fed to the IP */ - hhash->pHashInBuffPtr = pInBuffer; /* Points at data which will be fed to the IP at + to be fed to the IP */ + hhash->pHashInBuffPtr = pInBuffer; /* Points at data which will be fed to the IP at the next interruption */ - /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain - the information describing where the HASH process is stopped. - These variables are used later on to resume the HASH processing at the - correct location. */ - - hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ - } - + /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain + the information describing where the HASH process is stopped. + These variables are used later on to resume the HASH processing at the + correct location. */ + + hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ + } + /* Set the phase */ hhash->Phase = HAL_HASH_PHASE_PROCESS; - + /* Process Unlock */ __HAL_UNLOCK(hhash); - + /* Enable Interrupts */ __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI); - + /* Return function status */ return HAL_OK; } @@ -2211,107 +2514,107 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u /** * @brief Initialize the HASH peripheral then initiate a DMA transfer - * to feed the input buffer to the IP. + * to feed the input buffer to the IP. * @note If MDMAT bit is set before calling this function (multi-buffer - * HASH processing case), the input buffer size (in bytes) must be + * HASH processing case), the input buffer size (in bytes) must be * a multiple of 4 otherwise, the HASH digest computation is corrupted. * For the processing of the last buffer of the thread, MDMAT bit must - * be reset and the buffer length (in bytes) doesn't have to be a - * multiple of 4. + * be reset and the buffer length (in bytes) doesn't have to be a + * multiple of 4. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. - * @param Algorithm: HASH algorithm. + * @param Algorithm: HASH algorithm. * @retval HAL status - */ + */ HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) -{ +{ uint32_t inputaddr; uint32_t inputSize = 0x0; - - /* Make sure the input buffer size (in bytes) is a multiple of 4 when MDMAT bit is set + + /* Make sure the input buffer size (in bytes) is a multiple of 4 when MDMAT bit is set (case of multi-buffer HASH processing) */ assert_param(IS_HASH_DMA_MULTIBUFFER_SIZE(Size)); - + /* If State is ready or suspended, start or resume DMA-based HASH processing */ if ((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED)) { - /* Check input parameters */ + /* Check input parameters */ if ( (pInBuffer == NULL ) || (Size == 0) || - /* Check phase coherency. Phase must be + /* Check phase coherency. Phase must be either READY (fresh start) - or PROCESS (multi-buffer HASH management) */ + or PROCESS (multi-buffer HASH management) */ ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HASH_PROCESSING(hhash))))) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; } - - + + /* Process Locked */ __HAL_LOCK(hhash); - + /* If not a resumption case */ if (hhash->State == HAL_HASH_STATE_READY) { /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Check if initialization phase has already been performed. + hhash->State = HAL_HASH_STATE_BUSY; + + /* Check if initialization phase has already been performed. If Phase is already set to HAL_HASH_PHASE_PROCESS, this means the - API is processing a new input data message in case of multi-buffer HASH + API is processing a new input data message in case of multi-buffer HASH computation. */ if(hhash->Phase == HAL_HASH_PHASE_READY) { /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); - + MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); + /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; + hhash->Phase = HAL_HASH_PHASE_PROCESS; } - + /* Configure the Number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - - inputaddr = (uint32_t)pInBuffer; /* DMA transfer start address */ - inputSize = Size; /* DMA transfer size (in bytes) */ - + __HAL_HASH_SET_NBVALIDBITS(Size); + + inputaddr = (uint32_t)pInBuffer; /* DMA transfer start address */ + inputSize = Size; /* DMA transfer size (in bytes) */ + /* In case of suspension request, save the starting parameters */ hhash->pHashInBuffPtr = pInBuffer; /* DMA transfer start address */ - hhash->HashInCount = Size; /* DMA transfer size (in bytes) */ - + hhash->HashInCount = Size; /* DMA transfer size (in bytes) */ + } /* If resumption case */ else { /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Resumption case, inputaddr and inputSize are not set to the API input parameters - but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the - processing was suspended */ - inputaddr = (uint32_t)hhash->pHashInBuffPtr; /* DMA transfer start address */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Resumption case, inputaddr and inputSize are not set to the API input parameters + but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the + processing was suspended */ + inputaddr = (uint32_t)hhash->pHashInBuffPtr; /* DMA transfer start address */ inputSize = hhash->HashInCount; /* DMA transfer size (in bytes) */ - + } - + /* Set the HASH DMA transfert complete callback */ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; /* Set the DMA error callback */ hhash->hdmain->XferErrorCallback = HASH_DMAError; /* Store number of words already pushed to manage proper DMA processing suspension */ - hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED(); - + hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED(); + /* Enable the DMA In DMA Stream */ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (inputSize%4 ? (inputSize+3)/4:inputSize/4)); - + /* Enable DMA requests */ SET_BIT(HASH->CR, HASH_CR_DMAE); - + /* Process Unlock */ __HAL_UNLOCK(hhash); - + /* Return function status */ return HAL_OK; } @@ -2324,14 +2627,14 @@ HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /** * @brief Return the computed digest. - * @note The API waits for DCIS to be set then reads the computed digest. + * @note The API waits for DCIS to be set then reads the computed digest. * @param hhash: HASH handle. * @param pOutBuffer: pointer to the computed digest. - * @param Timeout: Timeout value. + * @param Timeout: Timeout value. * @retval HAL status */ HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) -{ +{ if(hhash->State == HAL_HASH_STATE_READY) { @@ -2340,56 +2643,56 @@ HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, ui { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hhash); - + /* Change the HASH state to busy */ hhash->State = HAL_HASH_STATE_BUSY; - + /* Wait for DCIS flag to be set */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) - { + { return HAL_TIMEOUT; } - + /* Read the message digest */ HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH()); - + /* Change the HASH state to ready */ hhash->State = HAL_HASH_STATE_READY; - + /* Process UnLock */ __HAL_UNLOCK(hhash); - + /* Return function status */ return HAL_OK; - + } else { return HAL_BUSY; - } - + } + } /** * @brief Initialize the HASH peripheral in HMAC mode, next process pInBuffer then - * read the computed digest. + * read the computed digest. * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. - * @param Timeout: Timeout value. - * @param Algorithm: HASH algorithm. + * @param Timeout: Timeout value. + * @param Algorithm: HASH algorithm. * @retval HAL status */ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm) -{ +{ /* If State is ready or suspended, start or resume polling-based HASH processing */ if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED)) @@ -2403,21 +2706,21 @@ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint /* Process Locked */ __HAL_LOCK(hhash); - + /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; - + /* Check if initialization phase has already be performed */ if(hhash->Phase == HAL_HASH_PHASE_READY) { /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */ if(hhash->Init.KeySize > 64) { - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); } else { - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); } /* Set the phase to Step 1 */ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1; @@ -2427,38 +2730,38 @@ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */ hhash->pHashInBuffPtr = pInBuffer; /* Input data address, HMAC_Processing input parameter for Step 2 */ hhash->HashInCount = Size; /* Input data size, HMAC_Processing input parameter for Step 2 */ - hhash->HashBuffSize = Size; /* Store the input buffer size for the whole HMAC process */ + hhash->HashBuffSize = Size; /* Store the input buffer size for the whole HMAC process */ hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address, HMAC_Processing input parameter for Step 1 and Step 3 */ - hhash->HashKeyCount = hhash->Init.KeySize; /* Key size, HMAC_Processing input parameter for Step 1 and Step 3 */ + hhash->HashKeyCount = hhash->Init.KeySize; /* Key size, HMAC_Processing input parameter for Step 1 and Step 3 */ } - + /* Carry out HMAC processing */ return HMAC_Processing(hhash, Timeout); - + } else { return HAL_BUSY; - } + } } /** * @brief Initialize the HASH peripheral in HMAC mode, next process pInBuffer then - * read the computed digest in interruption mode. + * read the computed digest in interruption mode. * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. - * @param Algorithm: HASH algorithm. + * @param Algorithm: HASH algorithm. * @retval HAL status */ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm) -{ +{ /* If State is ready or suspended, start or resume IT-based HASH processing */ if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED)) { @@ -2468,57 +2771,57 @@ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hhash); - + /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; - + /* Initialize IT counter */ hhash->HashITCounter = 1; - + /* Check if initialization phase has already be performed */ if (hhash->Phase == HAL_HASH_PHASE_READY) { /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */ if(hhash->Init.KeySize > 64) { - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); } else { - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); } - + /* Resort to hhash internal fields hhash->pHashInBuffPtr and hhash->HashInCount to feed the IP whatever the HMAC step. Lines below are set to start HMAC Step 1 processing where key is entered first. */ - hhash->HashInCount = hhash->Init.KeySize; /* Key size */ - hhash->pHashInBuffPtr = hhash->Init.pKey ; /* Key address */ - - /* Store input and output parameters in handle fields to manage steps transition + hhash->HashInCount = hhash->Init.KeySize; /* Key size */ + hhash->pHashInBuffPtr = hhash->Init.pKey ; /* Key address */ + + /* Store input and output parameters in handle fields to manage steps transition or possible HMAC suspension/resumption */ hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */ hhash->pHashMsgBuffPtr = pInBuffer; /* Input message address */ - hhash->HashBuffSize = Size; /* Input message size (in bytes) */ - hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */ - + hhash->HashBuffSize = Size; /* Input message size (in bytes) */ + hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */ + /* Configure the number of valid bits in last word of the key */ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - + /* Set the phase to Step 1 */ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1; } else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)) { /* Restart IT-based HASH processing after Step 1 or Step 3 suspension */ - + } else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2) { - /* Restart IT-based HASH processing after Step 2 suspension */ - + /* Restart IT-based HASH processing after Step 2 suspension */ + } else { @@ -2526,15 +2829,15 @@ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u /* Process Unlock */ __HAL_UNLOCK(hhash); hhash->State = HAL_HASH_STATE_READY; - return HAL_ERROR; + return HAL_ERROR; } - + /* Process Unlock */ __HAL_UNLOCK(hhash); - + /* Enable Interrupts */ __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI); - + /* Return function status */ return HAL_OK; } @@ -2543,52 +2846,52 @@ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u return HAL_BUSY; } -} +} /** - * @brief Initialize the HASH peripheral in HMAC mode then initiate the required - * DMA transfers to feed the key and the input buffer to the IP. - * @note Same key is used for the inner and the outer hash functions; pointer to key and + * @brief Initialize the HASH peripheral in HMAC mode then initiate the required + * DMA transfers to feed the key and the input buffer to the IP. + * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note In case of multi-buffer HMAC processing, the input buffer size (in bytes) must + * @note In case of multi-buffer HMAC processing, the input buffer size (in bytes) must * be a multiple of 4 otherwise, the HASH digest computation is corrupted. - * Only the length of the last buffer of the thread doesn't have to be a - * multiple of 4. + * Only the length of the last buffer of the thread doesn't have to be a + * multiple of 4. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. - * @param Algorithm: HASH algorithm. + * @param Algorithm: HASH algorithm. * @retval HAL status - */ + */ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) { uint32_t inputaddr; uint32_t inputSize = 0x0; - + /* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */ assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size)); - - /* If State is ready or suspended, start or resume DMA-based HASH processing */ + + /* If State is ready or suspended, start or resume DMA-based HASH processing */ if ((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ if ((pInBuffer == NULL ) || (Size == 0) || (hhash->Init.pKey == NULL ) || (hhash->Init.KeySize == 0) || - /* Check phase coherency. Phase must be + /* Check phase coherency. Phase must be either READY (fresh start) - or one of HMAC PROCESS steps (multi-buffer HASH management) */ + or one of HMAC PROCESS steps (multi-buffer HASH management) */ ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HMAC_PROCESSING(hhash))))) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; } - - + + /* Process Locked */ __HAL_LOCK(hhash); - + /* If not a case of resumption after suspension */ if (hhash->State == HAL_HASH_STATE_READY) { @@ -2597,100 +2900,100 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, { /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; - - /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits. + + /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits. At the same time, ensure MDMAT bit is cleared. */ if(hhash->Init.KeySize > 64) { - MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); } else { - MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); - } - - /* Store input aparameters in handle fields to manage steps transition + MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); + } + + /* Store input aparameters in handle fields to manage steps transition or possible HMAC suspension/resumption */ hhash->HashInCount = hhash->Init.KeySize; /* Initial size for first DMA transfer (key size) */ hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */ hhash->pHashInBuffPtr = hhash->Init.pKey ; /* First address passed to DMA (key address at Step 1) */ hhash->pHashMsgBuffPtr = pInBuffer; /* Input data address */ hhash->HashBuffSize = Size; /* input data size (in bytes) */ - + /* Set DMA input parameters */ inputaddr = (uint32_t)(hhash->Init.pKey); /* Address passed to DMA (start by entering Key message) */ inputSize = hhash->Init.KeySize; /* Size for first DMA transfer (in bytes) */ - + /* Configure the number of valid bits in last word of the key */ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - + /* Set the phase to Step 1 */ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1; - + } else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2) { - /* Process a new input data message in case of multi-buffer HMAC processing + /* Process a new input data message in case of multi-buffer HMAC processing (this is not a resumption case) */ - + /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; /* Save input parameters to be able to manage possible suspension/resumption */ hhash->HashInCount = Size; /* Input message address */ hhash->pHashInBuffPtr = pInBuffer; /* Input message size in bytes */ - + /* Set DMA input parameters */ inputaddr = (uint32_t)pInBuffer; /* Input message address */ inputSize = Size; /* Input message size in bytes */ - + if (hhash->DigestCalculationDisable == RESET) { /* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */ __HAL_HASH_RESET_MDMAT(); __HAL_HASH_SET_NBVALIDBITS(inputSize); - } + } } else { /* Phase not aligned with handle READY state */ __HAL_UNLOCK(hhash); /* Return function status */ - return HAL_ERROR; + return HAL_ERROR; } } else { /* Resumption case (phase may be Step 1, 2 or 3) */ - + /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; - - /* Set DMA input parameters at resumption location; - inputaddr and inputSize are not set to the API input parameters - but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the - processing was suspended. */ + + /* Set DMA input parameters at resumption location; + inputaddr and inputSize are not set to the API input parameters + but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the + processing was suspended. */ inputaddr = (uint32_t)(hhash->pHashInBuffPtr); /* Input message address */ inputSize = hhash->HashInCount; /* Input message size in bytes */ } - + /* Set the HASH DMA transfert complete callback */ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; /* Set the DMA error callback */ hhash->hdmain->XferErrorCallback = HASH_DMAError; - + /* Store number of words already pushed to manage proper DMA processing suspension */ - hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED(); - + hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED(); + /* Enable the DMA In DMA Stream */ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (inputSize%4 ? (inputSize+3)/4:inputSize/4)); /* Enable DMA requests */ SET_BIT(HASH->CR, HASH_CR_DMAE); - + /* Process Unlocked */ __HAL_UNLOCK(hhash); - + /* Return function status */ return HAL_OK; } @@ -2702,7 +3005,7 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /** * @} */ - + /** * @} */ @@ -2711,7 +3014,7 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, * @} */ -#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ +#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ #endif /* HAL_HASH_MODULE_ENABLED */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash_ex.c index ad5668013a..9a49ff1de3 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash_ex.c @@ -3,22 +3,22 @@ * @file stm32l4xx_hal_hash_ex.c * @author MCD Application Team * @brief Extended HASH HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the HASH peripheral for SHA-224 and SHA-256 * alogrithms: * + HASH or HMAC processing in polling mode * + HASH or HMAC processing in interrupt mode * + HASH or HMAC processing in DMA mode * Additionally, this file provides functions to manage HMAC - * multi-buffer DMA-based processing for MD-5, SHA-1, SHA-224 - * and SHA-256. - * - * + * multi-buffer DMA-based processing for MD-5, SHA-1, SHA-224 + * and SHA-256. + * + * @verbatim =============================================================================== ##### HASH peripheral extended features ##### =============================================================================== - [..] + [..] The SHA-224 and SHA-256 HASH and HMAC processing can be carried out exactly the same way as for SHA-1 or MD-5 algorithms. (#) Three modes are available. @@ -30,37 +30,37 @@ e.g. HAL_HASHEx_xxx_Start_IT() (##) DMA mode: processing APIs are not blocking functions and the CPU is not used for data transfer i.e. the data transfer is ensured by DMA, - e.g. HAL_HASHEx_xxx_Start_DMA(). Note that in DMA mode, a call to + e.g. HAL_HASHEx_xxx_Start_DMA(). Note that in DMA mode, a call to HAL_HASHEx_xxx_Finish() is then required to retrieve the digest. - - (#)Multi-buffer processing is possible in polling and DMA mode. - (##) In polling mode, only multi-buffer HASH processing is possible. + + (#)Multi-buffer processing is possible in polling and DMA mode. + (##) In polling mode, only multi-buffer HASH processing is possible. API HAL_HASHEx_xxx_Accumulate() must be called for each input buffer, except for the last one. - User must resort to HAL_HASHEx_xxx_Start() to enter the last one and retrieve as + User must resort to HAL_HASHEx_xxx_Start() to enter the last one and retrieve as well the computed digest. - + (##) In DMA mode, multi-buffer HASH and HMAC processing are possible. (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro. From that point, each buffer can be fed to the IP thru HAL_HASHEx_xxx_Start_DMA() API. Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT() macro then wrap-up the HASH processing in feeding the last input buffer thru the - same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to + same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to API HAL_HASHEx_xxx_Finish(). - + (+++) HMAC processing (MD-5, SHA-1, SHA-224 and SHA-256 must all resort to extended functions): after initialization, the key and the first input buffer are entered in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and starts step 2. The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this point, the HMAC processing is still carrying out step 2. - Then, step 2 for the last input buffer and step 3 are carried out by a single call + Then, step 2 for the last input buffer and step 3 are carried out by a single call to HAL_HMACEx_xxx_Step2_3_DMA(). - + The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish() for - MD-5 and SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 and SHA-256. - - + MD-5 and SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 and SHA-256. + + @endverbatim ****************************************************************************** * @attention @@ -89,8 +89,8 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -117,28 +117,28 @@ */ -/** @defgroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode - * @brief HASH extended processing functions using polling mode. +/** @defgroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode + * @brief HASH extended processing functions using polling mode. * -@verbatim +@verbatim =============================================================================== ##### Polling mode HASH extended processing functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in polling mode the hash value using one of the following algorithms: (+) SHA224 - (++) HAL_HASHEx_SHA224_Start() - (++) HAL_HASHEx_SHA224_Accumulate() + (++) HAL_HASHEx_SHA224_Start() + (++) HAL_HASHEx_SHA224_Accumulate() (+) SHA256 - (++) HAL_HASHEx_SHA256_Start() - (++) HAL_HASHEx_SHA256_Accumulate() - + (++) HAL_HASHEx_SHA256_Start() + (++) HAL_HASHEx_SHA256_Accumulate() + [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start(). - + [..] In case of multi-buffer HASH processing (a single digest is computed while several buffers are fed to the IP), the user can resort to successive calls to HAL_HASHEx_xxx_Accumulate() and wrap-up the digest computation by a call - to HAL_HASHEx_xxx_Start(). + to HAL_HASHEx_xxx_Start(). @endverbatim * @{ @@ -147,13 +147,13 @@ /** * @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then - * read the computed digest. + * read the computed digest. * @note Digest is available in pOutBuffer. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes. - * @param Timeout: Timeout value + * @param Timeout: Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -162,20 +162,20 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI } /** - * @brief If not already done, initialize the HASH peripheral in SHA224 mode then + * @brief If not already done, initialize the HASH peripheral in SHA224 mode then * processes pInBuffer. - * @note Consecutive calls to HAL_HASHEx_SHA224_Accumulate() can be used to feed + * @note Consecutive calls to HAL_HASHEx_SHA224_Accumulate() can be used to feed * several input buffers back-to-back to the IP that will yield a single - * HASH signature once all buffers have been entered. Wrap-up of input - * buffers feeding and retrieval of digest is done by a call to - * HAL_HASHEx_SHA224_Start(). + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASHEx_SHA224_Start(). * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the IP has already been initialized. + * the IP has already been initialized. * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Start() * to read it, feeding at the same time the last input buffer to the IP. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the * HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Start() is able - * to manage the ending buffer with a length in bytes not a multiple of 4. + * to manage the ending buffer with a length in bytes not a multiple of 4. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes, must be a multiple of 4. @@ -188,13 +188,13 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_ /** * @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then - * read the computed digest. + * read the computed digest. * @note Digest is available in pOutBuffer. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes. - * @param Timeout: Timeout value + * @param Timeout: Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -203,20 +203,20 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI } /** - * @brief If not already done, initialize the HASH peripheral in SHA256 mode then + * @brief If not already done, initialize the HASH peripheral in SHA256 mode then * processes pInBuffer. - * @note Consecutive calls to HAL_HASHEx_SHA256_Accumulate() can be used to feed + * @note Consecutive calls to HAL_HASHEx_SHA256_Accumulate() can be used to feed * several input buffers back-to-back to the IP that will yield a single - * HASH signature once all buffers have been entered. Wrap-up of input - * buffers feeding and retrieval of digest is done by a call to - * HAL_HASHEx_SHA256_Start(). + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASHEx_SHA256_Start(). * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the IP has already been initialized. + * the IP has already been initialized. * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Start() * to read it, feeding at the same time the last input buffer to the IP. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the * HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Start() is able - * to manage the ending buffer with a length in bytes not a multiple of 4. + * to manage the ending buffer with a length in bytes not a multiple of 4. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes, must be a multiple of 4. @@ -232,17 +232,17 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_ * @} */ -/** @defgroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode - * @brief HASH extended processing functions using interrupt mode. +/** @defgroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode + * @brief HASH extended processing functions using interrupt mode. * -@verbatim +@verbatim =============================================================================== ##### Interruption mode HASH extended processing functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in interrupt mode the hash value using one of the following algorithms: (+) SHA224 - (++) HAL_HASHEx_SHA224_Start_IT() + (++) HAL_HASHEx_SHA224_Start_IT() (+) SHA256 (++) HAL_HASHEx_SHA256_Start_IT() @@ -253,14 +253,14 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_ /** * @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then - * read the computed digest in interruption mode. + * read the computed digest in interruption mode. * @note Digest is available in pOutBuffer. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224); @@ -268,14 +268,14 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t /** * @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then - * read the computed digest in interruption mode. + * read the computed digest in interruption mode. * @note Digest is available in pOutBuffer. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256); @@ -285,30 +285,30 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @} */ -/** @defgroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode - * @brief HASH extended processing functions using DMA mode. +/** @defgroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode + * @brief HASH extended processing functions using DMA mode. * -@verbatim +@verbatim =============================================================================== ##### DMA mode HASH extended processing functionss ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in DMA mode the hash value using one of the following algorithms: (+) SHA224 - (++) HAL_HASHEx_SHA224_Start_DMA() - (++) HAL_HASHEx_SHA224_Finish() + (++) HAL_HASHEx_SHA224_Start_DMA() + (++) HAL_HASHEx_SHA224_Finish() (+) SHA256 (++) HAL_HASHEx_SHA256_Start_DMA() (++) HAL_HASHEx_SHA256_Finish() - + [..] When resorting to DMA mode to enter the data in the IP, user must resort - to HAL_HASHEx_xxx_Start_DMA() then read the resulting digest with - HAL_HASHEx_xxx_Finish(). - + to HAL_HASHEx_xxx_Start_DMA() then read the resulting digest with + HAL_HASHEx_xxx_Finish(). + [..] In case of multi-buffer HASH processing, MDMAT bit must first be set before - the successive calls to HAL_HASHEx_xxx_Start_DMA(). Then, MDMAT bit needs to be + the successive calls to HAL_HASHEx_xxx_Start_DMA(). Then, MDMAT bit needs to be reset before the last call to HAL_HASHEx_xxx_Start_DMA(). Digest is finally - retrieved thanks to HAL_HASHEx_xxx_Finish(). + retrieved thanks to HAL_HASHEx_xxx_Finish(). @endverbatim * @{ @@ -319,81 +319,81 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t /** * @brief Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer - * to feed the input buffer to the IP. + * to feed the input buffer to the IP. * @note Once the DMA transfer is finished, HAL_HASHEx_SHA224_Finish() API must - * be called to retrieve the computed digest. + * be called to retrieve the computed digest. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { - return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); + return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } /** * @brief Return the computed digest in SHA224 mode. * @note The API waits for DCIS to be set then reads the computed digest. * @note HAL_HASHEx_SHA224_Finish() can be used as well to retrieve the digest in - * HMAC SHA224 mode. + * HMAC SHA224 mode. * @param hhash: HASH handle. * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes. - * @param Timeout: Timeout value. + * @param Timeout: Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) -{ - return HASH_Finish(hhash, pOutBuffer, Timeout); +{ + return HASH_Finish(hhash, pOutBuffer, Timeout); } /** * @brief Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer - * to feed the input buffer to the IP. + * to feed the input buffer to the IP. * @note Once the DMA transfer is finished, HAL_HASHEx_SHA256_Finish() API must - * be called to retrieve the computed digest. + * be called to retrieve the computed digest. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { - return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); + return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } /** * @brief Return the computed digest in SHA256 mode. * @note The API waits for DCIS to be set then reads the computed digest. * @note HAL_HASHEx_SHA256_Finish() can be used as well to retrieve the digest in - * HMAC SHA256 mode. + * HMAC SHA256 mode. * @param hhash: HASH handle. * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes. - * @param Timeout: Timeout value. + * @param Timeout: Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) -{ - return HASH_Finish(hhash, pOutBuffer, Timeout); +{ + return HASH_Finish(hhash, pOutBuffer, Timeout); } /** * @} */ -/** @defgroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode - * @brief HMAC extended processing functions using polling mode. +/** @defgroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode + * @brief HMAC extended processing functions using polling mode. * -@verbatim +@verbatim =============================================================================== ##### Polling mode HMAC extended processing functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in polling mode the HMAC value using one of the following algorithms: (+) SHA224 - (++) HAL_HMACEx_SHA224_Start() + (++) HAL_HMACEx_SHA224_Start() (+) SHA256 - (++) HAL_HMACEx_SHA256_Start() + (++) HAL_HMACEx_SHA256_Start() @endverbatim * @{ @@ -403,124 +403,124 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p /** * @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then - * read the computed digest. + * read the computed digest. * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes. - * @param Timeout: Timeout value. + * @param Timeout: Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) -{ +{ return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); } /** * @brief Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then - * read the computed digest. + * read the computed digest. * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes. - * @param Timeout: Timeout value. + * @param Timeout: Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) -{ +{ return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); } /** * @} */ - - -/** @defgroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode - * @brief HMAC extended processing functions using interruption mode. + + +/** @defgroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode + * @brief HMAC extended processing functions using interruption mode. * -@verbatim +@verbatim =============================================================================== ##### Interrupt mode HMAC extended processing functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in interrupt mode the HMAC value using one of the following algorithms: (+) SHA224 - (++) HAL_HMACEx_SHA224_Start_IT() + (++) HAL_HMACEx_SHA224_Start_IT() (+) SHA256 - (++) HAL_HMACEx_SHA256_Start_IT() + (++) HAL_HMACEx_SHA256_Start_IT() @endverbatim * @{ */ - + /** * @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then - * read the computed digest in interrupt mode. + * read the computed digest in interrupt mode. * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) -{ +{ return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); -} - +} + /** * @brief Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then - * read the computed digest in interrupt mode. + * read the computed digest in interrupt mode. * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) -{ +{ return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); -} - - - - +} + + + + /** * @} */ - -/** @defgroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode - * @brief HMAC extended processing functions using DMA mode. + +/** @defgroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode + * @brief HMAC extended processing functions using DMA mode. * -@verbatim +@verbatim =============================================================================== ##### DMA mode HMAC extended processing functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in DMA mode the HMAC value using one of the following algorithms: (+) SHA224 - (++) HAL_HMACEx_SHA224_Start_DMA() + (++) HAL_HMACEx_SHA224_Start_DMA() (+) SHA256 (++) HAL_HMACEx_SHA256_Start_DMA() - - [..] When resorting to DMA mode to enter the data in the IP for HMAC processing, - user must resort to HAL_HMACEx_xxx_Start_DMA() then read the resulting digest - with HAL_HASHEx_xxx_Finish(). + + [..] When resorting to DMA mode to enter the data in the IP for HMAC processing, + user must resort to HAL_HMACEx_xxx_Start_DMA() then read the resulting digest + with HAL_HASHEx_xxx_Finish(). @endverbatim @@ -530,48 +530,48 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t /** - * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required - * DMA transfers to feed the key and the input buffer to the IP. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA224_Finish() API must be called to retrieve + * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required + * DMA transfers to feed the key and the input buffer to the IP. + * @note Once the DMA transfers are finished (indicated by hhash->State set back + * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA224_Finish() API must be called to retrieve * the computed digest. - * @note Same key is used for the inner and the outer hash functions; pointer to key and + * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note If MDMAT bit is set before calling this function (multi-buffer - * HASH processing case), the input buffer size (in bytes) must be + * HASH processing case), the input buffer size (in bytes) must be * a multiple of 4 otherwise, the HASH digest computation is corrupted. * For the processing of the last buffer of the thread, MDMAT bit must - * be reset and the buffer length (in bytes) doesn't have to be a - * multiple of 4. + * be reset and the buffer length (in bytes) doesn't have to be a + * multiple of 4. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } /** - * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required - * DMA transfers to feed the key and the input buffer to the IP. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve + * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required + * DMA transfers to feed the key and the input buffer to the IP. + * @note Once the DMA transfers are finished (indicated by hhash->State set back + * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve * the computed digest. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note If MDMAT bit is set before calling this function (multi-buffer - * HASH processing case), the input buffer size (in bytes) must be + * HASH processing case), the input buffer size (in bytes) must be * a multiple of 4 otherwise, the HASH digest computation is corrupted. * For the processing of the last buffer of the thread, MDMAT bit must - * be reset and the buffer length (in bytes) doesn't have to be a - * multiple of 4. + * be reset and the buffer length (in bytes) doesn't have to be a + * multiple of 4. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); @@ -582,50 +582,50 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @} */ -/** @defgroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode - * @brief HMAC extended processing functions in multi-buffer DMA mode. +/** @defgroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode + * @brief HMAC extended processing functions in multi-buffer DMA mode. * -@verbatim +@verbatim =============================================================================== ##### Multi-buffer DMA mode HMAC extended processing functions ##### =============================================================================== - [..] This section provides functions to manage HMAC multi-buffer + [..] This section provides functions to manage HMAC multi-buffer DMA-based processing for MD5, SHA1, SHA224 and SHA256 algorithms. (+) MD5 - (++) HAL_HMACEx_MD5_Step1_2_DMA() - (++) HAL_HMACEx_MD5_Step2_DMA() - (++) HAL_HMACEx_MD5_Step2_3_DMA() + (++) HAL_HMACEx_MD5_Step1_2_DMA() + (++) HAL_HMACEx_MD5_Step2_DMA() + (++) HAL_HMACEx_MD5_Step2_3_DMA() (+) SHA1 - (++) HAL_HMACEx_SHA1_Step1_2_DMA() - (++) HAL_HMACEx_SHA1_Step2_DMA() - (++) HAL_HMACEx_SHA1_Step2_3_DMA() + (++) HAL_HMACEx_SHA1_Step1_2_DMA() + (++) HAL_HMACEx_SHA1_Step2_DMA() + (++) HAL_HMACEx_SHA1_Step2_3_DMA() (+) SHA256 - (++) HAL_HMACEx_SHA224_Step1_2_DMA() - (++) HAL_HMACEx_SHA224_Step2_DMA() - (++) HAL_HMACEx_SHA224_Step2_3_DMA() + (++) HAL_HMACEx_SHA224_Step1_2_DMA() + (++) HAL_HMACEx_SHA224_Step2_DMA() + (++) HAL_HMACEx_SHA224_Step2_3_DMA() (+) SHA256 - (++) HAL_HMACEx_SHA256_Step1_2_DMA() - (++) HAL_HMACEx_SHA256_Step2_DMA() - (++) HAL_HMACEx_SHA256_Step2_3_DMA() - + (++) HAL_HMACEx_SHA256_Step1_2_DMA() + (++) HAL_HMACEx_SHA256_Step2_DMA() + (++) HAL_HMACEx_SHA256_Step2_3_DMA() + [..] User must first start-up the multi-buffer DMA-based HMAC computation in calling HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and intiates step 2 with the first input buffer. - + [..] The following buffers are next fed to the IP with a call to the API HAL_HMACEx_xxx_Step2_DMA(). There may be several consecutive calls to this API. - + [..] Multi-buffer DMA-based HMAC computation is wrapped up by a call to - HAL_HMACEx_xxx_Step2_3_DMA(). This finishes step 2 in feeding the last input - buffer to the IP then carries out step 3. - + HAL_HMACEx_xxx_Step2_3_DMA(). This finishes step 2 in feeding the last input + buffer to the IP then carries out step 3. + [..] Digest is retrieved by a call to HAL_HASH_xxx_Finish() for MD-5 or - SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 or SHA-256. - + SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 or SHA-256. + [..] If only two buffers need to be consecutively processed, a call to HAL_HMACEx_xxx_Step1_2_DMA() followed by a call to HAL_HMACEx_xxx_Step2_3_DMA() - is sufficient. + is sufficient. @endverbatim * @{ @@ -633,15 +633,15 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode. - * @note Step 1 consists in writing the inner hash function key in the IP, - * step 2 consists in writing the message text. + * @note Step 1 consists in writing the inner hash function key in the IP, + * step 2 consists in writing the message text. * @note The API carries out the HMAC step 1 then starts step 2 with * the first buffer entered to the IP. DCAL bit is not automatically set after * the message buffer feeding, allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and + * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. + * HASH digest computation is corrupted. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -655,14 +655,14 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief MD5 HMAC step 2 in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP. + * @note Step 2 consists in writing the message text in the IP. * @note The API carries on the HMAC step 2, applied to the buffer entered as input - * parameter. DCAL bit is not automatically set after the message buffer feeding, + * parameter. DCAL bit is not automatically set after the message buffer feeding, * allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. + * HASH digest computation is corrupted. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -672,23 +672,23 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *p { if (hhash->DigestCalculationDisable != SET) { - return HAL_ERROR; + return HAL_ERROR; } return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } /** * @brief MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP, - * step 3 consists in writing the outer hash function key. + * @note Step 2 consists in writing the message text in the IP, + * step 3 consists in writing the outer hash function key. * @note The API wraps up the HMAC step 2 in processing the buffer entered as input * parameter (the input buffer must be the last one of the multi-buffer thread) - * then carries out HMAC step 3. - * @note Same key is used for the inner and the outer hash functions; pointer to key and + * then carries out HMAC step 3. + * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve - * the computed digest. + * @note Once the DMA transfers are finished (indicated by hhash->State set back + * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve + * the computed digest. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -703,15 +703,15 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode. - * @note Step 1 consists in writing the inner hash function key in the IP, - * step 2 consists in writing the message text. + * @note Step 1 consists in writing the inner hash function key in the IP, + * step 2 consists in writing the message text. * @note The API carries out the HMAC step 1 then starts step 2 with * the first buffer entered to the IP. DCAL bit is not automatically set after * the message buffer feeding, allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. + * HASH digest computation is corrupted. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -725,14 +725,14 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief SHA1 HMAC step 2 in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP. + * @note Step 2 consists in writing the message text in the IP. * @note The API carries on the HMAC step 2, applied to the buffer entered as input - * parameter. DCAL bit is not automatically set after the message buffer feeding, + * parameter. DCAL bit is not automatically set after the message buffer feeding, * allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. + * HASH digest computation is corrupted. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -742,23 +742,23 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * { if (hhash->DigestCalculationDisable != SET) { - return HAL_ERROR; + return HAL_ERROR; } return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } /** * @brief SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP, - * step 3 consists in writing the outer hash function key. + * @note Step 2 consists in writing the message text in the IP, + * step 3 consists in writing the outer hash function key. * @note The API wraps up the HMAC step 2 in processing the buffer entered as input * parameter (the input buffer must be the last one of the multi-buffer thread) - * then carries out HMAC step 3. - * @note Same key is used for the inner and the outer hash functions; pointer to key and + * then carries out HMAC step 3. + * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve - * the computed digest. + * @note Once the DMA transfers are finished (indicated by hhash->State set back + * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve + * the computed digest. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -772,15 +772,15 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode. - * @note Step 1 consists in writing the inner hash function key in the IP, - * step 2 consists in writing the message text. + * @note Step 1 consists in writing the inner hash function key in the IP, + * step 2 consists in writing the message text. * @note The API carries out the HMAC step 1 then starts step 2 with * the first buffer entered to the IP. DCAL bit is not automatically set after * the message buffer feeding, allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. + * HASH digest computation is corrupted. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -794,14 +794,14 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 /** * @brief SHA224 HMAC step 2 in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP. + * @note Step 2 consists in writing the message text in the IP. * @note The API carries on the HMAC step 2, applied to the buffer entered as input - * parameter. DCAL bit is not automatically set after the message buffer feeding, + * parameter. DCAL bit is not automatically set after the message buffer feeding, * allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and + * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. + * HASH digest computation is corrupted. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -811,23 +811,23 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t { if (hhash->DigestCalculationDisable != SET) { - return HAL_ERROR; + return HAL_ERROR; } return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } /** * @brief SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP, - * step 3 consists in writing the outer hash function key. + * @note Step 2 consists in writing the message text in the IP, + * step 3 consists in writing the outer hash function key. * @note The API wraps up the HMAC step 2 in processing the buffer entered as input * parameter (the input buffer must be the last one of the multi-buffer thread) - * then carries out HMAC step 3. - * @note Same key is used for the inner and the outer hash functions; pointer to key and + * then carries out HMAC step 3. + * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve - * the computed digest. + * @note Once the DMA transfers are finished (indicated by hhash->State set back + * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve + * the computed digest. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -841,15 +841,15 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 /** * @brief SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode. - * @note Step 1 consists in writing the inner hash function key in the IP, - * step 2 consists in writing the message text. + * @note Step 1 consists in writing the inner hash function key in the IP, + * step 2 consists in writing the message text. * @note The API carries out the HMAC step 1 then starts step 2 with * the first buffer entered to the IP. DCAL bit is not automatically set after * the message buffer feeding, allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. + * HASH digest computation is corrupted. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -863,14 +863,14 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 /** * @brief SHA256 HMAC step 2 in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP. + * @note Step 2 consists in writing the message text in the IP. * @note The API carries on the HMAC step 2, applied to the buffer entered as input - * parameter. DCAL bit is not automatically set after the message buffer feeding, + * parameter. DCAL bit is not automatically set after the message buffer feeding, * allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. + * HASH digest computation is corrupted. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -880,23 +880,23 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t { if (hhash->DigestCalculationDisable != SET) { - return HAL_ERROR; + return HAL_ERROR; } return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } /** * @brief SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP, - * step 3 consists in writing the outer hash function key. + * @note Step 2 consists in writing the message text in the IP, + * step 3 consists in writing the outer hash function key. * @note The API wraps up the HMAC step 2 in processing the buffer entered as input * parameter (the input buffer must be the last one of the multi-buffer thread) - * then carries out HMAC step 3. - * @note Same key is used for the inner and the outer hash functions; pointer to key and + * then carries out HMAC step 3. + * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve - * the computed digest. + * @note Once the DMA transfers are finished (indicated by hhash->State set back + * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve + * the computed digest. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -916,7 +916,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 /** * @} */ - + /** * @} */ @@ -925,7 +925,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 * @} */ -#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ +#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ #endif /* HAL_HASH_MODULE_ENABLED */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hcd.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hcd.c index 6447fa7ffd..5b205dabdb 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hcd.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hcd.c @@ -3,13 +3,13 @@ * @file stm32l4xx_hal_hcd.c * @author MCD Application Team * @brief HCD HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State functions - * + * @verbatim ============================================================================== ##### How to use this driver ##### @@ -17,19 +17,18 @@ [..] (#)Declare a HCD_HandleTypeDef handle structure, for example: HCD_HandleTypeDef hhcd; - + (#)Fill parameters of Init structure in HCD handle - - (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...) + + (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...) (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API: - (##) Enable the HCD/USB Low Level interface clock using the following macro - (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE() - + (##) Enable the HCD/USB Low Level interface clock using the following macros + (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); (##) Initialize the related GPIO clocks (##) Configure HCD pin-out (##) Configure HCD NVIC interrupt - + (#)Associate the Upper USB Host stack to the HAL HCD Driver: (##) hhcd.pData = phost; @@ -65,26 +64,24 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" -#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /** @addtogroup STM32L4xx_HAL_Driver * @{ */ -/** @defgroup HCD HCD +/** @defgroup HCD HCD * @brief HCD HAL module driver * @{ */ #ifdef HAL_HCD_MODULE_ENABLED +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -94,7 +91,7 @@ * @{ */ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); -static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); +static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd); static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); /** @@ -106,88 +103,105 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); * @{ */ -/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: - + @endverbatim * @{ */ /** - * @brief Initialize the Host driver. - * @param hhcd: HCD handle + * @brief Initialize the host driver. + * @param hhcd HCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) -{ +{ /* Check the HCD handle allocation */ - if(hhcd == NULL) + if (hhcd == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance)); - if(hhcd->State == HAL_HCD_STATE_RESET) + if (hhcd->State == HAL_HCD_STATE_RESET) { /* Allocate lock resource and initialize it */ hhcd->Lock = HAL_UNLOCKED; - + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->SOFCallback = HAL_HCD_SOF_Callback; + hhcd->ConnectCallback = HAL_HCD_Connect_Callback; + hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback; + hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback; + hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback; + hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; + + if (hhcd->MspInitCallback == NULL) + { + hhcd->MspInitCallback = HAL_HCD_MspInit; + } + + /* Init the low level hardware */ + hhcd->MspInitCallback(hhcd); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_HCD_MspInit(hhcd); +#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */ } hhcd->State = HAL_HCD_STATE_BUSY; /* Disable the Interrupts */ - __HAL_HCD_DISABLE(hhcd); - - /*Init the Core (common init.) */ - USB_CoreInit(hhcd->Instance, hhcd->Init); - - /* Force Host Mode*/ - USB_SetCurrentMode(hhcd->Instance , USB_HOST_MODE); - - /* Init Host */ - USB_HostInit(hhcd->Instance, hhcd->Init); - - hhcd->State= HAL_HCD_STATE_READY; - - return HAL_OK; + __HAL_HCD_DISABLE(hhcd); + + /* Init the Core (common init.) */ + (void)USB_CoreInit(hhcd->Instance, hhcd->Init); + + /* Force Host Mode*/ + (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE); + + /* Init Host */ + (void)USB_HostInit(hhcd->Instance, hhcd->Init); + + hhcd->State = HAL_HCD_STATE_READY; + + return HAL_OK; } /** - * @brief Initialize a Host channel. - * @param hhcd: HCD handle - * @param ch_num: Channel number. + * @brief Initialize a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. * This parameter can be a value from 1 to 15 - * @param epnum: Endpoint number. + * @param epnum Endpoint number. * This parameter can be a value from 1 to 15 - * @param dev_address : Current device address + * @param dev_address Current device address * This parameter can be a value from 0 to 255 - * @param speed: Current device speed. + * @param speed Current device speed. * This parameter can be one of these values: * HCD_SPEED_HIGH: High speed mode, * HCD_SPEED_FULL: Full speed mode, * HCD_SPEED_LOW: Low speed mode - * @param ep_type: Endpoint Type. + * @param ep_type Endpoint Type. * This parameter can be one of these values: * EP_TYPE_CTRL: Control type, * EP_TYPE_ISOC: Isochronous type, * EP_TYPE_BULK: Bulk type, * EP_TYPE_INTR: Interrupt type - * @param mps: Max Packet Size. + * @param mps Max Packet Size. * This parameter can be a value from 0 to32K * @retval HAL status */ -HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, @@ -195,76 +209,95 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ep_type, uint16_t mps) { - HAL_StatusTypeDef status = HAL_OK; - - __HAL_LOCK(hhcd); - + HAL_StatusTypeDef status; + + __HAL_LOCK(hhcd); + hhcd->hc[ch_num].do_ping = 0U; hhcd->hc[ch_num].dev_addr = dev_address; hhcd->hc[ch_num].max_packet = mps; hhcd->hc[ch_num].ch_num = ch_num; hhcd->hc[ch_num].ep_type = ep_type; - hhcd->hc[ch_num].ep_num = epnum & 0x7F; - hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80); + hhcd->hc[ch_num].ep_num = epnum & 0x7FU; + + if ((epnum & 0x80U) == 0x80U) + { + hhcd->hc[ch_num].ep_is_in = 1U; + } + else + { + hhcd->hc[ch_num].ep_is_in = 0U; + } + hhcd->hc[ch_num].speed = speed; - status = USB_HC_Init(hhcd->Instance, + status = USB_HC_Init(hhcd->Instance, ch_num, epnum, dev_address, speed, ep_type, mps); - __HAL_UNLOCK(hhcd); - + __HAL_UNLOCK(hhcd); + return status; } /** - * @brief Halt a Host channel. - * @param hhcd: HCD handle - * @param ch_num: Channel number. + * @brief Halt a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. * This parameter can be a value from 1 to 15 * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num) { HAL_StatusTypeDef status = HAL_OK; - - __HAL_LOCK(hhcd); - USB_HC_Halt(hhcd->Instance, ch_num); + + __HAL_LOCK(hhcd); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_UNLOCK(hhcd); - + return status; } /** - * @brief DeInitialize the Host driver. - * @param hhcd: HCD handle + * @brief DeInitialize the host driver. + * @param hhcd HCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd) { /* Check the HCD handle allocation */ - if(hhcd == NULL) + if (hhcd == NULL) { return HAL_ERROR; } - + hhcd->State = HAL_HCD_STATE_BUSY; - + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + if (hhcd->MspDeInitCallback == NULL) + { + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; /* Legacy weak MspDeInit */ + } + /* DeInit the low level hardware */ + hhcd->MspDeInitCallback(hhcd); +#else + /* DeInit the low level hardware: CLOCK, NVIC.*/ HAL_HCD_MspDeInit(hhcd); - - __HAL_HCD_DISABLE(hhcd); - - hhcd->State = HAL_HCD_STATE_RESET; - +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + __HAL_HCD_DISABLE(hhcd); + + hhcd->State = HAL_HCD_STATE_RESET; + return HAL_OK; } /** * @brief Initialize the HCD MSP. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd) @@ -273,13 +306,13 @@ __weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd) UNUSED(hhcd); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_MspInit could be implemented in the user file + the HAL_HCD_MspInit could be implemented in the user file */ } /** * @brief DeInitialize the HCD MSP. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) @@ -288,7 +321,7 @@ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) UNUSED(hhcd); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_MspDeInit could be implemented in the user file + the HAL_HCD_MspDeInit could be implemented in the user file */ } @@ -296,57 +329,59 @@ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) * @} */ -/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions +/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions * @brief HCD IO operation functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USB Host Data + [..] This subsection provides a set of functions allowing to manage the USB Host Data Transfer - + @endverbatim * @{ */ - -/** + +/** * @brief Submit a new URB for processing. - * @param hhcd: HCD handle - * @param ch_num: Channel number. + * @param hhcd HCD handle + * @param ch_num Channel number. * This parameter can be a value from 1 to 15 - * @param direction: Channel number. + * @param direction Channel number. * This parameter can be one of these values: * 0 : Output / 1 : Input - * @param ep_type: Endpoint Type. + * @param ep_type Endpoint Type. * This parameter can be one of these values: * EP_TYPE_CTRL: Control type/ * EP_TYPE_ISOC: Isochronous type/ * EP_TYPE_BULK: Bulk type/ * EP_TYPE_INTR: Interrupt type/ - * @param token: Endpoint Type. + * @param token Endpoint Type. * This parameter can be one of these values: * 0: HC_PID_SETUP / 1: HC_PID_DATA1 - * @param pbuff: pointer to URB data - * @param length: Length of URB data - * @param do_ping: activate do ping protocol (for high speed only). + * @param pbuff pointer to URB data + * @param length Length of URB data + * @param do_ping activate do ping protocol (for high speed only). * This parameter can be one of these values: - * 0 : do ping inactive / 1 : do ping active + * 0 : do ping inactive / 1 : do ping active * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, - uint8_t ch_num, - uint8_t direction , - uint8_t ep_type, - uint8_t token, - uint8_t* pbuff, - uint16_t length, - uint8_t do_ping) + uint8_t ch_num, + uint8_t direction, + uint8_t ep_type, + uint8_t token, + uint8_t *pbuff, + uint16_t length, + uint8_t do_ping) { + UNUSED(do_ping); + hhcd->hc[ch_num].ep_is_in = direction; - hhcd->hc[ch_num].ep_type = ep_type; - - if(token == 0) + hhcd->hc[ch_num].ep_type = ep_type; + + if (token == 0U) { hhcd->hc[ch_num].data_pid = HC_PID_SETUP; } @@ -354,203 +389,216 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, { hhcd->hc[ch_num].data_pid = HC_PID_DATA1; } - + /* Manage Data Toggle */ - switch(ep_type) + switch (ep_type) { - case EP_TYPE_CTRL: - if((token == 1) && (direction == 0)) /*send data */ - { - if ( length == 0 ) - { /* For Status OUT stage, Length==0, Status Out PID = 1 */ - hhcd->hc[ch_num].toggle_out = 1; - } - - /* Set the Data Toggle bit as per the Flag */ - if ( hhcd->hc[ch_num].toggle_out == 0) - { /* Put the PID 0 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; - } - else - { /* Put the PID 1 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ; - } - if(hhcd->hc[ch_num].urb_state != URB_NOTREADY) + case EP_TYPE_CTRL: + if ((token == 1U) && (direction == 0U)) /*send data */ { - hhcd->hc[ch_num].do_ping = do_ping; - } - } - break; - - case EP_TYPE_BULK: - if(direction == 0) - { - /* Set the Data Toggle bit as per the Flag */ - if ( hhcd->hc[ch_num].toggle_out == 0) - { /* Put the PID 0 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; - } - else - { /* Put the PID 1 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ; - } - if(hhcd->hc[ch_num].urb_state != URB_NOTREADY) - { - hhcd->hc[ch_num].do_ping = do_ping; + if (length == 0U) + { + /* For Status OUT stage, Length==0, Status Out PID = 1 */ + hhcd->hc[ch_num].toggle_out = 1U; + } + + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } } - } - else - { - if( hhcd->hc[ch_num].toggle_in == 0) + break; + + case EP_TYPE_BULK: + if (direction == 0U) { - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } } else { - hhcd->hc[ch_num].data_pid = HC_PID_DATA1; - } - } - - break; - case EP_TYPE_INTR: - if(direction == 0) - { - /* Set the Data Toggle bit as per the Flag */ - if ( hhcd->hc[ch_num].toggle_out == 0) - { /* Put the PID 0 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; - } - else - { /* Put the PID 1 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ; + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } } - } - else - { - if( hhcd->hc[ch_num].toggle_in == 0) + + break; + case EP_TYPE_INTR: + if (direction == 0U) { - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } } else { - hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } } - } - break; - - case EP_TYPE_ISOC: - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; - break; + break; + + case EP_TYPE_ISOC: + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + break; + + default: + break; } - + hhcd->hc[ch_num].xfer_buff = pbuff; hhcd->hc[ch_num].xfer_len = length; - hhcd->hc[ch_num].urb_state = URB_IDLE; - hhcd->hc[ch_num].xfer_count = 0 ; + hhcd->hc[ch_num].urb_state = URB_IDLE; + hhcd->hc[ch_num].xfer_count = 0U; hhcd->hc[ch_num].ch_num = ch_num; hhcd->hc[ch_num].state = HC_IDLE; - - return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]), hhcd->Init.dma_enable); + + return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num]); } /** * @brief Handle HCD interrupt request. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint32_t i = 0 , interrupt = 0; - - /* ensure that we are in device mode */ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i, interrupt; + + /* Ensure that we are in device mode */ if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST) { - /* avoid spurious interrupt */ - if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) + /* Avoid spurious interrupt */ + if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) { return; } - - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) { - /* incorrect mode, acknowledge the interrupt */ + /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); } - - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR)) + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR)) { - /* incorrect mode, acknowledge the interrupt */ + /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR); } - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE)) + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE)) { - /* incorrect mode, acknowledge the interrupt */ + /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE); - } - - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS)) + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS)) { - /* incorrect mode, acknowledge the interrupt */ + /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS); - } - + } + /* Handle Host Disconnect Interrupts */ - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT)) + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT)) { - + /* Cleanup HPRT */ - USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - - /* Handle Host Port Interrupts */ + USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \ + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + /* Handle Host Port Disconnect Interrupt */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->DisconnectCallback(hhcd); +#else HAL_HCD_Disconnect_Callback(hhcd); - USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ ); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); } - + /* Handle Host Port Interrupts */ - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT)) + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT)) { - HCD_Port_IRQHandler (hhcd); + HCD_Port_IRQHandler(hhcd); } - - /* Handle Host SOF Interrupts */ - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF)) + + /* Handle Host SOF Interrupt */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF)) { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->SOFCallback(hhcd); +#else HAL_HCD_SOF_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF); } - - /* Handle Host channel Interrupts */ - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) + + /* Handle Host channel Interrupt */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) { interrupt = USB_HC_ReadInterrupt(hhcd->Instance); - for (i = 0; i < hhcd->Init.Host_channels ; i++) + for (i = 0U; i < hhcd->Init.Host_channels; i++) { - if (interrupt & (1 << i)) + if ((interrupt & (1UL << (i & 0xFU))) != 0U) { - if ((USBx_HC(i)->HCCHAR) & USB_OTG_HCCHAR_EPDIR) + if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR) { - HCD_HC_IN_IRQHandler (hhcd, i); + HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i); } else { - HCD_HC_OUT_IRQHandler (hhcd, i); + HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i); } } } __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT); - } - + } + /* Handle Rx Queue Level Interrupts */ - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) + if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) { USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); - - HCD_RXQLVL_IRQHandler (hhcd); - + + HCD_RXQLVL_IRQHandler(hhcd); + USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); } } @@ -558,7 +606,7 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) /** * @brief SOF callback. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) @@ -573,7 +621,7 @@ __weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) /** * @brief Connection Event callback. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) @@ -588,7 +636,7 @@ __weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) /** * @brief Disconnection Event callback. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) @@ -599,21 +647,51 @@ __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) /* NOTE : This function should not be modified, when the callback is needed, the HAL_HCD_Disconnect_Callback could be implemented in the user file */ -} +} + +/** + * @brief Port Enabled Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Port Disabled Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} /** * @brief Notify URB state change callback. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @param urb_state: * This parameter can be one of these values: * URB_IDLE/ * URB_DONE/ * URB_NOTREADY/ - * URB_NYET/ - * URB_ERROR/ - * URB_STALL/ + * URB_NYET/ + * URB_ERROR/ + * URB_STALL/ * @retval None */ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state) @@ -628,19 +706,295 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t */ } +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User USB HCD Callback + * To be used instead of the weak predefined callback + * @param hhcd USB HCD handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID + * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID + * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID + * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID + * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID + * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_HCD_SOF_CB_ID : + hhcd->SOFCallback = pCallback; + break; + + case HAL_HCD_CONNECT_CB_ID : + hhcd->ConnectCallback = pCallback; + break; + + case HAL_HCD_DISCONNECT_CB_ID : + hhcd->DisconnectCallback = pCallback; + break; + + case HAL_HCD_PORT_ENABLED_CB_ID : + hhcd->PortEnabledCallback = pCallback; + break; + + case HAL_HCD_PORT_DISABLED_CB_ID : + hhcd->PortDisabledCallback = pCallback; + break; + + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = pCallback; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hhcd->State == HAL_HCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = pCallback; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + return status; +} + +/** + * @brief Unregister an USB HCD Callback + * USB HCD callabck is redirected to the weak predefined callback + * @param hhcd USB HCD handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID + * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID + * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID + * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID + * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID + * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hhcd); + + /* Setup Legacy weak Callbacks */ + if (hhcd->State == HAL_HCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_HCD_SOF_CB_ID : + hhcd->SOFCallback = HAL_HCD_SOF_Callback; + break; + + case HAL_HCD_CONNECT_CB_ID : + hhcd->ConnectCallback = HAL_HCD_Connect_Callback; + break; + + case HAL_HCD_DISCONNECT_CB_ID : + hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback; + break; + + case HAL_HCD_PORT_ENABLED_CB_ID : + hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback; + break; + + case HAL_HCD_PORT_DISABLED_CB_ID : + hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback; + break; + + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = HAL_HCD_MspInit; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hhcd->State == HAL_HCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = HAL_HCD_MspInit; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + return status; +} + +/** + * @brief Register USB HCD Host Channel Notify URB Change Callback + * To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback + * @param hhcd HCD handle + * @param pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + hhcd->HC_NotifyURBChangeCallback = pCallback; + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief UnRegister the USB HCD Host Channel Notify URB Change Callback + * USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback */ + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + + return status; +} +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + /** * @} */ -/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions - * @brief Management functions +/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions + * @brief Management functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the HCD data + This subsection provides a set of functions allowing to control the HCD data transfers. @endverbatim @@ -648,36 +1002,36 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t */ /** - * @brief Start the Host driver. - * @param hhcd: HCD handle + * @brief Start the host driver. + * @param hhcd HCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) -{ - __HAL_LOCK(hhcd); +{ + __HAL_LOCK(hhcd); __HAL_HCD_ENABLE(hhcd); - USB_DriveVbus(hhcd->Instance, 1); - __HAL_UNLOCK(hhcd); + (void)USB_DriveVbus(hhcd->Instance, 1U); + __HAL_UNLOCK(hhcd); return HAL_OK; } /** - * @brief Stop the Host driver. - * @param hhcd: HCD handle + * @brief Stop the host driver. + * @param hhcd HCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) -{ - __HAL_LOCK(hhcd); - USB_StopHost(hhcd->Instance); - __HAL_UNLOCK(hhcd); +{ + __HAL_LOCK(hhcd); + (void)USB_StopHost(hhcd->Instance); + __HAL_UNLOCK(hhcd); return HAL_OK; } /** - * @brief Reset the Host port. - * @param hhcd: HCD handle + * @brief Reset the host port. + * @param hhcd HCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) @@ -689,15 +1043,15 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) * @} */ -/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions +/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State functions ##### - =============================================================================== + =============================================================================== [..] - This subsection permits to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -706,7 +1060,7 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) /** * @brief Return the HCD handle state. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval HAL state */ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd) @@ -716,17 +1070,17 @@ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd) /** * @brief Return URB state for a channel. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval URB state. * This parameter can be one of these values: * URB_IDLE/ * URB_DONE/ * URB_NOTREADY/ - * URB_NYET/ - * URB_ERROR/ - * URB_STALL + * URB_NYET/ + * URB_ERROR/ + * URB_STALL */ HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum) { @@ -735,32 +1089,32 @@ HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnu /** - * @brief Return the last Host transfer size. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @brief Return the last host transfer size. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval last transfer size in byte */ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum) { - return hhcd->hc[chnum].xfer_count; + return hhcd->hc[chnum].xfer_count; } - + /** * @brief Return the Host Channel state. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval Host channel state * This parameter can be one of these values: * HC_IDLE/ * HC_XFRC/ * HC_HALTED/ - * HC_NYET/ - * HC_NAK/ - * HC_STALL/ - * HC_XACTERR/ - * HC_BBLERR/ + * HC_NYET/ + * HC_NAK/ + * HC_STALL/ + * HC_XACTERR/ + * HC_BBLERR/ * HC_DATATGLERR */ HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum) @@ -770,7 +1124,7 @@ HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum) /** * @brief Return the current Host frame number. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval Current Host frame number */ uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) @@ -780,7 +1134,7 @@ uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) /** * @brief Return the Host enumeration speed. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval Enumeration speed */ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) @@ -801,420 +1155,470 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) */ /** * @brief Handle Host Channel IN interrupt requests. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval none */ -static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) +static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint32_t tmpreg = 0; - - if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR) + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)chnum; + + uint32_t tmpreg; + + if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK) + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - hhcd->hc[chnum].state = HC_STALL; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); - USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].state = HC_STALL; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - hhcd->hc[chnum].state = HC_DATATGLERR; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); - } - - if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR) + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + hhcd->hc[ch_num].state = HC_DATATGLERR; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); + } + else { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); + /* ... */ } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC) + + if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) { - - if (hhcd->Init.dma_enable) + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) + { + if (hhcd->Init.dma_enable != 0U) + { + hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].xfer_len - \ + (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); + } + + hhcd->hc[ch_num].state = HC_XFRC; + hhcd->hc[ch_num].ErrCnt = 0U; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); + + if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) { - hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].xfer_len - \ - (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); } - - hhcd->hc[chnum].state = HC_XFRC; - hhcd->hc[chnum].ErrCnt = 0; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); - - - if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)|| - (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + else if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - + USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; + hhcd->hc[ch_num].urb_state = URB_DONE; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } - else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR) + else { - USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; - hhcd->hc[chnum].urb_state = URB_DONE; - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); + /* ... */ } - hhcd->hc[chnum].toggle_in ^= 1; - + hhcd->hc[ch_num].toggle_in ^= 1U; + } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) { - __HAL_HCD_MASK_HALT_HC_INT(chnum); - - if(hhcd->hc[chnum].state == HC_XFRC) + __HAL_HCD_MASK_HALT_HC_INT(ch_num); + + if (hhcd->hc[ch_num].state == HC_XFRC) { - hhcd->hc[chnum].urb_state = URB_DONE; + hhcd->hc[ch_num].urb_state = URB_DONE; } - - else if (hhcd->hc[chnum].state == HC_STALL) + else if (hhcd->hc[ch_num].state == HC_STALL) { - hhcd->hc[chnum].urb_state = URB_STALL; - } - - else if((hhcd->hc[chnum].state == HC_XACTERR) || - (hhcd->hc[chnum].state == HC_DATATGLERR)) + hhcd->hc[ch_num].urb_state = URB_STALL; + } + else if ((hhcd->hc[ch_num].state == HC_XACTERR) || + (hhcd->hc[ch_num].state == HC_DATATGLERR)) { - if(hhcd->hc[chnum].ErrCnt++ > 3) - { - hhcd->hc[chnum].ErrCnt = 0; - hhcd->hc[chnum].urb_state = URB_ERROR; + hhcd->hc[ch_num].ErrCnt++; + if (hhcd->hc[ch_num].ErrCnt > 3U) + { + hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[ch_num].urb_state = URB_ERROR; } else { - hhcd->hc[chnum].urb_state = URB_NOTREADY; + hhcd->hc[ch_num].urb_state = URB_NOTREADY; } - + /* re-activate the channel */ - tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg = USBx_HC(ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; + USBx_HC(ch_num)->HCCHAR = tmpreg; } - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); - } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR) + else if (hhcd->hc[ch_num].state == HC_NAK) + { + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + /* re-activate the channel */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + } + else + { + /* ... */ + } + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - hhcd->hc[chnum].ErrCnt++; - hhcd->hc[chnum].state = HC_XACTERR; - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].ErrCnt++; + hhcd->hc[ch_num].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK) - { - if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) + { + if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); + hhcd->hc[ch_num].ErrCnt = 0U; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } - - /* Clear the NAK flag before re-enabling the channel for new IN request */ - hhcd->hc[chnum].state = HC_NAK; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - - if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)|| - (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) { - /* re-activate the channel */ - USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS; - USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - + hhcd->hc[ch_num].ErrCnt = 0U; + if (hhcd->Init.dma_enable == 0U) + { + hhcd->hc[ch_num].state = HC_NAK; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + } + } + else + { + /* ... */ } + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + } + else + { + /* ... */ } } /** * @brief Handle Host Channel OUT interrupt requests. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval none */ -static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) +static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint32_t tmpreg = 0; - - if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR) + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)chnum; + uint32_t tmpreg; + + if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK) + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); - - if( hhcd->hc[chnum].do_ping == 1) + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); + + if (hhcd->hc[ch_num].do_ping == 1U) { - hhcd->hc[chnum].state = HC_NYET; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - hhcd->hc[chnum].urb_state = URB_NOTREADY; + hhcd->hc[ch_num].do_ping = 0U; + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NYET) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) { - hhcd->hc[chnum].state = HC_NYET; - hhcd->hc[chnum].ErrCnt= 0; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); - - } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR) + hhcd->hc[ch_num].state = HC_NYET; + hhcd->hc[ch_num].do_ping = 1U; + hhcd->hc[ch_num].ErrCnt = 0U; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) { - hhcd->hc[chnum].ErrCnt = 0; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); - hhcd->hc[chnum].state = HC_XFRC; - - } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL) + hhcd->hc[ch_num].ErrCnt = 0U; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); + hhcd->hc[ch_num].state = HC_XFRC; + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - hhcd->hc[chnum].state = HC_STALL; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[ch_num].state = HC_STALL; } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) + { + hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[ch_num].state = HC_NAK; - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK) - { - hhcd->hc[chnum].ErrCnt = 0; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - hhcd->hc[chnum].state = HC_NAK; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - } + if (hhcd->hc[ch_num].do_ping == 0U) + { + if (hhcd->hc[ch_num].speed == HCD_SPEED_HIGH) + { + hhcd->hc[ch_num].do_ping = 1U; + } + } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR) + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - hhcd->hc[chnum].state = HC_XACTERR; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[ch_num].state = HC_XACTERR; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); - hhcd->hc[chnum].state = HC_DATATGLERR; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); + hhcd->hc[ch_num].state = HC_DATATGLERR; } - - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) { - __HAL_HCD_MASK_HALT_HC_INT(chnum); - - if(hhcd->hc[chnum].state == HC_XFRC) + __HAL_HCD_MASK_HALT_HC_INT(ch_num); + + if (hhcd->hc[ch_num].state == HC_XFRC) { - hhcd->hc[chnum].urb_state = URB_DONE; - if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK) + hhcd->hc[ch_num].urb_state = URB_DONE; + if (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) { - hhcd->hc[chnum].toggle_out ^= 1; - } + hhcd->hc[ch_num].toggle_out ^= 1U; + } } - else if (hhcd->hc[chnum].state == HC_NAK) + else if (hhcd->hc[ch_num].state == HC_NAK) { - hhcd->hc[chnum].urb_state = URB_NOTREADY; - } - - else if (hhcd->hc[chnum].state == HC_NYET) + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + } + else if (hhcd->hc[ch_num].state == HC_NYET) { - hhcd->hc[chnum].urb_state = URB_NOTREADY; - hhcd->hc[chnum].do_ping = 0; - } - - else if (hhcd->hc[chnum].state == HC_STALL) + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + } + else if (hhcd->hc[ch_num].state == HC_STALL) { - hhcd->hc[chnum].urb_state = URB_STALL; - } - - else if((hhcd->hc[chnum].state == HC_XACTERR) || - (hhcd->hc[chnum].state == HC_DATATGLERR)) + hhcd->hc[ch_num].urb_state = URB_STALL; + } + else if ((hhcd->hc[ch_num].state == HC_XACTERR) || + (hhcd->hc[ch_num].state == HC_DATATGLERR)) { - if(hhcd->hc[chnum].ErrCnt++ > 3) - { - hhcd->hc[chnum].ErrCnt = 0; - hhcd->hc[chnum].urb_state = URB_ERROR; + hhcd->hc[ch_num].ErrCnt++; + if (hhcd->hc[ch_num].ErrCnt > 3U) + { + hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[ch_num].urb_state = URB_ERROR; } else { - hhcd->hc[chnum].urb_state = URB_NOTREADY; + hhcd->hc[ch_num].urb_state = URB_NOTREADY; } - + /* re-activate the channel */ - tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg = USBx_HC(ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; + USBx_HC(ch_num)->HCCHAR = tmpreg; } - - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); + else + { + /* ... */ + } + + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); } -} + else + { + /* ... */ + } +} /** * @brief Handle Rx Queue Level interrupt requests. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval none */ -static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd) +static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint8_t channelnum =0; + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; uint32_t pktsts; - uint32_t pktcnt; - uint32_t temp = 0; - uint32_t tmpreg = 0; - - temp = hhcd->Instance->GRXSTSP ; - channelnum = temp & USB_OTG_GRXSTSP_EPNUM; - pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17; - pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - + uint32_t pktcnt; + uint32_t temp; + uint32_t tmpreg; + uint32_t ch_num; + + temp = hhcd->Instance->GRXSTSP; + ch_num = temp & USB_OTG_GRXSTSP_EPNUM; + pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17; + pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + switch (pktsts) { - case GRXSTS_PKTSTS_IN: - /* Read the data into the Host buffer. */ - if ((pktcnt > 0) && (hhcd->hc[channelnum].xfer_buff != (void *)0)) - { - - USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt); - - /*manage multiple Xfer */ - hhcd->hc[channelnum].xfer_buff += pktcnt; - hhcd->hc[channelnum].xfer_count += pktcnt; - - if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0) + case GRXSTS_PKTSTS_IN: + /* Read the data into the host buffer. */ + if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0)) { - /* re-activate the channel when more packets are expected */ - tmpreg = USBx_HC(channelnum)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(channelnum)->HCCHAR = tmpreg; - hhcd->hc[channelnum].toggle_in ^= 1; + (void)USB_ReadPacket(hhcd->Instance, hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt); + + /*manage multiple Xfer */ + hhcd->hc[ch_num].xfer_buff += pktcnt; + hhcd->hc[ch_num].xfer_count += pktcnt; + + if ((USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U) + { + /* re-activate the channel when more packets are expected */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + hhcd->hc[ch_num].toggle_in ^= 1U; + } } - } - break; - - case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: - break; - case GRXSTS_PKTSTS_IN_XFER_COMP: - case GRXSTS_PKTSTS_CH_HALTED: - default: - break; + break; + + case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: + break; + + case GRXSTS_PKTSTS_IN_XFER_COMP: + case GRXSTS_PKTSTS_CH_HALTED: + default: + break; } } /** * @brief Handle Host Port interrupt requests. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ -static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) +static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; __IO uint32_t hprt0, hprt0_dup; - + /* Handle Host Port Interrupts */ hprt0 = USBx_HPRT0; hprt0_dup = USBx_HPRT0; - - hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - - /* Check whether Port Connect Detected */ - if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET) - { - if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS) + + hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \ + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + /* Check whether Port Connect detected */ + if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET) + { + if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS) { USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->ConnectCallback(hhcd); +#else HAL_HCD_Connect_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } hprt0_dup |= USB_OTG_HPRT_PCDET; - } - + /* Check whether Port Enable Changed */ - if((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG) + if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG) { hprt0_dup |= USB_OTG_HPRT_PENCHNG; - - if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA) - { - if(hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) + + if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA) + { + if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) { if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) { - USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ ); + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ); } else { - USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ ); + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); } } else { - if(hhcd->Init.speed == HCD_SPEED_FULL) + if (hhcd->Init.speed == HCD_SPEED_FULL) { - USBx_HOST->HFIR = (uint32_t)60000; + USBx_HOST->HFIR = 60000U; } } +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->PortEnabledCallback(hhcd); + hhcd->ConnectCallback(hhcd); +#else + HAL_HCD_PortEnabled_Callback(hhcd); HAL_HCD_Connect_Callback(hhcd); - - if(hhcd->Init.speed == HCD_SPEED_HIGH) - { - USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); - } +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } else { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->PortDisabledCallback(hhcd); +#else + HAL_HCD_PortDisabled_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + /* Cleanup HPRT */ - USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - - USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); - } + USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \ + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); + } } - - /* Check For an overcurrent */ - if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG) + + /* Check for an overcurrent */ + if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG) { hprt0_dup |= USB_OTG_HPRT_POCCHNG; } @@ -1231,7 +1635,10 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) * @} */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + #endif /* HAL_HCD_MODULE_ENABLED */ + /** * @} */ @@ -1240,8 +1647,4 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) * @} */ -#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c index 1bfc4a9c75..830eacd17d 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c @@ -19,7 +19,7 @@ (#) Declare a I2C_HandleTypeDef handle structure, for example: I2C_HandleTypeDef hi2c; - (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: + (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API: (##) Enable the I2Cx interface clock (##) I2C pins configuration (+++) Enable the clock for the I2C GPIOs @@ -39,54 +39,54 @@ (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. - (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. + (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API. - (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() + (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady() (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : *** Polling mode IO operation *** ================================= [..] - (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() - (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() - (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() - (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive() *** Polling mode IO MEM operation *** ===================================== [..] - (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() - (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() + (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read() *** Interrupt mode IO operation *** =================================== [..] - (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() - (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() - (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() - (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() - (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. - *** Interrupt mode IO sequential operation *** - ============================================== + *** Interrupt mode or DMA mode IO sequential operation *** + ========================================================== [..] (@) These interfaces allow to manage a sequential transfer with a repeated start condition when a direction change during transfer @@ -98,97 +98,114 @@ and data to transfer without a final stop condition (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition, an then permit a call the same master sequential interface - several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT()) + several times (like @ref HAL_I2C_Master_Sequential_Transmit_IT() then @ref HAL_I2C_Master_Sequential_Transmit_IT() + or @ref HAL_I2C_Master_Sequential_Transmit_DMA() then @ref HAL_I2C_Master_Sequential_Transmit_DMA()) (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address and with new data to transfer if the direction change or manage only the new data to transfer if no direction change and without a final stop condition in both cases (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address and with new data to transfer if the direction change or manage only the new data to transfer if no direction change and with a final stop condition in both cases + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential + interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using HAL_I2C_Master_Sequential_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Sequential_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Sequential_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Sequential_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. + (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential + interface. + Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Sequential_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Sequential_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Sequential_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Sequential_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). + Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. (+) Differents sequential I2C interfaces are listed below: - (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() - (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT() - (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() - (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Sequential_Transmit_IT() + or using @ref HAL_I2C_Master_Sequential_Transmit_DMA() + (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Sequential_Receive_IT() + or using @ref HAL_I2C_Master_Sequential_Receive_DMA() + (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). - (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() - (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT() - (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT() - (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Sequential_Transmit_IT() + or using @ref HAL_I2C_Slave_Sequential_Transmit_DMA() + (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Sequential_Receive_IT() + or using @ref HAL_I2C_Slave_Sequential_Receive_DMA() + (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. *** Interrupt mode IO MEM operation *** ======================================= [..] (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using - HAL_I2C_Mem_Write_IT() - (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + @ref HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using - HAL_I2C_Mem_Read_IT() - (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() + @ref HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() *** DMA mode IO operation *** ============================== [..] (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Master_Transmit_DMA() - (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + @ref HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() (+) Receive in master mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Master_Receive_DMA() - (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + @ref HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Slave_Transmit_DMA() - (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + @ref HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Slave_Receive_DMA() - (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + @ref HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. *** DMA mode IO MEM operation *** ================================= [..] (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using - HAL_I2C_Mem_Write_DMA() - (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + @ref HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using - HAL_I2C_Mem_Read_DMA() - (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() + @ref HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() *** I2C HAL driver macros list *** @@ -196,13 +213,78 @@ [..] Below the list of most used macros in I2C HAL driver. - (+) __HAL_I2C_ENABLE: Enable the I2C peripheral - (+) __HAL_I2C_DISABLE: Disable the I2C peripheral - (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode - (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not - (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag - (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt - (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + *** Callback registration *** + ============================================= + + The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() + to register an interrupt callback. + + Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback(). + + Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default + weak function. + @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + + For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback(). + + By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() + or @ref HAL_I2C_Init() function. + + When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. [..] (@) You can refer to the I2C HAL driver header file for more useful macros @@ -300,7 +382,7 @@ */ /* Private macro -------------------------------------------------------------*/ -#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \ +#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ? \ ((uint32_t)(((DMA_Channel_TypeDef *)(__HANDLE__)->hdmatx->Instance)->CNDTR)) : \ ((uint32_t)(((DMA_Channel_TypeDef *)(__HANDLE__)->hdmarx->Instance)->CNDTR))) @@ -345,14 +427,17 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); /* Private functions to centralize the enable/disable of Interrupts */ -static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); -static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); -/* Private functions to flush TXDR register */ +/* Private function to flush TXDR register */ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); -/* Private functions to handle start, restart or stop a transfer */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); +/* Private function to handle start, restart or stop a transfer */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); + +/* Private function to Convert Specific options */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); /** * @} */ @@ -406,6 +491,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) /* Check the I2C handle allocation */ if (hi2c == NULL) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } @@ -424,8 +510,30 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + /* Init the I2C Callback settings */ + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + + if (hi2c->MspInitCallback == NULL) + { + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hi2c->MspInitCallback(hi2c); +#else /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_I2C_MspInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; @@ -493,6 +601,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) /* Check the I2C handle allocation */ if (hi2c == NULL) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } @@ -504,8 +613,18 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) /* Disable the I2C Peripheral Clock */ __HAL_I2C_DISABLE(hi2c); +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + if (hi2c->MspDeInitCallback == NULL) + { + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hi2c->MspDeInitCallback(hi2c); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_I2C_MspDeInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->State = HAL_I2C_STATE_RESET; @@ -550,6 +669,328 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) */ } +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User I2C Callback + * To be used instead of the weak predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = pCallback; + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = pCallback; + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = pCallback; + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = pCallback; + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = pCallback; + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief Unregister an I2C Callback + * I2C callback is redirected to the weak predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief Register the Slave Address Match I2C Callback + * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief UnRegister the Slave Address Match I2C Callback + * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + /** * @} */ @@ -591,6 +1032,13 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) (++) HAL_I2C_Slave_Receive_IT() (++) HAL_I2C_Mem_Write_IT() (++) HAL_I2C_Mem_Read_IT() + (++) HAL_I2C_Master_Sequential_Transmit_IT() + (++) HAL_I2C_Master_Sequential_Receive_IT() + (++) HAL_I2C_Slave_Sequential_Transmit_IT() + (++) HAL_I2C_Slave_Sequential_Receive_IT() + (++) HAL_I2C_EnableListen_IT() + (++) HAL_I2C_DisableListen_IT() + (++) HAL_I2C_Master_Abort_IT() (#) No-Blocking mode functions with DMA are : (++) HAL_I2C_Master_Transmit_DMA() @@ -599,15 +1047,22 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) (++) HAL_I2C_Slave_Receive_DMA() (++) HAL_I2C_Mem_Write_DMA() (++) HAL_I2C_Mem_Read_DMA() + (++) HAL_I2C_Master_Sequential_Transmit_DMA() + (++) HAL_I2C_Master_Sequential_Receive_DMA() + (++) HAL_I2C_Slave_Sequential_Transmit_DMA() + (++) HAL_I2C_Slave_Sequential_Receive_DMA() (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_I2C_MemTxCpltCallback() - (++) HAL_I2C_MemRxCpltCallback() (++) HAL_I2C_MasterTxCpltCallback() (++) HAL_I2C_MasterRxCpltCallback() (++) HAL_I2C_SlaveTxCpltCallback() (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_AddrCallback() + (++) HAL_I2C_ListenCpltCallback() (++) HAL_I2C_ErrorCallback() + (++) HAL_I2C_AbortCpltCallback() @endverbatim * @{ @@ -618,7 +1073,7 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration @@ -626,7 +1081,7 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) */ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tickstart = 0U; + uint32_t tickstart; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -638,7 +1093,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } hi2c->State = HAL_I2C_STATE_BUSY_TX; @@ -668,26 +1123,19 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* Write data to TXDR */ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); hi2c->XferCount--; hi2c->XferSize--; - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) { /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } if (hi2c->XferCount > MAX_NBYTE_SIZE) @@ -707,14 +1155,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Wait until STOPF flag is set */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* Clear STOP Flag */ @@ -742,7 +1183,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration @@ -750,7 +1191,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA */ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tickstart = 0U; + uint32_t tickstart; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -762,7 +1203,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } hi2c->State = HAL_I2C_STATE_BUSY_RX; @@ -792,14 +1233,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* Wait until RXNE flag is set */ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* Read data from RXDR */ @@ -807,12 +1241,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd hi2c->XferSize--; hi2c->XferCount--; - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) { /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } if (hi2c->XferCount > MAX_NBYTE_SIZE) @@ -832,14 +1266,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* Wait until STOPF flag is set */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* Clear STOP Flag */ @@ -873,12 +1300,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tickstart = 0U; + uint32_t tickstart; if (hi2c->State == HAL_I2C_STATE_READY) { if ((pData == NULL) || (Size == 0U)) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } /* Process Locked */ @@ -904,7 +1332,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; + return HAL_ERROR; } /* Clear ADDR flag */ @@ -918,7 +1346,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; + return HAL_ERROR; } /* Clear ADDR flag */ @@ -930,7 +1358,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; + return HAL_ERROR; } while (hi2c->XferCount > 0U) @@ -940,15 +1368,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* Write data to TXDR */ @@ -970,7 +1390,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } else { - return HAL_TIMEOUT; + return HAL_ERROR; } } @@ -982,7 +1402,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; + return HAL_ERROR; } /* Disable Address Acknowledge */ @@ -1013,12 +1433,13 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData */ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tickstart = 0U; + uint32_t tickstart; if (hi2c->State == HAL_I2C_STATE_READY) { if ((pData == NULL) || (Size == 0U)) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } /* Process Locked */ @@ -1044,7 +1465,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; + return HAL_ERROR; } /* Clear ADDR flag */ @@ -1055,7 +1476,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; + return HAL_ERROR; } while (hi2c->XferCount > 0U) @@ -1074,14 +1495,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, hi2c->XferCount--; } - if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) - { - return HAL_TIMEOUT; - } - else - { - return HAL_ERROR; - } + return HAL_ERROR; } /* Read data from RXDR */ @@ -1094,15 +1508,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* Clear STOP flag */ @@ -1113,7 +1519,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; + return HAL_ERROR; } /* Disable Address Acknowledge */ @@ -1138,14 +1544,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { - uint32_t xfermode = 0U; + uint32_t xfermode; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1207,14 +1613,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { - uint32_t xfermode = 0U; + uint32_t xfermode; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1374,14 +1780,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { - uint32_t xfermode = 0U; + uint32_t xfermode; + uint32_t dmaxferstatus; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1416,46 +1823,80 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t if (hi2c->XferSize > 0U) { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - else - { - /* Update Transfer ISR function pointer */ - hi2c->XferISR = I2C_Master_ISR_IT; + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; - /* Send Slave Address */ - /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1482,14 +1923,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { - uint32_t xfermode = 0U; + uint32_t xfermode; + uint32_t dmaxferstatus; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1524,37 +1966,71 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D if (hi2c->XferSize > 0U) { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Send Slave Address */ - /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } } else { @@ -1576,6 +2052,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } + return HAL_OK; } else @@ -1594,10 +2071,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { + uint32_t dmaxferstatus; + if (hi2c->State == HAL_I2C_STATE_READY) { if ((pData == NULL) || (Size == 0U)) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } /* Process Locked */ @@ -1614,33 +2094,67 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_DMA; - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + return HAL_ERROR; + } - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } return HAL_OK; } @@ -1660,10 +2174,13 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p */ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { + uint32_t dmaxferstatus; + if (hi2c->State == HAL_I2C_STATE_READY) { if ((pData == NULL) || (Size == 0U)) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } /* Process Locked */ @@ -1680,33 +2197,67 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_DMA; - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + return HAL_ERROR; + } - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } return HAL_OK; } @@ -1720,7 +2271,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -1730,7 +2281,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD */ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tickstart = 0U; + uint32_t tickstart; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -1739,6 +2290,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress { if ((pData == NULL) || (Size == 0U)) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } @@ -1750,7 +2302,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } hi2c->State = HAL_I2C_STATE_BUSY_TX; @@ -1765,18 +2317,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ @@ -1796,14 +2339,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* Write data to TXDR */ @@ -1811,12 +2347,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress hi2c->XferCount--; hi2c->XferSize--; - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) { /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } if (hi2c->XferCount > MAX_NBYTE_SIZE) @@ -1838,14 +2374,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /* Wait until STOPF flag is reset */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* Clear STOP Flag */ @@ -1873,7 +2402,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -1883,7 +2412,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress */ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tickstart = 0U; + uint32_t tickstart; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -1892,6 +2421,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, { if ((pData == NULL) || (Size == 0U)) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } @@ -1903,7 +2433,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } hi2c->State = HAL_I2C_STATE_BUSY_RX; @@ -1918,18 +2448,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; } /* Send Slave Address */ @@ -1950,7 +2471,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Wait until RXNE flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } /* Read data from RXDR */ @@ -1958,12 +2479,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, hi2c->XferSize--; hi2c->XferCount--; - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) { /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } if (hi2c->XferCount > MAX_NBYTE_SIZE) @@ -1984,14 +2505,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Wait until STOPF flag is reset */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* Clear STOP Flag */ @@ -2018,7 +2532,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2027,8 +2541,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, */ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; + uint32_t tickstart; + uint32_t xfermode; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -2037,6 +2551,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr { if ((pData == NULL) || (Size == 0U)) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } @@ -2075,18 +2590,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ @@ -2117,7 +2623,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2126,8 +2632,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr */ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; + uint32_t tickstart; + uint32_t xfermode; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -2136,6 +2642,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre { if ((pData == NULL) || (Size == 0U)) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } @@ -2174,18 +2681,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ @@ -2215,7 +2713,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2224,8 +2722,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre */ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; + uint32_t tickstart; + uint32_t xfermode; + uint32_t dmaxferstatus; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -2234,6 +2733,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd { if ((pData == NULL) || (Size == 0U)) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } @@ -2272,51 +2772,77 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; } - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + return HAL_ERROR; + } - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } return HAL_OK; } @@ -2331,7 +2857,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2340,8 +2866,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd */ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; + uint32_t tickstart; + uint32_t xfermode; + uint32_t dmaxferstatus; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -2350,6 +2877,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr { if ((pData == NULL) || (Size == 0U)) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } @@ -2388,50 +2916,75 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; } - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; + return HAL_ERROR; + } - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + if (dmaxferstatus == HAL_OK) + { + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } return HAL_OK; } @@ -2447,14 +3000,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param Trials Number of trials * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) { - uint32_t tickstart = 0U; + uint32_t tickstart; __IO uint32_t I2C_Trials = 0U; @@ -2483,13 +3036,18 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd { if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - /* Device is ready */ + /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; + + return HAL_ERROR; } } } @@ -2500,7 +3058,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } /* Clear STOP Flag */ @@ -2519,7 +3077,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } /* Clear NACK Flag */ @@ -2538,7 +3096,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } /* Clear STOP Flag */ @@ -2547,12 +3105,16 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd } while (I2C_Trials < Trials); + /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; + return HAL_ERROR; } else { @@ -2566,7 +3128,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS @@ -2574,7 +3136,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd */ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { - uint32_t xfermode = 0U; + uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_WRITE; /* Check the parameters */ @@ -2595,7 +3157,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Master_ISR_IT; - /* If size > MAX_NBYTE_SIZE, use reload mode */ + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; @@ -2607,12 +3169,23 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, xfermode = hi2c->XferOptions; } - /* If transfer direction not change, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(hi2c->XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount < MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } /* Send Slave Address and set NBYTES to write */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); @@ -2634,21 +3207,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, } /** - * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. * @note This interface allow to manage repeated start condition when a direction change during transfer * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { - uint32_t xfermode = 0U; - uint32_t xferrequest = I2C_GENERATE_START_READ; + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -2658,7 +3231,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -2666,7 +3239,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Master_ISR_IT; + hi2c->XferISR = I2C_Master_ISR_DMA; /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ if (hi2c->XferCount > MAX_NBYTE_SIZE) @@ -2680,23 +3253,94 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, xfermode = hi2c->XferOptions; } - /* If transfer direction not change, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(hi2c->XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); - /* Send Slave Address and set NBYTES to read */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount < MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } return HAL_OK; } @@ -2707,54 +3351,290 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, } /** - * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt * @note This interface allow to manage repeated start condition when a direction change during transfer * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if (hi2c->State == HAL_I2C_STATE_READY) { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); - /* Process Locked */ __HAL_LOCK(hi2c); - /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ - /* and then toggle the HAL slave RX state to TX state */ - if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) - { - /* Disable associated Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - } - - hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; - hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Slave_ISR_IT; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(hi2c->XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount < MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(hi2c->XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount < MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + HAL_DMA_Abort_IT(hi2c->hdmarx); + } + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) { @@ -2780,6 +3660,136 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, } } +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + HAL_DMA_Abort_IT(hi2c->hdmarx); + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + HAL_DMA_Abort_IT(hi2c->hdmatx); + } + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + /** * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt * @note This interface allow to manage repeated start condition when a direction change during transfer @@ -2799,6 +3809,89 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u { if ((pData == NULL) || (Size == 0U)) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + HAL_DMA_Abort_IT(hi2c->hdmatx); + } + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } @@ -2814,6 +3907,22 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u { /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + HAL_DMA_Abort_IT(hi2c->hdmatx); + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + HAL_DMA_Abort_IT(hi2c->hdmarx); + } } hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; @@ -2828,7 +3937,43 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u hi2c->XferCount = Size; hi2c->XferSize = hi2c->XferCount; hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Slave_ISR_IT; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) { @@ -2846,6 +3991,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u /* REnable ADDR interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + return HAL_OK; } else @@ -2914,7 +4062,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) @@ -3263,7 +4411,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) */ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { - uint16_t devaddress = 0U; + uint16_t devaddress; /* Process Locked */ __HAL_LOCK(hi2c); @@ -3297,7 +4445,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin } else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) { devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); @@ -3361,6 +4509,10 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); } } + else + { + /* Nothing to do */ + } if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { @@ -3473,6 +4625,10 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint } } } + else + { + /* Nothing to do */ + } /* Check if STOPF is set */ if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) @@ -3497,8 +4653,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint */ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { - uint16_t devaddress = 0U; - uint32_t xfermode = 0U; + uint16_t devaddress; + uint32_t xfermode; /* Process Locked */ __HAL_LOCK(hi2c); @@ -3538,7 +4694,14 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui else { hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + xfermode = hi2c->XferOptions; + } + else + { + xfermode = I2C_AUTOEND_MODE; + } } /* Set the new XferSize in Nbytes register */ @@ -3559,7 +4722,42 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui } else { - /* Wrong size Status regarding TCR flag event */ + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSequentialCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSequentialCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); } @@ -3569,6 +4767,10 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); } + else + { + /* Nothing to do */ + } /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3595,31 +4797,64 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0 */ /* So clear Flag NACKF only */ - if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) + if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || + ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + if (((hi2c->hdmarx != NULL) || (hi2c->hdmatx != NULL)) && (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U)) + { + if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ + (hi2c->State == HAL_I2C_STATE_LISTEN)) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } + else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSequentialCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } } else { - /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ - /* Clear NACK Flag */ + /* Only Clear NACK Flag, no DMA treatment is pending */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } } else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + I2C_ITAddrCplt(hi2c, ITFlags); } else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); } + else + { + /* Nothing to do */ + } /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3632,7 +4867,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param Timeout Timeout duration @@ -3646,14 +4881,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* If Memory address size is 8Bit */ @@ -3671,14 +4899,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* Send LSB of Memory Address */ @@ -3688,7 +4909,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } return HAL_OK; @@ -3699,7 +4920,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param Timeout Timeout duration @@ -3713,14 +4934,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* If Memory address size is 8Bit */ @@ -3738,14 +4952,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* Send LSB of Memory Address */ @@ -3755,7 +4962,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t /* Wait until TC flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } return HAL_OK; @@ -3769,10 +4976,10 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t */ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { - uint8_t transferdirection = 0U; - uint16_t slaveaddrcode = 0U; - uint16_t ownadd1code = 0U; - uint16_t ownadd2code = 0U; + uint8_t transferdirection; + uint16_t slaveaddrcode; + uint16_t ownadd1code; + uint16_t ownadd2code; /* Prevent unused argument(s) compilation warning */ UNUSED(ITFlags); @@ -3804,7 +5011,11 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) __HAL_UNLOCK(hi2c); /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } else @@ -3818,7 +5029,11 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) __HAL_UNLOCK(hi2c); /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } /* else 7 bits addressing mode is selected */ @@ -3831,7 +5046,11 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) __HAL_UNLOCK(hi2c); /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } /* Else clear address flag only */ @@ -3870,7 +5089,11 @@ static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c) __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ else @@ -3886,7 +5109,11 @@ static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c) __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } @@ -3912,8 +5139,12 @@ static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) /* Process Unlocked */ __HAL_UNLOCK(hi2c); - /* Call the Tx complete callback to inform upper layer of the end of transmit process */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) @@ -3928,8 +5159,16 @@ static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) /* Process Unlocked */ __HAL_UNLOCK(hi2c); - /* Call the Rx complete callback to inform upper layer of the end of receive process */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ } } @@ -3986,7 +5225,11 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } else { @@ -3996,7 +5239,11 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ @@ -4011,7 +5258,12 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Process Unlocked */ __HAL_UNLOCK(hi2c); + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } else { @@ -4020,7 +5272,12 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Process Unlocked */ __HAL_UNLOCK(hi2c); + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } } @@ -4055,14 +5312,10 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) { - hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c); - } - - /* All data are not transferred, so set error code accordingly */ - if (hi2c->XferCount != 0U) - { - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + if ((hi2c->hdmarx != NULL) || (hi2c->hdmatx != NULL)) + { + hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c); + } } /* Store Last receive data if any */ @@ -4075,12 +5328,16 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { hi2c->XferSize--; hi2c->XferCount--; - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } } + /* All data are not transferred, so set error code accordingly */ + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + hi2c->PreviousState = I2C_STATE_NONE; hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; @@ -4106,7 +5363,11 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) __HAL_UNLOCK(hi2c); /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } /* Call the corresponding callback to inform upper layer of End of Transfer */ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) @@ -4116,8 +5377,12 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Process Unlocked */ __HAL_UNLOCK(hi2c); - /* Call the Slave Rx Complete callback */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } else { @@ -4126,8 +5391,12 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Process Unlocked */ __HAL_UNLOCK(hi2c); - /* Call the Slave Tx Complete callback */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } @@ -4172,7 +5441,11 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) __HAL_UNLOCK(hi2c); /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } /** @@ -4225,18 +5498,21 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - /* Set the I2C DMA Abort callback : + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) - { - /* Call Directly XferAbortCallback function in case of error */ - hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } } } /* Abort DMA RX transfer if any */ @@ -4244,18 +5520,21 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) - { - /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ - hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } } } else if (hi2c->State == HAL_I2C_STATE_ABORT) @@ -4266,7 +5545,11 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } else { @@ -4274,7 +5557,11 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } @@ -4334,10 +5621,16 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) } /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Enable TC interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } } } @@ -4348,12 +5641,23 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - /* No specific action, Master fully manage the generation of STOP condition */ - /* Mean that this generation can arrive at any time, at the end or during DMA process */ - /* So STOP condition should be manage through Interrupt treatment */ + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSequentialCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } } /** @@ -4391,10 +5695,16 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) } /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); - - /* Enable TC interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } } } @@ -4405,12 +5715,23 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if ((I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) && \ + (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - /* No specific action, Master fully manage the generation of STOP condition */ - /* Mean that this generation can arrive at any time, at the end or during DMA process */ - /* So STOP condition should be manage through Interrupt treatment */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSequentialCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } } /** @@ -4452,12 +5773,20 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) hi2c->State = HAL_I2C_STATE_READY; /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } else { /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } @@ -4478,14 +5807,15 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; + return HAL_ERROR; } } } @@ -4513,7 +5843,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -4522,7 +5852,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; + return HAL_ERROR; } } } @@ -4548,7 +5878,7 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, } /* Check for the Timeout */ - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -4557,7 +5887,7 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; + return HAL_ERROR; } } return HAL_OK; @@ -4612,7 +5942,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, } /* Check for the Timeout */ - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -4620,7 +5950,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; + return HAL_ERROR; } } return HAL_OK; @@ -4645,14 +5975,16 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; + + return HAL_ERROR; } } } @@ -4669,7 +6001,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - hi2c->ErrorCode = HAL_I2C_ERROR_AF; + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; @@ -4700,7 +6032,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); @@ -4717,9 +6049,9 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) { uint32_t tmpisr = 0U; @@ -4781,8 +6113,6 @@ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Interr /* to avoid the risk of I2C interrupt handle execution before */ /* all interrupts requested done */ __HAL_I2C_ENABLE_IT(hi2c, tmpisr); - - return HAL_OK; } /** @@ -4790,9 +6120,9 @@ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Interr * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) { uint32_t tmpisr = 0U; @@ -4848,8 +6178,34 @@ static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Inter /* to avoid a breaking situation like at "t" time */ /* all disable interrupts request are not done */ __HAL_I2C_DISABLE_IT(hi2c, tmpisr); +} - return HAL_OK; +/** + * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +{ + /* if user set XferOptions to I2C_OTHER_FRAME */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to I2C_FIRST_FRAME */ + if (hi2c->XferOptions == I2C_OTHER_FRAME) + { + hi2c->XferOptions = I2C_FIRST_FRAME; + } + /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ + else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) + { + hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; + } + else + { + /* Nothing to do */ + } } /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c index 231389bae8..e8bfa650fa 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c @@ -156,7 +156,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t */ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) { - uint32_t tmpreg = 0U; + uint32_t tmpreg; /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_irda.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_irda.c index de7e6c6e62..41fc911a97 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_irda.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_irda.c @@ -26,13 +26,13 @@ (+++) Enable the clock for the USARTx/UARTx GPIOs. (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input). (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT() - and HAL_IRDA_Receive_IT() APIs): + and HAL_IRDA_Receive_IT() APIs): (+++) Configure the USARTx/UARTx interrupt priority. - (+++) Enable the NVIC USARTx/UARTx IRQ handle. + (+++) Enable the NVIC USARTx/UARTx IRQ handle. (+++) The specific IRDA interrupts (Transmission complete interrupt, RXNE interrupt and Error Interrupts) will be managed using the macros __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process. - + (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA() and HAL_IRDA_Receive_DMA() APIs): (+++) Declare a DMA handle structure for the Tx/Rx channel. @@ -48,11 +48,11 @@ (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API: (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized HAL_IRDA_MspInit() API. - + -@@- The specific IRDA interrupts (Transmission complete interrupt, RXNE interrupt and Error Interrupts) will be managed using the macros __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process. - + (#) Three operation modes are available within this driver : *** Polling mode IO operation *** @@ -105,6 +105,71 @@ [..] (@) You can refer to the IRDA HAL driver header file for more useful macros + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback. + Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) MspInitCallback : IRDA MspInit. + (+) MspDeInitCallback : IRDA MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) MspInitCallback : IRDA MspInit. + (+) MspDeInitCallback : IRDA MspDeInit. + + [..] + By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET + all callbacks are set to the corresponding weak (surcharged) functions: + examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init() + and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit() + or @ref HAL_IRDA_Init() function. + + [..] + When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak (surcharged) callbacks are used. + + @endverbatim ****************************************************************************** * @attention @@ -155,7 +220,7 @@ /** @defgroup IRDA_Private_Constants IRDA Private Constants * @{ */ -#define IRDA_TEACK_REACK_TIMEOUT 1000 /*!< IRDA TX or RX enable acknowledge time-out value */ +#define IRDA_TEACK_REACK_TIMEOUT 1000U /*!< IRDA TX or RX enable acknowledge time-out value */ #define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \ | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */ @@ -168,6 +233,9 @@ */ /* Private macros ------------------------------------------------------------*/ +/** @defgroup IRDA_Private_Macros IRDA Private Macros + * @{ + */ #if defined(USART_PRESC_PRESCALER) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. * @param __PCLK__ IRDA clock source. @@ -175,26 +243,38 @@ * @param __PRESCALER__ IRDA clock prescaler value. * @retval Division result */ -#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__) ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)]) + ((__BAUD__)/2)) / (__BAUD__)) +#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__) ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__)) #else /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. * @param __PCLK__ IRDA clock source. * @param __BAUD__ Baud rate set by the user. * @retval Division result */ -#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2)) / (__BAUD__)) +#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__)) #endif +/** + * @} + */ /* Private variables ---------------------------------------------------------*/ +/** @defgroup IRDA_Private_Variables IRDA Private Variables + * @{ + */ #if defined(USART_PRESC_PRESCALER) static const uint16_t IRDAPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; #else #endif +/** + * @} + */ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup IRDA_Private_Functions * @{ */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); @@ -248,10 +328,10 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); @endverbatim - Depending on the frame length defined by the M1 and M0 bits (7-bit, - 8-bit or 9-bit), the possible IRDA frame formats are listed in the + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible IRDA frame formats are listed in the following table. - + Table 1. IRDA frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | IRDA frame | @@ -282,7 +362,7 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) { /* Check the IRDA handle allocation */ - if(hirda == NULL) + if (hirda == NULL) { return HAL_ERROR; } @@ -290,13 +370,25 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) /* Check the USART/UART associated to the IRDA handle */ assert_param(IS_IRDA_INSTANCE(hirda->Instance)); - if(hirda->gState == HAL_IRDA_STATE_RESET) + if (hirda->gState == HAL_IRDA_STATE_RESET) { /* Allocate lock resource and initialize it */ hirda->Lock = HAL_UNLOCKED; +#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1 + IRDA_InitCallbacksToDefault(hirda); + + if (hirda->MspInitCallback == NULL) + { + hirda->MspInitCallback = HAL_IRDA_MspInit; + } + + /* Init the low level hardware */ + hirda->MspInitCallback(hirda); +#else /* Init the low level hardware : GPIO, CLOCK */ HAL_IRDA_MspInit(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ } hirda->gState = HAL_IRDA_STATE_BUSY; @@ -335,7 +427,7 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) { /* Check the IRDA handle allocation */ - if(hirda == NULL) + if (hirda == NULL) { return HAL_ERROR; } @@ -346,7 +438,16 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) hirda->gState = HAL_IRDA_STATE_BUSY; /* DeInit the low level hardware */ +#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1 + if (hirda->MspDeInitCallback == NULL) + { + hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; + } + /* DeInit the low level hardware */ + hirda->MspDeInitCallback(hirda); +#else HAL_IRDA_MspDeInit(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ /* Disable the Peripheral */ __HAL_IRDA_DISABLE(hirda); @@ -392,6 +493,244 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) */ } +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User IRDA Callback + * To be used instead of the weak predefined callback + * @param hirda irda handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hirda); + + if (hirda->gState == HAL_IRDA_STATE_READY) + { + switch (CallbackID) + { + case HAL_IRDA_TX_HALFCOMPLETE_CB_ID : + hirda->TxHalfCpltCallback = pCallback; + break; + + case HAL_IRDA_TX_COMPLETE_CB_ID : + hirda->TxCpltCallback = pCallback; + break; + + case HAL_IRDA_RX_HALFCOMPLETE_CB_ID : + hirda->RxHalfCpltCallback = pCallback; + break; + + case HAL_IRDA_RX_COMPLETE_CB_ID : + hirda->RxCpltCallback = pCallback; + break; + + case HAL_IRDA_ERROR_CB_ID : + hirda->ErrorCallback = pCallback; + break; + + case HAL_IRDA_ABORT_COMPLETE_CB_ID : + hirda->AbortCpltCallback = pCallback; + break; + + case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : + hirda->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : + hirda->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_IRDA_MSPINIT_CB_ID : + hirda->MspInitCallback = pCallback; + break; + + case HAL_IRDA_MSPDEINIT_CB_ID : + hirda->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hirda->gState == HAL_IRDA_STATE_RESET) + { + switch (CallbackID) + { + case HAL_IRDA_MSPINIT_CB_ID : + hirda->MspInitCallback = pCallback; + break; + + case HAL_IRDA_MSPDEINIT_CB_ID : + hirda->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hirda); + + return status; +} + +/** + * @brief Unregister an IRDA callback + * IRDA callback is redirected to the weak predefined callback + * @param hirda irda handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hirda); + + if (HAL_IRDA_STATE_READY == hirda->gState) + { + switch (CallbackID) + { + case HAL_IRDA_TX_HALFCOMPLETE_CB_ID : + hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_IRDA_TX_COMPLETE_CB_ID : + hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_IRDA_RX_HALFCOMPLETE_CB_ID : + hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_IRDA_RX_COMPLETE_CB_ID : + hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_IRDA_ERROR_CB_ID : + hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_IRDA_ABORT_COMPLETE_CB_ID : + hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : + hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + break; + + case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : + hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + break; + + case HAL_IRDA_MSPINIT_CB_ID : + hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_IRDA_MSPDEINIT_CB_ID : + hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_IRDA_STATE_RESET == hirda->gState) + { + switch (CallbackID) + { + case HAL_IRDA_MSPINIT_CB_ID : + hirda->MspInitCallback = HAL_IRDA_MspInit; + break; + + case HAL_IRDA_MSPDEINIT_CB_ID : + hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; + break; + + default : + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hirda); + + return status; +} +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + /** * @} */ @@ -464,7 +803,7 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side. @@ -488,13 +827,13 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) */ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; - uint32_t tickstart = 0; + uint16_t *tmp; + uint32_t tickstart = 0U; /* Check that a Tx process is not already ongoing */ - if(hirda->gState == HAL_IRDA_STATE_READY) + if (hirda->gState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -510,19 +849,19 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u hirda->TxXferSize = Size; hirda->TxXferCount = Size; - while(hirda->TxXferCount > 0) + while (hirda->TxXferCount > 0U) { hirda->TxXferCount--; - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) { - tmp = (uint16_t*) pData; + tmp = (uint16_t *) pData; hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF); - pData += 2; + pData += 2U; } else { @@ -530,7 +869,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u } } - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -560,14 +899,14 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u */ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; + uint16_t *tmp; uint16_t uhMask; - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check that a Rx process is not already ongoing */ - if(hirda->RxState == HAL_IRDA_STATE_READY) + if (hirda->RxState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -590,19 +929,19 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui uhMask = hirda->Mask; /* Check data remaining to be received */ - while(hirda->RxXferCount > 0) + while (hirda->RxXferCount > 0U) { hirda->RxXferCount--; - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) { - tmp = (uint16_t*) pData ; + tmp = (uint16_t *) pData ; *tmp = (uint16_t)(hirda->Instance->RDR & uhMask); - pData +=2; + pData += 2U; } else { @@ -635,9 +974,9 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ - if(hirda->gState == HAL_IRDA_STATE_READY) + if (hirda->gState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -661,7 +1000,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData #else SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE); #endif - + return HAL_OK; } else @@ -681,9 +1020,9 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { /* Check that a Rx process is not already ongoing */ - if(hirda->RxState == HAL_IRDA_STATE_READY) + if (hirda->RxState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -707,9 +1046,9 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, /* Enable the IRDA Parity Error and Data Register not empty Interrupts */ #if defined(USART_CR1_FIFOEN) - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE_RXFNEIE); + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); #else - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE); + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); #endif /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ @@ -734,9 +1073,9 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ - if(hirda->gState == HAL_IRDA_STATE_READY) + if (hirda->gState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -786,20 +1125,20 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat /** * @brief Receive an amount of data in DMA mode. + * @note When the IRDA parity is enabled (PCE = 1), the received data contains + * the parity bit (MSB position). * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @param pData Pointer to data buffer. * @param Size Amount of data to be received. - * @note When the IRDA parity is enabled (PCE = 1), the received data contains - * the parity bit (MSB position). * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { /* Check that a Rx process is not already ongoing */ - if(hirda->RxState == HAL_IRDA_STATE_READY) + if (hirda->RxState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -895,12 +1234,12 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) /* Process Locked */ __HAL_LOCK(hirda); - if(hirda->gState == HAL_IRDA_STATE_BUSY_TX) + if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) { /* Enable the IRDA DMA Tx request */ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); } - if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX) + if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) { /* Clear the Overrun flag before resuming the Rx transfer*/ __HAL_IRDA_CLEAR_OREFLAG(hirda); @@ -929,9 +1268,9 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) { /* The Lock is not implemented on this API to allow the user application to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() / - HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback: - indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete - interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of the stream and the corresponding call back is executed. */ /* Stop IRDA DMA Tx request if ongoing */ @@ -941,7 +1280,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); /* Abort the IRDA DMA Tx channel */ - if(hirda->hdmatx != NULL) + if (hirda->hdmatx != NULL) { HAL_DMA_Abort(hirda->hdmatx); } @@ -956,7 +1295,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); /* Abort the IRDA DMA Rx channel */ - if(hirda->hdmarx != NULL) + if (hirda->hdmarx != NULL) { HAL_DMA_Abort(hirda->hdmarx); } @@ -971,7 +1310,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) * @brief Abort ongoing transfers (blocking mode). * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable IRDA Interrupts (Tx and Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -996,9 +1335,9 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */ - if(hirda->hdmatx != NULL) + if (hirda->hdmatx != NULL) { - /* Set the IRDA DMA Abort callback to Null. + /* Set the IRDA DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ hirda->hdmatx->XferAbortCallback = NULL; @@ -1012,9 +1351,9 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */ - if(hirda->hdmarx != NULL) + if (hirda->hdmarx != NULL) { - /* Set the IRDA DMA Abort callback to Null. + /* Set the IRDA DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ hirda->hdmarx->XferAbortCallback = NULL; @@ -1023,8 +1362,8 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) } /* Reset Tx and Rx transfer counters */ - hirda->TxXferCount = 0; - hirda->RxXferCount = 0; + hirda->TxXferCount = 0U; + hirda->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); @@ -1043,7 +1382,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) * @brief Abort ongoing Transmit transfer (blocking mode). * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable IRDA Interrupts (Tx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1067,9 +1406,9 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */ - if(hirda->hdmatx != NULL) + if (hirda->hdmatx != NULL) { - /* Set the IRDA DMA Abort callback to Null. + /* Set the IRDA DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ hirda->hdmatx->XferAbortCallback = NULL; @@ -1078,7 +1417,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) } /* Reset Tx transfer counter */ - hirda->TxXferCount = 0; + hirda->TxXferCount = 0U; /* Restore hirda->gState to Ready */ hirda->gState = HAL_IRDA_STATE_READY; @@ -1090,7 +1429,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) * @brief Abort ongoing Receive transfer (blocking mode). * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable IRDA Interrupts (Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1115,9 +1454,9 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */ - if(hirda->hdmarx != NULL) + if (hirda->hdmarx != NULL) { - /* Set the IRDA DMA Abort callback to Null. + /* Set the IRDA DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ hirda->hdmarx->XferAbortCallback = NULL; @@ -1126,7 +1465,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) } /* Reset Rx transfer counter */ - hirda->RxXferCount = 0; + hirda->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); @@ -1141,7 +1480,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) * @brief Abort ongoing transfers (Interrupt mode). * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable IRDA Interrupts (Tx and Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1154,8 +1493,8 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) */ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) { - uint32_t abortcplt = 1; - + uint32_t abortcplt = 1U; + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ #if defined(USART_CR1_FIFOEN) CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); @@ -1167,11 +1506,11 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ /* DMA Tx Handle is valid */ - if(hirda->hdmatx != NULL) + if (hirda->hdmatx != NULL) { /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled. Otherwise, set it to NULL */ - if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) { hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback; } @@ -1181,11 +1520,11 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) } } /* DMA Rx Handle is valid */ - if(hirda->hdmarx != NULL) + if (hirda->hdmarx != NULL) { /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled. Otherwise, set it to NULL */ - if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) { hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback; } @@ -1194,27 +1533,27 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) hirda->hdmarx->XferAbortCallback = NULL; } } - + /* Disable the IRDA DMA Tx request if enabled */ - if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) { /* Disable DMA Tx at UART level */ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */ - if(hirda->hdmatx != NULL) + if (hirda->hdmatx != NULL) { - /* IRDA Tx DMA Abort callback has already been initialised : + /* IRDA Tx DMA Abort callback has already been initialised : will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK) + if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK) { hirda->hdmatx->XferAbortCallback = NULL; } else { - abortcplt = 0; + abortcplt = 0U; } } } @@ -1225,30 +1564,30 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */ - if(hirda->hdmarx != NULL) + if (hirda->hdmarx != NULL) { - /* IRDA Rx DMA Abort callback has already been initialised : + /* IRDA Rx DMA Abort callback has already been initialised : will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) { hirda->hdmarx->XferAbortCallback = NULL; - abortcplt = 1; + abortcplt = 1U; } else { - abortcplt = 0; + abortcplt = 0U; } } } /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ - if (abortcplt == 1) + if (abortcplt == 1U) { /* Reset Tx and Rx transfer counters */ - hirda->TxXferCount = 0; - hirda->RxXferCount = 0; + hirda->TxXferCount = 0U; + hirda->RxXferCount = 0U; /* Reset errorCode */ hirda->ErrorCode = HAL_IRDA_ERROR_NONE; @@ -1261,7 +1600,13 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) hirda->RxState = HAL_IRDA_STATE_READY; /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hirda->AbortCpltCallback(hirda); +#else + /* Call legacy weak Abort complete callback */ HAL_IRDA_AbortCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } return HAL_OK; @@ -1271,7 +1616,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) * @brief Abort ongoing Transmit transfer (Interrupt mode). * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable IRDA Interrupts (Tx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1297,14 +1642,14 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */ - if(hirda->hdmatx != NULL) + if (hirda->hdmatx != NULL) { - /* Set the IRDA DMA Abort callback : + /* Set the IRDA DMA Abort callback : will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback; /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK) + if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK) { /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */ hirda->hdmatx->XferAbortCallback(hirda->hdmatx); @@ -1313,25 +1658,37 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) else { /* Reset Tx transfer counter */ - hirda->TxXferCount = 0; + hirda->TxXferCount = 0U; /* Restore hirda->gState to Ready */ hirda->gState = HAL_IRDA_STATE_READY; /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hirda->AbortTransmitCpltCallback(hirda); +#else + /* Call legacy weak Abort Transmit Complete Callback */ HAL_IRDA_AbortTransmitCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } } else { /* Reset Tx transfer counter */ - hirda->TxXferCount = 0; + hirda->TxXferCount = 0U; /* Restore hirda->gState to Ready */ hirda->gState = HAL_IRDA_STATE_READY; /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hirda->AbortTransmitCpltCallback(hirda); +#else + /* Call legacy weak Abort Transmit Complete Callback */ HAL_IRDA_AbortTransmitCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } return HAL_OK; @@ -1341,7 +1698,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) * @brief Abort ongoing Receive transfer (Interrupt mode). * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable IRDA Interrupts (Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1368,14 +1725,14 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */ - if(hirda->hdmarx != NULL) + if (hirda->hdmarx != NULL) { - /* Set the IRDA DMA Abort callback : + /* Set the IRDA DMA Abort callback : will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback; /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) { /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */ hirda->hdmarx->XferAbortCallback(hirda->hdmarx); @@ -1384,7 +1741,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) else { /* Reset Rx transfer counter */ - hirda->RxXferCount = 0; + hirda->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); @@ -1393,13 +1750,19 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) hirda->RxState = HAL_IRDA_STATE_READY; /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hirda->AbortReceiveCpltCallback(hirda); +#else + /* Call legacy weak Abort Receive Complete Callback */ HAL_IRDA_AbortReceiveCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } } else { /* Reset Rx transfer counter */ - hirda->RxXferCount = 0; + hirda->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); @@ -1408,7 +1771,13 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) hirda->RxState = HAL_IRDA_STATE_READY; /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hirda->AbortReceiveCpltCallback(hirda); +#else + /* Call legacy weak Abort Receive Complete Callback */ HAL_IRDA_AbortReceiveCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } return HAL_OK; @@ -1416,7 +1785,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) /** * @brief Handle IRDA interrupt request. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -1433,28 +1802,28 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) { /* IRDA in mode Receiver ---------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET)) + if (((isrflags & USART_ISR_RXNE_RXFNE) != RESET) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET)) #else - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + if (((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) #endif { IRDA_Receive_IT(hirda); return; } - } + } /* If some errors occur */ cr3its = READ_REG(hirda->Instance->CR3); - if( (errorflags != RESET) - && ( ((cr3its & USART_CR3_EIE) != RESET) + if ((errorflags != RESET) + && (((cr3its & USART_CR3_EIE) != RESET) #if defined(USART_CR1_FIFOEN) - || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET)) ) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET))) #else - || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) ) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) #endif { /* IRDA parity error interrupt occurred -------------------------------------*/ - if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + if (((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) { __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF); @@ -1462,7 +1831,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) } /* IRDA frame error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF); @@ -1470,7 +1839,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) } /* IRDA noise error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF); @@ -1478,11 +1847,11 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) } /* IRDA Over-Run interrupt occurred -----------------------------------------*/ - if(((isrflags & USART_ISR_ORE) != RESET) && + if (((isrflags & USART_ISR_ORE) != RESET) && #if defined(USART_CR1_FIFOEN) - (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) + (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) #else - (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) + (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) #endif { __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF); @@ -1491,13 +1860,13 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) } /* Call IRDA Error Call back function if need be --------------------------*/ - if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE) + if (hirda->ErrorCode != HAL_IRDA_ERROR_NONE) { /* IRDA in mode Receiver ---------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET)) + if (((isrflags & USART_ISR_RXNE_RXFNE) != RESET) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET)) #else - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + if (((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) #endif { IRDA_Receive_IT(hirda); @@ -1507,7 +1876,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) consider error as blocking */ if (((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) || (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))) - { + { /* Blocking error : transfer is aborted Set the IRDA state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ @@ -1519,14 +1888,14 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); /* Abort the IRDA DMA Rx channel */ - if(hirda->hdmarx != NULL) + if (hirda->hdmarx != NULL) { - /* Set the IRDA DMA Abort callback : + /* Set the IRDA DMA Abort callback : will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */ hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError; /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) { /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */ hirda->hdmarx->XferAbortCallback(hirda->hdmarx); @@ -1534,21 +1903,37 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) } else { - /* Call user error callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hirda->ErrorCallback(hirda); +#else + /* Call legacy weak user error callback */ HAL_IRDA_ErrorCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } } else { - /* Call user error callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hirda->ErrorCallback(hirda); +#else + /* Call legacy weak user error callback */ HAL_IRDA_ErrorCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } } else { - /* Non Blocking error : transfer could go on. + /* Non Blocking error : transfer could go on. Error is notified to user through user error callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hirda->ErrorCallback(hirda); +#else + /* Call legacy weak user error callback */ HAL_IRDA_ErrorCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ hirda->ErrorCode = HAL_IRDA_ERROR_NONE; } } @@ -1558,9 +1943,9 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) /* IRDA in mode Transmitter ------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_TXE_TXFNF) != RESET) && ((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET)) + if (((isrflags & USART_ISR_TXE_TXFNF) != RESET) && ((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET)) #else - if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) + if (((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) #endif { IRDA_Transmit_IT(hirda); @@ -1568,7 +1953,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) } /* IRDA in mode Transmitter (transmission end) -----------------------------*/ - if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) + if (((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) { IRDA_EndTransmit_IT(hirda); return; @@ -1627,7 +2012,7 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) /** * @brief Rx Half Transfer complete callback. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. + * the configuration information for the specified IRDA module. * @retval None */ __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda) @@ -1662,7 +2047,7 @@ __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA module. * @retval None */ -__weak void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda) +__weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda) { /* Prevent unused argument(s) compilation warning */ UNUSED(hirda); @@ -1678,7 +2063,7 @@ __weak void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA module. * @retval None */ -__weak void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda) +__weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda) { /* Prevent unused argument(s) compilation warning */ UNUSED(hirda); @@ -1694,7 +2079,7 @@ __weak void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA module. * @retval None */ -__weak void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda) +__weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda) { /* Prevent unused argument(s) compilation warning */ UNUSED(hirda); @@ -1736,7 +2121,7 @@ __weak void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda) HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) { /* Return IRDA handle state */ - uint32_t temp1= 0x00, temp2 = 0x00; + uint32_t temp1 = 0x00U, temp2 = 0x00U; temp1 = hirda->gState; temp2 = hirda->RxState; @@ -1766,6 +2151,27 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) * @{ */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +/** + * @brief Initialize the callbacks to their default values. + * @param hirda IRDA handle. + * @retval none + */ +void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda) +{ + /* Init the IRDA Callback settings */ + hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */ + hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + +} +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + /** * @brief Configure the IRDA peripheral. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains @@ -1774,7 +2180,7 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) */ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) { - uint32_t tmpreg = 0x00000000; + uint32_t tmpreg = 0x00000000U; IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED; HAL_StatusTypeDef ret = HAL_OK; @@ -1813,7 +2219,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) /*-------------------------- USART BRR Configuration -----------------------*/ IRDA_GETCLOCKSOURCE(hirda, clocksource); - tmpreg = 0; + tmpreg = 0U; switch (clocksource) { case IRDA_CLOCKSOURCE_PCLK1: @@ -1878,7 +2284,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) */ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Initialize the IRDA ErrorCode */ hirda->ErrorCode = HAL_IRDA_ERROR_NONE; @@ -1887,20 +2293,20 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) tickstart = HAL_GetTick(); /* Check if the Transmitter is enabled */ - if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + if ((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) { /* Wait until TEACK flag is set */ - if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) + if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; } } /* Check if the Receiver is enabled */ - if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + if ((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) { /* Wait until REACK flag is set */ - if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) + if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; @@ -1930,12 +2336,12 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ - while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status) + while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ #if defined(USART_CR1_FIFOEN) @@ -2007,12 +2413,12 @@ static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda) */ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); /* DMA Normal mode */ - if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) + if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { - hirda->TxXferCount = 0; + hirda->TxXferCount = 0U; /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the IRDA CR3 register */ @@ -2024,7 +2430,13 @@ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* DMA Circular mode */ else { +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Tx complete callback */ + hirda->TxCpltCallback(hirda); +#else + /* Call legacy weak Tx complete callback */ HAL_IRDA_TxCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } } @@ -2037,9 +2449,15 @@ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Tx Half complete callback */ + hirda->TxHalfCpltCallback(hirda); +#else + /* Call legacy weak Tx complete callback */ HAL_IRDA_TxHalfCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } /** @@ -2050,12 +2468,12 @@ static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) */ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); /* DMA Normal mode */ - if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) + if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { - hirda->RxXferCount = 0; + hirda->RxXferCount = 0U; /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); @@ -2069,7 +2487,13 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) hirda->RxState = HAL_IRDA_STATE_READY; } +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hirda->RxCpltCallback(hirda); +#else + /* Call legacy weak Rx complete callback */ HAL_IRDA_RxCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ } /** @@ -2080,9 +2504,15 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + hirda->RxHalfCpltCallback(hirda); +#else + /* Call legacy weak Rx Half complete callback */ HAL_IRDA_RxHalfCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } /** @@ -2093,26 +2523,32 @@ static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma) */ static void IRDA_DMAError(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); /* Stop IRDA DMA Tx request if ongoing */ - if ( (hirda->gState == HAL_IRDA_STATE_BUSY_TX) - &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) ) + if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) + && (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))) { - hirda->TxXferCount = 0; + hirda->TxXferCount = 0U; IRDA_EndTxTransfer(hirda); } /* Stop IRDA DMA Rx request if ongoing */ - if ( (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) - &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) ) + if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) + && (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))) { - hirda->RxXferCount = 0; + hirda->RxXferCount = 0U; IRDA_EndRxTransfer(hirda); } hirda->ErrorCode |= HAL_IRDA_ERROR_DMA; +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hirda->ErrorCallback(hirda); +#else + /* Call legacy weak user error callback */ HAL_IRDA_ErrorCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } /** @@ -2123,11 +2559,17 @@ static void IRDA_DMAError(DMA_HandleTypeDef *hdma) */ static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); - hirda->RxXferCount = 0; - hirda->TxXferCount = 0; + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + hirda->RxXferCount = 0U; + hirda->TxXferCount = 0U; +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hirda->ErrorCallback(hirda); +#else + /* Call legacy weak user error callback */ HAL_IRDA_ErrorCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } /** @@ -2140,22 +2582,22 @@ static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma) */ static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent); - + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + hirda->hdmatx->XferAbortCallback = NULL; /* Check if an Abort process is still ongoing */ - if(hirda->hdmarx != NULL) + if (hirda->hdmarx != NULL) { - if(hirda->hdmarx->XferAbortCallback != NULL) + if (hirda->hdmarx->XferAbortCallback != NULL) { return; } } - + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - hirda->TxXferCount = 0; - hirda->RxXferCount = 0; + hirda->TxXferCount = 0U; + hirda->RxXferCount = 0U; /* Reset errorCode */ hirda->ErrorCode = HAL_IRDA_ERROR_NONE; @@ -2168,7 +2610,13 @@ static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma) hirda->RxState = HAL_IRDA_STATE_READY; /* Call user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hirda->AbortCpltCallback(hirda); +#else + /* Call legacy weak Abort complete callback */ HAL_IRDA_AbortCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } @@ -2182,22 +2630,22 @@ static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma) */ static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent); - + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + hirda->hdmarx->XferAbortCallback = NULL; /* Check if an Abort process is still ongoing */ - if(hirda->hdmatx != NULL) + if (hirda->hdmatx != NULL) { - if(hirda->hdmatx->XferAbortCallback != NULL) + if (hirda->hdmatx->XferAbortCallback != NULL) { return; } } - + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - hirda->TxXferCount = 0; - hirda->RxXferCount = 0; + hirda->TxXferCount = 0U; + hirda->RxXferCount = 0U; /* Reset errorCode */ hirda->ErrorCode = HAL_IRDA_ERROR_NONE; @@ -2210,7 +2658,13 @@ static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma) hirda->RxState = HAL_IRDA_STATE_READY; /* Call user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hirda->AbortCpltCallback(hirda); +#else + /* Call legacy weak Abort complete callback */ HAL_IRDA_AbortCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } @@ -2224,15 +2678,21 @@ static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma) */ static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); - hirda->TxXferCount = 0; + hirda->TxXferCount = 0U; /* Restore hirda->gState to Ready */ hirda->gState = HAL_IRDA_STATE_READY; /* Call user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hirda->AbortTransmitCpltCallback(hirda); +#else + /* Call legacy weak Abort Transmit Complete Callback */ HAL_IRDA_AbortTransmitCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } /** @@ -2245,9 +2705,9 @@ static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) */ static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - hirda->RxXferCount = 0; + hirda->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); @@ -2256,7 +2716,13 @@ static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) hirda->RxState = HAL_IRDA_STATE_READY; /* Call user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hirda->AbortReceiveCpltCallback(hirda); +#else + /* Call legacy weak Abort Receive Complete Callback */ HAL_IRDA_AbortReceiveCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } /** @@ -2269,12 +2735,12 @@ static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) */ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) { - uint16_t* tmp; + uint16_t *tmp; /* Check that a Tx process is ongoing */ - if(hirda->gState == HAL_IRDA_STATE_BUSY_TX) + if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) { - if(hirda->TxXferCount == 0) + if (hirda->TxXferCount == 0U) { /* Disable the IRDA Transmit Data Register Empty Interrupt */ #if defined(USART_CR1_FIFOEN) @@ -2292,9 +2758,9 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) { if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) { - tmp = (uint16_t*) hirda->pTxBuffPtr; + tmp = (uint16_t *) hirda->pTxBuffPtr; hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF); - hirda->pTxBuffPtr += 2; + hirda->pTxBuffPtr += 2U; } else { @@ -2325,7 +2791,13 @@ static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) /* Tx process is ended, restore hirda->gState to Ready */ hirda->gState = HAL_IRDA_STATE_READY; +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Tx complete callback */ + hirda->TxCpltCallback(hirda); +#else + /* Call legacy weak Tx complete callback */ HAL_IRDA_TxCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } /** @@ -2338,7 +2810,7 @@ static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) */ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) { - uint16_t* tmp; + uint16_t *tmp; uint16_t uhMask = hirda->Mask; uint16_t uhdata; @@ -2348,16 +2820,16 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) uhdata = (uint16_t) READ_REG(hirda->Instance->RDR); if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) { - tmp = (uint16_t*) hirda->pRxBuffPtr ; + tmp = (uint16_t *) hirda->pRxBuffPtr ; *tmp = (uint16_t)(uhdata & uhMask); - hirda->pRxBuffPtr +=2; + hirda->pRxBuffPtr += 2U; } else { *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); } - if(--hirda->RxXferCount == 0) + if (--hirda->RxXferCount == 0U) { /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */ #if defined(USART_CR1_FIFOEN) @@ -2372,7 +2844,13 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) /* Rx process is completed, restore hirda->RxState to Ready */ hirda->RxState = HAL_IRDA_STATE_READY; +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hirda->RxCpltCallback(hirda); +#else + /* Call legacy weak Rx complete callback */ HAL_IRDA_RxCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ return HAL_OK; } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c index 79fdc475a2..bac17d5edb 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c @@ -2,15 +2,15 @@ ****************************************************************************** * @file stm32l4xx_hal_lptim.c * @author MCD Application Team - * @brief LPTIM HAL module driver. - * This file provides firmware functions to manage the following + * @brief LPTIM HAL module driver. + * This file provides firmware functions to manage the following * functionalities of the Low Power Timer (LPTIM) peripheral: * + Initialization and de-initialization functions. * + Start/Stop operation functions in polling mode. * + Start/Stop operation functions in interrupt mode. * + Reading operation functions. * + Peripheral State functions. - * + * @verbatim ============================================================================== ##### How to use this driver ##### @@ -25,7 +25,7 @@ (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority(). (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ(). (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler(). - + (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function configures mainly: (++) The instance: LPTIM1 or LPTIM2. @@ -38,7 +38,7 @@ (+++) Polarity: polarity of the active edge for the counter unit if the ULPTIM input is selected. (+++) SampleTime: clock sampling time to configure the clock glitch - filter. + filter. (++) Trigger: How the counter start. (+++) Source: trigger can be software or one of the hardware triggers. (+++) ActiveEdge : only for hardware trigger. @@ -47,49 +47,95 @@ (++) OutputPolarity : 2 opposite polarities are possible. (++) UpdateMode: specifies whether the update of the autoreload and the compare values is done immediately or after the end of current - period. + period. (++) Input1Source: Source selected for input1 (GPIO or comparator output). - (++) Input2Source: Source selected for input2 (GPIO or comparator output). + (++) Input2Source: Source selected for input2 (GPIO or comparator output). Input2 is used only for encoder feature so is used only for LPTIM1 instance. - + (#)Six modes are available: - + (++) PWM Mode: To generate a PWM signal with specified period and pulse, call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption mode. - + (++) One Pulse Mode: To generate pulse with specified width in response to a stimulus, call HAL_LPTIM_OnePulse_Start() or HAL_LPTIM_OnePulse_Start_IT() for interruption mode. - + (++) Set once Mode: In this mode, the output changes the level (from low level to high level if the output polarity is configured high, else - the opposite) when a compare match occurs. To start this mode, call + the opposite) when a compare match occurs. To start this mode, call HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for interruption mode. - + (++) Encoder Mode: To use the encoder interface call - HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for + HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for interruption mode. Only available for LPTIM1 instance. - + (++) Time out Mode: an active edge on one selected trigger input rests the counter. The first trigger event will start the timer, any successive trigger event will reset the counter and the timer will - restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or + restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or HAL_LPTIM_TimeOut_Start_IT() for interruption mode. - + (++) Counter Mode: counter can be used to count external events on the LPTIM Input1 or it can be used to count internal clock cycles. - To start this mode, call HAL_LPTIM_Counter_Start() or - HAL_LPTIM_Counter_Start_IT() for interruption mode. + To start this mode, call HAL_LPTIM_Counter_Start() or + HAL_LPTIM_Counter_Start_IT() for interruption mode. + - (#) User can stop any process by calling the corresponding API: HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is already started in interruption mode. - + (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit(). + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback. + @ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the + default weak function. + @ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + These functions allow to register/unregister following callbacks: + + (+) MspInitCallback : LPTIM Base Msp Init Callback. + (+) MspDeInitCallback : LPTIM Base Msp DeInit Callback. + (+) CompareMatchCallback : Compare match Callback. + (+) AutoReloadMatchCallback : Auto-reload match Callback. + (+) TriggerCallback : External trigger event detection Callback. + (+) CompareWriteCallback : Compare register write complete Callback. + (+) AutoReloadWriteCallback : Auto-reload register write complete Callback. + (+) DirectionUpCallback : Up-counting direction change Callback. + (+) DirectionDownCallback : Down-counting direction change Callback. + + By default, after the Init and when the state is HAL_LPTIM_STATE_RESET + all interrupt callbacks are set to the corresponding weak functions: + examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback(). + + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init/DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function. + + When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. @endverbatim ****************************************************************************** * @attention @@ -118,8 +164,8 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -139,16 +185,20 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + /* Exported functions --------------------------------------------------------*/ /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions * @{ */ -/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions. +/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions. * -@verbatim +@verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== @@ -157,8 +207,8 @@ LPTIM_InitTypeDef and initialize the associated handle. (+) DeInitialize the LPTIM peripheral. (+) Initialize the LPTIM MSP. - (+) DeInitialize the LPTIM MSP. - + (+) DeInitialize the LPTIM MSP. + @endverbatim * @{ */ @@ -181,39 +231,52 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source)); - assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); + assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) { assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); - } + } assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source)); if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge)); - } - assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); + } + assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource)); - + if(hlptim->State == HAL_LPTIM_STATE_RESET) { /* Allocate lock resource and initialize it */ hlptim->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + LPTIM_ResetCallback(hlptim); + + if (hlptim->MspInitCallback == NULL) + { + hlptim->MspInitCallback = HAL_LPTIM_MspInit; + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + hlptim->MspInitCallback(hlptim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_LPTIM_MspInit(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } - + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; - + /* Get the LPTIMx CFGR value */ tmpcfgr = hlptim->Instance->CFGR; - + if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) { tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); @@ -222,24 +285,24 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) { tmpcfgr &= (uint32_t)(~ (LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL)); } - + /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE )); - + /* Set initialization parameters */ tmpcfgr |= (hlptim->Init.Clock.Source | hlptim->Init.Clock.Prescaler | hlptim->Init.OutputPolarity | hlptim->Init.UpdateMode | hlptim->Init.CounterSource); - + if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) { tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | hlptim->Init.UltraLowPowerClock.SampleTime); - } - + } + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable External trigger and set the trigger source */ @@ -247,7 +310,7 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) hlptim->Init.Trigger.ActiveEdge | hlptim->Init.Trigger.SampleTime); } - + /* Write to LPTIMx CFGR */ hlptim->Instance->CFGR = tmpcfgr; @@ -257,7 +320,7 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) /* Check LPTIM1 Input1 and Input2 sources */ assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance,hlptim->Init.Input1Source)); assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance,hlptim->Init.Input2Source)); - + /* Configure LPTIM1 Input1 and Input2 sources */ hlptim->Instance->OR = (hlptim->Init.Input1Source | hlptim->Init.Input2Source); } @@ -265,20 +328,20 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) { /* Check LPTIM2 Input1 source */ assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance,hlptim->Init.Input1Source)); - + /* Configure LPTIM2 Input1 source */ hlptim->Instance->OR = hlptim->Init.Input1Source; } - + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } /** - * @brief DeInitialize the LPTIM peripheral. + * @brief DeInitialize the LPTIM peripheral. * @param hlptim: LPTIM handle * @retval HAL status */ @@ -289,22 +352,32 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim) { return HAL_ERROR; } - + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; - + /* Disable the LPTIM Peripheral Clock */ __HAL_LPTIM_DISABLE(hlptim); - + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + if (hlptim->MspDeInitCallback == NULL) + { + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; + } + + /* DeInit the low level hardware: CLOCK, NVIC.*/ + hlptim->MspDeInitCallback(hlptim); +#else /* DeInit the low level hardware: CLOCK, NVIC.*/ HAL_LPTIM_MspDeInit(hlptim); - +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_RESET; - + /* Release Lock */ __HAL_UNLOCK(hlptim); - + /* Return function status */ return HAL_OK; } @@ -343,13 +416,13 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) * @} */ -/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions - * @brief Start-Stop operation functions. +/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions + * @brief Start-Stop operation functions. * -@verbatim +@verbatim ============================================================================== ##### LPTIM Start Stop operation functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: (+) Start the PWM mode. (+) Stop the PWM mode. @@ -360,15 +433,15 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) (+) Start the Encoder mode. (+) Stop the Encoder mode. (+) Start the Timeout mode. - (+) Stop the Timeout mode. + (+) Stop the Timeout mode. (+) Start the Counter mode. (+) Stop the Counter mode. - + @endverbatim * @{ */ - + /** * @brief Start the LPTIM PWM generation. * @param hlptim : LPTIM handle @@ -384,28 +457,28 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Peri assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_PERIOD(Period)); assert_param(IS_LPTIM_PULSE(Pulse)); - + /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; - + /* Reset WAVE bit to set PWM mode */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; - + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - + /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -419,16 +492,16 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -448,47 +521,47 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_PERIOD(Period)); assert_param(IS_LPTIM_PULSE(Pulse)); - + /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; - + /* Reset WAVE bit to set PWM mode */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; - + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); - + /* Enable Compare write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK); - + /* Enable Autoreload match interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); - + /* Enable Compare match interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); - + /* If external trigger source is used, then enable external trigger interrupt */ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable external trigger interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); - } - + } + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - + /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -502,35 +575,35 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - + /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); - + /* Disable Compare write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK); - + /* Disable Autoreload match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - + /* Disable Compare match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); - + /* If external trigger source is used, then disable external trigger interrupt */ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Disable external trigger interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); - } + } /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -550,28 +623,28 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_PERIOD(Period)); assert_param(IS_LPTIM_PULSE(Pulse)); - + /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; - + /* Reset WAVE bit to set one pulse mode */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; - + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - + /* Start timer in continuous mode */ __HAL_LPTIM_START_SINGLE(hlptim); - + /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -585,16 +658,16 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -614,47 +687,47 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_PERIOD(Period)); assert_param(IS_LPTIM_PULSE(Pulse)); - + /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; - + /* Reset WAVE bit to set one pulse mode */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; - + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); - + /* Enable Compare write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK); - + /* Enable Autoreload match interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); - + /* Enable Compare match interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); - + /* If external trigger source is used, then enable external trigger interrupt */ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable external trigger interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } - + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - + /* Start timer in continuous mode */ __HAL_LPTIM_START_SINGLE(hlptim); - + /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -668,35 +741,35 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - + /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); - + /* Disable Compare write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK); - + /* Disable Autoreload match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - + /* Disable Compare match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); - + /* If external trigger source is used, then disable external trigger interrupt */ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Disable external trigger interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } - + /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -716,28 +789,28 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_PERIOD(Period)); assert_param(IS_LPTIM_PULSE(Pulse)); - + /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; - + /* Set WAVE bit to enable the set once mode */ hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; - + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - + /* Start timer in continuous mode */ __HAL_LPTIM_START_SINGLE(hlptim); - + /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -751,16 +824,16 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -780,47 +853,47 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_PERIOD(Period)); assert_param(IS_LPTIM_PULSE(Pulse)); - + /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; - + /* Set WAVE bit to enable the set once mode */ hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; - + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); - + /* Enable Compare write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK); - + /* Enable Autoreload match interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); - + /* Enable Compare match interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); - + /* If external trigger source is used, then enable external trigger interrupt */ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable external trigger interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); - } - + } + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - + /* Start timer in continuous mode */ __HAL_LPTIM_START_SINGLE(hlptim); - + /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -834,35 +907,35 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); - + /* Disable Compare write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK); - + /* Disable Autoreload match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - + /* Disable Compare match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); - + /* If external trigger source is used, then disable external trigger interrupt */ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Disable external trigger interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); - } - + } + /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -937,19 +1010,19 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - + /* Reset ENC bit to disable the encoder interface */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; - + /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -999,7 +1072,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN); /* Enable "switch to up direction" interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP); + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP); /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); @@ -1031,25 +1104,25 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - + /* Reset ENC bit to disable the encoder interface */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; - + /* Disable "switch to down direction" interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN); - + /* Disable "switch to up direction" interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP); - + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP); + /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -1071,28 +1144,28 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_PERIOD(Period)); assert_param(IS_LPTIM_PULSE(Timeout)); - + /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; - + /* Set TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; - + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - + /* Load the Timeout value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Timeout); - + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - + /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -1106,19 +1179,19 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - + /* Reset TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; - + /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -1140,31 +1213,31 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_PERIOD(Period)); assert_param(IS_LPTIM_PULSE(Timeout)); - + /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; - + /* Set TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; - + /* Enable Compare match interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); - + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - + /* Load the Timeout value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Timeout); - + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - + /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -1178,22 +1251,22 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - + /* Reset TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; - + /* Disable Compare match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); - + /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -1210,10 +1283,10 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_PERIOD(Period)); - + /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; - + /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { @@ -1225,16 +1298,16 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - + /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -1248,16 +1321,16 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - + /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -1274,10 +1347,10 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_PERIOD(Period)); - + /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; - + /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { @@ -1286,25 +1359,25 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Set clock prescaler to 0 */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC; } - + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); - + /* Enable Autoreload match interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); - + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - + /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -1318,22 +1391,22 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - + /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); - + /* Disable Autoreload match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - + /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -1342,13 +1415,13 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @} */ -/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions +/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions * @brief Read operation functions. * -@verbatim +@verbatim ============================================================================== ##### LPTIM Read operation functions ##### - ============================================================================== + ============================================================================== [..] This section provides LPTIM Reading functions. (+) Read the counter value. (+) Read the period (Auto-reload) value. @@ -1366,7 +1439,7 @@ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + return (hlptim->Instance->CNT); } @@ -1379,7 +1452,7 @@ uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + return (hlptim->Instance->ARR); } @@ -1392,7 +1465,7 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + return (hlptim->Instance->CMP); } @@ -1405,11 +1478,11 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) /** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks * @brief LPTIM IRQ handler. * -@verbatim +@verbatim ============================================================================== ##### LPTIM IRQ handler and callbacks ##### - ============================================================================== -[..] This section provides LPTIM IRQ handler and callback functions called within + ============================================================================== +[..] This section provides LPTIM IRQ handler and callback functions called within the IRQ handler. @endverbatim @@ -1430,12 +1503,16 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) { /* Clear Compare match flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM); - + /* Compare match Callback */ - HAL_LPTIM_CompareMatchCallback(hlptim); +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->CompareMatchCallback(hlptim); +#else + HAL_LPTIM_CompareMatchCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } } - + /* Autoreload match interrupt */ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET) { @@ -1443,12 +1520,16 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) { /* Clear Autoreload match flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM); - + /* Autoreload match Callback */ - HAL_LPTIM_AutoReloadMatchCallback(hlptim); +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->AutoReloadMatchCallback(hlptim); +#else + HAL_LPTIM_AutoReloadMatchCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } } - + /* Trigger detected interrupt */ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET) { @@ -1456,12 +1537,16 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) { /* Clear Trigger detected flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG); - + /* Trigger detected callback */ - HAL_LPTIM_TriggerCallback(hlptim); +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->TriggerCallback(hlptim); +#else + HAL_LPTIM_TriggerCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } } - + /* Compare write interrupt */ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET) { @@ -1469,12 +1554,16 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) { /* Clear Compare write flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); - + /* Compare write Callback */ - HAL_LPTIM_CompareWriteCallback(hlptim); +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->CompareWriteCallback(hlptim); +#else + HAL_LPTIM_CompareWriteCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } } - + /* Autoreload write interrupt */ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET) { @@ -1482,12 +1571,16 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) { /* Clear Autoreload write flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); - + /* Autoreload write Callback */ - HAL_LPTIM_AutoReloadWriteCallback(hlptim); +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->AutoReloadWriteCallback(hlptim); +#else + HAL_LPTIM_AutoReloadWriteCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } } - + /* Direction counter changed from Down to Up interrupt */ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET) { @@ -1495,12 +1588,16 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) { /* Clear Direction counter changed from Down to Up flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP); - + /* Direction counter changed from Down to Up Callback */ - HAL_LPTIM_DirectionUpCallback(hlptim); +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->DirectionUpCallback(hlptim); +#else + HAL_LPTIM_DirectionUpCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } } - + /* Direction counter changed from Up to Down interrupt */ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET) { @@ -1508,9 +1605,13 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) { /* Clear Direction counter changed from Up to Down flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN); - + /* Direction counter changed from Up to Down Callback */ - HAL_LPTIM_DirectionDownCallback(hlptim); +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->DirectionDownCallback(hlptim); +#else + HAL_LPTIM_DirectionDownCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } } } @@ -1527,7 +1628,7 @@ __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim) /* NOTE : This function should not be modified, when the callback is needed, the HAL_LPTIM_CompareMatchCallback could be implemented in the user file - */ + */ } /** @@ -1542,7 +1643,7 @@ __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim) /* NOTE : This function should not be modified, when the callback is needed, the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file - */ + */ } /** @@ -1557,7 +1658,7 @@ __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim) /* NOTE : This function should not be modified, when the callback is needed, the HAL_LPTIM_TriggerCallback could be implemented in the user file - */ + */ } /** @@ -1572,11 +1673,11 @@ __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim) /* NOTE : This function should not be modified, when the callback is needed, the HAL_LPTIM_CompareWriteCallback could be implemented in the user file - */ + */ } /** - * @brief Autoreload write callback in non-blocking mode. + * @brief Autoreload write callback in non-blocking mode. * @param hlptim : LPTIM handle * @retval None */ @@ -1587,7 +1688,7 @@ __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim) /* NOTE : This function should not be modified, when the callback is needed, the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file - */ + */ } /** @@ -1602,7 +1703,7 @@ __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim) /* NOTE : This function should not be modified, when the callback is needed, the HAL_LPTIM_DirectionUpCallback could be implemented in the user file - */ + */ } /** @@ -1617,20 +1718,230 @@ __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim) /* NOTE : This function should not be modified, when the callback is needed, the HAL_LPTIM_DirectionDownCallback could be implemented in the user file - */ + */ +} + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User LPTIM callback to be used instead of the weak predefined callback + * @param hlptim LPTIM handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID + * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID + * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID + * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID + * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID + * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID + * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID + * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID + * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, + HAL_LPTIM_CallbackIDTypeDef CallbackID, + pLPTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hlptim); + + if (hlptim->State == HAL_LPTIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_LPTIM_MSPINIT_CB_ID : + hlptim->MspInitCallback = pCallback; + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + hlptim->MspDeInitCallback = pCallback; + break; + + case HAL_LPTIM_COMPARE_MATCH_CB_ID : + hlptim->CompareMatchCallback = pCallback; + break; + + case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : + hlptim->AutoReloadMatchCallback = pCallback; + break; + + case HAL_LPTIM_TRIGGER_CB_ID : + hlptim->TriggerCallback = pCallback; + break; + + case HAL_LPTIM_COMPARE_WRITE_CB_ID : + hlptim->CompareWriteCallback = pCallback; + break; + + case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : + hlptim->AutoReloadWriteCallback = pCallback; + break; + + case HAL_LPTIM_DIRECTION_UP_CB_ID : + hlptim->DirectionUpCallback = pCallback; + break; + + case HAL_LPTIM_DIRECTION_DOWN_CB_ID : + hlptim->DirectionDownCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hlptim->State == HAL_LPTIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_LPTIM_MSPINIT_CB_ID : + hlptim->MspInitCallback = pCallback; + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + hlptim->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hlptim); + + return status; } +/** + * @brief Unregister a LPTIM callback + * LLPTIM callback is redirected to the weak predefined callback + * @param hlptim LPTIM handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID + * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID + * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID + * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID + * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID + * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID + * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID + * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID + * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, + HAL_LPTIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hlptim); + + if (hlptim->State == HAL_LPTIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_LPTIM_MSPINIT_CB_ID : + hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */ + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */ + break; + + case HAL_LPTIM_COMPARE_MATCH_CB_ID : + hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Legacy weak IC Msp Init Callback */ + break; + + case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : + hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Legacy weak IC Msp DeInit Callback */ + break; + + case HAL_LPTIM_TRIGGER_CB_ID : + hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* Legacy weak OC Msp Init Callback */ + break; + + case HAL_LPTIM_COMPARE_WRITE_CB_ID : + hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Legacy weak OC Msp DeInit Callback */ + break; + + case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : + hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Legacy weak PWM Msp Init Callback */ + break; + + case HAL_LPTIM_DIRECTION_UP_CB_ID : + hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Legacy weak PWM Msp DeInit Callback */ + break; + + case HAL_LPTIM_DIRECTION_DOWN_CB_ID : + hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Legacy weak One Pulse Msp Init Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hlptim->State == HAL_LPTIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_LPTIM_MSPINIT_CB_ID : + hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */ + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hlptim); + + return status; +} +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + /** * @} */ -/** @defgroup LPTIM_Exported_Functions_Group5 Peripheral State functions - * @brief Peripheral State functions. +/** @defgroup LPTIM_Exported_Functions_Group5 Peripheral State functions + * @brief Peripheral State functions. * -@verbatim +@verbatim ============================================================================== ##### Peripheral State functions ##### - ============================================================================== + ============================================================================== [..] This subsection permits to get in run-time the status of the peripheral. @@ -1654,6 +1965,35 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim) */ +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup LPTIM_Private_Functions LPTIM Private Functions + * @{ + */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param lptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @retval None + */ +static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim) +{ + /* Reset the LPTIM callback to the legacy weak callbacks */ + lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Compare match Callback */ + lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Auto-reload match Callback */ + lptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* External trigger event detection Callback */ + lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Compare register write complete Callback */ + lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Auto-reload register write complete Callback */ + lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Up-counting direction change Callback */ + lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Down-counting direction change Callback */ +} +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc.c index 372b5345e9..e365143451 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc.c @@ -3,32 +3,32 @@ * @file stm32l4xx_hal_ltdc.c * @author MCD Application Team * @brief LTDC HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the LTDC peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State and Errors functions - * - @verbatim + * + @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] - (#) Program the required configuration through the following parameters: - the LTDC timing, the horizontal and vertical polarity, - the pixel clock polarity, Data Enable polarity and the LTDC background color value + (#) Program the required configuration through the following parameters: + the LTDC timing, the horizontal and vertical polarity, + the pixel clock polarity, Data Enable polarity and the LTDC background color value using HAL_LTDC_Init() function - (#) Program the required configuration through the following parameters: - the pixel format, the blending factors, input alpha value, the window size + (#) Program the required configuration through the following parameters: + the pixel format, the blending factors, input alpha value, the window size and the image size using HAL_LTDC_ConfigLayer() function for foreground - or/and background layer. - - (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and + or/and background layer. + + (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and HAL_LTDC_EnableCLUT functions. - - (#) Optionally, enable the Dither using HAL_LTDC_EnableDither(). + + (#) Optionally, enable the Dither using HAL_LTDC_EnableDither(). (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying() and HAL_LTDC_EnableColorKeying functions. @@ -37,41 +37,94 @@ function (#) If needed, reconfigure and change the pixel format value, the alpha value - value, the window size, the window position and the layer start address - for foreground or/and background layer using respectively the following + value, the window size, the window position and the layer start address + for foreground or/and background layer using respectively the following functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(), HAL_LTDC_SetWindowPosition() and HAL_LTDC_SetAddress(). (#) Variant functions with _NoReload suffix allows to set the LTDC configuration/settings without immediate reload. - This is useful in case when the program requires to modify serval LTDC settings (on one or both layers) + This is useful in case when the program requires to modify serval LTDC settings (on one or both layers) then applying(reload) these settings in one shot by calling the function HAL_LTDC_Reload(). - After calling the _NoReload functions to set different color/format/layer settings, - the program shall call the function HAL_LTDC_Reload() to apply(reload) these settings. - Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_IMMEDIATE if + After calling the _NoReload functions to set different color/format/layer settings, + the program shall call the function HAL_LTDC_Reload() to apply(reload) these settings. + Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_IMMEDIATE if an immediate reload is required. Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_VERTICAL_BLANKING if - the reload should be done in the next vertical blanking period, + the reload should be done in the next vertical blanking period, this option allows to avoid display flicker by applying the new settings during the vertical blanking period. - - (#) To control LTDC state you can use the following function: HAL_LTDC_GetState() + + + (#) To control LTDC state you can use the following function: HAL_LTDC_GetState() *** LTDC HAL driver macros list *** - ============================================= + ============================================= [..] Below the list of most used macros in LTDC HAL driver. - + (+) __HAL_LTDC_ENABLE: Enable the LTDC. (+) __HAL_LTDC_DISABLE: Disable the LTDC. - (+) __HAL_LTDC_LAYER_ENABLE: Enable a LTDC Layer. - (+) __HAL_LTDC_LAYER_DISABLE: Disable a LTDC Layer. + (+) __HAL_LTDC_LAYER_ENABLE: Enable an LTDC Layer. + (+) __HAL_LTDC_LAYER_DISABLE: Disable an LTDC Layer. + (+) __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG: Reload Layer Configuration. + (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags. (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags. - (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts. + (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts. (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts. - - [..] + (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not. + + + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_LTDC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function @ref HAL_LTDC_RegisterCallback() to register a callback. + + Function @ref HAL_LTDC_RegisterCallback() allows to register following callbacks: + (+) LineEventCallback : LTDC Line Event Callback. + (+) ReloadEventCallback : LTDC Reload Event Callback. + (+) ErrorCallback : LTDC Error Callback + (+) MspInitCallback : LTDC MspInit. + (+) MspDeInitCallback : LTDC MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_LTDC_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_LTDC_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) LineEventCallback : LTDC Line Event Callback. + (+) ReloadEventCallback : LTDC Reload Event Callback. + (+) ErrorCallback : LTDC Error Callback + (+) MspInitCallback : LTDC MspInit. + (+) MspDeInitCallback : LTDC MspDeInit. + + By default, after the HAL_LTDC_Init and when the state is HAL_LTDC_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_LTDC_LineEventCallback(), @ref HAL_LTDC_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the HAL_LTDC_Init/ @ref HAL_LTDC_DeInit only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the @ref HAL_LTDC_Init/ @ref HAL_LTDC_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_LTDC_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_LTDC_STATE_READY or HAL_LTDC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_LTDC_RegisterCallback() before calling @ref HAL_LTDC_DeInit + or HAL_LTDC_Init function. + + When The compilation define USE_HAL_LTDC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + [..] (@) You can refer to the LTDC HAL driver header file for more useful macros - + @endverbatim ****************************************************************************** * @attention @@ -101,28 +154,27 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" +#ifdef HAL_LTDC_MODULE_ENABLED +#if defined (LTDC) /** @addtogroup STM32L4xx_HAL_Driver * @{ */ -#if defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - /** @defgroup LTDC LTDC * @brief LTDC HAL module driver * @{ */ -#ifdef HAL_LTDC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); /* Private functions ---------------------------------------------------------*/ @@ -134,18 +186,18 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay /** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and Configuration functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the LTDC - (+) De-initialize the LTDC + (+) De-initialize the LTDC @endverbatim * @{ */ - + /** * @brief Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef. * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains @@ -154,7 +206,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay */ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) { - uint32_t tmp = 0, tmp1 = 0; + uint32_t tmp, tmp1; /* Check the LTDC peripheral state */ if(hltdc == NULL) @@ -177,6 +229,25 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity)); assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity)); +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + if(hltdc->State == HAL_LTDC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hltdc->Lock = HAL_UNLOCKED; + + /* Reset the LTDC callback to the legacy weak callbacks */ + hltdc->LineEventCallback = HAL_LTDC_LineEventCallback; /* Legacy weak LineEventCallback */ + hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback; /* Legacy weak ReloadEventCallback */ + hltdc->ErrorCallback = HAL_LTDC_ErrorCallback; /* Legacy weak ErrorCallback */ + + if(hltdc->MspInitCallback == NULL) + { + hltdc->MspInitCallback = HAL_LTDC_MspInit; + } + /* Init the low level hardware */ + hltdc->MspInitCallback(hltdc); + } +#else if(hltdc->State == HAL_LTDC_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -184,7 +255,8 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) /* Init the low level hardware */ HAL_LTDC_MspInit(hltdc); } - +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + /* Change LTDC peripheral state */ hltdc->State = HAL_LTDC_STATE_BUSY; @@ -195,27 +267,27 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) /* Set Synchronization size */ hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW); - tmp = (hltdc->Init.HorizontalSync << 16); + tmp = (hltdc->Init.HorizontalSync << 16U); hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync); /* Set Accumulated Back porch */ hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP); - tmp = (hltdc->Init.AccumulatedHBP << 16); + tmp = (hltdc->Init.AccumulatedHBP << 16U); hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP); /* Set Accumulated Active Width */ hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW); - tmp = (hltdc->Init.AccumulatedActiveW << 16); + tmp = (hltdc->Init.AccumulatedActiveW << 16U); hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH); /* Set Total Width */ hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW); - tmp = (hltdc->Init.TotalWidth << 16); + tmp = (hltdc->Init.TotalWidth << 16U); hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh); /* Set the background color value */ - tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8); - tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16); + tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U); + tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U); hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED); hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue); @@ -226,7 +298,7 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) __HAL_LTDC_ENABLE(hltdc); /* Initialize the error code */ - hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; + hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; /* Initialize the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; @@ -243,8 +315,17 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc) { +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + if(hltdc->MspDeInitCallback == NULL) + { + hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; + } /* DeInit the low level hardware */ - HAL_LTDC_MspDeInit(hltdc); + hltdc->MspDeInitCallback(hltdc); +#else + /* DeInit the low level hardware */ + HAL_LTDC_MspDeInit(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ /* Initialize the error code */ hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; @@ -268,10 +349,10 @@ __weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hltdc); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_LTDC_MspInit could be implemented in the user file - */ + */ } /** @@ -284,23 +365,205 @@ __weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hltdc); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_LTDC_MspDeInit could be implemented in the user file */ } +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User LTDC Callback + * To be used instead of the weak predefined callback + * @param hltdc ltdc handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID + * @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID + * @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hltdc); + + if(hltdc->State == HAL_LTDC_STATE_READY) + { + switch (CallbackID) + { + case HAL_LTDC_LINE_EVENT_CB_ID : + hltdc->LineEventCallback = pCallback; + break; + + case HAL_LTDC_RELOAD_EVENT_CB_ID : + hltdc->ReloadEventCallback = pCallback; + break; + + case HAL_LTDC_ERROR_CB_ID : + hltdc->ErrorCallback = pCallback; + break; + + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = pCallback; + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if(hltdc->State == HAL_LTDC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = pCallback; + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hltdc); + + return status; +} + +/** + * @brief Unregister an LTDC Callback + * LTDC callabck is redirected to the weak predefined callback + * @param hltdc ltdc handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID + * @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID + * @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hltdc); + + if(hltdc->State == HAL_LTDC_STATE_READY) + { + switch (CallbackID) + { + case HAL_LTDC_LINE_EVENT_CB_ID : + hltdc->LineEventCallback = HAL_LTDC_LineEventCallback; /* Legacy weak LineEventCallback */ + break; + + case HAL_LTDC_RELOAD_EVENT_CB_ID : + hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback; /* Legacy weak ReloadEventCallback */ + break; + + case HAL_LTDC_ERROR_CB_ID : + hltdc->ErrorCallback = HAL_LTDC_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */ + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; /* Legcay weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if(hltdc->State == HAL_LTDC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */ + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; /* Legcay weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hltdc); + + return status; +} +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + /** * @} */ - -/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions + +/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions * @verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] This section provides function allowing to: (+) Handle LTDC interrupt request @@ -310,16 +573,16 @@ __weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) /** * @brief Handle LTDC interrupt request. * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. + * the configuration information for the LTDC. * @retval HAL status */ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc) { uint32_t isrflags = READ_REG(hltdc->Instance->ISR); uint32_t itsources = READ_REG(hltdc->Instance->IER); - + /* Transfer Error Interrupt management ***************************************/ - if(((isrflags & LTDC_ISR_TERRIF) != RESET) && ((itsources & LTDC_IER_TERRIE) != RESET)) + if(((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U)) { /* Disable the transfer Error interrupt */ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE); @@ -337,11 +600,17 @@ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc) __HAL_UNLOCK(hltdc); /* Transfer error Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + hltdc->ErrorCallback(hltdc); +#else + /* Call legacy error callback*/ HAL_LTDC_ErrorCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ } /* FIFO underrun Interrupt management ***************************************/ - if(((isrflags & LTDC_ISR_FUIF) != RESET) && ((itsources & LTDC_IER_FUIE) != RESET)) + if(((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U)) { /* Disable the FIFO underrun interrupt */ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU); @@ -357,18 +626,24 @@ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc) /* Process unlocked */ __HAL_UNLOCK(hltdc); - + /* Transfer error Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + hltdc->ErrorCallback(hltdc); +#else + /* Call legacy error callback*/ HAL_LTDC_ErrorCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ } /* Line Interrupt management ************************************************/ - if(((isrflags & LTDC_ISR_LIF) != RESET) && ((itsources & LTDC_IER_LIE) != RESET)) + if(((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U)) { /* Disable the Line interrupt */ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI); - /* Clear the Line interrupt flag */ + /* Clear the Line interrupt flag */ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI); /* Change LTDC state */ @@ -378,26 +653,38 @@ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc) __HAL_UNLOCK(hltdc); /* Line interrupt Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered Line Event callback */ + hltdc->LineEventCallback(hltdc); +#else + /*Call Legacy Line Event callback */ HAL_LTDC_LineEventCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ } /* Register reload Interrupt management ***************************************/ - if(((isrflags & LTDC_ISR_RRIF) != RESET) && ((itsources & LTDC_IER_RRIE) != RESET)) + if(((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U)) { /* Disable the register reload interrupt */ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR); - + /* Clear the register reload flag */ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR); - + /* Change LTDC state */ hltdc->State = HAL_LTDC_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hltdc); - - /* Register reload interrupt Callback */ + + /* Reload interrupt Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered reload Event callback */ + hltdc->ReloadEventCallback(hltdc); +#else + /*Call Legacy Reload Event callback */ HAL_LTDC_ReloadEventCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ } } @@ -411,7 +698,7 @@ __weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hltdc); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_LTDC_ErrorCallback could be implemented in the user file */ @@ -427,7 +714,7 @@ __weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hltdc); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_LTDC_LineEventCallback could be implemented in the user file */ @@ -443,7 +730,7 @@ __weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hltdc); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_LTDC_ReloadEvenCallback could be implemented in the user file */ @@ -454,12 +741,12 @@ __weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) */ /** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions + * @brief Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Configure the LTDC foreground or/and background parameters. (+) Set the active layer. @@ -469,7 +756,7 @@ __weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) (+) Enable / Disable the C-LUT. (+) Update the layer position. (+) Update the layer size. - (+) Update pixel format on the fly. + (+) Update pixel format on the fly. (+) Update transparency on the fly. (+) Update address on the fly. @@ -490,7 +777,7 @@ __weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) -{ +{ /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); @@ -502,19 +789,19 @@ HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgT assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0)); assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1)); assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); - assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); + assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); /* Process locked */ __HAL_LOCK(hltdc); - + /* Change LTDC peripheral state */ hltdc->State = HAL_LTDC_STATE_BUSY; /* Copy new layer configuration into handle structure */ - hltdc->LayerCfg[LayerIdx] = *pLayerCfg; + hltdc->LayerCfg[LayerIdx] = *pLayerCfg; - /* Configure the LTDC Layer */ + /* Configure the LTDC Layer */ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); /* Set the Immediate Reload type */ @@ -571,7 +858,7 @@ HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @param pCLUT pointer to the color lookup table address. - * @param CLUTSize the color lookup table size. + * @param CLUTSize the color lookup table size. * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) @@ -579,41 +866,40 @@ HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t */ HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx) { - uint32_t tmp = 0; - uint32_t counter = 0; - uint32_t pcounter = 0; - + uint32_t tmp; + uint32_t counter; + uint32_t *pcolorlut = pCLUT; /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_LAYER(LayerIdx)); /* Process locked */ __HAL_LOCK(hltdc); /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; + hltdc->State = HAL_LTDC_STATE_BUSY; - for(counter = 0; (counter < CLUTSize); counter++) + for(counter = 0U; (counter < CLUTSize); counter++) { if(hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44) { - tmp = (((counter + 16*counter) << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000)); + tmp = (((counter + (16U*counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); } else - { - tmp = ((counter << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000)); + { + tmp = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); } - pcounter = (uint32_t)pCLUT + sizeof(*pCLUT); - pCLUT = (uint32_t *)pcounter; + + pcolorlut++; /* Specifies the C-LUT address and RGB value */ LTDC_LAYER(hltdc, LayerIdx)->CLUTWR = tmp; } - + /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; + hltdc->State = HAL_LTDC_STATE_READY; /* Process unlocked */ - __HAL_UNLOCK(hltdc); + __HAL_UNLOCK(hltdc); return HAL_OK; } @@ -628,7 +914,7 @@ HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) -{ +{ /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); @@ -645,14 +931,14 @@ HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t hltdc->Instance->SRCR = LTDC_SRCR_IMR; /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; + hltdc->State = HAL_LTDC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hltdc); - return HAL_OK; + return HAL_OK; } - + /** * @brief Disable the color keying. * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains @@ -680,7 +966,7 @@ HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_ hltdc->Instance->SRCR = LTDC_SRCR_IMR; /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; + hltdc->State = HAL_LTDC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hltdc); @@ -715,7 +1001,7 @@ HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerI hltdc->Instance->SRCR = LTDC_SRCR_IMR; /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; + hltdc->State = HAL_LTDC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hltdc); @@ -729,14 +1015,14 @@ HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerI * the configuration information for the LTDC. * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) { /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); - + /* Process locked */ __HAL_LOCK(hltdc); @@ -750,7 +1036,7 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t Layer hltdc->Instance->SRCR = LTDC_SRCR_IMR; /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; + hltdc->State = HAL_LTDC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hltdc); @@ -777,7 +1063,7 @@ HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc) LTDC->GCR |= (uint32_t)LTDC_GCR_DEN; /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; + hltdc->State = HAL_LTDC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hltdc); @@ -823,7 +1109,7 @@ HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc) * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ -HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) { LTDC_LayerCfgTypeDef *pLayerCfg; @@ -836,7 +1122,7 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSi __HAL_LOCK(hltdc); /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; + hltdc->State = HAL_LTDC_STATE_BUSY; /* Get layer configuration from handle structure */ pLayerCfg = &hltdc->LayerCfg[LayerIdx]; @@ -844,7 +1130,7 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSi /* update horizontal stop */ pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0; - /* update vertical stop */ + /* update vertical stop */ pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0; /* Reconfigures the color frame buffer pitch in byte */ @@ -882,7 +1168,7 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSi HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx) { LTDC_LayerCfgTypeDef *pLayerCfg; - + /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); assert_param(IS_LTDC_CFBLL(X0)); @@ -945,13 +1231,13 @@ HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pi hltdc->State = HAL_LTDC_STATE_BUSY; /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; /* Reconfigure the pixel format */ pLayerCfg->PixelFormat = Pixelformat; /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); /* Set the Immediate Reload type */ hltdc->Instance->SRCR = LTDC_SRCR_IMR; @@ -1055,8 +1341,8 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Addres /** * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is - * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we - * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels + * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we + * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). @@ -1068,63 +1354,63 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Addres */ HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) { - uint32_t tmp = 0; - uint32_t pitchUpdate = 0; - uint32_t pixelFormat = 0; - + uint32_t tmp; + uint32_t pitchUpdate; + uint32_t pixelFormat; + /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); - + /* Process locked */ __HAL_LOCK(hltdc); - + /* Change LTDC peripheral state */ hltdc->State = HAL_LTDC_STATE_BUSY; - + /* get LayerIdx used pixel format */ pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; - + if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) { - tmp = 4; + tmp = 4U; } else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) { - tmp = 3; + tmp = 3U; } else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) { - tmp = 2; + tmp = 2U; } else { - tmp = 1; + tmp = 1U; } - - pitchUpdate = ((LinePitchInPixels * tmp) << 16); - + + pitchUpdate = ((LinePitchInPixels * tmp) << 16U); + /* Clear previously set standard pitch */ LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; - + /* Set the Reload type as immediate update of LTDC pitch configured above */ LTDC->SRCR |= LTDC_SRCR_IMR; - + /* Set new line pitch value */ LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; - + /* Set the Reload type as immediate update of LTDC pitch configured above */ LTDC->SRCR |= LTDC_SRCR_IMR; - + /* Change the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hltdc); - - return HAL_OK; + + return HAL_OK; } /** @@ -1132,7 +1418,7 @@ HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitc * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @param Line Line Interrupt Position. - * @note User application may resort to HAL_LTDC_LineEventCallback() at line interrupt generation. + * @note User application may resort to HAL_LTDC_LineEventCallback() at line interrupt generation. * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line) @@ -1171,7 +1457,7 @@ HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t * @param ReloadType This parameter can be one of the following values : * LTDC_RELOAD_IMMEDIATE : Immediate Reload * LTDC_RELOAD_VERTICAL_BLANKING : Reload in the next Vertical Blanking - * @note User application may resort to HAL_LTDC_ReloadEventCallback() at reload interrupt generation. + * @note User application may resort to HAL_LTDC_ReloadEventCallback() at reload interrupt generation. * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType) @@ -1183,20 +1469,20 @@ HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadTyp __HAL_LOCK(hltdc); /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Enable the Reload interrupt */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable the Reload interrupt */ __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR); - + /* Apply Reload type */ - hltdc->Instance->SRCR = ReloadType; + hltdc->Instance->SRCR = ReloadType; /* Change the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hltdc); - + return HAL_OK; } @@ -1214,7 +1500,7 @@ HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadTyp * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) -{ +{ /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); @@ -1226,23 +1512,21 @@ HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_ assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0)); assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1)); assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); - assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); + assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); /* Process locked */ __HAL_LOCK(hltdc); - + /* Change LTDC peripheral state */ hltdc->State = HAL_LTDC_STATE_BUSY; /* Copy new layer configuration into handle structure */ - hltdc->LayerCfg[LayerIdx] = *pLayerCfg; + hltdc->LayerCfg[LayerIdx] = *pLayerCfg; - /* Configure the LTDC Layer */ + /* Configure the LTDC Layer */ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - /* Do not set the Immediate Reload */ - /* Initialize the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; @@ -1264,7 +1548,7 @@ HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ -HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) { LTDC_LayerCfgTypeDef *pLayerCfg; @@ -1277,7 +1561,7 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uin __HAL_LOCK(hltdc); /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; + hltdc->State = HAL_LTDC_STATE_BUSY; /* Get layer configuration from handle structure */ pLayerCfg = &hltdc->LayerCfg[LayerIdx]; @@ -1285,7 +1569,7 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uin /* update horizontal stop */ pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0; - /* update vertical stop */ + /* update vertical stop */ pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0; /* Reconfigures the color frame buffer pitch in byte */ @@ -1297,8 +1581,6 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uin /* Set LTDC parameters */ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - /* Do not set the Immediate Reload */ - /* Change the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; @@ -1323,7 +1605,7 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uin HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx) { LTDC_LayerCfgTypeDef *pLayerCfg; - + /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); assert_param(IS_LTDC_CFBLL(X0)); @@ -1349,8 +1631,6 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, /* Set LTDC parameters */ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - /* Do not set the Immediate Reload */ - /* Change the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; @@ -1386,15 +1666,13 @@ HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, ui hltdc->State = HAL_LTDC_STATE_BUSY; /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; /* Reconfigure the pixel format */ pLayerCfg->PixelFormat = Pixelformat; /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Do not set the Immediate Reload */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); /* Change the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; @@ -1439,8 +1717,6 @@ HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t /* Set LTDC parameters */ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - /* Do not set the Immediate Reload */ - /* Change the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; @@ -1452,7 +1728,7 @@ HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t /** * @brief Reconfigure the frame buffer Address without reloading. - * Variant of the function HAL_LTDC_SetAddress without immediate reload. + * Variant of the function HAL_LTDC_SetAddress without immediate reload. * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @param Address new address value. @@ -1483,8 +1759,6 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32 /* Set LTDC parameters */ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - /* Do not set the Immediate Reload */ - /* Change the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; @@ -1496,12 +1770,12 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32 /** * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is - * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we - * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels + * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we + * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). - * Variant of the function HAL_LTDC_SetPitch without immediate reload. + * Variant of the function HAL_LTDC_SetPitch without immediate reload. * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'. @@ -1510,59 +1784,57 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32 */ HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) { - uint32_t tmp = 0; - uint32_t pitchUpdate = 0; - uint32_t pixelFormat = 0; - + uint32_t tmp; + uint32_t pitchUpdate; + uint32_t pixelFormat; + /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); - + /* Process locked */ __HAL_LOCK(hltdc); - + /* Change LTDC peripheral state */ hltdc->State = HAL_LTDC_STATE_BUSY; - + /* get LayerIdx used pixel format */ pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; - + if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) { - tmp = 4; + tmp = 4U; } else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) { - tmp = 3; + tmp = 3U; } else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) { - tmp = 2; + tmp = 2U; } else { - tmp = 1; + tmp = 1U; } - - pitchUpdate = ((LinePitchInPixels * tmp) << 16); - + + pitchUpdate = ((LinePitchInPixels * tmp) << 16U); + /* Clear previously set standard pitch */ LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; - + /* Set new line pitch value */ LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; - - /* Do not set the Immediate Reload */ - + /* Change the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hltdc); - - return HAL_OK; + + return HAL_OK; } @@ -1592,8 +1864,6 @@ HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue; - /* Do not set the Immediate Reload */ - /* Change the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; @@ -1614,7 +1884,7 @@ HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) -{ +{ /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); @@ -1627,15 +1897,13 @@ HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, /* Enable LTDC color keying by setting COLKEN bit */ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN; - /* Do not set the Immediate Reload */ - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; + hltdc->State = HAL_LTDC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hltdc); - return HAL_OK; + return HAL_OK; } /** @@ -1662,10 +1930,8 @@ HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc /* Disable LTDC color keying by setting COLKEN bit */ LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; - /* Do not set the Immediate Reload */ - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; + hltdc->State = HAL_LTDC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hltdc); @@ -1697,10 +1963,8 @@ HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32 /* Disable LTDC color lookup table by setting CLUTEN bit */ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN; - /* Do not set the Immediate Reload */ - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; + hltdc->State = HAL_LTDC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hltdc); @@ -1715,14 +1979,14 @@ HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32 * the configuration information for the LTDC. * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) { /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); - + /* Process locked */ __HAL_LOCK(hltdc); @@ -1732,10 +1996,8 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3 /* Disable LTDC color lookup table by setting CLUTEN bit */ LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; - /* Do not set the Immediate Reload */ - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; + hltdc->State = HAL_LTDC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hltdc); @@ -1748,20 +2010,20 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3 */ /** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions + * @brief Peripheral State and Errors functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State and Errors functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides functions allowing to (+) Check the LTDC handle state. - (+) Get the LTDC handle error code. + (+) Get the LTDC handle error code. @endverbatim * @{ - */ + */ /** * @brief Return the LTDC handle state. @@ -1798,7 +2060,7 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc) */ /** - * @brief Configure the LTDC peripheral + * @brief Configure the LTDC peripheral * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @param pLayerCfg Pointer LTDC Layer Configuration structure @@ -1808,30 +2070,30 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc) */ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) { - uint32_t tmp = 0; - uint32_t tmp1 = 0; - uint32_t tmp2 = 0; + uint32_t tmp; + uint32_t tmp1; + uint32_t tmp2; /* Configure the horizontal start and stop position */ - tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16)) << 16); + tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U); LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); - LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16) + 1) | tmp); + LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); /* Configure the vertical start and stop position */ - tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16); + tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U); LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); - LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1) | tmp); + LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp); /* Specifies the pixel format */ LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF); LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat); /* Configure the default color values */ - tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8); - tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16); - tmp2 = (pLayerCfg->Alpha0 << 24); + tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U); + tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U); + tmp2 = (pLayerCfg->Alpha0 << 24U); LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA); - LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); + LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); /* Specifies the constant alpha value */ LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA); @@ -1847,33 +2109,32 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay if(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) { - tmp = 4; + tmp = 4U; } else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888) { - tmp = 3; + tmp = 3U; } else if((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88)) { - tmp = 2; + tmp = 2U; } else { - tmp = 1; + tmp = 1U; } /* Configure the color frame buffer pitch in byte */ LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP); - LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3)); - + LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U)); /* Configure the frame buffer line number */ LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR); LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight); - /* Enable LTDC_Layer by setting LEN bit */ + /* Enable LTDC_Layer by setting LEN bit */ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN; } @@ -1881,16 +2142,17 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay * @} */ -#endif /* HAL_LTDC_MODULE_ENABLED */ /** * @} */ -#endif /* STM32L4R7xx || STM32L4R9xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ +#endif /* LTDC */ +#endif /* HAL_LTDC_MODULE_ENABLED */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc_ex.c index 0f3659390c..efc556e9a9 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc_ex.c @@ -31,7 +31,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -40,7 +40,7 @@ * @{ */ -#if defined (STM32L4R9xx) || defined (STM32L4S9xx) +#if defined (LTDC) && defined (DSI) /** @defgroup LTDCEx LTDCEx * @brief LTDC HAL module driver @@ -63,10 +63,10 @@ /** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and Configuration functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the LTDC @@ -87,28 +87,26 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg) { /* Retrieve signal polarities from DSI */ - - /* The following polarities are inverted: - LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH - LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH - LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ - + + /* The following polarity is inverted: + LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */ + /* Note 1 : Code in line w/ Current LTDC specification */ hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; - hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; - hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; + hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL; + hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL; /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ /* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29; hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29; hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */ - + /* Retrieve vertical timing parameters from DSI */ - hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1; - hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1; - hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1; - hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1; - + hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1U; + hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U; + hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1U; + hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U; + return HAL_OK; } @@ -125,22 +123,22 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg) { /* Retrieve signal polarities from DSI */ - + /* The following polarities are inverted: LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ - + /* Note 1 : Code in line w/ Current LTDC specification */ hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; - + /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ /* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29; hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29; hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */ - + return HAL_OK; } @@ -158,7 +156,7 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD * @} */ -#endif /* STM32L4R9xx || STM32L4S9xx */ +#endif /* LTDC && DSI */ /** * @} diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nand.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nand.c index 873e76343a..52dc8945c0 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nand.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nand.c @@ -3,50 +3,53 @@ * @file stm32l4xx_hal_nand.c * @author MCD Application Team * @brief NAND HAL module driver. - * This file provides a generic firmware to drive NAND memories mounted + * This file provides a generic firmware to drive NAND memories mounted * as external device. - * + * @verbatim ============================================================================== ##### How to use this driver ##### - ============================================================================== + ============================================================================== [..] - This driver is a generic layered driver which contains a set of APIs used to - control NAND flash memories. It uses the FMC layer functions to interface + This driver is a generic layered driver which contains a set of APIs used to + control NAND flash memories. It uses the FMC layer functions to interface with NAND devices. This driver is used as follows: - - (+) NAND flash memory configuration sequence using the function HAL_NAND_Init() + + (+) NAND flash memory configuration sequence using the function HAL_NAND_Init() with control and timing parameters for both common and attribute spaces. - + (+) Read NAND flash memory maker and device IDs using the function - HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef - structure declared by the function caller. - + HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef + structure declared by the function caller. + (+) Access NAND flash memory by read/write operations using the functions - HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea() - to read/write page(s)/spare area(s). These functions use specific device - information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef + HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(), + HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(), + HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(), + HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b() + to read/write page(s)/spare area(s). These functions use specific device + information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef structure. The read/write address information is contained by the Nand_Address_Typedef structure passed as parameter. - + (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset(). - + (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block(). - The erase block address information is contained in the Nand_Address_Typedef + The erase block address information is contained in the Nand_Address_Typedef structure passed as parameter. - + (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status(). - + (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/ HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction - feature or the function HAL_NAND_GetECC() to get the ECC correction code. - + feature or the function HAL_NAND_GetECC() to get the ECC correction code. + (+) You can monitor the NAND device HAL state by calling the function - HAL_NAND_GetState() + HAL_NAND_GetState() [..] (@) This driver is a set of generic APIs which handle standard NAND flash operations. - If a NAND flash device contains different operations and/or implementations, + If a NAND flash device contains different operations and/or implementations, it should be implemented separately. @endverbatim @@ -78,14 +81,12 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(FMC_BANK3) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -99,61 +100,37 @@ */ /* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup NAND_Private_Constants NAND Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup NAND_Private_Macros NAND Private Macros - * @{ - */ - -/** - * @} - */ - +/* Private Constants ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @defgroup NAND_Private_Functions NAND Private Functions - * @{ - */ -static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address); -/** - * @} - */ - /* Exported functions ---------------------------------------------------------*/ /** @defgroup NAND_Exported_Functions NAND Exported Functions * @{ */ - -/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + +/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * - @verbatim + @verbatim ============================================================================== ##### NAND Initialization and de-initialization functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to initialize/de-initialize the NAND memory - + @endverbatim * @{ */ - + /** - * @brief Perform NAND memory Initialization sequence. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief Perform NAND memory Initialization sequence + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param ComSpace_Timing: pointer to Common space timing structure - * @param AttSpace_Timing: pointer to Attribute space timing structure + * @param ComSpace_Timing pointer to Common space timing structure + * @param AttSpace_Timing pointer to Attribute space timing structure * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing) @@ -168,23 +145,22 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT { /* Allocate lock resource and initialize it */ hnand->Lock = HAL_UNLOCKED; - /* Initialize the low level hardware (MSP) */ HAL_NAND_MspInit(hnand); - } + } /* Initialize NAND control Interface */ FMC_NAND_Init(hnand->Instance, &(hnand->Init)); - - /* Initialize NAND common space timing Interface */ + + /* Initialize NAND common space timing Interface */ FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank); - - /* Initialize NAND attribute space timing Interface */ + + /* Initialize NAND attribute space timing Interface */ FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank); - + /* Enable the NAND device */ - __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank); - + __FMC_NAND_ENABLE(hnand->Instance); + /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; @@ -192,12 +168,12 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT } /** - * @brief Perform NAND memory De-Initialization sequence. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief Perform NAND memory De-Initialization sequence + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) +HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) { /* Initialize the low level hardware (MSP) */ HAL_NAND_MspDeInit(hnand); @@ -215,8 +191,8 @@ HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) } /** - * @brief Initialize the NAND MSP. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief Initialize the NAND MSP + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval None */ @@ -227,12 +203,12 @@ __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand) /* NOTE : This function should not be modified, when the callback is needed, the HAL_NAND_MspInit could be implemented in the user file - */ + */ } /** - * @brief DeInitialize the NAND MSP. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief DeInitialize the NAND MSP + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval None */ @@ -243,13 +219,13 @@ __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand) /* NOTE : This function should not be modified, when the callback is needed, the HAL_NAND_MspDeInit could be implemented in the user file - */ + */ } /** * @brief This function handles NAND device interrupt request. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status */ @@ -260,11 +236,11 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) { /* NAND interrupt callback*/ HAL_NAND_ITCallback(hnand); - + /* Clear NAND interrupt Rising edge pending bit */ - __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE); + __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE); } - + /* Check NAND interrupt Level flag */ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL)) { @@ -272,7 +248,7 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) HAL_NAND_ITCallback(hnand); /* Clear NAND interrupt Level pending bit */ - __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL); + __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL); } /* Check NAND interrupt Falling edge flag */ @@ -280,25 +256,26 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) { /* NAND interrupt callback*/ HAL_NAND_ITCallback(hnand); - + /* Clear NAND interrupt Falling edge pending bit */ - __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE); + __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE); } - + /* Check NAND interrupt FIFO empty flag */ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT)) { /* NAND interrupt callback*/ HAL_NAND_ITCallback(hnand); - + /* Clear NAND interrupt FIFO empty pending bit */ - __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT); - } + __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT); + } + } /** - * @brief NAND interrupt feature callback. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief NAND interrupt feature callback + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval None */ @@ -311,476 +288,563 @@ __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand) the HAL_NAND_ITCallback could be implemented in the user file */ } - + /** * @} */ - -/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions - * @brief Input Output and memory control functions + +/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions + * @brief Input Output and memory control functions * - @verbatim + @verbatim ============================================================================== ##### NAND Input and Output functions ##### ============================================================================== - [..] - This section provides functions allowing to use and control the NAND + [..] + This section provides functions allowing to use and control the NAND memory - + @endverbatim * @{ */ /** - * @brief Read the NAND memory electronic signature. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief Read the NAND memory electronic signature + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pNAND_ID: NAND ID structure + * @param pNAND_ID NAND ID structure * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID) { __IO uint32_t data = 0; - uint32_t deviceaddress = 0; + __IO uint32_t data1 = 0; + uint32_t deviceAddress = 0; /* Process Locked */ - __HAL_LOCK(hnand); - + __HAL_LOCK(hnand); + /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) { return HAL_BUSY; } - + /* Identify the device address */ - deviceaddress = NAND_DEVICE; - - /* Update the NAND controller state */ + deviceAddress = NAND_DEVICE; + + /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_BUSY; - - /* Send Read ID command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - - /* Read the electronic signature from NAND flash */ - data = *(__IO uint32_t *)deviceaddress; - - /* Return the data read */ - pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); - pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data); - pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data); - pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data); - - /* Update the NAND controller state */ + + /* Send Read ID command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + + /* Read the electronic signature from NAND flash */ + if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8) + { + data = *(__IO uint32_t *)deviceAddress; + + /* Return the data read */ + pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); + pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data); + pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data); + pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data); + } + else + { + data = *(__IO uint32_t *)deviceAddress; + data1 = *((__IO uint32_t *)deviceAddress + 4); + + /* Return the data read */ + pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); + pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data); + pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1); + pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1); + } + + /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; - + /* Process unlocked */ - __HAL_UNLOCK(hnand); - + __HAL_UNLOCK(hnand); + return HAL_OK; } /** - * @brief NAND memory reset. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief NAND memory reset + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) { - uint32_t deviceaddress = 0; - + uint32_t deviceAddress = 0; + /* Process Locked */ __HAL_LOCK(hnand); - + /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) { return HAL_BUSY; } - /* Identify the device address */ - deviceaddress = NAND_DEVICE; - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Send NAND reset command */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF; - - - /* Update the NAND controller state */ + /* Identify the device address */ + deviceAddress = NAND_DEVICE; + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Send NAND reset command */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF; + + /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; - + /* Process unlocked */ - __HAL_UNLOCK(hnand); - + __HAL_UNLOCK(hnand); + + return HAL_OK; + +} + +/** + * @brief Configure the device: Enter the physical parameters of the device + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig) +{ + hnand->Config.PageSize = pDeviceConfig->PageSize; + hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize; + hnand->Config.BlockSize = pDeviceConfig->BlockSize; + hnand->Config.BlockNbr = pDeviceConfig->BlockNbr; + hnand->Config.PlaneSize = pDeviceConfig->PlaneSize; + hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr; + hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable; + return HAL_OK; - } + /** - * @brief Read Page(s) from NAND memory block. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief Read Page(s) from NAND memory block (8-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress: pointer to NAND address structure - * @param pBuffer: pointer to destination read buffer - * @param NumPageToRead: number of pages to read from block + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to destination read buffer + * @param NumPageToRead number of pages to read from block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead) -{ +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead) +{ __IO uint32_t index = 0; - uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS; - NAND_AddressTypeDef nandaddress; - uint32_t addressoffset = 0; - + uint32_t tickstart = 0U; + uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0; + /* Process Locked */ - __HAL_LOCK(hnand); - + __HAL_LOCK(hnand); + /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) { return HAL_BUSY; } - + /* Identify the device address */ - deviceaddress = NAND_DEVICE; + deviceAddress = NAND_DEVICE; - /* Update the NAND controller state */ + /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_BUSY; - - /* Save the content of pAddress as it will be modified */ - nandaddress.Block = pAddress->Block; - nandaddress.Page = pAddress->Page; - nandaddress.Zone = pAddress->Zone; - + + /* NAND raw address calculation */ + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + /* Page(s) read loop */ - while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS)) - { + while ((NumPageToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { /* update the buffer size */ - size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread); - - /* Get the address offset */ - addressoffset = ARRAY_ADDRESS(&nandaddress, hnand); - + size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead); + /* Send read page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512) + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + __DSB(); + + + if (hnand->Config.ExtraCommandEnable == ENABLE) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset); + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + __DSB(); } - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; - - /* Get Data into Buffer */ + + /* Get Data into Buffer */ for(; index < size; index++) { - *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress; + *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress; } - + /* Increment read pages number */ - numpagesread++; - + numPagesRead++; + /* Decrement pages to read */ NumPageToRead--; - + /* Increment the NAND address */ - addressstatus = NAND_AddressIncrement(hnand, &nandaddress); + nandAddress = (uint32_t)(nandAddress + 1); } - - /* Update the NAND controller state */ + + /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; - + /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_OK; + __HAL_UNLOCK(hnand); + return HAL_OK; } /** - * @brief Write Page(s) to NAND memory block. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief Read Page(s) from NAND memory block (16-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress: pointer to NAND address structure - * @param pBuffer: pointer to source buffer to write - * @param NumPageToWrite: number of pages to write to block + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to destination read buffer. pBuffer should be 16bits aligned + * @param NumPageToRead number of pages to read from block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite) +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead) { - __IO uint32_t index = 0; + __IO uint32_t index = 0; uint32_t tickstart = 0; - uint32_t deviceaddress = 0 , size = 0, numpageswritten = 0, addressstatus = NAND_VALID_ADDRESS; - NAND_AddressTypeDef nandaddress; - uint32_t addressoffset = 0; - + uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0; + /* Process Locked */ - __HAL_LOCK(hnand); + __HAL_LOCK(hnand); /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) + if (hnand->State == HAL_NAND_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - + /* Identify the device address */ - deviceaddress = NAND_DEVICE; - - /* Update the NAND controller state */ + deviceAddress = NAND_DEVICE; + + /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_BUSY; - - /* Save the content of pAddress as it will be modified */ - nandaddress.Block = pAddress->Block; - nandaddress.Page = pAddress->Page; - nandaddress.Zone = pAddress->Zone; - - /* Page(s) write loop */ - while((NumPageToWrite != 0) && (addressstatus == NAND_VALID_ADDRESS)) - { + + /* NAND raw address calculation */ + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Page(s) read loop */ + while ((NumPageToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { /* update the buffer size */ - size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten); - - /* Get the address offset */ - addressoffset = ARRAY_ADDRESS(&nandaddress, hnand); - - /* Send write page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; - - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead); + + /* Send read page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset); + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } } - - /* Write data to memory */ - for(; index < size; index++) + else /* (hnand->Config.PageSize) > 512 */ { - *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++; + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } } - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) + + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + __DSB(); + + if (hnand->Config.ExtraCommandEnable == ENABLE) { - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) { - return HAL_TIMEOUT; - } - } - - /* Increment written pages number */ - numpageswritten++; - - /* Decrement pages to write */ - NumPageToWrite--; - - /* Increment the NAND address */ - addressstatus = NAND_AddressIncrement(hnand, &nandaddress); - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_OK; -} + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } -/** - * @brief Read Spare area(s) from NAND memory. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress: pointer to NAND address structure - * @param pBuffer: pointer to source buffer to write - * @param NumSpareAreaToRead: Number of spare area to read - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead) -{ - __IO uint32_t index = 0; - uint32_t deviceaddress = 0, size = 0, num_spare_area_read = 0, addressstatus = NAND_VALID_ADDRESS; - NAND_AddressTypeDef nandaddress; - uint32_t addressoffset = 0; - - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - deviceaddress = NAND_DEVICE; - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Save the content of pAddress as it will be modified */ - nandaddress.Block = pAddress->Block; - nandaddress.Page = pAddress->Page; - nandaddress.Zone = pAddress->Zone; - - /* Spare area(s) read loop */ - while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS)) - { - /* update the buffer size */ - size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read); - - /* Get the address offset */ - addressoffset = ARRAY_ADDRESS(&nandaddress, hnand); - - /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; - - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset); - } + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + __DSB(); + } - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; - /* Get Data into Buffer */ - for ( ;index < size; index++) + for (; index < size; index++) { - *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress; + *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress; } - - /* Increment read spare areas number */ - num_spare_area_read++; - - /* Decrement spare areas to read */ - NumSpareAreaToRead--; - + + /* Increment read pages number */ + numPagesRead++; + + /* Decrement pages to read */ + NumPageToRead--; + /* Increment the NAND address */ - addressstatus = NAND_AddressIncrement(hnand, &nandaddress); + nandAddress = (uint32_t)(nandAddress + 1); } - + /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; - + /* Process unlocked */ - __HAL_UNLOCK(hnand); + __HAL_UNLOCK(hnand); - return HAL_OK; + return HAL_OK; } /** - * @brief Write Spare area(s) to NAND memory. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief Write Page(s) to NAND memory block (8-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress: pointer to NAND address structure - * @param pBuffer: pointer to source buffer to write - * @param NumSpareAreaTowrite: number of spare areas to write to block + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write + * @param NumPageToWrite number of pages to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite) { __IO uint32_t index = 0; uint32_t tickstart = 0; - uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS; - NAND_AddressTypeDef nandaddress; - uint32_t addressoffset = 0; + uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0; /* Process Locked */ - __HAL_LOCK(hnand); - + __HAL_LOCK(hnand); + /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) { return HAL_BUSY; } - + /* Identify the device address */ - deviceaddress = NAND_DEVICE; - - /* Update the FMC_NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Save the content of pAddress as it will be modified */ - nandaddress.Block = pAddress->Block; - nandaddress.Page = pAddress->Page; - nandaddress.Zone = pAddress->Zone; - - /* Spare area(s) write loop */ - while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS)) - { + deviceAddress = NAND_DEVICE; + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* NAND raw address calculation */ + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Page(s) write loop */ + while ((NumPageToWrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { /* update the buffer size */ - size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written); - - /* Get the address offset */ - addressoffset = ARRAY_ADDRESS(&nandaddress, hnand); - - /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; - - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten); + + /* Send write page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512) + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset); + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } } - + /* Write data to memory */ - for(; index < size; index++) + for (; index < size; index++) { - *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++; + *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++; + __DSB(); } - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; - + + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + __DSB(); + /* Get tick */ tickstart = HAL_GetTick(); - + /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) + while (HAL_NAND_Read_Status(hnand) != NAND_READY) { - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) { - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; + } } - /* Increment written spare areas number */ - num_spare_area_written++; - - /* Decrement spare areas to write */ - NumSpareAreaTowrite--; - + /* Increment written pages number */ + numPagesWritten++; + + /* Decrement pages to write */ + NumPageToWrite--; + /* Increment the NAND address */ - addressstatus = NAND_AddressIncrement(hnand, &nandaddress); + nandAddress = (uint32_t)(nandAddress + 1); } /* Update the NAND controller state */ @@ -788,117 +852,793 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre /* Process unlocked */ __HAL_UNLOCK(hnand); - - return HAL_OK; + + return HAL_OK; } /** - * @brief NAND memory Block erase. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief Write Page(s) to NAND memory block (16-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress: pointer to NAND address structure + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned + * @param NumPageToWrite number of pages to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite) { - uint32_t deviceaddress = 0; + __IO uint32_t index = 0; uint32_t tickstart = 0; - + uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0; + + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Check the NAND controller state */ + if (hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Identify the device address */ + deviceAddress = NAND_DEVICE; + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* NAND raw address calculation */ + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Page(s) write loop */ + while ((NumPageToWrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* update the buffer size */ + size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten); + + /* Send write page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512) + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + + /* Write data to memory */ + for(; index < size; index++) + { + *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++; + __DSB(); + } + + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + __DSB(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while(HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Increment written pages number */ + numPagesWritten++; + + /* Decrement pages to write */ + NumPageToWrite--; + + /* Increment the NAND address */ + nandAddress = (uint32_t)(nandAddress + 1); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_OK; +} + +/** + * @brief Read Spare area(s) from NAND memory (8-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write + * @param NumSpareAreaToRead Number of spare area to read + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0U; + uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0, columnAddress = 0; + + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Check the NAND controller state */ + if (hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Identify the device address */ + deviceAddress = NAND_DEVICE; + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* NAND raw address calculation */ + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnAddress = COLUMN_ADDRESS(hnand); + + /* Spare area(s) read loop */ + while ((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* update the buffer size */ + size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512) + { + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + __DSB(); + + if (hnand->Config.ExtraCommandEnable == ENABLE) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + __DSB(); + } + + /* Get Data into Buffer */ + for (; index < size; index++) + { + *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress; + } + + /* Increment read spare areas number */ + numSpareAreaRead++; + + /* Decrement spare areas to read */ + NumSpareAreaToRead--; + + /* Increment the NAND address */ + nandAddress = (uint32_t)(nandAddress + 1); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_OK; +} + +/** + * @brief Read Spare area(s) from NAND memory (16-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned. + * @param NumSpareAreaToRead Number of spare area to read + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0U; + uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0, columnAddress = 0; + /* Process Locked */ __HAL_LOCK(hnand); - + /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) { return HAL_BUSY; } - + /* Identify the device address */ - deviceaddress = NAND_DEVICE; - + deviceAddress = NAND_DEVICE; + /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Send Erase block command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0; - - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + hnand->State = HAL_NAND_STATE_BUSY; + + /* NAND raw address calculation */ + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2); + + /* Spare area(s) read loop */ + while ((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - } - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1; - + /* update the buffer size */ + size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512) + { + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + __DSB(); + + if (hnand->Config.ExtraCommandEnable == ENABLE) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + __DSB(); + } + + /* Get Data into Buffer */ + for ( ;index < size; index++) + { + *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress; + } + + /* Increment read spare areas number */ + numSpareAreaRead++; + + /* Decrement spare areas to read */ + NumSpareAreaToRead--; + + /* Increment the NAND address */ + nandAddress = (uint32_t)(nandAddress + 1); + } + /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_OK; +} + +/** + * @brief Write Spare area(s) to NAND memory (8-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write + * @param NumSpareAreaTowrite number of spare areas to write to block + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0, columnAddress = 0; + + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Check the NAND controller state */ + if(hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Identify the device address */ + deviceAddress = NAND_DEVICE; + + /* Update the FMC_NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Page address calculation */ + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnAddress = COLUMN_ADDRESS(hnand); + + /* Spare area(s) write loop */ + while ((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + /* update the buffer size */ + size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512) + { + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + + /* Write data to memory */ + for(; index < size; index++) + { + *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++; + __DSB(); + } + + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + __DSB(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while(HAL_NAND_Read_Status(hnand) != NAND_READY) { - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_TIMEOUT; - } - } - + if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Increment written spare areas number */ + numSpareAreaWritten++; + + /* Decrement spare areas to write */ + NumSpareAreaTowrite--; + + /* Increment the NAND address */ + nandAddress = (uint32_t)(nandAddress + 1); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_OK; + __HAL_UNLOCK(hnand); + + return HAL_OK; } /** - * @brief NAND memory read status. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief Write Spare area(s) to NAND memory (16-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @retval NAND status + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned. + * @param NumSpareAreaTowrite number of spare areas to write to block + * @retval HAL status */ -uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) { - uint32_t data = 0; - uint32_t deviceaddress = 0; - - /* Prevent unused argument(s) compilation warning */ - UNUSED(hnand); + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0, columnAddress = 0; + + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Check the NAND controller state */ + if (hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } /* Identify the device address */ - deviceaddress = NAND_DEVICE; + deviceAddress = NAND_DEVICE; - /* Send Read status operation command */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS; - - /* Read status register data */ - data = *(__IO uint8_t *)deviceaddress; + /* Update the FMC_NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; - /* Return the status */ - if((data & NAND_ERROR) == NAND_ERROR) + /* NAND raw address calculation */ + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2); + + /* Spare area(s) write loop */ + while ((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { - return NAND_ERROR; - } - else if((data & NAND_READY) == NAND_READY) + /* update the buffer size */ + size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512) + { + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + + /* Write data to memory */ + for (; index < size; index++) + { + *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++; + __DSB(); + } + + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + __DSB(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Increment written spare areas number */ + numSpareAreaWritten++; + + /* Decrement spare areas to write */ + NumSpareAreaTowrite--; + + /* Increment the NAND address */ + nandAddress = (uint32_t)(nandAddress + 1); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_OK; +} + +/** + * @brief NAND memory Block erase + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress pointer to NAND address structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) +{ + uint32_t DeviceAddress = 0; + + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Check the NAND controller state */ + if(hnand->State == HAL_NAND_STATE_BUSY) { - return NAND_READY; + return HAL_BUSY; } - return NAND_BUSY; + /* Identify the device address */ + DeviceAddress = NAND_DEVICE; + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Send Erase block command sequence */ + *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0; + __DSB(); + *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + __DSB(); + *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + __DSB(); + *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + __DSB(); + + *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1; + __DSB(); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_OK; } /** - * @brief Increment the NAND memory address. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief Increment the NAND memory address + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress: pointer to NAND address structure + * @param pAddress pointer to NAND address structure * @retval The new status of the increment address operation. It can be: * - NAND_VALID_ADDRESS: When the new address is valid address * - NAND_INVALID_ADDRESS: When the new address is invalid address @@ -906,56 +1646,56 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) { uint32_t status = NAND_VALID_ADDRESS; - + /* Increment page address */ pAddress->Page++; /* Check NAND address is valid */ - if(pAddress->Page == hnand->Info.BlockSize) + if (pAddress->Page == hnand->Config.BlockSize) { pAddress->Page = 0; pAddress->Block++; - - if(pAddress->Block == hnand->Info.ZoneSize) + + if (pAddress->Block == hnand->Config.PlaneSize) { pAddress->Block = 0; - pAddress->Zone++; + pAddress->Plane++; - if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr)) + if (pAddress->Plane == (hnand->Config.PlaneNbr)) { status = NAND_INVALID_ADDRESS; } } - } - + } + return (status); } /** * @} */ -/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions +/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions + * @brief management functions * -@verbatim +@verbatim ============================================================================== ##### NAND Control functions ##### - ============================================================================== + ============================================================================== [..] This subsection provides a set of functions allowing to control dynamically the NAND interface. @endverbatim * @{ - */ + */ + - /** * @brief Enable dynamically NAND ECC feature. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand) { /* Check the NAND controller state */ @@ -966,23 +1706,23 @@ HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand) /* Update the NAND state */ hnand->State = HAL_NAND_STATE_BUSY; - + /* Enable ECC feature */ FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank); - + /* Update the NAND state */ hnand->State = HAL_NAND_STATE_READY; - - return HAL_OK; + + return HAL_OK; } /** - * @brief Disable dynamically NAND ECC feature. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief Disable dynamically NAND ECC feature + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand) + */ +HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand) { /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) @@ -992,69 +1732,69 @@ HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand) /* Update the NAND state */ hnand->State = HAL_NAND_STATE_BUSY; - + /* Disable ECC feature */ FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank); - + /* Update the NAND state */ hnand->State = HAL_NAND_STATE_READY; - - return HAL_OK; + + return HAL_OK; } /** - * @brief Disable dynamically NAND ECC feature. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief Get NAND ECC value + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param ECCval: pointer to ECC value - * @param Timeout: maximum timeout to wait + * @param ECCval pointer to ECC value + * @param Timeout maximum timeout to wait * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) { return HAL_BUSY; } - + /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_BUSY; - + hnand->State = HAL_NAND_STATE_BUSY; + /* Get NAND ECC value */ status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout); - + /* Update the NAND state */ hnand->State = HAL_NAND_STATE_READY; - return status; + return status; } - + /** * @} */ - - -/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions + + +/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions * -@verbatim +@verbatim ============================================================================== ##### NAND State functions ##### - ============================================================================== + ============================================================================== [..] - This subsection permits to get in run-time the status of the NAND controller + This subsection permits to get in run-time the status of the NAND controller and the data flow. @endverbatim * @{ */ - + /** - * @brief Return the NAND handle state. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief Return the NAND state + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL state */ @@ -1065,50 +1805,36 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) } /** - * @} - */ - -/** - * @} - */ - -/** @addtogroup NAND_Private_Functions - * @{ - */ - -/** - * @brief Increment the NAND memory address. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief NAND memory read status + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param Address: address to be incremented. - * @retval The new status of the increment address operation. It can be: - * - NAND_VALID_ADDRESS: When the new address is valid address - * - NAND_INVALID_ADDRESS: When the new address is invalid address + * @retval NAND status */ -static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address) +uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) { - uint32_t status = NAND_VALID_ADDRESS; - - Address->Page++; + uint32_t data = 0; + uint32_t DeviceAddress = 0; + + /* Identify the device address */ + DeviceAddress = NAND_DEVICE; - if(Address->Page == hnand->Info.BlockSize) + /* Send Read status operation command */ + *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS; + + /* Read status register data */ + data = *(__IO uint8_t *)DeviceAddress; + + /* Return the status */ + if ((data & NAND_ERROR) == NAND_ERROR) { - Address->Page = 0; - Address->Block++; - - if(Address->Block == hnand->Info.ZoneSize) - { - Address->Block = 0; - Address->Zone++; + return NAND_ERROR; + } + else if ((data & NAND_READY) == NAND_READY) + { + return NAND_READY; + } - if(Address->Zone == hnand->Info.BlockNbr) - { - status = NAND_INVALID_ADDRESS; - } - } - } - - return (status); + return NAND_BUSY; } /** @@ -1119,14 +1845,16 @@ static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTyp * @} */ +/** + * @} + */ + #endif /* HAL_NAND_MODULE_ENABLED */ /** * @} */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* FMC_BANK3 */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nor.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nor.c index ff8c7936e6..d7668c9a86 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nor.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nor.c @@ -3,50 +3,50 @@ * @file stm32l4xx_hal_nor.c * @author MCD Application Team * @brief NOR HAL module driver. - * This file provides a generic firmware to drive NOR memories mounted + * This file provides a generic firmware to drive NOR memories mounted * as external device. - * + * @verbatim ============================================================================== ##### How to use this driver ##### - ============================================================================== + ============================================================================== [..] - This driver is a generic layered driver which contains a set of APIs used to - control NOR flash memories. It uses the FMC layer functions to interface + This driver is a generic layered driver which contains a set of APIs used to + control NOR flash memories. It uses the FMC layer functions to interface with NOR devices. This driver is used as follows: - - (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() + + (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() with control and timing parameters for both normal and extended mode. - + (+) Read NOR flash memory manufacturer code and device IDs using the function - HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef - structure declared by the function caller. - + HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef + structure declared by the function caller. + (+) Access NOR flash memory by read/write data unit operations using the functions HAL_NOR_Read(), HAL_NOR_Program(). - - (+) Perform NOR flash erase block/chip operations using the functions + + (+) Perform NOR flash erase block/chip operations using the functions HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip(). - + (+) Read the NOR flash CFI (common flash interface) IDs using the function HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef structure declared by the function caller. - + (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/ - HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation - + HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation + (+) You can monitor the NOR device HAL state by calling the function - HAL_NOR_GetState() + HAL_NOR_GetState() [..] (@) This driver is a set of generic APIs which handle standard NOR flash operations. - If a NOR flash device contains different operations and/or implementations, + If a NOR flash device contains different operations and/or implementations, it should be implemented separately. *** NOR HAL driver macros list *** - ============================================= + ============================================= [..] Below the list of most used macros in NOR HAL driver. - + (+) NOR_WRITE : NOR memory write data to specified address @endverbatim @@ -78,14 +78,12 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(FMC_BANK1) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -94,12 +92,14 @@ #ifdef HAL_NOR_MODULE_ENABLED /** @defgroup NOR NOR - * @brief NOR HAL module driver + * @brief NOR driver modules * @{ */ + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @defgroup NOR_Private_Constants NOR Private Constants + +/** @defgroup NOR_Private_Defines NOR Private Defines * @{ */ @@ -137,16 +137,7 @@ */ /* Private macro -------------------------------------------------------------*/ -/** @defgroup NOR_Private_Macros NOR Private Macros - * @{ - */ - -/** - * @} - */ - /* Private variables ---------------------------------------------------------*/ - /** @defgroup NOR_Private_Variables NOR Private Variables * @{ */ @@ -157,33 +148,33 @@ static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B; * @} */ -/* Exported functions ---------------------------------------------------------*/ - +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @defgroup NOR_Exported_Functions NOR Exported Functions * @{ */ -/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * - @verbatim + @verbatim ============================================================================== ##### NOR Initialization and de-initialization functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to initialize/de-initialize the NOR memory - + @endverbatim * @{ */ - + /** - * @brief Perform the NOR memory Initialization sequence. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @brief Perform the NOR memory Initialization sequence + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param Timing: pointer to NOR control timing structure - * @param ExtTiming: pointer to NOR extended mode timing structure + * @param Timing pointer to NOR control timing structure + * @param ExtTiming pointer to NOR extended mode timing structure * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) @@ -193,12 +184,11 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe { return HAL_ERROR; } - + if(hnor->State == HAL_NOR_STATE_RESET) { /* Allocate lock resource and initialize it */ hnor->Lock = HAL_UNLOCKED; - /* Initialize the low level hardware (MSP) */ HAL_NOR_MspInit(hnor); } @@ -207,13 +197,13 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init)); /* Initialize NOR timing Interface */ - FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); + FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); /* Initialize NOR extended mode timing Interface */ FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode); /* Enable the NORSRAM device */ - __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); + __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); /* Initialize NOR Memory Data Width*/ if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8) @@ -226,25 +216,25 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe } /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - + hnor->State = HAL_NOR_STATE_READY; + return HAL_OK; } /** - * @brief Perform NOR memory De-Initialization sequence. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @brief Perform NOR memory De-Initialization sequence + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval HAL status */ -HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) +HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) { /* De-Initialize the low level hardware (MSP) */ HAL_NOR_MspDeInit(hnor); - + /* Configure the NOR registers with their reset values */ FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); - + /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_RESET; @@ -256,7 +246,7 @@ HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) /** * @brief Initialize the NOR MSP. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval None */ @@ -267,12 +257,12 @@ __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor) /* NOTE : This function should not be modified, when the callback is needed, the HAL_NOR_MspInit could be implemented in the user file - */ + */ } /** * @brief DeInitialize the NOR MSP. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval None */ @@ -283,14 +273,14 @@ __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor) /* NOTE : This function should not be modified, when the callback is needed, the HAL_NOR_MspDeInit could be implemented in the user file - */ + */ } /** - * @brief NOR MSP Wait for Ready/Busy signal. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @brief NOR MSP Wait for Ready/Busy signal + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param Timeout: Maximum timeout value + * @param Timeout Maximum timeout value * @retval None */ __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) @@ -301,47 +291,47 @@ __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) /* NOTE : This function should not be modified, when the callback is needed, the HAL_NOR_MspWait could be implemented in the user file - */ + */ } - + /** * @} */ -/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions - * @brief Input Output and memory control functions +/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions + * @brief Input Output and memory control functions * - @verbatim + @verbatim ============================================================================== ##### NOR Input and Output functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to use and control the NOR memory - + @endverbatim * @{ */ - + /** - * @brief Read NOR flash IDs. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @brief Read NOR flash IDs + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param pNOR_ID : pointer to NOR ID structure + * @param pNOR_ID pointer to NOR ID structure * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID) { uint32_t deviceaddress = 0; - + /* Process Locked */ __HAL_LOCK(hnor); - + /* Check the NOR controller state */ if(hnor->State == HAL_NOR_STATE_BUSY) { return HAL_BUSY; } - + /* Select the NOR device address */ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) { @@ -358,11 +348,11 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I else /* FMC_NORSRAM_BANK4 */ { deviceaddress = NOR_MEMORY_ADRESS4; - } - + } + /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; - + /* Send read ID command */ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); @@ -373,35 +363,35 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR); pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR); pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR); - + /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; - + /* Process unlocked */ - __HAL_UNLOCK(hnor); - + __HAL_UNLOCK(hnor); + return HAL_OK; } /** * @brief Return the NOR memory to Read mode. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) { - uint32_t deviceaddress = 0; - + uint32_t deviceaddress = 0; + /* Process Locked */ __HAL_LOCK(hnor); - + /* Check the NOR controller state */ if(hnor->State == HAL_NOR_STATE_BUSY) { return HAL_BUSY; } - + /* Select the NOR device address */ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) { @@ -418,40 +408,40 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) else /* FMC_NORSRAM_BANK4 */ { deviceaddress = NOR_MEMORY_ADRESS4; - } - + } + NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET); /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; - + /* Process unlocked */ - __HAL_UNLOCK(hnor); - + __HAL_UNLOCK(hnor); + return HAL_OK; } /** - * @brief Read data from NOR memory. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @brief Read data from NOR memory + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param pAddress: pointer to Device address - * @param pData : pointer to read data + * @param pAddress pointer to Device address + * @param pData pointer to read data * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) { uint32_t deviceaddress = 0; - + /* Process Locked */ __HAL_LOCK(hnor); - + /* Check the NOR controller state */ if(hnor->State == HAL_NOR_STATE_BUSY) { return HAL_BUSY; } - + /* Select the NOR device address */ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) { @@ -468,49 +458,49 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint else /* FMC_NORSRAM_BANK4 */ { deviceaddress = NOR_MEMORY_ADRESS4; - } - + } + /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; - + /* Send read data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); /* Read the data */ *pData = *(__IO uint32_t *)(uint32_t)pAddress; - + /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hnor); - - return HAL_OK; + + return HAL_OK; } /** - * @brief Program data to NOR memory. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @brief Program data to NOR memory + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param pAddress: Device address - * @param pData : pointer to the data to write + * @param pAddress Device address + * @param pData pointer to the data to write * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) { uint32_t deviceaddress = 0; - + /* Process Locked */ __HAL_LOCK(hnor); - + /* Check the NOR controller state */ if(hnor->State == HAL_NOR_STATE_BUSY) { return HAL_BUSY; } - + /* Select the NOR device address */ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) { @@ -527,11 +517,11 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u else /* FMC_NORSRAM_BANK4 */ { deviceaddress = NOR_MEMORY_ADRESS4; - } - + } + /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; - + /* Send program data command */ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); @@ -539,39 +529,38 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u /* Write the data */ NOR_WRITE(pAddress, *pData); - + /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hnor); - - return HAL_OK; + + return HAL_OK; } /** - * @brief Read a block of data from the FMC NOR memory. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param uwAddress: NOR memory internal address to read from. - * @param pData: pointer to the buffer that receives the data read from the + * @brief Read a half-word buffer from the NOR memory. + * @param hnor pointer to the NOR handle + * @param uwAddress NOR memory internal address to read from. + * @param pData pointer to the buffer that receives the data read from the * NOR memory. - * @param uwBufferSize : number of Half word to read. + * @param uwBufferSize number of Half word to read. * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) { uint32_t deviceaddress = 0; - + /* Process Locked */ __HAL_LOCK(hnor); - + /* Check the NOR controller state */ if(hnor->State == HAL_NOR_STATE_BUSY) { return HAL_BUSY; } - + /* Select the NOR device address */ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) { @@ -588,62 +577,57 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress else /* FMC_NORSRAM_BANK4 */ { deviceaddress = NOR_MEMORY_ADRESS4; - } - + } + /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; - + /* Send read data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET); - + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + /* Read buffer */ - while( uwBufferSize > 0) + while( uwBufferSize > 0) { *pData++ = *(__IO uint16_t *)uwAddress; uwAddress += 2; uwBufferSize--; - } - + } + /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hnor); - - return HAL_OK; + + return HAL_OK; } /** - * @brief Write a half-word buffer to the FMC NOR memory. This function - * must be used only with S29GL128P NOR memory. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param uwAddress: NOR memory internal address from which the data - * @note Some NOR memory need Address aligned to xx bytes (can be aligned to - * 64 bytes boundary for example). - * @param pData: pointer to source data buffer. - * @param uwBufferSize: number of Half words to write. - * @note The maximum buffer size allowed is NOR memory dependent - * (can be 64 Bytes max for example). + * @brief Writes a half-word buffer to the NOR memory. This function must be used + only with S29GL128P NOR memory. + * @param hnor pointer to the NOR handle + * @param uwAddress NOR memory internal start write address + * @param pData pointer to source data buffer. + * @param uwBufferSize Size of the buffer to write * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) { uint16_t * p_currentaddress = (uint16_t *)NULL; uint16_t * p_endaddress = (uint16_t *)NULL; uint32_t lastloadedaddress = 0, deviceaddress = 0; - + /* Process Locked */ __HAL_LOCK(hnor); - + /* Check the NOR controller state */ if(hnor->State == HAL_NOR_STATE_BUSY) { return HAL_BUSY; } - + /* Select the NOR device address */ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) { @@ -660,11 +644,11 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr else /* FMC_NORSRAM_BANK4 */ { deviceaddress = NOR_MEMORY_ADRESS4; - } - + } + /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; - + /* Initialize variables */ p_currentaddress = (uint16_t*)((uint32_t)(uwAddress)); p_endaddress = p_currentaddress + (uwBufferSize-1); @@ -672,41 +656,41 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr /* Issue unlock command sequence */ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); /* Write Buffer Load Command */ - NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG); - NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1)); + NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG); + NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1)); /* Load Data into NOR Buffer */ while(p_currentaddress <= p_endaddress) { /* Store last loaded address & data value (for polling) */ lastloadedaddress = (uint32_t)p_currentaddress; - + NOR_WRITE(p_currentaddress, *pData++); - + p_currentaddress++; } - NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); - + NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); + /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hnor); - - return HAL_OK; - + + return HAL_OK; + } /** - * @brief Erase the specified block of the NOR memory. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @brief Erase the specified block of the NOR memory + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param BlockAddress : Block to erase address - * @param Address: Device address + * @param BlockAddress Block to erase address + * @param Address Device address * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address) @@ -715,13 +699,13 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd /* Process Locked */ __HAL_LOCK(hnor); - + /* Check the NOR controller state */ if(hnor->State == HAL_NOR_STATE_BUSY) { return HAL_BUSY; } - + /* Select the NOR device address */ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) { @@ -739,10 +723,10 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd { deviceaddress = NOR_MEMORY_ADRESS4; } - + /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; - + /* Send block erase command sequence */ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); @@ -753,37 +737,37 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd /* Check the NOR memory status and update the controller state */ hnor->State = HAL_NOR_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hnor); - + return HAL_OK; - + } /** * @brief Erase the entire NOR chip. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param Address : Device address + * @param Address Device address * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) { uint32_t deviceaddress = 0; - + /* Prevent unused argument(s) compilation warning */ UNUSED(Address); /* Process Locked */ __HAL_LOCK(hnor); - + /* Check the NOR controller state */ if(hnor->State == HAL_NOR_STATE_BUSY) { return HAL_BUSY; } - + /* Select the NOR device address */ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) { @@ -801,47 +785,47 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) { deviceaddress = NOR_MEMORY_ADRESS4; } - + /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - + hnor->State = HAL_NOR_STATE_BUSY; + /* Send NOR chip erase command sequence */ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); - + /* Check the NOR memory status and update the controller state */ hnor->State = HAL_NOR_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hnor); - - return HAL_OK; + + return HAL_OK; } /** - * @brief Read NOR flash CFI IDs. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @brief Read NOR flash CFI IDs + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param pNOR_CFI : pointer to NOR CFI IDs structure + * @param pNOR_CFI pointer to NOR CFI IDs structure * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI) { uint32_t deviceaddress = 0; - + /* Process Locked */ __HAL_LOCK(hnor); - + /* Check the NOR controller state */ if(hnor->State == HAL_NOR_STATE_BUSY) { return HAL_BUSY; } - + /* Select the NOR device address */ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) { @@ -858,11 +842,11 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR else /* FMC_NORSRAM_BANK4 */ { deviceaddress = NOR_MEMORY_ADRESS4; - } - + } + /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; - + /* Send read CFI query command */ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); @@ -874,21 +858,21 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hnor); - + return HAL_OK; } /** * @} */ - -/** @defgroup NOR_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions + +/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions + * @brief management functions * -@verbatim +@verbatim ============================================================================== ##### NOR Control functions ##### ============================================================================== @@ -899,10 +883,10 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR @endverbatim * @{ */ - + /** * @brief Enable dynamically NOR write operation. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval HAL status */ @@ -912,20 +896,20 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) __HAL_LOCK(hnor); /* Enable write operation */ - FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); - + FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); + /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; - + /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; + __HAL_UNLOCK(hnor); + + return HAL_OK; } /** * @brief Disable dynamically NOR write operation. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval HAL status */ @@ -936,41 +920,41 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) /* Update the SRAM controller state */ hnor->State = HAL_NOR_STATE_BUSY; - + /* Disable write operation */ - FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); - + FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); + /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_PROTECTED; - + /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; + __HAL_UNLOCK(hnor); + + return HAL_OK; } /** * @} - */ - -/** @defgroup NOR_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions + */ + +/** @defgroup NOR_Exported_Functions_Group4 NOR State functions + * @brief Peripheral State functions * -@verbatim +@verbatim ============================================================================== ##### NOR State functions ##### - ============================================================================== + ============================================================================== [..] - This subsection permits to get in run-time the status of the NOR controller + This subsection permits to get in run-time the status of the NOR controller and the data flow. @endverbatim * @{ */ - + /** - * @brief Return the NOR controller handle state. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @brief Return the NOR controller state + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval NOR controller state */ @@ -982,22 +966,24 @@ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) /** * @brief Return the NOR operation status. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param Address: Device address - * @param Timeout: NOR programming Timeout - * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR + * @param hnor pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @param Address Device address + * @param Timeout NOR programming Timeout + * @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR * or HAL_NOR_STATUS_TIMEOUT */ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) -{ +{ HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING; - uint16_t tmp_sr1 = 0, tmp_sr2 = 0; + uint16_t tmpSR1 = 0, tmpSR2 = 0; uint32_t tickstart = 0; /* Poll on NOR memory Ready/Busy signal ------------------------------------*/ HAL_NOR_MspWait(hnor, Timeout); - + + /* Get the NOR memory operation status -------------------------------------*/ + /* Get tick */ tickstart = HAL_GetTick(); while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT)) @@ -1007,37 +993,37 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres { if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { - status = HAL_NOR_STATUS_TIMEOUT; - } - } + status = HAL_NOR_STATUS_TIMEOUT; + } + } /* Read NOR status register (DQ6 and DQ5) */ - tmp_sr1 = *(__IO uint16_t *)Address; - tmp_sr2 = *(__IO uint16_t *)Address; + tmpSR1 = *(__IO uint16_t *)Address; + tmpSR2 = *(__IO uint16_t *)Address; - /* If DQ6 did not toggle between the two reads then return NOR_Success */ - if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6)) + /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ + if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) { return HAL_NOR_STATUS_SUCCESS; } - - if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5) + + if((tmpSR1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5) { status = HAL_NOR_STATUS_ONGOING; } - - tmp_sr1 = *(__IO uint16_t *)Address; - tmp_sr2 = *(__IO uint16_t *)Address; - /* If DQ6 did not toggle between the two reads then return NOR_Success */ - if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6)) + tmpSR1 = *(__IO uint16_t *)Address; + tmpSR2 = *(__IO uint16_t *)Address; + + /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ + if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) { return HAL_NOR_STATUS_SUCCESS; } - else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) { return HAL_NOR_STATUS_ERROR; - } + } } /* Return the operation status */ @@ -1051,17 +1037,17 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres /** * @} */ + /** * @} */ + #endif /* HAL_NOR_MODULE_ENABLED */ /** * @} */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* FMC_BANK1 */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp.c index 869e57748d..e2faf39655 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp.c @@ -110,6 +110,23 @@ (++) Configure the OPAMP input AND output in analog mode using HAL_GPIO_Init() to map the OPAMP output to the GPIO pin. + (#) Registrate Callbacks + (++) The compilation define USE_HAL_OPAMP_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + (++) Use Functions @ref HAL_OPAMP_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+++) MspInitCallback : OPAMP MspInit. + (+++) MspDeInitCallback : OPAMP MspFeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + (++) Use function @ref HAL_OPAMP_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+++) MspInitCallback : OPAMP MspInit. + (+++) MspDeInitCallback : OPAMP MspdeInit. + (+++) All Callbacks + (#) Configure the OPAMP using HAL_OPAMP_Init() function: (++) Select the mode (++) Select the inverting input @@ -299,6 +316,16 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp) assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode)); assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput)); + if(hopamp->State == HAL_OPAMP_STATE_RESET) + { +#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) + if(hopamp->MspInitCallback == NULL) + { + hopamp->MspInitCallback = HAL_OPAMP_MspInit; + } +#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ + } + if ((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE) { assert_param(IS_OPAMP_INVERTING_INPUT_STANDALONE(hopamp->Init.InvertingInput)); @@ -335,8 +362,12 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp) hopamp->Lock = HAL_UNLOCKED; } +#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) + hopamp->MspInitCallback(hopamp); +#else /* Call MSP init function */ HAL_OPAMP_MspInit(hopamp); +#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ /* Set operating mode */ CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALON); @@ -440,20 +471,26 @@ HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp) CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN); MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_RESET_BITS, OPAMP_CSR_RESET_VALUE); +#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) + if(hopamp->MspDeInitCallback == NULL) + { + hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit; + } + /* DeInit the low level hardware */ + hopamp->MspDeInitCallback(hopamp); +#else /* DeInit the low level hardware: GPIO, CLOCK and NVIC */ HAL_OPAMP_MspDeInit(hopamp); - +#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ /* Update the OPAMP state*/ hopamp->State = HAL_OPAMP_STATE_RESET; /* Process unlocked */ __HAL_UNLOCK(hopamp); } - return status; } - /** * @brief Initialize the OPAMP MSP. * @param hopamp: OPAMP handle @@ -972,6 +1009,142 @@ HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp) * @} */ +#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User OPAMP Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hopamp : OPAMP handle + * @param CallbackID : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_OPAMP_MSP_INIT_CB_ID OPAMP MspInit callback ID + * @arg @ref HAL_OPAMP_MSP_DEINIT_CB_ID OPAMP MspDeInit callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackID, pOPAMP_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hopamp); + + if(hopamp->State == HAL_OPAMP_STATE_READY) + { + switch (CallbackID) + { + case HAL_OPAMP_MSP_INIT_CB_ID : + hopamp->MspInitCallback = pCallback; + break; + case HAL_OPAMP_MSP_DEINIT_CB_ID : + hopamp->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hopamp->State == HAL_OPAMP_STATE_RESET) + { + switch (CallbackID) + { + case HAL_OPAMP_MSP_INIT_CB_ID : + hopamp->MspInitCallback = pCallback; + break; + case HAL_OPAMP_MSP_DEINIT_CB_ID : + hopamp->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hopamp); + return status; +} + +/** + * @brief Unregister a User OPAMP Callback + * OPAMP Callback is redirected to the weak (surcharged) predefined callback + * @param hopamp : OPAMP handle + * @param CallbackID : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_OPAMP_MSP_INIT_CB_ID OPAMP MSP Init Callback ID + * @arg @ref HAL_OPAMP_MSP_DEINIT_CB_ID OPAMP MSP DeInit Callback ID + * @arg @ref HAL_OPAMP_ALL_CB_ID OPAMP All Callbacks + * @retval status + */ + +HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hopamp); + + if(hopamp->State == HAL_OPAMP_STATE_READY) + { + switch (CallbackID) + { + case HAL_OPAMP_MSP_INIT_CB_ID : + hopamp->MspInitCallback = HAL_OPAMP_MspInit; + break; + case HAL_OPAMP_MSP_DEINIT_CB_ID : + hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit; + break; + case HAL_OPAMP_ALL_CB_ID : + hopamp->MspInitCallback = HAL_OPAMP_MspInit; + hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hopamp->State == HAL_OPAMP_STATE_RESET) + { + switch (CallbackID) + { + case HAL_OPAMP_MSP_INIT_CB_ID : + hopamp->MspInitCallback = HAL_OPAMP_MspInit; + break; + case HAL_OPAMP_MSP_DEINIT_CB_ID : + hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hopamp); + return status; +} + +#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ + + /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ospi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ospi.c index f51273c648..5a082932ff 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ospi.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ospi.c @@ -138,6 +138,65 @@ [..] (#) HAL_OSPIM_Config() function configures the IO manager for the OctoSPI instance. + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions @ref HAL_OSPI_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) FifoThresholdCallback : callback when the fifo threshold is reached. + (+) CmdCpltCallback : callback when a command without data is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxHalfCpltCallback : callback when half of the reception transfer is completed. + (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed. + (+) StatusMatchCallback : callback when a status match occurs. + (+) TimeOutCallback : callback when the timeout perioed expires. + (+) MspInitCallback : OSPI MspInit. + (+) MspDeInitCallback : OSPI MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_OSPI_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) FifoThresholdCallback : callback when the fifo threshold is reached. + (+) CmdCpltCallback : callback when a command without data is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxHalfCpltCallback : callback when half of the reception transfer is completed. + (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed. + (+) StatusMatchCallback : callback when a status match occurs. + (+) TimeOutCallback : callback when the timeout perioed expires. + (+) MspInitCallback : OSPI MspInit. + (+) MspDeInitCallback : OSPI MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the @ref HAL_OSPI_Init and if the state is HAL_OSPI_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_OSPI_Init + and @ref HAL_OSPI_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_OSPI_Init and @ref HAL_OSPI_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_OSPI_RegisterCallback before calling @ref HAL_OSPI_DeInit + or @ref HAL_OSPI_Init function. + + When The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + @endverbatim ****************************************************************************** * @attention @@ -283,8 +342,30 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi) /* Check if the state is the reset state */ if (hospi->State == HAL_OSPI_STATE_RESET) { +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) + /* Reset Callback pointers in HAL_OSPI_STATE_RESET only */ + hospi->ErrorCallback = HAL_OSPI_ErrorCallback; + hospi->AbortCpltCallback = HAL_OSPI_AbortCpltCallback; + hospi->FifoThresholdCallback = HAL_OSPI_FifoThresholdCallback; + hospi->CmdCpltCallback = HAL_OSPI_CmdCpltCallback; + hospi->RxCpltCallback = HAL_OSPI_RxCpltCallback; + hospi->TxCpltCallback = HAL_OSPI_TxCpltCallback; + hospi->RxHalfCpltCallback = HAL_OSPI_RxHalfCpltCallback; + hospi->TxHalfCpltCallback = HAL_OSPI_TxHalfCpltCallback; + hospi->StatusMatchCallback = HAL_OSPI_StatusMatchCallback; + hospi->TimeOutCallback = HAL_OSPI_TimeOutCallback; + + if(hospi->MspInitCallback == NULL) + { + hospi->MspInitCallback = HAL_OSPI_MspInit; + } + + /* Init the low level hardware */ + hospi->MspInitCallback(hospi); +#else /* Initialization of the low level hardware */ HAL_OSPI_MspInit(hospi); +#endif /* Configure the default timeout for the OSPI memory access */ status = HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE); @@ -294,8 +375,8 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi) { /* Configure memory type, device size, chip select high time, free running clock, clock mode */ MODIFY_REG(hospi->Instance->DCR1, (OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_FRCK | OCTOSPI_DCR1_CKMODE), - (hospi->Init.MemoryType | ((hospi->Init.DeviceSize - 1) << OCTOSPI_DCR1_DEVSIZE_Pos) | - ((hospi->Init.ChipSelectHighTime - 1) << OCTOSPI_DCR1_CSHT_Pos) | hospi->Init.FreeRunningClock | + (hospi->Init.MemoryType | ((hospi->Init.DeviceSize - 1U) << OCTOSPI_DCR1_DEVSIZE_Pos) | + ((hospi->Init.ChipSelectHighTime - 1U) << OCTOSPI_DCR1_CSHT_Pos) | hospi->Init.FreeRunningClock | hospi->Init.ClockMode)); /* Configure wrap size */ @@ -306,7 +387,7 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi) /* Configure FIFO threshold */ - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1) << OCTOSPI_CR_FTHRES_Pos)); + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1U) << OCTOSPI_CR_FTHRES_Pos)); /* Wait till busy flag is reset */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); @@ -314,7 +395,7 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi) if (status == HAL_OK) { /* Configure clock prescaler */ - MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, ((hospi->Init.ClockPrescaler - 1) << OCTOSPI_DCR2_PRESCALER_Pos)); + MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos)); /* Configure Dual Quad mode */ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad); @@ -377,8 +458,18 @@ HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi) /* Disable OctoSPI */ __HAL_OSPI_DISABLE(hospi); +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) + if(hospi->MspDeInitCallback == NULL) + { + hospi->MspDeInitCallback = HAL_OSPI_MspDeInit; + } + + /* DeInit the low level hardware */ + hospi->MspDeInitCallback(hospi); +#else /* De-initialize the low-level hardware */ HAL_OSPI_MspDeInit(hospi); +#endif /* Reset the driver state */ hospi->State = HAL_OSPI_STATE_RESET; @@ -440,22 +531,28 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) uint32_t currentstate = hospi->State; /* OctoSPI fifo threshold interrupt occurred -------------------------------*/ - if (((flag & HAL_OSPI_FLAG_FT) != 0) && ((itsource & HAL_OSPI_IT_FT) != 0)) + if (((flag & HAL_OSPI_FLAG_FT) != 0U) && ((itsource & HAL_OSPI_IT_FT) != 0U)) { if (currentstate == HAL_OSPI_STATE_BUSY_TX) { /* Write a data in the fifo */ - *(__IO uint8_t *)((__IO void *)data_reg) = *hospi->pBuffPtr++; + *((__IO uint8_t *)data_reg) = *hospi->pBuffPtr; + hospi->pBuffPtr++; hospi->XferCount--; } else if (currentstate == HAL_OSPI_STATE_BUSY_RX) { /* Read a data from the fifo */ - *hospi->pBuffPtr++ = *(__IO uint8_t *)((__IO void *)data_reg); + *hospi->pBuffPtr = *((__IO uint8_t *)data_reg); + hospi->pBuffPtr++; hospi->XferCount--; } + else + { + /* Nothing to do */ + } - if (hospi->XferCount == 0) + if (hospi->XferCount == 0U) { /* All data have been received or transmitted for the transfer */ /* Disable fifo threshold interrupt */ @@ -463,20 +560,25 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) } /* Fifo threshold callback */ +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) + hospi->FifoThresholdCallback(hospi); +#else HAL_OSPI_FifoThresholdCallback(hospi); +#endif } /* OctoSPI transfer complete interrupt occurred ----------------------------*/ - else if (((flag & HAL_OSPI_FLAG_TC) != 0) && ((itsource & HAL_OSPI_IT_TC) != 0)) + else if (((flag & HAL_OSPI_FLAG_TC) != 0U) && ((itsource & HAL_OSPI_IT_TC) != 0U)) { if (currentstate == HAL_OSPI_STATE_BUSY_RX) { - if (((flag & OCTOSPI_SR_FLEVEL) != 0) && (hospi->XferCount > 0)) + if ((hospi->XferCount > 0U) && ((flag & OCTOSPI_SR_FLEVEL) != 0U)) { /* Read the last data received in the fifo */ - *hospi->pBuffPtr++ = *(__IO uint8_t *)((__IO void*)data_reg); + *hospi->pBuffPtr = *((__IO uint8_t *)data_reg); + hospi->pBuffPtr++; hospi->XferCount--; } - else if(hospi->XferCount == 0) + else if(hospi->XferCount == 0U) { /* Clear flag */ hospi->Instance->FCR = HAL_OSPI_FLAG_TC; @@ -488,7 +590,15 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) hospi->State = HAL_OSPI_STATE_READY; /* RX complete callback */ +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) + hospi->RxCpltCallback(hospi); +#else HAL_OSPI_RxCpltCallback(hospi); +#endif + } + else + { + /* Nothing to do */ } } else @@ -505,12 +615,20 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) if (currentstate == HAL_OSPI_STATE_BUSY_TX) { /* TX complete callback */ +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) + hospi->TxCpltCallback(hospi); +#else HAL_OSPI_TxCpltCallback(hospi); +#endif } else if (currentstate == HAL_OSPI_STATE_BUSY_CMD) { /* Command complete callback */ +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) + hospi->CmdCpltCallback(hospi); +#else HAL_OSPI_CmdCpltCallback(hospi); +#endif } else if (currentstate == HAL_OSPI_STATE_ABORT) { @@ -518,25 +636,37 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) { /* Abort called by the user */ /* Abort complete callback */ +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) + hospi->AbortCpltCallback(hospi); +#else HAL_OSPI_AbortCpltCallback(hospi); +#endif } else { /* Abort due to an error (eg : DMA error) */ /* Error callback */ +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) + hospi->ErrorCallback(hospi); +#else HAL_OSPI_ErrorCallback(hospi); +#endif } } + else + { + /* Nothing to do */ + } } } /* OctoSPI status match interrupt occurred ---------------------------------*/ - else if (((flag & HAL_OSPI_FLAG_SM) != 0) && ((itsource & HAL_OSPI_IT_SM) != 0)) + else if (((flag & HAL_OSPI_FLAG_SM) != 0U) && ((itsource & HAL_OSPI_IT_SM) != 0U)) { /* Clear flag */ hospi->Instance->FCR = HAL_OSPI_FLAG_SM; /* Check if automatic poll mode stop is activated */ - if ((hospi->Instance->CR & OCTOSPI_CR_APMS) != 0) + if ((hospi->Instance->CR & OCTOSPI_CR_APMS) != 0U) { /* Disable the interrupts */ __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_SM | HAL_OSPI_IT_TE); @@ -546,10 +676,14 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) } /* Status match callback */ +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) + hospi->StatusMatchCallback(hospi); +#else HAL_OSPI_StatusMatchCallback(hospi); +#endif } /* OctoSPI transfer error interrupt occurred -------------------------------*/ - else if (((flag & HAL_OSPI_FLAG_TE) != 0) && ((itsource & HAL_OSPI_IT_TE) != 0)) + else if (((flag & HAL_OSPI_FLAG_TE) != 0U) && ((itsource & HAL_OSPI_IT_TE) != 0U)) { /* Clear flag */ hospi->Instance->FCR = HAL_OSPI_FLAG_TE; @@ -561,14 +695,25 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) hospi->ErrorCode = HAL_OSPI_ERROR_TRANSFER; /* Check if the DMA is enabled */ - if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0) + if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer on the OctoSPI side */ CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); /* Disable the DMA transfer on the DMA side */ hospi->hdma->XferAbortCallback = OSPI_DMAAbortCplt; - HAL_DMA_Abort_IT(hospi->hdma); + if (HAL_DMA_Abort_IT(hospi->hdma) != HAL_OK) + { + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + + /* Error callback */ +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) + hospi->ErrorCallback(hospi); +#else + HAL_OSPI_ErrorCallback(hospi); +#endif + } } else { @@ -576,17 +721,29 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) hospi->State = HAL_OSPI_STATE_READY; /* Error callback */ +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) + hospi->ErrorCallback(hospi); +#else HAL_OSPI_ErrorCallback(hospi); +#endif } } /* OctoSPI timeout interrupt occurred --------------------------------------*/ - else if (((flag & HAL_OSPI_FLAG_TO) != 0) && ((itsource & HAL_OSPI_IT_TO) != 0)) + else if (((flag & HAL_OSPI_FLAG_TO) != 0U) && ((itsource & HAL_OSPI_IT_TO) != 0U)) { /* Clear flag */ hospi->Instance->FCR = HAL_OSPI_FLAG_TO; /* Timeout callback */ +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) + hospi->TimeOutCallback(hospi); +#else HAL_OSPI_TimeOutCallback(hospi); +#endif + } + else + { + /* Nothing to do */ } } @@ -599,7 +756,8 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) */ HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; + uint32_t state; uint32_t tickstart = HAL_GetTick(); /* Check the parameters of the command structure */ @@ -646,9 +804,10 @@ HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTyp assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode)); /* Check the state of the driver */ - if (((hospi->State == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) || - ((hospi->State == HAL_OSPI_STATE_READ_CMD_CFG) && (cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)) || - ((hospi->State == HAL_OSPI_STATE_WRITE_CMD_CFG) && (cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG))) + state = hospi->State; + if (((state == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) || + ((state == HAL_OSPI_STATE_READ_CMD_CFG) && (cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)) || + ((state == HAL_OSPI_STATE_WRITE_CMD_CFG) && (cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG))) { /* Wait till busy flag is reset */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); @@ -723,7 +882,7 @@ HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTyp */ HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); /* Check the parameters of the command structure */ @@ -813,7 +972,8 @@ HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmd */ HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; + uint32_t state; uint32_t tickstart = HAL_GetTick(); /* Check the parameters of the hyperbus configuration structure */ @@ -823,7 +983,8 @@ HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusC assert_param(IS_OSPI_LATENCY_MODE (cfg->LatencyMode)); /* Check the state of the driver */ - if ((hospi->State == HAL_OSPI_STATE_HYPERBUS_INIT) || (hospi->State == HAL_OSPI_STATE_READY)) + state = hospi->State; + if ((state == HAL_OSPI_STATE_HYPERBUS_INIT) || (state == HAL_OSPI_STATE_READY)) { /* Wait till busy flag is reset */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); @@ -858,7 +1019,7 @@ HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusC */ HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); /* Check the parameters of the hyperbus command structure */ @@ -876,7 +1037,7 @@ HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusC if (status == HAL_OK) { /* Re-initialize the value of the functional mode */ - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0); + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0U); /* Configure the address space in the DCR1 register */ MODIFY_REG(hospi->Instance->DCR1, OCTOSPI_DCR1_MTYP_0, cmd->AddressSpace); @@ -891,7 +1052,7 @@ HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusC cmd->AddressSize | OCTOSPI_WCCR_ADDTR | OCTOSPI_WCCR_ADMODE_2)); /* Configure the DLR register with the number of data */ - WRITE_REG(hospi->Instance->DLR, (cmd->NbData - 1)); + WRITE_REG(hospi->Instance->DLR, (cmd->NbData - 1U)); /* Configure the AR register with the address value */ WRITE_REG(hospi->Instance->AR, cmd->Address); @@ -920,7 +1081,7 @@ HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusC */ HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); __IO uint32_t *data_reg = &hospi->Instance->DR; @@ -936,7 +1097,7 @@ HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, u if (hospi->State == HAL_OSPI_STATE_CMD_CFG) { /* Configure counters and size */ - hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1; + hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U; hospi->XferSize = hospi->XferCount; hospi->pBuffPtr = pData; @@ -953,9 +1114,10 @@ HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, u break; } - *(__IO uint8_t *)((__IO void *)data_reg) = *hospi->pBuffPtr++; + *((__IO uint8_t *)data_reg) = *hospi->pBuffPtr; + hospi->pBuffPtr++; hospi->XferCount--; - } while (hospi->XferCount > 0); + } while (hospi->XferCount > 0U); if (status == HAL_OK) { @@ -993,7 +1155,7 @@ HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, u */ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); __IO uint32_t *data_reg = &hospi->Instance->DR; uint32_t addr_reg = hospi->Instance->AR; @@ -1011,7 +1173,7 @@ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, ui if (hospi->State == HAL_OSPI_STATE_CMD_CFG) { /* Configure counters and size */ - hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1; + hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U; hospi->XferSize = hospi->XferCount; hospi->pBuffPtr = pData; @@ -1045,9 +1207,10 @@ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, ui break; } - *hospi->pBuffPtr++ = *(__IO uint8_t *)((__IO void *)data_reg); + *hospi->pBuffPtr = *((__IO uint8_t *)data_reg); + hospi->pBuffPtr++; hospi->XferCount--; - } while(hospi->XferCount > 0); + } while(hospi->XferCount > 0U); if (status == HAL_OK) { @@ -1098,7 +1261,7 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData if (hospi->State == HAL_OSPI_STATE_CMD_CFG) { /* Configure counters and size */ - hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1; + hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U; hospi->XferSize = hospi->XferCount; hospi->pBuffPtr = pData; @@ -1150,7 +1313,7 @@ HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData) if (hospi->State == HAL_OSPI_STATE_CMD_CFG) { /* Configure counters and size */ - hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1; + hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U; hospi->XferSize = hospi->XferCount; hospi->pBuffPtr = pData; @@ -1208,8 +1371,7 @@ HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData) HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; - uint32_t *tmp; - uint32_t data_size = hospi->Instance->DLR + 1; + uint32_t data_size = hospi->Instance->DLR + 1U; /* Check the data pointer allocation */ if (pData == NULL) @@ -1229,7 +1391,7 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pDat } else if (hospi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) { - if (((data_size % 2) != 0) || ((hospi->Init.FifoThreshold % 2) != 0)) + if (((data_size % 2U) != 0U) || ((hospi->Init.FifoThreshold % 2U) != 0U)) { /* The number of data or the fifo threshold is not aligned on halfword => no transfer possible with DMA peripheral access configured as halfword */ @@ -1243,7 +1405,7 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pDat } else if (hospi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) { - if (((data_size % 4) != 0) || ((hospi->Init.FifoThreshold % 4) != 0)) + if (((data_size % 4U) != 0U) || ((hospi->Init.FifoThreshold % 4U) != 0U)) { /* The number of data or the fifo threshold is not aligned on word => no transfer possible with DMA peripheral access configured as word */ @@ -1255,6 +1417,10 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pDat hospi->XferCount = (data_size >> 2); } } + else + { + /* Nothing to do */ + } if (status == HAL_OK) { @@ -1287,14 +1453,20 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pDat MODIFY_REG(hospi->hdma->Instance->CCR, DMA_CCR_DIR, hospi->hdma->Init.Direction); /* Enable the transmit DMA Channel */ - tmp = (uint32_t*)((void*)&pData); - HAL_DMA_Start_IT(hospi->hdma, *(uint32_t*)tmp, (uint32_t)&hospi->Instance->DR, hospi->XferSize); + if (HAL_DMA_Start_IT(hospi->hdma, (uint32_t)pData, (uint32_t)&hospi->Instance->DR, hospi->XferSize) == HAL_OK) + { + /* Enable the transfer error interrupt */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE); - /* Enable the transfer error interrupt */ - __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE); - - /* Enable the DMA transfer by setting the DMAEN bit */ - SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); + /* Enable the DMA transfer by setting the DMAEN bit */ + SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_DMA; + hospi->State = HAL_OSPI_STATE_READY; + } } } else @@ -1322,8 +1494,7 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pDat HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; - uint32_t *tmp; - uint32_t data_size = hospi->Instance->DLR + 1; + uint32_t data_size = hospi->Instance->DLR + 1U; uint32_t addr_reg = hospi->Instance->AR; uint32_t ir_reg = hospi->Instance->IR; @@ -1345,7 +1516,7 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData } else if (hospi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) { - if (((data_size % 2) != 0) || ((hospi->Init.FifoThreshold % 2) != 0)) + if (((data_size % 2U) != 0U) || ((hospi->Init.FifoThreshold % 2U) != 0U)) { /* The number of data or the fifo threshold is not aligned on halfword => no transfer possible with DMA peripheral access configured as halfword */ @@ -1359,7 +1530,7 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData } else if (hospi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) { - if (((data_size % 4) != 0) || ((hospi->Init.FifoThreshold % 4) != 0)) + if (((data_size % 4U) != 0U) || ((hospi->Init.FifoThreshold % 4U) != 0U)) { /* The number of data or the fifo threshold is not aligned on word => no transfer possible with DMA peripheral access configured as word */ @@ -1371,6 +1542,10 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData hospi->XferCount = (data_size >> 2); } } + else + { + /* Nothing to do */ + } if (status == HAL_OK) { @@ -1403,31 +1578,37 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData MODIFY_REG(hospi->hdma->Instance->CCR, DMA_CCR_DIR, hospi->hdma->Init.Direction); /* Enable the transmit DMA Channel */ - tmp = (uint32_t*)((void *)&pData); - HAL_DMA_Start_IT(hospi->hdma, (uint32_t)&hospi->Instance->DR, *(uint32_t*)tmp, hospi->XferSize); - - /* Enable the transfer error interrupt */ - __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE); - - /* Trig the transfer by re-writing address or instruction register */ - if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) - { - WRITE_REG(hospi->Instance->AR, addr_reg); - } - else + if (HAL_DMA_Start_IT(hospi->hdma, (uint32_t)&hospi->Instance->DR, (uint32_t)pData, hospi->XferSize) == HAL_OK) { - if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) + /* Enable the transfer error interrupt */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE); + + /* Trig the transfer by re-writing address or instruction register */ + if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) { WRITE_REG(hospi->Instance->AR, addr_reg); } else { - WRITE_REG(hospi->Instance->IR, ir_reg); + if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) + { + WRITE_REG(hospi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hospi->Instance->IR, ir_reg); + } } - } - /* Enable the DMA transfer by setting the DMAEN bit */ - SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); + /* Enable the DMA transfer by setting the DMAEN bit */ + SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_DMA; + hospi->State = HAL_OSPI_STATE_READY; + } } } else @@ -1452,16 +1633,19 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData */ HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); uint32_t addr_reg = hospi->Instance->AR; uint32_t ir_reg = hospi->Instance->IR; +#ifdef USE_FULL_ASSERT + uint32_t dlr_reg = hospi->Instance->DLR; +#endif /* Check the parameters of the autopolling configuration structure */ assert_param(IS_OSPI_MATCH_MODE (cfg->MatchMode)); assert_param(IS_OSPI_AUTOMATIC_STOP (cfg->AutomaticStop)); assert_param(IS_OSPI_INTERVAL (cfg->Interval)); - assert_param(IS_OSPI_STATUS_BYTES_SIZE(hospi->Instance->DLR+1)); + assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg+1U)); /* Check the state */ if ((hospi->State == HAL_OSPI_STATE_CMD_CFG) && (cfg->AutomaticStop == HAL_OSPI_AUTOMATIC_STOP_ENABLE)) @@ -1528,16 +1712,19 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPolli */ HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); uint32_t addr_reg = hospi->Instance->AR; uint32_t ir_reg = hospi->Instance->IR; +#ifdef USE_FULL_ASSERT + uint32_t dlr_reg = hospi->Instance->DLR; +#endif /* Check the parameters of the autopolling configuration structure */ assert_param(IS_OSPI_MATCH_MODE (cfg->MatchMode)); assert_param(IS_OSPI_AUTOMATIC_STOP (cfg->AutomaticStop)); assert_param(IS_OSPI_INTERVAL (cfg->Interval)); - assert_param(IS_OSPI_STATUS_BYTES_SIZE(hospi->Instance->DLR+1)); + assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg+1U)); /* Check the state */ if (hospi->State == HAL_OSPI_STATE_CMD_CFG) @@ -1600,7 +1787,7 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPo */ HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); /* Check the parameters of the memory-mapped configuration structure */ @@ -1796,6 +1983,218 @@ __weak void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi) */ } +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User OSPI Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hospi : OSPI handle + * @param CallbackID : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_OSPI_ERROR_CB_ID OSPI Error Callback ID + * @arg @ref HAL_OSPI_ABORT_CB_ID OSPI Abort Callback ID + * @arg @ref HAL_OSPI_FIFO_THRESHOLD_CB_ID OSPI FIFO Threshold Callback ID + * @arg @ref HAL_OSPI_CMD_CPLT_CB_ID OSPI Command Complete Callback ID + * @arg @ref HAL_OSPI_RX_CPLT_CB_ID OSPI Rx Complete Callback ID + * @arg @ref HAL_OSPI_TX_CPLT_CB_ID OSPI Tx Complete Callback ID + * @arg @ref HAL_OSPI_RX_HALF_CPLT_CB_ID OSPI Rx Half Complete Callback ID + * @arg @ref HAL_OSPI_TX_HALF_CPLT_CB_ID OSPI Tx Half Complete Callback ID + * @arg @ref HAL_OSPI_STATUS_MATCH_CB_ID OSPI Status Match Callback ID + * @arg @ref HAL_OSPI_TIMEOUT_CB_ID OSPI Timeout Callback ID + * @arg @ref HAL_OSPI_MSP_INIT_CB_ID OSPI MspInit callback ID + * @arg @ref HAL_OSPI_MSP_DEINIT_CB_ID OSPI MspDeInit callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, pOSPI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if(hospi->State == HAL_OSPI_STATE_READY) + { + switch (CallbackID) + { + case HAL_OSPI_ERROR_CB_ID : + hospi->ErrorCallback = pCallback; + break; + case HAL_OSPI_ABORT_CB_ID : + hospi->AbortCpltCallback = pCallback; + break; + case HAL_OSPI_FIFO_THRESHOLD_CB_ID : + hospi->FifoThresholdCallback = pCallback; + break; + case HAL_OSPI_CMD_CPLT_CB_ID : + hospi->CmdCpltCallback = pCallback; + break; + case HAL_OSPI_RX_CPLT_CB_ID : + hospi->RxCpltCallback = pCallback; + break; + case HAL_OSPI_TX_CPLT_CB_ID : + hospi->TxCpltCallback = pCallback; + break; + case HAL_OSPI_RX_HALF_CPLT_CB_ID : + hospi->RxHalfCpltCallback = pCallback; + break; + case HAL_OSPI_TX_HALF_CPLT_CB_ID : + hospi->TxHalfCpltCallback = pCallback; + break; + case HAL_OSPI_STATUS_MATCH_CB_ID : + hospi->StatusMatchCallback = pCallback; + break; + case HAL_OSPI_TIMEOUT_CB_ID : + hospi->TimeOutCallback = pCallback; + break; + case HAL_OSPI_MSP_INIT_CB_ID : + hospi->MspInitCallback = pCallback; + break; + case HAL_OSPI_MSP_DEINIT_CB_ID : + hospi->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hospi->State == HAL_OSPI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_OSPI_MSP_INIT_CB_ID : + hospi->MspInitCallback = pCallback; + break; + case HAL_OSPI_MSP_DEINIT_CB_ID : + hospi->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a User OSPI Callback + * OSPI Callback is redirected to the weak (surcharged) predefined callback + * @param hospi : OSPI handle + * @param CallbackID : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_OSPI_ERROR_CB_ID OSPI Error Callback ID + * @arg @ref HAL_OSPI_ABORT_CB_ID OSPI Abort Callback ID + * @arg @ref HAL_OSPI_FIFO_THRESHOLD_CB_ID OSPI FIFO Threshold Callback ID + * @arg @ref HAL_OSPI_CMD_CPLT_CB_ID OSPI Command Complete Callback ID + * @arg @ref HAL_OSPI_RX_CPLT_CB_ID OSPI Rx Complete Callback ID + * @arg @ref HAL_OSPI_TX_CPLT_CB_ID OSPI Tx Complete Callback ID + * @arg @ref HAL_OSPI_RX_HALF_CPLT_CB_ID OSPI Rx Half Complete Callback ID + * @arg @ref HAL_OSPI_TX_HALF_CPLT_CB_ID OSPI Tx Half Complete Callback ID + * @arg @ref HAL_OSPI_STATUS_MATCH_CB_ID OSPI Status Match Callback ID + * @arg @ref HAL_OSPI_TIMEOUT_CB_ID OSPI Timeout Callback ID + * @arg @ref HAL_OSPI_MSP_INIT_CB_ID OSPI MspInit callback ID + * @arg @ref HAL_OSPI_MSP_DEINIT_CB_ID OSPI MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(hospi->State == HAL_OSPI_STATE_READY) + { + switch (CallbackID) + { + case HAL_OSPI_ERROR_CB_ID : + hospi->ErrorCallback = HAL_OSPI_ErrorCallback; + break; + case HAL_OSPI_ABORT_CB_ID : + hospi->AbortCpltCallback = HAL_OSPI_AbortCpltCallback; + break; + case HAL_OSPI_FIFO_THRESHOLD_CB_ID : + hospi->FifoThresholdCallback = HAL_OSPI_FifoThresholdCallback; + break; + case HAL_OSPI_CMD_CPLT_CB_ID : + hospi->CmdCpltCallback = HAL_OSPI_CmdCpltCallback; + break; + case HAL_OSPI_RX_CPLT_CB_ID : + hospi->RxCpltCallback = HAL_OSPI_RxCpltCallback; + break; + case HAL_OSPI_TX_CPLT_CB_ID : + hospi->TxCpltCallback = HAL_OSPI_TxCpltCallback; + break; + case HAL_OSPI_RX_HALF_CPLT_CB_ID : + hospi->RxHalfCpltCallback = HAL_OSPI_RxHalfCpltCallback; + break; + case HAL_OSPI_TX_HALF_CPLT_CB_ID : + hospi->TxHalfCpltCallback = HAL_OSPI_TxHalfCpltCallback; + break; + case HAL_OSPI_STATUS_MATCH_CB_ID : + hospi->StatusMatchCallback = HAL_OSPI_StatusMatchCallback; + break; + case HAL_OSPI_TIMEOUT_CB_ID : + hospi->TimeOutCallback = HAL_OSPI_TimeOutCallback; + break; + case HAL_OSPI_MSP_INIT_CB_ID : + hospi->MspInitCallback = HAL_OSPI_MspInit; + break; + case HAL_OSPI_MSP_DEINIT_CB_ID : + hospi->MspDeInitCallback = HAL_OSPI_MspDeInit; + break; + default : + /* Update the error code */ + hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hospi->State == HAL_OSPI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_OSPI_MSP_INIT_CB_ID : + hospi->MspInitCallback = HAL_OSPI_MspInit; + break; + case HAL_OSPI_MSP_DEINIT_CB_ID : + hospi->MspDeInitCallback = HAL_OSPI_MspDeInit; + break; + default : + /* Update the error code */ + hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} +#endif + /** * @} */ @@ -1827,13 +2226,15 @@ __weak void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi) HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi) { HAL_StatusTypeDef status = HAL_OK; + uint32_t state; uint32_t tickstart = HAL_GetTick(); /* Check if the state is in one of the busy or configured states */ - if (((hospi->State & OSPI_BUSY_STATE_MASK) != 0) || ((hospi->State & OSPI_CFG_STATE_MASK) != 0)) + state = hospi->State; + if (((state & OSPI_BUSY_STATE_MASK) != 0U) || ((state & OSPI_CFG_STATE_MASK) != 0U)) { /* Check if the DMA is enabled */ - if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0) + if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer on the OctoSPI side */ CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); @@ -1846,26 +2247,34 @@ HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi) } } - /* Perform an abort of the OctoSPI */ - SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); - - /* Wait until the transfer complete flag is set to go back in idle state */ - status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, hospi->Timeout); - - if (status == HAL_OK) + if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET) { - /* Clear transfer complete flag */ - __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); - - /* Wait until the busy flag is reset to go back in idle state */ - status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); - + /* Perform an abort of the OctoSPI */ + SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); + + /* Wait until the transfer complete flag is set to go back in idle state */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, hospi->Timeout); + if (status == HAL_OK) { - /* Update state */ - hospi->State = HAL_OSPI_STATE_READY; + /* Clear transfer complete flag */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); + + /* Wait until the busy flag is reset to go back in idle state */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); + + if (status == HAL_OK) + { + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + } } } + else + { + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + } } else { @@ -1885,9 +2294,11 @@ HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi) HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi) { HAL_StatusTypeDef status = HAL_OK; + uint32_t state; /* Check if the state is in one of the busy or configured states */ - if (((hospi->State & OSPI_BUSY_STATE_MASK) != 0) || ((hospi->State & OSPI_CFG_STATE_MASK) != 0)) + state = hospi->State; + if (((state & OSPI_BUSY_STATE_MASK) != 0U) || ((state & OSPI_CFG_STATE_MASK) != 0U)) { /* Disable all interrupts */ __HAL_OSPI_DISABLE_IT(hospi, (HAL_OSPI_IT_TO | HAL_OSPI_IT_SM | HAL_OSPI_IT_FT | HAL_OSPI_IT_TC | HAL_OSPI_IT_TE)); @@ -1896,25 +2307,51 @@ HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi) hospi->State = HAL_OSPI_STATE_ABORT; /* Check if the DMA is enabled */ - if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0) + if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer on the OctoSPI side */ CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); /* Disable the DMA transfer on the DMA side */ hospi->hdma->XferAbortCallback = OSPI_DMAAbortCplt; - HAL_DMA_Abort_IT(hospi->hdma); + if (HAL_DMA_Abort_IT(hospi->hdma) != HAL_OK) + { + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + + /* Abort callback */ +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) + hospi->AbortCpltCallback(hospi); +#else + HAL_OSPI_AbortCpltCallback(hospi); +#endif + } } else { - /* Clear transfer complete flag */ - __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); - - /* Enable the transfer complete interrupts */ - __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC); + if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET) + { + /* Clear transfer complete flag */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); + + /* Enable the transfer complete interrupts */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC); + + /* Perform an abort of the OctoSPI */ + SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); + } + else + { + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; - /* Perform an abort of the OctoSPI */ - SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); + /* Abort callback */ +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) + hospi->AbortCpltCallback(hospi); +#else + HAL_OSPI_AbortCpltCallback(hospi); +#endif + } } } else @@ -1937,13 +2374,13 @@ HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t HAL_StatusTypeDef status = HAL_OK; /* Check the state */ - if ((hospi->State & OSPI_BUSY_STATE_MASK) == 0) + if ((hospi->State & OSPI_BUSY_STATE_MASK) == 0U) { /* Synchronize initialization structure with the new fifo threshold value */ hospi->Init.FifoThreshold = Threshold; /* Configure new fifo threshold */ - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold-1) << OCTOSPI_CR_FTHRES_Pos)); + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold-1U) << OCTOSPI_CR_FTHRES_Pos)); } else @@ -1962,7 +2399,7 @@ HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t */ uint32_t HAL_OSPI_GetFifoThreshold(OSPI_HandleTypeDef *hospi) { - return ((READ_BIT(hospi->Instance->CR, OCTOSPI_CR_FTHRES) >> OCTOSPI_CR_FTHRES_Pos) + 1); + return ((READ_BIT(hospi->Instance->CR, OCTOSPI_CR_FTHRES) >> OCTOSPI_CR_FTHRES_Pos) + 1U); } /** @brief Set OSPI timeout. @@ -2026,10 +2463,13 @@ uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi) HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout) { HAL_StatusTypeDef status = HAL_OK; - uint32_t instance = 0; - uint8_t index = 0, ospi_enabled = 0, other_instance = 0; + uint32_t instance = 0U; + uint8_t index = 0U, ospi_enabled = 0U, other_instance = 0U; OSPIM_CfgTypeDef IOM_cfg[OSPI_NB_INSTANCE]; + /* Prevent unused argument(s) compilation warning */ + UNUSED(Timeout); + /* Check the parameters of the OctoSPI IO Manager configuration structure */ assert_param(IS_OSPIM_PORT(cfg->ClkPort)); assert_param(IS_OSPIM_PORT(cfg->DQSPort)); @@ -2039,19 +2479,19 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * if (hospi->Instance == OCTOSPI1) { - instance = 0; - other_instance = 1; + instance = 0U; + other_instance = 1U; } else { - instance = 1; - other_instance = 0; + instance = 1U; + other_instance = 0U; } /**************** Get current configuration of the instances ****************/ - for (index = 0; index < OSPI_NB_INSTANCE; index++) + for (index = 0U; index < OSPI_NB_INSTANCE; index++) { - if (OSPIM_GetConfig(index+1, &(IOM_cfg[index])) != HAL_OK) + if (OSPIM_GetConfig(index+1U, &(IOM_cfg[index])) != HAL_OK) { status = HAL_ERROR; hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; @@ -2064,22 +2504,22 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * if ((OCTOSPI1->CR & OCTOSPI_CR_EN) != 0) { CLEAR_BIT(OCTOSPI1->CR, OCTOSPI_CR_EN); - ospi_enabled |= 0x1; + ospi_enabled |= 0x1U; } if ((OCTOSPI2->CR & OCTOSPI_CR_EN) != 0) { CLEAR_BIT(OCTOSPI2->CR, OCTOSPI_CR_EN); - ospi_enabled |= 0x2; + ospi_enabled |= 0x2U; } /***************** Deactivation of previous configuration *****************/ if (IOM_cfg[instance].ClkPort != 0) { - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1)], OCTOSPIM_PCR_CLKEN); - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1)], OCTOSPIM_PCR_DQSEN); - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort-1)], OCTOSPIM_PCR_NCSEN); - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort&0xF)-1)], OCTOSPIM_PCR_IOLEN); - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort&0xF)-1)], OCTOSPIM_PCR_IOHEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort&0xFU)-1U)], OCTOSPIM_PCR_IOLEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort&0xFU)-1U)], OCTOSPIM_PCR_IOHEN); } /********************* Deactivation of other instance *********************/ @@ -2087,45 +2527,45 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) { - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1)], OCTOSPIM_PCR_CLKEN); - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1)], OCTOSPIM_PCR_DQSEN); - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1)], OCTOSPIM_PCR_NCSEN); - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort&0xF)-1)], OCTOSPIM_PCR_IOLEN); - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort&0xF)-1)], OCTOSPIM_PCR_IOHEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort&0xFU)-1U)], OCTOSPIM_PCR_IOLEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort&0xFU)-1U)], OCTOSPIM_PCR_IOHEN); } /******************** Activation of new configuration *********************/ - MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos))); - MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos))); - MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort-1)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC), (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos))); + MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos))); + MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos))); + MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort-1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC), (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos))); - if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0) + if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U) { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort&0xF)-1)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort&0xFU)-1U)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | (instance << POSITION_VAL(OCTOSPIM_PCR_IOLSRC_1)))); } else { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort&0xF)-1)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort&0xF)-1U)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | (instance << POSITION_VAL(OCTOSPIM_PCR_IOHSRC_1)))); } - if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0) + if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U) { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort&0xF)-1)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort&0xF)-1U)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << POSITION_VAL(OCTOSPIM_PCR_IOLSRC_1)))); } else { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort&0xF)-1)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort&0xF)-1U)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << POSITION_VAL(OCTOSPIM_PCR_IOHSRC_1)))); } /******* Re-enable both OctoSPI after configure OctoSPI IO Manager ********/ - if ((ospi_enabled & 0x1) != 0) + if ((ospi_enabled & 0x1U) != 0U) { SET_BIT(OCTOSPI1->CR, OCTOSPI_CR_EN); } - if ((ospi_enabled & 0x2) != 0) + if ((ospi_enabled & 0x2U) != 0U) { SET_BIT(OCTOSPI2->CR, OCTOSPI_CR_EN); } @@ -2149,7 +2589,7 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * */ static void OSPI_DMACplt(DMA_HandleTypeDef *hdma) { - OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hdma->Parent); hospi->XferCount = 0; /* Disable the DMA transfer on the OctoSPI side */ @@ -2169,16 +2609,24 @@ static void OSPI_DMACplt(DMA_HandleTypeDef *hdma) */ static void OSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma) { - OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hdma->Parent); hospi->XferCount = (hospi->XferCount >> 1); if (hospi->State == HAL_OSPI_STATE_BUSY_RX) { +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) + hospi->RxHalfCpltCallback(hospi); +#else HAL_OSPI_RxHalfCpltCallback(hospi); +#endif } else { +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) + hospi->TxHalfCpltCallback(hospi); +#else HAL_OSPI_TxHalfCpltCallback(hospi); +#endif } } @@ -2189,7 +2637,7 @@ static void OSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma) */ static void OSPI_DMAError(DMA_HandleTypeDef *hdma) { - OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hdma->Parent); hospi->XferCount = 0; hospi->ErrorCode = HAL_OSPI_ERROR_DMA; @@ -2197,7 +2645,21 @@ static void OSPI_DMAError(DMA_HandleTypeDef *hdma) CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); /* Abort the OctoSPI */ - HAL_OSPI_Abort_IT(hospi); + if (HAL_OSPI_Abort_IT(hospi) != HAL_OK) + { + /* Disable the interrupts */ + __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE); + + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + + /* Error callback */ +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) + hospi->ErrorCallback(hospi); +#else + HAL_OSPI_ErrorCallback(hospi); +#endif + } } /** @@ -2207,21 +2669,36 @@ static void OSPI_DMAError(DMA_HandleTypeDef *hdma) */ static void OSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) { - OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hdma->Parent); hospi->XferCount = 0; /* Check the state */ if (hospi->State == HAL_OSPI_STATE_ABORT) { /* DMA abort called by OctoSPI abort */ - /* Clear transfer complete flag */ - __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); - - /* Enable the transfer complete interrupts */ - __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC); + if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET) + { + /* Clear transfer complete flag */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); + + /* Enable the transfer complete interrupts */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC); + + /* Perform an abort of the OctoSPI */ + SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); + } + else + { + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; - /* Perform an abort of the OctoSPI */ - SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); + /* Abort callback */ +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) + hospi->AbortCpltCallback(hospi); +#else + HAL_OSPI_AbortCpltCallback(hospi); +#endif + } } else { @@ -2230,7 +2707,11 @@ static void OSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) hospi->State = HAL_OSPI_STATE_READY; /* Error callback */ +#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) + hospi->ErrorCallback(hospi); +#else HAL_OSPI_ErrorCallback(hospi); +#endif } } @@ -2252,7 +2733,7 @@ static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hosp /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - Tickstart) > Timeout)) + if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { hospi->State = HAL_OSPI_STATE_ERROR; hospi->ErrorCode |= HAL_OSPI_ERROR_TIMEOUT; @@ -2276,7 +2757,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC __IO uint32_t *ccr_reg, *tcr_reg, *ir_reg, *abr_reg; /* Re-initialize the value of the functional mode */ - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0); + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0U); /* Configure the flash ID */ if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE) @@ -2320,7 +2801,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG) { /* Configure the DLR register with the number of data */ - hospi->Instance->DLR = (cmd->NbData - 1); + hospi->Instance->DLR = (cmd->NbData - 1U); } } @@ -2444,10 +2925,10 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg) { HAL_StatusTypeDef status = HAL_OK; - uint32_t reg = 0, value = 0; - uint32_t index = 0; + uint32_t reg = 0U, value = 0U; + uint32_t index = 0U; - if ((instance_nb == 0) || (instance_nb > OSPI_NB_INSTANCE) || (cfg == NULL)) + if ((instance_nb == 0U) || (instance_nb > OSPI_NB_INSTANCE) || (cfg == NULL)) { /* Invalid parameter -> error returned */ status = HAL_ERROR; @@ -2455,82 +2936,82 @@ static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef * else { /* Initialize the structure */ - cfg->ClkPort = cfg->DQSPort = cfg->NCSPort = cfg->IOLowPort = cfg->IOHighPort = 0; + cfg->ClkPort = cfg->DQSPort = cfg->NCSPort = cfg->IOLowPort = cfg->IOHighPort = 0U; - if (instance_nb == 1) + if (instance_nb == 1U) { - value = 0; + value = 0U; } - else if (instance_nb == 2) + else if (instance_nb == 2U) { value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1); } /* Get the information about the instance */ - for (index = 0; index < OSPI_IOM_NB_PORTS; index ++) + for (index = 0U; index < OSPI_IOM_NB_PORTS; index ++) { reg = OCTOSPIM->PCR[index]; - if ((reg & OCTOSPIM_PCR_CLKEN) != 0) + if ((reg & OCTOSPIM_PCR_CLKEN) != 0U) { /* The clock is enabled on this port */ if ((reg & OCTOSPIM_PCR_CLKSRC) == (value & OCTOSPIM_PCR_CLKSRC)) { /* The clock correspond to the instance passed as parameter */ - cfg->ClkPort = index+1; + cfg->ClkPort = index+1U; } } - if ((reg & OCTOSPIM_PCR_DQSEN) != 0) + if ((reg & OCTOSPIM_PCR_DQSEN) != 0U) { /* The DQS is enabled on this port */ if ((reg & OCTOSPIM_PCR_DQSSRC) == (value & OCTOSPIM_PCR_DQSSRC)) { /* The DQS correspond to the instance passed as parameter */ - cfg->DQSPort = index+1; + cfg->DQSPort = index+1U; } } - if ((reg & OCTOSPIM_PCR_NCSEN) != 0) + if ((reg & OCTOSPIM_PCR_NCSEN) != 0U) { /* The nCS is enabled on this port */ if ((reg & OCTOSPIM_PCR_NCSSRC) == (value & OCTOSPIM_PCR_NCSSRC)) { /* The nCS correspond to the instance passed as parameter */ - cfg->NCSPort = index+1; + cfg->NCSPort = index+1U; } } - if ((reg & OCTOSPIM_PCR_IOLEN) != 0) + if ((reg & OCTOSPIM_PCR_IOLEN) != 0U) { /* The IO Low is enabled on this port */ if ((reg & OCTOSPIM_PCR_IOLSRC_1) == (value & OCTOSPIM_PCR_IOLSRC_1)) { /* The IO Low correspond to the instance passed as parameter */ - if ((reg & OCTOSPIM_PCR_IOLSRC_0) == 0) + if ((reg & OCTOSPIM_PCR_IOLSRC_0) == 0U) { - cfg->IOLowPort = (OCTOSPIM_PCR_IOLEN | (index+1)); + cfg->IOLowPort = (OCTOSPIM_PCR_IOLEN | (index+1U)); } else { - cfg->IOLowPort = (OCTOSPIM_PCR_IOHEN | (index+1)); + cfg->IOLowPort = (OCTOSPIM_PCR_IOHEN | (index+1U)); } } } - if ((reg & OCTOSPIM_PCR_IOHEN) != 0) + if ((reg & OCTOSPIM_PCR_IOHEN) != 0U) { /* The IO High is enabled on this port */ if ((reg & OCTOSPIM_PCR_IOHSRC_1) == (value & OCTOSPIM_PCR_IOHSRC_1)) { /* The IO High correspond to the instance passed as parameter */ - if ((reg & OCTOSPIM_PCR_IOHSRC_0) == 0) + if ((reg & OCTOSPIM_PCR_IOHSRC_0) == 0U) { - cfg->IOHighPort = (OCTOSPIM_PCR_IOLEN | (index+1)); + cfg->IOHighPort = (OCTOSPIM_PCR_IOLEN | (index+1U)); } else { - cfg->IOHighPort = (OCTOSPIM_PCR_IOHEN | (index+1)); + cfg->IOHighPort = (OCTOSPIM_PCR_IOHEN | (index+1U)); } } } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c index 866218b7f8..0d31714d00 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c @@ -3,13 +3,13 @@ * @file stm32l4xx_hal_pcd.c * @author MCD Application Team * @brief PCD HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State functions - * + * @verbatim ============================================================================== ##### How to use this driver ##### @@ -19,18 +19,19 @@ (#) Declare a PCD_HandleTypeDef handle structure, for example: PCD_HandleTypeDef hpcd; - + (#) Fill parameters of Init structure in HCD handle - - (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) + + (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: - (##) Enable the PCD/USB Low Level interface clock using - (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + (##) Enable the PCD/USB Low Level interface clock using + (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device only FS peripheral + (##) Initialize the related GPIO clocks (##) Configure PCD pin-out (##) Configure PCD NVIC interrupt - + (#)Associate the Upper USB device stack to the HAL PCD Driver: (##) hpcd.pData = pdev; @@ -66,7 +67,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -81,22 +82,20 @@ */ #ifdef HAL_PCD_MODULE_ENABLED - -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + +#if defined (USB) || defined (USB_OTG_FS) || defined (USB_OTG_HS) /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** * USB_OTG_CORE VERSION ID */ -#define USB_OTG_CORE_ID_310A 0x4F54310A -#define USB_OTG_CORE_ID_320A 0x4F54320A - +#define USB_OTG_CORE_ID_300A 0x4F54300AU +#define USB_OTG_CORE_ID_310A 0x4F54310AU +#define USB_OTG_CORE_ID_320A 0x4F54320AU +#endif /* USB_OTG_FS || USB_OTG_HS */ /* Private macros ------------------------------------------------------------*/ /** @defgroup PCD_Private_Macros PCD Private Macros * @{ @@ -111,9 +110,10 @@ /** @defgroup PCD_Private_Functions PCD Private Functions * @{ */ -#if defined (USB_OTG_FS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum); -#endif /* USB_OTG_FS */ +#endif /* USB_OTG_FS || USB_OTG_HS */ + #if defined (USB) static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); #endif /* USB */ @@ -126,15 +126,15 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); * @{ */ -/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: - + @endverbatim * @{ */ @@ -142,29 +142,53 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); /** * @brief Initializes the PCD according to the specified * parameters in the PCD_InitTypeDef and initialize the associated handle. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { - uint32_t index = 0U; - + uint8_t i; + /* Check the PCD handle allocation */ - if(hpcd == NULL) + if (hpcd == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); - - if(hpcd->State == HAL_PCD_STATE_RESET) + + if (hpcd->State == HAL_PCD_STATE_RESET) { /* Allocate lock resource and initialize it */ hpcd->Lock = HAL_UNLOCKED; +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SOFCallback = HAL_PCD_SOFCallback; + hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback; + hpcd->ResetCallback = HAL_PCD_ResetCallback; + hpcd->SuspendCallback = HAL_PCD_SuspendCallback; + hpcd->ResumeCallback = HAL_PCD_ResumeCallback; + hpcd->ConnectCallback = HAL_PCD_ConnectCallback; + hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback; + hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; + hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; + hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; + hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; + hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; + hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; + + if (hpcd->MspInitCallback == NULL) + { + hpcd->MspInitCallback = HAL_PCD_MspInit; + } + + /* Init the low level hardware */ + hpcd->MspInitCallback(hpcd); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); +#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ } hpcd->State = HAL_PCD_STATE_BUSY; @@ -173,87 +197,98 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) __HAL_PCD_DISABLE(hpcd); /*Init the Core (common init.) */ - USB_CoreInit(hpcd->Instance, hpcd->Init); + (void)USB_CoreInit(hpcd->Instance, hpcd->Init); /* Force Device Mode*/ - USB_SetCurrentMode(hpcd->Instance , USB_DEVICE_MODE); + (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE); /* Init endpoints structures */ - for (index = 0; index < hpcd->Init.dev_endpoints ; index++) + for (i = 0U; i < 15U; i++) { /* Init ep structure */ - hpcd->IN_ep[index].is_in = 1; - hpcd->IN_ep[index].num = index; - hpcd->IN_ep[index].tx_fifo_num = index; + hpcd->IN_ep[i].is_in = 1U; + hpcd->IN_ep[i].num = i; + hpcd->IN_ep[i].tx_fifo_num = i; /* Control until ep is activated */ - hpcd->IN_ep[index].type = EP_TYPE_CTRL; - hpcd->IN_ep[index].maxpacket = 0; - hpcd->IN_ep[index].xfer_buff = 0; - hpcd->IN_ep[index].xfer_len = 0; + hpcd->IN_ep[i].type = EP_TYPE_CTRL; + hpcd->IN_ep[i].maxpacket = 0U; + hpcd->IN_ep[i].xfer_buff = 0U; + hpcd->IN_ep[i].xfer_len = 0U; } - - for (index = 0; index < 15 ; index++) + + for (i = 0U; i < 15U; i++) { - hpcd->OUT_ep[index].is_in = 0; - hpcd->OUT_ep[index].num = index; - hpcd->IN_ep[index].tx_fifo_num = index; + hpcd->OUT_ep[i].is_in = 0U; + hpcd->OUT_ep[i].num = i; /* Control until ep is activated */ - hpcd->OUT_ep[index].type = EP_TYPE_CTRL; - hpcd->OUT_ep[index].maxpacket = 0; - hpcd->OUT_ep[index].xfer_buff = 0; - hpcd->OUT_ep[index].xfer_len = 0; + hpcd->OUT_ep[i].type = EP_TYPE_CTRL; + hpcd->OUT_ep[i].maxpacket = 0U; + hpcd->OUT_ep[i].xfer_buff = 0U; + hpcd->OUT_ep[i].xfer_len = 0U; } /* Init Device */ - USB_DevInit(hpcd->Instance, hpcd->Init); + (void)USB_DevInit(hpcd->Instance, hpcd->Init); + + hpcd->USB_Address = 0U; + hpcd->State = HAL_PCD_STATE_READY; - hpcd->USB_Address = 0; - - hpcd->State= HAL_PCD_STATE_READY; - - /* Activate LPM */ - if (hpcd->Init.lpm_enable ==1) + /* Activate LPM */ + if (hpcd->Init.lpm_enable == 1U) { - HAL_PCDEx_ActivateLPM(hpcd); - } + (void)HAL_PCDEx_ActivateLPM(hpcd); + } + /* Activate Battery charging */ - if (hpcd->Init.battery_charging_enable ==1) + if (hpcd->Init.battery_charging_enable == 1U) { - HAL_PCDEx_ActivateBCD(hpcd); + (void)HAL_PCDEx_ActivateBCD(hpcd); } - USB_DevDisconnect (hpcd->Instance); + + (void)USB_DevDisconnect(hpcd->Instance); + return HAL_OK; } /** * @brief DeInitializes the PCD peripheral. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) { /* Check the PCD handle allocation */ - if(hpcd == NULL) + if (hpcd == NULL) { return HAL_ERROR; } hpcd->State = HAL_PCD_STATE_BUSY; - + /* Stop Device */ - HAL_PCD_Stop(hpcd); - + (void)HAL_PCD_Stop(hpcd); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + if (hpcd->MspDeInitCallback == NULL) + { + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit */ + } + /* DeInit the low level hardware */ + hpcd->MspDeInitCallback(hpcd); +#else + /* DeInit the low level hardware: CLOCK, NVIC.*/ HAL_PCD_MspDeInit(hpcd); - - hpcd->State = HAL_PCD_STATE_RESET; - +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + hpcd->State = HAL_PCD_STATE_RESET; + return HAL_OK; } /** * @brief Initializes the PCD MSP. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) @@ -268,7 +303,7 @@ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) /** * @brief DeInitializes PCD MSP. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) @@ -281,304 +316,964 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) */ } +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User USB PCD Callback + * To be used instead of the weak predefined callback + * @param hpcd USB PCD handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID + * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID + * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID + * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID + * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID + * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID + * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_PCD_SOF_CB_ID : + hpcd->SOFCallback = pCallback; + break; + + case HAL_PCD_SETUPSTAGE_CB_ID : + hpcd->SetupStageCallback = pCallback; + break; + + case HAL_PCD_RESET_CB_ID : + hpcd->ResetCallback = pCallback; + break; + + case HAL_PCD_SUSPEND_CB_ID : + hpcd->SuspendCallback = pCallback; + break; + + case HAL_PCD_RESUME_CB_ID : + hpcd->ResumeCallback = pCallback; + break; + + case HAL_PCD_CONNECT_CB_ID : + hpcd->ConnectCallback = pCallback; + break; + + case HAL_PCD_DISCONNECT_CB_ID : + hpcd->DisconnectCallback = pCallback; + break; + + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = pCallback; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hpcd->State == HAL_PCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = pCallback; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + return status; +} + +/** + * @brief Unregister an USB PCD Callback + * USB PCD callabck is redirected to the weak predefined callback + * @param hpcd USB PCD handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID + * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID + * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID + * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID + * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID + * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID + * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + /* Setup Legacy weak Callbacks */ + if (hpcd->State == HAL_PCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_PCD_SOF_CB_ID : + hpcd->SOFCallback = HAL_PCD_SOFCallback; + break; + + case HAL_PCD_SETUPSTAGE_CB_ID : + hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback; + break; + + case HAL_PCD_RESET_CB_ID : + hpcd->ResetCallback = HAL_PCD_ResetCallback; + break; + + case HAL_PCD_SUSPEND_CB_ID : + hpcd->SuspendCallback = HAL_PCD_SuspendCallback; + break; + + case HAL_PCD_RESUME_CB_ID : + hpcd->ResumeCallback = HAL_PCD_ResumeCallback; + break; + + case HAL_PCD_CONNECT_CB_ID : + hpcd->ConnectCallback = HAL_PCD_ConnectCallback; + break; + + case HAL_PCD_DISCONNECT_CB_ID : + hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback; + break; + + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = HAL_PCD_MspInit; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hpcd->State == HAL_PCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = HAL_PCD_MspInit; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + return status; +} + +/** + * @brief Register USB PCD Data OUT Stage Callback + * To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Data OUT Stage Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataOutStageCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief UnRegister the USB PCD Data OUT Stage Callback + * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Data IN Stage Callback + * To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Data IN Stage Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataInStageCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief UnRegister the USB PCD Data IN Stage Callback + * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Iso OUT incomplete Callback + * To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOOUTIncompleteCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief UnRegister the USB PCD Iso OUT incomplete Callback + * USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Iso IN incomplete Callback + * To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Iso IN incomplete Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOINIncompleteCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief UnRegister the USB PCD Iso IN incomplete Callback + * USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD BCD Callback + * To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD BCD Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->BCDCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief UnRegister the USB PCD BCD Callback + * USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD LPM Callback + * To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD LPM Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->LPMCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief UnRegister the USB PCD LPM Callback + * USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + /** * @} */ -/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions +/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to manage the PCD data + This subsection provides a set of functions allowing to manage the PCD data transfers. @endverbatim * @{ */ - + /** - * @brief Start The USB OTG Device. - * @param hpcd: PCD handle + * @brief Start the USB device + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - USB_DevConnect (hpcd->Instance); +{ + __HAL_LOCK(hpcd); + (void)USB_DevConnect(hpcd->Instance); __HAL_PCD_ENABLE(hpcd); - __HAL_UNLOCK(hpcd); + __HAL_UNLOCK(hpcd); return HAL_OK; } /** - * @brief Stop The USB OTG Device. - * @param hpcd: PCD handle + * @brief Stop the USB device. + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); +{ + __HAL_LOCK(hpcd); __HAL_PCD_DISABLE(hpcd); - USB_StopDevice(hpcd->Instance); - USB_DevDisconnect (hpcd->Instance); - __HAL_UNLOCK(hpcd); + (void)USB_StopDevice(hpcd->Instance); + (void)USB_DevDisconnect(hpcd->Instance); + __HAL_UNLOCK(hpcd); return HAL_OK; } -#if defined (USB_OTG_FS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** * @brief Handles PCD interrupt request. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - uint32_t index = 0U, ep_intr = 0U, epint = 0U, epnum = 0U; - uint32_t fifoemptymsk = 0U, temp = 0U; - USB_OTG_EPTypeDef *ep = NULL; - uint32_t hclk = 80000000; - + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t TempReg = USBx_BASE + 0x40U; + uint32_t gSNPSiD = *(uint32_t *) TempReg; + uint32_t i, ep_intr, epint, epnum = 0U; + uint32_t fifoemptymsk, temp; + USB_OTG_EPTypeDef *ep; + uint32_t hclk; + /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) { /* avoid spurious interrupt */ - if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) + if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) { return; } - - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) { /* incorrect mode, acknowledge the interrupt */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); } - - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) { - epnum = 0; - + epnum = 0U; + /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); - - while (ep_intr) + + while (ep_intr != 0U) { - if (ep_intr & 0x1) + if ((ep_intr & 0x1U) != 0U) { - epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum); - - if (( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) + epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); + + if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); - /* setup/out transaction management for Core ID 310A */ - if (USBx->GSNPSID == USB_OTG_CORE_ID_310A) + if (gSNPSiD == USB_OTG_CORE_ID_310A) { - if (!(USBx_OUTEP(0)->DOEPINT & (0x1 << 15))) - { - if (hpcd->Init.dma_enable == 1) - { - hpcd->OUT_ep[epnum].xfer_count = - hpcd->OUT_ep[epnum].maxpacket - - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); - - hpcd->OUT_ep[epnum].xfer_buff += - hpcd->OUT_ep[epnum].maxpacket; - } - - HAL_PCD_DataOutStageCallback(hpcd, epnum); - - if (hpcd->Init.dma_enable == 1) - { - if (!epnum && !hpcd->OUT_ep[epnum].xfer_len) - { - /* this is ZLP, so prepare EP0 for next setup */ - USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup); - } - } - } - - /* Clear the SetPktRcvd flag*/ - USBx_OUTEP(0)->DOEPINT |= (0x1 << 15) | (0x1 << 5); - } - else - { - if (hpcd->Init.dma_enable == 1) + if ((USBx_OUTEP(0U)->DOEPINT & (1U << 15)) != 0U) { - hpcd->OUT_ep[epnum].xfer_count = - hpcd->OUT_ep[epnum].maxpacket - - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); - hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket; + CLEAR_OUT_EP_INTR(epnum, (1U << 15)); } - - HAL_PCD_DataOutStageCallback(hpcd, epnum); - - if (hpcd->Init.dma_enable == 1) + else { - if (!epnum && !hpcd->OUT_ep[epnum].xfer_len) - { - /* this is ZLP, so prepare EP0 for next setup */ - USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup); - } +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } } - if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) + if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) { + if (gSNPSiD == USB_OTG_CORE_ID_310A) + { + if ((USBx_OUTEP(0U)->DOEPINT & (1U << 15)) != 0U) + { + CLEAR_OUT_EP_INTR(epnum, (1U << 15)); + } + } /* Inform the upper layer that a setup packet is available */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SetupStageCallback(hpcd); +#else HAL_PCD_SetupStageCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); } - - if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) + + if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); } - -#ifdef USB_OTG_DOEPINT_OTEPSPR + +#ifdef USB_OTG_DOEPINT_OTEPSPR /* Clear Status Phase Received interrupt */ - if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) + if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); } #endif /* USB_OTG_DOEPINT_OTEPSPR */ } epnum++; - ep_intr >>= 1; + ep_intr >>= 1U; } } - - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) { /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); - - epnum = 0; - - while ( ep_intr ) + + epnum = 0U; + + while (ep_intr != 0U) { - if (ep_intr & 0x1) /* In ITR */ + if ((ep_intr & 0x1U) != 0U) /* In ITR */ { - epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum); - - if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) + epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); + + if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) { - fifoemptymsk = 0x1 << epnum; + fifoemptymsk = (uint32_t)(0x1UL << (epnum & 0xFU)); USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; - + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); - - if (hpcd->Init.dma_enable == 1) - { - hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; - } - - HAL_PCD_DataInStageCallback(hpcd, epnum); - - if (hpcd->Init.dma_enable == 1) - { - /* this is ZLP, so prepare EP0 for next setup */ - if((epnum == 0) && (hpcd->IN_ep[epnum].xfer_len == 0)) - { - /* prepare to rx more setup packets */ - USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup); - } - } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) + if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); } - if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) + if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); } - if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) + if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); } - if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) + if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); - } - if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) + } + if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) { - PCD_WriteEmptyTxFifo(hpcd , epnum); + (void)PCD_WriteEmptyTxFifo(hpcd, epnum); } } epnum++; - ep_intr >>= 1; + ep_intr >>= 1U; } } - + /* Handle Resume Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) - { + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) + { /* Clear the Remote Wake-up Signaling */ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; - - if(hpcd->LPM_State == LPM_L1) + + if (hpcd->LPM_State == LPM_L1) { hpcd->LPM_State = LPM_L0; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); +#else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResumeCallback(hpcd); +#else HAL_PCD_ResumeCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); } - + /* Handle Suspend Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) { - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) { - +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); } - - /* Handle LPM Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) + + /* Handle LPM Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); - if( hpcd->LPM_State == LPM_L0) - { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); + + if (hpcd->LPM_State == LPM_L0) + { hpcd->LPM_State = LPM_L1; - hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >>2 ; + hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); +#else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } - + /* Handle Reset Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) { - USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; - USB_FlushTxFifo(hpcd->Instance , 0x10); - - for (index = 0; index < hpcd->Init.dev_endpoints ; index++) + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; + (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); + + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) { - USBx_INEP(index)->DIEPINT = 0xFF; - USBx_OUTEP(index)->DOEPINT = 0xFF; + USBx_INEP(i)->DIEPINT = 0xFB7FU; + USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; } - USBx_DEVICE->DAINT = 0xFFFFFFFF; - USBx_DEVICE->DAINTMSK |= 0x10001; - - if(hpcd->Init.use_dedicated_ep1) + USBx_DEVICE->DAINTMSK |= 0x10001U; + + if (hpcd->Init.use_dedicated_ep1 != 0U) { - USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); - USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); + USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); + USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); } else { @@ -589,292 +1284,331 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) #endif /* USB_OTG_DOEPINT_OTEPSPR */ USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); } - + /* Set Default Address to 0 */ USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; - + /* setup EP0 to receive SETUP packets */ - USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); - + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); } - + /* Handle Enumeration done Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) { - USB_ActivateSetup(hpcd->Instance); + (void)USB_ActivateSetup(hpcd->Instance); hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; - - hpcd->Init.speed = USB_OTG_SPEED_FULL; - hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ; - - /* The USBTRD is configured according to the tables below, depending on AHB frequency - used by application. In the low AHB frequency range it is used to stretch enough the USB response - time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access + hpcd->Init.speed = USB_OTG_SPEED_FULL; + hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE; + + /* The USBTRD is configured according to the tables below, depending on AHB frequency + used by application. In the low AHB frequency range it is used to stretch enough the USB response + time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access latency to the Data FIFO */ - /* Get hclk frequency value */ - hclk = HAL_RCC_GetHCLKFreq(); - - if((hclk >= 14200000)&&(hclk < 15000000)) - { - /* hclk Clock Range between 14.2-15 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xF << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 15000000)&&(hclk < 16000000)) - { - /* hclk Clock Range between 15-16 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xE << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 16000000)&&(hclk < 17200000)) - { - /* hclk Clock Range between 16-17.2 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xD << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 17200000)&&(hclk < 18500000)) - { - /* hclk Clock Range between 17.2-18.5 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xC << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 18500000)&&(hclk < 20000000)) - { - /* hclk Clock Range between 18.5-20 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xB << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 20000000)&&(hclk < 21800000)) - { - /* hclk Clock Range between 20-21.8 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xA << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 21800000)&&(hclk < 24000000)) - { - /* hclk Clock Range between 21.8-24 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x9 << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 24000000)&&(hclk < 27700000)) - { - /* hclk Clock Range between 24-27.7 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x8 << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 27700000)&&(hclk < 32000000)) - { - /* hclk Clock Range between 27.7-32 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x7 << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else /* if(hclk >= 32000000) */ - { - /* hclk Clock Range between 32-80 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x6 << 10) & USB_OTG_GUSBCFG_TRDT); - } - + /* Get hclk frequency value */ + hclk = HAL_RCC_GetHCLKFreq(); + + if ((hclk >= 14200000U) && (hclk < 15000000U)) + { + /* hclk Clock Range between 14.2-15 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0xFU << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if ((hclk >= 15000000U) && (hclk < 16000000U)) + { + /* hclk Clock Range between 15-16 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0xEU << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if ((hclk >= 16000000U) && (hclk < 17200000U)) + { + /* hclk Clock Range between 16-17.2 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0xDU << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if ((hclk >= 17200000U) && (hclk < 18500000U)) + { + /* hclk Clock Range between 17.2-18.5 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0xCU << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if ((hclk >= 18500000U) && (hclk < 20000000U)) + { + /* hclk Clock Range between 18.5-20 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0xBU << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if ((hclk >= 20000000U) && (hclk < 21800000U)) + { + /* hclk Clock Range between 20-21.8 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0xAU << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if ((hclk >= 21800000U) && (hclk < 24000000U)) + { + /* hclk Clock Range between 21.8-24 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0x9U << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if ((hclk >= 24000000U) && (hclk < 27700000U)) + { + /* hclk Clock Range between 24-27.7 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0x8U << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if ((hclk >= 27700000U) && (hclk < 32000000U)) + { + /* hclk Clock Range between 27.7-32 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0x7U << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else /* if(hclk >= 32000000) */ + { + /* hclk Clock Range between 32-200 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0x6U << 10) & USB_OTG_GUSBCFG_TRDT); + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResetCallback(hpcd); +#else HAL_PCD_ResetCallback(hpcd); - +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); } - + /* Handle RxQLevel Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); - + temp = USBx->GRXSTSP; - + ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; - - if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) + + if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) { - if((temp & USB_OTG_GRXSTSP_BCNT) != 0) + if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U) { - USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4); + (void)USB_ReadPacket(USBx, ep->xfer_buff, (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4)); ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; } } else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) { - USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8); + (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; } + else + { + /* ... */ + } USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); } - + /* Handle SOF Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SOFCallback(hpcd); +#else HAL_PCD_SOFCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); } - + /* Handle Incomplete ISO IN Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) { - HAL_PCD_ISOINIncompleteCallback(hpcd, epnum); +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); - } - + } + /* Handle Incomplete ISO OUT Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) { - HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum); +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); - } - + } + /* Handle Connection event Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ConnectCallback(hpcd); +#else HAL_PCD_ConnectCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); - } - + } + /* Handle Disconnection event Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) { temp = hpcd->Instance->GOTGINT; - - if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) + + if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DisconnectCallback(hpcd); +#else HAL_PCD_DisconnectCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } hpcd->Instance->GOTGINT |= temp; } } } - -#endif /* USB_OTG_FS */ +#endif /* USB_OTG_FS || USB_OTG_HS */ #if defined (USB) /** * @brief This function handles PCD interrupt request. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { - uint32_t wInterrupt_Mask = 0; - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_CTR)) { /* servicing of the endpoint correct transfer interrupt */ /* clear of the CTR flag into the sub */ - PCD_EP_ISR_Handler(hpcd); + (void)PCD_EP_ISR_Handler(hpcd); } - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_RESET)) { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResetCallback(hpcd); +#else HAL_PCD_ResetCallback(hpcd); - HAL_PCD_SetAddress(hpcd, 0); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + (void)HAL_PCD_SetAddress(hpcd, 0U); } - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_PMAOVR)) { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); } - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ERR)) { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); } - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP)) { - - hpcd->Instance->CNTR &= ~(USB_CNTR_LPMODE); - - /*set wInterrupt_Mask global variable*/ - wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ - | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM; - - /*Set interrupt mask*/ - hpcd->Instance->CNTR = wInterrupt_Mask; + hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE); + hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP); - /* enable L1REQ interrupt */ - if (hpcd->Init.lpm_enable ==1) - { - wInterrupt_Mask |= USB_CNTR_L1REQM; - - /* Enable LPM support and enable ACK answer to LPM request*/ - USB_TypeDef *USBx = hpcd->Instance; - hpcd->lpm_active = ENABLE; - hpcd->LPM_State = LPM_L0; - - USBx->LPMCSR |= (USB_LPMCSR_LMPEN); - USBx->LPMCSR |= (USB_LPMCSR_LPMACK); - } - - if(hpcd->LPM_State == LPM_L1) + if (hpcd->LPM_State == LPM_L1) { hpcd->LPM_State = LPM_L0; +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); +#else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResumeCallback(hpcd); +#else HAL_PCD_ResumeCallback(hpcd); - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); } - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP)) - { - /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); - + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SUSP)) + { /* Force low-power mode in the macrocell */ hpcd->Instance->CNTR |= USB_CNTR_FSUSP; + + /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); + hpcd->Instance->CNTR |= USB_CNTR_LPMODE; - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0) + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP) == 0U) { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } - /* Handle LPM Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_L1REQ)) + /* Handle LPM Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_L1REQ)) { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ); - if( hpcd->LPM_State == LPM_L0) - { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ); + if (hpcd->LPM_State == LPM_L0) + { /* Force suspend and low-power mode before going to L1 state*/ hpcd->Instance->CNTR |= USB_CNTR_LPMODE; hpcd->Instance->CNTR |= USB_CNTR_FSUSP; - + hpcd->LPM_State = LPM_L1; - hpcd->BESL = (hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >>2 ; + hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2; +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); +#else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SOF)) { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SOFCallback(hpcd); +#else HAL_PCD_SOFCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ESOF)) { /* clear ESOF flag in ISTR */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); } } #endif /* USB */ /** * @brief Data OUT stage callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -885,13 +1619,13 @@ __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_DataOutStageCallback could be implemented in the user file - */ + */ } /** - * @brief Data IN stage callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @brief Data IN stage callback + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -902,11 +1636,11 @@ __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_DataInStageCallback could be implemented in the user file - */ + */ } /** - * @brief Setup stage callback. - * @param hpcd: PCD handle + * @brief Setup stage callback + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) @@ -916,12 +1650,12 @@ __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_SetupStageCallback could be implemented in the user file - */ + */ } /** * @brief USB Start Of Frame callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) @@ -931,12 +1665,12 @@ __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_SOFCallback could be implemented in the user file - */ + */ } /** * @brief USB Reset callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) @@ -946,12 +1680,12 @@ __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_ResetCallback could be implemented in the user file - */ + */ } /** * @brief Suspend event callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) @@ -961,12 +1695,12 @@ __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_SuspendCallback could be implemented in the user file - */ + */ } /** * @brief Resume event callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) @@ -976,13 +1710,13 @@ __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_ResumeCallback could be implemented in the user file - */ + */ } /** * @brief Incomplete ISO OUT callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -993,13 +1727,13 @@ __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t ep /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file - */ + */ } /** * @brief Incomplete ISO IN callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -1010,12 +1744,12 @@ __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epn /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file - */ + */ } /** * @brief Connection event callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) @@ -1025,12 +1759,12 @@ __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_ConnectCallback could be implemented in the user file - */ + */ } /** * @brief Disconnection event callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) @@ -1040,22 +1774,22 @@ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_DisconnectCallback could be implemented in the user file - */ + */ } /** * @} */ - -/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions + +/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @brief management functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the PCD data + This subsection provides a set of functions allowing to control the PCD data transfers. @endverbatim @@ -1063,305 +1797,330 @@ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) */ /** - * @brief Connect the USB device. - * @param hpcd: PCD handle + * @brief Connect the USB device + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) { - __HAL_LOCK(hpcd); - USB_DevConnect(hpcd->Instance); - __HAL_UNLOCK(hpcd); + __HAL_LOCK(hpcd); + (void)USB_DevConnect(hpcd->Instance); + __HAL_UNLOCK(hpcd); return HAL_OK; } /** * @brief Disconnect the USB device. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) { - __HAL_LOCK(hpcd); - USB_DevDisconnect(hpcd->Instance); - __HAL_UNLOCK(hpcd); + __HAL_LOCK(hpcd); + (void)USB_DevDisconnect(hpcd->Instance); + __HAL_UNLOCK(hpcd); return HAL_OK; } /** * @brief Set the USB Device address. - * @param hpcd: PCD handle - * @param address: new device address + * @param hpcd PCD handle + * @param address new device address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) { - __HAL_LOCK(hpcd); + __HAL_LOCK(hpcd); hpcd->USB_Address = address; - USB_SetDevAddress(hpcd->Instance, address); - __HAL_UNLOCK(hpcd); + (void)USB_SetDevAddress(hpcd->Instance, address); + __HAL_UNLOCK(hpcd); return HAL_OK; } /** * @brief Open and configure an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param ep_mps: endpoint max packet size - * @param ep_type: endpoint type + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param ep_mps endpoint max packet size + * @param ep_type endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { HAL_StatusTypeDef ret = HAL_OK; - PCD_EPTypeDef *ep = NULL; - - if ((ep_addr & 0x80) == 0x80) + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0xFU]; + ep->is_in = 1U; } else { - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + ep = &hpcd->OUT_ep[ep_addr & 0xFU]; + ep->is_in = 0U; } - ep->num = ep_addr & 0x7F; - - ep->is_in = (0x80 & ep_addr) != 0; + + ep->num = ep_addr & 0xFU; ep->maxpacket = ep_mps; ep->type = ep_type; - + + if (ep->is_in != 0U) + { + /* Assign a Tx FIFO */ + ep->tx_fifo_num = ep->num; + } + /* Set initial data PID. */ + if (ep_type == EP_TYPE_BULK) + { + ep->data_pid_start = 0U; + } + __HAL_LOCK(hpcd); - USB_ActivateEndpoint(hpcd->Instance , ep); + (void)USB_ActivateEndpoint(hpcd->Instance, ep); __HAL_UNLOCK(hpcd); - return ret; + return ret; } - /** * @brief Deactivate an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - PCD_EPTypeDef *ep = NULL; - - if ((ep_addr & 0x80) == 0x80) +{ + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0xFU]; + ep->is_in = 1U; } else { - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + ep = &hpcd->OUT_ep[ep_addr & 0xFU]; + ep->is_in = 0U; } - ep->num = ep_addr & 0x7F; - - ep->is_in = (0x80 & ep_addr) != 0; - - __HAL_LOCK(hpcd); - USB_DeactivateEndpoint(hpcd->Instance , ep); - __HAL_UNLOCK(hpcd); + ep->num = ep_addr & 0xFU; + + __HAL_LOCK(hpcd); + (void)USB_DeactivateEndpoint(hpcd->Instance, ep); + __HAL_UNLOCK(hpcd); return HAL_OK; } /** * @brief Receive an amount of data. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param pBuf: pointer to the reception buffer - * @param len: amount of data to be received + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the reception buffer + * @param len amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { - PCD_EPTypeDef *ep = NULL; - - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; - + PCD_EPTypeDef *ep; + + ep = &hpcd->OUT_ep[ep_addr & 0xFU]; + /*setup and start the Xfer */ - ep->xfer_buff = pBuf; + ep->xfer_buff = pBuf; ep->xfer_len = len; - ep->xfer_count = 0; - ep->is_in = 0; - ep->num = ep_addr & 0x7F; - - if ((ep_addr & 0x7F) == 0 ) + ep->xfer_count = 0U; + ep->is_in = 0U; + ep->num = ep_addr & 0xFU; + + if ((ep_addr & 0xFU) == 0U) { - USB_EP0StartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); + (void)USB_EP0StartXfer(hpcd->Instance, ep); } else { - USB_EPStartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); + (void)USB_EPStartXfer(hpcd->Instance, ep); } return HAL_OK; } /** - * @brief Get Received Data Size. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @brief Get Received Data Size + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval Data Size */ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count; + return (uint16_t)hpcd->OUT_ep[ep_addr & 0xFU].xfer_count; } /** - * @brief Send an amount of data. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param pBuf: pointer to the transmission buffer - * @param len: amount of data to be sent + * @brief Send an amount of data + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the transmission buffer + * @param len amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { - PCD_EPTypeDef *ep = NULL; - - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - + PCD_EPTypeDef *ep; + + ep = &hpcd->IN_ep[ep_addr & 0xFU]; + /*setup and start the Xfer */ - ep->xfer_buff = pBuf; + ep->xfer_buff = pBuf; ep->xfer_len = len; - ep->xfer_count = 0; - ep->is_in = 1; - ep->num = ep_addr & 0x7F; - - if ((ep_addr & 0x7F) == 0 ) + ep->xfer_count = 0U; + ep->is_in = 1U; + ep->num = ep_addr & 0xFU; + + if ((ep_addr & 0xFU) == 0U) { - USB_EP0StartXfer(hpcd->Instance,ep, hpcd->Init.dma_enable); + (void)USB_EP0StartXfer(hpcd->Instance, ep); } else { - USB_EPStartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); + (void)USB_EPStartXfer(hpcd->Instance, ep); } - + return HAL_OK; } /** - * @brief Set a STALL condition over an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @brief Set a STALL condition over an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - PCD_EPTypeDef *ep = NULL; - - if ((0x80 & ep_addr) == 0x80) + PCD_EPTypeDef *ep; + + if (((uint32_t)ep_addr & 0xFU) > hpcd->Init.dev_endpoints) + { + return HAL_ERROR; + } + + if ((0x80U & ep_addr) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0xFU]; + ep->is_in = 1U; } else { ep = &hpcd->OUT_ep[ep_addr]; + ep->is_in = 0U; } - - ep->is_stall = 1; - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); - + + ep->is_stall = 1U; + ep->num = ep_addr & 0xFU; + __HAL_LOCK(hpcd); - USB_EPSetStall(hpcd->Instance , ep); - if((ep_addr & 0x7F) == 0) + + (void)USB_EPSetStall(hpcd->Instance, ep); + if ((ep_addr & 0xFU) == 0U) { - USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup); } - __HAL_UNLOCK(hpcd); - + __HAL_UNLOCK(hpcd); + return HAL_OK; } /** - * @brief Clear a STALL condition over in an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @brief Clear a STALL condition over in an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - PCD_EPTypeDef *ep = NULL; - - if ((0x80 & ep_addr) == 0x80) + PCD_EPTypeDef *ep; + + if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) + { + return HAL_ERROR; + } + + if ((0x80U & ep_addr) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0xFU]; + ep->is_in = 1U; } else { - ep = &hpcd->OUT_ep[ep_addr]; + ep = &hpcd->OUT_ep[ep_addr & 0xFU]; + ep->is_in = 0U; } - - ep->is_stall = 0; - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); - - __HAL_LOCK(hpcd); - USB_EPClearStall(hpcd->Instance , ep); - __HAL_UNLOCK(hpcd); - + + ep->is_stall = 0U; + ep->num = ep_addr & 0xFU; + + __HAL_LOCK(hpcd); + (void)USB_EPClearStall(hpcd->Instance, ep); + __HAL_UNLOCK(hpcd); + return HAL_OK; } /** - * @brief Flush an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @brief Flush an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - __HAL_LOCK(hpcd); - - if ((ep_addr & 0x80) == 0x80) + __HAL_LOCK(hpcd); + + if ((ep_addr & 0x80U) == 0x80U) { - USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F); + (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & 0xFU); } else { - USB_FlushRxFifo(hpcd->Instance); + (void)USB_FlushRxFifo(hpcd->Instance); } - - __HAL_UNLOCK(hpcd); - + + __HAL_UNLOCK(hpcd); + return HAL_OK; } /** - * @brief Activate remote wakeup signalling. - * @param hpcd: PCD handle + * @brief Activate remote wakeup signalling + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) { - return(USB_ActivateRemoteWakeup(hpcd->Instance)); + return (USB_ActivateRemoteWakeup(hpcd->Instance)); } /** * @brief De-activate remote wakeup signalling. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) { - return(USB_DeActivateRemoteWakeup(hpcd->Instance)); + return (USB_DeActivateRemoteWakeup(hpcd->Instance)); } + /** * @} */ - -/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions + +/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State functions ##### - =============================================================================== + =============================================================================== [..] - This subsection permits to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -1370,13 +2129,14 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) /** * @brief Return the PCD handle state. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL state */ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) { return hpcd->State; } + /** * @} */ @@ -1389,146 +2149,161 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) /** @addtogroup PCD_Private_Functions * @{ */ -#if defined (USB_OTG_FS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** * @brief Check FIFO for the next packet to be loaded. - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - USB_OTG_EPTypeDef *ep = NULL; - int32_t len = 0U; - uint32_t len32b = 0; - uint32_t fifoemptymsk = 0; + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + USB_OTG_EPTypeDef *ep; + uint32_t len; + uint32_t len32b; + uint32_t fifoemptymsk; ep = &hpcd->IN_ep[epnum]; + + if (ep->xfer_count > ep->xfer_len) + { + return HAL_ERROR; + } + len = ep->xfer_len - ep->xfer_count; - + if (len > ep->maxpacket) { len = ep->maxpacket; } - - - len32b = (len + 3) / 4; - - while ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b && - ep->xfer_count < ep->xfer_len && - ep->xfer_len != 0) + + len32b = (len + 3U) / 4U; + + while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b) && + (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) { /* Write the FIFO */ len = ep->xfer_len - ep->xfer_count; - + if (len > ep->maxpacket) { len = ep->maxpacket; } - len32b = (len + 3) / 4; - - USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable); - + len32b = (len + 3U) / 4U; + + (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len); + ep->xfer_buff += len; ep->xfer_count += len; } - - if(len <= 0) + + if (ep->xfer_len <= ep->xfer_count) { - fifoemptymsk = 0x1 << epnum; + fifoemptymsk = (uint32_t)(0x1UL << epnum); USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; - } - - return HAL_OK; + + return HAL_OK; } -#endif /* USB_OTG_FS */ +#endif /* USB_OTG_FS || USB_OTG_HS */ #if defined (USB) /** * @brief This function handles PCD Endpoint interrupt request. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { - PCD_EPTypeDef *ep = NULL; - uint16_t count = 0; - uint8_t epindex = 0; - __IO uint16_t wIstr = 0; - __IO uint16_t wEPVal = 0; - + PCD_EPTypeDef *ep; + uint16_t count; + uint16_t wIstr; + uint16_t wEPVal; + uint8_t epindex; + /* stay in loop while pending interrupts */ - while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0) + while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) { + wIstr = hpcd->Instance->ISTR; /* extract highest priority endpoint number */ epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); - - if (epindex == 0) + + if (epindex == 0U) { /* Decode and service control endpoint interrupt */ - - /* DIR bit = origin of the interrupt */ - if ((wIstr & USB_ISTR_DIR) == 0) + + /* DIR bit = origin of the interrupt */ + if ((wIstr & USB_ISTR_DIR) == 0U) { /* DIR = 0 */ - + /* DIR = 0 => IN int */ /* DIR = 0 implies that (EP_CTR_TX = 1) always */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); ep = &hpcd->IN_ep[0]; - + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); ep->xfer_buff += ep->xfer_count; - + /* TX COMPLETE */ - HAL_PCD_DataInStageCallback(hpcd, 0); - - - if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0)) +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, 0U); +#else + HAL_PCD_DataInStageCallback(hpcd, 0U); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U)) { - hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF); - hpcd->USB_Address = 0; + hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF); + hpcd->USB_Address = 0U; } - } else { /* DIR = 1 */ - + /* DIR = 1 & CTR_RX => SETUP or OUT int */ /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ ep = &hpcd->OUT_ep[0]; wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - - if ((wEPVal & USB_EP_SETUP) != 0) + + if ((wEPVal & USB_EP_SETUP) != 0U) { /* Get SETUP Packet*/ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - USB_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count); - /* SETUP bit kept frozen while CTR_RX = 1*/ - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); - + USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, ep->pmaadress, (uint16_t)ep->xfer_count); + /* SETUP bit kept frozen while CTR_RX = 1*/ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + /* Process SETUP Packet*/ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SetupStageCallback(hpcd); +#else HAL_PCD_SetupStageCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - - else if ((wEPVal & USB_EP_CTR_RX) != 0) + + else if ((wEPVal & USB_EP_CTR_RX) != 0U) { PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); /* Get Control Data OUT Packet*/ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - - if (ep->xfer_count != 0) + + if (ep->xfer_count != 0U) { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); - ep->xfer_buff+=ep->xfer_count; + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, (uint16_t)ep->xfer_count); + ep->xfer_buff += ep->xfer_count; } - + /* Process Control Data OUT Packet*/ - HAL_PCD_DataOutStageCallback(hpcd, 0); - +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, 0U); +#else + HAL_PCD_DataOutStageCallback(hpcd, 0U); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); } @@ -1537,31 +2312,31 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) else { /* Decode and service non control endpoints interrupt */ - + /* process related endpoint register */ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex); - if ((wEPVal & USB_EP_CTR_RX) != 0) - { + if ((wEPVal & USB_EP_CTR_RX) != 0U) + { /* clear int flag */ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex); ep = &hpcd->OUT_ep[epindex]; - + /* OUT double Buffering*/ - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0U) { - count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - if (count != 0) + count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + if (count != 0U) { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); } } else { - if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) + if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U) { /*read from endpoint BUF0Addr buffer*/ - count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (count != 0) + count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + if (count != 0U) { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); } @@ -1569,83 +2344,60 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) else { /*read from endpoint BUF1Addr buffer*/ - count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (count != 0) + count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + if (count != 0U) { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); } } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT); + PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT); } /*multi-packet on the NON control OUT endpoint*/ - ep->xfer_count+=count; - ep->xfer_buff+=count; - - if ((ep->xfer_len == 0) || (count < ep->maxpacket)) + ep->xfer_count += count; + ep->xfer_buff += count; + + if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) { /* RX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, ep->num); +#else HAL_PCD_DataOutStageCallback(hpcd, ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { - HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + (void)HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); } - + } /* if((wEPVal & EP_CTR_RX) */ - - if ((wEPVal & USB_EP_CTR_TX) != 0) + + if ((wEPVal & USB_EP_CTR_TX) != 0U) { ep = &hpcd->IN_ep[epindex]; - + /* clear int flag */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); - - /* IN double Buffering*/ - if (ep->doublebuffer == 0) - { - ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) - { - USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); - } - } - else - { - if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX) - { - /*read from endpoint BUF0Addr buffer*/ - ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) - { - USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count); - } - } - else - { - /*read from endpoint BUF1Addr buffer*/ - ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) - { - USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count); - } - } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN); - } + /*multi-packet on the NON control IN endpoint*/ ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - ep->xfer_buff+=ep->xfer_count; - + ep->xfer_buff += ep->xfer_count; + /* Zero Length Packet? */ - if (ep->xfer_len == 0) + if (ep->xfer_len == 0U) { /* TX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, ep->num); +#else HAL_PCD_DataInStageCallback(hpcd, ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { - HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + (void)HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); } - } + } } } return HAL_OK; @@ -1656,11 +2408,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) * @} */ -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* defined (USB) || defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #endif /* HAL_PCD_MODULE_ENABLED */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c index 15842b4b9e..7ea5b06237 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l4xx_hal_pcd_ex.c * @author MCD Application Team - * @brief PCD Extended HAL module driver. - * This file provides firmware functions to manage the following + * @brief PCD Extended HAL module driver. + * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: * + Extended features functions * @@ -35,7 +35,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -51,11 +51,7 @@ #ifdef HAL_PCD_MODULE_ENABLED -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined (USB) || defined (USB_OTG_FS) || defined (USB_OTG_HS) /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -67,216 +63,245 @@ /** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions * @{ */ - + /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions - * @brief PCDEx control functions + * @brief PCDEx control functions * -@verbatim +@verbatim =============================================================================== ##### Extended features functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Update FIFO configuration @endverbatim * @{ */ -#if defined (USB_OTG_FS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** * @brief Set Tx FIFO - * @param hpcd: PCD handle - * @param fifo: The number of Tx fifo - * @param size: Fifo size + * @param hpcd PCD handle + * @param fifo The number of Tx fifo + * @param size Fifo size * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) { - uint8_t index = 0; - uint32_t Tx_Offset = 0; + uint8_t i; + uint32_t Tx_Offset; /* TXn min size = 16 words. (n : Transmit FIFO index) - When a TxFIFO is not used, the Configuration should be as follows: + When a TxFIFO is not used, the Configuration should be as follows: case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) --> Txm can use the space allocated for Txn. case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) --> Txn should be configured with the minimum space of 16 words - The FIFO is used optimally when used TxFIFOs are allocated in the top + The FIFO is used optimally when used TxFIFOs are allocated in the top of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ - + Tx_Offset = hpcd->Instance->GRXFSIZ; - - if(fifo == 0) + + if (fifo == 0U) { - hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset; + hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; } else { Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; - for (index = 0; index < (fifo - 1); index++) + for (i = 0U; i < (fifo - 1U); i++) { - Tx_Offset += (hpcd->Instance->DIEPTXF[index] >> 16); + Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); } - + /* Multiply Tx_Size by 2 to get higher performance */ - hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset; + hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; } - + return HAL_OK; } /** * @brief Set Rx FIFO - * @param hpcd: PCD handle - * @param size: Size of Rx fifo + * @param hpcd PCD handle + * @param size Size of Rx fifo * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) { hpcd->Instance->GRXFSIZ = size; - + return HAL_OK; } /** * @brief Activate LPM feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - hpcd->lpm_active = ENABLE; + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 1U; hpcd->LPM_State = LPM_L0; USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); - return HAL_OK; + return HAL_OK; } /** * @brief Deactivate LPM feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - hpcd->lpm_active = DISABLE; + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 0U; USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM; USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); - - return HAL_OK; + + return HAL_OK; } /** * @brief Handle BatteryCharging Process. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tickstart = HAL_GetTick(); - + /* Start BCD When device is connected */ - if (USBx_DEVICE->DCTL & USB_OTG_DCTL_SDIS) - { + if ((USBx_DEVICE->DCTL & USB_OTG_DCTL_SDIS) == USB_OTG_DCTL_SDIS) + { /* Enable DCD : Data Contact Detect */ USBx->GCCFG |= USB_OTG_GCCFG_DCDEN; - + /* Wait Detect flag or a timeout is happen*/ - while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0) + while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > 1000) + if ((HAL_GetTick() - tickstart) > 1000U) { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); +#else HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + return; } } - + /* Right response got */ - HAL_Delay(100); - + HAL_Delay(100); + /* Check Detect flag*/ - if (USBx->GCCFG & USB_OTG_GCCFG_DCDET) + if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET) { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION); +#else HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - - /*Primary detection: checks if connected to Standard Downstream Port + + /*Primary detection: checks if connected to Standard Downstream Port (without charging capability) */ - USBx->GCCFG &=~ USB_OTG_GCCFG_DCDEN; + USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN; USBx->GCCFG |= USB_OTG_GCCFG_PDEN; - HAL_Delay(100); - - if (!(USBx->GCCFG & USB_OTG_GCCFG_PDET)) + HAL_Delay(100); + + if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U) { /* Case of Standard Downstream Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); +#else HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - else + else { - /* start secondary detection to check connection to Charging Downstream + /* start secondary detection to check connection to Charging Downstream Port or Dedicated Charging Port */ - USBx->GCCFG &=~ USB_OTG_GCCFG_PDEN; + USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN; USBx->GCCFG |= USB_OTG_GCCFG_SDEN; - HAL_Delay(100); - - if ((USBx->GCCFG) & USB_OTG_GCCFG_SDET) - { + HAL_Delay(100); + + if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET) + { /* case Dedicated Charging Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); +#else HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { /* case Charging Downstream Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); +#else HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } + /* Battery Charging capability discovery finished */ + (void)HAL_PCDEx_DeActivateBCD(hpcd); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#else HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } /** * @brief Activate BatteryCharging feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - hpcd->battery_charging_active = ENABLE; + hpcd->battery_charging_active = 1U; USBx->GCCFG |= (USB_OTG_GCCFG_BCDEN); - - return HAL_OK; + + return HAL_OK; } /** * @brief Deactivate BatteryCharging feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - hpcd->battery_charging_active = DISABLE; + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + hpcd->battery_charging_active = 0U; USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); - return HAL_OK; + return HAL_OK; } -#endif /* USB_OTG_FS */ +#endif /* USB_OTG_FS || USB_OTG_HS */ #if defined (USB) /** * @brief Configure PMA for EP - * @param hpcd : Device instance - * @param ep_addr: endpoint address - * @param ep_kind: endpoint Kind + * @param hpcd Device instance + * @param ep_addr endpoint address + * @param ep_kind endpoint Kind * USB_SNG_BUF: Single Buffer used * USB_DBL_BUF: Double Buffer used * @param pmaadress: EP address in The PMA: In case of single buffer endpoint @@ -289,200 +314,223 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) * @retval HAL status */ -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress) - { - PCD_EPTypeDef *ep = NULL; - + PCD_EPTypeDef *ep; + /* initialize ep structure*/ - if ((0x80 & ep_addr) == 0x80) + if ((0x80U & ep_addr) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0xFU]; } else { ep = &hpcd->OUT_ep[ep_addr]; } - + /* Here we check if the endpoint is single or double Buffer*/ if (ep_kind == PCD_SNG_BUF) { - /*Single Buffer*/ - ep->doublebuffer = 0; - /*Configure te PMA*/ + /* Single Buffer */ + ep->doublebuffer = 0U; + /* Configure the PMA */ ep->pmaadress = (uint16_t)pmaadress; } - else /*USB_DBL_BUF*/ + else /* USB_DBL_BUF */ { - /*Double Buffer Endpoint*/ - ep->doublebuffer = 1; - /*Configure the PMA*/ - ep->pmaaddr0 = pmaadress & 0xFFFF; - ep->pmaaddr1 = (pmaadress & 0xFFFF0000) >> 16; + /* Double Buffer Endpoint */ + ep->doublebuffer = 1U; + /* Configure the PMA */ + ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU); + ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16); } - - return HAL_OK; + + return HAL_OK; } /** * @brief Activate BatteryCharging feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) { USB_TypeDef *USBx = hpcd->Instance; - hpcd->battery_charging_active = ENABLE; - + hpcd->battery_charging_active = 1U; + USBx->BCDR |= (USB_BCDR_BCDEN); /* Enable DCD : Data Contact Detect */ USBx->BCDR |= (USB_BCDR_DCDEN); - - return HAL_OK; + + return HAL_OK; } /** * @brief Deactivate BatteryCharging feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) { USB_TypeDef *USBx = hpcd->Instance; - hpcd->battery_charging_active = DISABLE; - + hpcd->battery_charging_active = 0U; + USBx->BCDR &= ~(USB_BCDR_BCDEN); - return HAL_OK; + + return HAL_OK; } /** * @brief Handle BatteryCharging Process. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) { USB_TypeDef *USBx = hpcd->Instance; uint32_t tickstart = HAL_GetTick(); - + /* Wait Detect flag or a timeout is happen*/ - while ((USBx->BCDR & USB_BCDR_DCDET) == 0) + while ((USBx->BCDR & USB_BCDR_DCDET) == 0U) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > 1000) + if ((HAL_GetTick() - tickstart) > 1000U) { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); +#else HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + return; } } - HAL_Delay(300); - + HAL_Delay(300U); + /* Data Pin Contact ? Check Detect flag */ - if (USBx->BCDR & USB_BCDR_DCDET) + if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET) { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION); +#else HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); - } - /* Primary detection: checks if connected to Standard Downstream Port +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + /* Primary detection: checks if connected to Standard Downstream Port (without charging capability) */ USBx->BCDR &= ~(USB_BCDR_DCDEN); USBx->BCDR |= (USB_BCDR_PDEN); - HAL_Delay(300); - + HAL_Delay(300U); + /* If Charger detect ? */ - if (USBx->BCDR & USB_BCDR_PDET) + if ((USBx->BCDR & USB_BCDR_PDET) == USB_BCDR_PDET) { - /* Start secondary detection to check connection to Charging Downstream + /* Start secondary detection to check connection to Charging Downstream Port or Dedicated Charging Port */ USBx->BCDR &= ~(USB_BCDR_PDEN); USBx->BCDR |= (USB_BCDR_SDEN); - HAL_Delay(300); - + HAL_Delay(300U); + /* If CDP ? */ - if (USBx->BCDR & USB_BCDR_SDET) + if ((USBx->BCDR & USB_BCDR_SDET) == USB_BCDR_SDET) { /* Dedicated Downstream Port DCP */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); +#else HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { /* Charging Downstream Port CDP */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); +#else HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); - - /* Battery Charging capability discovery finished - Start Enumeration*/ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } else /* NO */ { /* Standard Downstream Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); +#else HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } + + /* Battery Charging capability discovery finished Start Enumeration */ + (void)HAL_PCDEx_DeActivateBCD(hpcd); +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } /** * @brief Activate LPM feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) { USB_TypeDef *USBx = hpcd->Instance; - hpcd->lpm_active = ENABLE; + hpcd->lpm_active = 1U; hpcd->LPM_State = LPM_L0; - - USBx->LPMCSR |= (USB_LPMCSR_LMPEN); - USBx->LPMCSR |= (USB_LPMCSR_LPMACK); - - - return HAL_OK; + + USBx->LPMCSR |= USB_LPMCSR_LMPEN; + USBx->LPMCSR |= USB_LPMCSR_LPMACK; + + return HAL_OK; } /** * @brief Deactivate LPM feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) { - USB_TypeDef *USBx = hpcd->Instance; - - hpcd->lpm_active = DISABLE; - - USBx->LPMCSR &= ~ (USB_LPMCSR_LMPEN); - USBx->LPMCSR &= ~ (USB_LPMCSR_LPMACK); - - return HAL_OK; -} + USB_TypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 0U; + + USBx->LPMCSR &= ~(USB_LPMCSR_LMPEN); + USBx->LPMCSR &= ~(USB_LPMCSR_LPMACK); + return HAL_OK; +} #endif /* USB */ /** * @brief Send LPM message to user layer callback. - * @param hpcd: PCD handle - * @param msg: LPM message + * @param hpcd PCD handle + * @param msg LPM message * @retval HAL status */ __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) -{ +{ /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); UNUSED(msg); /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCDEx_LPM_Callback could be implemented in the user file - */ + */ } /** * @brief Send BatteryCharging message to user layer callback. - * @param hpcd: PCD handle - * @param msg: LPM message + * @param hpcd PCD handle + * @param msg LPM message * @retval HAL status */ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg) @@ -493,7 +541,7 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCDEx_BCD_Callback could be implemented in the user file - */ + */ } /** @@ -504,11 +552,7 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m * @} */ -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* defined (USB) || defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #endif /* HAL_PCD_MODULE_ENABLED */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c index 02bff3ef1a..6a7ef5fa8a 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c @@ -3,7 +3,7 @@ * @file stm32l4xx_hal_qspi.c * @author MCD Application Team * @brief QSPI HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the QuadSPI interface (QSPI). * + Initialization and de-initialization functions * + Indirect functional mode management @@ -29,9 +29,9 @@ (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init(). (++) If interrupt mode is used, enable and configure QuadSPI global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). - (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel - with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), - link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure + (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel + with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), + link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). (#) Configure the flash size, the clock prescaler, the fifo threshold, the clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function. @@ -39,47 +39,47 @@ *** Indirect functional mode *** ================================ [..] - (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT() + (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT() functions : (++) Instruction phase : the mode used and if present the instruction opcode. (++) Address phase : the mode used and if present the size and the address value. - (++) Alternate-bytes phase : the mode used and if present the size and the alternate + (++) Alternate-bytes phase : the mode used and if present the size and the alternate bytes values. (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). (++) Data phase : the mode used and if present the number of bytes. - (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay + (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay if activated. (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. (#) If no data is required for the command, it is sent directly to the memory : (++) In polling mode, the output of the function is done when the transfer is complete. (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete. - (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or + (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or HAL_QSPI_Transmit_IT() after the command configuration : (++) In polling mode, the output of the function is done when the transfer is complete. - (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold + (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete. - (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and + (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete. - (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or + (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or HAL_QSPI_Receive_IT() after the command configuration : (++) In polling mode, the output of the function is done when the transfer is complete. - (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold + (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete. - (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and + (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete. *** Auto-polling functional mode *** ==================================== [..] - (#) Configure the command sequence and the auto-polling functional mode using the + (#) Configure the command sequence and the auto-polling functional mode using the HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions : (++) Instruction phase : the mode used and if present the instruction opcode. (++) Address phase : the mode used and if present the size and the address value. - (++) Alternate-bytes phase : the mode used and if present the size and the alternate + (++) Alternate-bytes phase : the mode used and if present the size and the alternate bytes values. (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). (++) Data phase : the mode used. - (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay + (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay if activated. (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND), @@ -92,31 +92,31 @@ *** Memory-mapped functional mode *** ===================================== [..] - (#) Configure the command sequence and the memory-mapped functional mode using the + (#) Configure the command sequence and the memory-mapped functional mode using the HAL_QSPI_MemoryMapped() functions : (++) Instruction phase : the mode used and if present the instruction opcode. (++) Address phase : the mode used and the size. - (++) Alternate-bytes phase : the mode used and if present the size and the alternate + (++) Alternate-bytes phase : the mode used and if present the size and the alternate bytes values. (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). (++) Data phase : the mode used. - (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay + (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay if activated. (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. (++) The timeout activation and the timeout period. - (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on + (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires. *** Errors management and abort functionality *** ================================================= [..] (#) HAL_QSPI_GetError() function gives the error raised during the last operation. - (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and + (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and flushes the fifo : - (++) In polling mode, the output of the function is done when the transfer + (++) In polling mode, the output of the function is done when the transfer complete bit is set and the busy bit cleared. - (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when - the transfer complete bi is set. + (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when + the transfer complete bit is set. *** Control functions *** ========================= @@ -124,7 +124,67 @@ (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver. (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver. (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP. - (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold + (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold + (#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed. + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions @ref HAL_QSPI_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) FifoThresholdCallback : callback when the fifo threshold is reached. + (+) CmdCpltCallback : callback when a command without data is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxHalfCpltCallback : callback when half of the reception transfer is completed. + (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed. + (+) StatusMatchCallback : callback when a status match occurs. + (+) TimeOutCallback : callback when the timeout perioed expires. + (+) MspInitCallback : QSPI MspInit. + (+) MspDeInitCallback : QSPI MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_QSPI_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) FifoThresholdCallback : callback when the fifo threshold is reached. + (+) CmdCpltCallback : callback when a command without data is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxHalfCpltCallback : callback when half of the reception transfer is completed. + (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed. + (+) StatusMatchCallback : callback when a status match occurs. + (+) TimeOutCallback : callback when the timeout perioed expires. + (+) MspInitCallback : QSPI MspInit. + (+) MspDeInitCallback : QSPI MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the @ref HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_QSPI_Init + and @ref HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_QSPI_Init and @ref HAL_QSPI_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_QSPI_RegisterCallback before calling @ref HAL_QSPI_DeInit + or @ref HAL_QSPI_Init function. + + When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. *** Workarounds linked to Silicon Limitation *** ==================================================== @@ -160,7 +220,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -177,14 +237,14 @@ * @{ */ #ifdef HAL_QSPI_MODULE_ENABLED - + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup QSPI_Private_Constants QSPI Private Constants * @{ */ -#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!Init.FlashSize)); assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime)); assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode)); -#if defined(QUADSPI_CR_DFM) +#if defined(QUADSPI_CR_DFM) assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash)); if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE ) @@ -271,25 +331,47 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID)); } #endif - + /* Process locked */ __HAL_LOCK(hqspi); - + if(hqspi->State == HAL_QSPI_STATE_RESET) - { + { /* Allocate lock resource and initialize it */ hqspi->Lock = HAL_UNLOCKED; +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + /* Reset Callback pointers in HAL_QSPI_STATE_RESET only */ + hqspi->ErrorCallback = HAL_QSPI_ErrorCallback; + hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback; + hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback; + hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback; + hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback; + hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback; + hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback; + hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback; + hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback; + hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback; + + if(hqspi->MspInitCallback == NULL) + { + hqspi->MspInitCallback = HAL_QSPI_MspInit; + } + + /* Init the low level hardware */ + hqspi->MspInitCallback(hqspi); +#else /* Init the low level hardware : GPIO, CLOCK */ HAL_QSPI_MspInit(hqspi); - +#endif + /* Configure the default timeout for the QSPI memory access */ HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE); } - + /* Configure QSPI FIFO Threshold */ - MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, - ((hqspi->Init.FifoThreshold - 1) << QUADSPI_CR_FTHRES_Pos)); + MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, + ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); /* Wait till BUSY flag reset */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); @@ -297,31 +379,31 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) if(status == HAL_OK) { /* Configure QSPI Clock Prescaler and Sample Shift */ -#if defined(QUADSPI_CR_DFM) - MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), - ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | +#if defined(QUADSPI_CR_DFM) + MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), + ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash)); #else - MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT), - ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | + MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT), + ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | hqspi->Init.SampleShifting)); #endif - + /* Configure QSPI Flash Size, CS High Time and Clock Mode */ - MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), - ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) | + MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), + ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode)); /* Enable the QSPI peripheral */ __HAL_QSPI_ENABLE(hqspi); - + /* Set QSPI error code to none */ - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; /* Initialize the QSPI state */ hqspi->State = HAL_QSPI_STATE_READY; } - + /* Release Lock */ __HAL_UNLOCK(hqspi); @@ -330,7 +412,7 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) } /** - * @brief De-Initialize the QSPI peripheral. + * @brief De-Initialize the QSPI peripheral. * @param hqspi : QSPI handle * @retval HAL status */ @@ -348,8 +430,18 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) /* Disable the QSPI Peripheral Clock */ __HAL_QSPI_DISABLE(hqspi); +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + if(hqspi->MspDeInitCallback == NULL) + { + hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; + } + + /* DeInit the low level hardware */ + hqspi->MspDeInitCallback(hqspi); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ HAL_QSPI_MspDeInit(hqspi); +#endif /* Set QSPI error code to none */ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; @@ -368,14 +460,14 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) * @param hqspi : QSPI handle * @retval None */ - __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) +__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); /* NOTE : This function should not be modified, when the callback is needed, the HAL_QSPI_MspInit can be implemented in the user file - */ + */ } /** @@ -383,24 +475,24 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) * @param hqspi : QSPI handle * @retval None */ - __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) +__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); /* NOTE : This function should not be modified, when the callback is needed, the HAL_QSPI_MspDeInit can be implemented in the user file - */ + */ } /** * @} */ -/** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions - * @brief QSPI Transmit/Receive functions +/** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions + * @brief QSPI Transmit/Receive functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== @@ -429,19 +521,20 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) uint32_t itsource = READ_REG(hqspi->Instance->CR); /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/ - if(((flag & QSPI_FLAG_FT) != 0) && ((itsource & QSPI_IT_FT) !=0 )) + if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U)) { data_reg = &hqspi->Instance->DR; if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) { /* Transmission process */ - while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0) + while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) { - if (hqspi->TxXferCount > 0) + if (hqspi->TxXferCount > 0U) { /* Fill the FIFO until the threshold is reached */ - *(__IO uint8_t *)((__IO void *)data_reg) = *hqspi->pTxBuffPtr++; + *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; + hqspi->pTxBuffPtr++; hqspi->TxXferCount--; } else @@ -456,12 +549,13 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) { /* Receiving Process */ - while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0) + while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) { - if (hqspi->RxXferCount > 0) + if (hqspi->RxXferCount > 0U) { /* Read the FIFO until the threshold is reached */ - *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)((__IO void *)data_reg); + *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); + hqspi->pRxBuffPtr++; hqspi->RxXferCount--; } else @@ -473,62 +567,75 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } } } - + else + { + /* Nothing to do */ + } + /* FIFO Threshold callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->FifoThresholdCallback(hqspi); +#else HAL_QSPI_FifoThresholdCallback(hqspi); +#endif } /* QSPI Transfer Complete interrupt occurred -------------------------------*/ - else if(((flag & QSPI_FLAG_TC) != 0) && ((itsource & QSPI_IT_TC) != 0)) + else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC); /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */ __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); - + /* Transfer complete callback */ if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) { - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - + /* Disable the DMA channel */ __HAL_DMA_DISABLE(hqspi->hdma); } - -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) + +#if (defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)) /* Clear Busy bit */ HAL_QSPI_Abort_IT(hqspi); #endif - + /* Change state of QSPI */ hqspi->State = HAL_QSPI_STATE_READY; /* TX Complete callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->TxCpltCallback(hqspi); +#else HAL_QSPI_TxCpltCallback(hqspi); +#endif } else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) { - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - + /* Disable the DMA channel */ __HAL_DMA_DISABLE(hqspi->hdma); } else { data_reg = &hqspi->Instance->DR; - while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0) + while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U) { - if (hqspi->RxXferCount > 0) + if (hqspi->RxXferCount > 0U) { /* Read the last data received in the FIFO until it is empty */ - *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)((__IO void *)data_reg); + *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); + hqspi->pRxBuffPtr++; hqspi->RxXferCount--; } else @@ -539,7 +646,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } } -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) +#if (defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)) /* Workaround - Extra data written in the FIFO at the end of a read transfer */ HAL_QSPI_Abort_IT(hqspi); #endif @@ -548,7 +655,11 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) hqspi->State = HAL_QSPI_STATE_READY; /* RX Complete callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->RxCpltCallback(hqspi); +#else HAL_QSPI_RxCpltCallback(hqspi); +#endif } else if(hqspi->State == HAL_QSPI_STATE_BUSY) { @@ -556,10 +667,17 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) hqspi->State = HAL_QSPI_STATE_READY; /* Command Complete callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->CmdCpltCallback(hqspi); +#else HAL_QSPI_CmdCpltCallback(hqspi); +#endif } else if(hqspi->State == HAL_QSPI_STATE_ABORT) { + /* Reset functional mode configuration to indirect write mode by default */ + CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); + /* Change state of QSPI */ hqspi->State = HAL_QSPI_STATE_READY; @@ -568,26 +686,38 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /* Abort called by the user */ /* Abort Complete callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->AbortCpltCallback(hqspi); +#else HAL_QSPI_AbortCpltCallback(hqspi); +#endif } - else + else { /* Abort due to an error (eg : DMA error) */ /* Error callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->ErrorCallback(hqspi); +#else HAL_QSPI_ErrorCallback(hqspi); +#endif } } + else + { + /* Nothing to do */ + } } /* QSPI Status Match interrupt occurred ------------------------------------*/ - else if(((flag & QSPI_FLAG_SM) != 0) && ((itsource & QSPI_IT_SM) != 0)) + else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM); - + /* Check if the automatic poll mode stop is activated */ - if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0) + if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U) { /* Disable the QSPI Transfer Error and Status Match Interrupts */ __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); @@ -597,29 +727,47 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* Status match callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->StatusMatchCallback(hqspi); +#else HAL_QSPI_StatusMatchCallback(hqspi); +#endif } /* QSPI Transfer Error interrupt occurred ----------------------------------*/ - else if(((flag & QSPI_FLAG_TE) != 0) && ((itsource & QSPI_IT_TE) != 0)) + else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE); - + /* Disable all the QSPI Interrupts */ __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); /* Set error code */ hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER; - - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0) + + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - + /* Disable the DMA channel */ hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt; - HAL_DMA_Abort_IT(hqspi->hdma); + if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK) + { + /* Set error code to DMA */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + + /* Error callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->ErrorCallback(hqspi); +#else + HAL_QSPI_ErrorCallback(hqspi); +#endif + } } else { @@ -627,23 +775,36 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) hqspi->State = HAL_QSPI_STATE_READY; /* Error callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->ErrorCallback(hqspi); +#else HAL_QSPI_ErrorCallback(hqspi); +#endif } } /* QSPI Timeout interrupt occurred -----------------------------------------*/ - else if(((flag & QSPI_FLAG_TO) != 0) && ((itsource & QSPI_IT_TO) != 0)) + else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO); - + /* Timeout callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->TimeOutCallback(hqspi); +#else HAL_QSPI_TimeOutCallback(hqspi); +#endif + } + + else + { + /* Nothing to do */ } } /** - * @brief Set the command configuration. + * @brief Set the command configuration. * @param hqspi : QSPI handle * @param cmd : structure that contains the command configuration information * @param Timeout : Timeout duration @@ -652,9 +813,9 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) */ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); - + /* Check the parameters */ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) @@ -680,51 +841,51 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); - + /* Process locked */ __HAL_LOCK(hqspi); if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - + /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_BUSY; - + hqspi->State = HAL_QSPI_STATE_BUSY; + /* Wait till BUSY flag reset */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); - + if (status == HAL_OK) { /* Call the configuration function */ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - + if (cmd->DataMode == QSPI_DATA_NONE) { - /* When there is no data phase, the transfer start as soon as the configuration is done + /* When there is no data phase, the transfer start as soon as the configuration is done so wait until TC flag is set to go back in idle state */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); if (status == HAL_OK) { __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - + /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_READY; + hqspi->State = HAL_QSPI_STATE_READY; } } else { /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_READY; + hqspi->State = HAL_QSPI_STATE_READY; } } } else { - status = HAL_BUSY; + status = HAL_BUSY; } - + /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -733,7 +894,7 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe } /** - * @brief Set the command configuration in interrupt mode. + * @brief Set the command configuration in interrupt mode. * @param hqspi : QSPI handle * @param cmd : structure that contains the command configuration information * @note This function is used only in Indirect Read or Write Modes @@ -741,9 +902,9 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe */ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); - + /* Check the parameters */ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) @@ -769,20 +930,20 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); - + /* Process locked */ __HAL_LOCK(hqspi); if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - + /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_BUSY; - + hqspi->State = HAL_QSPI_STATE_BUSY; + /* Wait till BUSY flag reset */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); - + if (status == HAL_OK) { if (cmd->DataMode == QSPI_DATA_NONE) @@ -790,13 +951,13 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp /* Clear interrupt */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); } - + /* Call the configuration function */ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - + if (cmd->DataMode == QSPI_DATA_NONE) { - /* When there is no data phase, the transfer start as soon as the configuration is done + /* When there is no data phase, the transfer start as soon as the configuration is done so activate TC and TE interrupts */ /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -807,7 +968,7 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp else { /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_READY; + hqspi->State = HAL_QSPI_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -821,8 +982,8 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp } else { - status = HAL_BUSY; - + status = HAL_BUSY; + /* Process unlocked */ __HAL_UNLOCK(hqspi); } @@ -832,7 +993,7 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp } /** - * @brief Transmit an amount of data in blocking mode. + * @brief Transmit an amount of data in blocking mode. * @param hqspi : QSPI handle * @param pData : pointer to data buffer * @param Timeout : Timeout duration @@ -851,34 +1012,35 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - + if(pData != NULL ) { /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; - + /* Configure counters and size of the handle */ - hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1; - hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1; + hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; + hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; hqspi->pTxBuffPtr = pData; - + /* Configure QSPI: CCR register with functional as indirect write */ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - while(hqspi->TxXferCount > 0) + while(hqspi->TxXferCount > 0U) { /* Wait until FT flag is set to send data */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout); if (status != HAL_OK) - { + { break; } - *(__IO uint8_t *)((__IO void *)data_reg) = *hqspi->pTxBuffPtr++; + *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; + hqspi->pTxBuffPtr++; hqspi->TxXferCount--; } - + if (status == HAL_OK) { /* Wait until TC flag is set to go back in idle state */ @@ -888,16 +1050,16 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u { /* Clear Transfer Complete bit */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) + +#if (defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)) /* Clear Busy bit */ status = HAL_QSPI_Abort(hqspi); #endif } } - + /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_READY; + hqspi->State = HAL_QSPI_STATE_READY; } else { @@ -938,15 +1100,15 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - + if(pData != NULL ) { /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; - + /* Configure counters and size of the handle */ - hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1; - hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1; + hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; + hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; hqspi->pRxBuffPtr = pData; /* Configure QSPI: CCR register with functional as indirect read */ @@ -954,21 +1116,22 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui /* Start the transfer by re-writing the address in AR register */ WRITE_REG(hqspi->Instance->AR, addr_reg); - - while(hqspi->RxXferCount > 0) + + while(hqspi->RxXferCount > 0U) { /* Wait until FT or TC flag is set to read received data */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout); if (status != HAL_OK) - { + { break; } - *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)((__IO void *)data_reg); + *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); + hqspi->pRxBuffPtr++; hqspi->RxXferCount--; } - + if (status == HAL_OK) { /* Wait until TC flag is set to go back in idle state */ @@ -979,7 +1142,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui /* Clear Transfer Complete bit */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) +#if (defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)) /* Workaround - Extra data written in the FIFO at the end of a read transfer */ status = HAL_QSPI_Abort(hqspi); #endif @@ -987,7 +1150,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui } /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_READY; + hqspi->State = HAL_QSPI_STATE_READY; } else { @@ -999,7 +1162,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui { status = HAL_BUSY; } - + /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -1014,7 +1177,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) -{ +{ HAL_StatusTypeDef status = HAL_OK; /* Process locked */ @@ -1030,19 +1193,19 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; /* Configure counters and size of the handle */ - hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1; - hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1; + hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; + hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; hqspi->pTxBuffPtr = pData; - - /* Configure QSPI: CCR register with functional as indirect write */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - + /* Clear interrupt */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); + /* Configure QSPI: CCR register with functional as indirect write */ + MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + /* Process unlocked */ __HAL_UNLOCK(hqspi); - + /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); } @@ -1084,26 +1247,26 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - + if(pData != NULL ) { /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; - + /* Configure counters and size of the handle */ - hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1; - hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1; + hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; + hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; hqspi->pRxBuffPtr = pData; + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); + /* Configure QSPI: CCR register with functional as indirect read */ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); /* Start the transfer by re-writing the address in AR register */ WRITE_REG(hqspi->Instance->AR, addr_reg); - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); - /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -1121,7 +1284,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) } else { - status = HAL_BUSY; + status = HAL_BUSY; /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -1131,31 +1294,30 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) } /** - * @brief Send an amount of data in non-blocking mode with DMA. + * @brief Send an amount of data in non-blocking mode with DMA. * @param hqspi : QSPI handle * @param pData : pointer to data buffer * @note This function is used only in Indirect Write Mode - * @note If DMA peripheral access is configured as halfword, the number + * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword - * @note If DMA peripheral access is configured as word, the number + * @note If DMA peripheral access is configured as word, the number * of data and the fifo threshold should be aligned on word * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; - uint32_t *tmp; - uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1); - + uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); + /* Process locked */ __HAL_LOCK(hqspi); if(hqspi->State == HAL_QSPI_STATE_READY) { - /* Clear the error code */ + /* Clear the error code */ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - if(pData != NULL ) + + if(pData != NULL ) { /* Configure counters of the handle */ if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) @@ -1164,9 +1326,9 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat } else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) { - if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0)) + if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) { - /* The number of data or the fifo threshold is not aligned on halfword + /* The number of data or the fifo threshold is not aligned on halfword => no transfer possible with DMA peripheral access configured as halfword */ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -1176,27 +1338,31 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat } else { - hqspi->TxXferCount = (data_size >> 1); + hqspi->TxXferCount = (data_size >> 1U); } } else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) { - if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0)) + if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) { - /* The number of data or the fifo threshold is not aligned on word + /* The number of data or the fifo threshold is not aligned on word => no transfer possible with DMA peripheral access configured as word */ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; - + /* Process unlocked */ __HAL_UNLOCK(hqspi); } else { - hqspi->TxXferCount = (data_size >> 2); + hqspi->TxXferCount = (data_size >> 2U); } } - + else + { + /* Nothing to do */ + } + if (status == HAL_OK) { /* Update state */ @@ -1208,20 +1374,20 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat /* Configure size and pointer of the handle */ hqspi->TxXferSize = hqspi->TxXferCount; hqspi->pTxBuffPtr = pData; - + /* Configure QSPI: CCR register with functional mode as indirect write */ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - + /* Set the QSPI DMA transfer complete callback */ hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt; - + /* Set the QSPI DMA Half transfer complete callback */ hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt; - + /* Set the DMA error callback */ hqspi->hdma->XferErrorCallback = QSPI_DMAError; - - /* Clear the DMA abort callback */ + + /* Clear the DMA abort callback */ hqspi->hdma->XferAbortCallback = NULL; /* Configure the direction of the DMA */ @@ -1229,17 +1395,26 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction); /* Enable the QSPI transmit DMA Channel */ - tmp = (uint32_t*)((void*)&pData); - HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize); - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Enable the QSPI transfer error Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize) == HAL_OK) + { + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Enable the QSPI transfer error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + + /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + hqspi->State = HAL_QSPI_STATE_READY; - /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } } } else @@ -1253,7 +1428,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat } else { - status = HAL_BUSY; + status = HAL_BUSY; /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -1263,32 +1438,31 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat } /** - * @brief Receive an amount of data in non-blocking mode with DMA. + * @brief Receive an amount of data in non-blocking mode with DMA. * @param hqspi : QSPI handle * @param pData : pointer to data buffer. * @note This function is used only in Indirect Read Mode - * @note If DMA peripheral access is configured as halfword, the number + * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword - * @note If DMA peripheral access is configured as word, the number + * @note If DMA peripheral access is configured as word, the number * of data and the fifo threshold should be aligned on word * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; - uint32_t *tmp; uint32_t addr_reg = READ_REG(hqspi->Instance->AR); - uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1); - + uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); + /* Process locked */ __HAL_LOCK(hqspi); if(hqspi->State == HAL_QSPI_STATE_READY) { - /* Clear the error code */ + /* Clear the error code */ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - if(pData != NULL ) + + if(pData != NULL ) { /* Configure counters of the handle */ if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) @@ -1297,44 +1471,48 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData } else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) { - if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0)) + if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) { - /* The number of data or the fifo threshold is not aligned on halfword + /* The number of data or the fifo threshold is not aligned on halfword => no transfer possible with DMA peripheral access configured as halfword */ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; - + /* Process unlocked */ __HAL_UNLOCK(hqspi); } else { - hqspi->RxXferCount = (data_size >> 1); + hqspi->RxXferCount = (data_size >> 1U); } } else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) { - if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0)) + if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) { - /* The number of data or the fifo threshold is not aligned on word + /* The number of data or the fifo threshold is not aligned on word => no transfer possible with DMA peripheral access configured as word */ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; - + /* Process unlocked */ __HAL_UNLOCK(hqspi); } else { - hqspi->RxXferCount = (data_size >> 2); + hqspi->RxXferCount = (data_size >> 2U); } } - + else + { + /* Nothing to do */ + } + if (status == HAL_OK) { /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; - + /* Clear interrupt */ __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); @@ -1344,14 +1522,14 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /* Set the QSPI DMA transfer complete callback */ hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt; - + /* Set the QSPI DMA Half transfer complete callback */ hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt; - + /* Set the DMA error callback */ hqspi->hdma->XferErrorCallback = QSPI_DMAError; - - /* Clear the DMA abort callback */ + + /* Clear the DMA abort callback */ hqspi->hdma->XferAbortCallback = NULL; /* Configure the direction of the DMA */ @@ -1359,23 +1537,32 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction); /* Enable the DMA Channel */ - tmp = (uint32_t*)((void*)&pData); - HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize); - - /* Configure QSPI: CCR register with functional as indirect read */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); + if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize) == HAL_OK) + { + /* Configure QSPI: CCR register with functional as indirect read */ + MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); - /* Start the transfer by re-writing the address in AR register */ - WRITE_REG(hqspi->Instance->AR, addr_reg); + /* Start the transfer by re-writing the address in AR register */ + WRITE_REG(hqspi->Instance->AR, addr_reg); - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Enable the QSPI transfer error Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Enable the QSPI transfer error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + + /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + hqspi->State = HAL_QSPI_STATE_READY; - /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } } } else @@ -1389,7 +1576,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData } else { - status = HAL_BUSY; + status = HAL_BUSY; /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -1399,7 +1586,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData } /** - * @brief Configure the QSPI Automatic Polling Mode in blocking mode. + * @brief Configure the QSPI Automatic Polling Mode in blocking mode. * @param hqspi : QSPI handle * @param cmd : structure that contains the command configuration information. * @param cfg : structure that contains the polling configuration information. @@ -1409,9 +1596,9 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData */ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); - + /* Check the parameters */ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) @@ -1441,47 +1628,47 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy assert_param(IS_QSPI_INTERVAL(cfg->Interval)); assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize)); assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode)); - + /* Process locked */ __HAL_LOCK(hqspi); - + if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - + /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; - + /* Wait till BUSY flag reset */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); - + if (status == HAL_OK) { /* Configure QSPI: PSMAR register with the status match value */ WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); - + /* Configure QSPI: PSMKR register with the status mask value */ WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); - + /* Configure QSPI: PIR register with the interval value */ WRITE_REG(hqspi->Instance->PIR, cfg->Interval); - - /* Configure QSPI: CR register with Match mode and Automatic stop enabled + + /* Configure QSPI: CR register with Match mode and Automatic stop enabled (otherwise there will be an infinite loop in blocking mode) */ - MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), + MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE)); - + /* Call the configuration function */ cmd->NbData = cfg->StatusBytesSize; QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); - + /* Wait until SM flag is set to go back in idle state */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout); if (status == HAL_OK) { __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM); - + /* Update state */ hqspi->State = HAL_QSPI_STATE_READY; } @@ -1489,18 +1676,18 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy } else { - status = HAL_BUSY; + status = HAL_BUSY; } - + /* Process unlocked */ __HAL_UNLOCK(hqspi); - + /* Return function status */ - return status; + return status; } /** - * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. + * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. * @param hqspi : QSPI handle * @param cmd : structure that contains the command configuration information. * @param cfg : structure that contains the polling configuration information. @@ -1509,9 +1696,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy */ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); - + /* Check the parameters */ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) @@ -1542,35 +1729,35 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize)); assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode)); assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop)); - + /* Process locked */ __HAL_LOCK(hqspi); - + if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - + /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; - + /* Wait till BUSY flag reset */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); - + if (status == HAL_OK) { /* Configure QSPI: PSMAR register with the status match value */ WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); - + /* Configure QSPI: PSMKR register with the status mask value */ WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); - + /* Configure QSPI: PIR register with the interval value */ WRITE_REG(hqspi->Instance->PIR, cfg->Interval); - + /* Configure QSPI: CR register with Match mode and Automatic stop mode */ - MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), + MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), (cfg->MatchMode | cfg->AutomaticStop)); - + /* Clear interrupt */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM); @@ -1580,7 +1767,7 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman /* Process unlocked */ __HAL_UNLOCK(hqspi); - + /* Enable the QSPI Transfer Error and status match Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); @@ -1593,18 +1780,18 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman } else { - status = HAL_BUSY; - + status = HAL_BUSY; + /* Process unlocked */ __HAL_UNLOCK(hqspi); } - + /* Return function status */ - return status; + return status; } /** - * @brief Configure the Memory Mapped mode. + * @brief Configure the Memory Mapped mode. * @param hqspi : QSPI handle * @param cmd : structure that contains the command configuration information. * @param cfg : structure that contains the memory mapped configuration information. @@ -1613,9 +1800,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman */ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); - + /* Check the parameters */ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) @@ -1643,53 +1830,53 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation)); - + /* Process locked */ __HAL_LOCK(hqspi); - + if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - + /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED; - + /* Wait till BUSY flag reset */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); - + if (status == HAL_OK) { /* Configure QSPI: CR register with timeout counter enable */ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation); - + if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE) { assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod)); - + /* Configure QSPI: LPTR register with the low-power timeout value */ WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod); - + /* Clear interrupt */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO); /* Enable the QSPI TimeOut Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO); } - + /* Call the configuration function */ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED); } } else { - status = HAL_BUSY; + status = HAL_BUSY; } - + /* Process unlocked */ __HAL_UNLOCK(hqspi); - + /* Return function status */ - return status; + return status; } /** @@ -1757,14 +1944,14 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) * @param hqspi : QSPI handle * @retval None */ - __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) +__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); /* NOTE: This function should not be modified, when the callback is needed, the HAL_QSPI_TxCpltCallback could be implemented in the user file - */ + */ } /** @@ -1787,14 +1974,14 @@ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) * @param hqspi : QSPI handle * @retval None */ - __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) +__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); /* NOTE: This function should not be modified, when the callback is needed, the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file - */ + */ } /** @@ -1841,25 +2028,246 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) the HAL_QSPI_TimeOutCallback could be implemented in the user file */ } +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User QSPI Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hqspi : QSPI handle + * @param CallbackID : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID + * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID + * @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID + * @arg @ref HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID + * @arg @ref HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID + * @arg @ref HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID + * @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID QSPI Rx Half Complete Callback ID + * @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID QSPI Tx Half Complete Callback ID + * @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID + * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID + * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID + * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackID, pQSPI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + switch (CallbackID) + { + case HAL_QSPI_ERROR_CB_ID : + hqspi->ErrorCallback = pCallback; + break; + case HAL_QSPI_ABORT_CB_ID : + hqspi->AbortCpltCallback = pCallback; + break; + case HAL_QSPI_FIFO_THRESHOLD_CB_ID : + hqspi->FifoThresholdCallback = pCallback; + break; + case HAL_QSPI_CMD_CPLT_CB_ID : + hqspi->CmdCpltCallback = pCallback; + break; + case HAL_QSPI_RX_CPLT_CB_ID : + hqspi->RxCpltCallback = pCallback; + break; + case HAL_QSPI_TX_CPLT_CB_ID : + hqspi->TxCpltCallback = pCallback; + break; + case HAL_QSPI_RX_HALF_CPLT_CB_ID : + hqspi->RxHalfCpltCallback = pCallback; + break; + case HAL_QSPI_TX_HALF_CPLT_CB_ID : + hqspi->TxHalfCpltCallback = pCallback; + break; + case HAL_QSPI_STATUS_MATCH_CB_ID : + hqspi->StatusMatchCallback = pCallback; + break; + case HAL_QSPI_TIMEOUT_CB_ID : + hqspi->TimeOutCallback = pCallback; + break; + case HAL_QSPI_MSP_INIT_CB_ID : + hqspi->MspInitCallback = pCallback; + break; + case HAL_QSPI_MSP_DEINIT_CB_ID : + hqspi->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hqspi->State == HAL_QSPI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_QSPI_MSP_INIT_CB_ID : + hqspi->MspInitCallback = pCallback; + break; + case HAL_QSPI_MSP_DEINIT_CB_ID : + hqspi->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hqspi); + return status; +} + +/** + * @brief Unregister a User QSPI Callback + * QSPI Callback is redirected to the weak (surcharged) predefined callback + * @param hqspi : QSPI handle + * @param CallbackID : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID + * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID + * @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID + * @arg @ref HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID + * @arg @ref HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID + * @arg @ref HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID + * @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID QSPI Rx Half Complete Callback ID + * @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID QSPI Tx Half Complete Callback ID + * @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID + * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID + * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID + * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + switch (CallbackID) + { + case HAL_QSPI_ERROR_CB_ID : + hqspi->ErrorCallback = HAL_QSPI_ErrorCallback; + break; + case HAL_QSPI_ABORT_CB_ID : + hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback; + break; + case HAL_QSPI_FIFO_THRESHOLD_CB_ID : + hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback; + break; + case HAL_QSPI_CMD_CPLT_CB_ID : + hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback; + break; + case HAL_QSPI_RX_CPLT_CB_ID : + hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback; + break; + case HAL_QSPI_TX_CPLT_CB_ID : + hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback; + break; + case HAL_QSPI_RX_HALF_CPLT_CB_ID : + hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback; + break; + case HAL_QSPI_TX_HALF_CPLT_CB_ID : + hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback; + break; + case HAL_QSPI_STATUS_MATCH_CB_ID : + hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback; + break; + case HAL_QSPI_TIMEOUT_CB_ID : + hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback; + break; + case HAL_QSPI_MSP_INIT_CB_ID : + hqspi->MspInitCallback = HAL_QSPI_MspInit; + break; + case HAL_QSPI_MSP_DEINIT_CB_ID : + hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; + break; + default : + /* Update the error code */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hqspi->State == HAL_QSPI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_QSPI_MSP_INIT_CB_ID : + hqspi->MspInitCallback = HAL_QSPI_MspInit; + break; + case HAL_QSPI_MSP_DEINIT_CB_ID : + hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; + break; + default : + /* Update the error code */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hqspi); + return status; +} +#endif /** * @} */ -/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions - * @brief QSPI control and State functions +/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions + * @brief QSPI control and State functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control and State functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides a set of functions allowing to : - (+) Check in run-time the state of the driver. + (+) Check in run-time the state of the driver. (+) Check the error code set during last operation. (+) Abort any operation. - + @endverbatim * @{ */ @@ -1894,14 +2302,14 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) { HAL_StatusTypeDef status = HAL_OK; uint32_t tickstart = HAL_GetTick(); - + /* Check if the state is in one of the busy states */ - if ((hqspi->State & 0x2) != 0) + if (((uint32_t)hqspi->State & 0x2U) != 0U) { /* Process unlocked */ __HAL_UNLOCK(hqspi); - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -1912,24 +2320,27 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) { hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; } - } - + } + /* Configure QSPI: CR register with Abort request */ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); /* Wait until TC flag is set to go back in idle state */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); - if (status == HAL_OK) - { + if (status == HAL_OK) + { __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - + /* Wait until BUSY flag is reset */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); } if (status == HAL_OK) { + /* Reset functional mode configuration to indirect write mode by default */ + CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); + /* Update state */ hqspi->State = HAL_QSPI_STATE_READY; } @@ -1946,36 +2357,47 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) { HAL_StatusTypeDef status = HAL_OK; - + /* Check if the state is in one of the busy states */ - if ((hqspi->State & 0x2) != 0) + if (((uint32_t)hqspi->State & 0x2U) != 0U) { /* Process unlocked */ __HAL_UNLOCK(hqspi); /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_ABORT; + hqspi->State = HAL_QSPI_STATE_ABORT; /* Disable all interrupts */ __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE)); - - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0) + + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); /* Abort DMA channel */ hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt; - HAL_DMA_Abort_IT(hqspi->hdma); - } + if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK) + { + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + + /* Abort Complete callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->AbortCpltCallback(hqspi); +#else + HAL_QSPI_AbortCpltCallback(hqspi); +#endif + } + } else { /* Clear interrupt */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - + /* Enable the QSPI Transfer Complete Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); - + /* Configure QSPI: CR register with Abort request */ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); } @@ -2009,16 +2431,16 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t { /* Synchronize init structure with new FIFO threshold value */ hqspi->Init.FifoThreshold = Threshold; - + /* Configure QSPI FIFO Threshold */ - MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, - ((hqspi->Init.FifoThreshold - 1) << QUADSPI_CR_FTHRES_Pos)); + MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, + ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); } else { - status = HAL_BUSY; + status = HAL_BUSY; } - + /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -2032,51 +2454,102 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t */ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) { - return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1); + return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U); +} + +#if defined(QUADSPI_CR_DFM) +/** @brief Set FlashID. + * @param hqspi : QSPI handle. + * @param FlashID : Index of the flash memory to be accessed. + * This parameter can be a value of @ref QSPI_Flash_Select. + * @note The FlashID is ignored when dual flash mode is enabled. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameter */ + assert_param(IS_QSPI_FLASH_ID(FlashID)); + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + /* Synchronize init structure with new FlashID value */ + hqspi->Init.FlashID = FlashID; + + /* Configure QSPI FlashID */ + MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID); + } + else + { + status = HAL_BUSY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Return function status */ + return status; } +#endif +/** + * @} + */ + /** * @} */ +/** @defgroup QSPI_Private_Functions QSPI Private Functions + * @{ + */ + /** - * @brief DMA QSPI receive process complete callback. + * @brief DMA QSPI receive process complete callback. * @param hdma : DMA handle * @retval None */ -static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) +static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hqspi->RxXferCount = 0; - + QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); + hqspi->RxXferCount = 0U; + /* Enable the QSPI transfer complete Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); } /** - * @brief DMA QSPI transmit process complete callback. + * @brief DMA QSPI transmit process complete callback. * @param hdma : DMA handle * @retval None */ -static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) +static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hqspi->TxXferCount = 0; - + QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); + hqspi->TxXferCount = 0U; + /* Enable the QSPI transfer complete Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); } /** - * @brief DMA QSPI receive process half complete callback. + * @brief DMA QSPI receive process half complete callback. * @param hdma : DMA handle * @retval None */ static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); - HAL_QSPI_RxHalfCpltCallback(hqspi); +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->RxHalfCpltCallback(hqspi); +#else + HAL_QSPI_RxHalfCpltCallback(hqspi); +#endif } /** @@ -2086,9 +2559,13 @@ static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) */ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->TxHalfCpltCallback(hqspi); +#else HAL_QSPI_TxHalfCpltCallback(hqspi); +#endif } /** @@ -2096,19 +2573,33 @@ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) * @param hdma : DMA handle * @retval None */ -static void QSPI_DMAError(DMA_HandleTypeDef *hdma) +static void QSPI_DMAError(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent); - hqspi->RxXferCount = 0; - hqspi->TxXferCount = 0; + hqspi->RxXferCount = 0U; + hqspi->TxXferCount = 0U; hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; - + /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); /* Abort the QSPI */ - HAL_QSPI_Abort_IT(hqspi); + if (HAL_QSPI_Abort_IT(hqspi) != HAL_OK) + { + /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */ + __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); + + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + + /* Error callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->ErrorCallback(hqspi); +#else + HAL_QSPI_ErrorCallback(hqspi); +#endif + } } /** @@ -2116,22 +2607,22 @@ static void QSPI_DMAError(DMA_HandleTypeDef *hdma) * @param hdma : DMA handle * @retval None */ -static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) +static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent); - hqspi->RxXferCount = 0; - hqspi->TxXferCount = 0; + hqspi->RxXferCount = 0U; + hqspi->TxXferCount = 0U; if(hqspi->State == HAL_QSPI_STATE_ABORT) { /* DMA Abort called by QSPI abort */ /* Clear interrupt */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - + /* Enable the QSPI Transfer Complete Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); - + /* Configure QSPI: CR register with Abort request */ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); } @@ -2142,7 +2633,11 @@ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) hqspi->State = HAL_QSPI_STATE_READY; /* Error callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->ErrorCallback(hqspi); +#else HAL_QSPI_ErrorCallback(hqspi); +#endif } } @@ -2151,24 +2646,24 @@ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) * @param hqspi : QSPI handle * @param Flag : Flag checked * @param State : Value of the flag expected + * @param Tickstart : Tick start value * @param Timeout : Duration of the timeout - * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout) { - /* Wait until flag is in expected state */ + /* Wait until flag is in expected state */ while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State) { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - Tickstart) > Timeout)) + if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { hqspi->State = HAL_QSPI_STATE_ERROR; hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; - + return HAL_ERROR; } } @@ -2195,7 +2690,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)) { /* Configure QSPI: DLR register with the number of data to read or write */ - WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1)); + WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U)); } if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) @@ -2209,10 +2704,10 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin { /*---- Command with instruction, address and alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateBytesSize | cmd->AlternateByteMode | - cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateBytesSize | cmd->AlternateByteMode | + cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) @@ -2225,10 +2720,10 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin { /*---- Command with instruction and alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateBytesSize | cmd->AlternateByteMode | - cmd->AddressMode | cmd->InstructionMode | + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateBytesSize | cmd->AlternateByteMode | + cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); } } @@ -2238,9 +2733,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin { /*---- Command with instruction and address ----*/ /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) @@ -2253,9 +2748,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin { /*---- Command with only instruction ----*/ /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateByteMode | cmd->AddressMode | + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); } } @@ -2271,10 +2766,10 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin { /*---- Command with address and alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateBytesSize | cmd->AlternateByteMode | - cmd->AddressSize | cmd->AddressMode | + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateBytesSize | cmd->AlternateByteMode | + cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) @@ -2287,9 +2782,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin { /*---- Command with only alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateBytesSize | cmd->AlternateByteMode | + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateBytesSize | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); } } @@ -2299,9 +2794,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin { /*---- Command with only address ----*/ /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateByteMode | cmd->AddressSize | + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) @@ -2316,9 +2811,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin if (cmd->DataMode != QSPI_DATA_NONE) { /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateByteMode | cmd->AddressMode | + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); } } @@ -2326,6 +2821,10 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin } } +/** + * @} + */ + /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c index 73aa95a0e4..91ca75f688 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c @@ -399,10 +399,15 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - uint32_t tickstart = 0; + uint32_t tickstart; + + /* Check Null pointer */ + if(RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } /* Check the parameters */ - assert_param(RCC_OscInitStruct != NULL); assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*----------------------------- MSI Configuration --------------------------*/ @@ -935,14 +940,19 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { - uint32_t tickstart = 0; + uint32_t tickstart; #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) uint32_t pllfreq = 0; uint32_t hpre = RCC_SYSCLK_DIV1; #endif + /* Check Null pointer */ + if(RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ - assert_param(RCC_ClkInitStruct != NULL); assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); assert_param(IS_FLASH_LATENCY(FLatency)); @@ -951,14 +961,14 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ - if(FLatency > READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)) + if(FLatency > __HAL_FLASH_GET_LATENCY()) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) != FLatency) + if(__HAL_FLASH_GET_LATENCY() != FLatency) { return HAL_ERROR; } @@ -1041,47 +1051,11 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /* Get Start Tick*/ tickstart = HAL_GetTick(); - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } + return HAL_TIMEOUT; } } } @@ -1104,14 +1078,14 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui #endif /* Decreasing the number of wait states because of lower CPU frequency */ - if(FLatency < READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)) + if(FLatency < __HAL_FLASH_GET_LATENCY()) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) != FLatency) + if(__HAL_FLASH_GET_LATENCY() != FLatency) { return HAL_ERROR; } @@ -1193,11 +1167,15 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui void HAL_RCC_MCOConfig( uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) { GPIO_InitTypeDef GPIO_InitStruct; + /* Check the parameters */ assert_param(IS_RCC_MCO(RCC_MCOx)); assert_param(IS_RCC_MCODIV(RCC_MCODiv)); assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(RCC_MCOx); + /* MCO Clock Enable */ __MCO1_CLK_ENABLE(); @@ -1509,7 +1487,7 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF RCC_ClkInitStruct->APB2CLKDivider = (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U); /* Get the Flash Wait State (Latency) configuration ------------------------*/ - *pFLatency = READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY); + *pFLatency = __HAL_FLASH_GET_LATENCY(); } /** @@ -1652,7 +1630,7 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) != latency) + if(__HAL_FLASH_GET_LATENCY() != latency) { return HAL_ERROR; } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c index 14c6f7279e..7896c12fc5 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c @@ -1200,11 +1200,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) pllvco = 0U; } -#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); -#endif - switch(PeriphClk) { #if defined(SAI2) @@ -1257,6 +1252,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI3CLK) != RESET) { + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; #if defined(RCC_PLLP_DIV_2_31_SUPPORT) @@ -1281,8 +1278,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET) { #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ /* f(PLLSAI1 Source) / PLLSAI1M */ pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); +#else + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); #endif /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */ plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; @@ -1318,6 +1319,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI2CLK) != RESET) { + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); /* f(PLLSAI2CLK) = f(VCO input) * PLLN / PLLP */ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; #if defined(RCC_PLLP_DIV_2_31_SUPPORT) @@ -1353,8 +1356,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET) { #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ /* f(PLLSAI1 Source) / PLLSAI1M */ pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); +#else + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); #endif /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */ plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; @@ -1395,8 +1402,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_SAI2CLK) != RESET) { #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* PLLSAI2M exists: apply PLLSAI2M divider for PLLSAI2 output computation */ /* f(PLLSAI2 Source) / PLLSAI2M */ pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)); +#else + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); #endif /* f(PLLSAI2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2P */ plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; @@ -1460,10 +1471,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) || defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) /* f(PLL Source) / PLLM */ pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); -#endif /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); @@ -1478,8 +1487,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN)) { #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ /* f(PLLSAI1 Source) / PLLSAI1M */ pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); +#else + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); #endif /* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */ plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; @@ -1515,10 +1528,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)) { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) || defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) /* f(PLL Source) / PLLM */ pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); -#endif /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; #if defined(RCC_PLLP_DIV_2_31_SUPPORT) @@ -1562,10 +1573,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) || defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) /* f(PLL Source) / PLLM */ pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); -#endif /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); @@ -1580,8 +1589,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN)) { #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ /* f(PLLSAI1 Source) / PLLSAI1M */ pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); +#else + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); #endif /* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */ plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; @@ -1792,8 +1805,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_ADC1CLK) != RESET) { #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ /* f(PLLSAI1 Source) / PLLSAI1M */ pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); +#else + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); #endif /* f(PLLADC1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1R */ plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; @@ -1806,8 +1823,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_ADC2CLK) != RESET) { #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* PLLSAI2M exists: apply PLLSAI2M divider for PLLSAI2 output computation */ /* f(PLLSAI2 Source) / PLLSAI2M */ pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)); +#else + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); #endif /* f(PLLADC2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2R */ plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c index d48a0b855d..9647b2cd7d 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c @@ -23,6 +23,60 @@ random data using (polling/interrupt) mode. (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function. + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_RNG_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_RNG_RegisterCallback() to register a user callback. + Function @ref HAL_RNG_RegisterCallback() allows to register following callbacks: + (+) ErrorCallback : RNG Error Callback. + (+) MspInitCallback : RNG MspInit. + (+) MspDeInitCallback : RNG MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function @ref HAL_RNG_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) ErrorCallback : RNG Error Callback. + (+) MspInitCallback : RNG MspInit. + (+) MspDeInitCallback : RNG MspDeInit. + + [..] + For specific callback ReadyDataCallback, use dedicated register callbacks: + respectively @ref HAL_RNG_RegisterReadyDataCallback() , @ref HAL_RNG_UnRegisterReadyDataCallback(). + + [..] + By default, after the @ref HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET + all callbacks are set to the corresponding weak (surcharged) functions: + example @ref HAL_RNG_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_RNG_Init() + and @ref HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_RNG_Init() and @ref HAL_RNG_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_RNG_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_RNG_RegisterCallback() before calling @ref HAL_RNG_DeInit() + or @ref HAL_RNG_Init() function. + + [..] + When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak (surcharged) callbacks are used. + @endverbatim ****************************************************************************** * @attention @@ -126,6 +180,24 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) assert_param(IS_RNG_CED(hrng->Init.ClockErrorDetection)); #endif /* defined(RNG_CR_CED) */ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + if(hrng->State == HAL_RNG_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrng->Lock = HAL_UNLOCKED; + + hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback */ + hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */ + + if(hrng->MspInitCallback == NULL) + { + hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hrng->MspInitCallback(hrng); + } +#else if(hrng->State == HAL_RNG_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -134,6 +206,7 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Init the low level hardware */ HAL_RNG_MspInit(hrng); } +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_BUSY; @@ -149,6 +222,9 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; + /* Initialise the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_NONE; + /* Return function status */ return HAL_OK; } @@ -177,12 +253,25 @@ HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng) /* Clear RNG interrupt status flags */ CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS); +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + if(hrng->MspDeInitCallback == NULL) + { + hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hrng->MspDeInitCallback(hrng); +#else /* DeInit the low level hardware */ HAL_RNG_MspDeInit(hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ /* Update the RNG state */ hrng->State = HAL_RNG_STATE_RESET; + /* Initialise the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_NONE; + /* Release Lock */ __HAL_UNLOCK(hrng); @@ -220,6 +309,233 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) */ } +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User RNG Callback + * To be used instead of the weak predefined callback + * @param hrng RNG handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID + * @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hrng); + + if(HAL_RNG_STATE_READY == hrng->State) + { + switch (CallbackID) + { + case HAL_RNG_ERROR_CB_ID : + hrng->ErrorCallback = pCallback; + break; + + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = pCallback; + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_RNG_STATE_RESET == hrng->State) + { + switch (CallbackID) + { + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = pCallback; + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrng); + return status; +} + +/** + * @brief Unregister an RNG Callback + * RNG callabck is redirected to the weak predefined callback + * @param hrng RNG handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID + * @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID) +{ +HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hrng); + + if(HAL_RNG_STATE_READY == hrng->State) + { + switch (CallbackID) + { + case HAL_RNG_ERROR_CB_ID : + hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_RNG_STATE_RESET == hrng->State) + { + switch (CallbackID) + { + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspInit */ + break; + + default : + /* Update the error code */ + hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrng); + return status; +} + +/** + * @brief Register Data Ready RNG Callback + * To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback + * @param hrng RNG handle + * @param pCallback pointer to the Data Ready Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hrng); + + if(HAL_RNG_STATE_READY == hrng->State) + { + hrng->ReadyDataCallback = pCallback; + } + else + { + /* Update the error code */ + hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrng); + return status; +} + +/** + * @brief UnRegister the Data Ready RNG Callback + * Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback + * @param hrng RNG handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hrng); + + if(HAL_RNG_STATE_READY == hrng->State) + { + hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback */ + } + else + { + /* Update the error code */ + hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrng); + return status; +} + +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + /** * @} */ @@ -346,8 +662,7 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng) * not have enough entropy. In this case, it is recommended to clear the * SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable * the RNG peripheral to reinitialize and restart the RNG. - * @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS - * or CEIS are set. + * @note RNG ErrorCallback() API is called once whether SEIS or CEIS are set. * @param hrng: pointer to a RNG_HandleTypeDef structure. * @retval None @@ -360,7 +675,13 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_ERROR; +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + /* Call registered Error callback */ + hrng->ErrorCallback(hrng); +#else + /* Call legacy weak Error callback */ HAL_RNG_ErrorCallback(hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ /* Clear the clock error flag */ __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI); @@ -381,8 +702,13 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_READY; - /* Data Ready callback */ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + /* Call registered Data Ready callback */ + hrng->ReadyDataCallback(hrng, hrng->RandomNumber); +#else + /* Call legacy weak Data Ready callback */ HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ } } } @@ -486,10 +812,12 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) * @verbatim =============================================================================== - ##### Peripheral State functions ##### + ##### Peripheral State and Error functions ##### =============================================================================== [..] - This subsection permits to get in run-time the status of the peripheral. + This subsection permits to : + (+) Return in run-time the status of the peripheral. + (+) Return the RNG handle error code @endverbatim * @{ @@ -506,6 +834,16 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) return hrng->State; } +/** + * @brief Return the RNG handle error code. + * @param hrng: pointer to a RNG_HandleTypeDef structure. + * @retval RNG Error Code +*/ +uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng) +{ + /* Return RNG Error Code */ + return hrng->ErrorCode; +} /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c index 6db81ac319..e3c0973532 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c @@ -84,6 +84,62 @@ Wakeup from STOP and Standby modes is possible only when the RTC clock source is LSE or LSI. + *** Callback registration *** + ============================================= + + The compilation define USE_RTC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback. + + Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks: + (+) AlarmAEventCallback : RTC Alarm A Event callback. + (+) AlarmBEventCallback : RTC Alarm B Event callback. + (+) TimeStampEventCallback : RTC TimeStamp Event callback. + (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. + (+) Tamper1EventCallback : RTC Tamper 1 Event callback. + (+) Tamper2EventCallback : RTC Tamper 2 Event callback. + (+) Tamper3EventCallback : RTC Tamper 3 Event callback. + (+) MspInitCallback : RTC MspInit callback. + (+) MspDeInitCallback : RTC MspDeInit callback. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) AlarmAEventCallback : RTC Alarm A Event callback. + (+) AlarmBEventCallback : RTC Alarm B Event callback. + (+) TimeStampEventCallback : RTC TimeStamp Event callback. + (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. + (+) Tamper1EventCallback : RTC Tamper 1 Event callback. + (+) Tamper2EventCallback : RTC Tamper 2 Event callback. + (+) Tamper3EventCallback : RTC Tamper 3 Event callback. + (+) MspInitCallback : RTC MspInit callback. + (+) MspDeInitCallback : RTC MspDeInit callback. + + By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, + all callbacks are set to the corresponding weak functions : + examples @ref AlarmAEventCallback(), @ref TimeStampEventCallback(). + Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function + in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null + (not registered beforehand). + If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit() + or @ref HAL_RTC_Init() function. + + When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + @endverbatim ****************************************************************************** @@ -199,6 +255,37 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + if(hrtc->State == HAL_RTC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + + hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ + hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */ + hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ + hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ +#if defined(RTC_TAMPER1_SUPPORT) + hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ +#endif /* RTC_TAMPER1_SUPPORT */ + hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ +#if defined(RTC_TAMPER3_SUPPORT) + hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ +#endif /* RTC_TAMPER3_SUPPORT */ + + if(hrtc->MspInitCallback == NULL) + { + hrtc->MspInitCallback = HAL_RTC_MspInit; + } + /* Init the low level hardware */ + hrtc->MspInitCallback(hrtc); + + if(hrtc->MspDeInitCallback == NULL) + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + } +#else if(hrtc->State == HAL_RTC_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -207,6 +294,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); } +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; @@ -359,8 +447,19 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + if(hrtc->MspDeInitCallback == NULL) + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + + /* DeInit the low level hardware: CLOCK, NVIC.*/ + hrtc->MspDeInitCallback(hrtc); + +#else /* De-Initialize RTC MSP */ HAL_RTC_MspDeInit(hrtc); +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ hrtc->State = HAL_RTC_STATE_RESET; @@ -370,6 +469,222 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) return HAL_OK; } +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User RTC Callback + * To be used instead of the weak predefined callback + * @param hrtc RTC handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID + * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID + * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID + * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID + * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID + * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID + * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID + * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hrtc); + + if(HAL_RTC_STATE_READY == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_ALARM_A_EVENT_CB_ID : + hrtc->AlarmAEventCallback = pCallback; + break; + + case HAL_RTC_ALARM_B_EVENT_CB_ID : + hrtc->AlarmBEventCallback = pCallback; + break; + + case HAL_RTC_TIMESTAMP_EVENT_CB_ID : + hrtc->TimeStampEventCallback = pCallback; + break; + + case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : + hrtc->WakeUpTimerEventCallback = pCallback; + break; + +#if defined(RTC_TAMPER1_SUPPORT) + case HAL_RTC_TAMPER1_EVENT_CB_ID : + hrtc->Tamper1EventCallback = pCallback; + break; +#endif /* RTC_TAMPER1_SUPPORT */ + + case HAL_RTC_TAMPER2_EVENT_CB_ID : + hrtc->Tamper2EventCallback = pCallback; + break; + +#if defined(RTC_TAMPER3_SUPPORT) + case HAL_RTC_TAMPER3_EVENT_CB_ID : + hrtc->Tamper3EventCallback = pCallback; + break; +#endif /* RTC_TAMPER3_SUPPORT */ + + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = pCallback; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_RTC_STATE_RESET == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = pCallback; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + return status; +} + +/** + * @brief Unregister an RTC Callback + * RTC callabck is redirected to the weak predefined callback + * @param hrtc RTC handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID + * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID + * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID + * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID + * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID + * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID + * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID + * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hrtc); + + if(HAL_RTC_STATE_READY == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_ALARM_A_EVENT_CB_ID : + hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ + break; + + case HAL_RTC_ALARM_B_EVENT_CB_ID : + hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */ + break; + + case HAL_RTC_TIMESTAMP_EVENT_CB_ID : + hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ + break; + + case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : + hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ + break; + +#if defined(RTC_TAMPER1_SUPPORT) + case HAL_RTC_TAMPER1_EVENT_CB_ID : + hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ + break; +#endif /* RTC_TAMPER1_SUPPORT */ + + case HAL_RTC_TAMPER2_EVENT_CB_ID : + hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ + break; + +#if defined(RTC_TAMPER3_SUPPORT) + case HAL_RTC_TAMPER3_EVENT_CB_ID : + hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ + break; +#endif /* RTC_TAMPER3_SUPPORT */ + + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = HAL_RTC_MspInit; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_RTC_STATE_RESET == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = HAL_RTC_MspInit; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + return status; +} +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + /** * @brief Initialize the RTC MSP. * @param hrtc: RTC handle @@ -1302,7 +1617,11 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); /* AlarmA callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->AlarmAEventCallback(hrtc); +#else HAL_RTC_AlarmAEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } /* Get the AlarmB interrupt source enable status and pending flag status*/ @@ -1312,7 +1631,11 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); /* AlarmB callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->AlarmBEventCallback(hrtc); +#else HAL_RTCEx_AlarmBEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c index fa70fe29f0..3eb3933ba6 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c @@ -208,6 +208,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(RTC_TimeStampPin); + /* Process Locked */ __HAL_LOCK(hrtc); @@ -264,6 +267,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(RTC_TimeStampPin); + /* Process Locked */ __HAL_LOCK(hrtc); @@ -718,7 +724,11 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) if((__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET) && (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET)) { /* TIMESTAMP callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->TimeStampEventCallback(hrtc); +#else HAL_RTCEx_TimeStampEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ /* Clear the TIMESTAMP interrupt pending bit (this will clear timestamp time and date registers) */ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); @@ -732,7 +742,11 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); /* Tamper1 callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->Tamper1EventCallback(hrtc); +#else HAL_RTCEx_Tamper1EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } #endif /* RTC_TAMPER1_SUPPORT */ @@ -743,7 +757,11 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); /* Tamper2 callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->Tamper2EventCallback(hrtc); +#else HAL_RTCEx_Tamper2EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } #if defined(RTC_TAMPER3_SUPPORT) @@ -754,7 +772,11 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); /* Tamper3 callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->Tamper3EventCallback(hrtc); +#else HAL_RTCEx_Tamper3EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } #endif /* RTC_TAMPER3_SUPPORT */ @@ -1256,7 +1278,11 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); /* WAKEUPTIMER callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->WakeUpTimerEventCallback(hrtc); +#else HAL_RTCEx_WakeUpTimerEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } /* Change RTC state */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c index 6966858816..b7c037cc39 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c @@ -94,7 +94,7 @@ (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT() (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can add his own code by customization of function pointer HAL_SAI_RxCpltCallback() - (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can + (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_SAI_ErrorCallback() *** DMA mode IO operation *** @@ -137,6 +137,58 @@ enabled or disabled (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not + *** Callback registration *** + ============================= + + The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use functions @ref HAL_SAI_RegisterCallback() to register a user callback. + + Function @ref HAL_SAI_RegisterCallback() allows to register following callbacks: + (+) RxCpltCallback : SAI receive complete. + (+) RxHalfCpltCallback : SAI receive half complete. + (+) TxCpltCallback : SAI transmit complete. + (+) TxHalfCpltCallback : SAI transmit half complete. + (+) ErrorCallback : SAI error. + (+) MspInitCallback : SAI MspInit. + (+) MspDeInitCallback : SAI MspDeInit. + This function takes as parameters the HAL peripheral handle, the callback ID + and a pointer to the user callback function. + + Use function @ref HAL_SAI_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the callback ID. + This function allows to reset following callbacks: + (+) RxCpltCallback : SAI receive complete. + (+) RxHalfCpltCallback : SAI receive half complete. + (+) TxCpltCallback : SAI transmit complete. + (+) TxHalfCpltCallback : SAI transmit half complete. + (+) ErrorCallback : SAI error. + (+) MspInitCallback : SAI MspInit. + (+) MspDeInitCallback : SAI MspDeInit. + + By default, after the @ref HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions: + examples @ref HAL_SAI_RxCpltCallback(), @ref HAL_SAI_ErrorCallback(). + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_SAI_Init + and @ref HAL_SAI_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_SAI_Init and @ref HAL_SAI_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_SAI_RegisterCallback before calling @ref HAL_SAI_DeInit + or @ref HAL_SAI_Init function. + + When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + @endverbatim ****************************************************************************** * @attention @@ -183,27 +235,25 @@ #ifdef HAL_SAI_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ - /** @defgroup SAI_Private_Typedefs SAI Private Typedefs * @{ */ -typedef enum { +typedef enum +{ SAI_MODE_DMA, SAI_MODE_IT -}SAI_ModeTypedef; +} SAI_ModeTypedef; /** * @} */ /* Private define ------------------------------------------------------------*/ - /** @defgroup SAI_Private_Constants SAI Private Constants * @{ */ -#define SAI_FIFO_SIZE 8 -#define SAI_DEFAULT_TIMEOUT 4 -#define SAI_LONG_TIMEOUT 1000 - +#define SAI_FIFO_SIZE 8 +#define SAI_DEFAULT_TIMEOUT 4U +#define SAI_LONG_TIMEOUT 1000U /** * @} */ @@ -211,12 +261,11 @@ typedef enum { /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ - /** @defgroup SAI_Private_Functions SAI Private Functions * @{ */ static void SAI_FillFifo(SAI_HandleTypeDef *hsai); -static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode); +static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode); static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); @@ -239,14 +288,13 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma); */ /* Exported functions ---------------------------------------------------------*/ - /** @defgroup SAI_Exported_Functions SAI Exported Functions * @{ */ /** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -281,7 +329,7 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma); * Init according to the specified parameters and call the function * HAL_SAI_Init to initialize the SAI block. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param protocol one of the supported protocol @ref SAI_Protocol * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize * the configuration information for SAI module. @@ -290,33 +338,33 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma); */ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) { - HAL_StatusTypeDef status = HAL_OK; - + HAL_StatusTypeDef status; + /* Check the parameters */ assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol)); assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize)); - - switch(protocol) - { - case SAI_I2S_STANDARD : - case SAI_I2S_MSBJUSTIFIED : - case SAI_I2S_LSBJUSTIFIED : - status = SAI_InitI2S(hsai, protocol, datasize, nbslot); - break; - case SAI_PCM_LONG : - case SAI_PCM_SHORT : - status = SAI_InitPCM(hsai, protocol, datasize, nbslot); - break; - default : - status = HAL_ERROR; - break; + + switch (protocol) + { + case SAI_I2S_STANDARD : + case SAI_I2S_MSBJUSTIFIED : + case SAI_I2S_LSBJUSTIFIED : + status = SAI_InitI2S(hsai, protocol, datasize, nbslot); + break; + case SAI_PCM_LONG : + case SAI_PCM_SHORT : + status = SAI_InitPCM(hsai, protocol, datasize, nbslot); + break; + default : + status = HAL_ERROR; + break; } - - if(status == HAL_OK) + + if (status == HAL_OK) { status = HAL_SAI_Init(hsai); } - + return status; } @@ -324,24 +372,24 @@ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protoco * @brief Initialize the SAI according to the specified parameters. * in the SAI_InitTypeDef structure and initialize the associated handle. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) { - uint32_t tmpregisterGCR = 0; - uint32_t ckstr_bits = 0; - uint32_t syncen_bits = 0; - + uint32_t tmpregisterGCR; + uint32_t ckstr_bits; + uint32_t syncen_bits; + /* Check the SAI handle allocation */ - if(hsai == NULL) + if (hsai == NULL) { return HAL_ERROR; } - + /* check the instance */ assert_param(IS_SAI_ALL_INSTANCE(hsai->Instance)); - + /* Check the SAI Block parameters */ assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency)); assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol)); @@ -360,54 +408,73 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) assert_param(IS_SAI_BLOCK_MCK_OVERSAMPLING(hsai->Init.MckOverSampling)); #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + /* Check the SAI Block Frame parameters */ assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength)); assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength)); assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition)); assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity)); assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset)); - + /* Check the SAI Block Slot parameters */ assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset)); assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize)); assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber)); assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive)); - + #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Check the SAI PDM parameters */ assert_param(IS_FUNCTIONAL_STATE(hsai->Init.PdmInit.Activation)); - if(hsai->Init.PdmInit.Activation == ENABLE) + if (hsai->Init.PdmInit.Activation == ENABLE) { assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(hsai->Init.PdmInit.MicPairsNbr)); assert_param(IS_SAI_PDM_CLOCK_ENABLE(hsai->Init.PdmInit.ClockEnable)); /* Check that SAI sub-block is SAI1 sub-block A, in master RX mode with free protocol */ - if((hsai->Instance != SAI1_Block_A) || - (hsai->Init.AudioMode != SAI_MODEMASTER_RX) || - (hsai->Init.Protocol != SAI_FREE_PROTOCOL)) + if ((hsai->Instance != SAI1_Block_A) || + (hsai->Init.AudioMode != SAI_MODEMASTER_RX) || + (hsai->Init.Protocol != SAI_FREE_PROTOCOL)) { return HAL_ERROR; } } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - - if(hsai->State == HAL_SAI_STATE_RESET) + + if (hsai->State == HAL_SAI_STATE_RESET) { /* Allocate lock resource and initialize it */ hsai->Lock = HAL_UNLOCKED; - + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + /* Reset callback pointers to the weak predefined callbacks */ + hsai->RxCpltCallback = HAL_SAI_RxCpltCallback; + hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback; + hsai->TxCpltCallback = HAL_SAI_TxCpltCallback; + hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback; + hsai->ErrorCallback = HAL_SAI_ErrorCallback; + + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + if (hsai->MspInitCallback == NULL) + { + hsai->MspInitCallback = HAL_SAI_MspInit; + } + hsai->MspInitCallback(hsai); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_SAI_MspInit(hsai); +#endif } - - hsai->State = HAL_SAI_STATE_BUSY; - + /* Disable the selected SAI peripheral */ - SAI_Disable(hsai); - + if (SAI_Disable(hsai) != HAL_OK) + { + return HAL_ERROR; + } + + hsai->State = HAL_SAI_STATE_BUSY; + /* SAI Block Synchro Configuration -----------------------------------------*/ /* This setting must be done with both audio block (A & B) disabled */ - switch(hsai->Init.SynchroExt) + switch (hsai->Init.SynchroExt) { case SAI_SYNCEXT_DISABLE : tmpregisterGCR = 0; @@ -418,105 +485,106 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) case SAI_SYNCEXT_OUTBLOCKB_ENABLE : tmpregisterGCR = SAI_GCR_SYNCOUT_1; break; + default : + tmpregisterGCR = 0; + break; } - - switch(hsai->Init.Synchro) + + switch (hsai->Init.Synchro) { case SAI_ASYNCHRONOUS : - { - syncen_bits = 0; - } + syncen_bits = 0; break; case SAI_SYNCHRONOUS : - { - syncen_bits = SAI_xCR1_SYNCEN_0; - } + syncen_bits = SAI_xCR1_SYNCEN_0; break; case SAI_SYNCHRONOUS_EXT_SAI1 : - { - syncen_bits = SAI_xCR1_SYNCEN_1; - } + syncen_bits = SAI_xCR1_SYNCEN_1; break; case SAI_SYNCHRONOUS_EXT_SAI2 : - { - syncen_bits = SAI_xCR1_SYNCEN_1; - tmpregisterGCR |= SAI_GCR_SYNCIN_0; - } + syncen_bits = SAI_xCR1_SYNCEN_1; + tmpregisterGCR |= SAI_GCR_SYNCIN_0; + break; + default : + syncen_bits = 0; break; } - + #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ defined(STM32L496xx) || defined(STM32L4A6xx) || \ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - - if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B)) + + if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B)) { SAI1->GCR = tmpregisterGCR; } - else + else { SAI2->GCR = tmpregisterGCR; } - + #else - + SAI1->GCR = tmpregisterGCR; - + #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - - if(hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV) + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + + if (hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV) { - uint32_t freq = 0; + uint32_t freq; uint32_t tmpval; - + /* In this case, the MCKDIV value is calculated to get AudioFrequency */ #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ defined(STM32L496xx) || defined(STM32L4A6xx) || \ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - - if((hsai->Instance == SAI1_Block_A ) || (hsai->Instance == SAI1_Block_B )) + + if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B)) { freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1); } - if((hsai->Instance == SAI2_Block_A ) || (hsai->Instance == SAI2_Block_B )) + else { + /* SAI2_Block_A or SAI2_Block_B */ freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2); } - + #else - + freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1); - + #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Configure Master Clock Divider using the following formula : - If NOMCK = 1 : MCKDIV[5:0] = SAI_CK_x / (FS * (FRL + 1)) - If NOMCK = 0 : MCKDIV[5:0] = SAI_CK_x / (FS * (OSR + 1) * 256) */ - if(hsai->Init.NoDivider == SAI_MASTERDIVIDER_DISABLE) - { /* NOMCK = 1 */ + if (hsai->Init.NoDivider == SAI_MASTERDIVIDER_DISABLE) + { + /* NOMCK = 1 */ /* (freq x 10) to keep Significant digits */ - tmpval = (freq * 10) / (hsai->Init.AudioFrequency * hsai->FrameInit.FrameLength); + tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * hsai->FrameInit.FrameLength); } else - { /* NOMCK = 0 */ + { + /* NOMCK = 0 */ uint32_t tmposr; - tmposr = (hsai->Init.MckOverSampling == SAI_MCK_OVERSAMPLING_ENABLE) ? 2 : 1; + tmposr = (hsai->Init.MckOverSampling == SAI_MCK_OVERSAMPLING_ENABLE) ? 2U : 1U; /* (freq x 10) to keep Significant digits */ - tmpval = (freq * 10) / (hsai->Init.AudioFrequency * tmposr * 256); + tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * tmposr * 256U); } - hsai->Init.Mckdiv = tmpval / 10; - + hsai->Init.Mckdiv = tmpval / 10U; + /* Round result to the nearest integer */ - if((tmpval % 10) > 8) + if ((tmpval % 10U) > 8U) { - hsai->Init.Mckdiv+= 1; + hsai->Init.Mckdiv += 1U; } #else /* Configure Master Clock using the following formula : @@ -524,167 +592,186 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) FS = SAI_CK_x / (MCKDIV[3:0] * 2) * 256 MCKDIV[3:0] = SAI_CK_x / FS * 512 */ /* (freq x 10) to keep Significant digits */ - tmpval = (freq * 10) / (hsai->Init.AudioFrequency * 2 * 256); - hsai->Init.Mckdiv = tmpval / 10; - + tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * 2U * 256U); + hsai->Init.Mckdiv = tmpval / 10U; + /* Round result to the nearest integer */ - if((tmpval % 10) > 8) + if ((tmpval % 10U) > 8U) { - hsai->Init.Mckdiv+= 1; + hsai->Init.Mckdiv += 1U; } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ } - + /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */ - if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) - { /* Transmit */ - ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0 : SAI_xCR1_CKSTR; + if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) + { + /* Transmit */ + ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0U : SAI_xCR1_CKSTR; } else - { /* Receive */ - ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0; + { + /* Receive */ + ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0U; } - + /* SAI Block Configuration -------------------------------------------------*/ /* SAI CR1 Configuration */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - hsai->Instance->CR1&=~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \ - SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\ - SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \ - SAI_xCR1_NOMCK | SAI_xCR1_MCKDIV | SAI_xCR1_OSR); - - hsai->Instance->CR1|=(hsai->Init.AudioMode | hsai->Init.Protocol | \ - hsai->Init.DataSize | hsai->Init.FirstBit | \ - ckstr_bits | syncen_bits | \ - hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \ - hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) | \ - hsai->Init.MckOverSampling); + hsai->Instance->CR1 &= ~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \ + SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN | \ + SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \ + SAI_xCR1_NOMCK | SAI_xCR1_MCKDIV | SAI_xCR1_OSR); + + hsai->Instance->CR1 |= (hsai->Init.AudioMode | hsai->Init.Protocol | \ + hsai->Init.DataSize | hsai->Init.FirstBit | \ + ckstr_bits | syncen_bits | \ + hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \ + hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) | \ + hsai->Init.MckOverSampling); #else - hsai->Instance->CR1&=~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \ - SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\ - SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \ - SAI_xCR1_NODIV | SAI_xCR1_MCKDIV); - - hsai->Instance->CR1|=(hsai->Init.AudioMode | hsai->Init.Protocol | \ - hsai->Init.DataSize | hsai->Init.FirstBit | \ - ckstr_bits | syncen_bits | \ - hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \ - hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20)); + hsai->Instance->CR1 &= ~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \ + SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN | \ + SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \ + SAI_xCR1_NODIV | SAI_xCR1_MCKDIV); + + hsai->Instance->CR1 |= (hsai->Init.AudioMode | hsai->Init.Protocol | \ + hsai->Init.DataSize | hsai->Init.FirstBit | \ + ckstr_bits | syncen_bits | \ + hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \ + hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20)); #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + /* SAI CR2 Configuration */ - hsai->Instance->CR2&= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL); - hsai->Instance->CR2|= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState); - + hsai->Instance->CR2 &= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL); + hsai->Instance->CR2 |= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState); + /* SAI Frame Configuration -----------------------------------------*/ - hsai->Instance->FRCR&=(~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \ - SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF)); - hsai->Instance->FRCR|=((hsai->FrameInit.FrameLength - 1) | - hsai->FrameInit.FSOffset | - hsai->FrameInit.FSDefinition | - hsai->FrameInit.FSPolarity | - ((hsai->FrameInit.ActiveFrameLength - 1) << 8)); - + hsai->Instance->FRCR &= (~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \ + SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF)); + hsai->Instance->FRCR |= ((hsai->FrameInit.FrameLength - 1U) | + hsai->FrameInit.FSOffset | + hsai->FrameInit.FSDefinition | + hsai->FrameInit.FSPolarity | + ((hsai->FrameInit.ActiveFrameLength - 1U) << 8)); + /* SAI Block_x SLOT Configuration ------------------------------------------*/ /* This register has no meaning in AC 97 and SPDIF audio protocol */ - hsai->Instance->SLOTR&= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ | \ - SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN )); - - hsai->Instance->SLOTR|= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize - | (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1) << 8); - + hsai->Instance->SLOTR &= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ | \ + SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN)); + + hsai->Instance->SLOTR |= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize | \ + (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1U) << 8); + #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* SAI PDM Configuration ---------------------------------------------------*/ - if(hsai->Instance == SAI1_Block_A) + if (hsai->Instance == SAI1_Block_A) { /* Disable PDM interface */ SAI1->PDMCR &= ~(SAI_PDMCR_PDMEN); - if(hsai->Init.PdmInit.Activation == ENABLE) + if (hsai->Init.PdmInit.Activation == ENABLE) { /* Configure and enable PDM interface */ - SAI1->PDMCR = (hsai->Init.PdmInit.ClockEnable | - ((hsai->Init.PdmInit.MicPairsNbr - 1) << SAI_PDMCR_MICNBR_Pos)); + SAI1->PDMCR = (hsai->Init.PdmInit.ClockEnable | + ((hsai->Init.PdmInit.MicPairsNbr - 1U) << SAI_PDMCR_MICNBR_Pos)); SAI1->PDMCR |= SAI_PDMCR_PDMEN; } } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + /* Initialize the error code */ hsai->ErrorCode = HAL_SAI_ERROR_NONE; - + /* Initialize the SAI state */ - hsai->State= HAL_SAI_STATE_READY; - + hsai->State = HAL_SAI_STATE_READY; + /* Release Lock */ __HAL_UNLOCK(hsai); - + return HAL_OK; } /** * @brief DeInitialize the SAI peripheral. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai) { /* Check the SAI handle allocation */ - if(hsai == NULL) + if (hsai == NULL) { return HAL_ERROR; } - + hsai->State = HAL_SAI_STATE_BUSY; - + /* Disabled All interrupt and clear all the flag */ hsai->Instance->IMR = 0; hsai->Instance->CLRFR = 0xFFFFFFFFU; - + /* Disable the SAI */ - SAI_Disable(hsai); - + if (SAI_Disable(hsai) != HAL_OK) + { + /* Reset SAI state to ready */ + hsai->State = HAL_SAI_STATE_READY; + + /* Release Lock */ + __HAL_UNLOCK(hsai); + + return HAL_ERROR; + } + /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); - + #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Disable SAI PDM interface */ - if(hsai->Instance == SAI1_Block_A) + if (hsai->Instance == SAI1_Block_A) { /* Reset PDM delays */ SAI1->PDMDLY = 0U; - + /* Disable PDM interface */ SAI1->PDMCR &= ~(SAI_PDMCR_PDMEN); } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + if (hsai->MspDeInitCallback == NULL) + { + hsai->MspDeInitCallback = HAL_SAI_MspDeInit; + } + hsai->MspDeInitCallback(hsai); +#else HAL_SAI_MspDeInit(hsai); - +#endif + /* Initialize the error code */ hsai->ErrorCode = HAL_SAI_ERROR_NONE; - + /* Initialize the SAI state */ hsai->State = HAL_SAI_STATE_RESET; - + /* Release Lock */ __HAL_UNLOCK(hsai); - + return HAL_OK; } /** * @brief Initialize the SAI MSP. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ __weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsai); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SAI_MspInit could be implemented in the user file */ @@ -693,26 +780,202 @@ __weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai) /** * @brief DeInitialize the SAI MSP. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsai); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SAI_MspDeInit could be implemented in the user file */ } +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) +/** + * @brief Register a user SAI callback + * to be used instead of the weak predefined callback. + * @param hsai SAI handle. + * @param CallbackID ID of the callback to be registered. + * This parameter can be one of the following values: + * @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID. + * @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID. + * @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID. + * @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID. + * @arg @ref HAL_SAI_ERROR_CB_ID error callback ID. + * @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID. + * @param pCallback pointer to the callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai, + HAL_SAI_CallbackIDTypeDef CallbackID, + pSAI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + else + { + if (HAL_SAI_STATE_READY == hsai->State) + { + switch (CallbackID) + { + case HAL_SAI_RX_COMPLETE_CB_ID : + hsai->RxCpltCallback = pCallback; + break; + case HAL_SAI_RX_HALFCOMPLETE_CB_ID : + hsai->RxHalfCpltCallback = pCallback; + break; + case HAL_SAI_TX_COMPLETE_CB_ID : + hsai->TxCpltCallback = pCallback; + break; + case HAL_SAI_TX_HALFCOMPLETE_CB_ID : + hsai->TxHalfCpltCallback = pCallback; + break; + case HAL_SAI_ERROR_CB_ID : + hsai->ErrorCallback = pCallback; + break; + case HAL_SAI_MSPINIT_CB_ID : + hsai->MspInitCallback = pCallback; + break; + case HAL_SAI_MSPDEINIT_CB_ID : + hsai->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SAI_STATE_RESET == hsai->State) + { + switch (CallbackID) + { + case HAL_SAI_MSPINIT_CB_ID : + hsai->MspInitCallback = pCallback; + break; + case HAL_SAI_MSPDEINIT_CB_ID : + hsai->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief Unregister a user SAI callback. + * SAI callback is redirected to the weak predefined callback. + * @param hsai SAI handle. + * @param CallbackID ID of the callback to be unregistered. + * This parameter can be one of the following values: + * @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID. + * @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID. + * @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID. + * @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID. + * @arg @ref HAL_SAI_ERROR_CB_ID error callback ID. + * @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai, + HAL_SAI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_SAI_STATE_READY == hsai->State) + { + switch (CallbackID) + { + case HAL_SAI_RX_COMPLETE_CB_ID : + hsai->RxCpltCallback = HAL_SAI_RxCpltCallback; + break; + case HAL_SAI_RX_HALFCOMPLETE_CB_ID : + hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback; + break; + case HAL_SAI_TX_COMPLETE_CB_ID : + hsai->TxCpltCallback = HAL_SAI_TxCpltCallback; + break; + case HAL_SAI_TX_HALFCOMPLETE_CB_ID : + hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback; + break; + case HAL_SAI_ERROR_CB_ID : + hsai->ErrorCallback = HAL_SAI_ErrorCallback; + break; + case HAL_SAI_MSPINIT_CB_ID : + hsai->MspInitCallback = HAL_SAI_MspInit; + break; + case HAL_SAI_MSPDEINIT_CB_ID : + hsai->MspDeInitCallback = HAL_SAI_MspDeInit; + break; + default : + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SAI_STATE_RESET == hsai->State) + { + switch (CallbackID) + { + case HAL_SAI_MSPINIT_CB_ID : + hsai->MspInitCallback = HAL_SAI_MspInit; + break; + case HAL_SAI_MSPDEINIT_CB_ID : + hsai->MspDeInitCallback = HAL_SAI_MspDeInit; + break; + default : + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + return status; +} +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + /** * @} */ /** @defgroup SAI_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim ============================================================================== ##### IO operation functions ##### @@ -755,95 +1018,110 @@ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai) /** * @brief Transmit an amount of data in blocking mode. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); - - if((pData == NULL ) || (Size == 0)) + uint32_t temp; + + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(hsai->State == HAL_SAI_STATE_READY) + + if (hsai->State == HAL_SAI_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsai); - + hsai->XferSize = Size; hsai->XferCount = Size; hsai->pBuffPtr = pData; hsai->State = HAL_SAI_STATE_BUSY_TX; hsai->ErrorCode = HAL_SAI_ERROR_NONE; - + /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) { /* fill the fifo with data before to enabled the SAI */ SAI_FillFifo(hsai); /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); } - - while(hsai->XferCount > 0) + + while (hsai->XferCount > 0U) { /* Write data if the FIFO is not full */ - if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) + if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) { - if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) { - hsai->Instance->DR = (*hsai->pBuffPtr++); + hsai->Instance->DR = *hsai->pBuffPtr; + hsai->pBuffPtr++; } - else if(hsai->Init.DataSize <= SAI_DATASIZE_16) + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) { - hsai->Instance->DR = *((uint16_t *)hsai->pBuffPtr); - hsai->pBuffPtr+= 2; + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; } else { - hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr); - hsai->pBuffPtr+= 4; + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 16); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 24); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; } hsai->XferCount--; } else { /* Check for the Timeout */ - if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))) + if ((((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) && (Timeout != HAL_MAX_DELAY)) { /* Update error code */ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; - + /* Clear all the flags */ hsai->Instance->CLRFR = 0xFFFFFFFFU; - + /* Disable SAI peripheral */ - SAI_Disable(hsai); - + if (SAI_Disable(hsai) != HAL_OK) + { + /* Nothing to do because state update, unlock and error return will be performed later */ + } + /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); - + /* Change the SAI state */ hsai->State = HAL_SAI_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_ERROR; } } } - + hsai->State = HAL_SAI_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } else @@ -855,7 +1133,7 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint /** * @brief Receive an amount of data in blocking mode. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param pData Pointer to data buffer * @param Size Amount of data to be received * @param Timeout Timeout duration @@ -864,84 +1142,99 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); - - if((pData == NULL ) || (Size == 0)) + uint32_t temp; + + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(hsai->State == HAL_SAI_STATE_READY) + + if (hsai->State == HAL_SAI_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsai); - + hsai->pBuffPtr = pData; hsai->XferSize = Size; hsai->XferCount = Size; hsai->State = HAL_SAI_STATE_BUSY_RX; hsai->ErrorCode = HAL_SAI_ERROR_NONE; - + /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) { /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); } - + /* Receive data */ - while(hsai->XferCount > 0) + while (hsai->XferCount > 0U) { - if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY) + if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY) { - if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) { - (*hsai->pBuffPtr++) = hsai->Instance->DR; + *hsai->pBuffPtr = (uint8_t)hsai->Instance->DR; + hsai->pBuffPtr++; } - else if(hsai->Init.DataSize <= SAI_DATASIZE_16) + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) { - *((uint16_t*)hsai->pBuffPtr) = hsai->Instance->DR; - hsai->pBuffPtr+= 2; + temp = hsai->Instance->DR; + *hsai->pBuffPtr = (uint8_t)temp; + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 8); + hsai->pBuffPtr++; } else { - *((uint32_t*)hsai->pBuffPtr) = hsai->Instance->DR; - hsai->pBuffPtr+= 4; + temp = hsai->Instance->DR; + *hsai->pBuffPtr = (uint8_t)temp; + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 8); + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 16); + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 24); + hsai->pBuffPtr++; } hsai->XferCount--; } else { /* Check for the Timeout */ - if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))) + if ((((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) && (Timeout != HAL_MAX_DELAY)) { /* Update error code */ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; - + /* Clear all the flags */ hsai->Instance->CLRFR = 0xFFFFFFFFU; - + /* Disable SAI peripheral */ - SAI_Disable(hsai); - + if (SAI_Disable(hsai) != HAL_OK) + { + /* Nothing to do because state update, unlock and error return will be performed later */ + } + /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); - + /* Change the SAI state */ hsai->State = HAL_SAI_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_ERROR; } } } - + hsai->State = HAL_SAI_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } else @@ -953,34 +1246,34 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint1 /** * @brief Transmit an amount of data in non-blocking mode with Interrupt. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(hsai->State == HAL_SAI_STATE_READY) + + if (hsai->State == HAL_SAI_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsai); - + hsai->pBuffPtr = pData; hsai->XferSize = Size; hsai->XferCount = Size; hsai->ErrorCode = HAL_SAI_ERROR_NONE; hsai->State = HAL_SAI_STATE_BUSY_TX; - - if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) { hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit; } - else if(hsai->Init.DataSize <= SAI_DATASIZE_16) + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) { hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit; } @@ -988,22 +1281,22 @@ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, u { hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit; } - + /* Fill the fifo before starting the communication */ SAI_FillFifo(hsai); - + /* Enable FRQ and OVRUDR interrupts */ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - + /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) { /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); } /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } else @@ -1015,34 +1308,34 @@ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, u /** * @brief Receive an amount of data in non-blocking mode with Interrupt. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param pData Pointer to data buffer * @param Size Amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(hsai->State == HAL_SAI_STATE_READY) + + if (hsai->State == HAL_SAI_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsai); - + hsai->pBuffPtr = pData; hsai->XferSize = Size; hsai->XferCount = Size; hsai->ErrorCode = HAL_SAI_ERROR_NONE; hsai->State = HAL_SAI_STATE_BUSY_RX; - - if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) { hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit; } - else if(hsai->Init.DataSize <= SAI_DATASIZE_16) + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) { hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit; } @@ -1050,20 +1343,20 @@ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, ui { hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit; } - + /* Enable TXE and OVRUDR interrupts */ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - + /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) { /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); } - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } else @@ -1075,152 +1368,186 @@ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, ui /** * @brief Pause the audio stream playing from the Media. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai) { /* Process Locked */ __HAL_LOCK(hsai); - + /* Pause the audio file playing by disabling the SAI DMA requests */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } /** * @brief Resume the audio stream playing from the Media. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai) { /* Process Locked */ __HAL_LOCK(hsai); - + /* Enable the SAI DMA requests */ hsai->Instance->CR1 |= SAI_xCR1_DMAEN; - + /* If the SAI peripheral is still not enabled, enable it */ - if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) { /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); } - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } /** * @brief Stop the audio stream playing from the Media. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) { + HAL_StatusTypeDef status = HAL_OK; + /* Process Locked */ __HAL_LOCK(hsai); - + /* Disable the SAI DMA request */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; - - /* Abort the SAI DMA Streams */ - if(hsai->hdmatx != NULL) + + /* Abort the SAI Tx DMA Stream */ + if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL)) { - if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) + if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) { - return HAL_ERROR; + /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */ + if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER) + { + status = HAL_ERROR; + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + } } } - - if(hsai->hdmarx != NULL) + + /* Abort the SAI Rx DMA Stream */ + if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL)) { - if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) + if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) { - return HAL_ERROR; + /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */ + if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER) + { + status = HAL_ERROR; + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + } } } - + /* Disable SAI peripheral */ - SAI_Disable(hsai); - + if (SAI_Disable(hsai) != HAL_OK) + { + status = HAL_ERROR; + } + /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); + /* Set hsai state to ready */ hsai->State = HAL_SAI_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - - return HAL_OK; + + return status; } /** * @brief Abort the current transfer and disable the SAI. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) { + HAL_StatusTypeDef status = HAL_OK; + /* Process Locked */ __HAL_LOCK(hsai); - + /* Check SAI DMA is enabled or not */ - if((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) + if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) { /* Disable the SAI DMA request */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; - - /* Abort the SAI DMA Streams */ - if(hsai->hdmatx != NULL) + + /* Abort the SAI Tx DMA Stream */ + if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL)) { - if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) + if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) { - return HAL_ERROR; + /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */ + if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER) + { + status = HAL_ERROR; + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + } } } - - if(hsai->hdmarx != NULL) + + /* Abort the SAI Rx DMA Stream */ + if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL)) { - if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) + if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) { - return HAL_ERROR; + /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */ + if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER) + { + status = HAL_ERROR; + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + } } } } - + /* Disabled All interrupt and clear all the flag */ hsai->Instance->IMR = 0; hsai->Instance->CLRFR = 0xFFFFFFFFU; - + /* Disable SAI peripheral */ - SAI_Disable(hsai); - + if (SAI_Disable(hsai) != HAL_OK) + { + status = HAL_ERROR; + } + /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); - + + /* Set hsai state to ready */ hsai->State = HAL_SAI_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - - return HAL_OK; + + return status; } /** * @brief Transmit an amount of data in non-blocking mode with DMA. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status @@ -1229,73 +1556,73 @@ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, { uint32_t tickstart = HAL_GetTick(); - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(hsai->State == HAL_SAI_STATE_READY) + + if (hsai->State == HAL_SAI_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsai); - + hsai->pBuffPtr = pData; hsai->XferSize = Size; hsai->XferCount = Size; hsai->ErrorCode = HAL_SAI_ERROR_NONE; hsai->State = HAL_SAI_STATE_BUSY_TX; - + /* Set the SAI Tx DMA Half transfer complete callback */ hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt; - + /* Set the SAI TxDMA transfer complete callback */ hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt; - + /* Set the DMA error callback */ hsai->hdmatx->XferErrorCallback = SAI_DMAError; - + /* Set the DMA Tx abort callback */ hsai->hdmatx->XferAbortCallback = NULL; - + /* Enable the Tx DMA Stream */ - if(HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, hsai->XferSize) != HAL_OK) + if (HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, hsai->XferSize) != HAL_OK) { __HAL_UNLOCK(hsai); return HAL_ERROR; } - + /* Enable the interrupts for error handling */ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); - + /* Enable SAI Tx DMA Request */ hsai->Instance->CR1 |= SAI_xCR1_DMAEN; - + /* Wait untill FIFO is not empty */ - while((hsai->Instance->SR & SAI_xSR_FLVL) == SAI_FIFOSTATUS_EMPTY) + while ((hsai->Instance->SR & SAI_xSR_FLVL) == SAI_FIFOSTATUS_EMPTY) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart) > SAI_LONG_TIMEOUT) + if ((HAL_GetTick() - tickstart) > SAI_LONG_TIMEOUT) { /* Update error code */ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; - + /* Process Unlocked */ __HAL_UNLOCK(hsai); return HAL_TIMEOUT; } } - + /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) { /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); } - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } else @@ -1307,7 +1634,7 @@ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, /** * @brief Receive an amount of data in non-blocking mode with DMA. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param pData Pointer to data buffer * @param Size Amount of data to be received * @retval HAL status @@ -1315,57 +1642,57 @@ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(hsai->State == HAL_SAI_STATE_READY) + + if (hsai->State == HAL_SAI_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsai); - + hsai->pBuffPtr = pData; hsai->XferSize = Size; hsai->XferCount = Size; hsai->ErrorCode = HAL_SAI_ERROR_NONE; hsai->State = HAL_SAI_STATE_BUSY_RX; - + /* Set the SAI Rx DMA Half transfer complete callback */ hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt; - + /* Set the SAI Rx DMA transfer complete callback */ hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt; - + /* Set the DMA error callback */ hsai->hdmarx->XferErrorCallback = SAI_DMAError; - + /* Set the DMA Rx abort callback */ hsai->hdmarx->XferAbortCallback = NULL; - + /* Enable the Rx DMA Stream */ - if(HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, hsai->XferSize) != HAL_OK) + if (HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, hsai->XferSize) != HAL_OK) { __HAL_UNLOCK(hsai); return HAL_ERROR; } - + /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) { /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); } - + /* Enable the interrupts for error handling */ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); - + /* Enable SAI Rx DMA Request */ hsai->Instance->CR1 |= SAI_xCR1_DMAEN; - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } else @@ -1377,18 +1704,18 @@ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, u /** * @brief Enable the Tx mute mode. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param val value sent during the mute @ref SAI_Block_Mute_Value * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val) { assert_param(IS_SAI_BLOCK_MUTE_VALUE(val)); - - if(hsai->State != HAL_SAI_STATE_RESET) + + if (hsai->State != HAL_SAI_STATE_RESET) { CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE); - SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | val); + SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | (uint32_t)val); return HAL_OK; } return HAL_ERROR; @@ -1397,12 +1724,12 @@ HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val /** * @brief Disable the Tx mute mode. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai) { - if(hsai->State != HAL_SAI_STATE_RESET) + if (hsai->State != HAL_SAI_STATE_RESET) { CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE); return HAL_OK; @@ -1413,7 +1740,7 @@ HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai) /** * @brief Enable the Rx mute detection. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param callback function called when the mute is detected. * @param counter number a data before mute detection max 63. * @retval HAL status @@ -1421,8 +1748,8 @@ HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai) HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter) { assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter)); - - if(hsai->State != HAL_SAI_STATE_RESET) + + if (hsai->State != HAL_SAI_STATE_RESET) { /* set the mute counter */ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT); @@ -1438,15 +1765,15 @@ HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback /** * @brief Disable the Rx mute detection. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai) { - if(hsai->State != HAL_SAI_STATE_RESET) + if (hsai->State != HAL_SAI_STATE_RESET) { /* set the mutecallback to NULL */ - hsai->mutecallback = (SAIcallback)NULL; + hsai->mutecallback = NULL; /* enable the IT interrupt */ __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET); return HAL_OK; @@ -1457,25 +1784,25 @@ HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai) /** * @brief Handle SAI interrupt request. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) { - if(hsai->State != HAL_SAI_STATE_RESET) + if (hsai->State != HAL_SAI_STATE_RESET) { uint32_t itflags = hsai->Instance->SR; uint32_t itsources = hsai->Instance->IMR; uint32_t cr1config = hsai->Instance->CR1; uint32_t tmperror; - - /* SAI Fifo request interrupt occured ------------------------------------*/ - if(((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ)) + + /* SAI Fifo request interrupt occurred -----------------------------------*/ + if (((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ)) { hsai->InterruptServiceRoutine(hsai); } /* SAI Overrun error interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR)) + else if (((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR)) { /* Clear the SAI Overrun flag */ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); @@ -1484,117 +1811,177 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) /* Change the SAI error code */ hsai->ErrorCode |= tmperror; /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else HAL_SAI_ErrorCallback(hsai); +#endif } /* SAI mutedet interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET)) + else if (((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET)) { /* Clear the SAI mutedet flag */ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET); /* call the call back function */ - if(hsai->mutecallback != (SAIcallback)NULL) + if (hsai->mutecallback != NULL) { /* inform the user that an RX mute event has been detected */ hsai->mutecallback(); } } /* SAI AFSDET interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET)) + else if (((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET)) { /* Change the SAI error code */ hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET; - + /* Check SAI DMA is enabled or not */ - if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) + if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) { /* Abort the SAI DMA Streams */ - if(hsai->hdmatx != NULL) + if (hsai->hdmatx != NULL) { /* Set the DMA Tx abort callback */ hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmatx); + if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ + HAL_SAI_ErrorCallback(hsai); + } } - else if(hsai->hdmarx != NULL) + if (hsai->hdmarx != NULL) { /* Set the DMA Rx abort callback */ hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmarx); + if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ + HAL_SAI_ErrorCallback(hsai); + } } } else { - /* Abort SAI */ - HAL_SAI_Abort(hsai); - + /* Abort SAI */ + if (HAL_SAI_Abort(hsai) != HAL_OK) + { + /* Nothing to do because HAL_SAI_ErrorCallback will be called later */ + } + /* Set error callback */ - HAL_SAI_ErrorCallback(hsai); +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif } } /* SAI LFSDET interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET)) + else if (((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET)) { /* Change the SAI error code */ hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET; - + /* Check SAI DMA is enabled or not */ - if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) + if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) { /* Abort the SAI DMA Streams */ - if(hsai->hdmatx != NULL) + if (hsai->hdmatx != NULL) { /* Set the DMA Tx abort callback */ hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; - + /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmatx); + if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ + HAL_SAI_ErrorCallback(hsai); + } } - else if(hsai->hdmarx != NULL) + if (hsai->hdmarx != NULL) { /* Set the DMA Rx abort callback */ hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; - + /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmarx); + if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ + HAL_SAI_ErrorCallback(hsai); + } } } else { - /* Abort SAI */ - HAL_SAI_Abort(hsai); - + /* Abort SAI */ + if (HAL_SAI_Abort(hsai) != HAL_OK) + { + /* Nothing to do because HAL_SAI_ErrorCallback will be called later */ + } + /* Set error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else HAL_SAI_ErrorCallback(hsai); +#endif } } /* SAI WCKCFG interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG)) + else if (((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG)) { /* Change the SAI error code */ hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG; - + /* Check SAI DMA is enabled or not */ - if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) + if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) { /* Abort the SAI DMA Streams */ - if(hsai->hdmatx != NULL) + if (hsai->hdmatx != NULL) { /* Set the DMA Tx abort callback */ hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; - + /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmatx); + if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ + HAL_SAI_ErrorCallback(hsai); + } } - else if(hsai->hdmarx != NULL) + if (hsai->hdmarx != NULL) { /* Set the DMA Rx abort callback */ hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; - + /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmarx); + if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ + HAL_SAI_ErrorCallback(hsai); + } } } else @@ -1605,23 +1992,31 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) hsai->Instance->CLRFR = 0xFFFFFFFFU; /* Set the SAI state to ready to be able to start again the process */ hsai->State = HAL_SAI_STATE_READY; - + /* Initialize XferCount */ hsai->XferCount = 0U; - + /* SAI error Callback */ - HAL_SAI_ErrorCallback(hsai); +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif } } /* SAI CNRDY interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY)) + else if (((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY)) { /* Clear the SAI CNRDY flag */ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY); /* Change the SAI error code */ hsai->ErrorCode |= HAL_SAI_ERROR_CNREADY; /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else HAL_SAI_ErrorCallback(hsai); +#endif } else { @@ -1633,14 +2028,14 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) /** * @brief Tx Transfer completed callback. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsai); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SAI_TxCpltCallback could be implemented in the user file */ @@ -1649,14 +2044,14 @@ __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief Tx Transfer Half completed callback. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsai); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SAI_TxHalfCpltCallback could be implemented in the user file */ @@ -1665,14 +2060,14 @@ __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief Rx Transfer completed callback. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ __weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsai); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SAI_RxCpltCallback could be implemented in the user file */ @@ -1681,14 +2076,14 @@ __weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief Rx Transfer half completed callback. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ __weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsai); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SAI_RxHalfCpltCallback could be implemented in the user file */ @@ -1697,14 +2092,14 @@ __weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief SAI error callback. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsai); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SAI_ErrorCallback could be implemented in the user file */ @@ -1714,10 +2109,9 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) * @} */ - /** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim =============================================================================== ##### Peripheral State and Errors functions ##### @@ -1733,7 +2127,7 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) /** * @brief Return the SAI handle state. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval HAL state */ HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) @@ -1742,15 +2136,16 @@ HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) } /** -* @brief Return the SAI error code. -* @param hsai pointer to a SAI_HandleTypeDef structure that contains + * @brief Return the SAI error code. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for the specified SAI Block. -* @retval SAI Error Code -*/ + * @retval SAI Error Code + */ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai) { return hsai->ErrorCode; } + /** * @} */ @@ -1760,7 +2155,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai) */ /** @addtogroup SAI_Private_Functions - * @brief Private functions + * @brief Private functions * @{ */ @@ -1768,84 +2163,89 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai) * @brief Initialize the SAI I2S protocol according to the specified parameters * in the SAI_InitTypeDef and create the associated handle. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param protocol one of the supported protocol. - * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize - * the configuration information for SAI module. + * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize. * @param nbslot number of slot minimum value is 2 and max is 16. - * the value must be a multiple of 2. + * the value must be a multiple of 2. * @retval HAL status */ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) { + HAL_StatusTypeDef status = HAL_OK; + hsai->Init.Protocol = SAI_FREE_PROTOCOL; hsai->Init.FirstBit = SAI_FIRSTBIT_MSB; /* Compute ClockStrobing according AudioMode */ - if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) - { /* Transmit */ + if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) + { + /* Transmit */ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; } else - { /* Receive */ + { + /* Receive */ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; } hsai->FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION; hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL; hsai->SlotInit.FirstBitOffset = 0; hsai->SlotInit.SlotNumber = nbslot; - + /* in IS2 the number of slot must be even */ - if((nbslot & 0x1) != 0 ) + if ((nbslot & 0x1U) != 0U) { return HAL_ERROR; } - - switch(protocol) - { - case SAI_I2S_STANDARD : - hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; - hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; - break; - case SAI_I2S_MSBJUSTIFIED : - case SAI_I2S_LSBJUSTIFIED : - hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH; - hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT; - break; - default : - return HAL_ERROR; + + switch (protocol) + { + case SAI_I2S_STANDARD : + hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; + hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; + break; + case SAI_I2S_MSBJUSTIFIED : + case SAI_I2S_LSBJUSTIFIED : + hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH; + hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT; + break; + default : + status = HAL_ERROR; + break; } - + /* Frame definition */ - switch(datasize) - { - case SAI_PROTOCOL_DATASIZE_16BIT: - hsai->Init.DataSize = SAI_DATASIZE_16; - hsai->FrameInit.FrameLength = 32*(nbslot/2); - hsai->FrameInit.ActiveFrameLength = 16*(nbslot/2); - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B; - break; - case SAI_PROTOCOL_DATASIZE_16BITEXTENDED : - hsai->Init.DataSize = SAI_DATASIZE_16; - hsai->FrameInit.FrameLength = 64*(nbslot/2); - hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2); - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - case SAI_PROTOCOL_DATASIZE_24BIT: - hsai->Init.DataSize = SAI_DATASIZE_24; - hsai->FrameInit.FrameLength = 64*(nbslot/2); - hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2); - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - case SAI_PROTOCOL_DATASIZE_32BIT: - hsai->Init.DataSize = SAI_DATASIZE_32; - hsai->FrameInit.FrameLength = 64*(nbslot/2); - hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2); - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - default : - return HAL_ERROR; + switch (datasize) + { + case SAI_PROTOCOL_DATASIZE_16BIT: + hsai->Init.DataSize = SAI_DATASIZE_16; + hsai->FrameInit.FrameLength = 32U * (nbslot / 2U); + hsai->FrameInit.ActiveFrameLength = 16U * (nbslot / 2U); + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B; + break; + case SAI_PROTOCOL_DATASIZE_16BITEXTENDED : + hsai->Init.DataSize = SAI_DATASIZE_16; + hsai->FrameInit.FrameLength = 64U * (nbslot / 2U); + hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U); + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + case SAI_PROTOCOL_DATASIZE_24BIT: + hsai->Init.DataSize = SAI_DATASIZE_24; + hsai->FrameInit.FrameLength = 64U * (nbslot / 2U); + hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U); + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + case SAI_PROTOCOL_DATASIZE_32BIT: + hsai->Init.DataSize = SAI_DATASIZE_32; + hsai->FrameInit.FrameLength = 64U * (nbslot / 2U); + hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U); + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + default : + status = HAL_ERROR; + break; } - if(protocol == SAI_I2S_LSBJUSTIFIED) + if (protocol == SAI_I2S_LSBJUSTIFIED) { if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) { @@ -1856,14 +2256,14 @@ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, hsai->SlotInit.FirstBitOffset = 8; } } - return HAL_OK; + return status; } /** * @brief Initialize the SAI PCM protocol according to the specified parameters * in the SAI_InitTypeDef and create the associated handle. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param protocol one of the supported protocol * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize * @param nbslot number of slot minimum value is 1 and the max is 16. @@ -1871,15 +2271,19 @@ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, */ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) { + HAL_StatusTypeDef status = HAL_OK; + hsai->Init.Protocol = SAI_FREE_PROTOCOL; hsai->Init.FirstBit = SAI_FIRSTBIT_MSB; /* Compute ClockStrobing according AudioMode */ - if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) - { /* Transmit */ + if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) + { + /* Transmit */ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; } else - { /* Receive */ + { + /* Receive */ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; } hsai->FrameInit.FSDefinition = SAI_FS_STARTFRAME; @@ -1888,72 +2292,87 @@ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, hsai->SlotInit.FirstBitOffset = 0; hsai->SlotInit.SlotNumber = nbslot; hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL; - - switch(protocol) - { - case SAI_PCM_SHORT : - hsai->FrameInit.ActiveFrameLength = 1; - break; - case SAI_PCM_LONG : - hsai->FrameInit.ActiveFrameLength = 13; - break; - default : - return HAL_ERROR; + + switch (protocol) + { + case SAI_PCM_SHORT : + hsai->FrameInit.ActiveFrameLength = 1; + break; + case SAI_PCM_LONG : + hsai->FrameInit.ActiveFrameLength = 13; + break; + default : + status = HAL_ERROR; + break; } - - switch(datasize) - { - case SAI_PROTOCOL_DATASIZE_16BIT: - hsai->Init.DataSize = SAI_DATASIZE_16; - hsai->FrameInit.FrameLength = 16 * nbslot; - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B; - break; - case SAI_PROTOCOL_DATASIZE_16BITEXTENDED : - hsai->Init.DataSize = SAI_DATASIZE_16; - hsai->FrameInit.FrameLength = 32 * nbslot; - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - case SAI_PROTOCOL_DATASIZE_24BIT : - hsai->Init.DataSize = SAI_DATASIZE_24; - hsai->FrameInit.FrameLength = 32 * nbslot; - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - case SAI_PROTOCOL_DATASIZE_32BIT: - hsai->Init.DataSize = SAI_DATASIZE_32; - hsai->FrameInit.FrameLength = 32 * nbslot; - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - default : - return HAL_ERROR; + + switch (datasize) + { + case SAI_PROTOCOL_DATASIZE_16BIT: + hsai->Init.DataSize = SAI_DATASIZE_16; + hsai->FrameInit.FrameLength = 16U * nbslot; + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B; + break; + case SAI_PROTOCOL_DATASIZE_16BITEXTENDED : + hsai->Init.DataSize = SAI_DATASIZE_16; + hsai->FrameInit.FrameLength = 32U * nbslot; + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + case SAI_PROTOCOL_DATASIZE_24BIT : + hsai->Init.DataSize = SAI_DATASIZE_24; + hsai->FrameInit.FrameLength = 32U * nbslot; + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + case SAI_PROTOCOL_DATASIZE_32BIT: + hsai->Init.DataSize = SAI_DATASIZE_32; + hsai->FrameInit.FrameLength = 32U * nbslot; + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + default : + status = HAL_ERROR; + break; } - - return HAL_OK; + + return status; } /** * @brief Fill the fifo. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ static void SAI_FillFifo(SAI_HandleTypeDef *hsai) { + uint32_t temp; + /* fill the fifo with data before to enabled the SAI */ - while(((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0)) + while (((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0U)) { - if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) { - hsai->Instance->DR = (*hsai->pBuffPtr++); + hsai->Instance->DR = *hsai->pBuffPtr; + hsai->pBuffPtr++; } - else if(hsai->Init.DataSize <= SAI_DATASIZE_16) + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) { - hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr); - hsai->pBuffPtr+= 2; + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; } else { - hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr); - hsai->pBuffPtr+= 4; + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 16); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 24); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; } hsai->XferCount--; } @@ -1962,33 +2381,33 @@ static void SAI_FillFifo(SAI_HandleTypeDef *hsai) /** * @brief Return the interrupt flag to set according the SAI setup. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param mode SAI_MODE_DMA or SAI_MODE_IT * @retval the list of the IT flag to enable - */ -static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode) + */ +static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode) { uint32_t tmpIT = SAI_IT_OVRUDR; - - if(mode == SAI_MODE_IT) + + if (mode == SAI_MODE_IT) { - tmpIT|= SAI_IT_FREQ; + tmpIT |= SAI_IT_FREQ; } - - if((hsai->Init.Protocol == SAI_AC97_PROTOCOL) && - ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX))) + + if ((hsai->Init.Protocol == SAI_AC97_PROTOCOL) && + ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX))) { - tmpIT|= SAI_IT_CNRDY; + tmpIT |= SAI_IT_CNRDY; } - - if((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) + + if ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) { - tmpIT|= SAI_IT_AFSDET | SAI_IT_LFSDET; + tmpIT |= SAI_IT_AFSDET | SAI_IT_LFSDET; } else { /* hsai has been configured in master mode */ - tmpIT|= SAI_IT_WCKCFG; + tmpIT |= SAI_IT_WCKCFG; } return tmpIT; } @@ -1996,49 +2415,59 @@ static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode) /** * @brief Disable the SAI and wait for the disabling. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai) { - uint32_t tickstart = HAL_GetTick(); + register uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock / 7U / 1000U); HAL_StatusTypeDef status = HAL_OK; - + + /* Disable the SAI instance */ __HAL_SAI_DISABLE(hsai); - while((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET) + + do { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart) > SAI_DEFAULT_TIMEOUT) + if (count == 0U) { /* Update error code */ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; - - return HAL_TIMEOUT; + status = HAL_TIMEOUT; + break; } + count--; } + while ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != 0U); + return status; } /** * @brief Tx Handler for Transmit in Interrupt mode 8-Bit transfer. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai) { - if(hsai->XferCount == 0) + if (hsai->XferCount == 0U) { /* Handle the end of the transmission */ /* Disable FREQ and OVRUDR interrupts */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->TxCpltCallback(hsai); +#else HAL_SAI_TxCpltCallback(hsai); +#endif } else { /* Write data on DR register */ - hsai->Instance->DR = (*hsai->pBuffPtr++); + hsai->Instance->DR = *hsai->pBuffPtr; + hsai->pBuffPtr++; hsai->XferCount--; } } @@ -2046,24 +2475,32 @@ static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai) /** * @brief Tx Handler for Transmit in Interrupt mode for 16-Bit transfer. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai) { - if(hsai->XferCount == 0) + if (hsai->XferCount == 0U) { /* Handle the end of the transmission */ /* Disable FREQ and OVRUDR interrupts */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->TxCpltCallback(hsai); +#else HAL_SAI_TxCpltCallback(hsai); +#endif } else { /* Write data on DR register */ - hsai->Instance->DR = *(uint16_t *)hsai->pBuffPtr; - hsai->pBuffPtr+=2; + uint32_t temp; + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; hsai->XferCount--; } } @@ -2071,24 +2508,36 @@ static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai) /** * @brief Tx Handler for Transmit in Interrupt mode for 32-Bit transfer. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai) { - if(hsai->XferCount == 0) + if (hsai->XferCount == 0U) { /* Handle the end of the transmission */ /* Disable FREQ and OVRUDR interrupts */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->TxCpltCallback(hsai); +#else HAL_SAI_TxCpltCallback(hsai); +#endif } else { /* Write data on DR register */ - hsai->Instance->DR = *(uint32_t *)hsai->pBuffPtr; - hsai->pBuffPtr+=4; + uint32_t temp; + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 16); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 24); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; hsai->XferCount--; } } @@ -2096,217 +2545,277 @@ static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai) /** * @brief Rx Handler for Receive in Interrupt mode 8-Bit transfer. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai) { /* Receive data */ - (*hsai->pBuffPtr++) = hsai->Instance->DR; + *hsai->pBuffPtr = (uint8_t)hsai->Instance->DR; + hsai->pBuffPtr++; hsai->XferCount--; - + /* Check end of the transfer */ - if(hsai->XferCount == 0) + if (hsai->XferCount == 0U) { /* Disable TXE and OVRUDR interrupts */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - + /* Clear the SAI Overrun flag */ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); - + hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->RxCpltCallback(hsai); +#else HAL_SAI_RxCpltCallback(hsai); +#endif } } /** * @brief Rx Handler for Receive in Interrupt mode for 16-Bit transfer. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai) { + uint32_t temp; + /* Receive data */ - *(uint16_t*)hsai->pBuffPtr = hsai->Instance->DR; - hsai->pBuffPtr+=2; + temp = hsai->Instance->DR; + *hsai->pBuffPtr = (uint8_t)temp; + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 8); + hsai->pBuffPtr++; hsai->XferCount--; - + /* Check end of the transfer */ - if(hsai->XferCount == 0) + if (hsai->XferCount == 0U) { /* Disable TXE and OVRUDR interrupts */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - + /* Clear the SAI Overrun flag */ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); - + hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->RxCpltCallback(hsai); +#else HAL_SAI_RxCpltCallback(hsai); +#endif } } + /** * @brief Rx Handler for Receive in Interrupt mode for 32-Bit transfer. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai) { + uint32_t temp; + /* Receive data */ - *(uint32_t*)hsai->pBuffPtr = hsai->Instance->DR; - hsai->pBuffPtr+=4; + temp = hsai->Instance->DR; + *hsai->pBuffPtr = (uint8_t)temp; + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 8); + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 16); + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 24); + hsai->pBuffPtr++; hsai->XferCount--; - + /* Check end of the transfer */ - if(hsai->XferCount == 0) + if (hsai->XferCount == 0U) { /* Disable TXE and OVRUDR interrupts */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - + /* Clear the SAI Overrun flag */ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); - + hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->RxCpltCallback(hsai); +#else HAL_SAI_RxCpltCallback(hsai); +#endif } } /** * @brief DMA SAI transmit process complete callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * the configuration information for the specified DMA module. * @retval None */ static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma) { - SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent; - - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma->Init.Mode != DMA_CIRCULAR) { hsai->XferCount = 0; - + /* Disable SAI Tx DMA Request */ hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN); - + /* Stop the interrupts error handling */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); - - hsai->State= HAL_SAI_STATE_READY; + + hsai->State = HAL_SAI_STATE_READY; } +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->TxCpltCallback(hsai); +#else HAL_SAI_TxCpltCallback(hsai); +#endif } /** * @brief DMA SAI transmit process half complete callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * the configuration information for the specified DMA module. * @retval None */ static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { - SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->TxHalfCpltCallback(hsai); +#else HAL_SAI_TxHalfCpltCallback(hsai); +#endif } /** * @brief DMA SAI receive process complete callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * the configuration information for the specified DMA module. * @retval None */ static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma) { - SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma->Init.Mode != DMA_CIRCULAR) { /* Disable Rx DMA Request */ hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN); hsai->XferCount = 0; - + /* Stop the interrupts error handling */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); - + hsai->State = HAL_SAI_STATE_READY; } +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->RxCpltCallback(hsai); +#else HAL_SAI_RxCpltCallback(hsai); +#endif } /** * @brief DMA SAI receive process half complete callback * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * the configuration information for the specified DMA module. * @retval None */ static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { - SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->RxHalfCpltCallback(hsai); +#else HAL_SAI_RxHalfCpltCallback(hsai); +#endif } + /** * @brief DMA SAI communication error callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * the configuration information for the specified DMA module. * @retval None */ static void SAI_DMAError(DMA_HandleTypeDef *hdma) { - SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Set SAI error code */ hsai->ErrorCode |= HAL_SAI_ERROR_DMA; - + /* Disable the SAI DMA request */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; /* Disable SAI peripheral */ - SAI_Disable(hsai); - + if (SAI_Disable(hsai) != HAL_OK) + { + /* Nothing to do because state will be updated and HAL_SAI_ErrorCallback will be called later */ + } + /* Set the SAI state ready to be able to start again the process */ hsai->State = HAL_SAI_STATE_READY; /* Initialize XferCount */ hsai->XferCount = 0U; - /* SAI error Callback */ + /* SAI error Callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else HAL_SAI_ErrorCallback(hsai); +#endif } /** * @brief DMA SAI Abort callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * the configuration information for the specified DMA module. * @retval None */ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma) { - SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Disable DMA request */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; /* Disable all interrupts and clear all flags */ hsai->Instance->IMR = 0U; hsai->Instance->CLRFR = 0xFFFFFFFFU; - - if(hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG) + + if (hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG) { /* Disable SAI peripheral */ - SAI_Disable(hsai); + if (SAI_Disable(hsai) != HAL_OK) + { + /* Nothing to do because state will be updated and HAL_SAI_ErrorCallback will be called later */ + } /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); } /* Set the SAI state to ready to be able to start again the process */ hsai->State = HAL_SAI_STATE_READY; - + /* Initialize XferCount */ hsai->XferCount = 0U; /* SAI error Callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else HAL_SAI_ErrorCallback(hsai); +#endif } /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c index 3ef20a7feb..882323e6eb 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32l4xx_hal_sai_ex.c * @author MCD Application Team - * @brief SAI Extended HAL module driver. + * @brief SAI Extended HAL module driver. * This file provides firmware functions to manage the following * functionality of the SAI Peripheral Controller: * + Modify PDM microphone delays. @@ -35,7 +35,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -54,22 +54,20 @@ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ - -#define SAI_PDM_DELAY_MASK 0x77U -#define SAI_PDM_DELAY_OFFSET 8U -#define SAI_PDM_RIGHT_DELAY_OFFSET 4U +#define SAI_PDM_DELAY_MASK 0x77U +#define SAI_PDM_DELAY_OFFSET 8U +#define SAI_PDM_RIGHT_DELAY_OFFSET 4U /* Private macros ------------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ - /** @defgroup SAIEx_Exported_Functions SAIEx Extended Exported Functions * @{ */ /** @defgroup SAIEx_Exported_Functions_Group1 Peripheral Control functions * @brief SAIEx control functions - * + * @verbatim =============================================================================== ##### Extended features functions ##### @@ -90,9 +88,10 @@ HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay) { HAL_StatusTypeDef status = HAL_OK; - + uint32_t offset; + /* Check that SAI sub-block is SAI1 sub-block A */ - if(hsai->Instance != SAI1_Block_A) + if (hsai->Instance != SAI1_Block_A) { status = HAL_ERROR; } @@ -102,16 +101,18 @@ HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_Pdm assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(pdmMicDelay->MicPair)); assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->LeftDelay)); assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->RightDelay)); - - /* Check SAI state */ - if(hsai->State != HAL_SAI_STATE_RESET) + + /* Compute offset on PDMDLY register according mic pair number */ + offset = SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1U); + + /* Check SAI state and offset */ + if ((hsai->State != HAL_SAI_STATE_RESET) && (offset <= 24U)) { /* Reset current delays for specified microphone */ - SAI1->PDMDLY &= ~(SAI_PDM_DELAY_MASK << (SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1))); - + SAI1->PDMDLY &= ~(SAI_PDM_DELAY_MASK << offset); + /* Apply new microphone delays */ - SAI1->PDMDLY |= (((pdmMicDelay->RightDelay << SAI_PDM_RIGHT_DELAY_OFFSET) | pdmMicDelay->LeftDelay) << \ - (SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1))); + SAI1->PDMDLY |= (((pdmMicDelay->RightDelay << SAI_PDM_RIGHT_DELAY_OFFSET) | pdmMicDelay->LeftDelay) << offset); } else { diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c index 30c007e268..d0e0777ee4 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c @@ -192,6 +192,65 @@ (@) You can refer to the SD HAL driver header file for more useful macros + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions @ref HAL_SD_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed. + (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed. + (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed. + (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed. + (+) MspInitCallback : SD MspInit. + (+) MspDeInitCallback : SD MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + For specific callbacks TransceiverCallback use dedicated register callbacks: + respectively @ref HAL_SD_RegisterTransceiverCallback(). + + Use function @ref HAL_SD_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed. + (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed. + (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed. + (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed. + (+) MspInitCallback : SD MspInit. + (+) MspDeInitCallback : SD MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + For specific callbacks TransceiverCallback use dedicated unregister callbacks: + respectively @ref HAL_SD_UnRegisterTransceiverCallback(). + + By default, after the @ref HAL_SD_Init and if the state is HAL_SD_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_SD_Init + and @ref HAL_SD_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_SD_Init and @ref HAL_SD_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_SD_RegisterCallback before calling @ref HAL_SD_DeInit + or @ref HAL_SD_Init function. + + When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + @endverbatim ****************************************************************************** * @attention @@ -263,9 +322,9 @@ static uint32_t SD_SendStatus (SD_HandleTypeDef *hsd, uint32_t *pCa static uint32_t SD_WideBus_Enable (SD_HandleTypeDef *hsd); static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd); static uint32_t SD_FindSCR (SD_HandleTypeDef *hsd, uint32_t *pSCR); -static HAL_StatusTypeDef SD_PowerOFF (SD_HandleTypeDef *hsd); -static HAL_StatusTypeDef SD_Write_IT (SD_HandleTypeDef *hsd); -static HAL_StatusTypeDef SD_Read_IT (SD_HandleTypeDef *hsd); +static void SD_PowerOFF (SD_HandleTypeDef *hsd); +static void SD_Write_IT (SD_HandleTypeDef *hsd); +static void SD_Read_IT (SD_HandleTypeDef *hsd); #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void SD_DMAReceiveCplt (DMA_HandleTypeDef *hdma); @@ -326,8 +385,31 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) { /* Allocate lock resource and initialize it */ hsd->Lock = HAL_UNLOCKED; +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + /* Reset Callback pointers in HAL_SD_STATE_RESET only */ + hsd->TxCpltCallback = HAL_SD_TxCpltCallback; + hsd->RxCpltCallback = HAL_SD_RxCpltCallback; + hsd->ErrorCallback = HAL_SD_ErrorCallback; + hsd->AbortCpltCallback = HAL_SD_AbortCallback; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + hsd->Read_DMADblBuf0CpltCallback = HAL_SDEx_Read_DMADoubleBuffer0CpltCallback; + hsd->Read_DMADblBuf1CpltCallback = HAL_SDEx_Read_DMADoubleBuffer1CpltCallback; + hsd->Write_DMADblBuf0CpltCallback = HAL_SDEx_Write_DMADoubleBuffer0CpltCallback; + hsd->Write_DMADblBuf1CpltCallback = HAL_SDEx_Write_DMADoubleBuffer1CpltCallback; + hsd->DriveTransceiver_1_8V_Callback = HAL_SDEx_DriveTransceiver_1_8V_Callback; +#endif + + if(hsd->MspInitCallback == NULL) + { + hsd->MspInitCallback = HAL_SD_MspInit; + } + + /* Init the low level hardware */ + hsd->MspInitCallback(hsd); +#else /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_SD_MspInit(hsd); +#endif } hsd->State = HAL_SD_STATE_BUSY; @@ -350,9 +432,9 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) if((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { - hsd->Instance->CLKCR |= 0x00100000; + hsd->Instance->CLKCR |= 0x00100000U; /* Enable High Speed */ - if(HAL_SDEx_HighSpeed(hsd) != HAL_OK) + if(HAL_SDEx_HighSpeed(hsd) != HAL_SD_ERROR_NONE) { return HAL_ERROR; } @@ -381,8 +463,8 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) */ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) { - uint32_t errorstate = HAL_SD_ERROR_NONE; - HAL_StatusTypeDef status = HAL_OK; + uint32_t errorstate; + HAL_StatusTypeDef status; SD_InitTypeDef Init; /* Default SDMMC peripheral configuration for SD card initialization */ @@ -472,8 +554,18 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) /* Set SD power state to off */ SD_PowerOFF(hsd); +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + if(hsd->MspDeInitCallback == NULL) + { + hsd->MspDeInitCallback = HAL_SD_MspDeInit; + } + + /* DeInit the low level hardware */ + hsd->MspDeInitCallback(hsd); +#else /* De-Initialize the MSP layer */ HAL_SD_MspDeInit(hsd); +#endif hsd->ErrorCode = HAL_SD_ERROR_NONE; hsd->State = HAL_SD_STATE_RESET; @@ -546,9 +638,11 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t count = 0, *tempbuff = (uint32_t *)pData; + uint32_t count, data; + uint32_t add = BlockAdd; + uint8_t *tempbuff = pData; if(NULL == pData) { @@ -560,7 +654,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 { hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -569,11 +663,11 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 hsd->State = HAL_SD_STATE_BUSY; /* Initialize data control register */ - hsd->Instance->DCTRL = 0; + hsd->Instance->DCTRL = 0U; if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { - BlockAdd *= 512; + add *= 512U; } /* Set Block Size for Card */ @@ -598,25 +692,25 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 #else config.DPSM = SDMMC_DPSM_ENABLE; #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - SDMMC_ConfigData(hsd->Instance, &config); + (void)SDMMC_ConfigData(hsd->Instance, &config); #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) __SDMMC_CMDTRANS_ENABLE( hsd->Instance); #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* Read block(s) in polling mode */ - if(NumberOfBlocks > 1) + if(NumberOfBlocks > 1U) { hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK; /* Read Multi Block command */ - errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); } else { hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK; /* Read Single Block command */ - errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); } if(errorstate != HAL_SD_ERROR_NONE) { @@ -624,6 +718,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } @@ -635,17 +730,25 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 /* Read data from SDMMC Rx FIFO */ for(count = 0U; count < 8U; count++) { - *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance); + data = SDMMC_ReadFIFO(hsd->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; } - tempbuff += 8U; } - if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; hsd->State= HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_TIMEOUT; } } @@ -666,6 +769,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } } @@ -678,6 +782,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) @@ -686,6 +791,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) @@ -694,22 +800,35 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } + else + { + /* Nothing to do */ + } #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Empty FIFO if there is still any data */ while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))) { - *tempbuff = SDMMC_ReadFIFO(hsd->Instance); + data = SDMMC_ReadFIFO(hsd->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); tempbuff++; - if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; hsd->State= HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } } @@ -744,10 +863,11 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t count = 0; - uint32_t *tempbuff = (uint32_t *)pData; + uint32_t count, data; + uint32_t add = BlockAdd; + uint8_t *tempbuff = pData; if(NULL == pData) { @@ -759,7 +879,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint { hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -768,11 +888,11 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint hsd->State = HAL_SD_STATE_BUSY; /* Initialize data control register */ - hsd->Instance->DCTRL = 0; + hsd->Instance->DCTRL = 0U; if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { - BlockAdd *= 512; + add *= 512U; } /* Set Block Size for Card */ @@ -797,7 +917,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint #else config.DPSM = SDMMC_DPSM_ENABLE; #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - SDMMC_ConfigData(hsd->Instance, &config); + (void)SDMMC_ConfigData(hsd->Instance, &config); #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) __SDMMC_CMDTRANS_ENABLE( hsd->Instance); #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ @@ -808,14 +928,14 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK; /* Write Multi Block command */ - errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); } else { hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK; /* Write Single Block command */ - errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); } if(errorstate != HAL_SD_ERROR_NONE) { @@ -823,6 +943,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } @@ -834,17 +955,25 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint /* Write data to SDMMC Tx FIFO */ for(count = 0U; count < 8U; count++) { - SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count)); + data = (uint32_t)(*tempbuff); + tempbuff++; + data |= ((uint32_t)(*tempbuff) << 8U); + tempbuff++; + data |= ((uint32_t)(*tempbuff) << 16U); + tempbuff++; + data |= ((uint32_t)(*tempbuff) << 24U); + tempbuff++; + (void)SDMMC_WriteFIFO(hsd->Instance, &data); } - tempbuff += 8U; } - if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_TIMEOUT; } } @@ -865,6 +994,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } } @@ -877,6 +1007,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) @@ -885,6 +1016,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR)) @@ -893,8 +1025,13 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } + else + { + /* Nothing to do */ + } /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); @@ -926,7 +1063,8 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; + uint32_t add = BlockAdd; if(NULL == pData) { @@ -938,7 +1076,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui { hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -949,14 +1087,14 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui /* Initialize data control register */ hsd->Instance->DCTRL = 0U; - hsd->pRxBuffPtr = (uint32_t *)pData; + hsd->pRxBuffPtr = pData; hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF)); if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { - BlockAdd *= 512U; + add *= 512U; } /* Set Block Size for Card */ @@ -981,7 +1119,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui #else config.DPSM = SDMMC_DPSM_ENABLE; #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - SDMMC_ConfigData(hsd->Instance, &config); + (void)SDMMC_ConfigData(hsd->Instance, &config); #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) __SDMMC_CMDTRANS_ENABLE( hsd->Instance); #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ @@ -992,14 +1130,14 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT); /* Read Multi Block command */ - errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); } else { hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT); /* Read Single Block command */ - errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); } if(errorstate != HAL_SD_ERROR_NONE) { @@ -1007,6 +1145,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } @@ -1034,7 +1173,8 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; + uint32_t add = BlockAdd; if(NULL == pData) { @@ -1046,7 +1186,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u { hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -1057,7 +1197,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u /* Initialize data control register */ hsd->Instance->DCTRL = 0U; - hsd->pTxBuffPtr = (uint32_t *)pData; + hsd->pTxBuffPtr = pData; hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks; /* Enable transfer interrupts */ @@ -1065,7 +1205,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { - BlockAdd *= 512U; + add *= 512U; } /* Set Block Size for Card */ @@ -1087,7 +1227,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_DISABLE; - SDMMC_ConfigData(hsd->Instance, &config); + (void)SDMMC_ConfigData(hsd->Instance, &config); __SDMMC_CMDTRANS_ENABLE( hsd->Instance); #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ @@ -1098,14 +1238,14 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT); /* Write Multi Block command */ - errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); } else { hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT); /* Write Single Block command */ - errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); } if(errorstate != HAL_SD_ERROR_NONE) { @@ -1113,6 +1253,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } @@ -1124,7 +1265,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &config); + (void)SDMMC_ConfigData(hsd->Instance, &config); #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ return HAL_OK; @@ -1151,7 +1292,8 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; + uint32_t add = BlockAdd; if(NULL == pData) { @@ -1163,7 +1305,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u { hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -1187,81 +1329,93 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u hsd->hdmarx->XferAbortCallback = NULL; /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4); - - /* Enable SD DMA transfer */ - __HAL_SD_DMA_ENABLE(hsd); -#else - hsd->pRxBuffPtr = (uint32_t*)pData; - hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; -#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ - - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + if(HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK) { - BlockAdd *= 512U; - } - - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; + __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DMA; hsd->State = HAL_SD_STATE_READY; return HAL_ERROR; } - - /* Configure the SD DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = BLOCKSIZE * NumberOfBlocks; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + else + { + /* Enable SD DMA transfer */ + __HAL_SD_DMA_ENABLE(hsd); +#else + hsd->pRxBuffPtr = pData; + hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + add *= 512U; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - config.DPSM = SDMMC_DPSM_DISABLE; + config.DPSM = SDMMC_DPSM_DISABLE; #else - config.DPSM = SDMMC_DPSM_ENABLE; + config.DPSM = SDMMC_DPSM_ENABLE; #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - SDMMC_ConfigData(hsd->Instance, &config); - + (void)SDMMC_ConfigData(hsd->Instance, &config); + #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /* Enable transfer interrupts */ - __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); - - __SDMMC_CMDTRANS_ENABLE( hsd->Instance); - hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; - hsd->Instance->IDMABASE0 = (uint32_t) pData ; -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - - /* Read Blocks in DMA mode */ - if(NumberOfBlocks > 1U) - { - hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA); + /* Enable transfer interrupts */ + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); - /* Read Multi Block command */ - errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd); - } - else - { - hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA); + __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; + hsd->Instance->IDMABASE0 = (uint32_t) pData ; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - /* Read Single Block command */ - errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd); - } - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + /* Read Blocks in DMA mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); + } + else + { + hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + + return HAL_OK; +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) } - - return HAL_OK; +#endif } else { @@ -1285,7 +1439,8 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; + uint32_t add = BlockAdd; if(NULL == pData) { @@ -1297,7 +1452,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, { hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -1309,7 +1464,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, hsd->Instance->DCTRL = 0U; #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - hsd->pTxBuffPtr = (uint32_t*)pData; + hsd->pTxBuffPtr = pData; hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks; #else /* Enable SD Error interrupts */ @@ -1327,7 +1482,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { - BlockAdd *= 512U; + add *= 512U; } /* Set Block Size for Card */ @@ -1348,7 +1503,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_DISABLE; - SDMMC_ConfigData(hsd->Instance, &config); + (void)SDMMC_ConfigData(hsd->Instance, &config); /* Enable transfer interrupts */ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); @@ -1365,14 +1520,14 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA); /* Write Multi Block command */ - errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); } else { hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA); /* Write Single Block command */ - errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); } if(errorstate != HAL_SD_ERROR_NONE) { @@ -1383,6 +1538,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } @@ -1391,19 +1547,31 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, __HAL_SD_DMA_ENABLE(hsd); /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4); - - /* Configure the SD DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = BLOCKSIZE * NumberOfBlocks; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &config); + if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK) + { + __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DMA; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + else + { + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ - return HAL_OK; + return HAL_OK; +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + } +#endif } else { @@ -1422,19 +1590,21 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, */ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd) { - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; + uint32_t start_add = BlockStartAdd; + uint32_t end_add = BlockEndAdd; if(hsd->State == HAL_SD_STATE_READY) { hsd->ErrorCode = HAL_SD_ERROR_NONE; - if(BlockEndAdd < BlockStartAdd) + if(end_add < start_add) { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; return HAL_ERROR; } - if(BlockEndAdd > (hsd->SdCard.LogBlockNbr)) + if(end_add > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -1464,15 +1634,15 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui /* Get start and end block for high capacity cards */ if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { - BlockStartAdd *= 512U; - BlockEndAdd *= 512U; + start_add *= 512U; + end_add *= 512U; } /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ if(hsd->SdCard.CardType != CARD_SECURED) { /* Send CMD32 SD_ERASE_GRP_START with argument as addr */ - errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, BlockStartAdd); + errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add); if(errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ @@ -1483,7 +1653,7 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui } /* Send CMD33 SD_ERASE_GRP_END with argument as addr */ - errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, BlockEndAdd); + errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add); if(errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ @@ -1522,7 +1692,8 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui */ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) { - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; + uint32_t context = hsd->Context; /* Check for SDMMC interrupt flags */ if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DATAEND) != RESET) @@ -1536,17 +1707,24 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC); __SDMMC_CMDTRANS_DISABLE( hsd->Instance); +#else + hsd->Instance->DCTRL &= ~(SDMMC_DCTRL_DTEN); + #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - if((hsd->Context & SD_CONTEXT_IT) != RESET) + if((context & SD_CONTEXT_IT) != 0U) { - if(((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)) + if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { errorstate = SDMMC_CmdStopTransfer(hsd->Instance); if(errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= errorstate; +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->ErrorCallback(hsd); +#else HAL_SD_ErrorCallback(hsd); +#endif } } @@ -1554,53 +1732,79 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); hsd->State = HAL_SD_STATE_READY; - if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET)) + hsd->Context = SD_CONTEXT_NONE; + if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->RxCpltCallback(hsd); +#else HAL_SD_RxCpltCallback(hsd); +#endif } else { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->TxCpltCallback(hsd); +#else HAL_SD_TxCpltCallback(hsd); +#endif } } - else if((hsd->Context & SD_CONTEXT_DMA) != RESET) + else if((context & SD_CONTEXT_DMA) != 0U) { #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) hsd->Instance->DLEN = 0; hsd->Instance->DCTRL = 0; hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; - /* Stop Transfer for Write Single/Multi blocks or Read Multi blocks */ - if((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) == RESET) + /* Stop Transfer for Write Multi blocks or Read Multi blocks */ + if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { errorstate = SDMMC_CmdStopTransfer(hsd->Instance); if(errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= errorstate; +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->ErrorCallback(hsd); +#else HAL_SD_ErrorCallback(hsd); +#endif } } hsd->State = HAL_SD_STATE_READY; - if(((hsd->Context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)) + hsd->Context = SD_CONTEXT_NONE; + if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->TxCpltCallback(hsd); +#else HAL_SD_TxCpltCallback(hsd); +#endif } - if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET)) + if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->RxCpltCallback(hsd); +#else HAL_SD_RxCpltCallback(hsd); +#endif } #else - if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET) + if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) { errorstate = SDMMC_CmdStopTransfer(hsd->Instance); if(errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= errorstate; +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->ErrorCallback(hsd); +#else HAL_SD_ErrorCallback(hsd); +#endif } } - if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == RESET)) + if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == 0U)) { /* Disable the DMA transfer for transmit request by setting the DMAEN bit in the SD DCTRL register */ @@ -1608,10 +1812,18 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) hsd->State = HAL_SD_STATE_READY; +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->TxCpltCallback(hsd); +#else HAL_SD_TxCpltCallback(hsd); +#endif } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ } + else + { + /* Nothing to do */ + } } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXFIFOHE) != RESET) @@ -1651,13 +1863,29 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); - if((hsd->Context & SD_CONTEXT_IT) != RESET) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __SDMMC_CMDTRANS_DISABLE( hsd->Instance); + hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; + hsd->Instance->CMD |= SDMMC_CMD_CMDSTOP; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + hsd->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DABORT); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + + if((context & SD_CONTEXT_IT) != 0U) { /* Set the SD state to ready to be able to start again the process */ hsd->State = HAL_SD_STATE_READY; - HAL_SD_ErrorCallback(hsd); + hsd->Context = SD_CONTEXT_NONE; +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif } - else if((hsd->Context & SD_CONTEXT_DMA) != RESET) + else if((context & SD_CONTEXT_DMA) != 0U) { #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) if(hsd->ErrorCode != HAL_SD_ERROR_NONE) @@ -1668,11 +1896,15 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) /* Set the SD state to ready to be able to start again the process */ hsd->State = HAL_SD_STATE_READY; +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->ErrorCallback(hsd); +#else HAL_SD_ErrorCallback(hsd); +#endif } #else /* Abort the SD DMA channel */ - if(hsd->hdmatx != NULL) + if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { /* Set the DMA Tx abort callback */ hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; @@ -1682,7 +1914,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) SD_DMATxAbort(hsd->hdmatx); } } - else if(hsd->hdmarx != NULL) + else if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) { /* Set the DMA Rx abort callback */ hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; @@ -1696,42 +1928,71 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) { hsd->ErrorCode = HAL_SD_ERROR_NONE; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->AbortCpltCallback(hsd); +#else HAL_SD_AbortCallback(hsd); +#endif } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ } + else + { + /* Nothing to do */ + } } #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_IDMABTC) != RESET) { - if(READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == SD_DMA_BUFFER0) + if(READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U) { /* Current buffer is buffer0, Transfer complete for buffer1 */ - if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET) + if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->Write_DMADblBuf1CpltCallback(hsd); +#else HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(hsd); +#endif } else /* SD_CONTEXT_READ_MULTIPLE_BLOCK */ { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->Read_DMADblBuf1CpltCallback(hsd); +#else HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(hsd); +#endif } } else /* SD_DMA_BUFFER1 */ { /* Current buffer is buffer1, Transfer complete for buffer0 */ - if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET) + if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->Write_DMADblBuf0CpltCallback(hsd); +#else HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(hsd); +#endif } else /* SD_CONTEXT_READ_MULTIPLE_BLOCK */ { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->Read_DMADblBuf0CpltCallback(hsd); +#else HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(hsd); +#endif } } __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMABTC); } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + else + { + /* Nothing to do */ + } } /** @@ -1760,7 +2021,7 @@ uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd) * @param hsd: Pointer to SD handle * @retval None */ - __weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd) +__weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsd); @@ -1811,10 +2072,281 @@ __weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd) UNUSED(hsd); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SD_ErrorCallback can be implemented in the user file + the HAL_SD_AbortCallback can be implemented in the user file */ } +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User SD Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hsd : SD handle + * @param CallbackID : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID + * @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID + * @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID + * @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID + * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID + * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hsd); + + if(hsd->State == HAL_SD_STATE_READY) + { + switch (CallbackID) + { + case HAL_SD_TX_CPLT_CB_ID : + hsd->TxCpltCallback = pCallback; + break; + case HAL_SD_RX_CPLT_CB_ID : + hsd->RxCpltCallback = pCallback; + break; + case HAL_SD_ERROR_CB_ID : + hsd->ErrorCallback = pCallback; + break; + case HAL_SD_ABORT_CB_ID : + hsd->AbortCpltCallback = pCallback; + break; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID : + hsd->Read_DMADblBuf0CpltCallback = pCallback; + break; + case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID : + hsd->Read_DMADblBuf1CpltCallback = pCallback; + break; + case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : + hsd->Write_DMADblBuf0CpltCallback = pCallback; + break; + case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : + hsd->Write_DMADblBuf1CpltCallback = pCallback; + break; +#endif + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = pCallback; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hsd->State == HAL_SD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = pCallback; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsd); + return status; +} + +/** + * @brief Unregister a User SD Callback + * SD Callback is redirected to the weak (surcharged) predefined callback + * @param hsd : SD handle + * @param CallbackID : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID + * @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID + * @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID + * @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID + * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID + * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hsd); + + if(hsd->State == HAL_SD_STATE_READY) + { + switch (CallbackID) + { + case HAL_SD_TX_CPLT_CB_ID : + hsd->TxCpltCallback = HAL_SD_TxCpltCallback; + break; + case HAL_SD_RX_CPLT_CB_ID : + hsd->RxCpltCallback = HAL_SD_RxCpltCallback; + break; + case HAL_SD_ERROR_CB_ID : + hsd->ErrorCallback = HAL_SD_ErrorCallback; + break; + case HAL_SD_ABORT_CB_ID : + hsd->AbortCpltCallback = HAL_SD_AbortCallback; + break; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID : + hsd->Read_DMADblBuf0CpltCallback = HAL_SDEx_Read_DMADoubleBuffer0CpltCallback; + break; + case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID : + hsd->Read_DMADblBuf1CpltCallback = HAL_SDEx_Read_DMADoubleBuffer1CpltCallback; + break; + case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : + hsd->Write_DMADblBuf0CpltCallback = HAL_SDEx_Write_DMADoubleBuffer0CpltCallback; + break; + case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : + hsd->Write_DMADblBuf1CpltCallback = HAL_SDEx_Write_DMADoubleBuffer1CpltCallback; + break; +#endif + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = HAL_SD_MspInit; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = HAL_SD_MspDeInit; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hsd->State == HAL_SD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = HAL_SD_MspInit; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = HAL_SD_MspDeInit; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsd); + return status; +} + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** + * @brief Register a User SD Transceiver Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hsd : SD handle + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hsd); + + if(hsd->State == HAL_SD_STATE_READY) + { + hsd->DriveTransceiver_1_8V_Callback = pCallback; + } + else + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsd); + return status; +} + +/** + * @brief Unregister a User SD Transceiver Callback + * SD Callback is redirected to the weak (surcharged) predefined callback + * @param hsd : SD handle + * @retval status + */ +HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hsd); + + if(hsd->State == HAL_SD_STATE_READY) + { + hsd->DriveTransceiver_1_8V_Callback = HAL_SDEx_DriveTransceiver_1_8V_Callback; + } + else + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsd); + return status; +} +#endif +#endif /** * @} @@ -1845,73 +2377,25 @@ __weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd) */ HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef *pCID) { - uint32_t tmp = 0; - - /* Byte 0 */ - tmp = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24); - pCID->ManufacturerID = tmp; + pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U); - /* Byte 1 */ - tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16); - pCID->OEM_AppliID = tmp << 8; + pCID->OEM_AppliID = (uint16_t)((hsd->CID[0] & 0x00FFFF00U) >> 8U); - /* Byte 2 */ - tmp = (uint8_t)((hsd->CID[0] & 0x0000FF00) >> 8); - pCID->OEM_AppliID |= tmp; + pCID->ProdName1 = (((hsd->CID[0] & 0x000000FFU) << 24U) | ((hsd->CID[1] & 0xFFFFFF00U) >> 8U)); - /* Byte 3 */ - tmp = (uint8_t)(hsd->CID[0] & 0x000000FF); - pCID->ProdName1 = tmp << 24; + pCID->ProdName2 = (uint8_t)(hsd->CID[1] & 0x000000FFU); - /* Byte 4 */ - tmp = (uint8_t)((hsd->CID[1] & 0xFF000000U) >> 24); - pCID->ProdName1 |= tmp << 16; + pCID->ProdRev = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24U); - /* Byte 5 */ - tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16); - pCID->ProdName1 |= tmp << 8; + pCID->ProdSN = (((hsd->CID[2] & 0x00FFFFFFU) << 8U) | ((hsd->CID[3] & 0xFF000000U) >> 24U)); - /* Byte 6 */ - tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8); - pCID->ProdName1 |= tmp; - - /* Byte 7 */ - tmp = (uint8_t)(hsd->CID[1] & 0x000000FF); - pCID->ProdName2 = tmp; - - /* Byte 8 */ - tmp = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24); - pCID->ProdRev = tmp; - - /* Byte 9 */ - tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16); - pCID->ProdSN = tmp << 24; - - /* Byte 10 */ - tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8); - pCID->ProdSN |= tmp << 16; - - /* Byte 11 */ - tmp = (uint8_t)(hsd->CID[2] & 0x000000FF); - pCID->ProdSN |= tmp << 8; - - /* Byte 12 */ - tmp = (uint8_t)((hsd->CID[3] & 0xFF000000U) >> 24); - pCID->ProdSN |= tmp; - - /* Byte 13 */ - tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16); - pCID->Reserved1 |= (tmp & 0xF0) >> 4; - pCID->ManufactDate = (tmp & 0x0F) << 8; - - /* Byte 14 */ - tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8); - pCID->ManufactDate |= tmp; + pCID->Reserved1 = (uint8_t)((hsd->CID[3] & 0x00F00000U) >> 20U); + + pCID->ManufactDate = (uint16_t)((hsd->CID[3] & 0x000FFF00U) >> 8U); - /* Byte 15 */ - tmp = (uint8_t)(hsd->CID[3] & 0x000000FF); - pCID->CID_CRC = (tmp & 0xFE) >> 1; - pCID->Reserved2 = 1; + pCID->CID_CRC = (uint8_t)((hsd->CID[3] & 0x000000FEU) >> 1U); + + pCID->Reserved2 = 1U; return HAL_OK; } @@ -1926,95 +2410,62 @@ HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef */ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef *pCSD) { - uint32_t tmp = 0; - - /* Byte 0 */ - tmp = (hsd->CSD[0] & 0xFF000000U) >> 24; - pCSD->CSDStruct = (uint8_t)((tmp & 0xC0) >> 6); - pCSD->SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2); - pCSD->Reserved1 = tmp & 0x03; - - /* Byte 1 */ - tmp = (hsd->CSD[0] & 0x00FF0000) >> 16; - pCSD->TAAC = (uint8_t)tmp; - - /* Byte 2 */ - tmp = (hsd->CSD[0] & 0x0000FF00) >> 8; - pCSD->NSAC = (uint8_t)tmp; - - /* Byte 3 */ - tmp = hsd->CSD[0] & 0x000000FF; - pCSD->MaxBusClkFrec = (uint8_t)tmp; - - /* Byte 4 */ - tmp = (hsd->CSD[1] & 0xFF000000U) >> 24; - pCSD->CardComdClasses = (uint16_t)(tmp << 4); - - /* Byte 5 */ - tmp = (hsd->CSD[1] & 0x00FF0000U) >> 16; - pCSD->CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4); - pCSD->RdBlockLen = (uint8_t)(tmp & 0x0F); - - /* Byte 6 */ - tmp = (hsd->CSD[1] & 0x0000FF00U) >> 8; - pCSD->PartBlockRead = (uint8_t)((tmp & 0x80) >> 7); - pCSD->WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6); - pCSD->RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5); - pCSD->DSRImpl = (uint8_t)((tmp & 0x10) >> 4); - pCSD->Reserved2 = 0; /*!< Reserved */ + pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U); + + pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U); + + pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U); + + pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U); + + pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U); + + pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU); + + pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U); + + pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U); + + pCSD->PartBlockRead = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U); + + pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U); + + pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U); + + pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U); + + pCSD->Reserved2 = 0U; /*!< Reserved */ if(hsd->SdCard.CardType == CARD_SDSC) { - pCSD->DeviceSize = (tmp & 0x03) << 10; + pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U)); - /* Byte 7 */ - tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU); - pCSD->DeviceSize |= (tmp) << 2; - - /* Byte 8 */ - tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24); - pCSD->DeviceSize |= (tmp & 0xC0) >> 6; - - pCSD->MaxRdCurrentVDDMin = (tmp & 0x38) >> 3; - pCSD->MaxRdCurrentVDDMax = (tmp & 0x07); + pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U); + + pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U); - /* Byte 9 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16); - pCSD->MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5; - pCSD->MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2; - pCSD->DeviceSizeMul = (tmp & 0x03) << 1; - /* Byte 10 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8); - pCSD->DeviceSizeMul |= (tmp & 0x80) >> 7; + pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U); + + pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U); + + pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U); - hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1) ; - hsd->SdCard.BlockNbr *= (1 << (pCSD->DeviceSizeMul + 2)); - hsd->SdCard.BlockSize = 1 << (pCSD->RdBlockLen); + hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ; + hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); + hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); - hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512); - hsd->SdCard.LogBlockSize = 512; + hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U); + hsd->SdCard.LogBlockSize = 512U; } else if(hsd->SdCard.CardType == CARD_SDHC_SDXC) { /* Byte 7 */ - tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU); - pCSD->DeviceSize = (tmp & 0x3F) << 16; - - /* Byte 8 */ - tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24); - - pCSD->DeviceSize |= (tmp << 8); - - /* Byte 9 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16); - - pCSD->DeviceSize |= (tmp); - - /* Byte 10 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8); - - hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr = (((uint64_t)pCSD->DeviceSize + 1) * 1024); - hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize = 512; + pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U)); + + hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U); + hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr; + hsd->SdCard.BlockSize = 512U; + hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize; } else { @@ -2025,40 +2476,40 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef return HAL_ERROR; } - pCSD->EraseGrSize = (tmp & 0x40) >> 6; - pCSD->EraseGrMul = (tmp & 0x3F) << 1; - - /* Byte 11 */ - tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF); - pCSD->EraseGrMul |= (tmp & 0x80) >> 7; - pCSD->WrProtectGrSize = (tmp & 0x7F); - - /* Byte 12 */ - tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000U) >> 24); - pCSD->WrProtectGrEnable = (tmp & 0x80) >> 7; - pCSD->ManDeflECC = (tmp & 0x60) >> 5; - pCSD->WrSpeedFact = (tmp & 0x1C) >> 2; - pCSD->MaxWrBlockLen = (tmp & 0x03) << 2; - - /* Byte 13 */ - tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16); - pCSD->MaxWrBlockLen |= (tmp & 0xC0) >> 6; - pCSD->WriteBlockPaPartial = (tmp & 0x20) >> 5; - pCSD->Reserved3 = 0; - pCSD->ContentProtectAppli = (tmp & 0x01); - - /* Byte 14 */ - tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8); - pCSD->FileFormatGrouop = (tmp & 0x80) >> 7; - pCSD->CopyFlag = (tmp & 0x40) >> 6; - pCSD->PermWrProtect = (tmp & 0x20) >> 5; - pCSD->TempWrProtect = (tmp & 0x10) >> 4; - pCSD->FileFormat = (tmp & 0x0C) >> 2; - pCSD->ECC = (tmp & 0x03); - - /* Byte 15 */ - tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF); - pCSD->CSD_CRC = (tmp & 0xFE) >> 1; + pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U); + + pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U); + + pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU); + + pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U); + + pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U); + + pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U); + + pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U); + + pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U); + + pCSD->Reserved3 = 0; + + pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U); + + pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U); + + pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U); + + pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U); + + pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U); + + pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U); + + pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U); + + pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U); + pCSD->Reserved4 = 1; return HAL_OK; @@ -2073,12 +2524,11 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef */ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pStatus) { - uint32_t tmp = 0; uint32_t sd_status[16]; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; errorstate = SD_SendSDStatus(hsd, sd_status); - if(errorstate != HAL_OK) + if(errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -2088,65 +2538,26 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT } else { - /* Byte 0 */ - tmp = (sd_status[0] & 0xC0) >> 6; - pStatus->DataBusWidth = (uint8_t)tmp; - - /* Byte 0 */ - tmp = (sd_status[0] & 0x20) >> 5; - pStatus->SecuredMode = (uint8_t)tmp; - - /* Byte 2 */ - tmp = (sd_status[0] & 0x00FF0000U) >> 16; - pStatus->CardType = (uint16_t)(tmp << 8); - - /* Byte 3 */ - tmp = (sd_status[0] & 0xFF000000U) >> 24; - pStatus->CardType |= (uint16_t)tmp; - - /* Byte 4 */ - tmp = (sd_status[1] & 0xFF); - pStatus->ProtectedAreaSize = (uint32_t)(tmp << 24); - - /* Byte 5 */ - tmp = (sd_status[1] & 0xFF00) >> 8; - pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 16); + pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U); - /* Byte 6 */ - tmp = (sd_status[1] & 0xFF0000) >> 16; - pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 8); + pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U); - /* Byte 7 */ - tmp = (sd_status[1] & 0xFF000000U) >> 24; - pStatus->ProtectedAreaSize |= (uint32_t)tmp; - - /* Byte 8 */ - tmp = (sd_status[2] & 0xFF); - pStatus->SpeedClass = (uint8_t)tmp; + pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U)); - /* Byte 9 */ - tmp = (sd_status[2] & 0xFF00) >> 8; - pStatus->PerformanceMove = (uint8_t)tmp; + pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U) | ((sd_status[1] & 0xFF00U) << 8U) | + ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U)); + + pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU); - /* Byte 10 */ - tmp = (sd_status[2] & 0xF00000) >> 20; - pStatus->AllocationUnitSize = (uint8_t)tmp; + pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U); - /* Byte 11 */ - tmp = (sd_status[2] & 0xFF000000U) >> 24; - pStatus->EraseSize = (uint16_t)(tmp << 8); + pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U); - /* Byte 12 */ - tmp = (sd_status[3] & 0xFF); - pStatus->EraseSize |= (uint16_t)tmp; + pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU)); - /* Byte 13 */ - tmp = (sd_status[3] & 0xFC00) >> 10; - pStatus->EraseTimeout = (uint8_t)tmp; + pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U); - /* Byte 13 */ - tmp = (sd_status[3] & 0x0300) >> 8; - pStatus->EraseOffset = (uint8_t)tmp; + pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U); } return HAL_OK; @@ -2187,7 +2598,7 @@ HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeD HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode) { SDMMC_InitTypeDef Init; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; /* Check the parameters */ assert_param(IS_SDMMC_BUS_WIDE(WideMode)); @@ -2270,7 +2681,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t Init.ClockDiv = hsd->Init.ClockDiv; #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - SDMMC_Init(hsd->Instance, Init); + (void)SDMMC_Init(hsd->Instance, Init); } /* Change State */ @@ -2286,8 +2697,8 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t */ HAL_SD_CardStateTypedef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) { - HAL_SD_CardStateTypedef cardstate = HAL_SD_CARD_TRANSFER; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t cardstate; + uint32_t errorstate; uint32_t resp1 = 0; errorstate = SD_SendStatus(hsd, &resp1); @@ -2296,9 +2707,9 @@ HAL_SD_CardStateTypedef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) hsd->ErrorCode |= errorstate; } - cardstate = (HAL_SD_CardStateTypedef)((resp1 >> 9) & 0x0F); + cardstate = ((resp1 >> 9U) & 0x0FU); - return cardstate; + return (HAL_SD_CardStateTypedef)cardstate; } /** @@ -2310,7 +2721,10 @@ HAL_SD_CardStateTypedef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) { HAL_SD_CardStateTypedef CardState; - +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + uint32_t context = hsd->Context; +#endif + /* DIsable All interrupts */ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); @@ -2322,29 +2736,42 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) /* If IDMA Context, disable Internal DMA */ hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; #else - if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL)) + CLEAR_BIT(hsd->Instance->DCTRL, SDMMC_DCTRL_DTEN); + + if ((context & SD_CONTEXT_DMA) != 0) { /* Disable the SD DMA request */ hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); /* Abort the SD DMA Tx channel */ - if(hsd->hdmatx != NULL) + if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0)) { - HAL_DMA_Abort(hsd->hdmatx); + if(HAL_DMA_Abort(hsd->hdmatx) != HAL_OK) + { + hsd->ErrorCode |= HAL_SD_ERROR_DMA; + } } /* Abort the SD DMA Rx channel */ - if(hsd->hdmarx != NULL) + else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0)) + { + if(HAL_DMA_Abort(hsd->hdmarx) != HAL_OK) + { + hsd->ErrorCode |= HAL_SD_ERROR_DMA; + } + } + else { - HAL_DMA_Abort(hsd->hdmarx); + /* Nothing to do */ } } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; CardState = HAL_SD_GetCardState(hsd); if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { - hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); } if(hsd->ErrorCode != HAL_SD_ERROR_NONE) { @@ -2362,6 +2789,9 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) { HAL_SD_CardStateTypedef CardState; +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + uint32_t context = hsd->Context; +#endif /* Disable All interrupts */ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ @@ -2388,42 +2818,52 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) } else { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->AbortCpltCallback(hsd); +#else HAL_SD_AbortCallback(hsd); +#endif } #else - if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL)) + CLEAR_BIT(hsd->Instance->DCTRL, SDMMC_DCTRL_DTEN); + + if ((context & SD_CONTEXT_DMA) != 0) { /* Disable the SD DMA request */ hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); /* Abort the SD DMA Tx channel */ - if(hsd->hdmatx != NULL) + if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0)) { - hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; + hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK) { hsd->hdmatx = NULL; } } /* Abort the SD DMA Rx channel */ - if(hsd->hdmarx != NULL) + else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0)) { - hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; + hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK) { hsd->hdmarx = NULL; } } + else + { + /* Nothing to do */ + } } - /* No transfer ongoing on both DMA channels*/ - if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL)) + else { /* Clear All flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); CardState = HAL_SD_GetCardState(hsd); hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); @@ -2434,7 +2874,11 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) } else { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->AbortCpltCallback(hsd); +#else HAL_SD_AbortCallback(hsd); +#endif } } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ @@ -2477,7 +2921,7 @@ static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma) static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; /* Send stop command in multiblock write */ if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA)) @@ -2486,7 +2930,11 @@ static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) if(errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= errorstate; +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->ErrorCallback(hsd); +#else HAL_SD_ErrorCallback(hsd); +#endif } } @@ -2498,8 +2946,13 @@ static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->RxCpltCallback(hsd); +#else HAL_SD_RxCpltCallback(hsd); +#endif } /** @@ -2511,8 +2964,11 @@ static void SD_DMAError(DMA_HandleTypeDef *hdma) { SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); HAL_SD_CardStateTypedef CardState; + uint32_t RxErrorCode, TxErrorCode; - if((hsd->hdmarx->ErrorCode == HAL_DMA_ERROR_TE) || (hsd->hdmatx->ErrorCode == HAL_DMA_ERROR_TE)) + RxErrorCode = hsd->hdmarx->ErrorCode; + TxErrorCode = hsd->hdmatx->ErrorCode; + if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE)) { /* Clear All flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -2529,9 +2985,14 @@ static void SD_DMAError(DMA_HandleTypeDef *hdma) } hsd->State= HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; } +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->ErrorCallback(hsd); +#else HAL_SD_ErrorCallback(hsd); +#endif } /** @@ -2544,32 +3005,32 @@ static void SD_DMATxAbort(DMA_HandleTypeDef *hdma) SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); HAL_SD_CardStateTypedef CardState; - if(hsd->hdmatx != NULL) + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + CardState = HAL_SD_GetCardState(hsd); + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { - hsd->hdmatx = NULL; + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); } - - /* All DMA channels are aborted */ - if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL)) + + if(hsd->ErrorCode == HAL_SD_ERROR_NONE) { - /* Clear All flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - - CardState = HAL_SD_GetCardState(hsd); - hsd->State = HAL_SD_STATE_READY; - if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) - { - hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); - - if(hsd->ErrorCode == HAL_SD_ERROR_NONE) - { - HAL_SD_AbortCallback(hsd); - } - else - { - HAL_SD_ErrorCallback(hsd); - } - } +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->AbortCpltCallback(hsd); +#else + HAL_SD_AbortCallback(hsd); +#endif + } + else + { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif } } @@ -2583,32 +3044,32 @@ static void SD_DMARxAbort(DMA_HandleTypeDef *hdma) SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); HAL_SD_CardStateTypedef CardState; - if(hsd->hdmarx != NULL) + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + CardState = HAL_SD_GetCardState(hsd); + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { - hsd->hdmarx = NULL; + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); } - - /* All DMA channels are aborted */ - if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL)) + + if(hsd->ErrorCode == HAL_SD_ERROR_NONE) { - /* Clear All flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - - CardState = HAL_SD_GetCardState(hsd); - hsd->State = HAL_SD_STATE_READY; - if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) - { - hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); - - if(hsd->ErrorCode == HAL_SD_ERROR_NONE) - { - HAL_SD_AbortCallback(hsd); - } - else - { - HAL_SD_ErrorCallback(hsd); - } - } +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->AbortCpltCallback(hsd); +#else + HAL_SD_AbortCallback(hsd); +#endif + } + else + { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif } } #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ @@ -2621,11 +3082,11 @@ static void SD_DMARxAbort(DMA_HandleTypeDef *hdma) static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) { HAL_SD_CardCSDTypedef CSD; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; uint16_t sd_rca = 1; /* Check the power State */ - if(SDMMC_GetPowerState(hsd->Instance) == 0) + if(SDMMC_GetPowerState(hsd->Instance) == 0U) { /* Power off */ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; @@ -2673,10 +3134,10 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) else { /* Get Card Specific Data */ - hsd->CSD[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); - hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); - hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); + hsd->CSD[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); + hsd->CSD[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); + hsd->CSD[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); + hsd->CSD[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); } } @@ -2684,7 +3145,10 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20); /* Get CSD parameters */ - HAL_SD_GetCardCSD(hsd, &CSD); + if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK) + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } /* Select the Card */ errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16)); @@ -2695,7 +3159,7 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Configure SDMMC peripheral interface */ - SDMMC_Init(hsd->Instance, hsd->Init); + (void)SDMMC_Init(hsd->Instance, hsd->Init); #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ /* All cards are initialized */ @@ -2713,7 +3177,10 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) { __IO uint32_t count = 0; uint32_t response = 0, validvoltage = 0; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t tickstart = HAL_GetTick(); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* CMD0: GO_IDLE_STATE */ errorstate = SDMMC_CmdGoIdleState(hsd->Instance); @@ -2730,7 +3197,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ - while(validvoltage == 0) + while(validvoltage == 0U) { if(count++ == SDMMC_MAX_VOLT_TRIAL) { @@ -2755,7 +3222,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); /* Get operating voltage*/ - validvoltage = (((response >> 31) == 1) ? 1 : 0); + validvoltage = (((response >> 31U) == 1U) ? 1U : 0U); } /* Card type is SDSC */ hsd->SdCard.CardType = CARD_SDSC; @@ -2767,7 +3234,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ - while(validvoltage == 0) + while(validvoltage == 0U) { if(count++ == SDMMC_MAX_VOLT_TRIAL) { @@ -2792,7 +3259,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); /* Get operating voltage*/ - validvoltage = (((response >> 31) == 1) ? 1 : 0); + validvoltage = (((response >> 31U) == 1U) ? 1U : 0U); } if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ @@ -2817,7 +3284,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) { /* SD CARD */ /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ - while((!validvoltage) && (count < SDMMC_MAX_VOLT_TRIAL)) + while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U)) { /* SEND CMD55 APP_CMD with RCA as 0 */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); @@ -2837,7 +3304,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); /* Get operating voltage*/ - validvoltage = (((response >> 31) == 1) ? 1 : 0); + validvoltage = (((response >> 31U) == 1U) ? 1U : 0U); count++; } @@ -2868,7 +3335,13 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) } /* Check to CKSTOP */ - while(( hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP); + while(( hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP) + { + if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } + } /* Clear CKSTOP Flag */ hsd->Instance->ICR = SDMMC_FLAG_CKSTOP; @@ -2882,13 +3355,23 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) else { /* Enable Transceiver Switch PIN */ +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->DriveTransceiver_1_8V_Callback(SET); +#else HAL_SDEx_DriveTransceiver_1_8V_Callback(SET); +#endif /* Switch ready */ hsd->Instance->POWER |= SDMMC_POWER_VSWITCH; /* Check VSWEND Flag */ - while(( hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND); + while(( hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND) + { + if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } + } /* Clear VSWEND Flag */ hsd->Instance->ICR = SDMMC_FLAG_VSWEND; @@ -2902,9 +3385,10 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /* Switch to 1.8V OK */ /* Disable VSWITCH FLAG from SDMMC IP */ - hsd->Instance->POWER = 0x13; + hsd->Instance->POWER = 0x13U; + /* Clean Status flags */ - hsd->Instance->ICR = 0xFFFFFFFF; + hsd->Instance->ICR = 0xFFFFFFFFU; } } } @@ -2918,14 +3402,12 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /** * @brief Turns the SDMMC output signals off. * @param hsd: Pointer to SD handle - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd) +static void SD_PowerOFF(SD_HandleTypeDef *hsd) { /* Set Power State to OFF */ - SDMMC_PowerState_OFF(hsd->Instance); - - return HAL_OK; + (void)SDMMC_PowerState_OFF(hsd->Instance); } /** @@ -2938,9 +3420,10 @@ static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd) static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t count = 0; + uint32_t count; + uint32_t *pData = pSDstatus; /* Check SD response */ if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) @@ -2971,7 +3454,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &config); + (void)SDMMC_ConfigData(hsd->Instance, &config); /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */ errorstate = SDMMC_CmdStatusRegister(hsd->Instance); @@ -2990,12 +3473,11 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) { if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) { - for(count = 0; count < 8; count++) + for(count = 0U; count < 8U; count++) { - *(pSDstatus + count) = SDMMC_ReadFIFO(hsd->Instance); + *pData = SDMMC_ReadFIFO(hsd->Instance); + pData++; } - - pSDstatus += 8; } if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) @@ -3016,6 +3498,10 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) { return HAL_SD_ERROR_RX_OVERRUN; } + else + { + /* Nothing to do */ + } #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DPSMACT))) @@ -3023,8 +3509,8 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))) #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ { - *pSDstatus = SDMMC_ReadFIFO(hsd->Instance); - pSDstatus++; + *pData = SDMMC_ReadFIFO(hsd->Instance); + pData++; if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) { @@ -3047,7 +3533,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) */ static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) { - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; if(pCardStatus == NULL) { @@ -3056,7 +3542,7 @@ static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) /* Send Status command */ errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16)); - if(errorstate != HAL_OK) + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -3075,7 +3561,7 @@ static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) { uint32_t scr[2] = {0, 0}; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { @@ -3084,7 +3570,7 @@ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) /* Get SCR Register */ errorstate = SD_FindSCR(hsd, scr); - if(errorstate != HAL_OK) + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -3094,14 +3580,14 @@ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) { /* Send CMD55 APP_CMD with argument as card's RCA.*/ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16)); - if(errorstate != HAL_OK) + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2); - if(errorstate != HAL_OK) + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -3122,7 +3608,7 @@ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) { uint32_t scr[2] = {0, 0}; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { @@ -3131,7 +3617,7 @@ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) /* Get SCR Register */ errorstate = SD_FindSCR(hsd, scr); - if(errorstate != HAL_OK) + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -3141,14 +3627,14 @@ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) { /* Send CMD55 APP_CMD with argument as card's RCA */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16)); - if(errorstate != HAL_OK) + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */ errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0); - if(errorstate != HAL_OK) + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -3171,21 +3657,22 @@ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); uint32_t index = 0; uint32_t tempscr[2] = {0, 0}; + uint32_t *scr = pSCR; /* Set Block Size To 8 Bytes */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8); - if(errorstate != HAL_OK) + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* Send CMD55 APP_CMD with argument as card's RCA */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16)); - if(errorstate != HAL_OK) + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -3196,11 +3683,11 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &config); + (void)SDMMC_ConfigData(hsd->Instance, &config); /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ errorstate = SDMMC_CmdSendSCR(hsd->Instance); - if(errorstate != HAL_OK) + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -3208,7 +3695,7 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DATAEND)) { - if((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0)) + if((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0U)) { tempscr[0] = SDMMC_ReadFIFO(hsd->Instance); tempscr[1] = SDMMC_ReadFIFO(hsd->Instance); @@ -3261,11 +3748,12 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - *(pSCR + 1) = ((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\ - ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24); + *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\ + ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); + scr++; + *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\ + ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); - *(pSCR) = ((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\ - ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24); } return HAL_SD_ERROR_NONE; @@ -3275,48 +3763,60 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) * @brief Wrap up reading in non-blocking mode. * @param hsd: pointer to a SD_HandleTypeDef structure that contains * the configuration information. - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd) +static void SD_Read_IT(SD_HandleTypeDef *hsd) { - uint32_t count = 0; - uint32_t* tmp; + uint32_t count, data; + uint8_t* tmp; - tmp = (uint32_t*)hsd->pRxBuffPtr; + tmp = hsd->pRxBuffPtr; /* Read data from SDMMC Rx FIFO */ - for(count = 0; count < 8; count++) + for(count = 0U; count < 8U; count++) { - *(tmp + count) = SDMMC_ReadFIFO(hsd->Instance); + data = SDMMC_ReadFIFO(hsd->Instance); + *tmp = (uint8_t)(data & 0xFFU); + tmp++; + *tmp = (uint8_t)((data >> 8U) & 0xFFU); + tmp++; + *tmp = (uint8_t)((data >> 16U) & 0xFFU); + tmp++; + *tmp = (uint8_t)((data >> 24U) & 0xFFU); + tmp++; } - hsd->pRxBuffPtr += 8; - - return HAL_OK; + hsd->pRxBuffPtr = tmp; } /** * @brief Wrap up writing in non-blocking mode. * @param hsd: pointer to a SD_HandleTypeDef structure that contains * the configuration information. - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd) +static void SD_Write_IT(SD_HandleTypeDef *hsd) { - uint32_t count = 0; - uint32_t* tmp; + uint32_t count, data; + uint8_t* tmp; - tmp = (uint32_t*)hsd->pTxBuffPtr; + tmp = hsd->pTxBuffPtr; /* Write data to SDMMC Tx FIFO */ - for(count = 0; count < 8; count++) + for(count = 0U; count < 8U; count++) { - SDMMC_WriteFIFO(hsd->Instance, (tmp + count)); + data = (uint32_t)(*tmp); + tmp++; + data |= ((uint32_t)(*tmp) << 8U); + tmp++; + data |= ((uint32_t)(*tmp) << 16U); + tmp++; + data |= ((uint32_t)(*tmp) << 24U); + tmp++; + (void)SDMMC_WriteFIFO(hsd->Instance, &data); } - hsd->pTxBuffPtr += 8; - - return HAL_OK; + hsd->pTxBuffPtr = tmp; } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd_ex.c index 458c2d0f72..552c31477a 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd_ex.c @@ -99,10 +99,11 @@ */ uint32_t HAL_SDEx_HighSpeed(SD_HandleTypeDef *hsd) { - uint32_t errorstate = HAL_OK; + uint32_t errorstate = HAL_SD_ERROR_NONE; SDMMC_DataInitTypeDef sdmmc_datainitstructure; uint8_t SD_hs[64] = {0}; - uint32_t count = 0, *tempbuff = (uint32_t *)SD_hs; + uint8_t *tempbuff = SD_hs; + uint32_t count, data; uint32_t Timeout = HAL_GetTick(); if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED) @@ -118,7 +119,7 @@ uint32_t HAL_SDEx_HighSpeed(SD_HandleTypeDef *hsd) hsd->Instance->DCTRL = 0; errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64); - if (errorstate != HAL_OK) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -130,10 +131,10 @@ uint32_t HAL_SDEx_HighSpeed(SD_HandleTypeDef *hsd) sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure); + (void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure); errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR25_SWITCH_PATTERN); - if(errorstate != HAL_OK) + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -142,19 +143,25 @@ uint32_t HAL_SDEx_HighSpeed(SD_HandleTypeDef *hsd) { if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) { - for (count = 0; count < 8; count++) + for (count = 0U; count < 8U; count++) { - *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance); + data = SDMMC_ReadFIFO(hsd->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; } - - tempbuff += 8; } if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State= HAL_SD_STATE_READY; - return HAL_TIMEOUT; + return HAL_SD_ERROR_TIMEOUT; } } @@ -191,13 +198,18 @@ uint32_t HAL_SDEx_HighSpeed(SD_HandleTypeDef *hsd) __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); /* Test if the switch mode HS is ok */ - if ((SD_hs[13]& 2) != 2) + if ((SD_hs[13U] & 2U) == 0U) { errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + return errorstate; } else { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->DriveTransceiver_1_8V_Callback(SET); +#else HAL_SDEx_DriveTransceiver_1_8V_Callback(SET); +#endif } /* Set Block Size for Card */ @@ -206,7 +218,7 @@ uint32_t HAL_SDEx_HighSpeed(SD_HandleTypeDef *hsd) { hsd->State = HAL_SD_STATE_READY; hsd->ErrorCode |= errorstate; - return HAL_ERROR; + return errorstate; } } @@ -214,7 +226,7 @@ uint32_t HAL_SDEx_HighSpeed(SD_HandleTypeDef *hsd) } /** - * @brief Enable/Disable the SD Transciver 1.8V Mode Callback. + * @brief Enable/Disable the SD Transceiver 1.8V Mode Callback. * @param status: Voltage Switch State * @retval None */ @@ -282,17 +294,21 @@ HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; + uint32_t DmaBase0_reg, DmaBase1_reg; + uint32_t add = BlockAdd; if(hsd->State == HAL_SD_STATE_READY) { - if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } - if ((hsd->Instance->IDMABASE0 == 0) || (hsd->Instance->IDMABASE1 == 0) || (hsd->Instance->IDMABSIZE == 0)) + DmaBase0_reg = hsd->Instance->IDMABASE0; + DmaBase1_reg = hsd->Instance->IDMABASE1; + if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U)) { hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -306,7 +322,7 @@ HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint3 if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { - BlockAdd *= 512; + add *= 512U; } /* Configure the SD DPSM (Data Path State Machine) */ @@ -316,18 +332,18 @@ HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint3 config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_DISABLE; - SDMMC_ConfigData(hsd->Instance, &config); + (void)SDMMC_ConfigData(hsd->Instance, &config); hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; -// /* Set Block Size for Card */ -// errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); -// if(errorstate != HAL_SD_ERROR_NONE) -// { -// hsd->State = HAL_SD_STATE_READY; -// hsd->ErrorCode |= errorstate; -// return HAL_ERROR; -// } + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->State = HAL_SD_STATE_READY; + hsd->ErrorCode |= errorstate; + return HAL_ERROR; + } __SDMMC_CMDTRANS_ENABLE( hsd->Instance); @@ -339,7 +355,7 @@ HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint3 hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA); /* Read Multi Block command */ - errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); if(errorstate != HAL_SD_ERROR_NONE) { hsd->State = HAL_SD_STATE_READY; @@ -367,17 +383,21 @@ HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint3 HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; + uint32_t DmaBase0_reg, DmaBase1_reg; + uint32_t add = BlockAdd; if(hsd->State == HAL_SD_STATE_READY) { - if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } - if ((hsd->Instance->IDMABASE0 == 0) || (hsd->Instance->IDMABASE1 == 0) || (hsd->Instance->IDMABSIZE == 0)) + DmaBase0_reg = hsd->Instance->IDMABASE0; + DmaBase1_reg = hsd->Instance->IDMABASE1; + if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U)) { hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -392,7 +412,7 @@ HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { - BlockAdd *= 512; + add *= 512U; } /* Configure the SD DPSM (Data Path State Machine) */ @@ -402,16 +422,16 @@ HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_DISABLE; - SDMMC_ConfigData(hsd->Instance, &config); + (void)SDMMC_ConfigData(hsd->Instance, &config); -// /* Set Block Size for Card */ -// errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); -// if(errorstate != HAL_SD_ERROR_NONE) -// { -// hsd->State = HAL_SD_STATE_READY; -// hsd->ErrorCode |= errorstate; -// return HAL_ERROR; -// } + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->State = HAL_SD_STATE_READY; + hsd->ErrorCode |= errorstate; + return HAL_ERROR; + } __SDMMC_CMDTRANS_ENABLE( hsd->Instance); @@ -423,7 +443,7 @@ HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA); /* Write Multi Block command */ - errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); if(errorstate != HAL_SD_ERROR_NONE) { hsd->State = HAL_SD_STATE_READY; diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard.c index e11f3a2c78..d8b6f47531 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard.c @@ -26,8 +26,8 @@ (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input). (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT() and HAL_SMARTCARD_Receive_IT() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA() and HAL_SMARTCARD_Receive_DMA() APIs): (+++) Declare a DMA handle structure for the Tx/Rx channel. @@ -99,6 +99,71 @@ [..] (@) You can refer to the SMARTCARD HAL driver header file for more useful macros + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback. + Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks: + (+) TxCpltCallback : Tx Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : SMARTCARD MspInit. + (+) MspDeInitCallback : SMARTCARD MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxCpltCallback : Tx Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : SMARTCARD MspInit. + (+) MspDeInitCallback : SMARTCARD MspDeInit. + + [..] + By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET + all callbacks are set to the corresponding weak (surcharged) functions: + examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init() + and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit() + or @ref HAL_SMARTCARD_Init() function. + + [..] + When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak (surcharged) callbacks are used. + + @endverbatim ****************************************************************************** * @attention @@ -149,7 +214,7 @@ /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants * @{ */ -#define SMARTCARD_TEACK_REACK_TIMEOUT 1000 /*!< SMARTCARD TX or RX enable acknowledge time-out value */ +#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */ #if defined(USART_CR1_FIFOEN) #define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ @@ -180,7 +245,7 @@ */ /* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ +/* Private variables -----------------------------------------------------*/ #if defined(USART_PRESC_PRESCALER) /** @defgroup SMARTCARD_Private_Variables SMARTCARD Private Variables * @{ @@ -195,6 +260,9 @@ static const uint16_t SMARTCARDPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, /** @addtogroup SMARTCARD_Private_Functions * @{ */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard); static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard); static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard); @@ -229,7 +297,7 @@ static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard); */ /** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * @verbatim ============================================================================== @@ -266,27 +334,27 @@ static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard); The USART frame format is given in the following table: Table 1. USART frame format. - +---------------------------------------------------------------+ - | M1M0 bits | PCE bit | USART frame | - |-----------------------|---------------------------------------| - | 01 | 1 | | SB | 8 bit data | PB | STB | | - +---------------------------------------------------------------+ + +---------------------------------------------------------------+ + | M1M0 bits | PCE bit | USART frame | + |-----------------------|---------------------------------------| + | 01 | 1 | | SB | 8 bit data | PB | STB | | + +---------------------------------------------------------------+ * @{ */ /** - * @brief Initialize the SMARTCARD mode according to the specified + * @brief Initialize the SMARTCARD mode according to the specified * parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) { /* Check the SMARTCARD handle allocation */ - if(hsmartcard == NULL) + if (hsmartcard == NULL) { return HAL_ERROR; } @@ -294,13 +362,25 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) /* Check the USART associated to the SMARTCARD handle */ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); - if(hsmartcard->gState == HAL_SMARTCARD_STATE_RESET) + if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET) { /* Allocate lock resource and initialize it */ hsmartcard->Lock = HAL_UNLOCKED; +#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1 + SMARTCARD_InitCallbacksToDefault(hsmartcard); + + if (hsmartcard->MspInitCallback == NULL) + { + hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; + } + + /* Init the low level hardware */ + hsmartcard->MspInitCallback(hsmartcard); +#else /* Init the low level hardware : GPIO, CLOCK */ HAL_SMARTCARD_MspInit(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ } hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; @@ -322,8 +402,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) { return HAL_ERROR; } - - /* Set the SMARTCARD transmission completion indication */ + + /* Set the SMARTCARD transmission completion indication */ SMARTCARD_TRANSMISSION_COMPLETION_SETTING(hsmartcard); if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT) @@ -339,15 +419,15 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) } /** - * @brief DeInitialize the SMARTCARD peripheral. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief DeInitialize the SMARTCARD peripheral. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) { /* Check the SMARTCARD handle allocation */ - if(hsmartcard == NULL) + if (hsmartcard == NULL) { return HAL_ERROR; } @@ -360,14 +440,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the Peripheral */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - WRITE_REG(hsmartcard->Instance->CR1, 0x0); - WRITE_REG(hsmartcard->Instance->CR2, 0x0); - WRITE_REG(hsmartcard->Instance->CR3, 0x0); - WRITE_REG(hsmartcard->Instance->RTOR, 0x0); - WRITE_REG(hsmartcard->Instance->GTPR, 0x0); + WRITE_REG(hsmartcard->Instance->CR1, 0x0U); + WRITE_REG(hsmartcard->Instance->CR2, 0x0U); + WRITE_REG(hsmartcard->Instance->CR3, 0x0U); + WRITE_REG(hsmartcard->Instance->RTOR, 0x0U); + WRITE_REG(hsmartcard->Instance->GTPR, 0x0U); /* DeInit the low level hardware */ +#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1 + if (hsmartcard->MspDeInitCallback == NULL) + { + hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; + } + /* DeInit the low level hardware */ + hsmartcard->MspDeInitCallback(hsmartcard); +#else HAL_SMARTCARD_MspDeInit(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; hsmartcard->gState = HAL_SMARTCARD_STATE_RESET; @@ -380,43 +469,286 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) } /** - * @brief Initialize the SMARTCARD MSP. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Initialize the SMARTCARD MSP. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ - __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard) +__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMARTCARD_MspInit can be implemented in the user file */ } /** - * @brief DeInitialize the SMARTCARD MSP. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief DeInitialize the SMARTCARD MSP. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ - __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) +__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMARTCARD_MspDeInit can be implemented in the user file */ } +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User SMARTCARD Callback + * To be used instead of the weak predefined callback + * @param hsmartcard smartcard handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hsmartcard); + + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + switch (CallbackID) + { + + case HAL_SMARTCARD_TX_COMPLETE_CB_ID : + hsmartcard->TxCpltCallback = pCallback; + break; + + case HAL_SMARTCARD_RX_COMPLETE_CB_ID : + hsmartcard->RxCpltCallback = pCallback; + break; + + case HAL_SMARTCARD_ERROR_CB_ID : + hsmartcard->ErrorCallback = pCallback; + break; + + case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID : + hsmartcard->AbortCpltCallback = pCallback; + break; + + case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID : + hsmartcard->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID : + hsmartcard->AbortReceiveCpltCallback = pCallback; + break; + +#if defined(USART_CR1_FIFOEN) + case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID : + hsmartcard->RxFifoFullCallback = pCallback; + break; + + case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID : + hsmartcard->TxFifoEmptyCallback = pCallback; + break; +#endif + + case HAL_SMARTCARD_MSPINIT_CB_ID : + hsmartcard->MspInitCallback = pCallback; + break; + + case HAL_SMARTCARD_MSPDEINIT_CB_ID : + hsmartcard->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SMARTCARD_MSPINIT_CB_ID : + hsmartcard->MspInitCallback = pCallback; + break; + + case HAL_SMARTCARD_MSPDEINIT_CB_ID : + hsmartcard->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsmartcard); + + return status; +} + +/** + * @brief Unregister an SMARTCARD callback + * SMARTCARD callback is redirected to the weak predefined callback + * @param hsmartcard smartcard handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hsmartcard); + + if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState) + { + switch (CallbackID) + { + case HAL_SMARTCARD_TX_COMPLETE_CB_ID : + hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_SMARTCARD_RX_COMPLETE_CB_ID : + hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_SMARTCARD_ERROR_CB_ID : + hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID : + hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID : + hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + break; + + case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID : + hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + break; + +#if defined(USART_CR1_FIFOEN) + case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID : + hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + break; + + case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID : + hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + break; +#endif + + case HAL_SMARTCARD_MSPINIT_CB_ID : + hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_SMARTCARD_MSPDEINIT_CB_ID : + hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SMARTCARD_STATE_RESET == hsmartcard->gState) + { + switch (CallbackID) + { + case HAL_SMARTCARD_MSPINIT_CB_ID : + hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; + break; + + case HAL_SMARTCARD_MSPDEINIT_CB_ID : + hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; + break; + + default : + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsmartcard); + + return status; +} +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + /** * @} */ /** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions - * @brief SMARTCARD Transmit and Receive functions + * @brief SMARTCARD Transmit and Receive functions * @verbatim ============================================================================== @@ -480,7 +812,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side. @@ -494,13 +826,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) */ /** - * @brief Send an amount of data in blocking mode. - * @note When FIFO mode is enabled, writing a data in the TDR register adds one - * data to the TXFIFO. Write operations to the TDR register are performed - * when TXFNF flag is set. From hardware perspective, TXFNF flag and - * TXE are mapped on the same bit-field. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Send an amount of data in blocking mode. + * @note When FIFO mode is enabled, writing a data in the TDR register adds one + * data to the TXFIFO. Write operations to the TDR register are performed + * when TXFNF flag is set. From hardware perspective, TXFNF flag and + * TXE are mapped on the same bit-field. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be sent. * @param Timeout Timeout duration. @@ -508,12 +840,12 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Check that a Tx process is not already ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -523,7 +855,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Disable the Peripheral first to update mode for TX master */ @@ -533,7 +865,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); - + /* Enable the Peripheral */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); @@ -541,21 +873,21 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui hsmartcard->TxXferSize = Size; hsmartcard->TxXferCount = Size; - while(hsmartcard->TxXferCount > 0) + while (hsmartcard->TxXferCount > 0U) { hsmartcard->TxXferCount--; - if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFF); } - if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, Timeout) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */ - if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) + if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) { /* Disable the Peripheral first to update modes */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); @@ -563,7 +895,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui /* Enable the Peripheral */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); } - + /* At end of Tx process, restore hsmartcard->gState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -579,13 +911,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui } /** - * @brief Receive an amount of data in blocking mode. - * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO - * is not empty. Read operations from the RDR register are performed when - * RXFNE flag is set. From hardware perspective, RXFNE flag and - * RXNE are mapped on the same bit-field. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Receive an amount of data in blocking mode. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be received. * @param Timeout Timeout duration. @@ -593,12 +925,12 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui */ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Check that a Rx process is not already ongoing */ - if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -609,18 +941,18 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); hsmartcard->RxXferSize = Size; hsmartcard->RxXferCount = Size; /* Check the remain data to be received */ - while(hsmartcard->RxXferCount > 0) + while (hsmartcard->RxXferCount > 0U) { hsmartcard->RxXferCount--; - if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -642,16 +974,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin } /** - * @brief Send an amount of data in interrupt mode. - * @note When FIFO mode is disabled, USART interrupt is generated whenever - * USART_TDR register is empty, i.e one interrupt per data to transmit. - * @note When FIFO mode is enabled, USART interrupt is generated whenever - * TXFIFO threshold reached. In that case the interrupt rate depends on - * TXFIFO threshold configuration. - * @note This function sets the hsmartcard->TxIsr function pointer according to - * the FIFO mode (data transmission processing depends on FIFO mode). - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Send an amount of data in interrupt mode. + * @note When FIFO mode is disabled, USART interrupt is generated whenever + * USART_TDR register is empty, i.e one interrupt per data to transmit. + * @note When FIFO mode is enabled, USART interrupt is generated whenever + * TXFIFO threshold reached. In that case the interrupt rate depends on + * TXFIFO threshold configuration. + * @note This function sets the hsmartcard->TxIsr function pointer according to + * the FIFO mode (data transmission processing depends on FIFO mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be sent. * @retval HAL status @@ -661,46 +993,46 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, /* Check that a Tx process is not already ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hsmartcard); - + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX; - + hsmartcard->pTxBuffPtr = pData; hsmartcard->TxXferSize = Size; hsmartcard->TxXferCount = Size; hsmartcard->TxISR = NULL; - + /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - + /* Disable Rx, enable Tx */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); - + /* Enable the Peripheral */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - -#if defined(USART_CR1_FIFOEN) + /* Configure Tx interrupt processing */ +#if defined(USART_CR1_FIFOEN) if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) - { + { /* Set the Tx ISR function pointer */ hsmartcard->TxISR = SMARTCARD_TxISR_FIFOEN; - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + /* Enable the SMARTCARD Error Interrupt: (Frame error) */ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - + /* Enable the TX FIFO threshold interrupt */ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE); } @@ -709,13 +1041,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, { /* Set the Tx ISR function pointer */ hsmartcard->TxISR = SMARTCARD_TxISR; - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + /* Enable the SMARTCARD Error Interrupt: (Frame error) */ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - + /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */ #if defined(USART_CR1_FIFOEN) SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); @@ -723,7 +1055,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE); #endif } - + return HAL_OK; } else @@ -733,16 +1065,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, } /** - * @brief Receive an amount of data in interrupt mode. - * @note When FIFO mode is disabled, USART interrupt is generated whenever - * USART_RDR register can be read, i.e one interrupt per data to receive. - * @note When FIFO mode is enabled, USART interrupt is generated whenever - * RXFIFO threshold reached. In that case the interrupt rate depends on - * RXFIFO threshold configuration. - * @note This function sets the hsmartcard->RxIsr function pointer according to - * the FIFO mode (data reception processing depends on FIFO mode). - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Receive an amount of data in interrupt mode. + * @note When FIFO mode is disabled, USART interrupt is generated whenever + * USART_RDR register can be read, i.e one interrupt per data to receive. + * @note When FIFO mode is enabled, USART interrupt is generated whenever + * RXFIFO threshold reached. In that case the interrupt rate depends on + * RXFIFO threshold configuration. + * @note This function sets the hsmartcard->RxIsr function pointer according to + * the FIFO mode (data reception processing depends on FIFO mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be received. * @retval HAL status @@ -750,9 +1082,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) { /* Check that a Rx process is not already ongoing */ - if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -770,13 +1102,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, /* Configure Rx interrupt processing */ #if defined(USART_CR1_FIFOEN) if ((hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) && (Size >= hsmartcard->NbRxDataToProcess)) - { + { /* Set the Rx ISR function pointer */ hsmartcard->RxISR = SMARTCARD_RxISR_FIFOEN; /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + /* Enable the SMARTCART Parity Error interrupt and RX FIFO Threshold interrupt */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); SET_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE); @@ -789,15 +1121,15 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */ #if defined(USART_CR1_FIFOEN) - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE_RXFNEIE); + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); #else - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE); + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); #endif } - + /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); @@ -810,9 +1142,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, } /** - * @brief Send an amount of data in DMA mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Send an amount of data in DMA mode. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be sent. * @retval HAL status @@ -822,7 +1154,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard /* Check that a Tx process is not already ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -844,7 +1176,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); - + /* Enable the Peripheral */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); @@ -882,9 +1214,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard } /** - * @brief Receive an amount of data in DMA mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Receive an amount of data in DMA mode. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be received. * @note The SMARTCARD-associated USART parity is enabled (PCE = 1), @@ -894,9 +1226,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) { /* Check that a Rx process is not already ongoing */ - if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -925,10 +1257,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - /* Enable the UART Parity Error Interrupt */ + /* Enable the SMARTCARD Parity Error Interrupt */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); /* Enable the DMA transfer for the receiver request by setting the DMAR bit @@ -946,8 +1278,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, /** * @brief Abort ongoing transfers (blocking mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Tx and Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -973,9 +1305,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */ - if(hsmartcard->hdmatx != NULL) + if (hsmartcard->hdmatx != NULL) { - /* Set the SMARTCARD DMA Abort callback to Null. + /* Set the SMARTCARD DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ hsmartcard->hdmatx->XferAbortCallback = NULL; @@ -989,9 +1321,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ - if(hsmartcard->hdmarx != NULL) + if (hsmartcard->hdmarx != NULL) { - /* Set the SMARTCARD DMA Abort callback to Null. + /* Set the SMARTCARD DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ hsmartcard->hdmarx->XferAbortCallback = NULL; @@ -1000,8 +1332,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) } /* Reset Tx and Rx transfer counters */ - hsmartcard->TxXferCount = 0; - hsmartcard->RxXferCount = 0; + hsmartcard->TxXferCount = 0U; + hsmartcard->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); @@ -1019,8 +1351,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief Abort ongoing Transmit transfer (blocking mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Tx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1041,7 +1373,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar #endif /* Check if a receive process is ongoing or not. If not disable ERR IT */ - if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) { /* Disable the SMARTCARD Error Interrupt: (Frame error) */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); @@ -1053,9 +1385,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */ - if(hsmartcard->hdmatx != NULL) + if (hsmartcard->hdmatx != NULL) { - /* Set the SMARTCARD DMA Abort callback to Null. + /* Set the SMARTCARD DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ hsmartcard->hdmatx->XferAbortCallback = NULL; @@ -1064,7 +1396,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar } /* Reset Tx transfer counter */ - hsmartcard->TxXferCount = 0; + hsmartcard->TxXferCount = 0U; /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF); @@ -1078,8 +1410,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar /** * @brief Abort ongoing Receive transfer (blocking mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1101,7 +1433,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard #endif /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ - if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { /* Disable the SMARTCARD Error Interrupt: (Frame error) */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); @@ -1113,9 +1445,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ - if(hsmartcard->hdmarx != NULL) + if (hsmartcard->hdmarx != NULL) { - /* Set the SMARTCARD DMA Abort callback to Null. + /* Set the SMARTCARD DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ hsmartcard->hdmarx->XferAbortCallback = NULL; @@ -1124,7 +1456,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard } /* Reset Rx transfer counter */ - hsmartcard->RxXferCount = 0; + hsmartcard->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); @@ -1138,8 +1470,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard /** * @brief Abort ongoing transfers (Interrupt mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Tx and Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1152,8 +1484,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard */ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) { - uint32_t abortcplt = 1; - + uint32_t abortcplt = 1U; + #if defined(USART_CR1_FIFOEN) /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); @@ -1167,11 +1499,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ /* DMA Tx Handle is valid */ - if(hsmartcard->hdmatx != NULL) + if (hsmartcard->hdmatx != NULL) { /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled. Otherwise, set it to NULL */ - if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback; } @@ -1181,11 +1513,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) } } /* DMA Rx Handle is valid */ - if(hsmartcard->hdmarx != NULL) + if (hsmartcard->hdmarx != NULL) { /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled. Otherwise, set it to NULL */ - if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback; } @@ -1196,25 +1528,25 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) } /* Disable the SMARTCARD DMA Tx request if enabled */ - if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { /* Disable DMA Tx at UART level */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ - if(hsmartcard->hdmatx != NULL) + if (hsmartcard->hdmatx != NULL) { - /* SMARTCARD Tx DMA Abort callback has already been initialised : + /* SMARTCARD Tx DMA Abort callback has already been initialised : will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) + if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) { hsmartcard->hdmatx->XferAbortCallback = NULL; } else { - abortcplt = 0; + abortcplt = 0U; } } } @@ -1225,30 +1557,30 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ - if(hsmartcard->hdmarx != NULL) + if (hsmartcard->hdmarx != NULL) { - /* SMARTCARD Rx DMA Abort callback has already been initialised : + /* SMARTCARD Rx DMA Abort callback has already been initialised : will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) { hsmartcard->hdmarx->XferAbortCallback = NULL; - abortcplt = 1; + abortcplt = 1U; } else { - abortcplt = 0; + abortcplt = 0U; } } } /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ - if (abortcplt == 1) + if (abortcplt == 1U) { /* Reset Tx and Rx transfer counters */ - hsmartcard->TxXferCount = 0; - hsmartcard->RxXferCount = 0; + hsmartcard->TxXferCount = 0U; + hsmartcard->RxXferCount = 0U; /* Clear ISR function pointers */ hsmartcard->RxISR = NULL; @@ -1265,7 +1597,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hsmartcard->AbortCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort complete callback */ HAL_SMARTCARD_AbortCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } return HAL_OK; @@ -1274,8 +1612,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief Abort ongoing Transmit transfer (Interrupt mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Tx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1298,7 +1636,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart #endif /* Check if a receive process is ongoing or not. If not disable ERR IT */ - if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) { /* Disable the SMARTCARD Error Interrupt: (Frame error) */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); @@ -1310,14 +1648,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ - if(hsmartcard->hdmatx != NULL) + if (hsmartcard->hdmatx != NULL) { - /* Set the SMARTCARD DMA Abort callback : + /* Set the SMARTCARD DMA Abort callback : will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback; /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) + if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) { /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */ hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx); @@ -1326,7 +1664,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart else { /* Reset Tx transfer counter */ - hsmartcard->TxXferCount = 0; + hsmartcard->TxXferCount = 0U; /* Clear TxISR function pointers */ hsmartcard->TxISR = NULL; @@ -1335,25 +1673,37 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart hsmartcard->gState = HAL_SMARTCARD_STATE_READY; /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hsmartcard->AbortTransmitCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Transmit Complete Callback */ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } } else { /* Reset Tx transfer counter */ - hsmartcard->TxXferCount = 0; - + hsmartcard->TxXferCount = 0U; + /* Clear TxISR function pointers */ hsmartcard->TxISR = NULL; - + /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF); - + /* Restore hsmartcard->gState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hsmartcard->AbortTransmitCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Transmit Complete Callback */ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } return HAL_OK; @@ -1362,8 +1712,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart /** * @brief Abort ongoing Receive transfer (Interrupt mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1385,28 +1735,28 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); #endif - + /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ - if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { /* Disable the SMARTCARD Error Interrupt: (Frame error) */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); } - + /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); - + /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ - if(hsmartcard->hdmarx != NULL) + if (hsmartcard->hdmarx != NULL) { - /* Set the SMARTCARD DMA Abort callback : - will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback; - + /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) { /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */ hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx); @@ -1415,46 +1765,58 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc else { /* Reset Rx transfer counter */ - hsmartcard->RxXferCount = 0; - + hsmartcard->RxXferCount = 0U; + /* Clear RxISR function pointer */ hsmartcard->RxISR = NULL; - + /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); - + /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hsmartcard->AbortReceiveCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Receive Complete Callback */ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } } else { /* Reset Rx transfer counter */ - hsmartcard->RxXferCount = 0; - + hsmartcard->RxXferCount = 0U; + /* Clear RxISR function pointer */ hsmartcard->RxISR = NULL; - + /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); - + /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hsmartcard->AbortReceiveCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Receive Complete Callback */ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } - + return HAL_OK; } /** - * @brief Handle SMARTCARD interrupt requests. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Handle SMARTCARD interrupt requests. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) @@ -1463,129 +1825,135 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) uint32_t cr1its = READ_REG(hsmartcard->Instance->CR1); uint32_t cr3its = READ_REG(hsmartcard->Instance->CR3); uint32_t errorflags; - + /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); if (errorflags == RESET) { /* SMARTCARD in mode Receiver ---------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) - && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) + if (((isrflags & USART_ISR_RXNE_RXFNE) != RESET) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) + || ((cr3its & USART_CR3_RXFTIE) != RESET))) #else - if(((isrflags & USART_ISR_RXNE) != RESET) + if (((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) #endif { - if (hsmartcard->RxISR != NULL) {hsmartcard->RxISR(hsmartcard);} + if (hsmartcard->RxISR != NULL) + { + hsmartcard->RxISR(hsmartcard); + } return; } - } - + } + /* If some errors occur */ #if defined(USART_CR1_FIFOEN) - if( (errorflags != RESET) - && ( (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET) - || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET))) ) + if ((errorflags != RESET) + && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET)))) #else - if( (errorflags != RESET) - && ( ((cr3its & USART_CR3_EIE) != RESET) - || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) ) + if ((errorflags != RESET) + && (((cr3its & USART_CR3_EIE) != RESET) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) #endif { /* SMARTCARD parity error interrupt occurred -------------------------------------*/ - if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + if (((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF); - + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE; } - + /* SMARTCARD frame error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF); - + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE; } - + /* SMARTCARD noise error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF); - + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE; } - + /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if( ((isrflags & USART_ISR_ORE) != RESET) - && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET) - || ((cr3its & USART_CR3_EIE) != RESET)) ) + if (((isrflags & USART_ISR_ORE) != RESET) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) + || ((cr3its & USART_CR3_RXFTIE) != RESET) + || ((cr3its & USART_CR3_EIE) != RESET))) #else - if( ((isrflags & USART_ISR_ORE) != RESET) - && ( ((cr1its & USART_CR1_RXNEIE) != RESET) - || ((cr3its & USART_CR3_EIE) != RESET)) ) + if (((isrflags & USART_ISR_ORE) != RESET) + && (((cr1its & USART_CR1_RXNEIE) != RESET) + || ((cr3its & USART_CR3_EIE) != RESET))) #endif { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF); - + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; } - + /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/ - if(((isrflags & USART_ISR_RTOF) != RESET) && ((cr1its & USART_CR1_RTOIE) != RESET)) + if (((isrflags & USART_ISR_RTOF) != RESET) && ((cr1its & USART_CR1_RTOIE) != RESET)) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF); - + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO; } - + /* Call SMARTCARD Error Call back function if need be --------------------------*/ - if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE) + if (hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE) { /* SMARTCARD in mode Receiver ---------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) - && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) + if (((isrflags & USART_ISR_RXNE_RXFNE) != RESET) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) + || ((cr3its & USART_CR3_RXFTIE) != RESET))) #else - if(((isrflags & USART_ISR_RXNE) != RESET) - && ((cr1its & USART_CR1_RXNEIE) != RESET) ) + if (((isrflags & USART_ISR_RXNE) != RESET) + && ((cr1its & USART_CR1_RXNEIE) != RESET)) #endif { - if (hsmartcard->RxISR != NULL) {hsmartcard->RxISR(hsmartcard);} + if (hsmartcard->RxISR != NULL) + { + hsmartcard->RxISR(hsmartcard); + } } - + /* If Error is to be considered as blocking : - Receiver Timeout error in Reception - Overrun error in Reception - any error occurs in DMA mode reception */ - if ( ((hsmartcard->ErrorCode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != RESET) - || (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))) - { + if ((HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + || ((hsmartcard->ErrorCode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != RESET)) + { /* Blocking error : transfer is aborted Set the SMARTCARD state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ SMARTCARD_EndRxTransfer(hsmartcard); - + /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); - + /* Abort the SMARTCARD DMA Rx channel */ - if(hsmartcard->hdmarx != NULL) + if (hsmartcard->hdmarx != NULL) { - /* Set the SMARTCARD DMA Abort callback : - will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError; - + /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) { /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */ hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx); @@ -1593,41 +1961,51 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) } else { - /* Call user error callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } } else { - /* Call user error callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } } /* other error type to be considered as blocking : - Frame error in Transmission */ - else if ( (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) - && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != RESET)) + else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) + && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != RESET)) { /* Blocking error : transfer is aborted Set the SMARTCARD state ready to be able to start again the process, Disable Tx Interrupts, and disable Tx DMA request, if ongoing */ SMARTCARD_EndTxTransfer(hsmartcard); - + /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); - + /* Abort the SMARTCARD DMA Tx channel */ - if(hsmartcard->hdmatx != NULL) + if (hsmartcard->hdmatx != NULL) { - /* Set the SMARTCARD DMA Abort callback : - will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError; - + /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) + if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) { /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */ hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx); @@ -1635,122 +2013,159 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) } else { - /* Call user error callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } } else { - /* Call user error callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } } else { - /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; } } return; - + } /* End if some error occurs */ - + /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/ - if(((isrflags & USART_ISR_EOBF) != RESET) && ((cr1its & USART_CR1_EOBIE) != RESET)) + if (((isrflags & USART_ISR_EOBF) != RESET) && ((cr1its & USART_CR1_EOBIE) != RESET)) { hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; __HAL_UNLOCK(hsmartcard); +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hsmartcard->RxCpltCallback(hsmartcard); +#else + /* Call legacy weak Rx complete callback */ HAL_SMARTCARD_RxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information * to be available during HAL_SMARTCARD_RxCpltCallback() processing */ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF); return; } - + /* SMARTCARD in mode Transmitter ------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_TXE_TXFNF) != RESET) - && ( ((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET) - || ((cr3its & USART_CR3_TXFTIE) != RESET)) ) + if (((isrflags & USART_ISR_TXE_TXFNF) != RESET) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET) + || ((cr3its & USART_CR3_TXFTIE) != RESET))) #else - if(((isrflags & USART_ISR_TXE) != RESET) + if (((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) #endif { - if (hsmartcard->TxISR != NULL) {hsmartcard->TxISR(hsmartcard);} + if (hsmartcard->TxISR != NULL) + { + hsmartcard->TxISR(hsmartcard); + } return; } - + /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ - if( (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) + if ((__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)) { SMARTCARD_EndTransmit_IT(hsmartcard); return; } - + #if defined(USART_CR1_FIFOEN) /* SMARTCARD TX Fifo Empty occurred ----------------------------------------------*/ - if(((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET)) + if (((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET)) { +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + hsmartcard->TxFifoEmptyCallback(hsmartcard); +#else + /* Call legacy weak Tx Fifo Empty Callback */ HAL_SMARTCARDEx_TxFifoEmptyCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ return; } - + /* SMARTCARD RX Fifo Full occurred ----------------------------------------------*/ - if(((isrflags & USART_ISR_RXFF) != RESET) && ((cr1its & USART_CR1_RXFFIE) != RESET)) + if (((isrflags & USART_ISR_RXFF) != RESET) && ((cr1its & USART_CR1_RXFFIE) != RESET)) { +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + hsmartcard->RxFifoFullCallback(hsmartcard); +#else + /* Call legacy weak Rx Fifo Full Callback */ HAL_SMARTCARDEx_RxFifoFullCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ return; } #endif } /** - * @brief Tx Transfer completed callback. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Tx Transfer completed callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ - __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) +__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file. */ } /** - * @brief Rx Transfer completed callback. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Rx Transfer completed callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file. */ } /** - * @brief SMARTCARD error callback. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief SMARTCARD error callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMARTCARD_ErrorCallback can be implemented in the user file. */ @@ -1759,10 +2174,10 @@ __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief SMARTCARD Abort Complete callback. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @retval None */ -__weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard) +__weak void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); @@ -1775,10 +2190,10 @@ __weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard /** * @brief SMARTCARD Abort Complete callback. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @retval None */ -__weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard) +__weak void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); @@ -1791,10 +2206,10 @@ __weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hs /** * @brief SMARTCARD Abort Receive Complete callback. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @retval None */ -__weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard) +__weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); @@ -1809,7 +2224,7 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsm */ /** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief SMARTCARD State and Errors functions + * @brief SMARTCARD State and Errors functions * @verbatim ============================================================================== @@ -1829,26 +2244,26 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsm /** * @brief Return the SMARTCARD handle state. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval SMARTCARD handle state */ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard) { /* Return SMARTCARD handle state */ - uint32_t temp1= 0x00, temp2 = 0x00; + uint32_t temp1, temp2; temp1 = hsmartcard->gState; temp2 = hsmartcard->RxState; - + return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2); } /** * @brief Return the SMARTCARD handle error code. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. -* @retval SMARTCARD handle Error Code -*/ + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval SMARTCARD handle Error Code + */ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) { return hsmartcard->ErrorCode; @@ -1862,19 +2277,42 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) * @} */ -/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions +/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions * @{ */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) /** - * @brief Configure the SMARTCARD associated USART peripheral. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Initialize the callbacks to their default values. + * @param hsmartcard SMARTCARD handle. + * @retval none + */ +void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Init the SMARTCARD Callback settings */ + hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ + hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ +#if defined(USART_CR1_FIFOEN) + hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ +#endif + +} +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + +/** + * @brief Configure the SMARTCARD associated USART peripheral. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval HAL status */ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard) { - uint32_t tmpreg = 0x00000000; + uint32_t tmpreg; SMARTCARD_ClockSourceTypeDef clocksource = SMARTCARD_CLOCKSOURCE_UNDEFINED; HAL_StatusTypeDef ret = HAL_OK; @@ -1902,7 +2340,12 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard * Configure the Parity and Mode: * set PS bit according to hsmartcard->Init.Parity value * set TE and RE bits according to hsmartcard->Init.Mode value */ +#if defined(USART_CR1_FIFOEN) + tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode; + tmpreg |= (uint32_t) hsmartcard->Init.WordLength | hsmartcard->FifoMode; +#else tmpreg = (uint32_t) (hsmartcard->Init.Parity | hsmartcard->Init.Mode | hsmartcard->Init.WordLength); +#endif MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg); /*-------------------------- USART CR2 Configuration -----------------------*/ @@ -1919,8 +2362,9 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard * according to hsmartcard->Init.OneBitSampling * - NACK transmission in case of parity error according * to hsmartcard->Init.NACKEnable - * - autoretry counter according to hsmartcard->Init.AutoRetryCount */ - tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable; + * - autoretry counter according to hsmartcard->Init.AutoRetryCount */ + + tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable; tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << USART_CR3_SCARCNT_Pos); MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_FIELDS, tmpreg); @@ -1933,63 +2377,63 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard /*-------------------------- USART GTPR Configuration ----------------------*/ tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos)); - MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg); + MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT | USART_GTPR_PSC), tmpreg); /*-------------------------- USART RTOR Configuration ----------------------*/ - tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos); + tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos); if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE) { assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); - tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue; + tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue; } - MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg); + MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg); /*-------------------------- USART BRR Configuration -----------------------*/ SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource); - tmpreg = 0; + tmpreg = 0U; switch (clocksource) { - case SMARTCARD_CLOCKSOURCE_PCLK1: + case SMARTCARD_CLOCKSOURCE_PCLK1: #if defined(USART_PRESC_PRESCALER) - tmpreg = (uint16_t)((HAL_RCC_GetPCLK1Freq()/SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)((HAL_RCC_GetPCLK1Freq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #else - tmpreg = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #endif - break; - case SMARTCARD_CLOCKSOURCE_PCLK2: + break; + case SMARTCARD_CLOCKSOURCE_PCLK2: #if defined(USART_PRESC_PRESCALER) - tmpreg = (uint16_t)((HAL_RCC_GetPCLK2Freq()/SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)((HAL_RCC_GetPCLK2Freq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #else - tmpreg = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #endif - break; - case SMARTCARD_CLOCKSOURCE_HSI: + break; + case SMARTCARD_CLOCKSOURCE_HSI: #if defined(USART_PRESC_PRESCALER) - tmpreg = (uint16_t)((HSI_VALUE/SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #else - tmpreg = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #endif - break; - case SMARTCARD_CLOCKSOURCE_SYSCLK: + break; + case SMARTCARD_CLOCKSOURCE_SYSCLK: #if defined(USART_PRESC_PRESCALER) - tmpreg = (uint16_t)((HAL_RCC_GetSysClockFreq()/SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)((HAL_RCC_GetSysClockFreq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #else - tmpreg = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #endif - break; - case SMARTCARD_CLOCKSOURCE_LSE: + break; + case SMARTCARD_CLOCKSOURCE_LSE: #if defined(USART_PRESC_PRESCALER) - tmpreg = (uint16_t)((LSE_VALUE/SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)((LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #else - tmpreg = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #endif - break; - case SMARTCARD_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; + break; + case SMARTCARD_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; } - + /* USARTDIV must be greater than or equal to 0d16 */ if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX)) { @@ -1999,11 +2443,11 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard { ret = HAL_ERROR; } - + #if defined(USART_CR1_FIFOEN) /* Initialize the number of data to process during RX/TX ISR execution */ - hsmartcard->NbTxDataToProcess = 1; - hsmartcard->NbRxDataToProcess = 1; + hsmartcard->NbTxDataToProcess = 1U; + hsmartcard->NbRxDataToProcess = 1U; #endif /* Clear ISR function pointers */ @@ -2084,29 +2528,29 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard) */ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Initialize the SMARTCARD ErrorCode */ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Check if the Transmitter is enabled */ - if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + if ((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) { /* Wait until TEACK flag is set */ - if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; } } /* Check if the Receiver is enabled */ - if((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + if ((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) { /* Wait until REACK flag is set */ - if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; @@ -2136,12 +2580,12 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ - while((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status) + while ((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout)) + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ #if defined(USART_CR1_FIFOEN) @@ -2150,10 +2594,10 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); #endif CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); return HAL_TIMEOUT; @@ -2167,7 +2611,7 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe /** * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @retval None */ static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) @@ -2188,7 +2632,7 @@ static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @retval None */ static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) @@ -2207,15 +2651,15 @@ static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) /** - * @brief DMA SMARTCARD transmit process complete callback. + * @brief DMA SMARTCARD transmit process complete callback. * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent); - hsmartcard->TxXferCount = 0; + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + hsmartcard->TxXferCount = 0U; /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the SMARTCARD associated USART CR3 register */ @@ -2226,15 +2670,15 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA SMARTCARD receive process complete callback. + * @brief DMA SMARTCARD receive process complete callback. * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent); - hsmartcard->RxXferCount = 0; + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + hsmartcard->RxXferCount = 0U; /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); @@ -2247,7 +2691,13 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /* At end of Rx process, restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hsmartcard->RxCpltCallback(hsmartcard); +#else + /* Call legacy weak Rx complete callback */ HAL_SMARTCARD_RxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } /** @@ -2258,26 +2708,32 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) { - SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent); + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); /* Stop SMARTCARD DMA Tx request if ongoing */ - if ( (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) - &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) ) + if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) + && (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))) { - hsmartcard->TxXferCount = 0; + hsmartcard->TxXferCount = 0U; SMARTCARD_EndTxTransfer(hsmartcard); } /* Stop SMARTCARD DMA Rx request if ongoing */ - if ( (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) - &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) ) + if ((hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) + && (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))) { - hsmartcard->RxXferCount = 0; + hsmartcard->RxXferCount = 0U; SMARTCARD_EndRxTransfer(hsmartcard); } hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA; +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } /** @@ -2288,11 +2744,17 @@ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) */ static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent); - hsmartcard->RxXferCount = 0; - hsmartcard->TxXferCount = 0; + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + hsmartcard->RxXferCount = 0U; + hsmartcard->TxXferCount = 0U; +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } /** @@ -2305,22 +2767,22 @@ static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma) */ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { - SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent); - + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + hsmartcard->hdmatx->XferAbortCallback = NULL; /* Check if an Abort process is still ongoing */ - if(hsmartcard->hdmarx != NULL) + if (hsmartcard->hdmarx != NULL) { - if(hsmartcard->hdmarx->XferAbortCallback != NULL) + if (hsmartcard->hdmarx->XferAbortCallback != NULL) { return; } } - + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - hsmartcard->TxXferCount = 0; - hsmartcard->RxXferCount = 0; + hsmartcard->TxXferCount = 0U; + hsmartcard->RxXferCount = 0U; /* Reset errorCode */ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; @@ -2332,8 +2794,13 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma) hsmartcard->gState = HAL_SMARTCARD_STATE_READY; hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - /* Call user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hsmartcard->AbortCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort complete callback */ HAL_SMARTCARD_AbortCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } @@ -2347,22 +2814,22 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma) */ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { - SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent); + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); hsmartcard->hdmarx->XferAbortCallback = NULL; /* Check if an Abort process is still ongoing */ - if(hsmartcard->hdmatx != NULL) + if (hsmartcard->hdmatx != NULL) { - if(hsmartcard->hdmatx->XferAbortCallback != NULL) + if (hsmartcard->hdmatx->XferAbortCallback != NULL) { return; } } /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - hsmartcard->TxXferCount = 0; - hsmartcard->RxXferCount = 0; + hsmartcard->TxXferCount = 0U; + hsmartcard->RxXferCount = 0U; /* Reset errorCode */ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; @@ -2374,8 +2841,13 @@ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma) hsmartcard->gState = HAL_SMARTCARD_STATE_READY; hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - /* Call user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hsmartcard->AbortCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort complete callback */ HAL_SMARTCARD_AbortCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } @@ -2389,9 +2861,9 @@ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma) */ static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { - SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent); + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); - hsmartcard->TxXferCount = 0; + hsmartcard->TxXferCount = 0U; /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF); @@ -2399,8 +2871,13 @@ static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) /* Restore hsmartcard->gState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - /* Call user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hsmartcard->AbortTransmitCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Transmit Complete Callback */ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } /** @@ -2413,9 +2890,9 @@ static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) */ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { - SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )(hdma->Parent); + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); - hsmartcard->RxXferCount = 0; + hsmartcard->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); @@ -2423,17 +2900,22 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - /* Call user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hsmartcard->AbortReceiveCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Receive Complete Callback */ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } /** - * @brief Send an amount of data in non-blocking mode. + * @brief Send an amount of data in non-blocking mode. * @note Function called under interruption only, once * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() * and when the FIFO mode is disabled. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard) @@ -2441,7 +2923,7 @@ static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard) /* Check that a Tx process is ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) { - if(hsmartcard->TxXferCount == 0) + if (hsmartcard->TxXferCount == 0U) { /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */ #if defined(USART_CR1_FIFOEN) @@ -2463,12 +2945,12 @@ static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard) #if defined(USART_CR1_FIFOEN) /** - * @brief Send an amount of data in non-blocking mode. + * @brief Send an amount of data in non-blocking mode. * @note Function called under interruption only, once * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() * and when the FIFO mode is enabled. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard) @@ -2478,13 +2960,13 @@ static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard) /* Check that a Tx process is ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) { - for(nb_tx_data = hsmartcard->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) - { - if(hsmartcard->TxXferCount == 0) + for (nb_tx_data = hsmartcard->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (hsmartcard->TxXferCount == 0U) { /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); - + /* Enable the SMARTCARD Transmit Complete Interrupt */ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); } @@ -2500,8 +2982,8 @@ static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief Wrap up transmission in non-blocking mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) @@ -2510,14 +2992,14 @@ static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) __HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); /* Check if a receive process is ongoing or not. If not disable ERR IT */ - if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) { /* Disable the SMARTCARD Error Interrupt: (Frame error) */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); } /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */ - if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) + if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) { /* Disable the Peripheral first to update modes */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); @@ -2532,16 +3014,22 @@ static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) /* Clear TxISR function pointer */ hsmartcard->TxISR = NULL; +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Tx complete callback */ + hsmartcard->TxCpltCallback(hsmartcard); +#else + /* Call legacy weak Tx complete callback */ HAL_SMARTCARD_TxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } /** - * @brief Receive an amount of data in non-blocking mode. + * @brief Receive an amount of data in non-blocking mode. * @note Function called under interruption only, once * interruptions have been enabled by HAL_SMARTCARD_Receive_IT() * and when the FIFO mode is disabled. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard) @@ -2550,31 +3038,37 @@ static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard) if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) { *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); - - if(--hsmartcard->RxXferCount == 0) + + if (--hsmartcard->RxXferCount == 0U) { #if defined(USART_CR1_FIFOEN) CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); #else CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE); #endif - + /* Check if a transmit process is ongoing or not. If not disable ERR IT */ - if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); } - + /* Disable the SMARTCARD Parity Error Interrupt */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); - + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - + /* Clear RxISR function pointer */ hsmartcard->RxISR = NULL; - + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hsmartcard->RxCpltCallback(hsmartcard); +#else + /* Call legacy weak Rx complete callback */ HAL_SMARTCARD_RxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } } else @@ -2586,60 +3080,66 @@ static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard) #if defined(USART_CR1_FIFOEN) /** - * @brief Receive an amount of data in non-blocking mode. + * @brief Receive an amount of data in non-blocking mode. * @note Function called under interruption only, once * interruptions have been enabled by HAL_SMARTCARD_Receive_IT() * and when the FIFO mode is enabled. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard) { uint8_t nb_rx_data; - + /* Check that a Rx process is ongoing */ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) { - for(nb_rx_data = hsmartcard->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) + for (nb_rx_data = hsmartcard->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) { *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); - - if(--hsmartcard->RxXferCount == 0) + + if (--hsmartcard->RxXferCount == 0U) { CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); - + /* Check if a transmit process is ongoing or not. If not disable ERR IT */ - if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); } - + /* Disable the SMARTCARD Parity Error Interrupt */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); - + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - + /* Clear RxISR function pointer */ hsmartcard->RxISR = NULL; - + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hsmartcard->RxCpltCallback(hsmartcard); +#else + /* Call legacy weak Rx complete callback */ HAL_SMARTCARD_RxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } } - - /* When remaining number of bytes to receive is less than the RX FIFO - threshold, next incoming frames are processed as if FIFO mode was + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ if (((hsmartcard->RxXferCount != 0U)) && (hsmartcard->RxXferCount < hsmartcard->NbRxDataToProcess)) { /* Disable the UART RXFT interrupt*/ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE); - + /* Update the RxISR function pointer */ hsmartcard->RxISR = SMARTCARD_RxISR; - + /* Enable the UART Data Register Not Empty interrupt */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard_ex.c index ce889ec0ac..31130df502 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard_ex.c @@ -20,7 +20,11 @@ then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut, auto-retry counter,...) in the hsmartcard AdvancedInit structure. + (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. + -@- When SMARTCARD operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be + configured prior starting RX/TX transfers. @endverbatim ****************************************************************************** @@ -68,6 +72,12 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +/* UART RX FIFO depth */ +#define RX_FIFO_DEPTH 8U + +/* UART TX FIFO depth */ +#define TX_FIFO_DEPTH 8U + /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -80,60 +90,7 @@ static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard); * @{ */ -/** @defgroup SMARTCARDEx_Exported_Functions_Group2 IO operation functions - * @brief Extended SMARTCARD Transmit/Receive functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of FIFO mode related callback functions. - - (#) TX/RX Fifos Callbacks: - (+) HAL_SMARTCARDEx_RxFifoFullCallback() - (+) HAL_SMARTCARDEx_TxFifoEmptyCallback() - -@endverbatim - * @{ - */ - -#if defined(USART_CR1_FIFOEN) -/** - * @brief SMARTCARD RX Fifo full callback. - * @param hsmartcard SMARTCARD handle. - * @retval None - */ -__weak void HAL_SMARTCARDEx_RxFifoFullCallback (SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmartcard); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMARTCARDEx_RxFifoFullCallback can be implemented in the user file. - */ -} - -/** - * @brief SMARTCARD TX Fifo empty callback. - * @param hsmartcard SMARTCARD handle. - * @retval None - */ -__weak void HAL_SMARTCARDEx_TxFifoEmptyCallback (SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmartcard); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMARTCARDEx_TxFifoEmptyCallback can be implemented in the user file. - */ -} -#endif - -/** - * @} - */ - -/** @defgroup SMARTCARDEx_Exported_Functions_Group3 Extended Peripheral Control functions +/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions * @brief Extended control functions * @verbatim @@ -146,10 +103,6 @@ __weak void HAL_SMARTCARDEx_TxFifoEmptyCallback (SMARTCARD_HandleTypeDef *hsmart (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature - (+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode - (+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode - (+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold - (+) HAL_SMARTCARDEx_SetRxFifoThreshold() API sets the RX FIFO threshold @endverbatim * @{ @@ -190,7 +143,7 @@ void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard) { - if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsmartcard); @@ -204,7 +157,7 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + return HAL_OK; } else @@ -222,7 +175,7 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard) { - if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsmartcard); @@ -236,7 +189,7 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + return HAL_OK; } else @@ -245,6 +198,83 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef } } +/** + * @} + */ + +/** @defgroup SMARTCARDEx_Exported_Functions_Group2 Extended Peripheral IO operation functions + * @brief SMARTCARD Transmit and Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of FIFO mode related callback functions. + + (#) TX/RX Fifos Callbacks: + (+) HAL_SMARTCARDEx_RxFifoFullCallback() + (+) HAL_SMARTCARDEx_TxFifoEmptyCallback() + + +@endverbatim + * @{ + */ + +#if defined(USART_CR1_FIFOEN) +/** + * @brief SMARTCARD RX Fifo full callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARDEx_RxFifoFullCallback can be implemented in the user file. + */ +} + +/** + * @brief SMARTCARD TX Fifo empty callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARDEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} +#endif + +/** + * @} + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group3 Extended Peripheral Peripheral Control functions + * @brief SMARTCARD control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SMARTCARD. + (+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode + (+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode + (+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold + (+) HAL_SMARTCARDEx_SetRxFifoThreshold() API sets the RX FIFO threshold +@endverbatim + * @{ + */ + #if defined(USART_CR1_FIFOEN) /** * @brief Enable the FIFO mode. @@ -253,37 +283,37 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef */ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard) { - uint32_t tmpcr1 = 0; + uint32_t tmpcr1 = 0U; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); /* Process Locked */ __HAL_LOCK(hsmartcard); - + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; - + /* Save actual SMARTCARD configuration */ tmpcr1 = READ_REG(hsmartcard->Instance->CR1); - + /* Disable SMARTCARD */ __HAL_SMARTCARD_DISABLE(hsmartcard); - + /* Enable FIFO mode */ SET_BIT(tmpcr1, USART_CR1_FIFOEN); hsmartcard->FifoMode = SMARTCARD_FIFOMODE_ENABLE; - + /* Restore SMARTCARD configuration */ WRITE_REG(hsmartcard->Instance->CR1, tmpcr1); - + /* Determine the number of data to process during RX/TX ISR execution */ SMARTCARDEx_SetNbDataToProcess(hsmartcard); hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + return HAL_OK; } @@ -294,34 +324,34 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmart */ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard) { - uint32_t tmpcr1 = 0; + uint32_t tmpcr1 = 0U; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); /* Process Locked */ __HAL_LOCK(hsmartcard); - + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; - + /* Save actual SMARTCARD configuration */ tmpcr1 = READ_REG(hsmartcard->Instance->CR1); - + /* Disable SMARTCARD */ __HAL_SMARTCARD_DISABLE(hsmartcard); - + /* Enable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); hsmartcard->FifoMode = SMARTCARD_FIFOMODE_DISABLE; - + /* Restore SMARTCARD configuration */ WRITE_REG(hsmartcard->Instance->CR1, tmpcr1); - + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + return HAL_OK; } @@ -340,37 +370,37 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmar */ HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold) { - uint32_t tmpcr1 = 0; - + uint32_t tmpcr1 = 0U; + /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); assert_param(IS_SMARTCARD_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(hsmartcard); - + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; - + /* Save actual SMARTCARD configuration */ tmpcr1 = READ_REG(hsmartcard->Instance->CR1); - + /* Disable SMARTCARD */ __HAL_SMARTCARD_DISABLE(hsmartcard); - + /* Update TX threshold configuration */ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG, Threshold); - + /* Determine the number of data to process during RX/TX ISR execution */ SMARTCARDEx_SetNbDataToProcess(hsmartcard); - + /* Restore SMARTCARD configuration */ MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1); - + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + return HAL_OK; } @@ -389,40 +419,41 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hs */ HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold) { - uint32_t tmpcr1 = 0; - + uint32_t tmpcr1 = 0U; + /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); assert_param(IS_SMARTCARD_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(hsmartcard); - + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; - + /* Save actual SMARTCARD configuration */ tmpcr1 = READ_REG(hsmartcard->Instance->CR1); - + /* Disable SMARTCARD */ __HAL_SMARTCARD_DISABLE(hsmartcard); - + /* Update RX threshold configuration */ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG, Threshold); - + /* Determine the number of data to process during RX/TX ISR execution */ SMARTCARDEx_SetNbDataToProcess(hsmartcard); - + /* Restore SMARTCARD configuration */ MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1); - + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + return HAL_OK; } #endif + /** * @} */ @@ -451,23 +482,24 @@ static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard) uint8_t tx_fifo_threshold; uint8_t numerator[] = {1, 1, 1, 3, 7, 1}; uint8_t denominator[] = {8, 4, 2, 4, 8, 1}; - + if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE) { - hsmartcard->NbTxDataToProcess = 1; - hsmartcard->NbRxDataToProcess = 1; + hsmartcard->NbTxDataToProcess = 1U; + hsmartcard->NbRxDataToProcess = 1U; } else { - rx_fifo_depth = 8; /* RX Fifo size */ - tx_fifo_depth = 8; /* TX Fifo size */ - rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); - tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); - hsmartcard->NbTxDataToProcess = (uint8_t)(tx_fifo_depth * numerator[tx_fifo_threshold])/denominator[tx_fifo_threshold]; - hsmartcard->NbRxDataToProcess = (uint8_t)(rx_fifo_depth * numerator[rx_fifo_threshold])/denominator[rx_fifo_threshold]; + rx_fifo_depth = RX_FIFO_DEPTH; + tx_fifo_depth = TX_FIFO_DEPTH; + rx_fifo_threshold = (READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); + tx_fifo_threshold = (READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); + hsmartcard->NbTxDataToProcess = (tx_fifo_depth * numerator[tx_fifo_threshold]) / denominator[tx_fifo_threshold]; + hsmartcard->NbRxDataToProcess = (rx_fifo_depth * numerator[rx_fifo_threshold]) / denominator[rx_fifo_threshold]; } } #endif + /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c index 3ec0d71e2b..2230912086 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c @@ -20,7 +20,7 @@ (#) Declare a SMBUS_HandleTypeDef handle structure, for example: SMBUS_HandleTypeDef hsmbus; - (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API: + (#)Initialize the SMBUS low level resources by implementing the @ref HAL_SMBUS_MspInit() API: (##) Enable the SMBUSx interface clock (##) SMBUS pins configuration (+++) Enable the clock for the SMBUS GPIOs @@ -33,64 +33,122 @@ Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode, Peripheral mode and Packet Error Check mode in the hsmbus Init structure. - (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API: + (#) Initialize the SMBUS registers by calling the @ref HAL_SMBUS_Init() API: (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customized HAL_SMBUS_MspInit(&hsmbus) API. + by calling the customized @ref HAL_SMBUS_MspInit(&hsmbus) API. - (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady() + (#) To check if target device is ready for communication, use the function @ref HAL_SMBUS_IsDeviceReady() (#) For SMBUS IO operations, only one mode of operations is available within this driver *** Interrupt mode IO operation *** =================================== [..] - (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Transmit_IT() - (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback() - (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Receive_IT() - (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback() - (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT() + (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Transmit_IT() + (++) At transmission end of transfer @ref HAL_SMBUS_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_SMBUS_MasterTxCpltCallback() + (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Receive_IT() + (++) At reception end of transfer @ref HAL_SMBUS_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_SMBUS_MasterRxCpltCallback() + (+) Abort a master/host SMBUS process communication with Interrupt using @ref HAL_SMBUS_Master_Abort_IT() (++) The associated previous transfer callback is called at the end of abort process - (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit - (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive + (++) mean @ref HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit + (++) mean @ref HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode - using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT() - (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can + using @ref HAL_SMBUS_EnableListen_IT() @ref HAL_SMBUS_DisableListen_IT() + (++) When address slave/device SMBUS match, @ref HAL_SMBUS_AddrCallback() is executed and user can add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read). - (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback() - (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Transmit_IT() - (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback() - (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Receive_IT() - (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback() - (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT() - (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can - add his own code by customization of function pointer HAL_SMBUS_ErrorCallback() - to check the Alert Error Code using function HAL_SMBUS_GetError() - (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError() - (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_SMBUS_ErrorCallback() - to check the Error Code using function HAL_SMBUS_GetError() + (++) At Listen mode end @ref HAL_SMBUS_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_SMBUS_ListenCpltCallback() + (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Transmit_IT() + (++) At transmission end of transfer @ref HAL_SMBUS_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_SMBUS_SlaveTxCpltCallback() + (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Receive_IT() + (++) At reception end of transfer @ref HAL_SMBUS_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_SMBUS_SlaveRxCpltCallback() + (+) Enable/Disable the SMBUS alert mode using @ref HAL_SMBUS_EnableAlert_IT() @ref HAL_SMBUS_DisableAlert_IT() + (++) When SMBUS Alert is generated @ref HAL_SMBUS_ErrorCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback() + to check the Alert Error Code using function @ref HAL_SMBUS_GetError() + (+) Get HAL state machine or error values using @ref HAL_SMBUS_GetState() or @ref HAL_SMBUS_GetError() + (+) In case of transfer Error, @ref HAL_SMBUS_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback() + to check the Error Code using function @ref HAL_SMBUS_GetError() *** SMBUS HAL driver macros list *** ================================== [..] Below the list of most used macros in SMBUS HAL driver. - (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral - (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral - (+) __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not - (+) __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag - (+) __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt - (+) __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt + (+) @ref __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral + (+) @ref __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral + (+) @ref __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not + (+) @ref __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag + (+) @ref __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt + (+) @ref __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt + + *** Callback registration *** + ============================================= + + The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback() + to register an interrupt callback. + + Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback. + + Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default + weak function. + @ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + + For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback. + + By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit() + or @ref HAL_SMBUS_Init() function. + + When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. [..] (@) You can refer to the SMBUS HAL driver header file for more useful macros - @endverbatim ****************************************************************************** * @attention @@ -163,8 +221,8 @@ */ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest); -static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest); +static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest); +static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest); static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus); static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus); @@ -255,8 +313,26 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /* Allocate lock resource and initialize it */ hsmbus->Lock = HAL_UNLOCKED; +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback; /* Legacy weak ErrorCallback */ + hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */ + + if (hsmbus->MspInitCallback == NULL) + { + hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hsmbus->MspInitCallback(hsmbus); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_SMBUS_MspInit(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } hsmbus->State = HAL_SMBUS_STATE_BUSY; @@ -347,8 +423,18 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) /* Disable the SMBUS Peripheral Clock */ __HAL_SMBUS_DISABLE(hsmbus); +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + if (hsmbus->MspDeInitCallback == NULL) + { + hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hsmbus->MspDeInitCallback(hsmbus); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_SMBUS_MspDeInit(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; hsmbus->PreviousState = HAL_SMBUS_STATE_RESET; @@ -490,6 +576,299 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin } } +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User SMBUS Callback + * To be used instead of the weak predefined callback + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID + * @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hsmbus); + + if (HAL_SMBUS_STATE_READY == hsmbus->State) + { + switch (CallbackID) + { + case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID : + hsmbus->MasterTxCpltCallback = pCallback; + break; + + case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID : + hsmbus->MasterRxCpltCallback = pCallback; + break; + + case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID : + hsmbus->SlaveTxCpltCallback = pCallback; + break; + + case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID : + hsmbus->SlaveRxCpltCallback = pCallback; + break; + + case HAL_SMBUS_LISTEN_COMPLETE_CB_ID : + hsmbus->ListenCpltCallback = pCallback; + break; + + case HAL_SMBUS_ERROR_CB_ID : + hsmbus->ErrorCallback = pCallback; + break; + + case HAL_SMBUS_MSPINIT_CB_ID : + hsmbus->MspInitCallback = pCallback; + break; + + case HAL_SMBUS_MSPDEINIT_CB_ID : + hsmbus->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SMBUS_STATE_RESET == hsmbus->State) + { + switch (CallbackID) + { + case HAL_SMBUS_MSPINIT_CB_ID : + hsmbus->MspInitCallback = pCallback; + break; + + case HAL_SMBUS_MSPDEINIT_CB_ID : + hsmbus->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsmbus); + return status; +} + +/** + * @brief Unregister an SMBUS Callback + * SMBUS callback is redirected to the weak predefined callback + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID + * @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hsmbus); + + if (HAL_SMBUS_STATE_READY == hsmbus->State) + { + switch (CallbackID) + { + case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID : + hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID : + hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID : + hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID : + hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_SMBUS_LISTEN_COMPLETE_CB_ID : + hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_SMBUS_ERROR_CB_ID : + hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_SMBUS_MSPINIT_CB_ID : + hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SMBUS_MSPDEINIT_CB_ID : + hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SMBUS_STATE_RESET == hsmbus->State) + { + switch (CallbackID) + { + case HAL_SMBUS_MSPINIT_CB_ID : + hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SMBUS_MSPDEINIT_CB_ID : + hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsmbus); + return status; +} + +/** + * @brief Register the Slave Address Match SMBUS Callback + * To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hsmbus); + + if (HAL_SMBUS_STATE_READY == hsmbus->State) + { + hsmbus->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsmbus); + return status; +} + +/** + * @brief UnRegister the Slave Address Match SMBUS Callback + * Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hsmbus); + + if (HAL_SMBUS_STATE_READY == hsmbus->State) + { + hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsmbus); + return status; +} + +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + /** * @} */ @@ -542,7 +921,7 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition @@ -583,7 +962,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* Send Slave Address */ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount)) + if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); } @@ -635,7 +1014,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition @@ -677,7 +1056,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 /* Send Slave Address */ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount)) + if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); } @@ -722,7 +1101,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @retval HAL status */ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress) @@ -768,6 +1147,10 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_ { SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); } + else + { + /* Nothing to do */ + } return HAL_OK; } @@ -791,11 +1174,12 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { if ((pData == NULL) || (Size == 0U)) { - return HAL_ERROR; + hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM; + return HAL_ERROR; } /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ @@ -804,7 +1188,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Process Locked */ __HAL_LOCK(hsmbus); - hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX; + hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_TX | HAL_SMBUS_STATE_LISTEN); hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; /* Set SBC bit to manage Acknowledge at each bit */ @@ -831,7 +1215,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 } /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount)) + if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); } @@ -866,7 +1250,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 } else { - return HAL_ERROR; + return HAL_BUSY; } } @@ -884,11 +1268,12 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { if ((pData == NULL) || (Size == 0U)) { - return HAL_ERROR; + hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM; + return HAL_ERROR; } /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ @@ -897,7 +1282,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* Process Locked */ __HAL_LOCK(hsmbus); - hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX; + hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_RX | HAL_SMBUS_STATE_LISTEN); hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; /* Set SBC bit to manage Acknowledge at each bit */ @@ -920,7 +1305,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */ /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */ /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ - if ((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET))) + if (((SMBUS_GET_PEC_MODE(hsmbus) != RESET) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U)) { SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } @@ -946,7 +1331,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ } else { - return HAL_ERROR; + return HAL_BUSY; } } @@ -1031,14 +1416,14 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param Trials Number of trials * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) { - uint32_t tickstart = 0U; + uint32_t tickstart; __IO uint32_t SMBUS_Trials = 0U; @@ -1067,14 +1452,17 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t { if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Device is ready */ hsmbus->State = HAL_SMBUS_STATE_READY; + /* Update SMBUS error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT; + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - return HAL_TIMEOUT; + return HAL_ERROR; } } } @@ -1085,7 +1473,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Wait until STOPF flag is reset */ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } /* Clear STOP Flag */ @@ -1104,7 +1492,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Wait until STOPF flag is reset */ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } /* Clear NACK Flag */ @@ -1123,7 +1511,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Wait until STOPF flag is reset */ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } /* Clear STOP Flag */ @@ -1134,10 +1522,13 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t hsmbus->State = HAL_SMBUS_STATE_READY; + /* Update SMBUS error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT; + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - return HAL_TIMEOUT; + return HAL_ERROR; } else { @@ -1160,11 +1551,9 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t */ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) { - uint32_t tmpisrvalue = 0U; - /* Use a local variable to store the current ISR flags */ /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */ - tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus); + uint32_t tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus); /* SMBUS in mode Transmitter ---------------------------------------------------*/ if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET)) @@ -1172,12 +1561,16 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) { - SMBUS_Slave_ISR(hsmbus); + (void)SMBUS_Slave_ISR(hsmbus); } /* Master mode selected */ else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX) { - SMBUS_Master_ISR(hsmbus); + (void)SMBUS_Master_ISR(hsmbus); + } + else + { + /* Nothing to do */ } } @@ -1187,12 +1580,16 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) { - SMBUS_Slave_ISR(hsmbus); + (void)SMBUS_Slave_ISR(hsmbus); } /* Master mode selected */ else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX) { - SMBUS_Master_ISR(hsmbus); + (void)SMBUS_Master_ISR(hsmbus); + } + else + { + /* Nothing to do */ } } @@ -1200,9 +1597,9 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET))) { - if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { - SMBUS_Slave_ISR(hsmbus); + (void)SMBUS_Slave_ISR(hsmbus); } } } @@ -1414,7 +1811,11 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) __HAL_UNLOCK(hsmbus); /* Call the Error callback to inform upper layer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->ErrorCallback(hsmbus); +#else HAL_SMBUS_ErrorCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) { @@ -1446,7 +1847,12 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* REenable the selected SMBUS peripheral */ __HAL_SMBUS_ENABLE(hsmbus); + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterTxCpltCallback(hsmbus); +#else HAL_SMBUS_MasterTxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { @@ -1478,7 +1884,16 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterRxCpltCallback(hsmbus); +#else HAL_SMBUS_MasterRxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ } } else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) @@ -1497,7 +1912,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) } else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET) { - if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U)) + if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U)) { DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD); @@ -1535,7 +1950,12 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterTxCpltCallback(hsmbus); +#else HAL_SMBUS_MasterTxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { @@ -1546,10 +1966,23 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterRxCpltCallback(hsmbus); +#else HAL_SMBUS_MasterRxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ } } } + else + { + /* Nothing to do */ + } } else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET) { @@ -1578,7 +2011,12 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterTxCpltCallback(hsmbus); +#else HAL_SMBUS_MasterTxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { @@ -1589,11 +2027,28 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterRxCpltCallback(hsmbus); +#else HAL_SMBUS_MasterRxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ } } + else + { + /* Nothing to do */ + } } } + else + { + /* Nothing to do */ + } /* Process Unlocked */ __HAL_UNLOCK(hsmbus); @@ -1608,8 +2063,8 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) */ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) { - uint8_t TransferDirection = 0U; - uint16_t SlaveAddrCode = 0U; + uint8_t TransferDirection; + uint16_t SlaveAddrCode; /* Process Locked */ __HAL_LOCK(hsmbus); @@ -1650,7 +2105,11 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) __HAL_UNLOCK(hsmbus); /* Call the Error callback to inform upper layer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->ErrorCallback(hsmbus); +#else HAL_SMBUS_ErrorCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } } else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET) @@ -1666,7 +2125,11 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) __HAL_UNLOCK(hsmbus); /* Call Slave Addr callback */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); +#else HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } else if ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)) { @@ -1697,8 +2160,12 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - /* Call the Rx complete callback to inform upper layer of the end of receive process */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->SlaveRxCpltCallback(hsmbus); +#else HAL_SMBUS_SlaveRxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } else { @@ -1711,7 +2178,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) } else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) { - if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U)) + if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U)) { if (hsmbus->XferCount > MAX_NBYTE_SIZE) { @@ -1732,6 +2199,10 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) } } } + else + { + /* Nothing to do */ + } } else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) { @@ -1758,10 +2229,18 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - /* Call the Tx complete callback to inform upper layer of the end of transmit process */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->SlaveTxCpltCallback(hsmbus); +#else HAL_SMBUS_SlaveTxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } } + else + { + /* Nothing to do */ + } /* Check if STOPF is set */ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) @@ -1807,7 +2286,11 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) __HAL_UNLOCK(hsmbus); /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->ListenCpltCallback(hsmbus); +#else HAL_SMBUS_ListenCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } } @@ -1823,7 +2306,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) +static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) { uint32_t tmpisr = 0U; @@ -1855,8 +2338,6 @@ static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t /* to avoid the risk of SMBUS interrupt handle execution before */ /* all interrupts requested done */ __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr); - - return HAL_OK; } /** * @brief Manage the disabling of Interrupts. @@ -1865,11 +2346,11 @@ static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) +static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) { uint32_t tmpisr = 0U; - if (((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY)) + if ((hsmbus->State == HAL_SMBUS_STATE_READY) && ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; @@ -1929,8 +2410,6 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t /* to avoid a breaking situation like at "t" time */ /* all disable interrupts request are not done */ __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr); - - return HAL_OK; } /** @@ -2014,7 +2493,11 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* Call the Error callback to inform upper layer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->ErrorCallback(hsmbus); +#else HAL_SMBUS_ErrorCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } } @@ -2032,46 +2515,27 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu uint32_t tickstart = HAL_GetTick(); /* Wait until flag is set */ - if (Status == RESET) + while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == Status) { - while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET) + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - hsmbus->PreviousState = hsmbus->State; - hsmbus->State = HAL_SMBUS_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; - return HAL_TIMEOUT; - } - } - } - } - else - { - while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - hsmbus->PreviousState = hsmbus->State; - hsmbus->State = HAL_SMBUS_STATE_READY; + /* Update SMBUS error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); - return HAL_TIMEOUT; - } + return HAL_ERROR; } } } + return HAL_OK; } @@ -2144,6 +2608,10 @@ static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) { hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC; } + else + { + /* Nothing to do */ + } } /** * @} diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c index d147f18e26..f33d1c318a 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c @@ -57,6 +57,65 @@ does not initiate a new transfer the following procedure has to be respected: (##) HAL_SPI_DeInit() (##) HAL_SPI_Init() + [..] + Callback registration: + + (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback. + + Function HAL_SPI_RegisterCallback() allows to register following callbacks: + (+) TxCpltCallback : SPI Tx Completed callback + (+) RxCpltCallback : SPI Rx Completed callback + (+) TxRxCpltCallback : SPI TxRx Completed callback + (+) TxHalfCpltCallback : SPI Tx Half Completed callback + (+) RxHalfCpltCallback : SPI Rx Half Completed callback + (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (+) ErrorCallback : SPI Error callback + (+) AbortCpltCallback : SPI Abort callback + (+) MspInitCallback : SPI Msp Init callback + (+) MspDeInitCallback : SPI Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + + (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default + weak function. + HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxCpltCallback : SPI Tx Completed callback + (+) RxCpltCallback : SPI Rx Completed callback + (+) TxRxCpltCallback : SPI TxRx Completed callback + (+) TxHalfCpltCallback : SPI Tx Half Completed callback + (+) RxHalfCpltCallback : SPI Rx Half Completed callback + (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (+) ErrorCallback : SPI Error callback + (+) AbortCpltCallback : SPI Abort callback + (+) MspInitCallback : SPI Msp Init callback + (+) MspDeInitCallback : SPI Msp DeInit callback + + By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() + or HAL_SPI_Init() function. + + When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + [..] Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes, the following table resume the max SPI frequency reached with data size 8bits/16bits, @@ -308,8 +367,28 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /* Allocate lock resource and initialize it */ hspi->Lock = HAL_UNLOCKED; +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + /* Init the SPI Callback settings */ + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + + if (hspi->MspInitCallback == NULL) + { + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_SPI_MspInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } hspi->State = HAL_SPI_STATE_BUSY; @@ -408,8 +487,18 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) /* Disable the SPI Peripheral Clock */ __HAL_SPI_DISABLE(hspi); +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + if (hspi->MspDeInitCallback == NULL) + { + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + hspi->MspDeInitCallback(hspi); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ HAL_SPI_MspDeInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->State = HAL_SPI_STATE_RESET; @@ -452,6 +541,221 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) */ } +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User SPI Callback + * To be used instead of the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be registered + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hspi); + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = pCallback; + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = pCallback; + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = pCallback; + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hspi); + return status; +} + +/** + * @brief Unregister an SPI Callback + * SPI callback is redirected to the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be unregistered + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hspi); + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hspi); + return status; +} +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ /** * @} */ @@ -2240,7 +2544,11 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) hspi->State = HAL_SPI_STATE_READY; /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } return errorcode; @@ -2406,7 +2714,11 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) else { /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } } return; @@ -2639,11 +2951,21 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ return; } } + /* Call user Tx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxCpltCallback(hspi); +#else HAL_SPI_TxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } /** @@ -2730,11 +3052,21 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ return; } } + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } /** @@ -2815,11 +3147,21 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ return; } } + /* Call user TxRx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxCpltCallback(hspi); +#else HAL_SPI_TxRxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } /** @@ -2832,7 +3174,12 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Call user Tx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxHalfCpltCallback(hspi); +#else HAL_SPI_TxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } /** @@ -2845,7 +3192,12 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Call user Rx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxHalfCpltCallback(hspi); +#else HAL_SPI_RxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } /** @@ -2858,7 +3210,12 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Call user TxRx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxHalfCpltCallback(hspi); +#else HAL_SPI_TxRxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } /** @@ -2876,7 +3233,12 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); hspi->State = HAL_SPI_STATE_READY; + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } /** @@ -2891,7 +3253,12 @@ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) hspi->RxXferCount = 0U; hspi->TxXferCount = 0U; + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } /** @@ -2953,7 +3320,11 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) hspi->State = HAL_SPI_STATE_READY; /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } /** @@ -3016,7 +3387,11 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) hspi->State = HAL_SPI_STATE_READY; /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } /** @@ -3619,7 +3994,12 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) hspi->State = HAL_SPI_STATE_READY; SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } else { @@ -3629,18 +4009,33 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) if (hspi->State == HAL_SPI_STATE_BUSY_RX) { hspi->State = HAL_SPI_STATE_READY; + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } else { hspi->State = HAL_SPI_STATE_READY; + /* Call user TxRx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxCpltCallback(hspi); +#else HAL_SPI_TxRxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } } else { hspi->State = HAL_SPI_STATE_READY; + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } #if (USE_SPI_CRC != 0U) } @@ -3671,18 +4066,33 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } else { #endif /* USE_SPI_CRC */ if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) { + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } else { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } #if (USE_SPI_CRC != 0U) } @@ -3720,11 +4130,21 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) hspi->State = HAL_SPI_STATE_READY; if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } else { + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxCpltCallback(hspi); +#else HAL_SPI_TxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c index a9fe491bcc..c2e70c373a 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c @@ -92,9 +92,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(FMC_BANK1) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -103,9 +101,10 @@ #ifdef HAL_SRAM_MODULE_ENABLED /** @defgroup SRAM SRAM - * @brief SRAM HAL module driver. + * @brief SRAM driver modules * @{ */ + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -132,11 +131,11 @@ */ /** - * @brief Perform the SRAM device initialization sequence. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @brief Perform the SRAM device initialization sequence + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param Timing: Pointer to SRAM control timing structure - * @param ExtTiming: Pointer to SRAM extended mode timing structure + * @param Timing Pointer to SRAM control timing structure + * @param ExtTiming Pointer to SRAM extended mode timing structure * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) @@ -151,7 +150,6 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp { /* Allocate lock resource and initialize it */ hsram->Lock = HAL_UNLOCKED; - /* Initialize the low level hardware (MSP) */ HAL_SRAM_MspInit(hsram); } @@ -173,7 +171,7 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp /** * @brief Perform the SRAM device de-initialization sequence. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval HAL status */ @@ -195,7 +193,7 @@ HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) /** * @brief Initialize the SRAM MSP. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval None */ @@ -211,7 +209,7 @@ __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) /** * @brief DeInitialize the SRAM MSP. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval None */ @@ -227,7 +225,7 @@ __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) /** * @brief DMA transfer complete callback. - * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains + * @param hdma pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval None */ @@ -243,7 +241,7 @@ __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) /** * @brief DMA transfer complete error callback. - * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains + * @param hdma pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval None */ @@ -277,11 +275,11 @@ __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) /** * @brief Read 8-bit buffer from SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) @@ -313,11 +311,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress /** * @brief Write 8-bit buffer to SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) @@ -355,11 +353,11 @@ HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres /** * @brief Read 16-bit buffer from SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) @@ -391,11 +389,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres /** * @brief Write 16-bit buffer to SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) @@ -433,11 +431,11 @@ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre /** * @brief Read 32-bit buffer from SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) @@ -467,11 +465,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres /** * @brief Write 32-bit buffer to SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) @@ -507,11 +505,11 @@ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre /** * @brief Read a Word data buffer from the SRAM memory using DMA transfer. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) @@ -540,11 +538,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddres /** * @brief Write a Word data buffer to SRAM memory using DMA transfer. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) @@ -598,7 +596,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre /** * @brief Enable dynamically SRAM write operation. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval HAL status */ @@ -621,7 +619,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) /** * @brief Disable dynamically SRAM write operation. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval HAL status */ @@ -665,8 +663,8 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) */ /** - * @brief Return the SRAM controller handle state. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @brief Return the SRAM controller state + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval HAL state */ @@ -683,17 +681,17 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) /** * @} */ + /** * @} */ + #endif /* HAL_SRAM_MODULE_ENABLED */ /** * @} */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* FMC_BANK1 */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_swpmi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_swpmi.c index 88b2286dc9..46e304b145 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_swpmi.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_swpmi.c @@ -42,7 +42,115 @@ (#) Program the Bite Rate, Tx Buffering mode, Rx Buffering mode in the Init structure. (#) Enable the SWPMI peripheral by calling the HAL_SWPMI_Init() function. - + + [..] + Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_SWPMI_Transmit() + (+) Receive an amount of data in blocking mode using HAL_SWPMI_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non-blocking mode using HAL_SWPMI_Transmit_IT() + (+) At transmission end of transfer HAL_SWPMI_TxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SWPMI_TxCpltCallback() + (+) Receive an amount of data in non-blocking mode using HAL_SWPMI_Receive_IT() + (+) At reception end of transfer HAL_SWPMI_RxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SWPMI_RxCpltCallback() + (+) In case of flag error, HAL_SWPMI_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SWPMI_ErrorCallback() + + *** DMA mode IO operation *** + ============================= + [..] + (+) Send an amount of data in non-blocking mode (DMA) using HAL_SWPMI_Transmit_DMA() + (+) At transmission end of transfer HAL_SWPMI_TxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SWPMI_TxCpltCallback() + (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SWPMI_Receive_DMA() + (+) At reception end of transfer HAL_SWPMI_RxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SWPMI_RxCpltCallback() + (+) In case of flag error, HAL_SWPMI_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SWPMI_ErrorCallback() + (+) Stop the DMA Transfer using HAL_SWPMI_DMAStop() + + *** SWPMI HAL driver additional function list *** + =============================================== + [..] + Below the list the others API available SWPMI HAL driver : + + (+) HAL_SWPMI_EnableLoopback(): Enable the loopback mode for test purpose only + (+) HAL_SWPMI_DisableLoopback(): Disable the loopback mode + + *** SWPMI HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in SWPMI HAL driver : + + (+) __HAL_SWPMI_ENABLE(): Enable the SWPMI peripheral + (+) __HAL_SWPMI_DISABLE(): Disable the SWPMI peripheral + (+) __HAL_SWPMI_ENABLE_IT(): Enable the specified SWPMI interrupts + (+) __HAL_SWPMI_DISABLE_IT(): Disable the specified SWPMI interrupts + (+) __HAL_SWPMI_GET_IT_SOURCE(): Check if the specified SWPMI interrupt source is + enabled or disabled + (+) __HAL_SWPMI_GET_FLAG(): Check whether the specified SWPMI flag is set or not + + *** Callback registration *** + ============================= + [..] + The compilation define USE_HAL_SWPMI_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + [..] + Use function HAL_SWPMI_RegisterCallback() to register a user callback. It allows + to register the following callbacks: + (+) RxCpltCallback : SWPMI receive complete. + (+) RxHalfCpltCallback : SWPMI receive half complete. + (+) TxCpltCallback : SWPMI transmit complete. + (+) TxHalfCpltCallback : SWPMI transmit half complete. + (+) ErrorCallback : SWPMI error. + (+) MspInitCallback : SWPMI MspInit. + (+) MspDeInitCallback : SWPMI MspDeInit. + [..] + This function takes as parameters the HAL peripheral handle, the callback ID + and a pointer to the user callback function. + [..] + Use function HAL_SWPMI_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + HAL_SWPMI_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the callback ID. + This function allows to reset following callbacks: + (+) RxCpltCallback : SWPMI receive complete. + (+) RxHalfCpltCallback : SWPMI receive half complete. + (+) TxCpltCallback : SWPMI transmit complete. + (+) TxHalfCpltCallback : SWPMI transmit half complete. + (+) ErrorCallback : SWPMI error. + (+) MspInitCallback : SWPMI MspInit. + (+) MspDeInitCallback : SWPMI MspDeInit. + [..] + By default, after the HAL_SWPMI_Init and if the state is HAL_SWPMI_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions: + examples HAL_SWPMI_RxCpltCallback(), HAL_SWPMI_ErrorCallback(). + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the HAL_SWPMI_Init + and HAL_SWPMI_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SWPMI_Init and HAL_SWPMI_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + [..] + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_SWPMI_RegisterCallback before calling @ref HAL_SWPMI_DeInit + or HAL_SWPMI_Init function. + [..] + When the compilation define USE_HAL_SWPMI_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + @endverbatim ****************************************************************************** * @attention @@ -77,14 +185,12 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" -#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) - /** @addtogroup STM32L4xx_HAL_Driver * @{ */ +#if defined(SWPMI1) + /** @defgroup SWPMI SWPMI * @brief HAL SWPMI module driver * @{ @@ -97,7 +203,7 @@ /** @addtogroup SWPMI_Private_Constants SWPMI Private Constants * @{ */ -#define SWPMI_TIMEOUT_VALUE ((uint32_t) 22000) +#define SWPMI_TIMEOUT_VALUE 22000U /* End of transmission timeout */ /** * @} @@ -142,7 +248,7 @@ static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hs /** * @brief Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval HAL status */ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi) @@ -167,9 +273,25 @@ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi) { /* Allocate lock resource and initialize it */ hswpmi->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + /* Reset callback pointers to the weak predefined callbacks */ + hswpmi->RxCpltCallback = HAL_SWPMI_RxCpltCallback; + hswpmi->RxHalfCpltCallback = HAL_SWPMI_RxHalfCpltCallback; + hswpmi->TxCpltCallback = HAL_SWPMI_TxCpltCallback; + hswpmi->TxHalfCpltCallback = HAL_SWPMI_TxHalfCpltCallback; + hswpmi->ErrorCallback = HAL_SWPMI_ErrorCallback; + + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + if(hswpmi->MspInitCallback == NULL) + { + hswpmi->MspInitCallback = HAL_SWPMI_MspInit; + } + hswpmi->MspInitCallback(hswpmi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_SWPMI_MspInit(hswpmi); +#endif } hswpmi->State = HAL_SWPMI_STATE_BUSY; @@ -207,7 +329,7 @@ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi) hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE; hswpmi->State = HAL_SWPMI_STATE_READY; - /* Enable SWPMI peripheral if not */ + /* Enable SWPMI peripheral */ SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT); } @@ -216,7 +338,7 @@ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi) /** * @brief De-initialize the SWPMI peripheral. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval HAL status */ HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi) @@ -238,11 +360,22 @@ HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi) /* Disable SWPMI interface */ CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT); - /* DeInit the low level hardware */ + /* Disable Loopback mode */ + CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK); + + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + if(hswpmi->MspDeInitCallback == NULL) + { + hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit; + } + hswpmi->MspDeInitCallback(hswpmi); +#else HAL_SWPMI_MspDeInit(hswpmi); +#endif hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE; - hswpmi->State = HAL_SWPMI_STATE_RESET; /* Release Lock */ @@ -254,7 +387,7 @@ HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi) /** * @brief Initialize the SWPMI MSP. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval None */ __weak void HAL_SWPMI_MspInit(SWPMI_HandleTypeDef *hswpmi) @@ -269,7 +402,7 @@ __weak void HAL_SWPMI_MspInit(SWPMI_HandleTypeDef *hswpmi) /** * @brief DeInitialize the SWPMI MSP. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval None */ __weak void HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi) @@ -282,6 +415,182 @@ __weak void HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi) */ } +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) +/** + * @brief Register a user SWPMI callback + * to be used instead of the weak predefined callback. + * @param hswpmi SWPMI handle. + * @param CallbackID ID of the callback to be registered. + * This parameter can be one of the following values: + * @arg @ref HAL_SWPMI_RX_COMPLETE_CB_ID receive complete callback ID. + * @arg @ref HAL_SWPMI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID. + * @arg @ref HAL_SWPMI_TX_COMPLETE_CB_ID transmit complete callback ID. + * @arg @ref HAL_SWPMI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID. + * @arg @ref HAL_SWPMI_ERROR_CB_ID error callback ID. + * @arg @ref HAL_SWPMI_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_SWPMI_MSPDEINIT_CB_ID MSP de-init callback ID. + * @param pCallback pointer to the callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef *hswpmi, + HAL_SWPMI_CallbackIDTypeDef CallbackID, + pSWPMI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* update the error code */ + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + else + { + if(hswpmi->State == HAL_SWPMI_STATE_READY) + { + switch (CallbackID) + { + case HAL_SWPMI_RX_COMPLETE_CB_ID : + hswpmi->RxCpltCallback = pCallback; + break; + case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID : + hswpmi->RxHalfCpltCallback = pCallback; + break; + case HAL_SWPMI_TX_COMPLETE_CB_ID : + hswpmi->TxCpltCallback = pCallback; + break; + case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID : + hswpmi->TxHalfCpltCallback = pCallback; + break; + case HAL_SWPMI_ERROR_CB_ID : + hswpmi->ErrorCallback = pCallback; + break; + case HAL_SWPMI_MSPINIT_CB_ID : + hswpmi->MspInitCallback = pCallback; + break; + case HAL_SWPMI_MSPDEINIT_CB_ID : + hswpmi->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(hswpmi->State == HAL_SWPMI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SWPMI_MSPINIT_CB_ID : + hswpmi->MspInitCallback = pCallback; + break; + case HAL_SWPMI_MSPDEINIT_CB_ID : + hswpmi->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief Unregister a user SWPMI callback. + * SWPMI callback is redirected to the weak predefined callback. + * @param hswpmi SWPMI handle. + * @param CallbackID ID of the callback to be unregistered. + * This parameter can be one of the following values: + * @arg @ref HAL_SWPMI_RX_COMPLETE_CB_ID receive complete callback ID. + * @arg @ref HAL_SWPMI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID. + * @arg @ref HAL_SWPMI_TX_COMPLETE_CB_ID transmit complete callback ID. + * @arg @ref HAL_SWPMI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID. + * @arg @ref HAL_SWPMI_ERROR_CB_ID error callback ID. + * @arg @ref HAL_SWPMI_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_SWPMI_MSPDEINIT_CB_ID MSP de-init callback ID. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback(SWPMI_HandleTypeDef *hswpmi, + HAL_SWPMI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(hswpmi->State == HAL_SWPMI_STATE_READY) + { + switch (CallbackID) + { + case HAL_SWPMI_RX_COMPLETE_CB_ID : + hswpmi->RxCpltCallback = HAL_SWPMI_RxCpltCallback; + break; + case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID : + hswpmi->RxHalfCpltCallback = HAL_SWPMI_RxHalfCpltCallback; + break; + case HAL_SWPMI_TX_COMPLETE_CB_ID : + hswpmi->TxCpltCallback = HAL_SWPMI_TxCpltCallback; + break; + case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID : + hswpmi->TxHalfCpltCallback = HAL_SWPMI_TxHalfCpltCallback; + break; + case HAL_SWPMI_ERROR_CB_ID : + hswpmi->ErrorCallback = HAL_SWPMI_ErrorCallback; + break; + case HAL_SWPMI_MSPINIT_CB_ID : + hswpmi->MspInitCallback = HAL_SWPMI_MspInit; + break; + case HAL_SWPMI_MSPDEINIT_CB_ID : + hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit; + break; + default : + /* update the error code */ + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(hswpmi->State == HAL_SWPMI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SWPMI_MSPINIT_CB_ID : + hswpmi->MspInitCallback = HAL_SWPMI_MspInit; + break; + case HAL_SWPMI_MSPDEINIT_CB_ID : + hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit; + break; + default : + /* update the error code */ + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + return status; +} +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ + /** * @} */ @@ -332,22 +641,22 @@ __weak void HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi) (++) HAL_SWPMI_RxCpltCallback() (++) HAL_SWPMI_ErrorCallback() - (#) The capability to launch the above IO operations in loopback mode for - user application verification: + (#) The capability to launch the above IO operations in loopback mode for + user application verification: (++) HAL_SWPMI_EnableLoopback() (++) HAL_SWPMI_DisableLoopback() - + @endverbatim * @{ */ /** * @brief Transmit an amount of data in blocking mode. - * @param hswpmi: pointer to a SWPMI_HandleTypeDef structure that contains + * @param hswpmi pointer to a SWPMI_HandleTypeDef structure that contains * the configuration information for SWPMI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pData, uint16_t Size, uint32_t Timeout) @@ -410,6 +719,9 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pDat /* Wait on TXBEF flag to be able to start a second transfer */ if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, Timeout) != HAL_OK) { + /* Timeout occurred */ + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_TXBEF_TIMEOUT; + status = HAL_TIMEOUT; } @@ -444,11 +756,11 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pDat /** * @brief Receive an amount of data in blocking mode. - * @param hswpmi: pointer to a SWPMI_HandleTypeDef structure that contains + * @param hswpmi pointer to a SWPMI_HandleTypeDef structure that contains * the configuration information for SWPMI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout) @@ -504,7 +816,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData } } } while(Size != 0); - + if(status == HAL_OK) { if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXBFF)) @@ -542,10 +854,10 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData /** * @brief Transmit an amount of data in non-blocking mode with interrupt. - * @param hswpmi: pointer to a SWPMI_HandleTypeDef structure that contains + * @param hswpmi pointer to a SWPMI_HandleTypeDef structure that contains * the configuration information for SWPMI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size) @@ -597,7 +909,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *p else { status = HAL_BUSY; - + /* Process Unlocked */ __HAL_UNLOCK(hswpmi); } @@ -607,10 +919,10 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *p } /** - * @brief Receive an amount of data in non-blocking mode with interrupt. - * @param hswpmi: SWPMI handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be received + * @brief Receive an amount of data in non-blocking mode with interrupt. + * @param hswpmi SWPMI handle + * @param pData Pointer to data buffer + * @param Size Amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size) @@ -658,7 +970,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pD else { status = HAL_BUSY; - + /* Process Unlocked */ __HAL_UNLOCK(hswpmi); } @@ -668,10 +980,10 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pD } /** - * @brief Transmit an amount of data in non-blocking mode with DMA interrupt. - * @param hswpmi: SWPMI handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @brief Transmit an amount of data in non-blocking mode with DMA interrupt. + * @param hswpmi SWPMI handle + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size) @@ -717,7 +1029,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t * /* Set the DMA error callback */ hswpmi->hdmatx->XferErrorCallback = SWPMI_DMAError; - /* Enable the SWPMI transmit DMA Channel */ + /* Enable the SWPMI transmit DMA channel */ HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, (uint32_t)&hswpmi->Instance->TDR, Size); /* Process Unlocked */ @@ -733,7 +1045,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t * else { status = HAL_BUSY; - + /* Process Unlocked */ __HAL_UNLOCK(hswpmi); } @@ -743,10 +1055,10 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t * } /** - * @brief Receive an amount of data in non-blocking mode with DMA interrupt. - * @param hswpmi: SWPMI handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be received + * @brief Receive an amount of data in non-blocking mode with DMA interrupt. + * @param hswpmi SWPMI handle + * @param pData Pointer to data buffer + * @param Size Amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size) @@ -818,7 +1130,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *p /** * @brief Stop all DMA transfers. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval HAL_OK */ HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi) @@ -854,7 +1166,7 @@ HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi) /** * @brief Enable the Loopback mode. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @note Loopback mode is to be used only for test purposes * @retval HAL_OK / HAL_BUSY */ @@ -865,16 +1177,14 @@ HAL_StatusTypeDef HAL_SWPMI_EnableLoopback(SWPMI_HandleTypeDef *hswpmi) /* Process Locked */ __HAL_LOCK(hswpmi); - /* Check SWPMI not enabled */ - if(READ_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT) != RESET) - { - status = HAL_BUSY; - } - else - { - /* Set Loopback */ - SET_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK); - } + /* Make sure the SWPMI interface is not enabled to set the loopback mode */ + CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT); + + /* Set Loopback */ + SET_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK); + + /* Enable SWPMI interface in loopback mode */ + SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT); /* Process Unlocked */ __HAL_UNLOCK(hswpmi); @@ -884,7 +1194,7 @@ HAL_StatusTypeDef HAL_SWPMI_EnableLoopback(SWPMI_HandleTypeDef *hswpmi) /** * @brief Disable the Loopback mode. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @note Loopback mode is to be used only for test purposes * @retval HAL_OK / HAL_BUSY */ @@ -895,16 +1205,14 @@ HAL_StatusTypeDef HAL_SWPMI_DisableLoopback(SWPMI_HandleTypeDef *hswpmi) /* Process Locked */ __HAL_LOCK(hswpmi); - /* Check SWPMI not enabled */ - if(READ_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT) != RESET) - { - status = HAL_BUSY; - } - else - { - /* Reset Loopback */ - CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK); - } + /* Make sure the SWPMI interface is not enabled to reset the loopback mode */ + CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT); + + /* Reset Loopback */ + CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK); + + /* Re-enable SWPMI interface in normal mode */ + SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT); /* Process Unlocked */ __HAL_UNLOCK(hswpmi); @@ -919,11 +1227,11 @@ HAL_StatusTypeDef HAL_SWPMI_DisableLoopback(SWPMI_HandleTypeDef *hswpmi) /** @defgroup SWPMI_Exported_Group3 SWPMI IRQ handler and callbacks * @brief SWPMI IRQ handler. * -@verbatim +@verbatim ============================================================================== ##### SWPMI IRQ handler and callbacks ##### - ============================================================================== -[..] This section provides SWPMI IRQ handler and callback functions called within + ============================================================================== +[..] This section provides SWPMI IRQ handler and callback functions called within the IRQ handler. @endverbatim @@ -932,7 +1240,7 @@ HAL_StatusTypeDef HAL_SWPMI_DisableLoopback(SWPMI_HandleTypeDef *hswpmi) /** * @brief Handle SWPMI interrupt request. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval None */ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) @@ -978,7 +1286,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) if(errcode != HAL_SWPMI_ERROR_NONE) { hswpmi->ErrorCode |= errcode; - + if((errcode & HAL_SWPMI_ERROR_UDR) != RESET) { /* Check TXDMA transfer to abort */ @@ -986,11 +1294,11 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) { /* Disable DMA TX at SWPMI level */ CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA); - + /* Abort the USART DMA Tx channel */ if(hswpmi->hdmatx != NULL) { - /* Set the SWPMI Tx DMA Abort callback : + /* Set the SWPMI Tx DMA Abort callback : will lead to call HAL_SWPMI_ErrorCallback() at end of DMA abort procedure */ hswpmi->hdmatx->XferAbortCallback = SWPMI_DMAAbortOnError; /* Abort DMA TX */ @@ -1005,7 +1313,11 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) /* Set the SWPMI state ready to be able to start again the process */ hswpmi->State = HAL_SWPMI_STATE_READY; +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->ErrorCallback(hswpmi); +#else HAL_SWPMI_ErrorCallback(hswpmi); +#endif } } else @@ -1013,7 +1325,11 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) /* Set the SWPMI state ready to be able to start again the process */ hswpmi->State = HAL_SWPMI_STATE_READY; +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->ErrorCallback(hswpmi); +#else HAL_SWPMI_ErrorCallback(hswpmi); +#endif } } else @@ -1023,11 +1339,11 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) { /* Disable DMA RX at SWPMI level */ CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA); - + /* Abort the USART DMA Rx channel */ if(hswpmi->hdmarx != NULL) { - /* Set the SWPMI Rx DMA Abort callback : + /* Set the SWPMI Rx DMA Abort callback : will lead to call HAL_SWPMI_ErrorCallback() at end of DMA abort procedure */ hswpmi->hdmarx->XferAbortCallback = SWPMI_DMAAbortOnError; /* Abort DMA RX */ @@ -1042,7 +1358,11 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) /* Set the SWPMI state ready to be able to start again the process */ hswpmi->State = HAL_SWPMI_STATE_READY; +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->ErrorCallback(hswpmi); +#else HAL_SWPMI_ErrorCallback(hswpmi); +#endif } } else @@ -1050,7 +1370,11 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) /* Set the SWPMI state ready to be able to start again the process */ hswpmi->State = HAL_SWPMI_STATE_READY; +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->ErrorCallback(hswpmi); +#else HAL_SWPMI_ErrorCallback(hswpmi); +#endif } } } @@ -1088,7 +1412,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) /** * @brief Tx Transfer completed callback. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval None */ __weak void HAL_SWPMI_TxCpltCallback(SWPMI_HandleTypeDef *hswpmi) @@ -1103,7 +1427,7 @@ __weak void HAL_SWPMI_TxCpltCallback(SWPMI_HandleTypeDef *hswpmi) /** * @brief Tx Half Transfer completed callback. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval None */ __weak void HAL_SWPMI_TxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi) @@ -1118,7 +1442,7 @@ __weak void HAL_SWPMI_TxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi) /** * @brief Rx Transfer completed callback. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval None */ __weak void HAL_SWPMI_RxCpltCallback(SWPMI_HandleTypeDef *hswpmi) @@ -1133,7 +1457,7 @@ __weak void HAL_SWPMI_RxCpltCallback(SWPMI_HandleTypeDef *hswpmi) /** * @brief Rx Half Transfer completed callback. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval None */ __weak void HAL_SWPMI_RxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi) @@ -1148,7 +1472,7 @@ __weak void HAL_SWPMI_RxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi) /** * @brief SWPMI error callback. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval None */ __weak void HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi) @@ -1182,7 +1506,7 @@ __weak void HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi) /** * @brief Return the SWPMI handle state. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval HAL state */ HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(SWPMI_HandleTypeDef *hswpmi) @@ -1219,7 +1543,7 @@ uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi) /** * @brief Transmit an amount of data in interrupt mode. * @note Function called under interruption only, once interruptions have been enabled by HAL_SWPMI_Transmit_IT() - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval HAL status */ static HAL_StatusTypeDef SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi) @@ -1249,7 +1573,7 @@ static HAL_StatusTypeDef SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi) /** * @brief Wraps up transmission in non-blocking mode. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval HAL status * @retval HAL status */ @@ -1269,8 +1593,12 @@ static HAL_StatusTypeDef SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi) { hswpmi->State = HAL_SWPMI_STATE_READY; } - + +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->TxCpltCallback(hswpmi); +#else HAL_SWPMI_TxCpltCallback(hswpmi); +#endif return HAL_OK; } @@ -1278,7 +1606,7 @@ static HAL_StatusTypeDef SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi) /** * @brief Receive an amount of data in interrupt mode. * @note Function called under interruption only, once interruptions have been enabled by HAL_SWPMI_Receive_IT() - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval HAL status */ static HAL_StatusTypeDef SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi) @@ -1292,7 +1620,11 @@ static HAL_StatusTypeDef SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi) if(--hswpmi->RxXferCount == 0) { /* Wait for RXBFF flag to update state */ +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->RxCpltCallback(hswpmi); +#else HAL_SWPMI_RxCpltCallback(hswpmi); +#endif } } else @@ -1305,7 +1637,7 @@ static HAL_StatusTypeDef SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi) /** * @brief Wraps up reception in non-blocking mode. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval HAL status * @retval HAL status */ @@ -1331,7 +1663,7 @@ static HAL_StatusTypeDef SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi) /** * @brief Wraps up transmission and reception in non-blocking mode. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval HAL status * @retval HAL status */ @@ -1357,7 +1689,7 @@ static HAL_StatusTypeDef SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi /** * @brief DMA SWPMI transmit process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma) @@ -1366,7 +1698,7 @@ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma) uint32_t tickstart = 0; /* DMA Normal mode*/ - if((hdma->Instance->CCR & DMA_CCR_CIRC) != SET) + if((hdma->Instance->CCR & DMA_CCR_CIRC) == RESET) { hswpmi->TxXferCount = 0; @@ -1381,7 +1713,13 @@ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma) if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, SWPMI_TIMEOUT_VALUE) != HAL_OK) { /* Timeout occurred */ + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_TXBEF_TIMEOUT; + +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->ErrorCallback(hswpmi); +#else HAL_SWPMI_ErrorCallback(hswpmi); +#endif } else { @@ -1396,32 +1734,44 @@ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma) hswpmi->State = HAL_SWPMI_STATE_READY; } +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->TxCpltCallback(hswpmi); +#else HAL_SWPMI_TxCpltCallback(hswpmi); +#endif } } /* DMA Circular mode */ else { +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->TxCpltCallback(hswpmi); +#else HAL_SWPMI_TxCpltCallback(hswpmi); +#endif } } /** * @brief DMA SWPMI transmit process half complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SWPMI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { SWPMI_HandleTypeDef* hswpmi = (SWPMI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->TxHalfCpltCallback(hswpmi); +#else HAL_SWPMI_TxHalfCpltCallback(hswpmi); +#endif } /** * @brief DMA SWPMI receive process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) @@ -1447,24 +1797,32 @@ static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) hswpmi->State = HAL_SWPMI_STATE_READY; } } +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->RxCpltCallback(hswpmi); +#else HAL_SWPMI_RxCpltCallback(hswpmi); +#endif } /** * @brief DMA SWPMI receive process half complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { SWPMI_HandleTypeDef* hswpmi = (SWPMI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->RxHalfCpltCallback(hswpmi); +#else HAL_SWPMI_RxHalfCpltCallback(hswpmi); +#endif } /** * @brief DMA SWPMI communication error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void SWPMI_DMAError(DMA_HandleTypeDef *hdma) @@ -1477,12 +1835,16 @@ static void SWPMI_DMAError(DMA_HandleTypeDef *hdma) hswpmi->State= HAL_SWPMI_STATE_READY; hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA; +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->ErrorCallback(hswpmi); +#else HAL_SWPMI_ErrorCallback(hswpmi); +#endif } /** * @brief DMA SWPMI communication abort callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma) @@ -1494,12 +1856,16 @@ static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma) hswpmi->TxXferCount = 0; hswpmi->State= HAL_SWPMI_STATE_READY; +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->ErrorCallback(hswpmi); +#else HAL_SWPMI_ErrorCallback(hswpmi); +#endif } /** * @brief Handle SWPMI Communication Timeout. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @param Flag: specifies the SWPMI flag to check. * @param Tickstart Tick start value * @param Timeout timeout duration. @@ -1517,6 +1883,7 @@ static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hs { if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout)) { + /* Set the SWPMI state ready to be able to start again the process */ hswpmi->State = HAL_SWPMI_STATE_READY; status = HAL_TIMEOUT; @@ -1533,16 +1900,15 @@ static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hs */ #endif /* HAL_SWPMI_MODULE_ENABLED */ + /** * @} */ +#endif /* SWPMI1 */ + /** * @} */ -#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c index 81368159df..f9aaf91fcc 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c @@ -42,6 +42,9 @@ (++) Output Compare (++) PWM generation (Edge and Center-aligned Mode) (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to interconnect + several timers together. + (#) Supports incremental encoder for positioning purposes ##### How to use this driver ##### ============================================================================== @@ -76,8 +79,8 @@ PWM signal. (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an external signal. - (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer - in One Pulse Mode. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. (#) Activate the TIM peripheral using one of the start functions depending from the feature used: @@ -92,6 +95,65 @@ HAL_TIM_DMABurst_WriteStart() HAL_TIM_DMABurst_ReadStart() + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Function @ref HAL_TIM_RegisterCallback() to register a callback. + @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + These functions allow to register/unregister following callbacks: + (+) Base_MspInitCallback : TIM Base Msp Init Callback. + (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + (+) IC_MspInitCallback : TIM IC Msp Init Callback. + (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + (+) OC_MspInitCallback : TIM OC Msp Init Callback. + (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. + (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. + (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + (+) TriggerCallback : TIM Trigger Callback. + (+) IC_CaptureCallback : TIM Input Capture Callback. + (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + (+) ErrorCallback : TIM Error Callback. + (+) CommutationCallback : TIM Commutation Callback. + (+) BreakCallback : TIM Break Callback. + +By default, after the Init and when the state is HAL_TIM_STATE_RESET +all interrupt callbacks are set to the corresponding weak functions: + examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). + + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init / DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + + Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + Exception done MspInit / MspDeInit that can be registered / unregistered + in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. + + When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + @endverbatim ****************************************************************************** * @attention @@ -149,17 +211,17 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); + uint32_t TIM_ICFilter); static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); + uint32_t TIM_ICFilter); static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource); + uint32_t TIM_ICFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig); + TIM_SlaveConfigTypeDef *sSlaveConfig); /* Exported functions --------------------------------------------------------*/ /** @defgroup TIM_Exported_Functions TIM Exported Functions @@ -190,17 +252,17 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /** * @brief Initializes the TIM Time base Unit according to the specified * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ - if(htim == NULL) + if (htim == NULL) { return HAL_ERROR; } @@ -211,29 +273,41 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - if(htim->State == HAL_TIM_STATE_RESET) + if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->Base_MspInitCallback == NULL) + { + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** - * @brief DeInitialize the TIM Base peripheral + * @brief DeInitializes the TIM Base peripheral * @param htim TIM Base handle * @retval HAL status */ @@ -247,8 +321,17 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Base_MspDeInitCallback == NULL) + { + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Base_MspDeInitCallback(htim); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -261,7 +344,7 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Base MSP. - * @param htim TIM handle + * @param htim TIM Base handle * @retval None */ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) @@ -275,8 +358,8 @@ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) } /** - * @brief DeInitialize TIM Base MSP. - * @param htim TIM handle + * @brief DeInitializes TIM Base MSP. + * @param htim TIM Base handle * @retval None */ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) @@ -292,22 +375,25 @@ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation. - * @param htim TIM handle + * @param htim TIM Base handle * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) + { + __HAL_TIM_ENABLE(htim); + } /* Change the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; @@ -315,22 +401,22 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Base generation. - * @param htim TIM handle + * @param htim TIM Base handle * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Change the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; @@ -338,19 +424,22 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation in interrupt mode. - * @param htim TIM handle + * @param htim TIM Base handle * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Enable the TIM Update interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -358,9 +447,9 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Base generation in interrupt mode. - * @param htim TIM handle + * @param htim TIM Base handle * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ @@ -377,23 +466,23 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation in DMA mode. - * @param htim TIM handle + * @param htim TIM Base handle * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to peripheral. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) { /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if ((htim->State == HAL_TIM_STATE_BUSY)) { - return HAL_BUSY; + return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if ((htim->State == HAL_TIM_STATE_READY)) { - if((pData == 0 ) && (Length > 0)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } @@ -402,6 +491,11 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat htim->State = HAL_TIM_STATE_BUSY; } } + else + { + /* nothing to do */ + } + /* Set the DMA Period elapsed callback */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; @@ -409,13 +503,19 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Update DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -423,9 +523,9 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /** * @brief Stops the TIM Base generation in DMA mode. - * @param htim TIM handle + * @param htim TIM Base handle * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) { /* Check the parameters */ @@ -471,18 +571,18 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) */ /** * @brief Initializes the TIM Output Compare according to the specified - * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() * @param htim TIM Output Compare handle * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ - if(htim == NULL) + if (htim == NULL) { return HAL_ERROR; } @@ -493,29 +593,41 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - if(htim->State == HAL_TIM_STATE_RESET) + if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->OC_MspInitCallback == NULL) + { + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OC_MspInitCallback(htim); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** - * @brief DeInitialize the TIM peripheral + * @brief DeInitializes the TIM peripheral * @param htim TIM Output Compare handle * @retval HAL status */ @@ -524,13 +636,22 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - htim->State = HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OC_MspDeInitCallback == NULL) + { + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OC_MspDeInitCallback(htim); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -543,7 +664,7 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare MSP. - * @param htim TIM handle + * @param htim TIM Output Compare handle * @retval None */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) @@ -557,8 +678,8 @@ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) } /** - * @brief DeInitialize TIM Output Compare MSP. - * @param htim TIM handle + * @brief DeInitializes TIM Output Compare MSP. + * @param htim TIM Output Compare handle * @retval None */ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) @@ -583,7 +704,7 @@ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -592,14 +713,17 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -607,7 +731,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation. - * @param htim TIM handle + * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -617,7 +741,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -626,9 +750,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } @@ -641,17 +765,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim TIM OC handle + * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -663,45 +785,48 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; } - break; case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; } - break; default: - break; + break; } /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -716,10 +841,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -731,40 +854,40 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; } - break; case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; } - break; default: - break; + break; } /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } @@ -784,24 +907,22 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if ((htim->State == HAL_TIM_STATE_BUSY)) { - return HAL_BUSY; + return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if ((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } @@ -810,6 +931,11 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->State = HAL_TIM_STATE_BUSY; } } + else + { + /* nothing to do */ + } + switch (Channel) { case TIM_CHANNEL_1: @@ -821,12 +947,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; } - break; case TIM_CHANNEL_2: { @@ -837,12 +966,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; } - break; case TIM_CHANNEL_3: { @@ -853,44 +985,51 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; } - break; case TIM_CHANNEL_4: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA Period elapsed callback */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; } - break; - default: - break; + default: + break; } /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -905,10 +1044,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -920,40 +1057,40 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + break; } - break; case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + break; } - break; default: - break; + break; } /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } @@ -980,7 +1117,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) ============================================================================== [..] This section provides functions allowing to: - (+) Initialize and configure the TIM OPWM. + (+) Initialize and configure the TIM PWM. (+) De-initialize the TIM PWM. (+) Start the Time PWM. (+) Stop the Time PWM. @@ -994,18 +1131,18 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) */ /** * @brief Initializes the TIM PWM Time Base according to the specified - * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() - * @param htim TIM handle + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ - if(htim == NULL) + if (htim == NULL) { return HAL_ERROR; } @@ -1016,30 +1153,42 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - if(htim->State == HAL_TIM_STATE_RESET) + if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->PWM_MspInitCallback == NULL) + { + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** - * @brief DeInitialize the TIM peripheral - * @param htim TIM handle + * @brief DeInitializes the TIM peripheral + * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) @@ -1052,8 +1201,17 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->PWM_MspDeInitCallback == NULL) + { + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + } + /* DeInit the low level hardware */ + htim->PWM_MspDeInitCallback(htim); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -1066,7 +1224,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM PWM MSP. - * @param htim TIM handle + * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) @@ -1080,8 +1238,8 @@ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) } /** - * @brief DeInitialize TIM PWM MSP. - * @param htim TIM handle + * @brief DeInitializes TIM PWM MSP. + * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) @@ -1106,7 +1264,7 @@ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -1115,14 +1273,17 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -1130,7 +1291,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the PWM signal generation. - * @param htim TIM handle + * @param htim TIM PWM handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1140,7 +1301,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -1149,9 +1310,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } @@ -1167,7 +1328,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the PWM signal generation in interrupt mode. - * @param htim TIM handle + * @param htim TIM PWM handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1175,7 +1336,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -1187,45 +1348,48 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; } - break; case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; } - break; default: - break; + break; } /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -1233,7 +1397,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the PWM signal generation in interrupt mode. - * @param htim TIM handle + * @param htim TIM PWM handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1241,8 +1405,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1253,40 +1417,40 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; } - break; case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; } - break; default: - break; + break; } /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } @@ -1299,7 +1463,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim TIM handle + * @param htim TIM PWM handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1309,19 +1473,19 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if ((htim->State == HAL_TIM_STATE_BUSY)) { - return HAL_BUSY; + return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if ((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } @@ -1330,6 +1494,11 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->State = HAL_TIM_STATE_BUSY; } } + else + { + /* nothing to do */ + } + switch (Channel) { case TIM_CHANNEL_1: @@ -1341,12 +1510,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; } - break; case TIM_CHANNEL_2: { @@ -1357,12 +1529,14 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; } - break; case TIM_CHANNEL_3: { @@ -1373,44 +1547,51 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Output Capture/Compare 3 request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; } - break; case TIM_CHANNEL_4: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA Period elapsed callback */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; } - break; default: - break; + break; } /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -1418,7 +1599,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim TIM handle + * @param htim TIM PWM handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1426,7 +1607,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -1438,40 +1619,40 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + break; } - break; case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + break; } - break; default: - break; + break; } /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } @@ -1494,36 +1675,36 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel * @verbatim ============================================================================== - ##### Time Input Capture functions ##### + ##### TIM Input Capture functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM Input Capture. (+) De-initialize the TIM Input Capture. - (+) Start the Time Input Capture. - (+) Stop the Time Input Capture. - (+) Start the Time Input Capture and enable interrupt. - (+) Stop the Time Input Capture and disable interrupt. - (+) Start the Time Input Capture and enable DMA transfer. - (+) Stop the Time Input Capture and disable DMA transfer. + (+) Start the TIM Input Capture. + (+) Stop the TIM Input Capture. + (+) Start the TIM Input Capture and enable interrupt. + (+) Stop the TIM Input Capture and disable interrupt. + (+) Start the TIM Input Capture and enable DMA transfer. + (+) Stop the TIM Input Capture and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Input Capture Time base according to the specified - * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ - if(htim == NULL) + if (htim == NULL) { return HAL_ERROR; } @@ -1534,29 +1715,41 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - if(htim->State == HAL_TIM_STATE_RESET) + if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->IC_MspInitCallback == NULL) + { + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->IC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the input capture */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** - * @brief DeInitialize the TIM peripheral + * @brief DeInitializes the TIM peripheral * @param htim TIM Input Capture handle * @retval HAL status */ @@ -1570,8 +1763,17 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->IC_MspDeInitCallback == NULL) + { + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->IC_MspDeInitCallback(htim); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -1583,8 +1785,8 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) } /** - * @brief Initializes the TIM INput Capture MSP. - * @param htim TIM handle + * @brief Initializes the TIM Input Capture MSP. + * @param htim TIM Input Capture handle * @retval None */ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) @@ -1598,7 +1800,7 @@ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) } /** - * @brief DeInitialize TIM Input Capture MSP. + * @brief DeInitializes TIM Input Capture MSP. * @param htim TIM handle * @retval None */ @@ -1622,8 +1824,8 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) + */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1631,8 +1833,11 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -1640,7 +1845,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Input Capture measurement. - * @param htim TIM handle + * @param htim TIM Input Capture handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1648,7 +1853,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -1674,8 +1879,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel) + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1686,38 +1891,41 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; } - break; case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; } - break; default: - break; + break; } /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -1725,7 +1933,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim TIM handle + * @param htim TIM Input Capture handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1733,7 +1941,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -1745,32 +1953,32 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; } - break; case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; } - break; default: - break; + break; } /* Disable the Input Capture channel */ @@ -1784,7 +1992,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } /** - * @brief Starts the TIM Input Capture measurement on in DMA mode. + * @brief Starts the TIM Input Capture measurement in DMA mode. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: @@ -1795,20 +2003,20 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) * @param pData The destination Buffer address. * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if ((htim->State == HAL_TIM_STATE_BUSY)) { - return HAL_BUSY; + return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if ((htim->State == HAL_TIM_STATE_READY)) { - if((pData == 0 ) && (Length > 0)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } @@ -1817,6 +2025,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->State = HAL_TIM_STATE_BUSY; } } + else + { + /* nothing to do */ + } switch (Channel) { @@ -1829,12 +2041,14 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; } - break; case TIM_CHANNEL_2: { @@ -1845,12 +2059,14 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; } - break; case TIM_CHANNEL_3: { @@ -1861,12 +2077,14 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; } - break; case TIM_CHANNEL_4: { @@ -1877,22 +2095,27 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; } - break; default: - break; + break; } /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -1908,7 +2131,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -1921,32 +2144,32 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + break; } - break; case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + break; } - break; default: - break; + break; } /* Disable the Input Capture channel */ @@ -1976,24 +2199,24 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) This section provides functions allowing to: (+) Initialize and configure the TIM One Pulse. (+) De-initialize the TIM One Pulse. - (+) Start the Time One Pulse. - (+) Stop the Time One Pulse. - (+) Start the Time One Pulse and enable interrupt. - (+) Stop the Time One Pulse and disable interrupt. - (+) Start the Time One Pulse and enable DMA transfer. - (+) Stop the Time One Pulse and disable DMA transfer. + (+) Start the TIM One Pulse. + (+) Stop the TIM One Pulse. + (+) Start the TIM One Pulse and enable interrupt. + (+) Stop the TIM One Pulse and disable interrupt. + (+) Start the TIM One Pulse and enable DMA transfer. + (+) Stop the TIM One Pulse and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM One Pulse Time Base according to the specified - * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() - * @param htim TIM OnePulse handle + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @param htim TIM One Pulse handle * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. @@ -2003,7 +2226,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) { /* Check the TIM handle allocation */ - if(htim == NULL) + if (htim == NULL) { return HAL_ERROR; } @@ -2015,17 +2238,29 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul assert_param(IS_TIM_OPM_MODE(OnePulseMode)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - if(htim->State == HAL_TIM_STATE_RESET) + if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->OnePulse_MspInitCallback == NULL) + { + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OnePulse_MspInitCallback(htim); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OnePulse_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; /* Configure the Time base in the One Pulse Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); @@ -2037,13 +2272,13 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul htim->Instance->CR1 |= OnePulseMode; /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** - * @brief DeInitialize the TIM One Pulse + * @brief DeInitializes the TIM One Pulse * @param htim TIM One Pulse handle * @retval HAL status */ @@ -2057,8 +2292,17 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OnePulse_MspDeInitCallback == NULL) + { + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OnePulse_MspDeInitCallback(htim); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_OnePulse_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -2071,7 +2315,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM One Pulse MSP. - * @param htim TIM handle + * @param htim TIM One Pulse handle * @retval None */ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) @@ -2085,8 +2329,8 @@ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) } /** - * @brief DeInitialize TIM One Pulse MSP. - * @param htim TIM handle + * @brief DeInitializes TIM One Pulse MSP. + * @param htim TIM One Pulse handle * @retval None */ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) @@ -2107,7 +2351,7 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Prevent unused argument(s) compilation warning */ @@ -2125,7 +2369,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); @@ -2143,7 +2387,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Prevent unused argument(s) compilation warning */ @@ -2158,9 +2402,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } @@ -2179,7 +2423,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Prevent unused argument(s) compilation warning */ @@ -2203,7 +2447,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); @@ -2221,7 +2465,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Prevent unused argument(s) compilation warning */ @@ -2241,14 +2485,14 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + __HAL_TIM_DISABLE(htim); /* Return function status */ return HAL_OK; @@ -2263,49 +2507,49 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @verbatim ============================================================================== - ##### Time Encoder functions ##### + ##### TIM Encoder functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM Encoder. (+) De-initialize the TIM Encoder. - (+) Start the Time Encoder. - (+) Stop the Time Encoder. - (+) Start the Time Encoder and enable interrupt. - (+) Stop the Time Encoder and disable interrupt. - (+) Start the Time Encoder and enable DMA transfer. - (+) Stop the Time Encoder and disable DMA transfer. + (+) Start the TIM Encoder. + (+) Stop the TIM Encoder. + (+) Start the TIM Encoder and enable interrupt. + (+) Stop the TIM Encoder and disable interrupt. + (+) Start the TIM Encoder and enable DMA transfer. + (+) Stop the TIM Encoder and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Encoder Interface and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) { - uint32_t tmpsmcr = 0; - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; /* Check the TIM handle allocation */ - if(htim == NULL) + if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); @@ -2316,17 +2560,29 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); - if(htim->State == HAL_TIM_STATE_RESET) + if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->Encoder_MspInitCallback == NULL) + { + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; /* Reset the SMS bits */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; @@ -2348,18 +2604,18 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); - tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8)); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); - tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8); - tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); /* Set the TI1 and the TI2 Polarities */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); - tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; @@ -2371,15 +2627,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini htim->Instance->CCER = tmpccer; /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** - * @brief DeInitialize the TIM Encoder interface - * @param htim TIM Encoder handle + * @brief DeInitializes the TIM Encoder interface + * @param htim TIM Encoder Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) @@ -2392,8 +2648,17 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Encoder_MspDeInitCallback == NULL) + { + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Encoder_MspDeInitCallback(htim); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_Encoder_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -2406,7 +2671,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Encoder Interface MSP. - * @param htim TIM handle + * @param htim TIM Encoder Interface handle * @retval None */ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) @@ -2420,8 +2685,8 @@ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) } /** - * @brief DeInitialize TIM Encoder Interface MSP. - * @param htim TIM handle + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle * @retval None */ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) @@ -2443,7 +2708,7 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -2455,21 +2720,21 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe case TIM_CHANNEL_1: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; } - break; case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; } - break; default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; } - break; } /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); @@ -2487,7 +2752,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -2500,21 +2765,21 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel case TIM_CHANNEL_1: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; } - break; case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; } - break; default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; } - break; } /* Disable the Peripheral */ @@ -2533,7 +2798,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -2547,15 +2812,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; } - break; case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; } - break; default : { @@ -2563,8 +2828,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; } - break; } /* Enable the Peripheral */ @@ -2583,7 +2848,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -2591,19 +2856,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if(Channel == TIM_CHANNEL_1) + if (Channel == TIM_CHANNEL_1) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 1 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); } - else if(Channel == TIM_CHANNEL_2) + else if (Channel == TIM_CHANNEL_2) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); } else { @@ -2637,19 +2902,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan * @param pData2 The destination Buffer address for IC2. * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) { /* Check the parameters */ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if ((htim->State == HAL_TIM_STATE_BUSY)) { - return HAL_BUSY; + return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if ((htim->State == HAL_TIM_STATE_READY)) { - if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0)) + if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) { return HAL_ERROR; } @@ -2658,6 +2923,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->State = HAL_TIM_STATE_BUSY; } } + else + { + /* nothing to do */ + } switch (Channel) { @@ -2670,8 +2939,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); @@ -2680,8 +2951,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; } - break; case TIM_CHANNEL_2: { @@ -2691,8 +2962,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); @@ -2701,8 +2974,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; } - break; case TIM_CHANNEL_ALL: { @@ -2713,7 +2986,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Set the DMA Period elapsed callback */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; @@ -2722,9 +2998,11 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); - - /* Enable the Peripheral */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); /* Enable the Capture compare channel */ @@ -2735,11 +3013,11 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; } - break; default: - break; + break; } /* Return function status */ return HAL_OK; @@ -2754,7 +3032,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -2762,14 +3040,14 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if(Channel == TIM_CHANNEL_1) + if (Channel == TIM_CHANNEL_1) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare DMA Request 1 */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); } - else if(Channel == TIM_CHANNEL_2) + else if (Channel == TIM_CHANNEL_2) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); @@ -2820,126 +3098,191 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { /* Capture compare 1 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00) + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } } /* Capture compare 2 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00) + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } /* Capture compare 3 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00) + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } /* Capture compare 4 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00) + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } /* TIM Update event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else HAL_TIMEx_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break2 input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->Break2Callback(htim); +#else + HAL_TIMEx_Break2Callback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else HAL_TIMEx_CommutationCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } @@ -2949,7 +3292,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) */ /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions - * @brief Peripheral Control functions + * @brief Peripheral Control functions * @verbatim ============================================================================== @@ -2983,7 +3326,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef* sConfig, + TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { /* Check the parameters */ @@ -3005,8 +3348,8 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); + break; } - break; case TIM_CHANNEL_2: { @@ -3015,51 +3358,51 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, /* Configure the TIM Channel 2 in Output Compare */ TIM_OC2_SetConfig(htim->Instance, sConfig); + break; } - break; case TIM_CHANNEL_3: { /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); + break; } - break; case TIM_CHANNEL_4: { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 4 in Output Compare */ - TIM_OC4_SetConfig(htim->Instance, sConfig); + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + break; } - break; case TIM_CHANNEL_5: { /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 5 in Output Compare */ - TIM_OC5_SetConfig(htim->Instance, sConfig); + /* Configure the TIM Channel 5 in Output Compare */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + break; } - break; case TIM_CHANNEL_6: { /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 6 in Output Compare */ - TIM_OC6_SetConfig(htim->Instance, sConfig); + /* Configure the TIM Channel 6 in Output Compare */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + break; } - break; default: - break; + break; } htim->State = HAL_TIM_STATE_READY; @@ -3074,7 +3417,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, * parameters in the TIM_IC_InitTypeDef. * @param htim TIM IC handle * @param sConfig TIM Input Capture configuration structure - * @param Channel TIM Channels to be enabled + * @param Channel TIM Channel to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3082,7 +3425,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel) +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); @@ -3100,9 +3443,9 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT { /* TI1 Configuration */ TIM_TI1_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; @@ -3124,7 +3467,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; /* Set the IC2PSC value */ - htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8); + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); } else if (Channel == TIM_CHANNEL_3) { @@ -3132,9 +3475,9 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); TIM_TI3_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); /* Reset the IC3PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; @@ -3148,15 +3491,15 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); TIM_TI4_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); /* Reset the IC4PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; /* Set the IC4PSC value */ - htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8); + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); } htim->State = HAL_TIM_STATE_READY; @@ -3182,7 +3525,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef* sConfig, + TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { /* Check the parameters */ @@ -3212,8 +3555,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; htim->Instance->CCMR1 |= sConfig->OCFastMode; + break; } - break; case TIM_CHANNEL_2: { @@ -3228,9 +3571,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode << 8; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + break; } - break; case TIM_CHANNEL_3: { @@ -3243,11 +3586,11 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; - /* Configure the Output Fast mode */ + /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; htim->Instance->CCMR2 |= sConfig->OCFastMode; + break; } - break; case TIM_CHANNEL_4: { @@ -3260,48 +3603,48 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; - /* Configure the Output Fast mode */ + /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + break; } - break; case TIM_CHANNEL_5: { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); - /* Configure the Channel 5 in PWM mode */ + /* Configure the Channel 5 in PWM mode */ TIM_OC5_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel5*/ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; - /* Configure the Output Fast mode */ + /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; htim->Instance->CCMR3 |= sConfig->OCFastMode; + break; } - break; case TIM_CHANNEL_6: { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); - /* Configure the Channel 5 in PWM mode */ + /* Configure the Channel 6 in PWM mode */ TIM_OC6_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel6 */ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; - /* Configure the Output Fast mode */ + /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; - htim->Instance->CCMR3 |= sConfig->OCFastMode << 8; + htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; + break; } - break; default: - break; + break; } htim->State = HAL_TIM_STATE_READY; @@ -3316,17 +3659,17 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, * parameters in the TIM_OnePulse_InitTypeDef. * @param htim TIM One Pulse handle * @param sConfig TIM One Pulse configuration structure - * @param OutputChannel TIM Channels to be enabled + * @param OutputChannel TIM output channel to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param InputChannel TIM Channels to be enabled + * @param InputChannel TIM input Channel to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel) +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel) { TIM_OC_InitTypeDef temp1; @@ -3334,14 +3677,14 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); - if(OutputChannel != InputChannel) + if (OutputChannel != InputChannel) { /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; - /* Extract the Ouput compare configuration from sConfig structure */ + /* Extract the Output compare configuration from sConfig structure */ temp1.OCMode = sConfig->OCMode; temp1.Pulse = sConfig->Pulse; temp1.OCPolarity = sConfig->OCPolarity; @@ -3356,17 +3699,17 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); TIM_OC1_SetConfig(htim->Instance, &temp1); + break; } - break; case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); TIM_OC2_SetConfig(htim->Instance, &temp1); + break; } - break; default: - break; + break; } switch (InputChannel) @@ -3388,8 +3731,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O /* Select the Slave Mode */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; } - break; case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); @@ -3407,11 +3750,11 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O /* Select the Slave Mode */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; } - break; default: - break; + break; } htim->State = HAL_TIM_STATE_READY; @@ -3429,8 +3772,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O /** * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data write - * This parameters can be on of the following values: + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR @@ -3451,7 +3794,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR * @param BurstRequestSrc TIM DMA Request sources - * This parameters can be on of the following values: + * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source @@ -3461,11 +3804,11 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t* BurstBuffer, uint32_t BurstLength) + uint32_t *BurstBuffer, uint32_t BurstLength) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); @@ -3473,13 +3816,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if ((htim->State == HAL_TIM_STATE_BUSY)) { - return HAL_BUSY; + return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if ((htim->State == HAL_TIM_STATE_READY)) { - if((BurstBuffer == 0 ) && (BurstLength > 0)) + if ((BurstBuffer == NULL) && (BurstLength > 0U)) { return HAL_ERROR; } @@ -3488,7 +3831,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->State = HAL_TIM_STATE_BUSY; } } - switch(BurstRequestSrc) + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { @@ -3499,57 +3846,72 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_CC1: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_CC2: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_CC3: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_CC4: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_COM: { /* Set the DMA Period elapsed callback */ @@ -3559,9 +3921,12 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_TRIGGER: { /* Set the DMA Period elapsed callback */ @@ -3571,19 +3936,22 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; default: - break; + break; } - /* configure the DMA Burst Mode */ - htim->Instance->DCR = BurstBaseAddress | BurstLength; + /* configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - htim->State = HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; @@ -3597,63 +3965,67 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { + HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); /* Abort the DMA transfer (at least disable the DMA channel) */ - switch(BurstRequestSrc) + switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); + status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); + break; } - break; case TIM_DMA_CC1: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); + status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); + break; } - break; case TIM_DMA_CC2: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); + status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); + break; } - break; case TIM_DMA_CC3: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); + status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); + break; } - break; case TIM_DMA_CC4: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); + status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); + break; } - break; case TIM_DMA_COM: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); + status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; } - break; case TIM_DMA_TRIGGER: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); + status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; } - break; default: - break; + break; } - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + if (HAL_OK == status) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + } /* Return function status */ - return HAL_OK; + return status; } /** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data read - * This parameters can be on of the following values: + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR @@ -3674,7 +4046,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR * @param BurstRequestSrc TIM DMA Request sources - * This parameters can be on of the following values: + * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source @@ -3684,7 +4056,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, @@ -3696,13 +4068,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if ((htim->State == HAL_TIM_STATE_BUSY)) { - return HAL_BUSY; + return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if ((htim->State == HAL_TIM_STATE_READY)) { - if((BurstBuffer == 0 ) && (BurstLength > 0)) + if ((BurstBuffer == NULL) && (BurstLength > 0U)) { return HAL_ERROR; } @@ -3711,7 +4083,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->State = HAL_TIM_STATE_BUSY; } } - switch(BurstRequestSrc) + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { @@ -3722,57 +4098,72 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_CC1: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_CC2: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_CC3: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_CC4: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_COM: { /* Set the DMA Period elapsed callback */ @@ -3782,9 +4173,12 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_TRIGGER: { /* Set the DMA Period elapsed callback */ @@ -3794,15 +4188,18 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; default: - break; + break; } /* configure the DMA Burst Mode */ - htim->Instance->DCR = BurstBaseAddress | BurstLength; + htim->Instance->DCR = (BurstBaseAddress | BurstLength); /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); @@ -3821,56 +4218,60 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { + HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); /* Abort the DMA transfer (at least disable the DMA channel) */ - switch(BurstRequestSrc) + switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); + status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); + break; } - break; case TIM_DMA_CC1: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); + status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); + break; } - break; case TIM_DMA_CC2: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); + status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); + break; } - break; case TIM_DMA_CC3: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); + status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); + break; } - break; case TIM_DMA_CC4: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); + status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); + break; } - break; case TIM_DMA_COM: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); + status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; } - break; case TIM_DMA_TRIGGER: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); + status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; } - break; default: - break; + break; } - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + if (HAL_OK == status) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -3887,6 +4288,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source + * @note Basic timers can only generate an update event. + * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. + * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant + * only for timer instances supporting break input(s). * @retval HAL status */ @@ -3921,20 +4326,18 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS * contains the OCREF clear feature and parameters for the TIM peripheral. * @param Channel specifies the TIM Channel * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @arg TIM_Channel_5: TIM Channel 5 - * @arg TIM_Channel_6: TIM Channel 6 - * @retval None + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel) { - uint32_t tmpsmcr = 0; - /* Check the parameters */ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); @@ -3942,28 +4345,20 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, /* Process Locked */ __HAL_LOCK(htim); + htim->State = HAL_TIM_STATE_BUSY; + switch (sClearInputConfig->ClearInputSource) { case TIM_CLEARINPUTSOURCE_NONE: { - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Clear the OCREF clear selection bit */ - tmpsmcr &= ~TIM_SMCR_OCCS; - - /* Clear the ETR Bits */ - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - - /* Set TIMx_SMCR */ - htim->Instance->SMCR = tmpsmcr; - } - break; - + /* Clear the OCREF clear selection bit and the the ETR Bits */ + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + break; + } case TIM_CLEARINPUTSOURCE_OCREFCLR: { /* Clear the OCREF clear selection bit */ - htim->Instance->SMCR &= ~TIM_SMCR_OCCS; + CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); } break; @@ -3980,104 +4375,106 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, sClearInputConfig->ClearInputFilter); /* Set the OCREF clear selection bit */ - htim->Instance->SMCR |= TIM_SMCR_OCCS; + SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); + break; } - break; - default: - break; + default: + break; } switch (Channel) { case TIM_CHANNEL_1: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; - } - else - { - /* Disable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; - } + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); } break; + } case TIM_CHANNEL_2: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; - } - else - { - /* Disable the OCREF clear feature for Channel 2 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; - } + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); } - break; + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; + } case TIM_CHANNEL_3: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; - } - else - { - /* Disable the OCREF clear feature for Channel 3 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; - } + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); } - break; + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; + } case TIM_CHANNEL_4: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; - } - else - { - /* Disable the OCREF clear feature for Channel 4 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; - } + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); } - break; + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; + } case TIM_CHANNEL_5: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE; - } - else - { - /* Disable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE; - } + /* Enable the OCREF clear feature for Channel 5 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); } - break; + else + { + /* Disable the OCREF clear feature for Channel 5 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + break; + } case TIM_CHANNEL_6: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE; - } - else - { - /* Disable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE; - } + /* Enable the OCREF clear feature for Channel 6 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); } - break; + else + { + /* Disable the OCREF clear feature for Channel 6 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + break; + } default: - break; + break; } + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); return HAL_OK; @@ -4090,9 +4487,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, * contains the clock source information for the TIM peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) { - uint32_t tmpsmcr = 0; + uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); @@ -4110,15 +4507,15 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo switch (sClockSourceConfig->ClockSource) { - case TIM_CLOCKSOURCE_INTERNAL: + case TIM_CLOCKSOURCE_INTERNAL: { assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Disable slave mode to clock the prescaler directly with the internal clock */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; + break; } - break; - case TIM_CLOCKSOURCE_ETRMODE1: + case TIM_CLOCKSOURCE_ETRMODE1: { /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); @@ -4141,10 +4538,10 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; + break; } - break; - case TIM_CLOCKSOURCE_ETRMODE2: + case TIM_CLOCKSOURCE_ETRMODE2: { /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); @@ -4161,10 +4558,10 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo sClockSourceConfig->ClockFilter); /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; + break; } - break; - case TIM_CLOCKSOURCE_TI1: + case TIM_CLOCKSOURCE_TI1: { /* Check whether or not the timer instance supports external clock mode 1 */ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); @@ -4177,10 +4574,10 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + break; } - break; - case TIM_CLOCKSOURCE_TI2: + case TIM_CLOCKSOURCE_TI2: { /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); @@ -4193,10 +4590,10 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + break; } - break; - case TIM_CLOCKSOURCE_TI1ED: + case TIM_CLOCKSOURCE_TI1ED: { /* Check whether or not the timer instance supports external clock mode 1 */ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); @@ -4209,47 +4606,23 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + break; } - break; - - case TIM_CLOCKSOURCE_ITR0: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0); - } - break; - - case TIM_CLOCKSOURCE_ITR1: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1); - } - break; - - case TIM_CLOCKSOURCE_ITR2: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2); - } - break; - case TIM_CLOCKSOURCE_ITR3: + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3); + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; } - break; - default: - break; + default: + break; } htim->State = HAL_TIM_STATE_READY; @@ -4272,7 +4645,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo */ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) { - uint32_t tmpcr2 = 0; + uint32_t tmpcr2; /* Check the parameters */ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); @@ -4298,11 +4671,11 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S * @param htim TIM handle. * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the ) and the Slave - * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); @@ -4326,21 +4699,21 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI __HAL_UNLOCK(htim); return HAL_OK; - } +} /** * @brief Configures the TIM in Slave mode in interrupt mode * @param htim TIM handle. * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the ) and the Slave - * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig) - { - /* Check the parameters */ + TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); @@ -4362,7 +4735,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, __HAL_UNLOCK(htim); return HAL_OK; - } +} /** * @brief Read the captured value from Capture Compare unit @@ -4377,13 +4750,13 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, */ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; __HAL_LOCK(htim); switch (Channel) { - case TIM_CHANNEL_1: + case TIM_CHANNEL_1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); @@ -4393,7 +4766,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) break; } - case TIM_CHANNEL_2: + case TIM_CHANNEL_2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); @@ -4404,7 +4777,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) break; } - case TIM_CHANNEL_3: + case TIM_CHANNEL_3: { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); @@ -4415,7 +4788,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) break; } - case TIM_CHANNEL_4: + case TIM_CHANNEL_4: { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); @@ -4426,8 +4799,8 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) break; } - default: - break; + default: + break; } __HAL_UNLOCK(htim); @@ -4468,7 +4841,7 @@ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, - the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } @@ -4483,7 +4856,7 @@ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, - the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } /** @@ -4497,7 +4870,7 @@ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, - the __HAL_TIM_IC_CaptureCallback could be implemented in the user file + the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } @@ -4512,7 +4885,7 @@ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, - the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } @@ -4546,6 +4919,447 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) */ } +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TIM callback to be used instead of the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(htim); + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = pCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = pCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = pCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = pCallback; + break; + + case HAL_TIM_BREAK2_CB_ID : + htim->Break2Callback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Unregister a TIM callback + * TIM callback is redirected to the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + */ +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(htim); + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = HAL_TIMEx_CommutationCallback; /* Legacy weak Commutation Callback */ + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */ + break; + + case HAL_TIM_BREAK2_CB_ID : + htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /** * @} */ @@ -4577,7 +5391,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM OC handle state. - * @param htim TIM Ouput Compare handle + * @param htim TIM Output Compare handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) @@ -4617,7 +5431,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Encoder Mode handle state. - * @param htim TIM Encoder handle + * @param htim TIM Encoder Interface handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) @@ -4629,6 +5443,14 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) * @} */ +/** + * @} + */ + +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ + /** * @brief TIM DMA error callback * @param hdma pointer to DMA handle. @@ -4636,11 +5458,15 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) */ void TIM_DMAError(DMA_HandleTypeDef *hdma) { - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** @@ -4650,9 +5476,9 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) */ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { @@ -4670,8 +5496,16 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; } + else + { + /* nothing to do */ + } +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } @@ -4682,9 +5516,9 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) */ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) { - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { @@ -4702,8 +5536,16 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; } + else + { + /* nothing to do */ + } +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } @@ -4715,11 +5557,15 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) */ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) { - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** @@ -4729,11 +5575,15 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) */ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) { - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** @@ -4744,7 +5594,7 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { - uint32_t tmpcr1 = 0; + uint32_t tmpcr1; tmpcr1 = TIMx->CR1; /* Set TIM Time Base Unit parameters ---------------------------------------*/ @@ -4755,7 +5605,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) tmpcr1 |= Structure->CounterMode; } - if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; @@ -4763,8 +5613,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) } /* Set the auto-reload preload */ - tmpcr1 &= ~TIM_CR1_ARPE; - tmpcr1 |= (uint32_t)Structure->AutoReloadPreload; + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); TIMx->CR1 = tmpcr1; @@ -4772,7 +5621,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) TIMx->ARR = (uint32_t)Structure->Period ; /* Set the Prescaler value */ - TIMx->PSC = (uint32_t)Structure->Prescaler; + TIMx->PSC = Structure->Prescaler; if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) { @@ -4781,23 +5630,23 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) } /* Generate an update event to reload the Prescaler - and the repetition counter(only for TIM1 and TIM8) value immediately */ + and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; } /** - * @brief Time Ouput Compare 1 configuration + * @brief Timer Output Compare 1 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; - /* Disable the Channel 1: Reset the CC1E Bit */ + /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; /* Get the TIMx CCER register value */ @@ -4819,7 +5668,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; - if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); @@ -4832,7 +5681,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpccer &= ~TIM_CCER_CC1NE; } - if(IS_TIM_BREAK_INSTANCE(TIMx)) + if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); @@ -4846,6 +5695,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; } + /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; @@ -4860,16 +5710,16 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) } /** - * @brief Time Ouput Compare 2 configuration + * @brief Timer Output Compare 2 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The ouput configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; @@ -4887,27 +5737,27 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpccmrx &= ~TIM_CCMR1_CC2S; /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); + tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 4); + tmpccer |= (OC_Config->OCPolarity << 4U); - if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 4); + tmpccer |= (OC_Config->OCNPolarity << 4U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; } - if(IS_TIM_BREAK_INSTANCE(TIMx)) + if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); @@ -4917,9 +5767,9 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpcr2 &= ~TIM_CR2_OIS2; tmpcr2 &= ~TIM_CR2_OIS2N; /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 2); + tmpcr2 |= (OC_Config->OCIdleState << 2U); /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 2); + tmpcr2 |= (OC_Config->OCNIdleState << 2U); } /* Write to TIMx CR2 */ @@ -4936,16 +5786,16 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) } /** - * @brief Time Ouput Compare 3 configuration + * @brief Timer Output Compare 3 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; @@ -4967,21 +5817,21 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 8); + tmpccer |= (OC_Config->OCPolarity << 8U); - if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 8); + tmpccer |= (OC_Config->OCNPolarity << 8U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; } - if(IS_TIM_BREAK_INSTANCE(TIMx)) + if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); @@ -4991,9 +5841,9 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpcr2 &= ~TIM_CR2_OIS3; tmpcr2 &= ~TIM_CR2_OIS3N; /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 4); + tmpcr2 |= (OC_Config->OCIdleState << 4U); /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 4); + tmpcr2 |= (OC_Config->OCNIdleState << 4U); } /* Write to TIMx CR2 */ @@ -5010,16 +5860,16 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) } /** - * @brief Time Ouput Compare 4 configuration + * @brief Timer Output Compare 4 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; @@ -5037,21 +5887,23 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpccmrx &= ~TIM_CCMR2_CC4S; /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); + tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 12); + tmpccer |= (OC_Config->OCPolarity << 12U); - if(IS_TIM_BREAK_INSTANCE(TIMx)) + if (IS_TIM_BREAK_INSTANCE(TIMx)) { + /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - /* Reset the Output Compare IDLE State */ + /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; + /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 6); + tmpcr2 |= (OC_Config->OCIdleState << 6U); } /* Write to TIMx CR2 */ @@ -5068,7 +5920,7 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) } /** - * @brief Timer Ouput Compare 5 configuration + * @brief Timer Output Compare 5 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The ouput configuration structure * @retval None @@ -5076,9 +5928,9 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; @@ -5098,14 +5950,14 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC5P; /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 16); + tmpccer |= (OC_Config->OCPolarity << 16U); - if(IS_TIM_BREAK_INSTANCE(TIMx)) + if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS5; /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 8); + tmpcr2 |= (OC_Config->OCIdleState << 8U); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; @@ -5121,7 +5973,7 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, } /** - * @brief Timer Ouput Compare 6 configuration + * @brief Timer Output Compare 6 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The ouput configuration structure * @retval None @@ -5129,9 +5981,9 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; @@ -5146,19 +5998,19 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC6M); /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); + tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= (uint32_t)~TIM_CCER_CC6P; /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 20); + tmpccer |= (OC_Config->OCPolarity << 20U); - if(IS_TIM_BREAK_INSTANCE(TIMx)) + if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS6; /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 10); + tmpcr2 |= (OC_Config->OCIdleState << 10U); } /* Write to TIMx CR2 */ @@ -5174,12 +6026,18 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIMx->CCER = tmpccer; } +/** + * @brief Slave Timer configuration function + * @param htim TIM handle + * @param sSlaveConfig Slave timer configuration + * @retval None + */ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig) + TIM_SlaveConfigTypeDef *sSlaveConfig) { - uint32_t tmpsmcr = 0; - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; @@ -5200,7 +6058,7 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /* Configure the trigger prescaler, filter, and polarity */ switch (sSlaveConfig->InputTrigger) { - case TIM_TS_ETRF: + case TIM_TS_ETRF: { /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); @@ -5212,10 +6070,10 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, sSlaveConfig->TriggerPrescaler, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); + break; } - break; - case TIM_TS_TI1F_ED: + case TIM_TS_TI1F_ED: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); @@ -5228,16 +6086,15 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4); + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); /* Write to TIMx CCMR1 and CCER registers */ htim->Instance->CCMR1 = tmpccmr1; htim->Instance->CCER = tmpccer; - + break; } - break; - case TIM_TS_TI1FP1: + case TIM_TS_TI1FP1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); @@ -5248,10 +6105,10 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, TIM_TI1_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); + break; } - break; - case TIM_TS_TI2FP2: + case TIM_TS_TI2FP2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); @@ -5260,41 +6117,23 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /* Configure TI2 Filter and Polarity */ TIM_TI2_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_ITR0: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR1: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR2: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; } - break; - case TIM_TS_ITR3: + case TIM_TS_ITR0: + case TIM_TS_ITR1: + case TIM_TS_ITR2: + case TIM_TS_ITR3: { /* Check the parameter */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; } - break; - default: - break; + default: + break; } } @@ -5303,14 +6142,14 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None @@ -5321,8 +6160,8 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr1; + uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; @@ -5330,7 +6169,7 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ tmpccer = TIMx->CCER; /* Select the Input */ - if(IS_TIM_CC2_INSTANCE(TIMx) != RESET) + if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) { tmpccmr1 &= ~TIM_CCMR1_CC1S; tmpccmr1 |= TIM_ICSelection; @@ -5342,7 +6181,7 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F); + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); @@ -5358,17 +6197,17 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr1; + uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; @@ -5377,7 +6216,7 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= (TIM_ICFilter << 4); + tmpccmr1 |= (TIM_ICFilter << 4U); /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); @@ -5393,14 +6232,14 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None @@ -5409,10 +6248,10 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, * protected against un-initialized filter and polarity values. */ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) + uint32_t TIM_ICFilter) { - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr1; + uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; @@ -5421,15 +6260,15 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; - tmpccmr1 |= (TIM_ICSelection << 8); + tmpccmr1 |= (TIM_ICSelection << 8U); /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F); + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; @@ -5441,17 +6280,17 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr1; + uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; @@ -5460,11 +6299,11 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= (TIM_ICFilter << 12); + tmpccmr1 |= (TIM_ICFilter << 12U); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (TIM_ICPolarity << 4); + tmpccer |= (TIM_ICPolarity << 4U); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; @@ -5476,14 +6315,14 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None @@ -5492,10 +6331,10 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, * protected against un-initialized filter and polarity values. */ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) + uint32_t TIM_ICFilter) { - uint32_t tmpccmr2 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr2; + uint32_t tmpccer; /* Disable the Channel 3: Reset the CC3E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; @@ -5508,11 +6347,11 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC3F; - tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F); + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); /* Select the Polarity and set the CC3E Bit */ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; @@ -5524,14 +6363,14 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 @@ -5540,10 +6379,10 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @retval None */ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) + uint32_t TIM_ICFilter) { - uint32_t tmpccmr2 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr2; + uint32_t tmpccer; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; @@ -5552,15 +6391,15 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S; - tmpccmr2 |= (TIM_ICSelection << 8); + tmpccmr2 |= (TIM_ICSelection << 8U); /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC4F; - tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F); + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); /* Select the Polarity and set the CC4E Bit */ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; @@ -5582,40 +6421,40 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ -static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { - uint32_t tmpsmcr = 0; - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the TS Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source and the slave mode*/ - tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; } /** * @brief Configures the TIMx External Trigger (ETR). * @param TIMx to select the TIM peripheral * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. * This parameter can be one of the following values: - * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF. - * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2. - * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4. - * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8. + * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. * @param TIM_ExtTRGPolarity The external Trigger Polarity. * This parameter can be one of the following values: - * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active. - * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active. + * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. * @param ExtTRGFilter External Trigger Filter. * This parameter must be a value between 0x00 and 0x0F * @retval None */ -void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { - uint32_t tmpsmcr = 0; + uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; @@ -5623,7 +6462,7 @@ void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8))); + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; @@ -5638,27 +6477,49 @@ void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @arg TIM_CHANNEL_4: TIM Channel 4 - * @param ChannelState: specifies the TIM Channel CCxE bit new state. + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. * @retval None */ -void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState) +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { - uint32_t tmp = 0; + uint32_t tmp; /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); - tmp = TIM_CCER_CC1E << Channel; + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint32_t)(ChannelState << Channel); + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ } +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy week callbacks. + * @param htim pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +void TIM_ResetCallback(TIM_HandleTypeDef *htim) +{ + /* Reset the TIM callback to the legacy weak callbacks */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ + htim->CommutationCallback = HAL_TIMEx_CommutationCallback; /* Legacy weak CommutationCallback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */ +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c index 6f332d1441..5c26d23357 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c @@ -50,10 +50,10 @@ (#) Configure the TIM in the desired functioning mode using one of the initialization function of this driver: (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutationEvent(): to use the - Timer Hall Sensor Interface and the commutation event with the corresponding - Interrupt and DMA request if needed (Note that One Timer is used to interface - with the Hall sensor Interface and another Timer should be used to use - the commutation event). + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). (#) Activate the TIM peripheral using one of the start functions: (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT() @@ -61,7 +61,6 @@ (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). - @endverbatim ****************************************************************************** * @attention @@ -109,16 +108,10 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -#define BDTR_BKF_SHIFT (16) -#define BDTR_BK2F_SHIFT (20) -#define TIMx_ETRSEL_MASK ((uint32_t)0x0003C000) - /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState); - -/* Private functions ---------------------------------------------------------*/ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); /* Exported functions --------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions @@ -148,20 +141,21 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha */ /** * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. - * @param htim TIM Encoder Interface handle + * @param htim TIM Hall Sensor Interface handle * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig) +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) { TIM_OC_InitTypeDef OC_Config; /* Check the TIM handle allocation */ - if(htim == NULL) + if (htim == NULL) { return HAL_ERROR; } + /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); @@ -170,13 +164,25 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - if(htim->State == HAL_TIM_STATE_RESET) + if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->HallSensor_MspInitCallback == NULL) + { + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->HallSensor_MspInitCallback(htim); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIMEx_HallSensor_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ @@ -221,14 +227,14 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen htim->Instance->CR2 |= TIM_TRGO_OC2REF; /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** - * @brief DeInitialize the TIM Hall Sensor interface - * @param htim TIM Hall Sensor handle + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) @@ -241,8 +247,17 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->HallSensor_MspDeInitCallback == NULL) + { + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + } + /* DeInit the low level hardware */ + htim->HallSensor_MspDeInitCallback(htim); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIMEx_HallSensor_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -255,7 +270,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Hall Sensor MSP. - * @param htim TIM handle + * @param htim TIM Hall Sensor Interface handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) @@ -269,8 +284,8 @@ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) } /** - * @brief DeInitialize TIM Hall Sensor MSP. - * @param htim TIM handle + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) @@ -285,7 +300,7 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface. - * @param htim TIM Hall Sensor handle + * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) @@ -297,8 +312,11 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -306,7 +324,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Hall sensor Interface. - * @param htim TIM Hall Sensor handle + * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) @@ -327,7 +345,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface in interrupt mode. - * @param htim TIM Hall Sensor handle + * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) @@ -342,8 +360,11 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -351,7 +372,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Hall Sensor Interface in interrupt mode. - * @param htim TIM handle + * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) @@ -375,7 +396,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface in DMA mode. - * @param htim TIM Hall Sensor handle + * @param htim TIM Hall Sensor Interface handle * @param pData The destination Buffer address. * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status @@ -385,13 +406,13 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if ((htim->State == HAL_TIM_STATE_BUSY)) { - return HAL_BUSY; + return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if ((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if (((uint32_t)pData == 0U) && (Length > 0U)) { return HAL_ERROR; } @@ -400,6 +421,10 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 htim->State = HAL_TIM_STATE_BUSY; } } + else + { + /* nothing to do */ + } /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); @@ -410,13 +435,18 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel for Capture 1*/ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the capture compare 1 Interrupt */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -424,7 +454,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /** * @brief Stops the TIM Hall Sensor Interface in DMA mode. - * @param htim TIM handle + * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) @@ -490,11 +520,14 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Ouput */ + /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -519,7 +552,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ @@ -551,32 +584,26 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; } - break; - case TIM_CHANNEL_4: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; default: - break; + break; } /* Enable the TIM Break interrupt */ @@ -585,11 +612,14 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Ouput */ + /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -608,8 +638,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { - uint32_t tmpccer = 0; - + uint32_t tmpccer; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -619,32 +648,25 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; default: - break; + break; } /* Disable the Capture compare channel N */ @@ -652,12 +674,12 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ @@ -685,13 +707,13 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if ((htim->State == HAL_TIM_STATE_BUSY)) { - return HAL_BUSY; + return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if ((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if (((uint32_t)pData == 0U) && (Length > 0U)) { return HAL_ERROR; } @@ -700,6 +722,11 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan htim->State = HAL_TIM_STATE_BUSY; } } + else + { + /* nothing to do */ + } + switch (Channel) { case TIM_CHANNEL_1: @@ -711,12 +738,14 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; } - break; case TIM_CHANNEL_2: { @@ -727,15 +756,17 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; } - break; case TIM_CHANNEL_3: -{ + { /* Set the DMA Period elapsed callback */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; @@ -743,41 +774,30 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; default: - break; + break; } /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Ouput */ + /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -805,38 +825,31 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + break; } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; default: - break; + break; } /* Disable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ @@ -901,11 +914,14 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Ouput */ + /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -929,7 +945,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ @@ -961,32 +977,25 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; default: - break; + break; } /* Enable the TIM Break interrupt */ @@ -995,11 +1004,14 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Ouput */ + /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -1016,9 +1028,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { - uint32_t tmpccer = 0; + uint32_t tmpccer; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -1029,46 +1041,38 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; default: - break; + break; } /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ @@ -1096,13 +1100,13 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if ((htim->State == HAL_TIM_STATE_BUSY)) { - return HAL_BUSY; + return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if ((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if (((uint32_t)pData == 0U) && (Length > 0U)) { return HAL_ERROR; } @@ -1111,6 +1115,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha htim->State = HAL_TIM_STATE_BUSY; } } + else + { + /* nothing to do */ + } switch (Channel) { case TIM_CHANNEL_1: @@ -1122,12 +1130,14 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; } - break; case TIM_CHANNEL_2: { @@ -1138,12 +1148,14 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; } - break; case TIM_CHANNEL_3: { @@ -1154,41 +1166,30 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; default: - break; + break; } /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Ouput */ + /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -1216,38 +1217,31 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + break; } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; default: - break; + break; } /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ @@ -1293,14 +1287,14 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) - { +{ /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Enable the complementary One Pulse output */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - /* Enable the Main Ouput */ + /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Return function status */ @@ -1326,7 +1320,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /* Disable the complementary One Pulse output */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ @@ -1360,7 +1354,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t /* Enable the complementary One Pulse output */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - /* Enable the Main Ouput */ + /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Return function status */ @@ -1391,7 +1385,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t /* Disable the complementary One Pulse output */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ @@ -1414,13 +1408,13 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t ============================================================================== [..] This section provides functions allowing to: - (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure the commutation event in case of use of the Hall sensor interface. (+) Configure Output channels for OC and PWM mode. (+) Configure Complementary channels, break features and dead time. (+) Configure Master synchronization. (+) Configure timer remapping capabilities. - (+) Enable or disable channel grouping + (+) Enable or disable channel grouping. @endverbatim * @{ @@ -1595,7 +1589,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef * sMasterConfig) + TIM_MasterConfigTypeDef *sMasterConfig) { uint32_t tmpcr2; uint32_t tmpsmcr; @@ -1608,7 +1602,10 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /* Check input state */ __HAL_LOCK(htim); - /* Get the TIMx CR2 register value */ + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; /* Get the TIMx SMCR register value */ @@ -1642,13 +1639,16 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); return HAL_OK; } /** - * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State * and the AOE(automatic output enable). * @param htim TIM handle * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that @@ -1656,9 +1656,10 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig) + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { - uint32_t tmpbdtr = 0; + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t tmpbdtr = 0U; /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); @@ -1685,8 +1686,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); - MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) { @@ -1696,7 +1696,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); /* Set the BREAK2 input related BDTR bits */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); } @@ -1724,142 +1724,116 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) { - uint32_t tmporx = 0; - uint32_t bkin_enable_mask = 0; - uint32_t bkin_polarity_mask = 0; - uint32_t bkin_enable_bitpos = 0; - uint32_t bkin_polarity_bitpos = 0; + uint32_t tmporx; + uint32_t bkin_enable_mask = 0U; + uint32_t bkin_polarity_mask = 0U; + uint32_t bkin_enable_bitpos = 0U; + uint32_t bkin_polarity_bitpos = 0U; /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_BREAKINPUT(BreakInput)); assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); - -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#if defined(DFSDM1_Channel0) if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) { assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); } #else - assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); +#endif /* DFSDM1_Channel0 */ /* Check input state */ __HAL_LOCK(htim); - switch(sBreakInputConfig->Source) + switch (sBreakInputConfig->Source) { - case TIM_BREAKINPUTSOURCE_BKIN: + case TIM_BREAKINPUTSOURCE_BKIN: { bkin_enable_mask = TIM1_OR2_BKINE; - bkin_enable_bitpos = 0; + bkin_enable_bitpos = TIM1_OR2_BKINE_Pos; bkin_polarity_mask = TIM1_OR2_BKINP; - bkin_polarity_bitpos = 9; + bkin_polarity_bitpos = TIM1_OR2_BKINP_Pos; + break; } - break; - case TIM_BREAKINPUTSOURCE_COMP1: + case TIM_BREAKINPUTSOURCE_COMP1: { bkin_enable_mask = TIM1_OR2_BKCMP1E; - bkin_enable_bitpos = 1; + bkin_enable_bitpos = TIM1_OR2_BKCMP1E_Pos; bkin_polarity_mask = TIM1_OR2_BKCMP1P; - bkin_polarity_bitpos = 10; + bkin_polarity_bitpos = TIM1_OR2_BKCMP1P_Pos; + break; } - break; - case TIM_BREAKINPUTSOURCE_COMP2: + case TIM_BREAKINPUTSOURCE_COMP2: { bkin_enable_mask = TIM1_OR2_BKCMP2E; - bkin_enable_bitpos = 2; + bkin_enable_bitpos = TIM1_OR2_BKCMP2E_Pos; bkin_polarity_mask = TIM1_OR2_BKCMP2P; - bkin_polarity_bitpos = 11; + bkin_polarity_bitpos = TIM1_OR2_BKCMP2P_Pos; + break; } - break; - -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - case TIM_BREAKINPUTSOURCE_DFSDM1: +#if defined(DFSDM1_Channel0) + case TIM_BREAKINPUTSOURCE_DFSDM1: { bkin_enable_mask = TIM1_OR2_BKDF1BK0E; - bkin_enable_bitpos = 8; + bkin_enable_bitpos = 8U; + break; } - break; -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - - default: - break; +#endif /* DFSDM1_Channel0 */ + + default: + break; } - switch(BreakInput) + switch (BreakInput) { case TIM_BREAKINPUT_BRK: + { + /* Get the TIMx_OR2 register value */ + tmporx = htim->Instance->OR2; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ +#if defined(DFSDM1_Channel0) + if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) +#endif /* DFSDM1_Channel0 */ { - /* Get the TIMx_OR2 register value */ - tmporx = htim->Instance->OR2; - - /* Enable the break input */ - tmporx &= ~bkin_enable_mask; - tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; - - /* Set the break input polarity */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - { - tmporx &= ~bkin_polarity_mask; - tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; - } - - /* Set TIMx_OR2 */ - htim->Instance->OR2 = tmporx; + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; } - break; + + /* Set TIMx_OR2 */ + htim->Instance->OR2 = tmporx; + break; + } case TIM_BREAKINPUT_BRK2: + { + /* Get the TIMx_OR3 register value */ + tmporx = htim->Instance->OR3; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ +#if defined(DFSDM1_Channel0) + if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) +#endif /* DFSDM1_Channel0 */ { - /* Get the TIMx_OR3 register value */ - tmporx = htim->Instance->OR3; - - /* Enable the break input */ - tmporx &= ~bkin_enable_mask; - tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; - - /* Set the break input polarity */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - { - tmporx &= ~bkin_polarity_mask; - tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; - } - - /* Set TIMx_OR3 */ - htim->Instance->OR3 = tmporx; + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; } + + /* Set TIMx_OR3 */ + htim->Instance->OR3 = tmporx; + break; + } + default: break; - default: - break; } __HAL_UNLOCK(htim); @@ -1870,8 +1844,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, /** * @brief Configures the TIMx Remapping input capabilities. * @param htim TIM handle. - * @param Remap: specifies the TIM remapping source. - * + * @param Remap specifies the TIM remapping source. @if STM32L486xx * For TIM1, the parameter is a combination of 4 fields (field1 | field2 | field3 | field4): * @@ -2036,8 +2009,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, */ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) { - uint32_t tmpor1 = 0; - uint32_t tmpor2 = 0; + uint32_t tmpor1 = 0U; + uint32_t tmpor2 = 0U; __HAL_LOCK(htim); @@ -2049,8 +2022,8 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) if (IS_TIM_ETRSEL_INSTANCE(htim->Instance)) { tmpor2 = htim->Instance->OR2; - tmpor2 &= ~TIMx_ETRSEL_MASK; - tmpor2 |= (Remap & TIMx_ETRSEL_MASK); + tmpor2 &= ~TIM1_OR2_ETRSEL_Msk; + tmpor2 |= (Remap & TIM1_OR2_ETRSEL_Msk); /* Set TIMx_OR2 */ htim->Instance->OR2 = tmpor2; @@ -2058,13 +2031,11 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) /* Set other remapping capabilities */ tmpor1 = Remap; - tmpor1 &= ~TIMx_ETRSEL_MASK; + tmpor1 &= ~TIM1_OR2_ETRSEL_Msk; /* Set TIMx_OR1 */ htim->Instance->OR1 = tmpor1; - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); return HAL_OK; @@ -2093,11 +2064,12 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Chan htim->State = HAL_TIM_STATE_BUSY; /* Clear GC5Cx bit fields */ - htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1); + htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); /* Set GC5Cx bit fields */ htim->Instance->CCR5 |= Channels; + /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); @@ -2155,6 +2127,20 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) */ } +/** + * @brief Hall Break2 detection callback in non blocking mode + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_Break2Callback could be implemented in the user file + */ +} /** * @} */ @@ -2188,6 +2174,15 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) * @} */ +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIMEx Private Functions + * @{ + */ + /** * @brief TIM DMA Commutation callback. * @param hdma pointer to DMA handle. @@ -2195,11 +2190,16 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) { - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State= HAL_TIM_STATE_READY; + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else HAL_TIMEx_CommutationCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** @@ -2207,26 +2207,25 @@ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 * @param ChannelNState specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None */ -static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState) +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) { - uint32_t tmp = 0; + uint32_t tmp; - tmp = TIM_CCER_CC1NE << Channel; + tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ /* Reset the CCxNE Bit */ TIMx->CCER &= ~tmp; /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint32_t)(ChannelNState << Channel); + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ } - /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tsc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tsc.c index 38d0ee295f..b1b72651ac 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tsc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tsc.c @@ -2,46 +2,45 @@ ****************************************************************************** * @file stm32l4xx_hal_tsc.c * @author MCD Application Team - * @brief This file provides firmware functions to manage the following + * @brief This file provides firmware functions to manage the following * functionalities of the Touch Sensing Controller (TSC) peripheral: * + Initialization and De-initialization * + Channel IOs, Shield IOs and Sampling IOs configuration * + Start and Stop an acquisition * + Read acquisition result * + Interrupts and flags management - * + * @verbatim ================================================================================ ##### TSC specific features ##### ================================================================================ [..] (#) Proven and robust surface charge transfer acquisition principle - + (#) Supports up to 3 capacitive sensing channels per group - + (#) Capacitive sensing channels can be acquired in parallel offering a very good response time - + (#) Spread spectrum feature to improve system robustness in noisy environments - + (#) Full hardware management of the charge transfer acquisition sequence - + (#) Programmable charge transfer frequency - + (#) Programmable sampling capacitor I/O pin - + (#) Programmable channel I/O pin - + (#) Programmable max count value to avoid long acquisition when a channel is faulty - + (#) Dedicated end of acquisition and max count error flags with interrupt capability - + (#) One sampling capacitor for up to 3 capacitive sensing channels to reduce the system components - + (#) Compatible with proximity, touchkey, linear and rotary touch sensor implementation - ##### How to use this driver ##### ================================================================================ [..] @@ -54,14 +53,14 @@ using HAL_GPIO_Init() function. (#) Interrupts configuration - (++) Configure the NVIC (if the interrupt model is used) using HAL_NVIC_SetPriority() + (++) Configure the NVIC (if the interrupt model is used) using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() and function. (#) TSC configuration (++) Configure all TSC parameters and used TSC IOs using HAL_TSC_Init() function. [..] TSC peripheral alternate functions are mapped on AF9. - + *** Acquisition sequence *** =================================== [..] @@ -76,56 +75,102 @@ HAL_TSC_GetState() function or using WFI instruction for example. (+) Check the group acquisition status using HAL_TSC_GroupGetStatus() function. (+) Read the acquisition value using HAL_TSC_GroupGetValue() function. - + + *** Callback registration *** + ============================================= + + The compilation flag USE_HAL_TSC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_TSC_RegisterCallback() to register an interrupt callback. + + Function @ref HAL_TSC_RegisterCallback() allows to register following callbacks: + (+) ConvCpltCallback : callback for conversion complete process. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_TSC_UnRegisterCallback to reset a callback to the default + weak function. + @ref HAL_TSC_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) ConvCpltCallback : callback for conversion complete process. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + + By default, after the @ref HAL_TSC_Init() and when the state is @ref HAL_TSC_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_TSC_ConvCpltCallback(), @ref HAL_TSC_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the @ref HAL_TSC_Init()/ @ref HAL_TSC_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the @ref HAL_TSC_Init()/ @ref HAL_TSC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + Callbacks can be registered/unregistered in @ref HAL_TSC_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in @ref HAL_TSC_STATE_READY or @ref HAL_TSC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_TSC_RegisterCallback() before calling @ref HAL_TSC_DeInit() + or @ref HAL_TSC_Init() function. + + When the compilation flag USE_HAL_TSC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + @endverbatim ****************************************************************************** Table 1. IOs for the STM32L4xx devices - +--------------------------------+ - | IOs | TSC functions | + +--------------------------------+ + | IOs | TSC functions | |--------------|-----------------| - | PB12 (AF) | TSC_G1_IO1 | - | PB13 (AF) | TSC_G1_IO2 | - | PB14 (AF) | TSC_G1_IO3 | - | PB15 (AF) | TSC_G1_IO4 | + | PB12 (AF) | TSC_G1_IO1 | + | PB13 (AF) | TSC_G1_IO2 | + | PB14 (AF) | TSC_G1_IO3 | + | PB15 (AF) | TSC_G1_IO4 | |--------------|-----------------| - | PB4 (AF) | TSC_G2_IO1 | - | PB5 (AF) | TSC_G2_IO2 | - | PB6 (AF) | TSC_G2_IO3 | - | PB7 (AF) | TSC_G2_IO4 | + | PB4 (AF) | TSC_G2_IO1 | + | PB5 (AF) | TSC_G2_IO2 | + | PB6 (AF) | TSC_G2_IO3 | + | PB7 (AF) | TSC_G2_IO4 | |--------------|-----------------| - | PA15 (AF) | TSC_G3_IO1 | - | PC10 (AF) | TSC_G3_IO2 | - | PC11 (AF) | TSC_G3_IO3 | - | PC12 (AF) | TSC_G3_IO4 | + | PA15 (AF) | TSC_G3_IO1 | + | PC10 (AF) | TSC_G3_IO2 | + | PC11 (AF) | TSC_G3_IO3 | + | PC12 (AF) | TSC_G3_IO4 | |--------------|-----------------| - | PC6 (AF) | TSC_G4_IO1 | - | PC7 (AF) | TSC_G4_IO2 | - | PC8 (AF) | TSC_G4_IO3 | - | PC9 (AF) | TSC_G4_IO4 | + | PC6 (AF) | TSC_G4_IO1 | + | PC7 (AF) | TSC_G4_IO2 | + | PC8 (AF) | TSC_G4_IO3 | + | PC9 (AF) | TSC_G4_IO4 | |--------------|-----------------| - | PE10 (AF) | TSC_G5_IO1 | - | PE11 (AF) | TSC_G5_IO2 | - | PE12 (AF) | TSC_G5_IO3 | - | PE13 (AF) | TSC_G5_IO4 | + | PE10 (AF) | TSC_G5_IO1 | + | PE11 (AF) | TSC_G5_IO2 | + | PE12 (AF) | TSC_G5_IO3 | + | PE13 (AF) | TSC_G5_IO4 | |--------------|-----------------| - | PD10 (AF) | TSC_G6_IO1 | - | PD11 (AF) | TSC_G6_IO2 | - | PD12 (AF) | TSC_G6_IO3 | - | PD13 (AF) | TSC_G6_IO4 | + | PD10 (AF) | TSC_G6_IO1 | + | PD11 (AF) | TSC_G6_IO2 | + | PD12 (AF) | TSC_G6_IO3 | + | PD13 (AF) | TSC_G6_IO4 | |--------------|-----------------| - | PE2 (AF) | TSC_G7_IO1 | - | PE3 (AF) | TSC_G7_IO2 | - | PE4 (AF) | TSC_G7_IO3 | - | PE5 (AF) | TSC_G7_IO4 | + | PE2 (AF) | TSC_G7_IO1 | + | PE3 (AF) | TSC_G7_IO2 | + | PE4 (AF) | TSC_G7_IO3 | + | PE5 (AF) | TSC_G7_IO4 | |--------------|-----------------| - | PF14 (AF) | TSC_G8_IO1 | - | PF15 (AF) | TSC_G8_IO2 | - | PG0 (AF) | TSC_G8_IO3 | - | PG1 (AF) | TSC_G8_IO4 | + | PF14 (AF) | TSC_G8_IO1 | + | PF15 (AF) | TSC_G8_IO2 | + | PG0 (AF) | TSC_G8_IO3 | + | PG1 (AF) | TSC_G8_IO4 | |--------------|-----------------| - | PB10 (AF) | TSC_SYNC | - | PD2 (AF) | | + | PB10 (AF) | TSC_SYNC | + | PD2 (AF) | | +--------------------------------+ ****************************************************************************** @@ -171,7 +216,7 @@ */ #ifdef HAL_TSC_MODULE_ENABLED - + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -183,12 +228,12 @@ static uint32_t TSC_extract_groups(uint32_t iomask); /** @defgroup TSC_Exported_Functions Exported Functions * @{ - */ + */ /** @defgroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== @@ -200,12 +245,12 @@ static uint32_t TSC_extract_groups(uint32_t iomask); */ /** - * @brief Initialize the TSC peripheral according to the specified parameters + * @brief Initialize the TSC peripheral according to the specified parameters * in the TSC_InitTypeDef structure and initialize the associated handle. - * @param htsc: TSC handle + * @param htsc TSC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc) +HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc) { /* Check TSC handle allocation */ if (htsc == NULL) @@ -226,29 +271,46 @@ HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc) assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity)); assert_param(IS_TSC_ACQ_MODE(htsc->Init.AcquisitionMode)); assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt)); + assert_param(IS_TSC_GROUP(htsc->Init.ChannelIOs)); + assert_param(IS_TSC_GROUP(htsc->Init.ShieldIOs)); + assert_param(IS_TSC_GROUP(htsc->Init.SamplingIOs)); - if(htsc->State == HAL_TSC_STATE_RESET) + if (htsc->State == HAL_TSC_STATE_RESET) { /* Allocate lock resource and initialize it */ htsc->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) + /* Init the TSC Callback settings */ + htsc->ConvCpltCallback = HAL_TSC_ConvCpltCallback; /* Legacy weak ConvCpltCallback */ + htsc->ErrorCallback = HAL_TSC_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (htsc->MspInitCallback == NULL) + { + htsc->MspInitCallback = HAL_TSC_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + htsc->MspInitCallback(htsc); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + HAL_TSC_MspInit(htsc); +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ } /* Initialize the TSC state */ htsc->State = HAL_TSC_STATE_BUSY; - /* Init the low level hardware : GPIO, CLOCK, CORTEX */ - HAL_TSC_MspInit(htsc); - - /*--------------------------------------------------------------------------*/ + /*--------------------------------------------------------------------------*/ /* Set TSC parameters */ /* Enable TSC */ htsc->Instance->CR = TSC_CR_TSCE; - + /* Set all functions */ htsc->Instance->CR |= (htsc->Init.CTPulseHighLength | htsc->Init.CTPulseLowLength | - (uint32_t)(htsc->Init.SpreadSpectrumDeviation << 17) | + (uint32_t)(htsc->Init.SpreadSpectrumDeviation << TSC_CR_SSD_Pos) | htsc->Init.SpreadSpectrumPrescaler | htsc->Init.PulseGeneratorPrescaler | htsc->Init.MaxCountValue | @@ -260,40 +322,40 @@ HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc) { htsc->Instance->CR |= TSC_CR_SSE; } - + /* Disable Schmitt trigger hysteresis on all used TSC IOs */ htsc->Instance->IOHCR = (uint32_t)(~(htsc->Init.ChannelIOs | htsc->Init.ShieldIOs | htsc->Init.SamplingIOs)); /* Set channel and shield IOs */ htsc->Instance->IOCCR = (htsc->Init.ChannelIOs | htsc->Init.ShieldIOs); - + /* Set sampling IOs */ htsc->Instance->IOSCR = htsc->Init.SamplingIOs; - + /* Set the groups to be acquired */ htsc->Instance->IOGCSR = TSC_extract_groups(htsc->Init.ChannelIOs); - + /* Disable interrupts */ htsc->Instance->IER &= (uint32_t)(~(TSC_IT_EOA | TSC_IT_MCE)); - + /* Clear flags */ htsc->Instance->ICR = (TSC_FLAG_EOA | TSC_FLAG_MCE); /*--------------------------------------------------------------------------*/ - + /* Initialize the TSC state */ htsc->State = HAL_TSC_STATE_READY; - + /* Return function status */ return HAL_OK; } /** * @brief Deinitialize the TSC peripheral registers to their default reset values. - * @param htsc: TSC handle + * @param htsc TSC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc) +HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc) { /* Check TSC handle allocation */ if (htsc == NULL) @@ -303,13 +365,23 @@ HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc) /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); - + /* Change TSC state */ htsc->State = HAL_TSC_STATE_BUSY; - + +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) + if (htsc->MspDeInitCallback == NULL) + { + htsc->MspDeInitCallback = HAL_TSC_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + htsc->MspDeInitCallback(htsc); +#else /* DeInit the low level hardware */ HAL_TSC_MspDeInit(htsc); - +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ + /* Change TSC state */ htsc->State = HAL_TSC_STATE_RESET; @@ -322,47 +394,227 @@ HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc) /** * @brief Initialize the TSC MSP. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains - * the configuration information for the specified TSC. + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. * @retval None */ -__weak void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc) +__weak void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc) { /* Prevent unused argument(s) compilation warning */ UNUSED(htsc); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TSC_MspInit could be implemented in the user file. - */ + */ } /** * @brief DeInitialize the TSC MSP. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains - * the configuration information for the specified TSC. + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. * @retval None */ -__weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc) +__weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc) { /* Prevent unused argument(s) compilation warning */ UNUSED(htsc); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TSC_MspDeInit could be implemented in the user file. - */ + */ } +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TSC Callback + * To be used instead of the weak predefined callback + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TSC_CONV_COMPLETE_CB_ID Conversion completed callback ID + * @arg @ref HAL_TSC_ERROR_CB_ID Error callback ID + * @arg @ref HAL_TSC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_TSC_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, pTSC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(htsc); + + if (HAL_TSC_STATE_READY == htsc->State) + { + switch (CallbackID) + { + case HAL_TSC_CONV_COMPLETE_CB_ID : + htsc->ConvCpltCallback = pCallback; + break; + + case HAL_TSC_ERROR_CB_ID : + htsc->ErrorCallback = pCallback; + break; + + case HAL_TSC_MSPINIT_CB_ID : + htsc->MspInitCallback = pCallback; + break; + + case HAL_TSC_MSPDEINIT_CB_ID : + htsc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_TSC_STATE_RESET == htsc->State) + { + switch (CallbackID) + { + case HAL_TSC_MSPINIT_CB_ID : + htsc->MspInitCallback = pCallback; + break; + + case HAL_TSC_MSPDEINIT_CB_ID : + htsc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htsc); + return status; +} + +/** + * @brief Unregister an TSC Callback + * TSC callback is redirected to the weak predefined callback + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_TSC_CONV_COMPLETE_CB_ID Conversion completed callback ID + * @arg @ref HAL_TSC_ERROR_CB_ID Error callback ID + * @arg @ref HAL_TSC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_TSC_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(htsc); + + if (HAL_TSC_STATE_READY == htsc->State) + { + switch (CallbackID) + { + case HAL_TSC_CONV_COMPLETE_CB_ID : + htsc->ConvCpltCallback = HAL_TSC_ConvCpltCallback; /* Legacy weak ConvCpltCallback */ + break; + + case HAL_TSC_ERROR_CB_ID : + htsc->ErrorCallback = HAL_TSC_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_TSC_MSPINIT_CB_ID : + htsc->MspInitCallback = HAL_TSC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_TSC_MSPDEINIT_CB_ID : + htsc->MspDeInitCallback = HAL_TSC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_TSC_STATE_RESET == htsc->State) + { + switch (CallbackID) + { + case HAL_TSC_MSPINIT_CB_ID : + htsc->MspInitCallback = HAL_TSC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_TSC_MSPDEINIT_CB_ID : + htsc->MspDeInitCallback = HAL_TSC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htsc); + return status; +} + +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ + /** * @} */ /** @defgroup TSC_Exported_Functions_Group2 Input and Output operation functions - * @brief Input and Output operation functions + * @brief Input and Output operation functions * -@verbatim +@verbatim =============================================================================== ##### IO Operation functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Start acquisition in polling mode. (+) Start acquisition in interrupt mode. @@ -377,18 +629,18 @@ __weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc) /** * @brief Start the acquisition. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL status */ -HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc) +HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); - + /* Process locked */ __HAL_LOCK(htsc); - + /* Change TSC state */ htsc->State = HAL_TSC_STATE_BUSY; @@ -407,24 +659,24 @@ HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc) { __HAL_TSC_SET_IODEF_INFLOAT(htsc); } - + /* Launch the acquisition */ __HAL_TSC_START_ACQ(htsc); - + /* Process unlocked */ __HAL_UNLOCK(htsc); - + /* Return function status */ return HAL_OK; } /** * @brief Start the acquisition in interrupt mode. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL status. */ -HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc) +HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); @@ -432,10 +684,10 @@ HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc) /* Process locked */ __HAL_LOCK(htsc); - + /* Change TSC state */ htsc->State = HAL_TSC_STATE_BUSY; - + /* Enable end of acquisition interrupt */ __HAL_TSC_ENABLE_IT(htsc, TSC_IT_EOA); @@ -451,7 +703,7 @@ HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc) /* Clear flags */ __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE)); - + /* Set touch sensing IOs not acquired to the specified IODefaultMode */ if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW) { @@ -461,82 +713,82 @@ HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc) { __HAL_TSC_SET_IODEF_INFLOAT(htsc); } - + /* Launch the acquisition */ __HAL_TSC_START_ACQ(htsc); /* Process unlocked */ __HAL_UNLOCK(htsc); - + /* Return function status */ return HAL_OK; } /** * @brief Stop the acquisition previously launched in polling mode. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL status */ -HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc) +HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); /* Process locked */ __HAL_LOCK(htsc); - + /* Stop the acquisition */ __HAL_TSC_STOP_ACQ(htsc); /* Set touch sensing IOs in low power mode (output push-pull) */ __HAL_TSC_SET_IODEF_OUTPPLOW(htsc); - + /* Clear flags */ __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE)); - + /* Change TSC state */ htsc->State = HAL_TSC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(htsc); - + /* Return function status */ return HAL_OK; } /** * @brief Stop the acquisition previously launched in interrupt mode. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL status */ -HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc) +HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); /* Process locked */ __HAL_LOCK(htsc); - + /* Stop the acquisition */ __HAL_TSC_STOP_ACQ(htsc); - + /* Set touch sensing IOs in low power mode (output push-pull) */ __HAL_TSC_SET_IODEF_OUTPPLOW(htsc); - + /* Disable interrupts */ __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE)); /* Clear flags */ __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE)); - + /* Change TSC state */ htsc->State = HAL_TSC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(htsc); - + /* Return function status */ return HAL_OK; } @@ -545,18 +797,18 @@ HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc) * @brief Start acquisition and wait until completion. * @note There is no need of a timeout parameter as the max count error is already * managed by the TSC peripheral. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL state */ -HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc) +HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); /* Process locked */ __HAL_LOCK(htsc); - + /* Check end of acquisition */ while (HAL_TSC_GetState(htsc) == HAL_TSC_STATE_BUSY) { @@ -565,55 +817,55 @@ HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc) /* Process unlocked */ __HAL_UNLOCK(htsc); - + return HAL_OK; } /** * @brief Get the acquisition status for a group. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. - * @param gx_index: Index of the group + * @param gx_index Index of the group * @retval Group status */ -TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index) +TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); assert_param(IS_TSC_GROUP_INDEX(gx_index)); - /* Return the group status */ - return(__HAL_TSC_GET_GROUP_STATUS(htsc, gx_index)); + /* Return the group status */ + return (__HAL_TSC_GET_GROUP_STATUS(htsc, gx_index)); } /** * @brief Get the acquisition measure for a group. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. - * @param gx_index: Index of the group + * @param gx_index Index of the group * @retval Acquisition measure */ -uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index) -{ +uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index) +{ /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); assert_param(IS_TSC_GROUP_INDEX(gx_index)); - /* Return the group acquisition counter */ + /* Return the group acquisition counter */ return htsc->Instance->IOGXCR[gx_index]; } /** * @} */ - + /** @defgroup TSC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions + * @brief Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Configure TSC IOs (+) Discharge TSC IOs @@ -623,16 +875,19 @@ uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index) /** * @brief Configure TSC IOs. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. - * @param config: pointer to the configuration structure. + * @param config Pointer to the configuration structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config) +HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); - + assert_param(IS_TSC_GROUP(config->ChannelIOs)); + assert_param(IS_TSC_GROUP(config->ShieldIOs)); + assert_param(IS_TSC_GROUP(config->SamplingIOs)); + /* Process locked */ __HAL_LOCK(htsc); @@ -644,35 +899,35 @@ HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* /* Set channel and shield IOs */ htsc->Instance->IOCCR = (config->ChannelIOs | config->ShieldIOs); - + /* Set sampling IOs */ htsc->Instance->IOSCR = config->SamplingIOs; - + /* Set groups to be acquired */ htsc->Instance->IOGCSR = TSC_extract_groups(config->ChannelIOs); - + /* Process unlocked */ __HAL_UNLOCK(htsc); - + /* Return function status */ return HAL_OK; } /** * @brief Discharge TSC IOs. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. - * @param choice: enable or disable + * @param choice This parameter can be set to ENABLE or DISABLE. * @retval HAL status */ -HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice) -{ +HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, uint32_t choice) +{ /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); /* Process locked */ __HAL_LOCK(htsc); - + if (choice == ENABLE) { __HAL_TSC_SET_IODEF_OUTPPLOW(htsc); @@ -684,8 +939,8 @@ HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice) /* Process unlocked */ __HAL_UNLOCK(htsc); - - /* Return the group acquisition counter */ + + /* Return the group acquisition counter */ return HAL_OK; } @@ -694,31 +949,31 @@ HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice) */ /** @defgroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions + * @brief Peripheral State and Errors functions * -@verbatim +@verbatim =============================================================================== ##### State and Errors functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides functions allowing to (+) Get TSC state. - + @endverbatim * @{ */ /** * @brief Return the TSC handle state. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL state */ -HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc) +HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); - + if (htsc->State == HAL_TSC_STATE_BUSY) { /* Check end of acquisition flag */ @@ -737,7 +992,7 @@ HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc) } } } - + /* Return TSC state */ return htsc->State; } @@ -748,15 +1003,15 @@ HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc) /** @defgroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks * @{ - */ + */ /** * @brief Handle TSC interrupt request. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval None */ -void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc) +void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); @@ -767,7 +1022,7 @@ void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc) /* Clear EOA flag */ __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_EOA); } - + /* Check if max count error occurred */ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET) { @@ -775,25 +1030,33 @@ void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc) __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_MCE); /* Change TSC state */ htsc->State = HAL_TSC_STATE_ERROR; +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) + htsc->ErrorCallback(htsc); +#else /* Conversion completed callback */ HAL_TSC_ErrorCallback(htsc); +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ } else { /* Change TSC state */ htsc->State = HAL_TSC_STATE_READY; +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) + htsc->ConvCpltCallback(htsc); +#else /* Conversion completed callback */ HAL_TSC_ConvCpltCallback(htsc); +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ } } /** * @brief Acquisition completed callback in non-blocking mode. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval None */ -__weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc) +__weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc) { /* Prevent unused argument(s) compilation warning */ UNUSED(htsc); @@ -805,11 +1068,11 @@ __weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc) /** * @brief Error callback in non-blocking mode. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval None */ -__weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc) +__weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc) { /* Prevent unused argument(s) compilation warning */ UNUSED(htsc); @@ -831,25 +1094,25 @@ __weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc) /** @defgroup TSC_Private_Functions Private Functions * @{ */ - + /** * @brief Utility function used to set the acquired groups mask. - * @param iomask: Channels IOs mask + * @param iomask Channels IOs mask * @retval Acquired groups mask */ static uint32_t TSC_extract_groups(uint32_t iomask) { - uint32_t groups = 0; + uint32_t groups = 0U; uint32_t idx; - - for (idx = 0; idx < TSC_NB_OF_GROUPS; idx++) + + for (idx = 0U; idx < TSC_NB_OF_GROUPS; idx++) { - if ((iomask & ((uint32_t)0x0F << (idx * 4))) != RESET) + if ((iomask & (0x0FU << (idx * 4U))) != RESET) { - groups |= ((uint32_t)1 << idx); + groups |= (1U << idx); } } - + return groups; } @@ -861,10 +1124,10 @@ static uint32_t TSC_extract_groups(uint32_t iomask) /** * @} - */ + */ /** * @} - */ + */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c index 00e01ee163..0152c0072c 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c @@ -67,6 +67,77 @@ also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized HAL_UART_MspInit() API. + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_UART_RegisterCallback() to register a user callback. + Function @ref HAL_UART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + + [..] + By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + all callbacks are set to the corresponding weak (surcharged) functions: + examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init() + and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit() + or @ref HAL_UART_Init() function. + + [..] + When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak (surcharged) callbacks are used. + + @endverbatim ****************************************************************************** * @attention @@ -149,6 +220,9 @@ /** @addtogroup UART_Private_Functions * @{ */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart); static void UART_EndRxTransfer(UART_HandleTypeDef *huart); static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); @@ -174,7 +248,6 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart); static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); #endif - /** * @} */ @@ -221,10 +294,10 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); @endverbatim - Depending on the frame length defined by the M1 and M0 bits (7-bit, - 8-bit or 9-bit), the possible UART formats are listed in the + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the following table. - + Table 1. UART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | UART frame | @@ -247,19 +320,19 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); /** * @brief Initialize the UART mode according to the specified - * parameters in the UART_InitTypeDef and initialize the associated handle. + * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { /* Check the UART handle allocation */ - if(huart == NULL) + if (huart == NULL) { return HAL_ERROR; } - - if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + + if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) { /* Check the parameters */ assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); @@ -269,99 +342,123 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } - - if(huart->gState == HAL_UART_STATE_RESET) + + if (huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - + /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } /** * @brief Initialize the half-duplex mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle. + * parameters in the UART_InitTypeDef and creates the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) { /* Check the UART handle allocation */ - if(huart == NULL) + if (huart == NULL) { return HAL_ERROR; } - + /* Check UART instance */ assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); - - if(huart->gState == HAL_UART_STATE_RESET) + + if (huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - + /* In half-duplex mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); - + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -369,7 +466,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /** * @brief Initialize the LIN mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle . + * parameters in the UART_InitTypeDef and creates the associated handle . * @param huart UART handle. * @param BreakDetectLength Specifies the LIN break detection length. * This parameter can be one of the following values: @@ -380,67 +477,79 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) { /* Check the UART handle allocation */ - if(huart == NULL) + if (huart == NULL) { return HAL_ERROR; } - + /* Check the LIN UART instance */ assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); /* Check the Break detection length parameter */ assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); - + /* LIN mode limited to 16-bit oversampling only */ - if(huart->Init.OverSampling == UART_OVERSAMPLING_8) + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) { return HAL_ERROR; } /* LIN mode limited to 8-bit data length */ - if(huart->Init.WordLength != UART_WORDLENGTH_8B) + if (huart->Init.WordLength != UART_WORDLENGTH_8B) { return HAL_ERROR; } - - if(huart->gState == HAL_UART_STATE_RESET) + + if (huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - + /* In LIN mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); - + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); - + /* Set the USART LIN Break detection length. */ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -448,7 +557,7 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe /** * @brief Initialize the multiprocessor mode according to the specified - * parameters in the UART_InitTypeDef and initialize the associated handle. + * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @param Address UART node address (4-, 6-, 7- or 8-bit long). * @param WakeUpMethod Specifies the UART wakeup method. @@ -467,57 +576,69 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) { /* Check the UART handle allocation */ - if(huart == NULL) + if (huart == NULL) { return HAL_ERROR; } - + /* Check the wake up method parameter */ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); - - if(huart->gState == HAL_UART_STATE_RESET) + + if (huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - + /* In multiprocessor mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - + if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) { /* If address mark wake up method is chosen, set the USART address node */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); } - + /* Set the wake up method by setting the WAKE bit in the CR1 register */ MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -531,33 +652,42 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) { /* Check the UART handle allocation */ - if(huart == NULL) + if (huart == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + huart->Instance->CR1 = 0x0U; huart->Instance->CR2 = 0x0U; huart->Instance->CR3 = 0x0U; - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + if (huart->MspDeInitCallback == NULL) + { + huart->MspDeInitCallback = HAL_UART_MspDeInit; + } + /* DeInit the low level hardware */ + huart->MspDeInitCallback(huart); +#else /* DeInit the low level hardware */ HAL_UART_MspDeInit(huart); - +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_RESET; huart->RxState = HAL_UART_STATE_RESET; - + /* Process Unlock */ __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -570,7 +700,7 @@ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_MspInit can be implemented in the user file */ @@ -585,12 +715,284 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_MspDeInit can be implemented in the user file */ } +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User UART Callback + * To be used instead of the weak predefined callback + * @param huart uart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = pCallback; + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = pCallback; + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = pCallback; + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = pCallback; + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = pCallback; + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = pCallback; + break; + +#if defined(USART_CR1_FIFOEN) + case HAL_UART_RX_FIFO_FULL_CB_ID : + huart->RxFifoFullCallback = pCallback; + break; + + case HAL_UART_TX_FIFO_EMPTY_CB_ID : + huart->TxFifoEmptyCallback = pCallback; + break; +#endif + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (huart->gState == HAL_UART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief Unregister an UART Callback + * UART callaback is redirected to the weak predefined callback + * @param huart uart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(huart); + + if (HAL_UART_STATE_READY == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + break; + + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ + break; + +#if defined(USART_CR1_FIFOEN) + case HAL_UART_RX_FIFO_FULL_CB_ID : + huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + break; + + case HAL_UART_TX_FIFO_EMPTY_CB_ID : + huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + break; +#endif + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_UART_STATE_RESET == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + + return status; +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + /** * @} */ @@ -656,7 +1058,7 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side. @@ -674,9 +1076,9 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) /** * @brief Send an amount of data in blocking mode. - * @note When FIFO mode is enabled, writing a data in the TDR register adds one + * @note When FIFO mode is enabled, writing a data in the TDR register adds one * data to the TXFIFO. Write operations to the TDR register are performed - * when TXFNF flag is set. From hardware perspective, TXFNF flag and + * when TXFNF flag is set. From hardware perspective, TXFNF flag and * TXE are mapped on the same bit-field. * @param huart UART handle. * @param pData Pointer to data buffer. @@ -686,38 +1088,38 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; + uint16_t *tmp; uint32_t tickstart = 0U; - + /* Check that a Tx process is not already ongoing */ - if(huart->gState == HAL_UART_STATE_READY) + if (huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - + huart->TxXferSize = Size; huart->TxXferCount = Size; - - while(huart->TxXferCount > 0U) + + while (huart->TxXferCount > 0U) { - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { - tmp = (uint16_t*) pData; + tmp = (uint16_t *) pData; huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); pData += 2U; } @@ -727,18 +1129,18 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u } huart->TxXferCount--; } - - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - + /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } else @@ -749,9 +1151,9 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. - * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO - * is not empty. Read operations from the RDR register are performed when - * RXFNE flag is set. From hardware perspective, RXFNE flag and + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and * RXNE are mapped on the same bit-field. * @param huart UART handle. * @param pData Pointer to data buffer. @@ -761,46 +1163,46 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u */ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; + uint16_t *tmp; uint16_t uhMask; uint32_t tickstart = 0; - + /* Check that a Rx process is not already ongoing */ - if(huart->RxState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - + huart->RxXferSize = Size; huart->RxXferCount = Size; - + /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); uhMask = huart->Mask; - + /* as long as data have to be received */ - while(huart->RxXferCount > 0U) + while (huart->RxXferCount > 0U) { - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { - tmp = (uint16_t*) pData ; + tmp = (uint16_t *) pData ; *tmp = (uint16_t)(huart->Instance->RDR & uhMask); - pData +=2U; + pData += 2U; } else { @@ -808,13 +1210,13 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui } huart->RxXferCount--; } - + /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } else @@ -833,28 +1235,28 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ - if(huart->gState == HAL_UART_STATE_READY) + if (huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - + huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; huart->TxISR = NULL; - + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; - + #if defined(USART_CR1_FIFOEN) /* Configure Tx interrupt processing */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) - { + { /* Set the Tx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { @@ -863,11 +1265,11 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData else { huart->TxISR = UART_TxISR_8BIT_FIFOEN; - } - + } + /* Process Unlocked */ __HAL_UNLOCK(huart); - + /* Enable the TX FIFO threshold interrupt */ SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); } @@ -882,19 +1284,19 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData else { huart->TxISR = UART_TxISR_8BIT; - } - + } + /* Process Unlocked */ __HAL_UNLOCK(huart); - + /* Enable the Transmit Data Register Empty interrupt */ #if defined(USART_CR1_FIFOEN) - SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); #else - SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); + SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); #endif } - + return HAL_OK; } else @@ -913,30 +1315,30 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { /* Check that a Rx process is not already ongoing */ - if(huart->RxState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - + huart->pRxBuffPtr = pData; huart->RxXferSize = Size; huart->RxXferCount = Size; huart->RxISR = NULL; - + /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); - + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; - + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - + #if defined(USART_CR1_FIFOEN) /* Configure Rx interrupt processing*/ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) @@ -950,10 +1352,10 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, { huart->RxISR = UART_RxISR_8BIT_FIFOEN; } - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); @@ -970,18 +1372,18 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, { huart->RxISR = UART_RxISR_8BIT; } - - /* Process Unlocked */ + + /* Process Unlocked */ __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ #if defined(USART_CR1_FIFOEN) SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); #else SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); #endif } - + return HAL_OK; } else @@ -1000,48 +1402,48 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ - if(huart->gState == HAL_UART_STATE_READY) + if (huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - + huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; - + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; - + /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; - + /* Set the UART DMA Half transfer complete callback */ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; - + /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; - + /* Set the DMA abort callback */ huart->hdmatx->XferAbortCallback = NULL; - + /* Enable the UART transmit DMA channel */ HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size); - + /* Clear the TC flag in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + return HAL_OK; } else @@ -1052,60 +1454,60 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /** * @brief Receive an amount of data in DMA mode. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). * @param huart UART handle. * @param pData Pointer to data buffer. * @param Size Amount of data to be received. - * @note When the UART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position). * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { /* Check that a Rx process is not already ongoing */ - if(huart->RxState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - + huart->pRxBuffPtr = pData; huart->RxXferSize = Size; - + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; - + /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; - + /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; - + /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; - + /* Set the DMA abort callback */ huart->hdmarx->XferAbortCallback = NULL; - + /* Enable the DMA channel */ HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size); - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + /* Enable the UART Parity Error Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - + /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + return HAL_OK; } else @@ -1123,7 +1525,7 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) { @@ -1136,14 +1538,14 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - + /* Disable the UART DMA Rx request */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -1156,28 +1558,28 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - - if(huart->gState == HAL_UART_STATE_BUSY_TX) + + if (huart->gState == HAL_UART_STATE_BUSY_TX) { /* Enable the UART DMA Tx request */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); } - if(huart->RxState == HAL_UART_STATE_BUSY_RX) + if (huart->RxState == HAL_UART_STATE_BUSY_RX) { /* Clear the Overrun flag before resuming the Rx transfer */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - + /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - + /* Enable the UART DMA Rx request */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -1190,48 +1592,48 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) { /* The Lock is not implemented on this API to allow the user application to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / - HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: - indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete - interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of the stream and the corresponding call back is executed. */ - + /* Stop UART DMA Tx request if ongoing */ if ((huart->gState == HAL_UART_STATE_BUSY_TX) && (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Abort the UART DMA Tx channel */ - if(huart->hdmatx != NULL) + if (huart->hdmatx != NULL) { HAL_DMA_Abort(huart->hdmatx); } - + UART_EndTxTransfer(huart); } - + /* Stop UART DMA Rx request if ongoing */ if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel */ - if(huart->hdmarx != NULL) + if (huart->hdmarx != NULL) { HAL_DMA_Abort(huart->hdmarx); } - + UART_EndRxTransfer(huart); } - + return HAL_OK; } /** * @brief Abort ongoing transfers (blocking mode). * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable UART Interrupts (Tx and Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1242,53 +1644,55 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) { - /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ #if defined(USART_CR1_FIFOEN) + /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); #else + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +#endif /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ - if(huart->hdmatx != NULL) + if (huart->hdmatx != NULL) { - /* Set the UART DMA Abort callback to Null. + /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmatx->XferAbortCallback = NULL; - + HAL_DMA_Abort(huart->hdmatx); } } - + /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ - if(huart->hdmarx != NULL) + if (huart->hdmarx != NULL) { - /* Set the UART DMA Abort callback to Null. + /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = NULL; - + HAL_DMA_Abort(huart->hdmarx); } } - + /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + #if defined(USART_CR1_FIFOEN) /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) @@ -1296,24 +1700,24 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); } #endif - + /* Discard the received data */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - + /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - + /* Reset Handle ErrorCode to No Error */ huart->ErrorCode = HAL_UART_ERROR_NONE; - + return HAL_OK; } /** * @brief Abort ongoing Transmit transfer (blocking mode). * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable UART Interrupts (Tx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1324,10 +1728,12 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) { - /* Disable TXEIE and TCIE interrupts */ #if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + /* Disable TCIE, TXEIE and TXFTIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); #else + /* Disable TXEIE and TCIE interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); #endif @@ -1335,21 +1741,21 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ - if(huart->hdmatx != NULL) + if (huart->hdmatx != NULL) { - /* Set the UART DMA Abort callback to Null. + /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmatx->XferAbortCallback = NULL; - + HAL_DMA_Abort(huart->hdmatx); } } - + /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - + huart->TxXferCount = 0U; + #if defined(USART_CR1_FIFOEN) /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) @@ -1357,17 +1763,17 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); } #endif - + /* Restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - + return HAL_OK; } /** * @brief Abort ongoing Receive transfer (blocking mode). * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable UART Interrupts (Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1378,49 +1784,51 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) { - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ #if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); #else + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +#endif /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ - if(huart->hdmarx != NULL) + if (huart->hdmarx != NULL) { - /* Set the UART DMA Abort callback to Null. + /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = NULL; - + HAL_DMA_Abort(huart->hdmarx); } } - + /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - + huart->RxXferCount = 0U; + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + /* Discard the received data */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - + /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + return HAL_OK; } /** * @brief Abort ongoing transfers (Interrupt mode). * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable UART Interrupts (Tx and Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1434,23 +1842,24 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) { uint32_t abortcplt = 1U; - - /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + + /* Disable interrupts */ #if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | USART_CR1_TXEIE_TXFNFIE)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); #else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +#endif /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ /* DMA Tx Handle is valid */ - if(huart->hdmatx != NULL) + if (huart->hdmatx != NULL) { /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. Otherwise, set it to NULL */ - if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; } @@ -1460,11 +1869,11 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) } } /* DMA Rx Handle is valid */ - if(huart->hdmarx != NULL) + if (huart->hdmarx != NULL) { /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. Otherwise, set it to NULL */ - if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; } @@ -1473,21 +1882,21 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) huart->hdmarx->XferAbortCallback = NULL; } } - + /* Disable the UART DMA Tx request if enabled */ - if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { /* Disable DMA Tx at UART level */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ - if(huart->hdmatx != NULL) + if (huart->hdmatx != NULL) { - /* UART Tx DMA Abort callback has already been initialised : + /* UART Tx DMA Abort callback has already been initialised : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) { huart->hdmatx->XferAbortCallback = NULL; } @@ -1497,20 +1906,20 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) } } } - + /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ - if(huart->hdmarx != NULL) + if (huart->hdmarx != NULL) { - /* UART Rx DMA Abort callback has already been initialised : + /* UART Rx DMA Abort callback has already been initialised : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) { huart->hdmarx->XferAbortCallback = NULL; abortcplt = 1U; @@ -1521,24 +1930,24 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) } } } - + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ if (abortcplt == 1U) { /* Reset Tx and Rx transfer counters */ huart->TxXferCount = 0U; huart->RxXferCount = 0U; - + /* Clear ISR function pointers */ huart->RxISR = NULL; huart->TxISR = NULL; - + /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + #if defined(USART_CR1_FIFOEN) /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) @@ -1546,25 +1955,31 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); } #endif - + /* Discard the received data */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - + /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - + return HAL_OK; } /** * @brief Abort ongoing Transmit transfer (Interrupt mode). * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable UART Interrupts (Tx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1577,9 +1992,10 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) { - /* Disable TXEIE and TCIE interrupts */ + /* Disable interrupts */ #if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); #else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); #endif @@ -1588,16 +2004,16 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ - if(huart->hdmatx != NULL) + if (huart->hdmatx != NULL) { - /* Set the UART DMA Abort callback : + /* Set the UART DMA Abort callback : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; - + /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) { /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ huart->hdmatx->XferAbortCallback(huart->hdmatx); @@ -1606,23 +2022,29 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) else { /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - + huart->TxXferCount = 0U; + /* Clear TxISR function pointers */ huart->TxISR = NULL; - + /* Restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } else { /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - + huart->TxXferCount = 0U; + /* Clear TxISR function pointers */ huart->TxISR = NULL; @@ -1633,21 +2055,27 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); } #endif - + /* Restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - + return HAL_OK; } /** * @brief Abort ongoing Receive transfer (Interrupt mode). * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable UART Interrupts (Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1662,26 +2090,27 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ #if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); #else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +#endif /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ - if(huart->hdmarx != NULL) + if (huart->hdmarx != NULL) { - /* Set the UART DMA Abort callback : + /* Set the UART DMA Abort callback : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; - + /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) { /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); @@ -1691,41 +2120,53 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) { /* Reset Rx transfer counter */ huart->RxXferCount = 0U; - + /* Clear RxISR function pointer */ huart->pRxBuffPtr = NULL; - + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + /* Discard the received data */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - + /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } else { /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - + huart->RxXferCount = 0U; + /* Clear RxISR function pointer */ huart->pRxBuffPtr = NULL; - + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - + return HAL_OK; } @@ -1740,117 +2181,123 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) uint32_t cr1its = READ_REG(huart->Instance->CR1); uint32_t cr3its = READ_REG(huart->Instance->CR3); uint32_t errorflags; - + /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); if (errorflags == RESET) { /* UART in mode Receiver ---------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) - && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) + if (((isrflags & USART_ISR_RXNE_RXFNE) != RESET) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) + || ((cr3its & USART_CR3_RXFTIE) != RESET))) #else - if(((isrflags & USART_ISR_RXNE) != RESET) - && ((cr1its & USART_CR1_RXNEIE) != RESET)) + if (((isrflags & USART_ISR_RXNE) != RESET) + && ((cr1its & USART_CR1_RXNEIE) != RESET)) #endif { - if (huart->RxISR != NULL) {huart->RxISR(huart);} + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } return; } - } - + } + /* If some errors occur */ #if defined(USART_CR1_FIFOEN) - if( (errorflags != RESET) - && ( (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET) - || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET))) ) + if ((errorflags != RESET) + && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET)))) #else - if( (errorflags != RESET) - && ( ((cr3its & USART_CR3_EIE) != RESET) - || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) ) + if ((errorflags != RESET) + && (((cr3its & USART_CR3_EIE) != RESET) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) #endif { /* UART parity error interrupt occurred -------------------------------------*/ - if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + if (((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); - + huart->ErrorCode |= HAL_UART_ERROR_PE; } - + /* UART frame error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); - + huart->ErrorCode |= HAL_UART_ERROR_FE; } - + /* UART noise error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); - + huart->ErrorCode |= HAL_UART_ERROR_NE; } - + /* UART Over-Run interrupt occurred -----------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if( ((isrflags & USART_ISR_ORE) != RESET) - &&( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) || + if (((isrflags & USART_ISR_ORE) != RESET) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) || ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET))) #else - if( ((isrflags & USART_ISR_ORE) != RESET) - &&( ((cr1its & USART_CR1_RXNEIE) != RESET) || - ((cr3its & USART_CR3_EIE) != RESET))) + if (((isrflags & USART_ISR_ORE) != RESET) + && (((cr1its & USART_CR1_RXNEIE) != RESET) || + ((cr3its & USART_CR3_EIE) != RESET))) #endif { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - + huart->ErrorCode |= HAL_UART_ERROR_ORE; } - + /* Call UART Error Call back function if need be --------------------------*/ - if(huart->ErrorCode != HAL_UART_ERROR_NONE) + if (huart->ErrorCode != HAL_UART_ERROR_NONE) { /* UART in mode Receiver ---------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) - && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) + if (((isrflags & USART_ISR_RXNE_RXFNE) != RESET) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) + || ((cr3its & USART_CR3_RXFTIE) != RESET))) #else - if(((isrflags & USART_ISR_RXNE) != RESET) - && ((cr1its & USART_CR1_RXNEIE) != RESET)) + if (((isrflags & USART_ISR_RXNE) != RESET) + && ((cr1its & USART_CR1_RXNEIE) != RESET)) #endif { - if (huart->RxISR != NULL) {huart->RxISR(huart);} + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } } - + /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ + consider error as blocking */ if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) { /* Blocking error : transfer is aborted - Set the UART state ready to be able to start again the process, - Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); - + /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel */ - if(huart->hdmarx != NULL) + if (huart->hdmarx != NULL) { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; - + /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) { /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); @@ -1859,71 +2306,112 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) else { /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } } else { /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } else { - /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; } } return; - + } /* End if some error occurs */ - + /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ - if(((isrflags & USART_ISR_WUF) != RESET) && ((cr3its & USART_CR3_WUFIE) != RESET)) + if (((isrflags & USART_ISR_WUF) != RESET) && ((cr3its & USART_CR3_WUFIE) != RESET)) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); - /* Set the UART state ready to be able to start again the process */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; + + /* UART Rx state is not reset as a reception process might be ongoing. + If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Wakeup Callback */ + huart->WakeupCallback(huart); +#else + /* Call legacy weak Wakeup Callback */ HAL_UARTEx_WakeupCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; } - + /* UART in mode Transmitter ------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_TXE_TXFNF) != RESET) - && ( ((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET) - || ((cr3its & USART_CR3_TXFTIE) != RESET)) ) + if (((isrflags & USART_ISR_TXE_TXFNF) != RESET) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET) + || ((cr3its & USART_CR3_TXFTIE) != RESET))) #else - if(((isrflags & USART_ISR_TXE) != RESET) - && ((cr1its & USART_CR1_TXEIE) != RESET)) + if (((isrflags & USART_ISR_TXE) != RESET) + && ((cr1its & USART_CR1_TXEIE) != RESET)) #endif { - if (huart->TxISR != NULL) {huart->TxISR(huart);} + if (huart->TxISR != NULL) + { + huart->TxISR(huart); + } return; } - + /* UART in mode Transmitter (transmission end) -----------------------------*/ - if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) + if (((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) { UART_EndTransmit_IT(huart); return; } - + #if defined(USART_CR1_FIFOEN) /* UART TX Fifo Empty occurred ----------------------------------------------*/ - if(((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET)) + if (((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET)) { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + huart->TxFifoEmptyCallback(huart); +#else + /* Call legacy weak Tx Fifo Empty Callback */ HAL_UARTEx_TxFifoEmptyCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; } - + /* UART RX Fifo Full occurred ----------------------------------------------*/ - if(((isrflags & USART_ISR_RXFF) != RESET) && ((cr1its & USART_CR1_RXFFIE) != RESET)) + if (((isrflags & USART_ISR_RXFF) != RESET) && ((cr1its & USART_CR1_RXFFIE) != RESET)) { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + huart->RxFifoFullCallback(huart); +#else + /* Call legacy weak Rx Fifo Full Callback */ HAL_UARTEx_RxFifoFullCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; } #endif @@ -1953,7 +2441,7 @@ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback can be implemented in the user file. */ @@ -1968,7 +2456,7 @@ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback can be implemented in the user file. */ @@ -1983,7 +2471,7 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback can be implemented in the user file. */ @@ -2009,7 +2497,7 @@ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) * @param huart UART handle. * @retval None */ -__weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart) +__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); @@ -2024,7 +2512,7 @@ __weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart) * @param huart UART handle. * @retval None */ -__weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart) +__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); @@ -2039,7 +2527,7 @@ __weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart) * @param huart UART handle. * @retval None */ -__weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart) +__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); @@ -2087,14 +2575,14 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Enable USART mute mode by setting the MME bit in the CR1 register */ SET_BIT(huart->Instance->CR1, USART_CR1_MME); - + huart->gState = HAL_UART_STATE_READY; - + return (UART_CheckIdleState(huart)); } @@ -2108,14 +2596,14 @@ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable USART mute mode by clearing the MME bit in the CR1 register */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); - + huart->gState = HAL_UART_STATE_READY; - + return (UART_CheckIdleState(huart)); } @@ -2140,18 +2628,18 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; - + /* Clear TE and RE bits */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); - + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ SET_BIT(huart->Instance->CR1, USART_CR1_TE); - + huart->gState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -2165,18 +2653,18 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; - + /* Clear TE and RE bits */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); - + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ SET_BIT(huart->Instance->CR1, USART_CR1_RE); - + huart->gState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -2190,20 +2678,20 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) { /* Check the parameters */ assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); - + /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Send break characters */ SET_BIT(huart->Instance->RQR, UART_SENDBREAK_REQUEST); - + huart->gState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -2235,10 +2723,10 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) */ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) { - uint32_t temp1= 0x00U, temp2 = 0x00U; + uint32_t temp1 = 0x00U, temp2 = 0x00U; temp1 = huart->gState; temp2 = huart->RxState; - + return (HAL_UART_StateTypeDef)(temp1 | temp2); } @@ -2264,6 +2752,32 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) * @{ */ +/** + * @brief Initialize the callbacks to their default values. + * @param huart UART handle. + * @retval none + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) +{ + /* Init the UART Callback settings */ + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ +#if defined(USART_CR1_FIFOEN) + huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ +#endif + +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + /** * @brief Configure the UART peripheral. * @param huart UART handle. @@ -2277,20 +2791,20 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) uint32_t usartdiv = 0x00000000U; HAL_StatusTypeDef ret = HAL_OK; uint32_t lpuart_ker_ck_pres = 0x00000000U; - + /* Check the parameters */ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); - if(UART_INSTANCE_LOWPOWER(huart)) + if (UART_INSTANCE_LOWPOWER(huart)) { - assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits)); } else { assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); } - + assert_param(IS_UART_PARITY(huart->Init.Parity)); assert_param(IS_UART_MODE(huart->Init.Mode)); assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); @@ -2298,7 +2812,7 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) #if defined(USART_PRESC_PRESCALER) assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler)); #endif - + /*-------------------------- USART CR1 Configuration -----------------------*/ /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure * the UART Word Length, Parity, Mode and oversampling: @@ -2307,85 +2821,86 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; +#if defined(USART_CR1_FIFOEN) + tmpreg |= (uint32_t)huart->FifoMode; +#endif MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); - + /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - + /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according - * to huart->Init.OneBitSampling (not applicable to LPUART) - * - set TXFTCFG bit according to huart->Init.TxFifoThreshold value - * - set RXFTCFG bit according to huart->Init.RxFifoThreshold value */ + * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; - + if (!(UART_INSTANCE_LOWPOWER(huart))) { tmpreg |= huart->Init.OneBitSampling; } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); - + #if defined(USART_PRESC_PRESCALER) /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); #endif - + /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); - + /* Check LPUART instance */ - if(UART_INSTANCE_LOWPOWER(huart)) + if (UART_INSTANCE_LOWPOWER(huart)) { /* Retrieve frequency clock */ switch (clocksource) { - case UART_CLOCKSOURCE_PCLK1: + case UART_CLOCKSOURCE_PCLK1: #if defined(USART_PRESC_PRESCALER) - lpuart_ker_ck_pres = (HAL_RCC_GetPCLK1Freq()/UARTPrescTable[huart->Init.ClockPrescaler]); + lpuart_ker_ck_pres = (HAL_RCC_GetPCLK1Freq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); #else - lpuart_ker_ck_pres = HAL_RCC_GetPCLK1Freq(); + lpuart_ker_ck_pres = HAL_RCC_GetPCLK1Freq(); #endif - break; - case UART_CLOCKSOURCE_HSI: + break; + case UART_CLOCKSOURCE_HSI: #if defined(USART_PRESC_PRESCALER) - lpuart_ker_ck_pres = ((uint32_t)HSI_VALUE/UARTPrescTable[huart->Init.ClockPrescaler]); + lpuart_ker_ck_pres = ((uint32_t)HSI_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); #else - lpuart_ker_ck_pres = (uint32_t)HSI_VALUE; + lpuart_ker_ck_pres = (uint32_t)HSI_VALUE; #endif - break; - case UART_CLOCKSOURCE_SYSCLK: + break; + case UART_CLOCKSOURCE_SYSCLK: #if defined(USART_PRESC_PRESCALER) - lpuart_ker_ck_pres = (HAL_RCC_GetSysClockFreq()/UARTPrescTable[huart->Init.ClockPrescaler]); + lpuart_ker_ck_pres = (HAL_RCC_GetSysClockFreq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); #else - lpuart_ker_ck_pres = HAL_RCC_GetSysClockFreq(); + lpuart_ker_ck_pres = HAL_RCC_GetSysClockFreq(); #endif - break; - case UART_CLOCKSOURCE_LSE: + break; + case UART_CLOCKSOURCE_LSE: #if defined(USART_PRESC_PRESCALER) - lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE/UARTPrescTable[huart->Init.ClockPrescaler]); + lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); #else - lpuart_ker_ck_pres = (uint32_t)LSE_VALUE; + lpuart_ker_ck_pres = (uint32_t)LSE_VALUE; #endif - break; - case UART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; + break; + case UART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; } - + /* if proper clock source reported */ if (lpuart_ker_ck_pres != 0U) { /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ - if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || - (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) + if ((lpuart_ker_ck_pres < (3 * huart->Init.BaudRate)) || + (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate))) { ret = HAL_ERROR; } @@ -2393,40 +2908,40 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { switch (clocksource) { - case UART_CLOCKSOURCE_PCLK1: + case UART_CLOCKSOURCE_PCLK1: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); + usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); #endif - break; - case UART_CLOCKSOURCE_HSI: + break; + case UART_CLOCKSOURCE_HSI: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate)); + usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate)); #endif - break; - case UART_CLOCKSOURCE_SYSCLK: + break; + case UART_CLOCKSOURCE_SYSCLK: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); + usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); #endif - break; - case UART_CLOCKSOURCE_LSE: + break; + case UART_CLOCKSOURCE_LSE: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate)); + usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate)); #endif - break; - case UART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; + break; + case UART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; } - + /* It is forbidden to write values lower than 0x300 in the LPUART_BRR register */ if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) { @@ -2444,47 +2959,47 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { switch (clocksource) { - case UART_CLOCKSOURCE_PCLK1: + case UART_CLOCKSOURCE_PCLK1: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); #endif - break; - case UART_CLOCKSOURCE_PCLK2: + break; + case UART_CLOCKSOURCE_PCLK2: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); #endif - break; - case UART_CLOCKSOURCE_HSI: + break; + case UART_CLOCKSOURCE_HSI: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); #endif - break; - case UART_CLOCKSOURCE_SYSCLK: + break; + case UART_CLOCKSOURCE_SYSCLK: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); #endif - break; - case UART_CLOCKSOURCE_LSE: + break; + case UART_CLOCKSOURCE_LSE: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); #endif - break; - case UART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; + break; + case UART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; } - + /* USARTDIV must be greater than or equal to 0d16 */ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) { @@ -2501,47 +3016,47 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { switch (clocksource) { - case UART_CLOCKSOURCE_PCLK1: + case UART_CLOCKSOURCE_PCLK1: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); #endif - break; - case UART_CLOCKSOURCE_PCLK2: + break; + case UART_CLOCKSOURCE_PCLK2: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); #endif - break; - case UART_CLOCKSOURCE_HSI: + break; + case UART_CLOCKSOURCE_HSI: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); #endif - break; - case UART_CLOCKSOURCE_SYSCLK: + break; + case UART_CLOCKSOURCE_SYSCLK: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); #endif - break; - case UART_CLOCKSOURCE_LSE: + break; + case UART_CLOCKSOURCE_LSE: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); #endif - break; - case UART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; + break; + case UART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; } - + /* USARTDIV must be greater than or equal to 0d16 */ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) { @@ -2552,17 +3067,17 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) ret = HAL_ERROR; } } - + #if defined(USART_CR1_FIFOEN) /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; huart->NbRxDataToProcess = 1; #endif - + /* Clear ISR function pointers */ huart->RxISR = NULL; huart->TxISR = NULL; - + return ret; } @@ -2575,65 +3090,65 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); - + /* if required, configure TX pin active level inversion */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); } - + /* if required, configure RX pin active level inversion */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); } - + /* if required, configure data inversion */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); } - + /* if required, configure RX/TX pins swap */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); } - + /* if required, configure RX overrun detection disabling */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); } - + /* if required, configure DMA disabling on reception error */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); } - + /* if required, configure auto Baud rate detection scheme */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); /* set auto Baudrate detection parameters if detection is enabled */ - if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); } } - + /* if required, configure MSB first on communication line */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); @@ -2648,41 +3163,41 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { uint32_t tickstart = 0U; - + /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - + /* Check if the Transmitter is enabled */ - if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) { /* Wait until TEACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; } } /* Check if the Receiver is enabled */ - if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) { /* Wait until REACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; } } - + /* Initialize the UART State */ - huart->gState= HAL_UART_STATE_READY; - huart->RxState= HAL_UART_STATE_READY; - + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -2698,12 +3213,12 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ - while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ #if defined(USART_CR1_FIFOEN) @@ -2712,13 +3227,13 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); #endif CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - + huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_TIMEOUT; } } @@ -2734,10 +3249,12 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { - /* Disable TXEIE and TCIE interrupts */ #if defined(USART_CR1_FIFOEN) + /* Disable TXEIE, TCIE, TXFT interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); #else + /* Disable TXEIE and TCIE interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); #endif @@ -2756,14 +3273,15 @@ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ #if defined(USART_CR1_FIFOEN) CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); #else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +#endif /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* Reset RxIsr function pointer */ huart->RxISR = NULL; } @@ -2776,24 +3294,30 @@ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + /* DMA Normal mode */ - if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) - { + if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) + { huart->TxXferCount = 0U; - + /* Disable the DMA transfer for transmit request by resetting the DMAT bit - in the UART CR3 register */ + in the UART CR3 register */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Enable the UART Transmit Complete Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } /* DMA Circular mode */ else { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } @@ -2804,9 +3328,15 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx Half complete callback*/ + huart->TxHalfCpltCallback(huart); +#else + /*Call legacy weak Tx Half complete callback*/ HAL_UART_TxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } /** @@ -2816,26 +3346,32 @@ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + /* DMA Normal mode */ - if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) + if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { huart->RxXferCount = 0U; - + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; } - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } /** @@ -2845,9 +3381,15 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + huart->RxHalfCpltCallback(huart); +#else + /*Call legacy weak Rx Half complete callback*/ HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } /** @@ -2857,26 +3399,33 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + /* Stop UART DMA Tx request if ongoing */ - if ( (huart->gState == HAL_UART_STATE_BUSY_TX) - &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) ) + if ((huart->gState == HAL_UART_STATE_BUSY_TX) + && (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) { huart->TxXferCount = 0U; UART_EndTxTransfer(huart); } - + /* Stop UART DMA Rx request if ongoing */ - if ( (huart->RxState == HAL_UART_STATE_BUSY_RX) - &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ) + if ((huart->RxState == HAL_UART_STATE_BUSY_RX) + && (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) { huart->RxXferCount = 0U; UART_EndRxTransfer(huart); } - + huart->ErrorCode |= HAL_UART_ERROR_DMA; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } /** @@ -2887,11 +3436,17 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); huart->RxXferCount = 0U; huart->TxXferCount = 0U; - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } /** @@ -2904,29 +3459,29 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) */ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent); - + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + huart->hdmatx->XferAbortCallback = NULL; - + /* Check if an Abort process is still ongoing */ - if(huart->hdmarx != NULL) + if (huart->hdmarx != NULL) { - if(huart->hdmarx->XferAbortCallback != NULL) + if (huart->hdmarx->XferAbortCallback != NULL) { return; } } - + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ huart->TxXferCount = 0U; huart->RxXferCount = 0U; - + /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + #if defined(USART_CR1_FIFOEN) /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) @@ -2938,9 +3493,15 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } @@ -2954,38 +3515,44 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) */ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent); - + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + huart->hdmarx->XferAbortCallback = NULL; - + /* Check if an Abort process is still ongoing */ - if(huart->hdmatx != NULL) + if (huart->hdmatx != NULL) { - if(huart->hdmatx->XferAbortCallback != NULL) + if (huart->hdmatx->XferAbortCallback != NULL) { return; } } - + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ huart->TxXferCount = 0U; huart->RxXferCount = 0U; - + /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + /* Discard the received data */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - + /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } @@ -2999,10 +3566,10 @@ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) */ static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + huart->TxXferCount = 0U; - + #if defined(USART_CR1_FIFOEN) /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) @@ -3010,12 +3577,18 @@ static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); } #endif - + /* Restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } /** @@ -3028,21 +3601,27 @@ static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) */ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + huart->RxXferCount = 0U; - + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + /* Discard the received data */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - + /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } /** @@ -3057,7 +3636,7 @@ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) { - if(huart->TxXferCount == 0) + if (huart->TxXferCount == 0) { /* Disable the UART Transmit Data Register Empty Interrupt */ #if defined(USART_CR1_FIFOEN) @@ -3065,7 +3644,7 @@ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) #else CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); #endif - + /* Enable the UART Transmit Complete Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } @@ -3086,12 +3665,12 @@ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) */ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) { - uint16_t* tmp; - + uint16_t *tmp; + /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) { - if(huart->TxXferCount == 0) + if (huart->TxXferCount == 0) { /* Disable the UART Transmit Data Register Empty Interrupt */ #if defined(USART_CR1_FIFOEN) @@ -3105,7 +3684,7 @@ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) } else { - tmp = (uint16_t*) huart->pTxBuffPtr; + tmp = (uint16_t *) huart->pTxBuffPtr; huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); huart->pTxBuffPtr += 2; huart->TxXferCount--; @@ -3124,20 +3703,20 @@ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { uint8_t nb_tx_data; - + /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) { - for(nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) - { - if(huart->TxXferCount == 0U) + for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) + { + if (huart->TxXferCount == 0U) { /* Disable the TX FIFO threshold interrupt */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - + /* Enable the UART Transmit Complete Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - + break; /* force exit loop */ } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != RESET) @@ -3158,30 +3737,30 @@ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) */ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { - uint16_t* tmp; + uint16_t *tmp; uint8_t nb_tx_data; - + /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) { - for(nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) - { - if(huart->TxXferCount == 0U) + for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) + { + if (huart->TxXferCount == 0U) { /* Disable the TX FIFO threshold interrupt */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - + /* Enable the UART Transmit Complete Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - + break; /* force exit loop */ } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != RESET) { - tmp = (uint16_t*) huart->pTxBuffPtr; + tmp = (uint16_t *) huart->pTxBuffPtr; huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); huart->pTxBuffPtr += 2U; - huart->TxXferCount--; + huart->TxXferCount--; } } } @@ -3198,14 +3777,20 @@ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { /* Disable the UART Transmit Complete Interrupt */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); - + /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - + /* Cleat TxISR function pointer */ huart->TxISR = NULL; - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } /** @@ -3217,32 +3802,38 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) { uint16_t uhMask = huart->Mask; uint16_t uhdata; - + /* Check that a Rx process is ongoing */ - if(huart->RxState == HAL_UART_STATE_BUSY_RX) + if (huart->RxState == HAL_UART_STATE_BUSY_RX) { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); - - if(--huart->RxXferCount == 0) + + if (--huart->RxXferCount == 0) { - /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ #if defined(USART_CR1_FIFOEN) CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); #else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); #endif - + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - + /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* Clear RxISR function pointer */ huart->RxISR = NULL; - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } else @@ -3261,19 +3852,19 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) */ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) { - uint16_t* tmp; + uint16_t *tmp; uint16_t uhMask = huart->Mask; uint16_t uhdata; - + /* Check that a Rx process is ongoing */ - if(huart->RxState == HAL_UART_STATE_BUSY_RX) + if (huart->RxState == HAL_UART_STATE_BUSY_RX) { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - tmp = (uint16_t*) huart->pRxBuffPtr ; + tmp = (uint16_t *) huart->pRxBuffPtr ; *tmp = (uint16_t)(uhdata & uhMask); - huart->pRxBuffPtr +=2; - - if(--huart->RxXferCount == 0) + huart->pRxBuffPtr += 2; + + if (--huart->RxXferCount == 0) { /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ #if defined(USART_CR1_FIFOEN) @@ -3281,17 +3872,23 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) #else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); #endif - + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - + /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* Clear RxISR function pointer */ huart->RxISR = NULL; +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } else @@ -3314,46 +3911,52 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) uint16_t uhMask = huart->Mask; uint16_t uhdata; uint8_t nb_rx_data; - + /* Check that a Rx process is ongoing */ - if(huart->RxState == HAL_UART_STATE_BUSY_RX) + if (huart->RxState == HAL_UART_STATE_BUSY_RX) { - for(nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) + for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); huart->RxXferCount--; - - if(huart->RxXferCount == 0U) + + if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - + /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* Clear RxISR function pointer */ huart->RxISR = NULL; - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } - - /* When remaining number of bytes to receive is less than the RX FIFO - threshold, next incoming frames are processed as if FIFO mode was + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ if (((huart->RxXferCount != 0U)) && (huart->RxXferCount < huart->NbRxDataToProcess)) { /* Disable the UART RXFT interrupt*/ CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); - + /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_8BIT; - + /* Enable the UART Data Register Not Empty interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); } @@ -3374,55 +3977,61 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) */ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { - uint16_t* tmp; + uint16_t *tmp; uint16_t uhMask = huart->Mask; uint16_t uhdata; uint8_t nb_rx_data; - + /* Check that a Rx process is ongoing */ - if(huart->RxState == HAL_UART_STATE_BUSY_RX) + if (huart->RxState == HAL_UART_STATE_BUSY_RX) { - for(nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) + for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - tmp = (uint16_t*) huart->pRxBuffPtr ; + tmp = (uint16_t *) huart->pRxBuffPtr ; *tmp = (uint16_t)(uhdata & uhMask); - huart->pRxBuffPtr +=2; + huart->pRxBuffPtr += 2; huart->RxXferCount--; - - if(huart->RxXferCount == 0U) + + if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - + /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* Clear RxISR function pointer */ huart->RxISR = NULL; - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } - - /* When remaining number of bytes to receive is less than the RX FIFO - threshold, next incoming frames are processed as if FIFO mode was + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ if (((huart->RxXferCount != 0U)) && (huart->RxXferCount < huart->NbRxDataToProcess)) { /* Disable the UART RXFT interrupt*/ CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); - + /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_16BIT; - + /* Enable the UART Data Register Not Empty interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); - } + } } else { diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c index 750643a925..2fd9977f12 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c @@ -21,15 +21,10 @@ (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. - -@- When USART operates in FIFO mode, FIFO mode must be enabled prior - starting RX/TX transfers. Also RX/TX FIFO thresholds must be + -@- When UART operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be configured prior starting RX/TX transfers. - (#) Slave mode enabling/disabling and NSS pin configuration. - - -@- When USART operates in Slave mode, Slave mode must be enabled prior - starting RX/TX transfers. - @endverbatim ****************************************************************************** * @attention @@ -77,12 +72,23 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +#if defined(USART_CR1_FIFOEN) +/* UART RX FIFO depth */ +#define RX_FIFO_DEPTH 8U + +/* UART TX FIFO depth */ +#define TX_FIFO_DEPTH 8U +#endif + /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup UARTEx_Private_Functions UARTEx Private Functions * @{ */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +extern void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); #if defined(USART_CR1_FIFOEN) static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); @@ -131,10 +137,10 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); @endverbatim - Depending on the frame length defined by the M1 and M0 bits (7-bit, - 8-bit or 9-bit), the possible UART formats are listed in the + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the following table. - + Table 1. UART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | UART frame | @@ -176,64 +182,76 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); */ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime) { - uint32_t temp = 0x0; - + uint32_t temp = 0x0U; + /* Check the UART handle allocation */ - if(huart == NULL) + if (huart == NULL) { return HAL_ERROR; } /* Check the Driver Enable UART instance */ assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); - + /* Check the Driver Enable polarity */ assert_param(IS_UART_DE_POLARITY(Polarity)); - + /* Check the Driver Enable assertion time */ assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); - + /* Check the Driver Enable deassertion time */ assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); - - if(huart->gState == HAL_UART_STATE_RESET) + + if (huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else /* Init the low level hardware : GPIO, CLOCK, CORTEX */ HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - - if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - + /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DEM); - + /* Set the Driver Enable polarity */ MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); - + /* Set the Driver Enable assertion and deassertion times */ temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); - MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp); - + MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -268,7 +286,7 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, * @param huart UART handle. * @retval None */ - __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); @@ -284,7 +302,7 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, * @param huart UART handle. * @retval None */ -__weak void HAL_UARTEx_RxFifoFullCallback (UART_HandleTypeDef *huart) +__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); @@ -299,7 +317,7 @@ __weak void HAL_UARTEx_RxFifoFullCallback (UART_HandleTypeDef *huart) * @param huart UART handle. * @retval None */ -__weak void HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart) +__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); @@ -331,9 +349,6 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart) (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode (+) HAL_UARTEx_DisableStopMode() API disables the above functionality (+) HAL_UARTEx_WakeupCallback() called upon UART wakeup interrupt - (+) HAL_UARTEx_EnableSPISlaveMode() API enables the SPI slave mode - (+) HAL_UARTEx_DisableSPISlaveMode() API disables the SPI slave mode - (+) HAL_UARTEx_ConfigNSS API configures the Slave Select input pin (NSS) (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold @@ -345,13 +360,56 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart) +#if defined(USART_CR3_UCESM) +/** + * @brief Keep UART Clock enabled when in Stop Mode. + * @note When the USART clock source is configured to be LSE or HSI, it is possible to keep enabled + * this clock during STOP mode by setting the UCESM bit in USART_CR3 control register. + * @note When LPUART is used to wakeup from stop with LSE is selected as LPUART clock source, + * and desired baud rate is 9600 baud, the bit UCESM bit in LPUART_CR3 control register must be set. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Set UCESM bit */ + SET_BIT(huart->Instance->CR3, USART_CR3_UCESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable UART Clock when in Stop Mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Clear UCESM bit */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_UCESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} +#endif /* USART_CR3_UCESM */ /** * @brief By default in multiprocessor mode, when the wake up method is set * to address mark, the UART handles only 4-bit long addresses detection; * this API allows to enable longer addresses detection (6-, 7- or 8-bit * long). - * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, + * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. * @param huart UART handle. * @param AddressLength This parameter can be one of the following values: @@ -362,25 +420,25 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) { /* Check the UART handle allocation */ - if(huart == NULL) + if (huart == NULL) { return HAL_ERROR; } - + /* Check the address length parameter */ assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the address length */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState to Ready */ return (UART_CheckIdleState(huart)); } @@ -401,37 +459,37 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) { HAL_StatusTypeDef status = HAL_OK; - uint32_t tickstart = 0; - + uint32_t tickstart = 0U; + /* check the wake-up from stop mode UART instance */ assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); /* check the wake-up selection parameter */ assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); - + /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the wake-up selection scheme */ MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); - + if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) { UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); } - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - + /* Wait until REACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { status = HAL_TIMEOUT; } @@ -440,10 +498,10 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; } - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return status; } @@ -458,17 +516,13 @@ HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - + /* Set UESM bit */ SET_BIT(huart->Instance->CR1, USART_CR1_UESM); - - huart->gState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -481,165 +535,15 @@ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - + /* Clear UESM bit */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} -#if defined(USART_CR2_SLVEN) -/** - * @brief Enable the SPI slave mode. - * @note When the UART operates in SPI slave mode, it handles data flow using - * the serial interface clock derived from the external SCLK signal - * provided by the external master SPI device. - * @note In SPI slave mode, the UART must be enabled before starting the master - * communications (or between frames while the clock is stable). Otherwise, - * if the UART slave is enabled while the master is in the middle of a - * frame, it will become desynchronized with the master. - * @note The data register of the slave needs to be ready before the first edge - * of the communication clock or before the end of the ongoing communication, - * otherwise the SPI slave will transmit zeros. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_EnableSlaveMode(UART_HandleTypeDef *huart) -{ - uint32_t tmpcr1 = 0; - - /* Check parameters */ - assert_param(IS_UART_SPI_SLAVE_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* In SPI slave mode mode, the following bits must be kept cleared: - - LINEN and CLKEN bit in the USART_CR2 register - - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - - /* Enable SPI slave mode */ - SET_BIT(huart->Instance->CR2, USART_CR2_SLVEN); - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - huart->SlaveMode = UART_SLAVEMODE_ENABLE; - - huart->gState = HAL_UART_STATE_READY; - - /* Enable UART */ - __HAL_UART_ENABLE(huart); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Disable the SPI slave mode. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_DisableSlaveMode(UART_HandleTypeDef *huart) -{ - uint32_t tmpcr1 = 0; - - /* Check parameters */ - assert_param(IS_UART_SPI_SLAVE_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* Disable SPI slave mode */ - CLEAR_BIT(huart->Instance->CR2, USART_CR2_SLVEN); - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - huart->SlaveMode = UART_SLAVEMODE_ENABLE; - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Configure the Slave Select input pin (NSS). - * @note Software NSS management: SPI slave will always be selected and NSS - * input pin will be ignored. - * @note Hardware NSS management: the SPI slave selection depends on NSS - * input pin. The slave is selected when NSS is low and deselected when - * NSS is high. - * @param huart UART handle. - * @param NSSConfig NSS configuration. - * This parameter can be one of the following values: - * @arg @ref UART_NSS_HARD - * @arg @ref UART_NSS_SOFT - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_ConfigNSS(UART_HandleTypeDef *huart, uint32_t NSSConfig) -{ - uint32_t tmpcr1 = 0; - - /* Check parameters */ - assert_param(IS_UART_SPI_SLAVE_INSTANCE(huart->Instance)); - assert_param(IS_UART_NSS(NSSConfig)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* Program DIS_NSS bit in the USART_CR2 register */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig); - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; } -#endif #if defined(USART_CR1_FIFOEN) /** @@ -649,37 +553,37 @@ HAL_StatusTypeDef HAL_UARTEx_ConfigNSS(UART_HandleTypeDef *huart, uint32_t NSSCo */ HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) { - uint32_t tmpcr1 = 0; - + uint32_t tmpcr1 = 0U; + /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); - + /* Disable UART */ __HAL_UART_DISABLE(huart); - + /* Enable FIFO mode */ SET_BIT(tmpcr1, USART_CR1_FIFOEN); huart->FifoMode = UART_FIFOMODE_ENABLE; - + /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); - + /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); - + huart->gState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -690,34 +594,34 @@ HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { - uint32_t tmpcr1 = 0; + uint32_t tmpcr1 = 0U; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); - + /* Disable UART */ __HAL_UART_DISABLE(huart); - + /* Enable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); huart->FifoMode = UART_FIFOMODE_DISABLE; - + /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); - + huart->gState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -736,37 +640,37 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { - uint32_t tmpcr1 = 0; - + uint32_t tmpcr1 = 0U; + /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); - + /* Disable UART */ __HAL_UART_DISABLE(huart); - + /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); - + /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); - + /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); - + huart->gState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -785,37 +689,37 @@ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint3 */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { - uint32_t tmpcr1 = 0; - + uint32_t tmpcr1 = 0U; + /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); - + /* Disable UART */ __HAL_UART_DISABLE(huart); - + /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); - + /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); - + /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); - + huart->gState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } #endif @@ -841,10 +745,10 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) { assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); - + /* Set the USART address length */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); - + /* Set the USART address node */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); } @@ -857,32 +761,31 @@ static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTy * @param huart UART handle. * @retval None */ -void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) +static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { uint8_t rx_fifo_depth; uint8_t tx_fifo_depth; uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; - uint8_t numerator[] = {1, 1, 1, 3, 7, 1}; - uint8_t denominator[] = {8, 4, 2, 4, 8, 1}; - + uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U}; + uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U}; + if (huart->FifoMode == UART_FIFOMODE_DISABLE) { - huart->NbTxDataToProcess = 1; - huart->NbRxDataToProcess = 1; + huart->NbTxDataToProcess = 1U; + huart->NbRxDataToProcess = 1U; } else { - rx_fifo_depth = 8; /* RX Fifo size */ - tx_fifo_depth = 8; /* TX Fifo size */ + rx_fifo_depth = RX_FIFO_DEPTH; + tx_fifo_depth = TX_FIFO_DEPTH; rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); - huart->NbTxDataToProcess = (uint8_t)(tx_fifo_depth * numerator[tx_fifo_threshold])/denominator[tx_fifo_threshold]; - huart->NbRxDataToProcess = (uint8_t)(rx_fifo_depth * numerator[rx_fifo_threshold])/denominator[rx_fifo_threshold]; + huart->NbTxDataToProcess = (uint8_t)(tx_fifo_depth * numerator[tx_fifo_threshold]) / denominator[tx_fifo_threshold]; + huart->NbRxDataToProcess = (uint8_t)(rx_fifo_depth * numerator[rx_fifo_threshold]) / denominator[rx_fifo_threshold]; } } #endif - /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart.c index 802b25d0f9..cb6ac32997 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart.c @@ -50,8 +50,75 @@ [..] (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's - HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and - HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef. + HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and + HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_USART_RegisterCallback() to register a user callback. + Function @ref HAL_USART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) TxRxCpltCallback : Tx Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : USART MspInit. + (+) MspDeInitCallback : USART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function @ref HAL_USART_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) TxRxCpltCallback : Tx Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : USART MspInit. + (+) MspDeInitCallback : USART MspDeInit. + + [..] + By default, after the @ref HAL_USART_Init() and when the state is HAL_USART_STATE_RESET + all callbacks are set to the corresponding weak (surcharged) functions: + examples @ref HAL_USART_TxCpltCallback(), @ref HAL_USART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_USART_Init() + and @ref HAL_USART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_USART_Init() and @ref HAL_USART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_USART_RegisterCallback() before calling @ref HAL_USART_DeInit() + or @ref HAL_USART_Init() function. + + [..] + When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak (surcharged) callbacks are used. + @endverbatim ****************************************************************************** @@ -104,8 +171,7 @@ * @{ */ #define USART_DUMMY_DATA ((uint16_t) 0xFFFF) /*!< USART transmitted dummy data */ -#define USART_TEACK_REACK_TIMEOUT ((uint32_t) 1000) /*!< USART TX or RX enable acknowledge time-out value */ - +#define USART_TEACK_REACK_TIMEOUT 1000U /*!< USART TX or RX enable acknowledge time-out value */ #if defined(USART_CR1_FIFOEN) #define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 | \ @@ -124,6 +190,7 @@ #endif #define USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */ +#define USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */ /** * @} */ @@ -134,6 +201,9 @@ /** @addtogroup USART_Private_Functions * @{ */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ static void USART_EndTransfer(USART_HandleTypeDef *husart); static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); @@ -198,10 +268,10 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); @endverbatim - Depending on the frame length defined by the M1 and M0 bits (7-bit, - 8-bit or 9-bit), the possible USART formats are listed in the + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible USART formats are listed in the following table. - + Table 1. USART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | USART frame | @@ -231,7 +301,7 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) { /* Check the USART handle allocation */ - if(husart == NULL) + if (husart == NULL) { return HAL_ERROR; } @@ -239,13 +309,25 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) /* Check the parameters */ assert_param(IS_USART_INSTANCE(husart->Instance)); - if(husart->State == HAL_USART_STATE_RESET) + if (husart->State == HAL_USART_STATE_RESET) { /* Allocate lock resource and initialize it */ husart->Lock = HAL_UNLOCKED; +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + USART_InitCallbacksToDefault(husart); + + if (husart->MspInitCallback == NULL) + { + husart->MspInitCallback = HAL_USART_MspInit; + } + + /* Init the low level hardware */ + husart->MspInitCallback(husart); +#else /* Init the low level hardware : GPIO, CLOCK */ HAL_USART_MspInit(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } husart->State = HAL_USART_STATE_BUSY; @@ -279,8 +361,8 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) { - /* Check the USART handle allocation */ - if(husart == NULL) + /* Check the USART handle allocation */ + if (husart == NULL) { return HAL_ERROR; } @@ -290,12 +372,21 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) husart->State = HAL_USART_STATE_BUSY; - husart->Instance->CR1 = 0x0; - husart->Instance->CR2 = 0x0; - husart->Instance->CR3 = 0x0; + husart->Instance->CR1 = 0x0U; + husart->Instance->CR2 = 0x0U; + husart->Instance->CR3 = 0x0U; +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + if (husart->MspDeInitCallback == NULL) + { + husart->MspDeInitCallback = HAL_USART_MspDeInit; + } + /* DeInit the low level hardware */ + husart->MspDeInitCallback(husart); +#else /* DeInit the low level hardware */ HAL_USART_MspDeInit(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_RESET; @@ -311,11 +402,11 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) * @param husart USART handle. * @retval None */ - __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) +__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_MspInit can be implemented in the user file */ @@ -326,16 +417,269 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) * @param husart USART handle. * @retval None */ - __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) +__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_MspDeInit can be implemented in the user file */ } +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User USART Callback + * To be used instead of the weak predefined callback + * @param husart usart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status ++ */ +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(husart); + + if (husart->State == HAL_USART_STATE_READY) + { + switch (CallbackID) + { + case HAL_USART_TX_HALFCOMPLETE_CB_ID : + husart->TxHalfCpltCallback = pCallback; + break; + + case HAL_USART_TX_COMPLETE_CB_ID : + husart->TxCpltCallback = pCallback; + break; + + case HAL_USART_RX_HALFCOMPLETE_CB_ID : + husart->RxHalfCpltCallback = pCallback; + break; + + case HAL_USART_RX_COMPLETE_CB_ID : + husart->RxCpltCallback = pCallback; + break; + + case HAL_USART_TX_RX_COMPLETE_CB_ID : + husart->TxRxCpltCallback = pCallback; + break; + + case HAL_USART_ERROR_CB_ID : + husart->ErrorCallback = pCallback; + break; + + case HAL_USART_ABORT_COMPLETE_CB_ID : + husart->AbortCpltCallback = pCallback; + break; + +#if defined(USART_CR1_FIFOEN) + case HAL_USART_RX_FIFO_FULL_CB_ID : + husart->RxFifoFullCallback = pCallback; + break; + + case HAL_USART_TX_FIFO_EMPTY_CB_ID : + husart->TxFifoEmptyCallback = pCallback; + break; +#endif + + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = pCallback; + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (husart->State == HAL_USART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = pCallback; + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(husart); + + return status; +} + +/** + * @brief Unregister an UART Callback + * UART callaback is redirected to the weak predefined callback + * @param husart uart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(husart); + + if (HAL_USART_STATE_READY == husart->State) + { + switch (CallbackID) + { + case HAL_USART_TX_HALFCOMPLETE_CB_ID : + husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_USART_TX_COMPLETE_CB_ID : + husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_USART_RX_HALFCOMPLETE_CB_ID : + husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_USART_RX_COMPLETE_CB_ID : + husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_USART_TX_RX_COMPLETE_CB_ID : + husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + break; + + case HAL_USART_ERROR_CB_ID : + husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_USART_ABORT_COMPLETE_CB_ID : + husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + +#if defined(USART_CR1_FIFOEN) + case HAL_USART_RX_FIFO_FULL_CB_ID : + husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + break; + + case HAL_USART_TX_FIFO_EMPTY_CB_ID : + husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + break; +#endif + + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_USART_STATE_RESET == husart->State) + { + switch (CallbackID) + { + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = HAL_USART_MspInit; + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = HAL_USART_MspDeInit; + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(husart); + + return status; +} +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + + /** * @} */ @@ -402,7 +746,7 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side. @@ -425,68 +769,68 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; - uint32_t tickstart = 0; + uint16_t *tmp; + uint32_t tickstart = 0U; - if(husart->State == HAL_USART_STATE_READY) + if (husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (Size == 0)) + if ((pTxData == NULL) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(husart); - + husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX; - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - + husart->TxXferSize = Size; husart->TxXferCount = Size; - + /* Check the remaining data to be sent */ - while(husart->TxXferCount > 0) + while (husart->TxXferCount > 0U) { - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { - tmp = (uint16_t*) pTxData; + tmp = (uint16_t *) pTxData; husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - pTxData += 2; + pTxData += 2U; } else { husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFF); } - + husart->TxXferCount--; } - - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - + /* Clear Transmission Complete Flag */ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); - + /* Clear overrun flag and discard the received data */ __HAL_USART_CLEAR_OREFLAG(husart); __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); - + /* At end of Tx process, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } else @@ -506,35 +850,35 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa */ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; + uint16_t *tmp; uint16_t uhMask; - uint32_t tickstart = 0; - - if(husart->State == HAL_USART_STATE_READY) + uint32_t tickstart = 0U; + + if (husart->State == HAL_USART_STATE_READY) { - if((pRxData == NULL) || (Size == 0)) + if ((pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(husart); - + husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - + husart->RxXferSize = Size; husart->RxXferCount = Size; - + /* Computation of USART mask to apply to RDR register */ USART_MASK_COMPUTATION(husart); uhMask = husart->Mask; - + /* as long as data have to be received */ - while(husart->RxXferCount > 0) + while (husart->RxXferCount > 0U) { #if defined(USART_CR2_SLVEN) if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) @@ -544,34 +888,34 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat * clock for the slave to send data. * Whatever the frame length (7, 8 or 9-bit long), the same dummy value * can be written for all the cases. */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF); } - + /* Wait for RXNE Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { - tmp = (uint16_t*) pRxData ; + tmp = (uint16_t *) pRxData ; *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - pRxData +=2; + pRxData += 2U; } else { *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); } - + husart->RxXferCount--; - + } - + #if defined(USART_CR2_SLVEN) /* Clear SPI slave underrun flag and discard transmit data */ if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) @@ -580,13 +924,13 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); } #endif - + /* At end of Rx process, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } else @@ -606,17 +950,17 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat */ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; + uint16_t *tmp; uint16_t uhMask; - uint32_t tickstart = 0; + uint32_t tickstart = 0U; - if(husart->State == HAL_USART_STATE_READY) + if (husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(husart); @@ -642,67 +986,67 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t #endif { /* Wait until TXE flag is set to send data */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { - tmp = (uint16_t*) pTxData; + tmp = (uint16_t *) pTxData; husart->Instance->TDR = (*tmp & uhMask); pTxData += 2U; } else - { + { husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask); } husart->TxXferCount--; } - + /* Check the remain data to be sent */ - while ((husart->TxXferCount > 0) || (husart->RxXferCount > 0)) + while ((husart->TxXferCount > 0U) || (husart->RxXferCount > 0U)) { - if (husart->TxXferCount > 0) + if (husart->TxXferCount > 0U) { /* Wait until TXE flag is set to send data */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { - tmp = (uint16_t*) pTxData; + tmp = (uint16_t *) pTxData; husart->Instance->TDR = (*tmp & uhMask); - pTxData += 2; + pTxData += 2U; } else { husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask); } - + husart->TxXferCount--; } - - if (husart->RxXferCount > 0) + + if (husart->RxXferCount > 0U) { /* Wait for RXNE Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { - tmp = (uint16_t*) pRxData ; + tmp = (uint16_t *) pRxData ; *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - pRxData +=2; + pRxData += 2U; } else { *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); } - + husart->RxXferCount--; } } @@ -730,9 +1074,9 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t */ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) { - if(husart->State == HAL_USART_STATE_READY) + if (husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL ) || (Size == 0)) + if ((pTxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -757,7 +1101,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT #if defined(USART_CR1_FIFOEN) /* Configure Tx interrupt processing */ if (husart->FifoMode == USART_FIFOMODE_ENABLE) - { + { /* Set the Tx ISR function pointer according to the data word length */ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { @@ -766,11 +1110,11 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT else { husart->TxISR = USART_TxISR_8BIT_FIFOEN; - } - + } + /* Process Unlocked */ __HAL_UNLOCK(husart); - + /* Enable the TX FIFO threshold interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_TXFT); } @@ -785,11 +1129,11 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT else { husart->TxISR = USART_TxISR_8BIT; - } - + } + /* Process Unlocked */ __HAL_UNLOCK(husart); - + /* Enable the USART Transmit Data Register Empty Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); } @@ -815,10 +1159,10 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx #if defined(USART_CR1_FIFOEN) uint8_t nb_dummy_data; #endif - - if(husart->State == HAL_USART_STATE_READY) + + if (husart->State == HAL_USART_STATE_READY) { - if((pRxData == NULL ) || (Size == 0)) + if ((pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -852,10 +1196,10 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx { husart->RxISR = USART_RxISR_8BIT_FIFOEN; } - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + /* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); @@ -872,10 +1216,10 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx { husart->RxISR = USART_RxISR_8BIT; } - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + /* Enable the USART Parity Error and Data Register not empty Interrupts */ #if defined(USART_CR1_FIFOEN) SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); @@ -895,7 +1239,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx #if defined(USART_CR1_FIFOEN) if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess)) { - for (nb_dummy_data = husart->NbRxDataToProcess ; nb_dummy_data > 0 ; nb_dummy_data--) + for (nb_dummy_data = husart->NbRxDataToProcess ; nb_dummy_data > 0U ; nb_dummy_data--) { husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); } @@ -906,7 +1250,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); } } - + return HAL_OK; } else @@ -919,19 +1263,20 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx * @brief Full-Duplex Send and Receive an amount of data in interrupt mode. * @param husart USART handle. * @param pTxData pointer to TX data buffer. - * @param pRxData pointer to RX data buffer. + * @param pRxData pointer to RX data buffer. * @param Size amount of data to be sent (same amount to be received). * @retval HAL status */ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { - if(husart->State == HAL_USART_STATE_READY) + if (husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } + /* Process Locked */ __HAL_LOCK(husart); @@ -947,7 +1292,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX_RX; - + #if defined(USART_CR1_FIFOEN) /* Configure TxRx interrupt processing */ if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess)) @@ -963,13 +1308,13 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint husart->TxISR = USART_TxISR_8BIT_FIFOEN; husart->RxISR = USART_RxISR_8BIT_FIFOEN; } - + /* Process Locked */ __HAL_UNLOCK(husart); - + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - + /* Enable the USART Parity Error interrupt */ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); @@ -992,17 +1337,17 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint /* Process Locked */ __HAL_UNLOCK(husart); - + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - + /* Enable the USART Parity Error and USART Data Register not empty Interrupts */ #if defined(USART_CR1_FIFOEN) SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); #else - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); #endif - + /* Enable the USART Transmit Data Register Empty Interrupt */ #if defined(USART_CR1_FIFOEN) SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); @@ -1030,12 +1375,13 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p { uint32_t *tmp; - if(husart->State == HAL_USART_STATE_READY) + if (husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL ) || (Size == 0)) + if ((pTxData == NULL) || (Size == 0U)) { return HAL_ERROR; } + /* Process Locked */ __HAL_LOCK(husart); @@ -1056,8 +1402,8 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p husart->hdmatx->XferErrorCallback = USART_DMAError; /* Enable the USART transmit DMA channel */ - tmp = (uint32_t*)&pTxData; - HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); + tmp = (uint32_t *)&pTxData; + HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); /* Clear the TC flag in the ICR register */ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); @@ -1079,12 +1425,12 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p /** * @brief Receive an amount of data in DMA mode. + * @note When the USART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. * @param husart USART handle. * @param pRxData pointer to data buffer. * @param Size amount of data to be received. - * @note When the USART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position). - * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) @@ -1092,9 +1438,9 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR uint32_t *tmp; /* Check that a Rx process is not already ongoing */ - if(husart->State == HAL_USART_STATE_READY) + if (husart->State == HAL_USART_STATE_READY) { - if((pRxData == NULL ) || (Size == 0)) + if ((pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1120,24 +1466,24 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR husart->hdmarx->XferErrorCallback = USART_DMAError; /* Enable the USART receive DMA channel */ - tmp = (uint32_t*)&pRxData; - HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size); + tmp = (uint32_t *)&pRxData; + HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size); #if defined(USART_CR2_SLVEN) if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) +#endif { /* Enable the USART transmit DMA channel: the transmit channel is used in order to generate in the non-blocking mode the clock to the slave device, this mode isn't a simplex receive mode but a full-duplex receive mode */ - tmp = (uint32_t*)&pRxData; + /* Set the USART DMA Tx Complete and Error callback to Null */ husart->hdmatx->XferErrorCallback = NULL; husart->hdmatx->XferHalfCpltCallback = NULL; husart->hdmatx->XferCpltCallback = NULL; - HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); + HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); } -#endif - + /* Process Unlocked */ __HAL_UNLOCK(husart); @@ -1165,23 +1511,24 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /** * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. + * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. * @param husart USART handle. * @param pTxData pointer to TX data buffer. * @param pRxData pointer to RX data buffer. * @param Size amount of data to be received/sent. - * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { uint32_t *tmp; - if(husart->State == HAL_USART_STATE_READY) + if (husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } + /* Process Locked */ __HAL_LOCK(husart); @@ -1212,12 +1559,12 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin husart->hdmarx->XferErrorCallback = USART_DMAError; /* Enable the USART receive DMA channel */ - tmp = (uint32_t*)&pRxData; - HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size); + tmp = (uint32_t *)&pRxData; + HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size); /* Enable the USART transmit DMA channel */ - tmp = (uint32_t*)&pTxData; - HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); + tmp = (uint32_t *)&pTxData; + HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); /* Process Unlocked */ __HAL_UNLOCK(husart); @@ -1257,27 +1604,27 @@ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) /* Process Locked */ __HAL_LOCK(husart); - if( (husart->State == HAL_USART_STATE_BUSY_TX) && + if ((husart->State == HAL_USART_STATE_BUSY_TX) && (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))) { /* Disable the USART DMA Tx request */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); } - else if( (husart->State == HAL_USART_STATE_BUSY_RX) || - (husart->State == HAL_USART_STATE_BUSY_TX_RX) ) + else if ((husart->State == HAL_USART_STATE_BUSY_RX) || + (husart->State == HAL_USART_STATE_BUSY_TX_RX)) { if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { /* Disable the USART DMA Tx request */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - } + } if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) - { + { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - /* Disable the USART DMA Rx request */ + /* Disable the USART DMA Rx request */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); } } @@ -1298,16 +1645,16 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) /* Process Locked */ __HAL_LOCK(husart); - if(husart->State == HAL_USART_STATE_BUSY_TX) + if (husart->State == HAL_USART_STATE_BUSY_TX) { /* Enable the USART DMA Tx request */ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); } - else if( (husart->State == HAL_USART_STATE_BUSY_RX) || - (husart->State == HAL_USART_STATE_BUSY_TX_RX) ) + else if ((husart->State == HAL_USART_STATE_BUSY_RX) || + (husart->State == HAL_USART_STATE_BUSY_TX_RX)) { /* Clear the Overrun flag before resuming the Rx transfer*/ - __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); @@ -1335,22 +1682,22 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) { /* The Lock is not implemented on this API to allow the user application to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() / - HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback: - indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete - interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of - the stream and the corresponding call back is executed. */ + HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ /* Disable the USART Tx/Rx DMA requests */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* Abort the USART DMA tx channel */ - if(husart->hdmatx != NULL) + if (husart->hdmatx != NULL) { HAL_DMA_Abort(husart->hdmatx); } /* Abort the USART DMA rx channel */ - if(husart->hdmarx != NULL) + if (husart->hdmarx != NULL) { HAL_DMA_Abort(husart->hdmarx); } @@ -1364,7 +1711,7 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) /** * @brief Abort ongoing transfers (blocking mode). * @param husart USART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable USART Interrupts (Tx and Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1390,9 +1737,9 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */ - if(husart->hdmatx != NULL) + if (husart->hdmatx != NULL) { - /* Set the USART DMA Abort callback to Null. + /* Set the USART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ husart->hdmatx->XferAbortCallback = NULL; @@ -1406,9 +1753,9 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */ - if(husart->hdmarx != NULL) + if (husart->hdmarx != NULL) { - /* Set the USART DMA Abort callback to Null. + /* Set the USART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ husart->hdmarx->XferAbortCallback = NULL; @@ -1417,8 +1764,8 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) } /* Reset Tx and Rx transfer counters */ - husart->TxXferCount = 0; - husart->RxXferCount = 0; + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); @@ -1430,7 +1777,7 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); } #endif - + /* Discard the received data */ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); @@ -1446,7 +1793,7 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) /** * @brief Abort ongoing transfers (Interrupt mode). * @param husart USART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable USART Interrupts (Tx and Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1459,8 +1806,8 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) { - uint32_t abortcplt = 1; - + uint32_t abortcplt = 1U; + #if defined(USART_CR1_FIFOEN) /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); @@ -1473,11 +1820,11 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ /* DMA Tx Handle is valid */ - if(husart->hdmatx != NULL) + if (husart->hdmatx != NULL) { /* Set DMA Abort Complete callback if USART DMA Tx request if enabled. Otherwise, set it to NULL */ - if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback; } @@ -1487,11 +1834,11 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) } } /* DMA Rx Handle is valid */ - if(husart->hdmarx != NULL) + if (husart->hdmarx != NULL) { /* Set DMA Abort Complete callback if USART DMA Rx request if enabled. Otherwise, set it to NULL */ - if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback; } @@ -1500,27 +1847,27 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) husart->hdmarx->XferAbortCallback = NULL; } } - + /* Disable the USART DMA Tx request if enabled */ - if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { /* Disable DMA Tx at USART level */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */ - if(husart->hdmatx != NULL) + if (husart->hdmatx != NULL) { - /* USART Tx DMA Abort callback has already been initialised : + /* USART Tx DMA Abort callback has already been initialised : will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK) + if (HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK) { husart->hdmatx->XferAbortCallback = NULL; } else { - abortcplt = 0; + abortcplt = 0U; } } } @@ -1531,30 +1878,30 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */ - if(husart->hdmarx != NULL) + if (husart->hdmarx != NULL) { - /* USART Rx DMA Abort callback has already been initialised : + /* USART Rx DMA Abort callback has already been initialised : will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) { husart->hdmarx->XferAbortCallback = NULL; - abortcplt = 1; + abortcplt = 1U; } else { - abortcplt = 0; + abortcplt = 0U; } } } /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ - if (abortcplt == 1) + if (abortcplt == 1U) { /* Reset Tx and Rx transfer counters */ - husart->TxXferCount = 0; - husart->RxXferCount = 0; + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; /* Reset errorCode */ husart->ErrorCode = HAL_USART_ERROR_NONE; @@ -1568,16 +1915,22 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) { __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); } - #endif + /* Discard the received data */ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); - + /* Restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->AbortCpltCallback(husart); +#else + /* Call legacy weak Abort Complete Callback */ HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } return HAL_OK; @@ -1595,7 +1948,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) uint32_t cr3its = READ_REG(husart->Instance->CR3); uint32_t errorflags; - + /* If no error occurs */ #if defined(USART_CR2_SLVEN) errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_UDR)); @@ -1606,73 +1959,76 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) { /* USART in mode Receiver ---------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) - && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) + if (((isrflags & USART_ISR_RXNE_RXFNE) != RESET) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) + || ((cr3its & USART_CR3_RXFTIE) != RESET))) #else - if(((isrflags & USART_ISR_RXNE) != RESET) - && ((cr1its & USART_CR1_RXNEIE) != RESET)) + if (((isrflags & USART_ISR_RXNE) != RESET) + && ((cr1its & USART_CR1_RXNEIE) != RESET)) #endif { - if (husart->RxISR != NULL) {husart->RxISR(husart);} + if (husart->RxISR != NULL) + { + husart->RxISR(husart); + } return; } } - + /* If some errors occur */ #if defined(USART_CR1_FIFOEN) - if( (errorflags != RESET) - && ( ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET) - || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET))) + if ((errorflags != RESET) + && (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET))) #else - if( (errorflags != RESET) - && ( ((cr3its & USART_CR3_EIE) != RESET) - || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) + if ((errorflags != RESET) + && (((cr3its & USART_CR3_EIE) != RESET) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) #endif { /* USART parity error interrupt occurred -------------------------------------*/ - if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + if (((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) { __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF); - + husart->ErrorCode |= HAL_USART_ERROR_PE; } - + /* USART frame error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF); - + husart->ErrorCode |= HAL_USART_ERROR_FE; } - + /* USART noise error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF); - + husart->ErrorCode |= HAL_USART_ERROR_NE; } - + /* USART Over-Run interrupt occurred -----------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if( ((isrflags & USART_ISR_ORE) != RESET) - &&( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) || + if (((isrflags & USART_ISR_ORE) != RESET) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) || ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET))) #else - if( ((isrflags & USART_ISR_ORE) != RESET) - &&( ((cr1its & USART_CR1_RXNEIE) != RESET) || + if (((isrflags & USART_ISR_ORE) != RESET) + && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) #endif { __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF); - + husart->ErrorCode |= HAL_USART_ERROR_ORE; } - + #if defined(USART_CR2_SLVEN) /* USART SPI slave underrun error interrupt occurred -------------------------*/ - if(((isrflags & USART_ISR_UDR) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_UDR) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { /* Ignore SPI slave underrun errors when reception is going on */ if (husart->State == HAL_USART_STATE_BUSY_RX) @@ -1687,58 +2043,61 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) } } #endif - + /* Call USART Error Call back function if need be --------------------------*/ - if(husart->ErrorCode != HAL_USART_ERROR_NONE) + if (husart->ErrorCode != HAL_USART_ERROR_NONE) { /* USART in mode Receiver ---------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) - && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET))) + if (((isrflags & USART_ISR_RXNE_RXFNE) != RESET) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) + || ((cr3its & USART_CR3_RXFTIE) != RESET))) #else - if(((isrflags & USART_ISR_RXNE) != RESET) - && ((cr1its & USART_CR1_RXNEIE) != RESET)) + if (((isrflags & USART_ISR_RXNE) != RESET) + && ((cr1its & USART_CR1_RXNEIE) != RESET)) #endif { - if (husart->RxISR != NULL) {husart->RxISR(husart);} + if (husart->RxISR != NULL) + { + husart->RxISR(husart); + } } - + /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) || (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))) - { + { /* Blocking error : transfer is aborted Set the USART state ready to be able to start again the process, Disable Interrupts, and disable DMA requests, if ongoing */ USART_EndTransfer(husart); - + /* Disable the USART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR); - + /* Abort the USART DMA Tx channel */ - if(husart->hdmatx != NULL) + if (husart->hdmatx != NULL) { /* Set the USART Tx DMA Abort callback to NULL : no callback executed at end of DMA abort procedure */ husart->hdmatx->XferAbortCallback = NULL; - + /* Abort DMA TX */ HAL_DMA_Abort_IT(husart->hdmatx); } - + /* Abort the USART DMA Rx channel */ - if(husart->hdmarx != NULL) + if (husart->hdmarx != NULL) { - /* Set the USART Rx DMA Abort callback : + /* Set the USART Rx DMA Abort callback : will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */ husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError; - + /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) { /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */ husart->hdmarx->XferAbortCallback(husart->hdmarx); @@ -1747,61 +2106,94 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) else { /* Call user error callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } } else { /* Call user error callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } } else { - /* Non Blocking error : transfer could go on. + /* Non Blocking error : transfer could go on. Error is notified to user through user error callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ husart->ErrorCode = HAL_USART_ERROR_NONE; } } return; - + } /* End if some error occurs */ - - + + /* USART in mode Transmitter ------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_TXE_TXFNF) != RESET) - && ( ((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET) - || ((cr3its & USART_CR3_TXFTIE) != RESET))) + if (((isrflags & USART_ISR_TXE_TXFNF) != RESET) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET) + || ((cr3its & USART_CR3_TXFTIE) != RESET))) #else - if(((isrflags & USART_ISR_TXE) != RESET) - && ((cr1its & USART_CR1_TXEIE) != RESET)) + if (((isrflags & USART_ISR_TXE) != RESET) + && ((cr1its & USART_CR1_TXEIE) != RESET)) #endif { - if (husart->TxISR != NULL) {husart->TxISR(husart);} + if (husart->TxISR != NULL) + { + husart->TxISR(husart); + } return; } - + /* USART in mode Transmitter (transmission end) -----------------------------*/ - if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) + if (((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) { USART_EndTransmit_IT(husart); return; } - + #if defined(USART_CR1_FIFOEN) /* USART TX Fifo Empty occurred ----------------------------------------------*/ - if(((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET)) + if (((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET)) { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + husart->TxFifoEmptyCallback(husart); +#else + /* Call legacy weak Tx Fifo Empty Callback */ HAL_USARTEx_TxFifoEmptyCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ return; } - + /* USART RX Fifo Full occurred ----------------------------------------------*/ - if(((isrflags & USART_ISR_RXFF) != RESET) && ((cr1its & USART_CR1_RXFFIE) != RESET)) + if (((isrflags & USART_ISR_RXFF) != RESET) && ((cr1its & USART_CR1_RXFFIE) != RESET)) { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + husart->RxFifoFullCallback(husart); +#else + /* Call legacy weak Rx Fifo Full Callback */ HAL_USARTEx_RxFifoFullCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ return; } #endif @@ -1816,7 +2208,7 @@ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_TxCpltCallback can be implemented in the user file. */ @@ -1827,11 +2219,11 @@ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) * @param husart USART handle. * @retval None */ - __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) +__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE: This function should not be modified, when the callback is needed, the HAL_USART_TxHalfCpltCallback can be implemented in the user file. */ @@ -1846,7 +2238,7 @@ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE: This function should not be modified, when the callback is needed, the HAL_USART_RxCpltCallback can be implemented in the user file. */ @@ -1861,7 +2253,7 @@ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_RxHalfCpltCallback can be implemented in the user file */ @@ -1876,7 +2268,7 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_TxRxCpltCallback can be implemented in the user file */ @@ -1891,7 +2283,7 @@ __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_ErrorCallback can be implemented in the user file. */ @@ -1902,7 +2294,7 @@ __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) * @param husart USART handle. * @retval None */ -__weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart) +__weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); @@ -1967,6 +2359,29 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) * @{ */ +/** + * @brief Initialize the callbacks to their default values. + * @param husart USART handle. + * @retval none + */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart) +{ + /* Init the USART Callback settings */ + husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ + husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ +#if defined(USART_CR1_FIFOEN) + husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ +#endif +} +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + /** * @brief End ongoing transfer on USART peripheral (following error detection or Transfer completion). * @param husart USART handle. @@ -1995,14 +2410,14 @@ static void USART_EndTransfer(USART_HandleTypeDef *husart) */ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent); + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); /* DMA Normal mode */ - if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) - { - husart->TxXferCount = 0; + if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) + { + husart->TxXferCount = 0U; - if(husart->State == HAL_USART_STATE_BUSY_TX) + if (husart->State == HAL_USART_STATE_BUSY_TX) { /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the USART CR3 register */ @@ -2015,11 +2430,17 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* DMA Circular mode */ else { - if(husart->State == HAL_USART_STATE_BUSY_TX) + if (husart->State == HAL_USART_STATE_BUSY_TX) { - HAL_USART_TxCpltCallback(husart); - } - } +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Complete Callback */ + husart->TxCpltCallback(husart); +#else + /* Call legacy weak Tx Complete Callback */ + HAL_USART_TxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } } /** @@ -2029,9 +2450,15 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { - USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent); + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Half Complete Callback */ + husart->TxHalfCpltCallback(husart); +#else + /* Call legacy weak Tx Half Complete Callback */ HAL_USART_TxHalfCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } /** @@ -2041,46 +2468,70 @@ static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) */ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent); - + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + /* DMA Normal mode */ - if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) + if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { - husart->RxXferCount = 0; - + husart->RxXferCount = 0U; + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - + /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit in USART CR3 register */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* similarly, disable the DMA TX transfer that was started to provide the clock to the slave device */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - - if(husart->State == HAL_USART_STATE_BUSY_RX) + + if (husart->State == HAL_USART_STATE_BUSY_RX) { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ else { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } - husart->State= HAL_USART_STATE_READY; + husart->State = HAL_USART_STATE_READY; } /* DMA circular mode */ else { - if(husart->State == HAL_USART_STATE_BUSY_RX) + if (husart->State == HAL_USART_STATE_BUSY_RX) { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ else { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } } } @@ -2092,9 +2543,15 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { - USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent); + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Half Complete Callback */ + husart->RxHalfCpltCallback(husart); +#else + /* Call legacy weak Rx Half Complete Callback */ HAL_USART_RxHalfCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } /** @@ -2104,16 +2561,22 @@ static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) */ static void USART_DMAError(DMA_HandleTypeDef *hdma) { - USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent); + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); - husart->RxXferCount = 0; - husart->TxXferCount = 0; + husart->RxXferCount = 0U; + husart->TxXferCount = 0U; USART_EndTransfer(husart); husart->ErrorCode |= HAL_USART_ERROR_DMA; - husart->State= HAL_USART_STATE_READY; + husart->State = HAL_USART_STATE_READY; +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } /** @@ -2124,11 +2587,17 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma) */ static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent); - husart->RxXferCount = 0; - husart->TxXferCount = 0; + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + husart->RxXferCount = 0U; + husart->TxXferCount = 0U; +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } /** @@ -2141,22 +2610,22 @@ static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma) */ static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { - USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent); - + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + husart->hdmatx->XferAbortCallback = NULL; /* Check if an Abort process is still ongoing */ - if(husart->hdmarx != NULL) + if (husart->hdmarx != NULL) { - if(husart->hdmarx->XferAbortCallback != NULL) + if (husart->hdmarx->XferAbortCallback != NULL) { return; } } - + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - husart->TxXferCount = 0; - husart->RxXferCount = 0; + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; /* Reset errorCode */ husart->ErrorCode = HAL_USART_ERROR_NONE; @@ -2168,7 +2637,14 @@ static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) husart->State = HAL_USART_STATE_READY; /* Call user Abort complete callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->AbortCpltCallback(husart); +#else + /* Call legacy weak Abort Complete Callback */ HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } @@ -2182,22 +2658,22 @@ static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) */ static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { - USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent); - + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + husart->hdmarx->XferAbortCallback = NULL; /* Check if an Abort process is still ongoing */ - if(husart->hdmatx != NULL) + if (husart->hdmatx != NULL) { - if(husart->hdmatx->XferAbortCallback != NULL) + if (husart->hdmatx->XferAbortCallback != NULL) { return; } } - + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - husart->TxXferCount = 0; - husart->RxXferCount = 0; + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; /* Reset errorCode */ husart->ErrorCode = HAL_USART_ERROR_NONE; @@ -2209,7 +2685,13 @@ static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) husart->State = HAL_USART_STATE_READY; /* Call user Abort complete callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->AbortCpltCallback(husart); +#else + /* Call legacy weak Abort Complete Callback */ HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } @@ -2225,18 +2707,18 @@ static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ - while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status) + while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { - husart->State= HAL_USART_STATE_READY; - + husart->State = HAL_USART_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_TIMEOUT; } } @@ -2251,11 +2733,11 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar */ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) { - uint32_t tmpreg = 0x0; + uint32_t tmpreg = 0x0U; USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED; HAL_StatusTypeDef ret = HAL_OK; uint16_t brrtemp = 0x0000; - uint16_t usartdiv = 0x0000; + uint32_t usartdiv = 0x00000000; /* Check the parameters */ assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); @@ -2269,14 +2751,14 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) #if defined(USART_PRESC_PRESCALER) assert_param(IS_USART_PRESCALER(husart->Init.ClockPrescaler)); #endif - + /*-------------------------- USART CR1 Configuration -----------------------*/ - /* Clear M, PCE, PS, TE and RE bits and configure - * the USART Word Length, Parity and Mode: - * set the M bits according to husart->Init.WordLength value - * set PCE and PS bits according to husart->Init.Parity value - * set TE and RE bits according to husart->Init.Mode value - * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */ + /* Clear M, PCE, PS, TE and RE bits and configure + * the USART Word Length, Parity and Mode: + * set the M bits according to husart->Init.WordLength value + * set PCE and PS bits according to husart->Init.Parity value + * set TE and RE bits according to husart->Init.Mode value + * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */ tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8; MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg); @@ -2286,7 +2768,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) * set CPHA bit according to husart->Init.CLKPhase value * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only) * set STOP[13:12] bits according to husart->Init.StopBits value */ - tmpreg = 0; + tmpreg = 0U; tmpreg = (uint32_t)(USART_CLOCK_ENABLE); tmpreg |= (uint32_t)husart->Init.CLKLastBit; tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase); @@ -2301,56 +2783,56 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) #endif /*-------------------------- USART BRR Configuration -----------------------*/ - /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */ + /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */ USART_GETCLOCKSOURCE(husart, clocksource); - + switch (clocksource) { - case USART_CLOCKSOURCE_PCLK1: + case USART_CLOCKSOURCE_PCLK1: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate)); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate)); #endif - break; - case USART_CLOCKSOURCE_PCLK2: + break; + case USART_CLOCKSOURCE_PCLK2: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate)); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate)); #endif - break; - case USART_CLOCKSOURCE_HSI: + break; + case USART_CLOCKSOURCE_HSI: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate)); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate)); #endif - break; - case USART_CLOCKSOURCE_SYSCLK: + break; + case USART_CLOCKSOURCE_SYSCLK: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), husart->Init.BaudRate)); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), husart->Init.BaudRate)); #endif - break; - case USART_CLOCKSOURCE_LSE: + break; + case USART_CLOCKSOURCE_LSE: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate)); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate)); #endif - break; - case USART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; + break; + case USART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; } - - /* USARTDIV must be greater than or equal to 0d16 */ - if (usartdiv >= USART_BRR_MIN) + + /* USARTDIV must be greater than or equal to 0d16 and smaller than or equal to ffff */ + if ((usartdiv >= USART_BRR_MIN) && (usartdiv <= USART_BRR_MAX)) { - brrtemp = usartdiv & 0xFFF0U; + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); husart->Instance->BRR = brrtemp; } @@ -2358,28 +2840,28 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) { ret = HAL_ERROR; } - + #if defined(USART_CR1_FIFOEN) /* Initialize the number of data to process during RX/TX ISR execution */ - husart->NbTxDataToProcess = 1; - husart->NbRxDataToProcess = 1; + husart->NbTxDataToProcess = 1U; + husart->NbRxDataToProcess = 1U; #endif - + /* Clear ISR function pointers */ husart->RxISR = NULL; husart->TxISR = NULL; - + return ret; } /** * @brief Check the USART Idle State. - * @param husart: USART handle. + * @param husart USART handle. * @retval HAL status */ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Initialize the USART ErrorCode */ husart->ErrorCode = HAL_USART_ERROR_NONE; @@ -2388,20 +2870,20 @@ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) tickstart = HAL_GetTick(); /* Check if the Transmitter is enabled */ - if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + if ((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) { /* Wait until TEACK flag is set */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) + if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; } } /* Check if the Receiver is enabled */ - if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + if ((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) { /* Wait until REACK flag is set */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) + if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; @@ -2409,7 +2891,7 @@ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) } /* Initialize the USART state*/ - husart->State= HAL_USART_STATE_READY; + husart->State = HAL_USART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(husart); @@ -2433,11 +2915,11 @@ static void USART_TxISR_8BIT(USART_HandleTypeDef *husart) if ((husart->State == HAL_USART_STATE_BUSY_TX) || (husart->State == HAL_USART_STATE_BUSY_TX_RX)) { - if(husart->TxXferCount == 0) + if (husart->TxXferCount == 0U) { /* Disable the USART Transmit data register empty interrupt */ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); - + /* Enable the USART Transmit Complete Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_TC); } @@ -2461,24 +2943,24 @@ static void USART_TxISR_8BIT(USART_HandleTypeDef *husart) */ static void USART_TxISR_16BIT(USART_HandleTypeDef *husart) { - uint16_t* tmp; - + uint16_t *tmp; + if ((husart->State == HAL_USART_STATE_BUSY_TX) || (husart->State == HAL_USART_STATE_BUSY_TX_RX)) { - if(husart->TxXferCount == 0) + if (husart->TxXferCount == 0U) { /* Disable the USART Transmit data register empty interrupt */ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); - + /* Enable the USART Transmit Complete Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_TC); } else { - tmp = (uint16_t*) husart->pTxBuffPtr; + tmp = (uint16_t *) husart->pTxBuffPtr; husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - husart->pTxBuffPtr += 2; + husart->pTxBuffPtr += 2U; husart->TxXferCount--; } } @@ -2502,16 +2984,16 @@ static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) if ((husart->State == HAL_USART_STATE_BUSY_TX) || (husart->State == HAL_USART_STATE_BUSY_TX_RX)) { - for(nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) + for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) { - if(husart->TxXferCount == 0) + if (husart->TxXferCount == 0U) { /* Disable the TX FIFO threshold interrupt */ __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT); - + /* Enable the USART Transmit Complete Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_TC); - + break; /* force exit loop */ } else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET) @@ -2519,7 +3001,7 @@ static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF); husart->TxXferCount--; } - } + } } } @@ -2535,30 +3017,30 @@ static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) */ static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) { - uint16_t* tmp; + uint16_t *tmp; uint8_t nb_tx_data; - + /* Check that a Tx process is ongoing */ if ((husart->State == HAL_USART_STATE_BUSY_TX) || (husart->State == HAL_USART_STATE_BUSY_TX_RX)) { - for(nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) - { - if(husart->TxXferCount == 0) + for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (husart->TxXferCount == 0U) { /* Disable the TX FIFO threshold interrupt */ __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT); - + /* Enable the USART Transmit Complete Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_TC); - + break; /* force exit loop */ } else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET) { - tmp = (uint16_t*) husart->pTxBuffPtr; + tmp = (uint16_t *) husart->pTxBuffPtr; husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - husart->pTxBuffPtr += 2; + husart->pTxBuffPtr += 2U; husart->TxXferCount--; } } @@ -2566,7 +3048,6 @@ static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) } #endif - /** * @brief Wraps up transmission in non-blocking mode. * @param husart Pointer to a USART_HandleTypeDef structure that contains @@ -2583,24 +3064,36 @@ static void USART_EndTransmit_IT(USART_HandleTypeDef *husart) /* Clear TxISR function pointer */ husart->TxISR = NULL; - + if (husart->State == HAL_USART_STATE_BUSY_TX) { /* Clear overrun flag and discard the received data */ __HAL_USART_CLEAR_OREFLAG(husart); __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); - + /* Tx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Complete Callback */ + husart->TxCpltCallback(husart); +#else + /* Call legacy weak Tx Complete Callback */ HAL_USART_TxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } - else if (husart->RxXferCount == 0) + else if (husart->RxXferCount == 0U) { /* TxRx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } } @@ -2617,13 +3110,13 @@ static void USART_EndTransmit_IT(USART_HandleTypeDef *husart) static void USART_RxISR_8BIT(USART_HandleTypeDef *husart) { uint16_t uhMask = husart->Mask; - + if ((husart->State == HAL_USART_STATE_BUSY_RX) || (husart->State == HAL_USART_STATE_BUSY_TX_RX)) { *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); - - if(--husart->RxXferCount == 0) + + if (--husart->RxXferCount == 0U) { /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ #if defined(USART_CR1_FIFOEN) @@ -2631,14 +3124,14 @@ static void USART_RxISR_8BIT(USART_HandleTypeDef *husart) #else CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); #endif - + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); /* Clear RxISR function pointer */ husart->RxISR = NULL; - - if(husart->State == HAL_USART_STATE_BUSY_RX) + + if (husart->State == HAL_USART_STATE_BUSY_RX) { #if defined(USART_CR2_SLVEN) /* Clear SPI slave underrun flag and discard transmit data */ @@ -2648,31 +3141,43 @@ static void USART_RxISR_8BIT(USART_HandleTypeDef *husart) __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); } #endif - + /* Rx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } - else if ((husart->TxXferCount == 0) && + else if ((husart->TxXferCount == 0U) && (READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE)) { /* TxRx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } } #if defined(USART_CR2_SLVEN) - else if ( (husart->State == HAL_USART_STATE_BUSY_RX) && - (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + else if ((husart->State == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) #else else if (husart->State == HAL_USART_STATE_BUSY_RX) #endif { /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); - } + } } } @@ -2687,17 +3192,17 @@ static void USART_RxISR_8BIT(USART_HandleTypeDef *husart) */ static void USART_RxISR_16BIT(USART_HandleTypeDef *husart) { - uint16_t* tmp; + uint16_t *tmp; uint16_t uhMask = husart->Mask; if ((husart->State == HAL_USART_STATE_BUSY_RX) || (husart->State == HAL_USART_STATE_BUSY_TX_RX)) { - tmp = (uint16_t*) husart->pRxBuffPtr; + tmp = (uint16_t *) husart->pRxBuffPtr; *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - husart->pRxBuffPtr += 2; - - if(--husart->RxXferCount == 0) + husart->pRxBuffPtr += 2U; + + if (--husart->RxXferCount == 0U) { /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ #if defined(USART_CR1_FIFOEN) @@ -2711,8 +3216,8 @@ static void USART_RxISR_16BIT(USART_HandleTypeDef *husart) /* Clear RxISR function pointer */ husart->RxISR = NULL; - - if(husart->State == HAL_USART_STATE_BUSY_RX) + + if (husart->State == HAL_USART_STATE_BUSY_RX) { #if defined(USART_CR2_SLVEN) /* Clear SPI slave underrun flag and discard transmit data */ @@ -2722,24 +3227,36 @@ static void USART_RxISR_16BIT(USART_HandleTypeDef *husart) __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); } #endif - + /* Rx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } - else if ((husart->TxXferCount == 0) && + else if ((husart->TxXferCount == 0U) && (READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE)) { /* TxRx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } } #if defined(USART_CR2_SLVEN) - else if ( (husart->State == HAL_USART_STATE_BUSY_RX) && - (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + else if ((husart->State == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) #else else if (husart->State == HAL_USART_STATE_BUSY_RX) #endif @@ -2757,35 +3274,35 @@ static void USART_RxISR_16BIT(USART_HandleTypeDef *husart) * interruptions have been enabled by HAL_USART_Receive_IT(). * @note ISR function executed when FIFO mode is enabled and when the * data word length is less than 9 bits long. + * @param husart USART handle * @retval None - * @retval HAL status */ static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) { uint16_t uhMask = husart->Mask; uint8_t nb_rx_data; - + /* Check that a Rx process is ongoing */ if ((husart->State == HAL_USART_STATE_BUSY_RX) || (husart->State == HAL_USART_STATE_BUSY_TX_RX)) { - for(nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) - { + for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) + { if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET) { *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); - - if(--husart->RxXferCount == 0) + + if (--husart->RxXferCount == 0U) { /* Disable the USART Parity Error Interrupt */ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); - + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - + /* Clear RxISR function pointer */ husart->RxISR = NULL; - + if (husart->State == HAL_USART_STATE_BUSY_RX) { #if defined(USART_CR2_SLVEN) @@ -2796,20 +3313,32 @@ static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); } #endif - + /* Rx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } - else if ((husart->TxXferCount == 0) && + else if ((husart->TxXferCount == 0U) && (READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE)) { /* TxRx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ HAL_USART_TxRxCpltCallback(husart); - } +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } } #if defined(USART_CR2_SLVEN) else if ((husart->State == HAL_USART_STATE_BUSY_RX) && @@ -2823,29 +3352,29 @@ static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) } } } - - /* When remaining number of bytes to receive is less than the RX FIFO - threshold, next incoming frames are processed as if FIFO mode was + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ if (((husart->RxXferCount != 0U)) && (husart->RxXferCount < husart->NbRxDataToProcess)) { /* Disable the USART RXFT interrupt*/ CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); - + /* Update the RxISR function pointer */ husart->RxISR = USART_RxISR_8BIT; - + /* Enable the USART Data Register Not Empty interrupt */ SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); - + #if defined(USART_CR2_SLVEN) - if ( (husart->State == HAL_USART_STATE_BUSY_TX_RX) && - (husart->SlaveMode == USART_SLAVEMODE_DISABLE) && - (husart->TxXferCount == 0U)) + if ((husart->State == HAL_USART_STATE_BUSY_TX_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE) && + (husart->TxXferCount == 0U)) #else - if ( (husart->State == HAL_USART_STATE_BUSY_TX_RX) && - (husart->TxXferCount == 0U)) + if ((husart->State == HAL_USART_STATE_BUSY_TX_RX) && + (husart->TxXferCount == 0U)) #endif { /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ @@ -2871,34 +3400,34 @@ static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) */ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) { - uint16_t* tmp; + uint16_t *tmp; uint16_t uhMask = husart->Mask; uint8_t nb_rx_data; - + /* Check that a Tx process is ongoing */ if ((husart->State == HAL_USART_STATE_BUSY_RX) || (husart->State == HAL_USART_STATE_BUSY_TX_RX)) { - for(nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) - { + for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) + { if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET) { - tmp = (uint16_t*) husart->pRxBuffPtr; + tmp = (uint16_t *) husart->pRxBuffPtr; *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - husart->pRxBuffPtr += 2; - - if(--husart->RxXferCount == 0) + husart->pRxBuffPtr += 2U; + + if (--husart->RxXferCount == 0U) { /* Disable the USART Parity Error Interrupt */ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); - + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - + /* Clear RxISR function pointer */ husart->RxISR = NULL; - - if(husart->State == HAL_USART_STATE_BUSY_RX) + + if (husart->State == HAL_USART_STATE_BUSY_RX) { #if defined(USART_CR2_SLVEN) /* Clear SPI slave underrun flag and discard transmit data */ @@ -2908,19 +3437,31 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); } #endif - + /* Rx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ HAL_USART_RxCpltCallback(husart); - } - else if ((husart->TxXferCount == 0) && +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((husart->TxXferCount == 0U) && (READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE)) { /* TxRx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } } #if defined(USART_CR2_SLVEN) @@ -2935,29 +3476,29 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) } } } - - /* When remaining number of bytes to receive is less than the RX FIFO - threshold, next incoming frames are processed as if FIFO mode was + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ if (((husart->RxXferCount != 0U)) && (husart->RxXferCount < husart->NbRxDataToProcess)) { /* Disable the USART RXFT interrupt*/ CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); - + /* Update the RxISR function pointer */ husart->RxISR = USART_RxISR_16BIT; - + /* Enable the USART Data Register Not Empty interrupt */ SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); - + #if defined(USART_CR2_SLVEN) - if ( (husart->State == HAL_USART_STATE_BUSY_TX_RX) && - (husart->SlaveMode == USART_SLAVEMODE_DISABLE) && - (husart->TxXferCount == 0U)) + if ((husart->State == HAL_USART_STATE_BUSY_TX_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE) && + (husart->TxXferCount == 0U)) #else - if ( (husart->State == HAL_USART_STATE_BUSY_TX_RX) && - (husart->TxXferCount == 0U)) + if ((husart->State == HAL_USART_STATE_BUSY_TX_RX) && + (husart->TxXferCount == 0U)) #endif { /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart_ex.c index 13780cc5f3..dbcf6567ec 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart_ex.c @@ -15,13 +15,13 @@ (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. - -@- When USART operates in FIFO mode, FIFO mode must be enabled prior - starting RX/TX transfers. Also RX/TX FIFO thresholds must be + -@- When USART operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be configured prior starting RX/TX transfers. (#) Slave mode enabling/disabling and NSS pin configuration. - -@- When USART operates in Slave mode, Slave mode must be enabled prior + -@- When USART operates in Slave mode, Slave mode must be enabled prior starting RX/TX transfers. @endverbatim @@ -70,6 +70,14 @@ #ifdef HAL_USART_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ +#if defined(USART_CR1_FIFOEN) +/* UART RX FIFO depth */ +#define RX_FIFO_DEPTH 8U + +/* UART TX FIFO depth */ +#define TX_FIFO_DEPTH 8U + +#endif /* Private define ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -113,7 +121,7 @@ static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart); * @param husart USART handle. * @retval None */ -__weak void HAL_USARTEx_RxFifoFullCallback (USART_HandleTypeDef *husart) +__weak void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); @@ -128,7 +136,7 @@ __weak void HAL_USARTEx_RxFifoFullCallback (USART_HandleTypeDef *husart) * @param husart USART handle. * @retval None */ -__weak void HAL_USARTEx_TxFifoEmptyCallback (USART_HandleTypeDef *husart) +__weak void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); @@ -173,7 +181,7 @@ __weak void HAL_USARTEx_TxFifoEmptyCallback (USART_HandleTypeDef *husart) * @note In SPI slave mode, the USART must be enabled before starting the master * communications (or between frames while the clock is stable). Otherwise, * if the USART slave is enabled while the master is in the middle of a - * frame, it will become desynchronized with the master. + * frame, it will become desynchronized with the master. * @note The data register of the slave needs to be ready before the first edge * of the communication clock or before the end of the ongoing communication, * otherwise the SPI slave will transmit zeros. @@ -182,45 +190,45 @@ __weak void HAL_USARTEx_TxFifoEmptyCallback (USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart) { - uint32_t tmpcr1 = 0; + uint32_t tmpcr1 = 0U; /* Check parameters */ assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); - + /* Process Locked */ __HAL_LOCK(husart); - + husart->State = HAL_USART_STATE_BUSY; - + /* Save actual USART configuration */ tmpcr1 = READ_REG(husart->Instance->CR1); - + /* Disable USART */ __HAL_USART_DISABLE(husart); - + /* In SPI slave mode mode, the following bits must be kept cleared: - LINEN and CLKEN bit in the USART_CR2 register - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - + /* Enable SPI slave mode */ SET_BIT(husart->Instance->CR2, USART_CR2_SLVEN); - + /* Restore USART configuration */ WRITE_REG(husart->Instance->CR1, tmpcr1); - + husart->SlaveMode = USART_SLAVEMODE_ENABLE; - + husart->State = HAL_USART_STATE_READY; - + /* Enable USART */ __HAL_USART_ENABLE(husart); - + /* Process Unlocked */ __HAL_UNLOCK(husart); - - return HAL_OK; + + return HAL_OK; } /** @@ -230,36 +238,36 @@ HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart) { - uint32_t tmpcr1 = 0; + uint32_t tmpcr1 = 0U; /* Check parameters */ assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); - + /* Process Locked */ __HAL_LOCK(husart); - + husart->State = HAL_USART_STATE_BUSY; - + /* Save actual USART configuration */ tmpcr1 = READ_REG(husart->Instance->CR1); - + /* Disable USART */ __HAL_USART_DISABLE(husart); /* Disable SPI slave mode */ CLEAR_BIT(husart->Instance->CR2, USART_CR2_SLVEN); - + /* Restore USART configuration */ WRITE_REG(husart->Instance->CR1, tmpcr1); husart->SlaveMode = USART_SLAVEMODE_ENABLE; - + husart->State = HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - - return HAL_OK; + + return HAL_OK; } /** @@ -278,31 +286,31 @@ HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig) { - uint32_t tmpcr1 = 0; + uint32_t tmpcr1 = 0U; /* Check parameters */ assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); assert_param(IS_USART_NSS(NSSConfig)); - + /* Process Locked */ __HAL_LOCK(husart); - + husart->State = HAL_USART_STATE_BUSY; - + /* Save actual USART configuration */ tmpcr1 = READ_REG(husart->Instance->CR1); - + /* Disable USART */ __HAL_USART_DISABLE(husart); /* Program DIS_NSS bit in the USART_CR2 register */ MODIFY_REG(husart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig); - + /* Restore USART configuration */ WRITE_REG(husart->Instance->CR1, tmpcr1); - + husart->State = HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); @@ -318,37 +326,37 @@ HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NS */ HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart) { - uint32_t tmpcr1 = 0; - + uint32_t tmpcr1 = 0U; + /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); /* Process Locked */ __HAL_LOCK(husart); - + husart->State = HAL_USART_STATE_BUSY; - + /* Save actual USART configuration */ tmpcr1 = READ_REG(husart->Instance->CR1); - + /* Disable USART */ __HAL_USART_DISABLE(husart); - + /* Enable FIFO mode */ SET_BIT(tmpcr1, USART_CR1_FIFOEN); husart->FifoMode = USART_FIFOMODE_ENABLE; - + /* Restore USART configuration */ WRITE_REG(husart->Instance->CR1, tmpcr1); - + /* Determine the number of data to process during RX/TX ISR execution */ USARTEx_SetNbDataToProcess(husart); - + husart->State = HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } @@ -359,34 +367,34 @@ HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) { - uint32_t tmpcr1 = 0; + uint32_t tmpcr1 = 0U; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); /* Process Locked */ __HAL_LOCK(husart); - + husart->State = HAL_USART_STATE_BUSY; - + /* Save actual USART configuration */ tmpcr1 = READ_REG(husart->Instance->CR1); - + /* Disable USART */ __HAL_USART_DISABLE(husart); - + /* Enable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); husart->FifoMode = USART_FIFOMODE_DISABLE; - + /* Restore USART configuration */ WRITE_REG(husart->Instance->CR1, tmpcr1); - + husart->State = HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } @@ -405,37 +413,37 @@ HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold) { - uint32_t tmpcr1 = 0; - + uint32_t tmpcr1 = 0U; + /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); assert_param(IS_USART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(husart); - + husart->State = HAL_USART_STATE_BUSY; - + /* Save actual USART configuration */ tmpcr1 = READ_REG(husart->Instance->CR1); - + /* Disable USART */ __HAL_USART_DISABLE(husart); - + /* Update TX threshold configuration */ MODIFY_REG(husart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); - + /* Determine the number of data to process during RX/TX ISR execution */ USARTEx_SetNbDataToProcess(husart); - + /* Restore USART configuration */ WRITE_REG(husart->Instance->CR1, tmpcr1); - + husart->State = HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } @@ -454,37 +462,37 @@ HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, ui */ HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold) { - uint32_t tmpcr1 = 0; - + uint32_t tmpcr1 = 0U; + /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); assert_param(IS_USART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(husart); - + husart->State = HAL_USART_STATE_BUSY; - + /* Save actual USART configuration */ tmpcr1 = READ_REG(husart->Instance->CR1); - + /* Disable USART */ __HAL_USART_DISABLE(husart); - + /* Update RX threshold configuration */ MODIFY_REG(husart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); - + /* Determine the number of data to process during RX/TX ISR execution */ USARTEx_SetNbDataToProcess(husart); - + /* Restore USART configuration */ WRITE_REG(husart->Instance->CR1, tmpcr1); - + husart->State = HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } #endif @@ -509,7 +517,7 @@ HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, ui * @param husart USART handle. * @retval None */ -void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) +static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) { uint8_t rx_fifo_depth; uint8_t tx_fifo_depth; @@ -517,20 +525,20 @@ void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) uint8_t tx_fifo_threshold; uint8_t numerator[] = {1, 1, 1, 3, 7, 1}; uint8_t denominator[] = {8, 4, 2, 4, 8, 1}; - + if (husart->FifoMode == USART_FIFOMODE_DISABLE) { - husart->NbTxDataToProcess = 1; - husart->NbRxDataToProcess = 1; + husart->NbTxDataToProcess = 1U; + husart->NbRxDataToProcess = 1U; } else { - rx_fifo_depth = 8; /* RX Fifo size */ - tx_fifo_depth = 8; /* TX Fifo size */ - rx_fifo_threshold = (uint8_t)(READ_BIT(husart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); - tx_fifo_threshold = (uint8_t)(READ_BIT(husart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); - husart->NbTxDataToProcess = (uint8_t)(tx_fifo_depth * numerator[tx_fifo_threshold])/denominator[tx_fifo_threshold]; - husart->NbRxDataToProcess = (uint8_t)(rx_fifo_depth * numerator[rx_fifo_threshold])/denominator[rx_fifo_threshold]; + rx_fifo_depth = RX_FIFO_DEPTH; + tx_fifo_depth = TX_FIFO_DEPTH; + rx_fifo_threshold = (READ_BIT(husart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); + tx_fifo_threshold = (READ_BIT(husart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); + husart->NbTxDataToProcess = (tx_fifo_depth * numerator[tx_fifo_threshold]) / denominator[tx_fifo_threshold]; + husart->NbRxDataToProcess = (rx_fifo_depth * numerator[rx_fifo_threshold]) / denominator[rx_fifo_threshold]; } } #endif diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_wwdg.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_wwdg.c index 0cd53478e7..1fa6ef77bd 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_wwdg.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_wwdg.c @@ -3,92 +3,100 @@ * @file stm32l4xx_hal_wwdg.c * @author MCD Application Team * @brief WWDG HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: - * + Initialization and Configuration function + * + Initialization and Configuration functions * + IO operation functions @verbatim ============================================================================== - ##### WWDG specific features ##### + ##### WWDG Specific features ##### ============================================================================== [..] Once enabled the WWDG generates a system reset on expiry of a programmed time period, unless the program refreshes the counter (T[6;0] downcounter) before reaching 0x3F value (i.e. a reset is generated when the counter - value rolls over from 0x40 to 0x3F). + value rolls down from 0x40 to 0x3F). (+) An MCU reset is also generated if the counter value is refreshed before the counter has reached the refresh window value. This implies that the counter must be refreshed in a limited window. - (+) Once enabled the WWDG cannot be disabled except by a system reset. - - (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has - occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)). - - (+) The WWDG downcounter input clock is derived from the APB clock divided + (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG + reset occurs. + (+) The WWDG counter input clock is derived from the APB clock divided by a programmable prescaler. - - (+) WWDG downcounter clock (Hz) = PCLK1 / (4096 * Prescaler) - - (+) WWDG timeout (ms) = (1000 * (T[5;0] + 1)) / (WWDG downcounter clock) - where T[5;0] are the lowest 6 bits of downcounter. - + (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler) + (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz) + where T[5;0] are the lowest 6 bits of Counter. (+) WWDG Counter refresh is allowed between the following limits : - (++) min time (ms) = (1000 * (T[5;0] - Window)) / (WWDG downcounter clock) - (++) max time (ms) = (1000 * (T[5;0] - 0x40)) / (WWDG downcounter clock) - - (+) Min-max timeout value @80 MHz(PCLK1): ~51.2 us / ~26.22 ms - - (+) The Early Wakeup Interrupt (EWI) can be used if specific safety - operations or data logging must be performed before the actual reset is - generated. When the downcounter reaches the value 0x40, an EWI interrupt - is generated and the corresponding interrupt service routine (ISR) can - be used to trigger specific actions (such as communications or data - logging), before resetting the device. - In some applications, the EWI interrupt can be used to manage a software - system check and/or system recovery/graceful degradation, without - generating a WWDG reset. In this case, the corresponding interrupt - service routine (ISR) should reload the WWDG counter to avoid the WWDG - reset, then trigger the required actions. - Note:When the EWI interrupt cannot be served, e.g. due to a system lock - in a higher priority task, the WWDG reset will eventually be generated. - - (+) Debug mode : When the microcontroller enters debug mode (core halted), - the WWDG counter either continues to work normally or stops, depending - on DBG_WWDG_STOP configuration bit in DBG module, accessible through - __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros + (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock + (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock + (+) Typical values: + (++) Counter min (T[5;0] = 0x00) @80 MHz(PCLK1) with zero prescaler: + max timeout before reset: ~51.2 �s + (++) Counter max (T[5;0] = 0x3F) @80 MHz(PCLK1) with prescaler dividing by 128: + max timeout before reset: ~26.22 ms + ============================================================================== ##### How to use this driver ##### ============================================================================== [..] + *** Common driver usage *** + =========================== (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE(). - - (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup - Interrupt mode using using HAL_WWDG_Init() function. - This enables WWDG peripheral and the downcounter starts downcounting - from given counter value. - Init function can be called again to modify all watchdog parameters, - however if EWI mode has been set once, it can't be clear until next - reset. - - (+) The application program must refresh the WWDG counter at regular - intervals during normal operation to prevent an MCU reset using + (+) Set the WWDG prescaler, refresh window and counter value + using HAL_WWDG_Init() function. + (+) Start the WWDG using HAL_WWDG_Start() function. + When the WWDG is enabled the counter value should be configured to + a value greater than 0x40 to prevent generating an immediate reset. + (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is + generated when the counter reaches 0x40, and then start the WWDG using + HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can + add his own code by customization of callback HAL_WWDG_WakeupCallback. + Once enabled, EWI interrupt cannot be disabled except by a system reset. + (+) Then the application program must refresh the WWDG counter at regular + intervals during normal operation to prevent an MCU reset, using HAL_WWDG_Refresh() function. This operation must occur only when - the counter is lower than the window value already programmed. - - (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when - the counter reaches 0x40. User can add his own code in weak function - HAL_WWDG_EarlyWakeupCallback(). + the counter is lower than the refresh window value already programmed. - *** WWDG HAL driver macros list *** - ================================== - [..] - Below the list of most used macros in WWDG HAL driver. - - (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source. - (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status. - (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags. + [..] + *** Callback registration *** + ============================= + The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows + the user to configure dynamically the driver callbacks. Use Functions + @ref HAL_WWDG_RegisterCallback() to register a user callback. + + (+) Function @ref HAL_WWDG_RegisterCallback() allows to register following + callbacks: + (++) EwiCallback : callback for Early WakeUp Interrupt. + (++) MspInitCallback : WWDG MspInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + (+) Use function @ref HAL_WWDG_UnRegisterCallback() to reset a callback to + the default weak (surcharged) function. @ref HAL_WWDG_UnRegisterCallback() + takes as parameters the HAL peripheral handle and the Callback ID. + This function allows to reset following callbacks: + (++) EwiCallback : callback for Early WakeUp Interrupt. + (++) MspInitCallback : WWDG MspInit. + + When calling @ref HAL_WWDG_Init function, callbacks are reset to the + corresponding legacy weak (surcharged) functions: + @ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have + not been registered before. + + When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + *** WWDG HAL driver macros list *** + =================================== + [..] + Below the list of most used macros in WWDG HAL driver. + (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral + (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status + (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags + (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt @endverbatim ****************************************************************************** @@ -152,7 +160,7 @@ ============================================================================== ##### Initialization and Configuration functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to: (+) Initialize and start the WWDG according to the specified parameters in the WWDG_InitTypeDef of associated handle. @@ -172,7 +180,7 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) { /* Check the WWDG handle allocation */ - if(hwwdg == NULL) + if (hwwdg == NULL) { return HAL_ERROR; } @@ -184,8 +192,24 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter)); assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode)); +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) + /* Reset Callback pointers */ + if(hwwdg->EwiCallback == NULL) + { + hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback; + } + + if(hwwdg->MspInitCallback == NULL) + { + hwwdg->MspInitCallback = HAL_WWDG_MspInit; + } + + /* Init the low level hardware */ + hwwdg->MspInitCallback(hwwdg); +#else /* Init the low level hardware */ HAL_WWDG_MspInit(hwwdg); +#endif /* Set WWDG Counter */ WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter)); @@ -217,17 +241,93 @@ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) */ } + +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User WWDG Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hwwdg WWDG handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID + * @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + status = HAL_ERROR; + } + else + { + switch(CallbackID) + { + case HAL_WWDG_EWI_CB_ID: + hwwdg->EwiCallback = pCallback; + break; + + case HAL_WWDG_MSPINIT_CB_ID: + hwwdg->MspInitCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; + } + } + + return status; +} + + +/** + * @brief Unregister a WWDG Callback + * WWDG Callback is redirected to the weak (surcharged) predefined callback + * @param hwwdg WWDG handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID + * @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch(CallbackID) + { + case HAL_WWDG_EWI_CB_ID: + hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback; + break; + + case HAL_WWDG_MSPINIT_CB_ID: + hwwdg->MspInitCallback = HAL_WWDG_MspInit; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} +#endif + /** * @} */ /** @defgroup WWDG_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions + * @brief IO operation functions * @verbatim ============================================================================== ##### IO operation functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: (+) Refresh the WWDG. @@ -256,7 +356,7 @@ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg) * @brief Handle WWDG interrupt request. * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations * or data logging must be performed before the actual reset is generated. - * The EWI interrupt is enabled by calling HAL_WWDG_Init function with + * The EWI interrupt is enabled by calling HAL_WWDG_Init function with * EWIMode set to WWDG_EWI_ENABLE. * When the downcounter reaches the value 0x40, and EWI interrupt is * generated and the corresponding Interrupt Service Routine (ISR) can @@ -269,16 +369,21 @@ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg) void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) { /* Check if Early Wakeup Interrupt is enable */ - if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET) + if (__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET) { /* Check if WWDG Early Wakeup Interrupt occurred */ - if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET) + if (__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET) { /* Clear the WWDG Early Wakeup flag */ __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF); - /* Early Wakeup callback */ +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) + /* Early Wakeup registered callback */ + hwwdg->EwiCallback(hwwdg); +#else + /* Early Wakeup callback */ HAL_WWDG_EarlyWakeupCallback(hwwdg); +#endif } } } @@ -290,7 +395,7 @@ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) * the configuration information for the specified WWDG module. * @retval None */ -__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg) +__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg) { /* Prevent unused argument(s) compilation warning */ UNUSED(hwwdg); diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_adc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_adc.c index ba92146674..3ad5ed650d 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_adc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_adc.c @@ -512,7 +512,8 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) while (( LL_ADC_REG_IsStopConversionOngoing(ADCx) | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1U) { - if(timeout_cpu_cycles-- == 0U) + timeout_cpu_cycles--; + if(timeout_cpu_cycles == 0U) { /* Time-out error */ status = ERROR; @@ -531,7 +532,8 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES; while (LL_ADC_IsDisableOngoing(ADCx) == 1U) { - if(timeout_cpu_cycles-- == 0U) + timeout_cpu_cycles--; + if(timeout_cpu_cycles == 0U) { /* Time-out error */ status = ERROR; diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma2d.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma2d.c index d29ac24490..c5fc57df36 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma2d.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma2d.c @@ -83,7 +83,7 @@ ((MODE) == LL_DMA2D_MODE_M2M_PFC) || \ ((MODE) == LL_DMA2D_MODE_M2M_BLEND) || \ ((MODE) == LL_DMA2D_MODE_R2M)) -#endif +#endif /*DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT*/ #define IS_LL_DMA2D_OCMODE(MODE_ARGB) (((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB8888) || \ ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB888) || \ @@ -99,8 +99,8 @@ #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) #define IS_LL_DMA2D_OFFSET_MODE(MODE) (((MODE) == LL_DMA2D_LINE_OFFSET_PIXELS) || \ ((MODE) == LL_DMA2D_LINE_OFFSET_BYTES)) - #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ + #define IS_LL_DMA2D_OFFSET(OFFSET) ((OFFSET) <= LL_DMA2D_OFFSET_MAX) #define IS_LL_DMA2D_LINE(LINES) ((LINES) <= LL_DMA2D_NUMBEROFLINES) @@ -109,8 +109,8 @@ #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) #define IS_LL_DMA2D_SWAP_MODE(MODE) (((MODE) == LL_DMA2D_SWAP_MODE_REGULAR) || \ ((MODE) == LL_DMA2D_SWAP_MODE_TWO_BY_TWO)) - #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ + #define IS_LL_DMA2D_ALPHAINV(ALPHA) (((ALPHA) == LL_DMA2D_ALPHA_REGULAR) || \ ((ALPHA) == LL_DMA2D_ALPHA_INVERTED)) @@ -137,6 +137,8 @@ #define IS_LL_DMA2D_ALPHAMODE(MODE) (((MODE) == LL_DMA2D_ALPHA_MODE_NO_MODIF) || \ ((MODE) == LL_DMA2D_ALPHA_MODE_REPLACE) || \ ((MODE) == LL_DMA2D_ALPHA_MODE_COMBINE)) + + /** * @} */ @@ -187,7 +189,7 @@ ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx) * @note DMA2D transfers must be disabled to set initialization bits in configuration registers, * otherwise ERROR result is returned. * @param DMA2Dx DMA2D Instance - * @param DMA2D_InitStruct: pointer to a LL_DMA2D_InitTypeDef structure + * @param DMA2D_InitStruct pointer to a LL_DMA2D_InitTypeDef structure * that contains the configuration information for the specified DMA2D peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: DMA2D registers are initialized according to DMA2D_InitStruct content @@ -197,7 +199,8 @@ ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_Ini { ErrorStatus status = ERROR; LL_DMA2D_ColorTypeDef DMA2D_ColorStruct; - uint32_t tmp = 0U, tmp1 = 0U, tmp2 = 0U; + uint32_t tmp, tmp1, tmp2; + uint32_t regMask, regValue; /* Check the parameters */ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); @@ -234,14 +237,20 @@ ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_Ini #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ /* DMA2D OPFCCR register configuration ---------------------------------------*/ + regMask = DMA2D_OPFCCR_CM; + regValue = DMA2D_InitStruct->ColorMode; + #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) - MODIFY_REG(DMA2Dx->OPFCCR, (DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB | DMA2D_OPFCCR_AI | DMA2D_OPFCCR_RBS), \ - (DMA2D_InitStruct->ColorMode | DMA2D_InitStruct->OutputSwapMode | DMA2D_InitStruct->AlphaInversionMode | DMA2D_InitStruct->RBSwapMode)); -#else - MODIFY_REG(DMA2Dx->OPFCCR, (DMA2D_OPFCCR_CM | DMA2D_OPFCCR_RBS | DMA2D_OPFCCR_AI), \ - (DMA2D_InitStruct->ColorMode | DMA2D_InitStruct->AlphaInversionMode | DMA2D_InitStruct->RBSwapMode)); + regMask |= DMA2D_OPFCCR_SB; + regValue |= DMA2D_InitStruct->OutputSwapMode; #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ + regMask |= (DMA2D_OPFCCR_RBS | DMA2D_OPFCCR_AI); + regValue |= (DMA2D_InitStruct->AlphaInversionMode | DMA2D_InitStruct->RBSwapMode); + + + MODIFY_REG(DMA2Dx->OPFCCR, regMask, regValue); + /* DMA2D OOR register configuration ------------------------------------------*/ LL_DMA2D_SetLineOffset(DMA2Dx, DMA2D_InitStruct->LineOffset); @@ -268,7 +277,7 @@ ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_Ini /** * @brief Set each @ref LL_DMA2D_InitTypeDef field to default value. - * @param DMA2D_InitStruct: pointer to a @ref LL_DMA2D_InitTypeDef structure + * @param DMA2D_InitStruct pointer to a @ref LL_DMA2D_InitTypeDef structure * whose fields will be set to default values. * @retval None */ @@ -299,9 +308,9 @@ void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct) * @brief Configure the foreground or background according to the specified parameters * in the LL_DMA2D_LayerCfgTypeDef structure. * @param DMA2Dx DMA2D Instance - * @param DMA2D_LayerCfg: pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains + * @param DMA2D_LayerCfg pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains * the configuration information for the specified layer. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval None @@ -321,6 +330,7 @@ void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D assert_param(IS_LL_DMA2D_ALPHAINV(DMA2D_LayerCfg->AlphaInversionMode)); assert_param(IS_LL_DMA2D_RBSWAP(DMA2D_LayerCfg->RBSwapMode)); + if (LayerIdx == 0U) { /* Configure the background memory address */ @@ -373,7 +383,7 @@ void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D /** * @brief Set each @ref LL_DMA2D_LayerCfgTypeDef field to default value. - * @param DMA2D_LayerCfg: pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure + * @param DMA2D_LayerCfg pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure * whose fields will be set to default values. * @retval None */ @@ -399,15 +409,15 @@ void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg) * @brief Initialize DMA2D output color register according to the specified parameters * in DMA2D_ColorStruct. * @param DMA2Dx DMA2D Instance - * @param DMA2D_ColorStruct: pointer to a LL_DMA2D_ColorTypeDef structure that contains + * @param DMA2D_ColorStruct pointer to a LL_DMA2D_ColorTypeDef structure that contains * the color configuration information for the specified DMA2D peripheral. * @retval None */ void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct) { - uint32_t outgreen = 0U; - uint32_t outred = 0U; - uint32_t outalpha = 0U; + uint32_t outgreen; + uint32_t outred; + uint32_t outalpha; /* Check the parameters */ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); @@ -464,7 +474,7 @@ void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DM */ uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { - uint32_t color = 0U; + uint32_t color; /* Check the parameters */ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); @@ -491,7 +501,7 @@ uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFU)); } - + return color; } @@ -508,7 +518,7 @@ uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) */ uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { - uint32_t color = 0U; + uint32_t color; /* Check the parameters */ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); @@ -535,7 +545,7 @@ uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF0U) >> 4U); } - + return color; } @@ -552,7 +562,7 @@ uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) */ uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { - uint32_t color = 0U; + uint32_t color; /* Check the parameters */ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); @@ -579,7 +589,7 @@ uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF00U) >> 8U); } - + return color; } @@ -596,7 +606,7 @@ uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) */ uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { - uint32_t color = 0U; + uint32_t color; /* Check the parameters */ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); @@ -619,7 +629,7 @@ uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF000U) >> 12U); } - + return color; } @@ -657,3 +667,4 @@ void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t Nb #endif /* USE_FULL_LL_DRIVER */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c index 2b2ab2d507..cf381df1b1 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c @@ -11,27 +11,28 @@ * + Peripheral State functions * @verbatim - ============================================================================= + ============================================================================== ##### FMC peripheral features ##### - ============================================================================= + ============================================================================== [..] The Flexible memory controller (FMC) includes following memory controllers: (+) The NOR/PSRAM memory controller (+) The NAND memory controller [..] The FMC functional block makes the interface with synchronous and asynchronous static memories. Its main purposes are: - (+) to translate AHB transactions into the appropriate external device protocol. - (+) to meet the access time requirements of the external memory devices. + (+) to translate AHB transactions into the appropriate external device protocol + (+) to meet the access time requirements of the external memory devices [..] All external memories share the addresses, data and control signals with the controller. Each external device is accessed by means of a unique Chip Select. The FMC performs only one access at a time to an external device. The main features of the FMC controller are the following: (+) Interface with static-memory mapped devices including: - (++) Static random access memory (SRAM). - (++) NOR Flash memory. - (++) PSRAM (4 memory banks). - (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of + (++) Static random access memory (SRAM) + (++) Read-only memory (ROM) + (++) NOR Flash memory/OneNAND Flash memory + (++) PSRAM (4 memory banks) + (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of data (+) Independent Chip Select control for each memory bank (+) Independent configuration for each memory bank @@ -74,8 +75,6 @@ * @{ */ -#if defined(FMC_BANK1) - #if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) /** @defgroup FMC_LL FMC Low Layer @@ -85,31 +84,18 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ + /** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants * @{ */ /* ----------------------- FMC registers bit mask --------------------------- */ -/* --- PCR Register ---*/ -/* PCR register clear mask */ -#define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \ - FMC_PCR_PTYP | FMC_PCR_PWID | \ - FMC_PCR_ECCEN | FMC_PCR_TCLR | \ - FMC_PCR_TAR | FMC_PCR_ECCPS)) - -/* --- PMEM Register ---*/ -/* PMEM register clear mask */ -#define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET | FMC_PMEM_MEMWAIT |\ - FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ)) - -/* --- PATT Register ---*/ -/* PATT register clear mask */ -#define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET | FMC_PATT_ATTWAIT |\ - FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ)) +#if defined(FMC_BANK1) /* --- BCR Register ---*/ /* BCR register clear mask */ #if defined(FMC_BCRx_NBLSET) +#if defined(FMC_BCR1_WFDIS) #define BCR_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\ FMC_BCRx_MTYP | FMC_BCRx_MWID |\ FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\ @@ -119,7 +105,18 @@ FMC_BCRx_CPSIZE | FMC_BCRx_CBURSTRW |\ FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS |\ FMC_BCRx_NBLSET)) -#elif defined(FMC_BCR1_WFDIS) +#else +#define BCR_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\ + FMC_BCRx_MTYP | FMC_BCRx_MWID |\ + FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\ + FMC_BCRx_WAITPOL | FMC_BCRx_WAITCFG |\ + FMC_BCRx_WREN | FMC_BCRx_WAITEN |\ + FMC_BCRx_EXTMOD | FMC_BCRx_ASYNCWAIT |\ + FMC_BCRx_CPSIZE | FMC_BCRx_CBURSTRW |\ + FMC_BCR1_CCLKEN | FMC_BCRx_NBLSET)) +#endif /* FMC_BCR1_WFDIS */ +#else +#if defined(FMC_BCR1_WFDIS) #define BCR_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\ FMC_BCRx_MTYP | FMC_BCRx_MWID |\ FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\ @@ -138,6 +135,7 @@ FMC_BCRx_CPSIZE | FMC_BCRx_CBURSTRW |\ FMC_BCR1_CCLKEN)) #endif /* FMC_BCR1_WFDIS */ +#endif /* FMC_BCRx_NBLSET */ /* --- BTR Register ---*/ /* BTR register clear mask */ @@ -164,20 +162,33 @@ FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\ FMC_BWTRx_ACCMOD)) #endif /* FMC_BWTRx_DATAHLD */ +#endif /* FMC_BANK1 */ +#if defined(FMC_BANK3) -/** - * @} - */ +/* --- PCR Register ---*/ +/* PCR register clear mask */ +#define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \ + FMC_PCR_PTYP | FMC_PCR_PWID | \ + FMC_PCR_ECCEN | FMC_PCR_TCLR | \ + FMC_PCR_TAR | FMC_PCR_ECCPS)) -/* Private macro -------------------------------------------------------------*/ -/** @defgroup FMC_LL_Private_Macros FMC Low Layer Private Macros - * @{ - */ +/* --- PMEM Register ---*/ +/* PMEM register clear mask */ +#define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET | FMC_PMEM_MEMWAIT |\ + FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ)) + +/* --- PATT Register ---*/ +/* PATT register clear mask */ +#define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET | FMC_PATT_ATTWAIT |\ + FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ)) + +#endif /* FMC_BANK3 */ /** * @} */ +/* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -186,7 +197,9 @@ * @{ */ -/** @defgroup FMC_NORSRAM FMC NORSRAM Controller functions +#if defined(FMC_BANK1) + +/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions * @brief NORSRAM Controller functions * @verbatim @@ -206,12 +219,11 @@ (+) FMC NORSRAM bank enable/disable write operation using the functions FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() - @endverbatim * @{ */ -/** @defgroup FMC_NORSRAM_Group1 Initialization/de-initialization functions +/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim @@ -237,6 +249,8 @@ */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init) { + uint32_t flashaccess; + /* Check the parameters */ assert_param(IS_FMC_NORSRAM_DEVICE(Device)); assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); @@ -255,10 +269,10 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini #if defined(FMC_BCR1_WFDIS) assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); #endif /* FMC_BCR1_WFDIS */ + assert_param(IS_FMC_PAGESIZE(Init->PageSize)); #if defined(FMC_BCRx_NBLSET) - assert_param(IS_FMC_NBLSETUP_TIME(Init->NBLSetupTime)); + assert_param(IS_FMC_NBL_SETUPTIME(Init->NBLSetupTime)); #endif /* FMC_BCRx_NBLSET */ - assert_param(IS_FMC_PAGESIZE(Init->PageSize)); /* Disable NORSRAM Device */ __FMC_NORSRAM_DISABLE(Device, Init->NSBank); @@ -266,54 +280,33 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini /* Set NORSRAM device control parameters */ if (Init->MemoryType == FMC_MEMORY_TYPE_NOR) { - MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_ENABLE - | Init->DataAddressMux - | Init->MemoryType - | Init->MemoryDataWidth - | Init->BurstAccessMode - | Init->WaitSignalPolarity - | Init->WaitSignalActive - | Init->WriteOperation - | Init->WaitSignal - | Init->ExtendedMode - | Init->AsynchronousWait - | Init->WriteBurst - | Init->ContinuousClock -#if defined(FMC_BCR1_WFDIS) - | Init->WriteFifo -#endif /* FMC_BCR1_WFDIS */ -#if defined(FMC_BCRx_NBLSET) - | Init->NBLSetupTime << POSITION_VAL(FMC_BCRx_NBLSET) -#endif /* FMC_BCRx_NBLSET */ - | Init->PageSize - ) - ); + flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE; } else { - MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_DISABLE - | Init->DataAddressMux - | Init->MemoryType - | Init->MemoryDataWidth - | Init->BurstAccessMode - | Init->WaitSignalPolarity - | Init->WaitSignalActive - | Init->WriteOperation - | Init->WaitSignal - | Init->ExtendedMode - | Init->AsynchronousWait - | Init->WriteBurst - | Init->ContinuousClock + flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE; + } + + MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (flashaccess | + Init->DataAddressMux | + Init->MemoryType | + Init->MemoryDataWidth | + Init->BurstAccessMode | + Init->WaitSignalPolarity | + Init->WaitSignalActive | + Init->WriteOperation | + Init->WaitSignal | + Init->ExtendedMode | + Init->AsynchronousWait | + Init->WriteBurst | + Init->ContinuousClock | #if defined(FMC_BCR1_WFDIS) - | Init->WriteFifo + Init->WriteFifo | #endif /* FMC_BCR1_WFDIS */ #if defined(FMC_BCRx_NBLSET) - | Init->NBLSetupTime << POSITION_VAL(FMC_BCRx_NBLSET) + Init->NBLSetupTime | #endif /* FMC_BCRx_NBLSET */ - | Init->PageSize - ) - ); - } + Init->PageSize)); /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) @@ -354,16 +347,16 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EX /* FMC_NORSRAM_BANK1 */ if (Bank == FMC_NORSRAM_BANK1) { - Device->BTCR[Bank] = 0x000030DB; + Device->BTCR[Bank] = 0x000030DBU; } /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */ else { - Device->BTCR[Bank] = 0x000030D2; + Device->BTCR[Bank] = 0x000030D2U; } - Device->BTCR[Bank + 1] = 0x0FFFFFFF; - ExDevice->BWTR[Bank] = 0x0FFFFFFF; + Device->BTCR[Bank + 1] = 0x0FFFFFFFU; + ExDevice->BWTR[Bank] = 0x0FFFFFFFU; return HAL_OK; } @@ -385,10 +378,10 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSR assert_param(IS_FMC_NORSRAM_DEVICE(Device)); assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); - assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); #if defined(FMC_BTRx_DATAHLD) - assert_param(IS_FMC_DATAHOLD_TIME(Timing->DataHoldTime)); + assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); #endif /* FMC_BTRx_DATAHLD */ + assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); @@ -396,24 +389,22 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSR assert_param(IS_FMC_NORSRAM_BANK(Bank)); /* Set FMC_NORSRAM device timing parameters */ - MODIFY_REG(Device->BTCR[Bank + 1], - BTR_CLEAR_MASK, - (uint32_t)(Timing->AddressSetupTime | - ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BTRx_ADDHLD)) | - ((Timing->DataSetupTime) << POSITION_VAL(FMC_BTRx_DATAST)) | + MODIFY_REG(Device->BTCR[Bank + 1], BTR_CLEAR_MASK, (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) | #if defined(FMC_BTRx_DATAHLD) - ((Timing->DataHoldTime) << POSITION_VAL(FMC_BTRx_DATAHLD)) | + ((Timing->DataHoldTime) << FMC_BTRx_DATAHLD_Pos) | #endif /* FMC_BTRx_DATAHLD */ - ((Timing->BusTurnAroundDuration) << POSITION_VAL(FMC_BTRx_BUSTURN)) | - (((Timing->CLKDivision) - 1) << POSITION_VAL(FMC_BTRx_CLKDIV)) | - (((Timing->DataLatency) - 2) << POSITION_VAL(FMC_BTRx_DATLAT)) | + ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) | + (((Timing->CLKDivision) - 1) << FMC_BTRx_CLKDIV_Pos) | + (((Timing->DataLatency) - 2) << FMC_BTRx_DATLAT_Pos) | (Timing->AccessMode))); /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) { - tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << POSITION_VAL(FMC_BTRx_CLKDIV))); - tmpr |= (uint32_t)(((Timing->CLKDivision) - 1) << POSITION_VAL(FMC_BTRx_CLKDIV)); + tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << FMC_BTRx_CLKDIV_Pos)); + tmpr |= (uint32_t)(((Timing->CLKDivision) - 1) << FMC_BTRx_CLKDIV_Pos); MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1], FMC_BTRx_CLKDIV, tmpr); } @@ -444,41 +435,36 @@ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); + assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); #if defined(FMC_BTRx_DATAHLD) - assert_param(IS_FMC_DATAHOLD_TIME(Timing->DataHoldTime)); + assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); #endif /* FMC_BTRx_DATAHLD */ - assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); assert_param(IS_FMC_NORSRAM_BANK(Bank)); /* Set NORSRAM device timing register for write configuration, if extended mode is used */ - MODIFY_REG(Device->BWTR[Bank], - BWTR_CLEAR_MASK, - (uint32_t)(Timing->AddressSetupTime | - ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BWTRx_ADDHLD)) | - ((Timing->DataSetupTime) << POSITION_VAL(FMC_BWTRx_DATAST)) | + MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) | #if defined(FMC_BTRx_DATAHLD) - ((Timing->DataHoldTime) << POSITION_VAL(FMC_BTRx_DATAHLD)) | + ((Timing->DataHoldTime) << FMC_BWTRx_DATAHLD_Pos) | #endif /* FMC_BTRx_DATAHLD */ - Timing->AccessMode | - ((Timing->BusTurnAroundDuration) << POSITION_VAL(FMC_BWTRx_BUSTURN)))); + Timing->AccessMode | + ((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos))); } else { - Device->BWTR[Bank] = 0x0FFFFFFF; + Device->BWTR[Bank] = 0x0FFFFFFFU; } return HAL_OK; } - - /** * @} */ - -/** @defgroup FMC_NORSRAM_Group2 Control functions +/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2 * @brief management functions * @verbatim @@ -536,7 +522,11 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device /** * @} */ -/** @defgroup FMC_NAND FMC NAND Controller functions +#endif /* FMC_BANK1 */ + +#if defined(FMC_BANK3) + +/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions * @brief NAND Controller functions * @verbatim @@ -561,7 +551,7 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device * @{ */ -/** @defgroup FMC_NAND_Exported_Functions_Group1 Initialization and de-initialization functions +/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim @@ -597,17 +587,16 @@ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef * assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); - /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature | - FMC_PCR_MEMORY_TYPE_NAND | - Init->MemoryDataWidth | - Init->EccComputation | - Init->ECCPageSize | - ((Init->TCLRSetupTime) << POSITION_VAL(FMC_PCR_TCLR)) | - ((Init->TARSetupTime) << POSITION_VAL(FMC_PCR_TAR)))); + /* NAND bank 3 registers configuration */ + MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature | + FMC_PCR_MEMORY_TYPE_NAND | + Init->MemoryDataWidth | + Init->EccComputation | + Init->ECCPageSize | + ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) | + ((Init->TARSetupTime) << FMC_PCR_TAR_Pos))); return HAL_OK; - } /** @@ -626,13 +615,15 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); - assert_param(IS_FMC_NAND_BANK(Bank)); - /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEM_MEMWAIT)) | - ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEM_MEMHOLD)) | - ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEM_MEMHIZ)))); + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + /* NAND bank 3 registers configuration */ + MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos))); return HAL_OK; } @@ -653,20 +644,21 @@ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); - assert_param(IS_FMC_NAND_BANK(Bank)); - /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PATT_ATTWAIT)) | - ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PATT_ATTHOLD)) | - ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PATT_ATTHIZ)))); + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + /* NAND bank 3 registers configuration */ + MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos))); return HAL_OK; } - /** - * @brief DeInitialize the FMC_NAND device + * @brief DeInitializes the FMC_NAND device * @param Device Pointer to NAND device instance * @param Bank NAND bank number * @retval HAL status @@ -675,17 +667,19 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); /* Disable the NAND Bank */ - __FMC_NAND_DISABLE(Device, Bank); + __FMC_NAND_DISABLE(Device); /* De-initialize the NAND Bank */ - /* Set the FMC_NAND_BANK3 registers to their reset values */ - WRITE_REG(Device->PCR, 0x00000018); - WRITE_REG(Device->SR, 0x00000040); - WRITE_REG(Device->PMEM, 0xFCFCFCFC); - WRITE_REG(Device->PATT, 0xFCFCFCFC); + /* Set the FMC_NAND_BANK3 registers to their reset values */ + WRITE_REG(Device->PCR, 0x00000018); + WRITE_REG(Device->SR, 0x00000040); + WRITE_REG(Device->PMEM, 0xFCFCFCFC); + WRITE_REG(Device->PATT, 0xFCFCFCFC); return HAL_OK; } @@ -694,8 +688,7 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) * @} */ - -/** @defgroup FMC_NAND_Exported_Functions_Group2 Peripheral Control functions +/** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions * @brief management functions * @verbatim @@ -721,10 +714,12 @@ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); /* Enable ECC feature */ - SET_BIT(Device->PCR, FMC_PCR_ECCEN); + SET_BIT(Device->PCR, FMC_PCR_ECCEN); return HAL_OK; } @@ -740,10 +735,12 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); /* Disable ECC feature */ - CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN); + CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN); return HAL_OK; } @@ -762,7 +759,9 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); /* Get tick */ tickstart = HAL_GetTick(); @@ -780,8 +779,8 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui } } - /* Get the ECCR register value */ - *ECCval = (uint32_t)Device->ECCR; + /* Get the ECCR register value */ + *ECCval = (uint32_t)Device->ECCR; return HAL_OK; } @@ -789,10 +788,9 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui /** * @} */ +#endif /* FMC_BANK3 */ + -/** - * @} - */ /** * @} @@ -803,9 +801,6 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui */ #endif /* defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) */ - -#endif /* FMC_BANK1 */ - /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lpuart.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lpuart.c index 53e852a9d3..df5810900a 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lpuart.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lpuart.c @@ -93,11 +93,14 @@ /* - fck must be in the range [3 x baudrate, 4096 x baudrate] */ /* - LPUART_BRR register value should be >= 0x300 */ /* - LPUART_BRR register value should be <= 0xFFFFF (20 bits) */ -/* Baudrate specified by the user should belong to [8, 26000000].*/ -#define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 26000000U) && ((__BAUDRATE__) >= 8U)) +/* Baudrate specified by the user should belong to [8, 40000000].*/ +#define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 40000000U) && ((__BAUDRATE__) >= 8U)) /* __VALUE__ BRR content must be greater than or equal to 0x300. */ -#define IS_LL_LPUART_BRR(__VALUE__) ((__VALUE__) >= 0x300U) +#define IS_LL_LPUART_BRR_MIN(__VALUE__) ((__VALUE__) >= 0x300U) + +/* __VALUE__ BRR content must be lower than or equal to 0xFFFFF. */ +#define IS_LL_LPUART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x000FFFFFU) #define IS_LL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == LL_LPUART_DIRECTION_NONE) \ || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \ @@ -245,10 +248,13 @@ ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART LPUART_InitStruct->BaudRate); /* Check BRR is greater than or equal to 0x300 */ - assert_param(IS_LL_LPUART_BRR(LPUARTx->BRR)); + assert_param(IS_LL_LPUART_BRR_MIN(LPUARTx->BRR)); + + /* Check BRR is lower than or equal to 0xFFFF */ + assert_param(IS_LL_LPUART_BRR_MAX(LPUARTx->BRR)); } -#if defined(USART_PRESC_PRESCALER) +#if defined(USART_PRESC_PRESCALER) /*---------------------------- LPUART PRESC Configuration ----------------------- * Configure LPUARTx PRESC (Prescaler) with parameters: * - PrescalerValue: LPUART_PRESC_PRESCALER bits according to LPUART_InitStruct->PrescalerValue value. diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c index 528875fea5..6df00afc43 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c @@ -281,7 +281,6 @@ ErrorStatus LL_RCC_DeInit(void) #if defined(RCC_PLLSAI2_SUPPORT) vl_mask |= RCC_CICR_PLLSAI2RDYC; #endif - LL_RCC_WriteReg(CICR, vl_mask); /* Clear reset flags */ @@ -800,7 +799,7 @@ uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) * (*) value not defined in all devices. * @retval SAI clock frequency (in Hz) * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready - * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used + */ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) { @@ -838,8 +837,10 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) break; case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */ + sai_frequency = EXTERNAL_SAI1_CLOCK_VALUE; + break; + default: - sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA; break; } } @@ -874,10 +875,12 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) } break; - case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */ - default: - sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA; - break; + case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */ + sai_frequency = EXTERNAL_SAI2_CLOCK_VALUE; + break; + + default: + break; } } #endif /* RCC_CCIPR_SAI2SEL */ @@ -1033,14 +1036,14 @@ uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource) #if defined(RCC_HSI48_SUPPORT) - case LL_RCC_RNG_CLKSOURCE_HSI48: /* HSI48 used as SDMMC1 clock source */ + case LL_RCC_RNG_CLKSOURCE_HSI48: /* HSI48 used as RNG clock source */ if (LL_RCC_HSI48_IsReady()) { rng_frequency = HSI48_VALUE; } break; #else - case LL_RCC_RNG_CLKSOURCE_NONE: /* No clock used as SDMMC1 clock source */ + case LL_RCC_RNG_CLKSOURCE_NONE: /* No clock used as RNG clock source */ #endif default: rng_frequency = LL_RCC_PERIPH_FREQUENCY_NA; diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_sdmmc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_sdmmc.c index 1a4156066a..316ca47763 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_sdmmc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_sdmmc.c @@ -444,13 +444,13 @@ uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx) */ uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response) { - __IO uint32_t tmp = 0; + uint32_t tmp; /* Check the parameters */ assert_param(IS_SDMMC_RESP(Response)); /* Get the response */ - tmp = (uint32_t)&(SDMMCx->RESP1) + Response; + tmp = (uint32_t)(&(SDMMCx->RESP1)) + Response; return (*(__IO uint32_t *) tmp); } @@ -556,7 +556,7 @@ HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDM uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)BlockSize; @@ -564,7 +564,7 @@ uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCKLEN, SDMMC_CMDTIMEOUT); @@ -580,7 +580,7 @@ uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize) uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; @@ -588,7 +588,7 @@ uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_SINGLE_BLOCK, SDMMC_CMDTIMEOUT); @@ -604,7 +604,7 @@ uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; @@ -612,7 +612,7 @@ uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_MULT_BLOCK, SDMMC_CMDTIMEOUT); @@ -628,7 +628,7 @@ uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; @@ -636,7 +636,7 @@ uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDMMC_CMDTIMEOUT); @@ -652,7 +652,7 @@ uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; @@ -660,7 +660,7 @@ uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_MULT_BLOCK, SDMMC_CMDTIMEOUT); @@ -676,7 +676,7 @@ uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)StartAdd; @@ -684,7 +684,7 @@ uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_START, SDMMC_CMDTIMEOUT); @@ -700,7 +700,7 @@ uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)EndAdd; @@ -708,7 +708,7 @@ uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_END, SDMMC_CMDTIMEOUT); @@ -724,7 +724,7 @@ uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)StartAdd; @@ -732,7 +732,7 @@ uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_START, SDMMC_CMDTIMEOUT); @@ -748,7 +748,7 @@ uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)EndAdd; @@ -756,7 +756,7 @@ uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_END, SDMMC_CMDTIMEOUT); @@ -772,7 +772,7 @@ uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = 0; @@ -780,7 +780,7 @@ uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE, SDMMC_MAXERASETIMEOUT); @@ -796,7 +796,7 @@ uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx) uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Send CMD12 STOP_TRANSMISSION */ sdmmc_cmdinit.Argument = 0; @@ -804,7 +804,7 @@ uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, SDMMC_STOPTRANSFERTIMEOUT); @@ -821,7 +821,7 @@ uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx) uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Send CMD7 SDMMC_SEL_DESEL_CARD */ sdmmc_cmdinit.Argument = (uint32_t)Addr; @@ -829,7 +829,7 @@ uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEL_DESEL_CARD, SDMMC_CMDTIMEOUT); @@ -845,14 +845,14 @@ uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr) uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; sdmmc_cmdinit.Argument = 0; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE; sdmmc_cmdinit.Response = SDMMC_RESPONSE_NO; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdError(SDMMCx); @@ -868,7 +868,7 @@ uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx) uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Send CMD8 to verify SD card interface operating condition */ /* Argument: - [31:12]: Reserved (shall be set to '0') @@ -880,7 +880,7 @@ uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp7(SDMMCx); @@ -899,14 +899,14 @@ uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx) uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; sdmmc_cmdinit.Argument = (uint32_t)Argument; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ /* If there is a HAL_ERROR, it is a MMC card, else @@ -927,7 +927,7 @@ uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) sdmmc_cmdinit.Argument = Argument; @@ -938,7 +938,7 @@ uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp3(SDMMCx); @@ -955,14 +955,14 @@ uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; sdmmc_cmdinit.Argument = (uint32_t)BusWidth; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDMMC_CMDTIMEOUT); @@ -978,7 +978,7 @@ uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth) uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Send CMD51 SD_APP_SEND_SCR */ sdmmc_cmdinit.Argument = 0; @@ -986,7 +986,7 @@ uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_SEND_SCR, SDMMC_CMDTIMEOUT); @@ -1002,7 +1002,7 @@ uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx) uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Send CMD2 ALL_SEND_CID */ sdmmc_cmdinit.Argument = 0; @@ -1010,7 +1010,7 @@ uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx) sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp2(SDMMCx); @@ -1027,7 +1027,7 @@ uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx) uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Send CMD9 SEND_CSD */ sdmmc_cmdinit.Argument = Argument; @@ -1035,7 +1035,7 @@ uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp2(SDMMCx); @@ -1052,7 +1052,7 @@ uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Send CMD3 SD_CMD_SET_REL_ADDR */ sdmmc_cmdinit.Argument = 0; @@ -1060,7 +1060,7 @@ uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp6(SDMMCx, SDMMC_CMD_SET_REL_ADDR, pRCA); @@ -1077,14 +1077,14 @@ uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA) uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; sdmmc_cmdinit.Argument = Argument; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEND_STATUS, SDMMC_CMDTIMEOUT); @@ -1100,14 +1100,14 @@ uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument) uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; sdmmc_cmdinit.Argument = 0; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_STATUS, SDMMC_CMDTIMEOUT); @@ -1125,14 +1125,14 @@ uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx) uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; sdmmc_cmdinit.Argument = Argument; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp3(SDMMCx); @@ -1149,14 +1149,14 @@ uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument) uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; sdmmc_cmdinit.Argument = Argument; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SWITCH, SDMMC_CMDTIMEOUT); @@ -1174,14 +1174,14 @@ uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument) uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; sdmmc_cmdinit.Argument = 0x00000000; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_VOLTAGE_SWITCH; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_VOLTAGE_SWITCH, SDMMC_CMDTIMEOUT); @@ -1209,11 +1209,11 @@ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) { /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000); + register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); do { - if (count-- == 0) + if (count-- == 0U) { return SDMMC_ERROR_TIMEOUT; } @@ -1241,11 +1241,11 @@ static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_ /* 8 is the number of required instructions cycles for the below loop statement. The Timeout is expressed in ms */ - register uint32_t count = Timeout * (SystemCoreClock / 8 /1000); + register uint32_t count = Timeout * (SystemCoreClock / 8U /1000U); do { - if (count-- == 0) + if (count-- == 0U) { return SDMMC_ERROR_TIMEOUT; } @@ -1264,6 +1264,10 @@ static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_ return SDMMC_ERROR_CMD_CRC_FAIL; } + else + { + /* Nothing to do */ + } /* Check response received is of desired command */ if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) @@ -1368,11 +1372,11 @@ static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) { /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000); + register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); do { - if (count-- == 0) + if (count-- == 0U) { return SDMMC_ERROR_TIMEOUT; } @@ -1410,11 +1414,11 @@ static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) { /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000); + register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); do { - if (count-- == 0) + if (count-- == 0U) { return SDMMC_ERROR_TIMEOUT; } @@ -1450,11 +1454,11 @@ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_ /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000); + register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); do { - if (count-- == 0) + if (count-- == 0U) { return SDMMC_ERROR_TIMEOUT; } @@ -1473,6 +1477,10 @@ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_ return SDMMC_ERROR_CMD_CRC_FAIL; } + else + { + /* Nothing to do */ + } /* Check response received is of desired command */ if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) @@ -1515,11 +1523,11 @@ static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) { /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000); + register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); do { - if (count-- == 0) + if (count-- == 0U) { return SDMMC_ERROR_TIMEOUT; } @@ -1541,6 +1549,10 @@ static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) return SDMMC_ERROR_CMD_CRC_FAIL; } + else + { + /* Nothing to do */ + } if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND)) { diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_swpmi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_swpmi.c index 8dfbd5e1ea..42c07e240b 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_swpmi.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_swpmi.c @@ -47,7 +47,7 @@ * @{ */ -#if defined (SWPMI1) +#if defined(SWPMI1) /** @addtogroup SWPMI_LL * @{ @@ -119,7 +119,7 @@ ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx) ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_SWPMI_INSTANCE(SWPMIx)); assert_param(IS_LL_SWPMI_BITRATE_VALUE(SWPMI_InitStruct->BitRatePrescaler)); @@ -177,7 +177,7 @@ void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct) * @} */ -#endif /* defined (SWPMI1) */ +#endif /* SWPMI1 */ /** * @} diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_tim.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_tim.c index a45451abcd..cf24e355e2 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_tim.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_tim.c @@ -338,7 +338,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) */ ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) { - uint32_t tmpcr1 = 0U; + uint32_t tmpcr1; /* Check the parameters */ assert_param(IS_TIM_INSTANCE(TIMx)); @@ -528,8 +528,8 @@ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct */ ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) { - uint32_t tmpccmr1 = 0U; - uint32_t tmpccer = 0U; + uint32_t tmpccmr1; + uint32_t tmpccer; /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); @@ -619,10 +619,10 @@ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorI */ ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) { - uint32_t tmpcr2 = 0U; - uint32_t tmpccmr1 = 0U; - uint32_t tmpccer = 0U; - uint32_t tmpsmcr = 0U; + uint32_t tmpcr2; + uint32_t tmpccmr1; + uint32_t tmpccer; + uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx)); @@ -797,9 +797,9 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT */ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { - uint32_t tmpccmr1 = 0U; - uint32_t tmpccer = 0U; - uint32_t tmpcr2 = 0U; + uint32_t tmpccmr1; + uint32_t tmpccer; + uint32_t tmpcr2; /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); @@ -876,9 +876,9 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni */ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { - uint32_t tmpccmr1 = 0U; - uint32_t tmpccer = 0U; - uint32_t tmpcr2 = 0U; + uint32_t tmpccmr1; + uint32_t tmpccer; + uint32_t tmpcr2; /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(TIMx)); @@ -955,9 +955,9 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni */ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { - uint32_t tmpccmr2 = 0U; - uint32_t tmpccer = 0U; - uint32_t tmpcr2 = 0U; + uint32_t tmpccmr2; + uint32_t tmpccer; + uint32_t tmpcr2; /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(TIMx)); @@ -1034,9 +1034,9 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni */ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { - uint32_t tmpccmr2 = 0U; - uint32_t tmpccer = 0U; - uint32_t tmpcr2 = 0U; + uint32_t tmpccmr2; + uint32_t tmpccer; + uint32_t tmpcr2; /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(TIMx)); @@ -1104,8 +1104,8 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni */ static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { - uint32_t tmpccmr3 = 0U; - uint32_t tmpccer = 0U; + uint32_t tmpccmr3; + uint32_t tmpccer; /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(TIMx)); @@ -1165,8 +1165,8 @@ static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni */ static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { - uint32_t tmpccmr3 = 0U; - uint32_t tmpccer = 0U; + uint32_t tmpccmr3; + uint32_t tmpccer; /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(TIMx)); diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usart.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usart.c index ac614918cb..b24c4672e0 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usart.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usart.c @@ -84,8 +84,8 @@ || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \ || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \ || ((__VALUE__) == LL_USART_PRESCALER_DIV256)) - #endif + /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available * divided by the smallest oversampling used on the USART (i.e. 8) */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) @@ -95,8 +95,10 @@ #endif /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */ -#define IS_LL_USART_BRR(__VALUE__) (((__VALUE__) >= 16U) \ - && ((__VALUE__) <= 0x0000FFFFU)) +#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) + +/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */ +#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ || ((__VALUE__) == LL_USART_DIRECTION_RX) \ @@ -226,7 +228,7 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0). * @param USARTx USART Instance - * @param USART_InitStruct: pointer to a LL_USART_InitTypeDef structure + * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure * that contains the configuration information for the specified USART peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: USART registers are initialized according to USART_InitStruct content @@ -315,9 +317,9 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini } /* Configure the USART Baud Rate : -#if defined(USART_PRESC_PRESCALER) + #if defined(USART_PRESC_PRESCALER) - prescaler value is required -#endif + #endif - valid baud rate value (different from 0) is required - Peripheral clock as returned by RCC service, should be valid (different from 0). */ @@ -334,7 +336,10 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini USART_InitStruct->BaudRate); /* Check BRR is greater than or equal to 16d */ - assert_param(IS_LL_USART_BRR(USARTx->BRR)); + assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR)); + + /* Check BRR is lower than or equal to 0xFFFF */ + assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR)); } #if defined(USART_PRESC_PRESCALER) @@ -352,8 +357,8 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /** * @brief Set each @ref LL_USART_InitTypeDef field to default value. - * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure - * whose fields will be set to default values. + * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure + * whose fields will be set to default values. * @retval None */ @@ -378,7 +383,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. * @param USARTx USART Instance - * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure + * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure * that contains the Clock configuration information for the specified USART peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content @@ -439,8 +444,8 @@ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef /** * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value. - * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure - * whose fields will be set to default values. + * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure + * whose fields will be set to default values. * @retval None */ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c index b1dbbb34a4..40d12f0032 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c @@ -3,21 +3,21 @@ * @file stm32l4xx_ll_usb.c * @author MCD Application Team * @brief USB Low Layer HAL module driver. - * - * This file provides firmware functions to manage the following + * + * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: * + Initialization/de-initialization functions * + I/O operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State functions - * + * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure. - + (#) Call USB_CoreInit() API to initialize the USB Core peripheral. (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. @@ -51,28 +51,18 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" -/** @defgroup USB_LL USB Low Layer - * @brief Low layer module for USB_FS and USB_OTG_FS drivers - * @{ - */ -#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) - -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /** @addtogroup STM32L4xx_LL_USB_DRIVER * @{ */ +#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) +#if defined (USB) || defined (USB_OTG_FS) || defined (USB_OTG_HS) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -80,66 +70,70 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ -#if defined (USB_OTG_FS) -/** @defgroup USB_LL_Private_Functions USB Low Layer Private Functions - * @{ - */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); -/** - * @} - */ -#endif /* USB_OTG_FS */ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions +/* Exported functions --------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions * @{ */ -/** @defgroup LL_USB_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== - ##### Initialization/de-initialization functions ##### + ##### Initialization/de-initialization functions ##### =============================================================================== - [..] This section provides functions allowing to: - + @endverbatim * @{ */ -/*============================================================================== - USB OTG FS peripheral available on STM32L475xx, STM32L476xx, STM32L485xx and - STM32L486xx devices -==============================================================================*/ -#if defined (USB_OTG_FS) + /** * @brief Initializes the USB Core - * @param USBx: USB Instance - * @param cfg: pointer to a USB_OTG_CfgTypeDef structure that contains + * @param USBx USB Instance + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(cfg); + if (cfg.phy_itface == USB_OTG_ULPI_PHY) + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + + /* Init The ULPI Interface */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); + + /* Select vbus source */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); + if (cfg.use_external_vbus == 1U) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; + } + /* Reset after a PHY select */ + (void)USB_CoreReset(USBx); + } + else /* FS interface (embedded Phy) */ + { + /* Select FS Embedded PHY */ + USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; + + /* Reset after a PHY select and set Host mode */ + (void)USB_CoreReset(USBx); + + /* Deactivate the power down*/ + USBx->GCCFG = USB_OTG_GCCFG_PWRDWN; + } - /* Select FS Embedded PHY */ - USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; - - /* Reset after a PHY select and set Host mode */ - USB_CoreReset(USBx); - - /* Deactivate the power down*/ - USBx->GCCFG = USB_OTG_GCCFG_PWRDWN; - return HAL_OK; } /** * @brief USB_EnableGlobalInt * Enables the controller's Global Int in the AHB Config reg - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) @@ -148,11 +142,10 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) return HAL_OK; } - /** * @brief USB_DisableGlobalInt * Disable the controller's Global Int in the AHB Config reg - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) @@ -160,392 +153,418 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; return HAL_OK; } - + /** * @brief USB_SetCurrentMode : Set functional mode - * @param USBx: Selected device - * @param mode: current core mode + * @param USBx Selected device + * @param mode current core mode * This parameter can be one of these values: - * @arg USB_OTG_DEVICE_MODE: Peripheral mode - * @arg USB_OTG_HOST_MODE: Host mode - * @arg USB_OTG_DRD_MODE: Dual Role Device mode + * @arg USB_DEVICE_MODE: Peripheral mode + * @arg USB_HOST_MODE: Host mode + * @arg USB_DRD_MODE: Dual Role Device mode * @retval HAL status */ -HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_ModeTypeDef mode) +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode) { - USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); - - if ( mode == USB_HOST_MODE) + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); + + if (mode == USB_HOST_MODE) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; + } + else if (mode == USB_DEVICE_MODE) { - USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; } - else if ( mode == USB_DEVICE_MODE) + else { - USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + return HAL_ERROR; } - HAL_Delay(50); - + HAL_Delay(50U); + return HAL_OK; } /** - * @brief USB_DevInit : Initializes the USB_OTG controller registers + * @brief USB_DevInit : Initializes the USB_OTG controller registers * for device mode - * @param USBx: Selected device - * @param cfg: pointer to a USB_OTG_CfgTypeDef structure that contains + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ -HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { - uint32_t index = 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + for (i = 0U; i < 15U; i++) + { + USBx->DIEPTXF[i] = 0U; + } /*Activate VBUS Sensing B */ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; - - if (cfg.vbus_sensing_enable == 0) + + if (cfg.vbus_sensing_enable == 0U) { /* Deactivate VBUS Sensing B */ - USBx->GCCFG &= ~ USB_OTG_GCCFG_VBDEN; - - /* B-peripheral session valid override enable*/ + USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + + /* B-peripheral session valid override enable*/ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; } - + /* Restart the Phy Clock */ - USBx_PCGCCTL = 0; + USBx_PCGCCTL = 0U; /* Device mode configuration */ USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; - + /* Set Full speed phy */ - USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL); + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); /* Flush the FIFOs */ - USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */ - USB_FlushRxFifo(USBx); - + (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */ + (void)USB_FlushRxFifo(USBx); + /* Clear all pending Device Interrupts */ - USBx_DEVICE->DIEPMSK = 0; - USBx_DEVICE->DOEPMSK = 0; - USBx_DEVICE->DAINT = 0xFFFFFFFF; - USBx_DEVICE->DAINTMSK = 0; - - for (index = 0; index < cfg.dev_endpoints; index++) - { - if ((USBx_INEP(index)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; + + for (i = 0U; i < cfg.dev_endpoints; i++) + { + if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) { - USBx_INEP(index)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK); + if (i == 0U) + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; + } + else + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; + } } else { - USBx_INEP(index)->DIEPCTL = 0; + USBx_INEP(i)->DIEPCTL = 0U; } - - USBx_INEP(index)->DIEPTSIZ = 0; - USBx_INEP(index)->DIEPINT = 0xFF; + + USBx_INEP(i)->DIEPTSIZ = 0U; + USBx_INEP(i)->DIEPINT = 0xFB7FU; } - - for (index = 0; index < cfg.dev_endpoints; index++) + + for (i = 0U; i < cfg.dev_endpoints; i++) { - if ((USBx_OUTEP(index)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) { - USBx_OUTEP(index)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK); + if (i == 0U) + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; + } + else + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; + } } else { - USBx_OUTEP(index)->DOEPCTL = 0; + USBx_OUTEP(i)->DOEPCTL = 0U; } - - USBx_OUTEP(index)->DOEPTSIZ = 0; - USBx_OUTEP(index)->DOEPINT = 0xFF; + + USBx_OUTEP(i)->DOEPTSIZ = 0U; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; } - + USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); - - if (cfg.dma_enable == 1) - { - /*Set threshold parameters */ - USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6); - USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN); - - index= USBx_DEVICE->DTHRCTL; - } - + /* Disable all interrupts. */ - USBx->GINTMSK = 0; - + USBx->GINTMSK = 0U; + /* Clear any pending interrupts */ - USBx->GINTSTS = 0xBFFFFFFF; + USBx->GINTSTS = 0xBFFFFFFFU; /* Enable the common interrupts */ - if (cfg.dma_enable == DISABLE) - { - USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; - } + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; - /* Enable interrupts matching to the Device mode ONLY */ - USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\ - USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\ - USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|\ - USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); + /* Enable interrupts matching to the Device mode ONLY */ + USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | + USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | + USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; - if(cfg.Sof_enable) + if (cfg.Sof_enable != 0U) { USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; } - if (cfg.vbus_sensing_enable == ENABLE) + if (cfg.vbus_sensing_enable == 1U) { - USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); + USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); } - + return HAL_OK; } - /** * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO - * @param USBx: Selected device - * @param num: FIFO number + * @param USBx Selected device + * @param num FIFO number * This parameter can be a value from 1 to 15 15 means Flush all Tx FIFOs * @retval HAL status */ -HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num) +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { - uint32_t count = 0; - - USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6)); - + uint32_t count = 0U; + + USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); + do { - if (++count > 200000) + if (++count > 200000U) { return HAL_TIMEOUT; } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); - + return HAL_OK; } - /** * @brief USB_FlushRxFifo : Flush Rx FIFO - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { uint32_t count = 0; - + USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; - + do { - if (++count > 200000) + if (++count > 200000U) { return HAL_TIMEOUT; } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); - + return HAL_OK; } /** - * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register + * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register * depending the PHY type and the enumeration speed of the device. - * @param USBx: Selected device - * @param speed: device speed + * @param USBx Selected device + * @param speed device speed * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode - * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode * @arg USB_OTG_SPEED_LOW: Low speed mode * @retval Hal status */ -HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed) +HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) { + uint32_t USBx_BASE = (uint32_t)USBx; + USBx_DEVICE->DCFG |= speed; return HAL_OK; } /** - * @brief USB_GetDevSpeed :Return the Dev Speed - * @param USBx: Selected device + * @brief USB_GetDevSpeed :Return the Dev Speed + * @param USBx Selected device * @retval speed : device speed * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode * @arg USB_OTG_SPEED_LOW: Low speed mode */ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) { - uint8_t speed = 0; - - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) - { - speed = USB_OTG_SPEED_HIGH; - } - else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)|| - ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ)) + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t speed; + uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; + + if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || + (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) { speed = USB_OTG_SPEED_FULL; } - else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) + else if (DevEnumSpeed == DSTS_ENUMSPD_LS_PHY_6MHZ) { speed = USB_OTG_SPEED_LOW; } - + else + { + speed = 0U; + } + return speed; } /** * @brief Activate and configure an endpoint - * @param USBx: Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { - if (ep->is_in == 1) + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) { - USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))); - - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0) - { - USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); - } + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU)); + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + } } else { - USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16); - - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0) + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16); + + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) { - USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP)); - } + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_USBAEP; + } } return HAL_OK; } + /** * @brief Activate and configure a dedicated endpoint - * @param USBx: Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { - static __IO uint32_t debug = 0; - + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + /* Read DEPCTLn register */ - if (ep->is_in == 1) + if (ep->is_in == 1U) { - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0) + if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U) { - USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); - } - - - debug |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); - - USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))); + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + } + + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU)); } else { - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0) + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) { - USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); - - debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE); - debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL; - debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); - } - - USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16); + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DOEPCTL_USBAEP; + } + + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16); } return HAL_OK; } + /** * @brief De-activate and de-initialize an endpoint - * @param USBx: Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + /* Read DEPCTLn register */ - if (ep->is_in == 1) + if (ep->is_in == 1U) { - USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); - USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU))); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU))); + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | + USB_OTG_DIEPCTL_MPSIZ | + USB_OTG_DIEPCTL_TXFNUM | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_EPTYP); } else { - USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); - USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16)); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16)); + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | + USB_OTG_DOEPCTL_MPSIZ | + USB_OTG_DOEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_EPTYP); } + return HAL_OK; } /** * @brief De-activate and de-initialize a dedicated endpoint - * @param USBx: Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + /* Read DEPCTLn register */ - if (ep->is_in == 1) + if (ep->is_in == 1U) { - USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); + USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU))); } else { - USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16)); } + return HAL_OK; } /** * @brief USB_EPStartXfer : setup and starts a transfer over an EP - * @param USBx: Selected device - * @param ep: pointer to endpoint structure - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma) +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { - uint16_t pktcnt = 0; - + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + uint16_t pktcnt; + /* IN endpoint */ - if (ep->is_in == 1) + if (ep->is_in == 1U) { /* Zero Length Packet? */ - if (ep->xfer_len == 0) + if (ep->xfer_len == 0U) { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); } else { @@ -554,109 +573,106 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe * short_packet pktcnt = N + (short_packet * exist ? 1 : 0) */ - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + if (ep->type == EP_TYPE_ISOC) { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29)); - } + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); + } } - if (ep->type != EP_TYPE_ISOC) + + if (ep->type != EP_TYPE_ISOC) + { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0U) { - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0) - { - USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num; - } + USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & 0xFU); } + } if (ep->type == EP_TYPE_ISOC) { - if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0) + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) { - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; } else { - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; } - } - + } + /* EP enable, IN data in FIFO */ - USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); - + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + if (ep->type == EP_TYPE_ISOC) { - USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma); - } + (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len); + } } else /* OUT endpoint */ { /* Program the transfer size and packet count as follows: * pktcnt = N * xfersize = N * maxpacket - */ - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - - if (ep->xfer_len == 0) + */ + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + + if (ep->xfer_len == 0U) { - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ; + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); } else { - pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket; - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19)); ; - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt)); + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt); } if (ep->type == EP_TYPE_ISOC) { - if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0) + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) { - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; } else { - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; } } /* EP enable */ - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); } + return HAL_OK; } /** * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0 - * @param USBx: Selected device - * @param ep: pointer to endpoint structure - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma) +HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(dma); - + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + /* IN endpoint */ - if (ep->is_in == 1) + if (ep->is_in == 1U) { /* Zero Length Packet? */ - if (ep->xfer_len == 0) + if (ep->xfer_len == 0U) { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); } else { @@ -665,26 +681,25 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD * short_packet pktcnt = N + (short_packet * exist ? 1 : 0) */ - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - - if(ep->xfer_len > ep->maxpacket) + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + + if (ep->xfer_len > ep->maxpacket) { ep->xfer_len = ep->maxpacket; } - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); } - + /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0) + if (ep->xfer_len > 0U) { - USBx_DEVICE->DIEPEMPMSK |= 1 << (ep->num); + USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & 0xFU); } - + /* EP enable, IN data in FIFO */ - USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); } else /* OUT endpoint */ { @@ -692,537 +707,615 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD * pktcnt = N * xfersize = N * maxpacket */ - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - - if (ep->xfer_len > 0) + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + + if (ep->xfer_len > 0U) { ep->xfer_len = ep->maxpacket; } - - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)); - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); - + + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); + /* EP enable */ - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); } + return HAL_OK; } /** - * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated + * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated * with the EP/channel - * @param USBx: Selected device - * @param src: pointer to source buffer - * @param ch_ep_num: endpoint or host channel number - * @param len: Number of bytes to write - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used + * @param USBx Selected device + * @param src pointer to source buffer + * @param ch_ep_num endpoint or host channel number + * @param len Number of bytes to write * @retval HAL status */ -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) +HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(dma); - - uint32_t count32b= 0 , index= 0; - count32b = (len + 3) / 4; - for (index = 0; index < count32b; index++, src += 4) + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t *pSrc = (uint32_t *)src; + uint32_t count32b, i; + + count32b = ((uint32_t)len + 3U) / 4U; + for (i = 0U; i < count32b; i++) { - USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src); + USBx_DFIFO((uint32_t)ch_ep_num) = *((__packed uint32_t *)pSrc); + pSrc++; } + return HAL_OK; } /** - * @brief USB_ReadPacket : read a packet from the Tx FIFO associated + * @brief USB_ReadPacket : read a packet from the Tx FIFO associated * with the EP/channel - * @param USBx: Selected device - * @param src: source pointer - * @param ch_ep_num: endpoint or host channel number - * @param len: Number of bytes to read - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used + * @param USBx Selected device + * @param dest source pointer + * @param len Number of bytes to read * @retval pointer to destination buffer */ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { - uint32_t index=0; - uint32_t count32b = (len + 3) / 4; - - for ( index = 0; index < count32b; index++, dest += 4 ) + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t *pDest = (uint32_t *)dest; + uint32_t i; + uint32_t count32b = ((uint32_t)len + 3U) / 4U; + + for (i = 0U; i < count32b; i++) { - *(__packed uint32_t *)dest = USBx_DFIFO(0); - + *(__packed uint32_t *)pDest = USBx_DFIFO(0U); + pDest++; } - return ((void *)dest); + + return ((void *)pDest); } /** * @brief USB_EPSetStall : set a stall condition over an EP - * @param USBx: Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { - if (ep->is_in == 1) + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) { - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0) + if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) { - USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); - } - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); + } + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; } else { - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0) + if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) { - USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); - } - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); + } + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; } + return HAL_OK; } - /** * @brief USB_EPClearStall : Clear a stall condition over an EP - * @param USBx: Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { - if (ep->is_in == 1) + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) { - USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) + USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) { - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ - } + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } } else { - USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; - if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) { - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ - } + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } } return HAL_OK; } /** - * @brief USB_StopDevice : Stop the USB device mode - * @param USBx: Selected device + * @brief USB_StopDevice : Stop the usb device mode + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) { - uint32_t index; - + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + /* Clear Pending interrupt */ - for (index = 0; index < 15 ; index++) + for (i = 0U; i < 15U; i++) { - USBx_INEP(index)->DIEPINT = 0xFF; - USBx_OUTEP(index)->DOEPINT = 0xFF; + USBx_INEP(i)->DIEPINT = 0xFB7FU; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; } - USBx_DEVICE->DAINT = 0xFFFFFFFF; - + /* Clear interrupt masks */ - USBx_DEVICE->DIEPMSK = 0; - USBx_DEVICE->DOEPMSK = 0; - USBx_DEVICE->DAINTMSK = 0; - + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; + /* Flush the FIFO */ - USB_FlushRxFifo(USBx); - USB_FlushTxFifo(USBx , 0x10 ); - + (void)USB_FlushRxFifo(USBx); + (void)USB_FlushTxFifo(USBx, 0x10U); + return HAL_OK; } /** - * @brief USB_SetDevAddress : Stop the USB device mode - * @param USBx: Selected device - * @param address: new device address to be assigned + * @brief USB_SetDevAddress : Stop the usb device mode + * @param USBx Selected device + * @param address new device address to be assigned * This parameter can be a value from 0 to 255 * @retval HAL status */ -HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address) +HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address) { - USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD); - USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD ; - - return HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); + USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; + + return HAL_OK; } /** * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) { - USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ; - HAL_Delay(3); - - return HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; + HAL_Delay(3U); + + return HAL_OK; } /** * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) { - USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ; - HAL_Delay(3); - - return HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + HAL_Delay(3U); + + return HAL_OK; } /** * @brief USB_ReadInterrupts: return the global USB interrupt status - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL status */ -uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx) { - uint32_t tmpreg = 0; - + uint32_t tmpreg; + tmpreg = USBx->GINTSTS; tmpreg &= USBx->GINTMSK; - return tmpreg; + + return tmpreg; } /** * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL status */ -uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) { + uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; + tmpreg = USBx_DEVICE->DAINT; tmpreg &= USBx_DEVICE->DAINTMSK; - return ((tmpreg & 0xffff0000) >> 16); + + return ((tmpreg & 0xffff0000U) >> 16); } /** * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL status */ -uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx) { + uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; + tmpreg = USBx_DEVICE->DAINT; tmpreg &= USBx_DEVICE->DAINTMSK; - return ((tmpreg & 0xFFFF)); + + return ((tmpreg & 0xFFFFU)); } /** * @brief Returns Device OUT EP Interrupt register - * @param USBx: Selected device - * @param epnum: endpoint number + * @param USBx Selected device + * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ -uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) +uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { + uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; - tmpreg = USBx_OUTEP(epnum)->DOEPINT; + + tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; tmpreg &= USBx_DEVICE->DOEPMSK; + return tmpreg; } /** * @brief Returns Device IN EP Interrupt register - * @param USBx: Selected device - * @param epnum: endpoint number + * @param USBx Selected device + * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ -uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) +uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { - uint32_t tmpreg = 0, msk = 0, emp = 0; - + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg, msk, emp; + msk = USBx_DEVICE->DIEPMSK; emp = USBx_DEVICE->DIEPEMPMSK; - msk |= ((emp >> epnum) & 0x1) << 7; - tmpreg = USBx_INEP(epnum)->DIEPINT & msk; + msk |= ((emp >> (epnum & 0xFU)) & 0x1U) << 7; + tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; + return tmpreg; } /** * @brief USB_ClearInterrupts: clear a USB interrupt - * @param USBx: Selected device - * @param interrupt: interrupt flag + * @param USBx Selected device + * @param interrupt interrupt flag * @retval None */ -void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) +void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) { - USBx->GINTSTS |= interrupt; + USBx->GINTSTS |= interrupt; } /** * @brief Returns USB core mode - * @param USBx: Selected device + * @param USBx Selected device * @retval return core mode : Host or Device * This parameter can be one of these values: - * 0 : Host + * 0 : Host * 1 : Device */ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) { - return ((USBx->GINTSTS ) & 0x1); + return ((USBx->GINTSTS) & 0x1U); } - /** * @brief Activate EP0 for Setup transactions - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) { + uint32_t USBx_BASE = (uint32_t)USBx; + /* Set the MPS of the IN EP based on the enumeration speed */ - USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; - - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) + USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; + + if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) { - USBx_INEP(0)->DIEPCTL |= 3; + USBx_INEP(0U)->DIEPCTL |= 3U; } USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; return HAL_OK; } - /** * @brief Prepare the EP0 to start the first control setup - * @param USBx: Selected device - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @param psetup: pointer to setup packet + * @param USBx Selected device + * @param psetup pointer to setup packet * @retval HAL status */ -HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup) +HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup) { - /* Prevent unused argument(s) compilation warning */ UNUSED(psetup); + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_OUTEP(0U)->DOEPTSIZ = 0U; + USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); + USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; + + return HAL_OK; +} + +/** + * @brief Reset the USB Core (needed after USB clock settings change) + * @param USBx Selected device + * @retval HAL status + */ +static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + if (++count > 200000U) + { + return HAL_TIMEOUT; + } + } + while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); - USBx_OUTEP(0)->DOEPTSIZ = 0; - USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8); - USBx_OUTEP(0)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; - - return HAL_OK; + /* Core Soft Reset */ + count = 0U; + USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + + do + { + if (++count > 200000U) + { + return HAL_TIMEOUT; + } + } + while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); + + return HAL_OK; } /** - * @brief USB_HostInit : Initializes the USB OTG controller registers - * for Host mode - * @param USBx: Selected device - * @param cfg: pointer to a USB_OTG_CfgTypeDef structure that contains + * @brief USB_HostInit : Initializes the USB OTG controller registers + * for Host mode + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ -HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { - uint32_t index = 0; - + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + /* Restart the Phy Clock */ - USBx_PCGCCTL = 0; - + USBx_PCGCCTL = 0U; + + /* Disable VBUS sensing */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN); + + /* Disable Battery chargin detector */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); + /* Disable the FS/LS support mode only */ - if((cfg.speed == USB_OTG_SPEED_FULL)&& - (USBx != USB_OTG_FS)) + if ((cfg.speed == USB_OTG_SPEED_FULL) && (USBx != USB_OTG_FS)) { - USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; + USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; } else { - USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); } /* Make sure the FIFOs are flushed. */ - USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */ - USB_FlushRxFifo(USBx); + (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */ + (void)USB_FlushRxFifo(USBx); /* Clear all pending HC Interrupts */ - for (index = 0; index < cfg.Host_channels; index++) + for (i = 0U; i < cfg.Host_channels; i++) { - USBx_HC(index)->HCINT = 0xFFFFFFFF; - USBx_HC(index)->HCINTMSK = 0; + USBx_HC(i)->HCINT = 0xFFFFFFFFU; + USBx_HC(i)->HCINTMSK = 0U; } - + /* Enable VBUS driving */ - USB_DriveVbus(USBx, 1); - - HAL_Delay(200); - + (void)USB_DriveVbus(USBx, 1U); + + HAL_Delay(200U); + /* Disable all interrupts. */ - USBx->GINTMSK = 0; - + USBx->GINTMSK = 0U; + /* Clear any pending interrupts */ - USBx->GINTSTS = 0xFFFFFFFF; - - /* set Rx FIFO size */ - USBx->GRXFSIZ = (uint32_t )0x80; - USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80); - USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0); - - /* Enable the common interrupts */ - if (cfg.dma_enable == DISABLE) + USBx->GINTSTS = 0xFFFFFFFFU; + + if (USBx == USB_OTG_FS) + { + /* set Rx FIFO size */ + USBx->GRXFSIZ = 0x80U; + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U); + USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U); + } + else { - USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + /* set Rx FIFO size */ + USBx->GRXFSIZ = 0x200U; + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U); + USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); } - /* Enable interrupts matching to the Host mode ONLY */ - USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM |\ - USB_OTG_GINTMSK_SOFM |USB_OTG_GINTSTS_DISCINT|\ + /* Enable the common interrupts */ + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + + /* Enable interrupts matching to the Host mode ONLY */ + USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \ + USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); - + return HAL_OK; } /** - * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the + * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the * HCFG register on the PHY type and set the right frame interval - * @param USBx: Selected device - * @param freq: clock frequency + * @param USBx Selected device + * @param freq clock frequency * This parameter can be one of these values: - * HCFG_48_MHZ : Full Speed 48 MHz Clock - * HCFG_6_MHZ : Low Speed 6 MHz Clock + * HCFG_48_MHZ : Full Speed 48 MHz Clock + * HCFG_6_MHZ : Low Speed 6 MHz Clock * @retval HAL status */ -HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq) +HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) { + uint32_t USBx_BASE = (uint32_t)USBx; + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); - USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS); - - if (freq == HCFG_48_MHZ) + USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS; + + if (freq == HCFG_48_MHZ) + { + USBx_HOST->HFIR = 48000U; + } + else if (freq == HCFG_6_MHZ) { - USBx_HOST->HFIR = (uint32_t)48000; + USBx_HOST->HFIR = 6000U; } - else if (freq == HCFG_6_MHZ) + else { - USBx_HOST->HFIR = (uint32_t)6000; - } - return HAL_OK; + /* ... */ + } + + return HAL_OK; } /** * @brief USB_OTG_ResetPort : Reset Host Port - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL status - * @note (1)The application must wait at least 10 ms + * @note (1)The application must wait at least 10 ms * before clearing the reset bit. */ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) { - __IO uint32_t hprt0 = 0; - + uint32_t USBx_BASE = (uint32_t)USBx; + + __IO uint32_t hprt0 = 0U; + hprt0 = USBx_HPRT0; - - hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - - USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); - HAL_Delay (10); /* See Note #1 */ - USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); + HAL_Delay(100U); /* See Note #1 */ + USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); + HAL_Delay(10U); + return HAL_OK; } /** * @brief USB_DriveVbus : activate or de-activate vbus - * @param state: VBUS state + * @param state VBUS state * This parameter can be one of these values: - * 0 : VBUS Active + * 0 : VBUS Active * 1 : VBUS Inactive * @retval HAL status */ -HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state) +HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state) { - __IO uint32_t hprt0 = 0; - + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; + hprt0 = USBx_HPRT0; - hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - - if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 )) + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U)) { - USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); + USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); } - if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 )) + if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U)) { - USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); + USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); } - return HAL_OK; + return HAL_OK; } /** * @brief Return Host Core speed - * @param USBx: Selected device + * @param USBx Selected device * @retval speed : Host speed * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode * @arg USB_OTG_SPEED_LOW: Low speed mode */ -uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx) { - __IO uint32_t hprt0 = 0; - + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; + hprt0 = USBx_HPRT0; return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); } /** * @brief Return Host Current Frame number - * @param USBx: Selected device + * @param USBx Selected device * @retval current frame number */ -uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx) { + uint32_t USBx_BASE = (uint32_t)USBx; + return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); } /** * @brief Initialize a host channel - * @param USBx: Selected device - * @param ch_num : Channel number + * @param USBx Selected device + * @param ch_num Channel number * This parameter can be a value from 1 to 15 - * @param epnum: Endpoint number + * @param epnum Endpoint number * This parameter can be a value from 1 to 15 - * @param dev_address: Current device address + * @param dev_address Current device address * This parameter can be a value from 0 to 255 - * @param speed: Current device speed + * @param speed Current device speed * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode * @arg USB_OTG_SPEED_LOW: Low speed mode - * @param ep_type: Endpoint Type + * @param ep_type Endpoint Type * This parameter can be one of these values: * @arg EP_TYPE_CTRL: Control type * @arg EP_TYPE_ISOC: Isochronous type * @arg EP_TYPE_BULK: Bulk type * @arg EP_TYPE_INTR: Interrupt type - * @param mps: Max Packet Size + * @param mps Max Packet Size * This parameter can be a value from 0 to32K * @retval HAL state */ -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, @@ -1230,371 +1323,397 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ep_type, uint16_t mps) { - + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t HCcharEpDir, HCcharLowSpeed; + /* Clear old interrupt conditions for this host channel. */ - USBx_HC(ch_num)->HCINT = 0xFFFFFFFF; - + USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU; + /* Enable channel interrupts required for this transfer. */ - switch (ep_type) - { - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - - USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ - USB_OTG_HCINTMSK_STALLM |\ - USB_OTG_HCINTMSK_TXERRM |\ - USB_OTG_HCINTMSK_DTERRM |\ - USB_OTG_HCINTMSK_AHBERR |\ - USB_OTG_HCINTMSK_NAKM ; - - if (epnum & 0x80) - { - USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; - } - break; - - case EP_TYPE_INTR: - - USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ - USB_OTG_HCINTMSK_STALLM |\ - USB_OTG_HCINTMSK_TXERRM |\ - USB_OTG_HCINTMSK_DTERRM |\ - USB_OTG_HCINTMSK_NAKM |\ - USB_OTG_HCINTMSK_AHBERR |\ - USB_OTG_HCINTMSK_FRMORM ; - - if (epnum & 0x80) - { - USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; - } - - break; - case EP_TYPE_ISOC: - - USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ - USB_OTG_HCINTMSK_ACKM |\ - USB_OTG_HCINTMSK_AHBERR |\ - USB_OTG_HCINTMSK_FRMORM ; - - if (epnum & 0x80) - { - USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); - } - break; + switch (ep_type) + { + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_NAKM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + } + break; + + case EP_TYPE_INTR: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_NAKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + } + + break; + + case EP_TYPE_ISOC: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); + } + break; + + default: + ret = HAL_ERROR; + break; } - + /* Enable the top level host channel interrupt. */ - USBx_HOST->HAINTMSK |= (1 << ch_num); - + USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); + /* Make sure host channel interrupts are enabled. */ USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; - + /* Program the HCCHAR register */ - USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD) |\ - (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\ - ((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)|\ - (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\ - ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\ - (mps & USB_OTG_HCCHAR_MPSIZ)); - + if ((epnum & 0x80U) == 0x80U) + { + HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR; + } + else + { + HCcharEpDir = 0U; + } + + if (speed == HPRT0_PRTSPD_LOW_SPEED) + { + HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; + } + else + { + HCcharLowSpeed = 0U; + } + + USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | + ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | + (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | + ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed; + if (ep_type == EP_TYPE_INTR) { - USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; + USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; } - return HAL_OK; + return ret; } /** * @brief Start a transfer over a host channel - * @param USBx: Selected device - * @param hc: pointer to host channel structure - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used + * @param USBx Selected device + * @param hc pointer to host channel structure * @retval HAL state */ -#if defined (__CC_ARM) /*!< ARM Compiler */ -#pragma O0 -#elif defined (__GNUC__) /*!< GNU Compiler */ -#pragma GCC optimize ("O0") -#endif /* __CC_ARM */ -HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma) -{ - uint8_t is_oddframe = 0; - uint16_t len_words = 0; - uint16_t num_packets = 0; - uint16_t max_hc_pkt_count = 256; - uint32_t tmpreg = 0; - +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)hc->ch_num; + static __IO uint32_t tmpreg = 0U; + uint8_t is_oddframe; + uint16_t len_words; + uint16_t num_packets; + uint16_t max_hc_pkt_count = 256U; + /* Compute the expected number of packets associated to the transfer */ - if (hc->xfer_len > 0) + if (hc->xfer_len > 0U) { - num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet; - + num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); + if (num_packets > max_hc_pkt_count) { num_packets = max_hc_pkt_count; - hc->xfer_len = num_packets * hc->max_packet; + hc->xfer_len = (uint32_t)num_packets * hc->max_packet; } } else { - num_packets = 1; + num_packets = 1U; } - if (hc->ep_is_in) + if (hc->ep_is_in != 0U) { - hc->xfer_len = num_packets * hc->max_packet; + hc->xfer_len = (uint32_t)num_packets * hc->max_packet; } - + /* Initialize the HCTSIZn register */ - USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\ - ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ - (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID); - - if (dma) - { - /* xfer_buff MUST be 32-bits aligned */ - USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff; - } - - is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1; - USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; - USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29); - + USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) | + (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); + + is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U; + USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; + USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; + /* Set host channel enable */ - tmpreg = USBx_HC(hc->ch_num)->HCCHAR; + tmpreg = USBx_HC(ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + + /* make sure to set the correct ep direction */ + if (hc->ep_is_in != 0U) + { + tmpreg |= USB_OTG_HCCHAR_EPDIR; + } + else + { + tmpreg &= ~USB_OTG_HCCHAR_EPDIR; + } tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hc->ch_num)->HCCHAR = tmpreg; - - if (dma == 0) /* Slave mode */ - { - if((hc->ep_is_in == 0) && (hc->xfer_len > 0)) + USBx_HC(ch_num)->HCCHAR = tmpreg; + + if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U)) { - switch(hc->ep_type) + switch (hc->ep_type) { /* Non periodic transfer */ - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - - len_words = (hc->xfer_len + 3) / 4; - - /* check if there is enough space in FIFO space */ - if(len_words > (USBx->HNPTXSTS & 0xFFFF)) - { - /* need to process data in nptxfempty interrupt */ - USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; - } - break; + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + + /* check if there is enough space in FIFO space */ + if (len_words > (USBx->HNPTXSTS & 0xFFFFU)) + { + /* need to process data in nptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; + } + break; + /* Periodic transfer */ - case EP_TYPE_INTR: - case EP_TYPE_ISOC: - len_words = (hc->xfer_len + 3) / 4; - /* check if there is enough space in FIFO space */ - if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */ - { - /* need to process data in ptxfempty interrupt */ - USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; - } - break; - - default: - break; + case EP_TYPE_INTR: + case EP_TYPE_ISOC: + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + /* check if there is enough space in FIFO space */ + if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ + { + /* need to process data in ptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; + } + break; + + default: + break; } - + /* Write packet into the Tx FIFO. */ - USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0); + (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len); } - } - + return HAL_OK; } /** * @brief Read all host channel interrupts status - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL state */ -uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx) { - return ((USBx_HOST->HAINT) & 0xFFFF); + uint32_t USBx_BASE = (uint32_t)USBx; + + return ((USBx_HOST->HAINT) & 0xFFFFU); } /** * @brief Halt a host channel - * @param USBx: Selected device - * @param hc_num: Host Channel number + * @param USBx Selected device + * @param hc_num Host Channel number * This parameter can be a value from 1 to 15 * @retval HAL state */ -HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num) +HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { - uint32_t count = 0; - + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t hcnum = (uint32_t)hc_num; + uint32_t count = 0U; + uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; + /* Check for space in the request queue to issue the halt. */ - if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18))) + if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - - if ((USBx->HNPTXSTS & 0xFFFF) == 0) + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + + if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) { - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; - do + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; + do { - if (++count > 1000) + if (++count > 1000U) { break; } - } - while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); } else { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; } } else { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - - if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0) + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + + if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U) { - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; - do + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; + do { - if (++count > 1000) + if (++count > 1000U) { break; } - } - while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); } else { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; } } - + return HAL_OK; } /** * @brief Initiate Do Ping protocol - * @param USBx: Selected device - * @param hc_num: Host Channel number + * @param USBx Selected device + * @param hc_num Host Channel number * This parameter can be a value from 1 to 15 * @retval HAL state */ -HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num) +HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) { - uint8_t num_packets = 1; - uint32_t tmpreg = 0; - - USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ - USB_OTG_HCTSIZ_DOPING; - + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t chnum = (uint32_t)ch_num; + uint32_t num_packets = 1U; + uint32_t tmpreg; + + USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + USB_OTG_HCTSIZ_DOPING; + /* Set host channel enable */ - tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg = USBx_HC(chnum)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; - - return HAL_OK; + USBx_HC(chnum)->HCCHAR = tmpreg; + + return HAL_OK; } /** * @brief Stop Host Core - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL state */ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) { - uint8_t index; - uint32_t count = 0; - uint32_t value = 0; - - USB_DisableGlobalInt(USBx); - - /* Flush FIFO */ - USB_FlushTxFifo(USBx, 0x10); - USB_FlushRxFifo(USBx); - + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t count = 0U; + uint32_t value; + uint32_t i; + + + (void)USB_DisableGlobalInt(USBx); + + /* Flush FIFO */ + (void)USB_FlushTxFifo(USBx, 0x10U); + (void)USB_FlushRxFifo(USBx); + /* Flush out any leftover queued requests. */ - for (index = 0; index <= 15; index++) + for (i = 0U; i <= 15U; i++) { - value = USBx_HC(index)->HCCHAR; + value = USBx_HC(i)->HCCHAR; value |= USB_OTG_HCCHAR_CHDIS; - value &= ~USB_OTG_HCCHAR_CHENA; + value &= ~USB_OTG_HCCHAR_CHENA; value &= ~USB_OTG_HCCHAR_EPDIR; - USBx_HC(index)->HCCHAR = value; + USBx_HC(i)->HCCHAR = value; } - + /* Halt all channels to put them into a known state. */ - for (index = 0; index <= 15; index++) + for (i = 0U; i <= 15U; i++) { - value = USBx_HC(index)->HCCHAR ; + value = USBx_HC(i)->HCCHAR; value |= USB_OTG_HCCHAR_CHDIS; - value |= USB_OTG_HCCHAR_CHENA; + value |= USB_OTG_HCCHAR_CHENA; value &= ~USB_OTG_HCCHAR_EPDIR; - USBx_HC(index)->HCCHAR = value; - - USBx_HC(index)->HCCHAR = value; - do + USBx_HC(i)->HCCHAR = value; + + do { - if (++count > 1000) + if (++count > 1000U) { break; } } - while ((USBx_HC(index)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); } - /* Clear any pending Host interrupts */ - USBx_HOST->HAINT = 0xFFFFFFFF; - USBx->GINTSTS = 0xFFFFFFFF; - USB_EnableGlobalInt(USBx); - return HAL_OK; + /* Clear any pending Host interrupts */ + USBx_HOST->HAINT = 0xFFFFFFFFU; + USBx->GINTSTS = 0xFFFFFFFFU; + (void)USB_EnableGlobalInt(USBx); + + return HAL_OK; } /** - * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling - * @param USBx : Selected device + * @brief USB_ActivateRemoteWakeup active remote wakeup signalling + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) { - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + uint32_t USBx_BASE = (uint32_t)USBx; + + if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) { /* active Remote wakeup signalling */ USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; } + return HAL_OK; } /** - * @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling - * @param USBx : Selected device + * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) { + uint32_t USBx_BASE = (uint32_t)USBx; + /* active Remote wakeup signalling */ - USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); + USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); + return HAL_OK; } +#endif /* defined USB_OTG_FS || defined USB_OTG_HS */ -#endif /* USB_OTG_FS */ - -/*============================================================================== - USB Device FS peripheral available on STM32L432xx, STM32L433xx, STM32L442xx) - and STM32L443xx devices -==============================================================================*/ #if defined (USB) /** * @brief Initializes the USB Core @@ -1605,15 +1724,15 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - /* Prevent unused argument(s) compilation warning */ UNUSED(USBx); UNUSED(cfg); + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + return HAL_OK; } @@ -1625,15 +1744,17 @@ HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) { - uint32_t winterruptmask = 0; - + uint16_t winterruptmask; + /* Set winterruptmask variable */ - winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ - | USB_CNTR_ESOFM | USB_CNTR_RESETM; - + winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | + USB_CNTR_SUSPM | USB_CNTR_ERRM | + USB_CNTR_SOFM | USB_CNTR_ESOFM | + USB_CNTR_RESETM | USB_CNTR_L1REQM; + /* Set interrupt mask */ USBx->CNTR |= winterruptmask; - + return HAL_OK; } @@ -1645,15 +1766,17 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) { - uint32_t winterruptmask = 0; - + uint16_t winterruptmask; + /* Set winterruptmask variable */ - winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ - | USB_CNTR_ESOFM | USB_CNTR_RESETM; - + winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | + USB_CNTR_SUSPM | USB_CNTR_ERRM | + USB_CNTR_SOFM | USB_CNTR_ESOFM | + USB_CNTR_RESETM | USB_CNTR_L1REQM; + /* Clear interrupt mask */ USBx->CNTR &= ~winterruptmask; - + return HAL_OK; } @@ -1665,29 +1788,28 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) * @arg USB_DEVICE_MODE: Peripheral mode mode * @retval HAL status */ -HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode) +HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - /* Prevent unused argument(s) compilation warning */ UNUSED(USBx); UNUSED(mode); + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ return HAL_OK; } /** - * @brief USB_DevInit : Initializes the USB controller registers + * @brief USB_DevInit : Initializes the USB controller registers * for device mode * @param USBx : Selected device * @param cfg : pointer to a USB_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ -HAL_StatusTypeDef USB_DevInit (USB_TypeDef *USBx, USB_CfgTypeDef cfg) +HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) { /* Prevent unused argument(s) compilation warning */ UNUSED(cfg); @@ -1695,16 +1817,19 @@ HAL_StatusTypeDef USB_DevInit (USB_TypeDef *USBx, USB_CfgTypeDef cfg) /* Init Device */ /*CNTR_FRES = 1*/ USBx->CNTR = USB_CNTR_FRES; - + /*CNTR_FRES = 0*/ USBx->CNTR = 0; - + /*Clear pending interrupts*/ USBx->ISTR = 0; - + /*Set Btable Address*/ USBx->BTABLE = BTABLE_ADDRESS; - + + /* Enable USB Device Interrupt mask */ + (void)USB_EnableGlobalInt(USBx); + return HAL_OK; } @@ -1716,17 +1841,17 @@ HAL_StatusTypeDef USB_DevInit (USB_TypeDef *USBx, USB_CfgTypeDef cfg) 15 means Flush all Tx FIFOs * @retval HAL status */ -HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num ) +HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - /* Prevent unused argument(s) compilation warning */ UNUSED(USBx); UNUSED(num); + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + return HAL_OK; } @@ -1737,14 +1862,14 @@ HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num ) */ HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - return HAL_OK; } @@ -1756,36 +1881,57 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx) */ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) { + HAL_StatusTypeDef ret = HAL_OK; + uint16_t wEpRegVal; + + wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK; + /* initialize Endpoint */ switch (ep->type) { - case EP_TYPE_CTRL: - PCD_SET_EPTYPE(USBx, ep->num, USB_EP_CONTROL); - break; - case EP_TYPE_BULK: - PCD_SET_EPTYPE(USBx, ep->num, USB_EP_BULK); - break; - case EP_TYPE_INTR: - PCD_SET_EPTYPE(USBx, ep->num, USB_EP_INTERRUPT); - break; - case EP_TYPE_ISOC: - PCD_SET_EPTYPE(USBx, ep->num, USB_EP_ISOCHRONOUS); - break; - default: + case EP_TYPE_CTRL: + wEpRegVal |= USB_EP_CONTROL; + break; + + case EP_TYPE_BULK: + wEpRegVal |= USB_EP_BULK; + break; + + case EP_TYPE_INTR: + wEpRegVal |= USB_EP_INTERRUPT; + break; + + case EP_TYPE_ISOC: + wEpRegVal |= USB_EP_ISOCHRONOUS; + break; + + default: + ret = HAL_ERROR; break; - } - + } + + PCD_SET_ENDPOINT(USBx, ep->num, wEpRegVal); + PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num); - - if (ep->doublebuffer == 0) + + if (ep->doublebuffer == 0U) { - if (ep->is_in) + if (ep->is_in != 0U) { /*Set the endpoint Transmit buffer address */ PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress); PCD_CLEAR_TX_DTOG(USBx, ep->num); - /* Configure NAK status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + + if (ep->type != EP_TYPE_ISOC) + { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + } + else + { + /* Configure TX Endpoint to disabled state */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + } } else { @@ -1801,36 +1947,46 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) /*Double Buffer*/ else { - /*Set the endpoint as double buffered*/ + /* Set the endpoint as double buffered */ PCD_SET_EP_DBUF(USBx, ep->num); - /*Set buffer address for double buffered mode*/ - PCD_SET_EP_DBUF_ADDR(USBx, ep->num,ep->pmaaddr0, ep->pmaaddr1); - - if (ep->is_in==0) + /* Set buffer address for double buffered mode */ + PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1); + + if (ep->is_in == 0U) { - /* Clear the data toggle bits for the endpoint IN/OUT*/ + /* Clear the data toggle bits for the endpoint IN/OUT */ PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); - - /* Reset value of the data toggle bits for the endpoint out*/ + + /* Reset value of the data toggle bits for the endpoint out */ PCD_TX_DTOG(USBx, ep->num); - + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } else { - /* Clear the data toggle bits for the endpoint IN/OUT*/ + /* Clear the data toggle bits for the endpoint IN/OUT */ PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); PCD_RX_DTOG(USBx, ep->num); - /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + + if (ep->type != EP_TYPE_ISOC) + { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + } + else + { + /* Configure TX Endpoint to disabled state */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + } + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); } } - - return HAL_OK; + + return ret; } /** @@ -1841,13 +1997,13 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) */ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0U) { - if (ep->is_in) + if (ep->is_in != 0U) { PCD_CLEAR_TX_DTOG(USBx, ep->num); /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } else { @@ -1858,16 +2014,16 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) } /*Double Buffer*/ else - { - if (ep->is_in==0) + { + if (ep->is_in == 0U) { /* Clear the data toggle bits for the endpoint IN/OUT*/ PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); - + /* Reset value of the data toggle bits for the endpoint out*/ PCD_TX_DTOG(USBx, ep->num); - + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } @@ -1882,7 +2038,7 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); } } - + return HAL_OK; } @@ -1892,36 +2048,36 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) * @param ep: pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep, uint8_t dma) +HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - uint16_t pmabuffer = 0; + uint16_t pmabuffer; uint32_t len = ep->xfer_len; - + /* IN endpoint */ - if (ep->is_in == 1) + if (ep->is_in == 1U) { /*Multi packet transfer*/ if (ep->xfer_len > ep->maxpacket) { - len=ep->maxpacket; - ep->xfer_len-=len; + len = ep->maxpacket; + ep->xfer_len -= len; } else - { - len=ep->xfer_len; - ep->xfer_len =0; + { + len = ep->xfer_len; + ep->xfer_len = 0U; } - + /* configure and validate Tx endpoint */ - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0U) { - USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, len); + USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len); PCD_SET_EP_TX_CNT(USBx, ep->num, len); } else { /* Write the data to the USB endpoint */ - if (PCD_GET_ENDPOINT(USBx, ep->num)& USB_EP_DTOG_TX) + if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) { /* Set the Double buffer counter for pmabuffer1 */ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); @@ -1933,10 +2089,10 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep, uint8_t PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); pmabuffer = ep->pmaaddr0; } - USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, len); + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); PCD_FreeUserBuffer(USBx, ep->num, ep->is_in); } - + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); } else /* OUT endpoint */ @@ -1944,17 +2100,17 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep, uint8_t /* Multi packet transfer*/ if (ep->xfer_len > ep->maxpacket) { - len=ep->maxpacket; - ep->xfer_len-=len; + len = ep->maxpacket; + ep->xfer_len -= len; } else { - len=ep->xfer_len; - ep->xfer_len =0; + len = ep->xfer_len; + ep->xfer_len = 0U; } - + /* configure and validate Rx endpoint */ - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0U) { /*Set RX buffer count*/ PCD_SET_EP_RX_CNT(USBx, ep->num, len); @@ -1962,17 +2118,17 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep, uint8_t else { /*Set the Double buffer counter*/ - PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); } - + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); } - + return HAL_OK; } /** - * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated + * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated * with the EP/channel * @param USBx : Selected device * @param src : pointer to source buffer @@ -1982,22 +2138,20 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep, uint8_t */ HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - /* Prevent unused argument(s) compilation warning */ UNUSED(USBx); UNUSED(src); UNUSED(ch_ep_num); UNUSED(len); - + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ return HAL_OK; } /** - * @brief USB_ReadPacket : read a packet from the Tx FIFO associated + * @brief USB_ReadPacket : read a packet from the Tx FIFO associated * with the EP/channel * @param USBx : Selected device * @param dest : destination pointer @@ -2006,43 +2160,34 @@ HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep */ void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - /* Prevent unused argument(s) compilation warning */ UNUSED(USBx); UNUSED(dest); UNUSED(len); - + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ return ((void *)NULL); } /** * @brief USB_EPSetStall : set a stall condition over an EP * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param ep: pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx , USB_EPTypeDef *ep) +HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - if (ep->num == 0) + if (ep->is_in != 0U) { - /* This macro sets STALL status for RX & TX*/ - PCD_SET_EP_TXRX_STATUS(USBx, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL); + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL); } else { - if (ep->is_in) - { - PCD_SET_EP_TX_STATUS(USBx, ep->num , USB_EP_TX_STALL); - } - else - { - PCD_SET_EP_RX_STATUS(USBx, ep->num , USB_EP_RX_STALL); - } + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL); } + return HAL_OK; } @@ -2054,7 +2199,7 @@ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx , USB_EPTypeDef *ep) */ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - if (ep->is_in) + if (ep->is_in != 0U) { PCD_CLEAR_TX_DTOG(USBx, ep->num); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); @@ -2076,13 +2221,13 @@ HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) { /* disable all interrupts and force USB reset */ USBx->CNTR = USB_CNTR_FRES; - + /* clear interrupt status register */ USBx->ISTR = 0; - + /* switch-off device */ USBx->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN); - + return HAL_OK; } @@ -2093,14 +2238,14 @@ HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) * This parameter can be a value from 0 to 255 * @retval HAL status */ -HAL_StatusTypeDef USB_SetDevAddress (USB_TypeDef *USBx, uint8_t address) +HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address) { - if(address == 0) + if (address == 0U) { - /* set device address and enable function */ - USBx->DADDR = USB_DADDR_EF; + /* set device address and enable function */ + USBx->DADDR = USB_DADDR_EF; } - + return HAL_OK; } @@ -2109,11 +2254,11 @@ HAL_StatusTypeDef USB_SetDevAddress (USB_TypeDef *USBx, uint8_t address) * @param USBx : Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DevConnect (USB_TypeDef *USBx) +HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx) { - /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */ - USB->BCDR |= USB_BCDR_DPPU; - + /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */ + USBx->BCDR |= USB_BCDR_DPPU; + return HAL_OK; } @@ -2122,11 +2267,11 @@ HAL_StatusTypeDef USB_DevConnect (USB_TypeDef *USBx) * @param USBx : Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DevDisconnect (USB_TypeDef *USBx) +HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx) { - /* Disable DP Pull-Down bit*/ - USB->BCDR &= ~(USB_BCDR_DPPU); - + /* Disable DP Pull-Up bit to disconnect the Internal PU resistor on USB DP line */ + USBx->BCDR &= (uint16_t)(~(USB_BCDR_DPPU)); + return HAL_OK; } @@ -2135,10 +2280,10 @@ HAL_StatusTypeDef USB_DevDisconnect (USB_TypeDef *USBx) * @param USBx : Selected device * @retval HAL status */ -uint32_t USB_ReadInterrupts (USB_TypeDef *USBx) +uint32_t USB_ReadInterrupts(USB_TypeDef *USBx) { - uint32_t tmpreg = 0; - + uint32_t tmpreg; + tmpreg = USBx->ISTR; return tmpreg; } @@ -2148,16 +2293,14 @@ uint32_t USB_ReadInterrupts (USB_TypeDef *USBx) * @param USBx : Selected device * @retval HAL status */ -uint32_t USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx) +uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - return (0); } @@ -2166,16 +2309,14 @@ uint32_t USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx) * @param USBx : Selected device * @retval HAL status */ -uint32_t USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx) +uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - return (0); } @@ -2186,17 +2327,15 @@ uint32_t USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx) * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ -uint32_t USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) +uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - /* Prevent unused argument(s) compilation warning */ UNUSED(USBx); UNUSED(epnum); - + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ return (0); } @@ -2207,74 +2346,68 @@ uint32_t USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ -uint32_t USB_ReadDevInEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) +uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - /* Prevent unused argument(s) compilation warning */ UNUSED(USBx); UNUSED(epnum); - + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ return (0); } /** * @brief USB_ClearInterrupts: clear a USB interrupt - * @param USBx : Selected device - * @param interrupt : interrupt flag + * @param USBx Selected device + * @param interrupt interrupt flag * @retval None */ -void USB_ClearInterrupts (USB_TypeDef *USBx, uint32_t interrupt) +void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - /* Prevent unused argument(s) compilation warning */ UNUSED(USBx); UNUSED(interrupt); + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ } /** * @brief Prepare the EP0 to start the first control setup - * @param USBx : Selected device - * @param psetup : pointer to setup packet + * @param USBx Selected device + * @param psetup pointer to setup packet * @retval HAL status */ -HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t dma ,uint8_t *psetup) +HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - /* Prevent unused argument(s) compilation warning */ UNUSED(USBx); UNUSED(psetup); - UNUSED(dma); - + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ return HAL_OK; } /** * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx) { USBx->CNTR |= USB_CNTR_RESUME; - + return HAL_OK; } /** * @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx) @@ -2284,114 +2417,96 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx) } /** - * @brief Copy a buffer from user memory area to packet memory area (PMA) - * @param USBx : pointer to USB register. - * @param pbUsrBuf : pointer to user memory area. - * @param wPMABufAddr : address into PMA. - * @param wNBytes : number of bytes to be copied. + * @brief Copy a buffer from user memory area to packet memory area (PMA) + * @param USBx USB peripheral instance register address. + * @param pbUsrBuf pointer to user memory area. + * @param wPMABufAddr address into PMA. + * @param wNBytes: no. of bytes to be copied. * @retval None */ void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { - uint32_t n = (wNBytes + 1) >> 1; - uint32_t i; - uint16_t temp1, temp2; + uint32_t n = ((uint32_t)wNBytes + 1U) >> 1; + uint32_t BaseAddr = (uint32_t)USBx; + uint32_t i, temp1, temp2; uint16_t *pdwVal; - pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400); + uint8_t *pBuf = pbUsrBuf; - for (i = n; i != 0; i--) + pdwVal = (uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); + + for (i = n; i != 0U; i--) { - temp1 = (uint16_t) * pbUsrBuf; - pbUsrBuf++; - temp2 = temp1 | (uint16_t) * pbUsrBuf << 8; - *pdwVal++ = temp2; - pbUsrBuf++; + temp1 = (uint16_t) * pBuf; + pBuf++; + temp2 = temp1 | ((uint16_t)((uint16_t) * pBuf << 8)); + *pdwVal = (uint16_t)temp2; + pdwVal++; + + if (PMA_ACCESS > 1U) + { + pdwVal++; + } + pBuf++; } } /** - * @brief Copy a buffer from user memory area to packet memory area (PMA) - * @param USBx : pointer to USB register. -* @param pbUsrBuf : pointer to user memory area. - * @param wPMABufAddr : address into PMA. - * @param wNBytes : number of bytes to be copied. + * @brief Copy a buffer from user memory area to packet memory area (PMA) + * @param USBx: USB peripheral instance register address. + * @param pbUsrBuf pointer to user memory area. + * @param wPMABufAddr address into PMA. + * @param wNBytes: no. of bytes to be copied. * @retval None */ void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { - uint32_t n = (wNBytes + 1) >> 1; - uint32_t i; + uint32_t n = (uint32_t)wNBytes >> 1; + uint32_t BaseAddr = (uint32_t)USBx; + uint32_t i, temp; uint16_t *pdwVal; - pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400); - for (i = n; i != 0; i--) - { - *(uint16_t*)pbUsrBuf++ = *pdwVal++; - pbUsrBuf++; - } -} -#endif /* USB */ -/** - * @} - */ -/** - * @} - */ + uint8_t *pBuf = pbUsrBuf; -#if defined (USB_OTG_FS) -/** @addtogroup USB_LL_Private_Functions - * @{ - */ -/** - * @brief Reset the USB Core (needed after USB clock settings change) - * @param USBx : Selected device - * @retval HAL status - */ -static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t count = 0; - - /* Wait for AHB master IDLE state. */ - do + pdwVal = (uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); + + for (i = n; i != 0U; i--) { - if (++count > 200000) + temp = *pdwVal; + pdwVal++; + *pBuf = (uint8_t)((temp >> 0) & 0xFFU); + pBuf++; + *pBuf = (uint8_t)((temp >> 8) & 0xFFU); + pBuf++; + + if (PMA_ACCESS > 1U) { - return HAL_TIMEOUT; + pdwVal++; } } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0); - - /* Core Soft Reset */ - count = 0; - USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; - - do + + if ((wNBytes % 2U) != 0U) { - if (++count > 200000) - { - return HAL_TIMEOUT; - } + temp = *pdwVal; + pdwVal++; + *pBuf = (uint8_t)((temp >> 0) & 0xFFU); + pBuf++; } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); - - return HAL_OK; } +#endif /* USB */ + /** * @} */ -#endif /* USB_OTG_FS */ - -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ /** * @} */ +#endif /* defined (USB) || defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ + /** * @} */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index ed3464d3fc..abfad245e6 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -3,12 +3,12 @@ * STM32F0: 1.7.0 * STM32F1: 1.1.2 * STM32F2: 1.2.2 - * STM32F3: 1.5.0 + * STM32F3: 1.5.1 * STM32F4: 1.7.4 * STM32F7: 1.2.5 * STM32L0: 1.8.2 * STM32L1: 1.3.1 - * STM32L4: 1.8.2 + * STM32L4: 1.8.3 Release notes of each STM32YYxx HAL Drivers available here: diff --git a/variants/DISCO_L475VG_IOT/stm32l4xx_hal_conf.h b/variants/DISCO_L475VG_IOT/stm32l4xx_hal_conf.h index e35f48aed9..8d16799cab 100644 --- a/variants/DISCO_L475VG_IOT/stm32l4xx_hal_conf.h +++ b/variants/DISCO_L475VG_IOT/stm32l4xx_hal_conf.h @@ -107,11 +107,11 @@ * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -119,7 +119,7 @@ * This value is the default MSI range value after Reset. */ #if !defined (MSI_VALUE) - #define MSI_VALUE ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/ + #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* MSI_VALUE */ /** @@ -128,7 +128,7 @@ * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** @@ -139,7 +139,7 @@ * which is subject to manufacturing process variations. */ #if !defined (HSI48_VALUE) - #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. + #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. The real value my vary depending on manufacturing process variations.*/ #endif /* HSI48_VALUE */ @@ -147,7 +147,7 @@ * @brief Internal Low Speed oscillator (LSI) value. */ #if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ + #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature.*/ @@ -156,11 +156,11 @@ * This value is used by the UART, RTC HAL module to compute the system frequency */ #if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/ + #define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/ #endif /* LSE_VALUE */ #if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -169,7 +169,7 @@ * frequency. */ #if !defined (EXTERNAL_SAI1_CLOCK_VALUE) - #define EXTERNAL_SAI1_CLOCK_VALUE ((uint32_t)48000U) /*!< Value of the SAI1 External clock source in Hz*/ + #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1 External clock source in Hz*/ #endif /* EXTERNAL_SAI1_CLOCK_VALUE */ /** @@ -178,7 +178,7 @@ * frequency. */ #if !defined (EXTERNAL_SAI2_CLOCK_VALUE) - #define EXTERNAL_SAI2_CLOCK_VALUE ((uint32_t)48000U) /*!< Value of the SAI2 External clock source in Hz*/ + #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2 External clock source in Hz*/ #endif /* EXTERNAL_SAI2_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, @@ -188,8 +188,8 @@ /** * @brief This is the HAL system configuration section */ -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0x0FU) /*!< tick interrupt priority */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ #define USE_RTOS 0U #define PREFETCH_ENABLE 0U #define INSTRUCTION_CACHE_ENABLE 1U @@ -202,6 +202,50 @@ */ /* #define USE_FULL_ASSERT 1U */ +/* ################## Register callback feature configuration ############### */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/deregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32l4xx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U +#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_TSC_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U + /* ################## SPI peripheral configuration ########################## */ /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver diff --git a/variants/NUCLEO_L432KC/stm32l4xx_hal_conf.h b/variants/NUCLEO_L432KC/stm32l4xx_hal_conf.h index e76e19cdbb..90109e68fa 100644 --- a/variants/NUCLEO_L432KC/stm32l4xx_hal_conf.h +++ b/variants/NUCLEO_L432KC/stm32l4xx_hal_conf.h @@ -107,11 +107,11 @@ * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -119,7 +119,7 @@ * This value is the default MSI range value after Reset. */ #if !defined (MSI_VALUE) - #define MSI_VALUE ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/ + #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* MSI_VALUE */ /** @@ -128,7 +128,7 @@ * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** @@ -139,7 +139,7 @@ * which is subject to manufacturing process variations. */ #if !defined (HSI48_VALUE) - #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. + #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. The real value my vary depending on manufacturing process variations.*/ #endif /* HSI48_VALUE */ @@ -147,7 +147,7 @@ * @brief Internal Low Speed oscillator (LSI) value. */ #if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ + #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature.*/ @@ -156,11 +156,11 @@ * This value is used by the UART, RTC HAL module to compute the system frequency */ #if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/ + #define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/ #endif /* LSE_VALUE */ #if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -169,7 +169,7 @@ * frequency. */ #if !defined (EXTERNAL_SAI1_CLOCK_VALUE) - #define EXTERNAL_SAI1_CLOCK_VALUE ((uint32_t)48000U) /*!< Value of the SAI1 External clock source in Hz*/ + #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1 External clock source in Hz*/ #endif /* EXTERNAL_SAI1_CLOCK_VALUE */ /** @@ -178,7 +178,7 @@ * frequency. */ #if !defined (EXTERNAL_SAI2_CLOCK_VALUE) - #define EXTERNAL_SAI2_CLOCK_VALUE ((uint32_t)48000U) /*!< Value of the SAI2 External clock source in Hz*/ + #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2 External clock source in Hz*/ #endif /* EXTERNAL_SAI2_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, @@ -188,8 +188,8 @@ /** * @brief This is the HAL system configuration section */ -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0x0FU) /*!< tick interrupt priority */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ #define USE_RTOS 0U #define PREFETCH_ENABLE 0U #define INSTRUCTION_CACHE_ENABLE 1U @@ -202,6 +202,50 @@ */ /* #define USE_FULL_ASSERT 1U */ +/* ################## Register callback feature configuration ############### */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/deregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32l4xx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U +#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_TSC_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U + /* ################## SPI peripheral configuration ########################## */ /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver diff --git a/variants/NUCLEO_L476RG/stm32l4xx_hal_conf.h b/variants/NUCLEO_L476RG/stm32l4xx_hal_conf.h index e76e19cdbb..90109e68fa 100644 --- a/variants/NUCLEO_L476RG/stm32l4xx_hal_conf.h +++ b/variants/NUCLEO_L476RG/stm32l4xx_hal_conf.h @@ -107,11 +107,11 @@ * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -119,7 +119,7 @@ * This value is the default MSI range value after Reset. */ #if !defined (MSI_VALUE) - #define MSI_VALUE ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/ + #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* MSI_VALUE */ /** @@ -128,7 +128,7 @@ * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** @@ -139,7 +139,7 @@ * which is subject to manufacturing process variations. */ #if !defined (HSI48_VALUE) - #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. + #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. The real value my vary depending on manufacturing process variations.*/ #endif /* HSI48_VALUE */ @@ -147,7 +147,7 @@ * @brief Internal Low Speed oscillator (LSI) value. */ #if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ + #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature.*/ @@ -156,11 +156,11 @@ * This value is used by the UART, RTC HAL module to compute the system frequency */ #if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/ + #define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/ #endif /* LSE_VALUE */ #if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -169,7 +169,7 @@ * frequency. */ #if !defined (EXTERNAL_SAI1_CLOCK_VALUE) - #define EXTERNAL_SAI1_CLOCK_VALUE ((uint32_t)48000U) /*!< Value of the SAI1 External clock source in Hz*/ + #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1 External clock source in Hz*/ #endif /* EXTERNAL_SAI1_CLOCK_VALUE */ /** @@ -178,7 +178,7 @@ * frequency. */ #if !defined (EXTERNAL_SAI2_CLOCK_VALUE) - #define EXTERNAL_SAI2_CLOCK_VALUE ((uint32_t)48000U) /*!< Value of the SAI2 External clock source in Hz*/ + #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2 External clock source in Hz*/ #endif /* EXTERNAL_SAI2_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, @@ -188,8 +188,8 @@ /** * @brief This is the HAL system configuration section */ -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0x0FU) /*!< tick interrupt priority */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ #define USE_RTOS 0U #define PREFETCH_ENABLE 0U #define INSTRUCTION_CACHE_ENABLE 1U @@ -202,6 +202,50 @@ */ /* #define USE_FULL_ASSERT 1U */ +/* ################## Register callback feature configuration ############### */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/deregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32l4xx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U +#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_TSC_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U + /* ################## SPI peripheral configuration ########################## */ /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver