From 8e97f16d8ca66ac4c7354497d2afede9bf6eb4f5 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 19 Aug 2024 16:59:18 +0200 Subject: [PATCH 1/4] system(WBA) update STM32WBAxx HAL Drivers to v1.4.0 Included in STM32CubeWBA FW v1.4.1 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 25 +- .../Inc/stm32wbaxx_hal.h | 182 ++++++++++++- .../Inc/stm32wbaxx_hal_cortex.h | 70 ++--- .../Inc/stm32wbaxx_hal_gpio_ex.h | 51 +--- .../Inc/stm32wbaxx_hal_gtzc.h | 20 ++ .../Inc/stm32wbaxx_hal_i2c_ex.h | 6 +- .../Inc/stm32wbaxx_hal_rcc.h | 202 ++++++++++----- .../Inc/stm32wbaxx_hal_rcc_ex.h | 2 +- .../Inc/stm32wbaxx_hal_smbus_ex.h | 6 +- .../Inc/stm32wbaxx_hal_tim_ex.h | 2 +- .../Inc/stm32wbaxx_hal_tsc.h | 39 ++- .../Inc/stm32wbaxx_hal_uart.h | 5 +- .../Inc/stm32wbaxx_hal_usart.h | 3 +- .../Inc/stm32wbaxx_ll_bus.h | 117 +++++++-- .../Inc/stm32wbaxx_ll_cortex.h | 67 ++--- .../Inc/stm32wbaxx_ll_hsem.h | 118 +-------- .../Inc/stm32wbaxx_ll_i2c.h | 6 +- .../Inc/stm32wbaxx_ll_rcc.h | 4 + .../Inc/stm32wbaxx_ll_rng.h | 15 +- .../Inc/stm32wbaxx_ll_system.h | 160 +++++++++++- .../Inc/stm32wbaxx_ll_tim.h | 2 +- .../Inc/stm32wbaxx_ll_utils.h | 22 +- .../STM32WBAxx_HAL_Driver/Release_Notes.html | 178 ++++++++++--- .../Src/stm32wbaxx_hal.c | 244 +++++++++++++++++- .../Src/stm32wbaxx_hal_cortex.c | 39 ++- .../Src/stm32wbaxx_hal_crc.c | 2 +- .../Src/stm32wbaxx_hal_crc_ex.c | 2 - .../Src/stm32wbaxx_hal_gtzc.c | 18 +- .../Src/stm32wbaxx_hal_rcc_ex.c | 21 +- .../Src/stm32wbaxx_hal_rng.c | 14 +- .../Src/stm32wbaxx_hal_uart.c | 24 ++ .../Src/stm32wbaxx_hal_uart_ex.c | 2 +- .../Src/stm32wbaxx_hal_usart.c | 17 +- .../Src/stm32wbaxx_hal_usart_ex.c | 2 +- .../Src/stm32wbaxx_ll_exti.c | 8 - .../Src/stm32wbaxx_ll_rcc.c | 6 +- .../Src/stm32wbaxx_ll_rng.c | 2 +- .../Src/stm32wbaxx_ll_tim.c | 2 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 39 files changed, 1259 insertions(+), 448 deletions(-) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index d10f6f6f89..3e06f51918 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -806,6 +806,21 @@ extern "C" { #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 #endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ /** * @} */ @@ -1817,7 +1832,7 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) @@ -2731,6 +2746,12 @@ extern "C" { #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET @@ -3910,7 +3931,7 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h index 018bc66144..61c21bc63f 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h @@ -79,7 +79,7 @@ extern HAL_TickFreqTypeDef uwTickFreq; * @brief STM32WBAxx HAL Driver version number */ #define __STM32WBAxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WBAxx_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ +#define __STM32WBAxx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ #define __STM32WBAxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WBAxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBAxx_HAL_VERSION ((__STM32WBAxx_HAL_VERSION_MAIN << 24U)\ @@ -119,6 +119,38 @@ extern HAL_TickFreqTypeDef uwTickFreq; * @} */ +/** @defgroup SYSCFG_Compensation_Cell_Selection Compensation Cell Selection + * @{ + */ +#define SYSCFG_IO_CELL SYSCFG_CCCSR_EN1 /*!< Compensation cell for the VDD I/O power rail */ +#ifdef SYSCFG_CCCSR_EN2 +#define SYSCFG_IO2_CELL SYSCFG_CCCSR_EN2 /*!< Compensation cell for the VDDIO2 I/O power rail */ +#endif /* SYSCFG_CCCSR_EN2 */ +/** + * @} + */ + +/** @defgroup SYSCFG_Compensation_Cell_Ready_Selection Compensation Cell Ready Selection + * @{ + */ +#define SYSCFG_IO_CELL_READY SYSCFG_CCCSR_RDY1 /*!< Ready flag of compensation cell for the VDD I/O power rail */ +#ifdef SYSCFG_CCCSR_EN2 +#define SYSCFG_IO2_CELL_READY SYSCFG_CCCSR_RDY2 /*!< Ready flag of compensation cell for the VDDIO2 I/O power rail */ +#endif /* SYSCFG_CCCSR_EN2 */ +/** + * @} + */ + +/** @defgroup SYSCFG_IO_Compensation_Code_Config IO Compensation Code config + * @{ + */ +#define SYSCFG_IO_CELL_CODE 0UL /*!< Code from the cell */ +#define SYSCFG_IO_REGISTER_CODE 1UL /*!< Code from the values in the cell code register */ +/** + * @} + */ + + /** @defgroup SYSCFG_Flags_Definition Flags * @{ */ @@ -188,6 +220,83 @@ extern HAL_TickFreqTypeDef uwTickFreq; * @} */ +#ifdef SYSCFG_OTGHSPHYCR_EN +/** @defgroup SYSCFG_OTG_PHY_RefenceClockSelection OTG PHY Reference Clock Selection + * @{ + */ + +/** @brief OTG HS PHY reference clock frequency selection + */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_1 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1) /*!< 16Mhz */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_2 SYSCFG_OTGHSPHYCR_CLKSEL_3 /*!< 19.2Mhz */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_3 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 20Mhz */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_4 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 24Mhz */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_5 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_2 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 26Mhz */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_6 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 32Mhz */ +/** + * @} + */ + +/** @defgroup SYSCFG_OTG_PHY_PowerDown OTG PHY Power Down + * @{ + */ + +/** @brief OTG HS PHY Power Down config + */ +#define SYSCFG_OTG_HS_PHY_POWER_ON 0x00000000U /*!< PHY state machine, bias and OTG PHY PLL are powered down */ +#define SYSCFG_OTG_HS_PHY_POWER_DOWN SYSCFG_OTGHSPHYCR_PDCTRL /*!< PHY state machine, bias and OTG PHY PLL remain powered */ +/** + * @} + */ + +/** @defgroup SYSCFG_OTG_PHY_Enable OTG PHY Enable + * @{ + */ +#define SYSCFG_OTG_HS_PHY_UNDERRESET 0x00000000U /*!< PHY under reset */ +#define SYSCFG_OTG_HS_PHY_ENABLE SYSCFG_OTGHSPHYCR_EN /*!< PHY enabled */ +/** + * @} + */ + +/** @defgroup SYSCFG_OTG_PHYTUNER_PreemphasisCurrent OTG PHYTUNER Preemphasis Current + * @{ + */ + +/** @brief High-speed (HS) transmitter preemphasis current control + */ +#define SYSCFG_OTG_HS_PHY_PREEMP_DISABLED 0x00000000U /*!< HS transmitter preemphasis circuit disabled */ +#define SYSCFG_OTG_HS_PHY_PREEMP_1X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 /*!< HS transmitter preemphasis circuit sources 1x preemphasis current */ +#define SYSCFG_OTG_HS_PHY_PREEMP_2X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1 /*!< HS transmitter preemphasis circuit sources 2x preemphasis current */ +#define SYSCFG_OTG_HS_PHY_PREEMP_3X (SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 | SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1) /*!< HS transmitter preemphasis circuit sources 3x preemphasis current */ +/** + * @} + */ + +/** @defgroup SYSCFG_OTG_PHYTUNER_SquelchThreshold OTG PHYTUNER Squelch Threshold + * @{ + */ + +/** @brief Squelch threshold adjustment + */ +#define SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT 0x00000000U /*!< +15% (recommended value) */ +#define SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT (SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_0 | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_1) /*!< 0% (default value) */ +/** + * @} + */ + +/** @defgroup SYSCFG_OTG_PHYTUNER_DisconnectThreshold OTG PHYTUNER Disconnect Threshold + * @{ + */ + +/** @brief Disconnect threshold adjustment + */ +#define SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_1 /*!< +5.9% (recommended value) */ +#define SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_0 /*!< 0% (default value) */ +/** + * @} + */ +#endif /* SYSCFG_OTGHSPHYCR_EN */ + /** * @} */ @@ -391,11 +500,31 @@ extern HAL_TickFreqTypeDef uwTickFreq; #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_ALL) != 0x00U) && \ (((__INTERRUPT__) & ~SYSCFG_IT_FPU_ALL) == 0x00U)) +#ifdef SYSCFG_CCCSR_EN2 +#define IS_SYSCFG_COMPENSATION_CELL(__CELL__) (((__CELL__) == SYSCFG_IO_CELL) || \ + ((__CELL__) == SYSCFG_IO2_CELL)) + +#define IS_SYSCFG_COMPENSATION_CELL_READY(__CELL__) (((__CELL__) == SYSCFG_IO_CELL_READY) || \ + ((__CELL__) == SYSCFG_IO2_CELL_READY)) +#else +#define IS_SYSCFG_COMPENSATION_CELL(__CELL__) (((__CELL__) == SYSCFG_IO_CELL)) + +#define IS_SYSCFG_COMPENSATION_CELL_READY(__CELL__) (((__CELL__) == SYSCFG_IO_CELL_READY)) +#endif /* SYSCFG_CCCSR_EN2 */ + +#define IS_SYSCFG_COMPENSATION_CELL_CODE(__VALUE__) (((__VALUE__) == SYSCFG_IO_CELL_CODE) || \ + ((__VALUE__) == SYSCFG_IO_REGISTER_CODE)) + +#define IS_SYSCFG_COMPENSATION_CELL_PMOS_VALUE(__VALUE__) (((__VALUE__) < 16U)) + +#define IS_SYSCFG_COMPENSATION_CELL_NMOS_VALUE(__VALUE__) (((__VALUE__) < 16U)) + #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) + #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_ALL) != 0x00U) && \ (((__PIN__) & ~SYSCFG_FASTMODEPLUS_ALL) == 0x00U)) @@ -418,6 +547,31 @@ extern HAL_TickFreqTypeDef uwTickFreq; #define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_LOCK_ALL) != 0x00U) && \ (((__ITEM__) & ~SYSCFG_LOCK_ALL) == 0x00U)) +#ifdef SYSCFG_OTGHSPHYCR_EN +#define IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_1) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_2) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_3) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_4) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_5) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_6)) + +#define IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_DOWN) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_ON)) + +#define IS_SYSCFG_OTGPHY_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_UNDERRESET) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_ENABLE)) + +#define IS_SYSCFG_OTGPHY_DISCONNECT(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT)) + +#define IS_SYSCFG_OTGPHY_SQUELCH(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT)) + +#define IS_SYSCFG_OTGPHY_PREEMPHASIS(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_DISABLED) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_1X) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_2X) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_3X)) +#endif /* SYSCFG_OTGHSPHYCR_EN */ /** * @} @@ -487,10 +641,28 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void); */ /* SYSCFG Control functions ****************************************************/ -void HAL_SYSCFG_SRAM2Erase(void); void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); - +void HAL_SYSCFG_EnableIOAnalogSwitchVdd(void); +void HAL_SYSCFG_DisableIOAnalogSwitchVdd(void); + + +#ifdef SYSCFG_OTGHSPHYCR_EN +void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClockSelection); +void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig); +void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig); +void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold); +void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold); +void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent); +#endif /* SYSCFG_OTGHSPHYCR_EN */ + +void HAL_SYSCFG_EnableCompensationCell(uint32_t Selection); +void HAL_SYSCFG_DisableCompensationCell(uint32_t Selection); +uint32_t HAL_SYSCFG_GetCompensationCellReadyStatus(uint32_t Selection); +void HAL_SYSCFG_ConfigCompensationCell(uint32_t Selection, uint32_t Code, uint32_t NmosValue, + uint32_t PmosValue); +HAL_StatusTypeDef HAL_SYSCFG_GetCompensationCell(uint32_t Selection, uint32_t *pCode, uint32_t *pNmosValue, + uint32_t *pPmosValue); /** * @} */ @@ -500,7 +672,7 @@ void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); */ /* SYSCFG Lock functions ********************************************/ -void HAL_SYSCFG_Lock(uint32_t Item); +void HAL_SYSCFG_Lock(uint32_t Item); HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem); /** @@ -514,7 +686,7 @@ HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem); #if defined (SYSCFG_SECCFGR_SYSCFGSEC) /* SYSCFG Attributes functions ********************************************/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes); +void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes); #endif /* __ARM_FEATURE_CMSE */ HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); #endif /* SYSCFG_SECCFGR_SYSCFGSEC */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cortex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cortex.h index 8d0f9ac345..2c6ff05071 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cortex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cortex.h @@ -121,10 +121,10 @@ typedef struct /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control * @{ */ -#define MPU_HFNMI_PRIVDEF_NONE 0U -#define MPU_HARDFAULT_NMI 2U -#define MPU_PRIVILEGED_DEFAULT 4U -#define MPU_HFNMI_PRIVDEF 6U +#define MPU_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ /** * @} */ @@ -132,8 +132,8 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable * @{ */ -#define MPU_REGION_ENABLE 1U -#define MPU_REGION_DISABLE 0U +#define MPU_REGION_ENABLE 1U /*!< Enable region */ +#define MPU_REGION_DISABLE 0U /*!< Disable region */ /** * @} */ @@ -141,8 +141,8 @@ typedef struct /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access * @{ */ -#define MPU_INSTRUCTION_ACCESS_ENABLE 0U -#define MPU_INSTRUCTION_ACCESS_DISABLE 1U +#define MPU_INSTRUCTION_ACCESS_ENABLE 0U /*!< Execute attribute */ +#define MPU_INSTRUCTION_ACCESS_DISABLE 1U /*!< Execute never attribute */ /** * @} */ @@ -150,9 +150,9 @@ typedef struct /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable * @{ */ -#define MPU_ACCESS_NOT_SHAREABLE 0U -#define MPU_ACCESS_OUTER_SHAREABLE 2U -#define MPU_ACCESS_INNER_SHAREABLE 3U +#define MPU_ACCESS_NOT_SHAREABLE 0U /*!< Not shareable attribute */ +#define MPU_ACCESS_OUTER_SHAREABLE 2U /*!< Outer shareable attribute */ +#define MPU_ACCESS_INNER_SHAREABLE 3U /*!< Inner shareable attribute */ /** * @} */ @@ -160,10 +160,10 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ -#define MPU_REGION_PRIV_RW 0U -#define MPU_REGION_ALL_RW 1U -#define MPU_REGION_PRIV_RO 2U -#define MPU_REGION_ALL_RO 3U +#define MPU_REGION_PRIV_RW 0U /*!< Read/write privileged-only attribute */ +#define MPU_REGION_ALL_RW 1U /*!< Read/write privileged/unprivileged attribute */ +#define MPU_REGION_PRIV_RO 2U /*!< Read-only privileged-only attribute */ +#define MPU_REGION_ALL_RO 3U /*!< Read-only privileged/unprivileged attribute */ /** * @} */ @@ -201,22 +201,30 @@ typedef struct /** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes * @{ */ -#define MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ -#define MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ -#define MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ -#define MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ - -#define MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ -#define MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ -#define MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ - -#define MPU_TRANSIENT 0x0U /* Normal memory, transient. */ -#define MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ - -#define MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ -#define MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ -#define MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ -#define MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ +/* Device memory attributes */ +#define MPU_DEVICE_nGnRnE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */ +#define MPU_DEVICE_nGnRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */ +#define MPU_DEVICE_nGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */ +#define MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */ + +/* Normal memory attributes */ +/* To set with INNER_OUTER() macro for both inner/outer cache attributes */ + +/* Non-cacheable memory attribute */ +#define MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable */ + +/* Cacheable memory attributes: combination of cache write policy, transient and allocation */ +/* - cache write policy */ +#define MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through */ +#define MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back */ +/* - transient mode attribute */ +#define MPU_TRANSIENT 0x0U /*!< Normal memory, transient */ +#define MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient */ +/* - allocation attribute */ +#define MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate */ +#define MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate */ +#define MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate */ +#define MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate */ /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio_ex.h index 25bda94e3a..cabce15d41 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio_ex.h @@ -44,9 +44,7 @@ extern "C" { * @{ */ -/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection - * @{ - */ + #if defined(STM32WBA54xx) || defined(STM32WBA55xx) /** @@ -117,18 +115,7 @@ extern "C" { /** * @brief AF 11 selection */ -#define GPIO_AF11_RF_ANTSW0 ((uint8_t)0x0B) /*!< RF_ANTSW0 Alternate Function mapping */ -#define GPIO_AF11_RF_ANTSW1 ((uint8_t)0x0B) /*!< RF_ANTSW1 Alternate Function mapping */ -#define GPIO_AF11_RF_ANTSW2 ((uint8_t)0x0B) /*!< RF_ANTSW2 Alternate Function mapping */ -#define GPIO_AF11_RF_IO1 ((uint8_t)0x0B) /*!< RF_IO1 Alternate Function mapping */ -#define GPIO_AF11_RF_IO2 ((uint8_t)0x0B) /*!< RF_IO2 Alternate Function mapping */ -#define GPIO_AF11_RF_IO3 ((uint8_t)0x0B) /*!< RF_IO3 Alternate Function mapping */ -#define GPIO_AF11_RF_IO4 ((uint8_t)0x0B) /*!< RF_IO4 Alternate Function mapping */ -#define GPIO_AF11_RF_IO5 ((uint8_t)0x0B) /*!< RF_IO5 Alternate Function mapping */ -#define GPIO_AF11_RF_IO6 ((uint8_t)0x0B) /*!< RF_IO6 Alternate Function mapping */ -#define GPIO_AF11_RF_IO7 ((uint8_t)0x0B) /*!< RF_IO7 Alternate Function mapping */ -#define GPIO_AF11_RF_IO8 ((uint8_t)0x0B) /*!< RF_IO8 Alternate Function mapping */ -#define GPIO_AF11_RF_IO9 ((uint8_t)0x0B) /*!< RF_IO9 Alternate Function mapping */ +#define GPIO_AF11_RF ((uint8_t)0x0B) /*!< RF_ANTSW0 Alternate Function mapping */ /** * @brief AF 12 selection @@ -228,18 +215,7 @@ extern "C" { /** * @brief AF 11 selection */ -#define GPIO_AF11_RF_ANTSW0 ((uint8_t)0x0B) /*!< RF_ANTSW0 Alternate Function mapping */ -#define GPIO_AF11_RF_ANTSW1 ((uint8_t)0x0B) /*!< RF_ANTSW1 Alternate Function mapping */ -#define GPIO_AF11_RF_ANTSW2 ((uint8_t)0x0B) /*!< RF_ANTSW2 Alternate Function mapping */ -#define GPIO_AF11_RF_IO1 ((uint8_t)0x0B) /*!< RF_IO1 Alternate Function mapping */ -#define GPIO_AF11_RF_IO2 ((uint8_t)0x0B) /*!< RF_IO2 Alternate Function mapping */ -#define GPIO_AF11_RF_IO3 ((uint8_t)0x0B) /*!< RF_IO3 Alternate Function mapping */ -#define GPIO_AF11_RF_IO4 ((uint8_t)0x0B) /*!< RF_IO4 Alternate Function mapping */ -#define GPIO_AF11_RF_IO5 ((uint8_t)0x0B) /*!< RF_IO5 Alternate Function mapping */ -#define GPIO_AF11_RF_IO6 ((uint8_t)0x0B) /*!< RF_IO6 Alternate Function mapping */ -#define GPIO_AF11_RF_IO7 ((uint8_t)0x0B) /*!< RF_IO7 Alternate Function mapping */ -#define GPIO_AF11_RF_IO8 ((uint8_t)0x0B) /*!< RF_IO8 Alternate Function mapping */ -#define GPIO_AF11_RF_IO9 ((uint8_t)0x0B) /*!< RF_IO9 Alternate Function mapping */ +#define GPIO_AF11_RF ((uint8_t)0x0B) /*!< RF_ANTSW0 Alternate Function mapping */ /** * @brief AF 13 selection @@ -316,18 +292,7 @@ extern "C" { /** * @brief AF 11 selection */ -#define GPIO_AF11_RF_ANTSW0 ((uint8_t)0x0B) /*!< RF_ANTSW0 Alternate Function mapping */ -#define GPIO_AF11_RF_ANTSW1 ((uint8_t)0x0B) /*!< RF_ANTSW1 Alternate Function mapping */ -#define GPIO_AF11_RF_ANTSW2 ((uint8_t)0x0B) /*!< RF_ANTSW2 Alternate Function mapping */ -#define GPIO_AF11_RF_IO1 ((uint8_t)0x0B) /*!< RF_IO1 Alternate Function mapping */ -#define GPIO_AF11_RF_IO2 ((uint8_t)0x0B) /*!< RF_IO2 Alternate Function mapping */ -#define GPIO_AF11_RF_IO3 ((uint8_t)0x0B) /*!< RF_IO3 Alternate Function mapping */ -#define GPIO_AF11_RF_IO4 ((uint8_t)0x0B) /*!< RF_IO4 Alternate Function mapping */ -#define GPIO_AF11_RF_IO5 ((uint8_t)0x0B) /*!< RF_IO5 Alternate Function mapping */ -#define GPIO_AF11_RF_IO6 ((uint8_t)0x0B) /*!< RF_IO6 Alternate Function mapping */ -#define GPIO_AF11_RF_IO7 ((uint8_t)0x0B) /*!< RF_IO7 Alternate Function mapping */ -#define GPIO_AF11_RF_IO8 ((uint8_t)0x0B) /*!< RF_IO8 Alternate Function mapping */ -#define GPIO_AF11_RF_IO9 ((uint8_t)0x0B) /*!< RF_IO9 Alternate Function mapping */ +#define GPIO_AF11_RF ((uint8_t)0x0B) /*!< RF_ANTSW0 Alternate Function mapping */ /** * @brief AF 14 selection @@ -352,10 +317,6 @@ extern "C" { #endif /* defined(STM32WBA50xx) */ -/** - * @} - */ - /** * @} */ @@ -378,6 +339,10 @@ extern "C" { * @} */ +/** + * @} + */ + /* Exported functions --------------------------------------------------------*/ /** * @} diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gtzc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gtzc.h index 0d756f4de5..60d9584a94 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gtzc.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gtzc.h @@ -152,14 +152,22 @@ typedef struct */ /* GTZC */ #define GTZC_PERIPH_TIM2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM2_Pos) +#if defined (TIM3) #define GTZC_PERIPH_TIM3 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM3_Pos) +#endif /* TIM3 */ +#if defined (WWDG) #define GTZC_PERIPH_WWDG (GTZC_PERIPH_REG1 | GTZC_CFGR1_WWDG_Pos) +#endif /* WWDG */ #define GTZC_PERIPH_IWDG (GTZC_PERIPH_REG1 | GTZC_CFGR1_IWDG_Pos) +#if defined (USART2) #define GTZC_PERIPH_USART2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_USART2_Pos) +#endif /* USART2 */ #define GTZC_PERIPH_I2C1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_I2C1_Pos) #define GTZC_PERIPH_LPTIM2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_LPTIM2_Pos) +#if defined (TIM1) #define GTZC_PERIPH_TIM1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM1_Pos) +#endif /* TIM1 */ #define GTZC_PERIPH_SPI1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos) #define GTZC_PERIPH_USART1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_USART1_Pos) #define GTZC_PERIPH_TIM16 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM16_Pos) @@ -167,7 +175,9 @@ typedef struct #if defined (SAI1) #define GTZC_PERIPH_SAI1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SAI1_Pos) #endif /* SAI1 */ +#if defined (SPI3) #define GTZC_PERIPH_SPI3 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SPI3_Pos) +#endif /* SPI3 */ #define GTZC_PERIPH_LPUART1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_LPUART1_Pos) #define GTZC_PERIPH_I2C3 (GTZC_PERIPH_REG2 | GTZC_CFGR2_I2C3_Pos) #define GTZC_PERIPH_LPTIM1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_LPTIM1_Pos) @@ -177,13 +187,19 @@ typedef struct #define GTZC_PERIPH_ADC4 (GTZC_PERIPH_REG2 | GTZC_CFGR2_ADC4_Pos) #define GTZC_PERIPH_CRC (GTZC_PERIPH_REG3 | GTZC_CFGR3_CRC_Pos) +#if defined (TSC) #define GTZC_PERIPH_TSC (GTZC_PERIPH_REG3 | GTZC_CFGR3_TSC_Pos) +#endif /* TSC */ #define GTZC_PERIPH_ICACHE_REG (GTZC_PERIPH_REG3 | GTZC_CFGR3_ICACHE_REG_Pos) #define GTZC_PERIPH_AES (GTZC_PERIPH_REG3 | GTZC_CFGR3_AES_Pos) #define GTZC_PERIPH_HASH (GTZC_PERIPH_REG3 | GTZC_CFGR3_HASH_Pos) #define GTZC_PERIPH_RNG (GTZC_PERIPH_REG3 | GTZC_CFGR3_RNG_Pos) +#if defined (SAES) #define GTZC_PERIPH_SAES (GTZC_PERIPH_REG3 | GTZC_CFGR3_SAES_Pos) +#endif /* SAES */ +#if defined (HSEM) #define GTZC_PERIPH_HSEM (GTZC_PERIPH_REG3 | GTZC_CFGR3_HSEM_Pos) +#endif /* HSEM */ #define GTZC_PERIPH_PKA (GTZC_PERIPH_REG3 | GTZC_CFGR3_PKA_Pos) #define GTZC_PERIPH_RAMCFG (GTZC_PERIPH_REG3 | GTZC_CFGR3_RAMCFG_Pos) #define GTZC_PERIPH_RADIO (GTZC_PERIPH_REG3 | GTZC_CFGR3_RADIO_Pos) @@ -191,7 +207,9 @@ typedef struct #define GTZC_PERIPH_PTACONV (GTZC_PERIPH_REG3 | GTZC_CFGR3_PTACONV_Pos) #endif /* PTACONV */ +#if defined (GPDMA1) #define GTZC_PERIPH_GPDMA1 (GTZC_PERIPH_REG4 | GTZC_CFGR4_GPDMA1_Pos) +#endif /* GPDMA1 */ #define GTZC_PERIPH_FLASH (GTZC_PERIPH_REG4 | GTZC_CFGR4_FLASH_Pos) #define GTZC_PERIPH_FLASH_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_FLASH_REG_Pos) #define GTZC_PERIPH_SYSCFG (GTZC_PERIPH_REG4 | GTZC_CFGR4_SYSCFG_Pos) @@ -206,8 +224,10 @@ typedef struct #define GTZC_PERIPH_MPCBB1_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB1_REG_Pos) #define GTZC_PERIPH_SRAM2 (GTZC_PERIPH_REG4 | GTZC_CFGR4_SRAM2_Pos) #define GTZC_PERIPH_MPCBB2_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB2_REG_Pos) +#if defined (SRAM6_BASE) #define GTZC_PERIPH_SRAM6 (GTZC_PERIPH_REG4 | GTZC_CFGR4_SRAM6_Pos) #define GTZC_PERIPH_MPCBB6_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB6_REG_Pos) +#endif /* SRAM6 */ #define GTZC_PERIPH_ALL (0x00000020U) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c_ex.h index 4309ee25ac..cc84e89e04 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c_ex.h @@ -100,9 +100,9 @@ typedef struct * @{ */ #if defined(I2C1) -#define I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2 */ -#endif /* I2C1, I2C2 */ -#define I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3, I2C4 */ +#define I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1 */ +#endif /* I2C1 */ +#define I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ #if defined(I2C_TRIG_GRP1) #define I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x00000000U)) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc.h index 8ccc312fc0..79e9380fc8 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc.h @@ -477,7 +477,9 @@ typedef struct #define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ #define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ #define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ +#if defined(WWDG) #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ +#endif /* WWDG */ #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ /** * @} @@ -501,11 +503,18 @@ typedef struct #define RCC_RESET_FLAG_PWR RCC_CSR_BORRSTF /*!< BOR or POR/PDR reset flag */ #define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */ #define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#if defined(WWDG) #define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#endif /* WWDG */ #define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */ +#if defined(WWDG) #define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \ RCC_RESET_FLAG_LPWR) +#else +#define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ + RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_LPWR) +#endif /* WWDG */ /** * @} */ @@ -534,7 +543,7 @@ typedef struct */ #define RCC_NSEC_PRIV 0x00000001U /*!< Non-secure Privilege attribute item */ #define RCC_NSEC_NPRIV 0x00000002U /*!< Non-secure Non-privilege attribute item */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define RCC_SEC_PRIV 0x00000010U /*!< Secure Privilege attribute item */ #define RCC_SEC_NPRIV 0x00000020U /*!< Secure Non-privilege attribute item */ #endif @@ -555,6 +564,8 @@ typedef struct * using it. * @{ */ + +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ @@ -562,6 +573,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -579,6 +591,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(TSC) #define __HAL_RCC_TSC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ @@ -586,6 +599,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ UNUSED(tmpreg); \ } while(0) +#endif /* TSC */ #define __HAL_RCC_RAMCFG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -613,14 +627,16 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) +#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) #define __HAL_RCC_RAMCFG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) #if defined(GTZC_TZSC) #define __HAL_RCC_GTZC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) -#endif +#endif /* GTZC_TZSC */ #define __HAL_RCC_SRAM1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) /** @@ -703,6 +719,7 @@ typedef struct } while(0) #endif /* SAES */ +#if defined(HSEM) #define __HAL_RCC_HSEM_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN); \ @@ -710,6 +727,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN); \ UNUSED(tmpreg); \ } while(0) +#endif /* HSEM */ #define __HAL_RCC_PKA_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -719,6 +737,8 @@ typedef struct UNUSED(tmpreg); \ } while(0) + + #define __HAL_RCC_SRAM2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN); \ @@ -736,8 +756,10 @@ typedef struct #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) #if defined(SAES) #define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) -#endif +#endif /* SAES */ +#if defined(HSEM) #define __HAL_RCC_HSEM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN) +#endif /* HSEM */ #define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) #define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) /** @@ -802,7 +824,7 @@ typedef struct #if defined(PTACONV) #define __HAL_RCC_PTACONV_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_PTACONVEN) -#endif +#endif /* PTACONV */ /** * @} */ @@ -834,6 +856,7 @@ typedef struct #endif /* TIM3 */ +#if defined(WWDG) #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ @@ -841,6 +864,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ UNUSED(tmpreg); \ } while(0) +#endif /* WWDG */ #if defined(USART2) @@ -879,16 +903,16 @@ typedef struct #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) #if defined(TIM3) #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) -#endif +#endif /* TIM3 */ #if defined(USART2) #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) -#endif +#endif /* USART2 */ #if defined(I2C1) #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) -#endif +#endif /* I2C1 */ #if defined(LPTIM2) #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) -#endif +#endif /* LPTIM2 */ /** * @} */ @@ -900,6 +924,7 @@ typedef struct * using it. * @{ */ +#if defined(TIM1) #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ @@ -907,6 +932,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* TIM1 */ #if defined(SPI1) #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ @@ -954,18 +980,21 @@ typedef struct } while(0) #endif /* SAI1 */ + +#if defined(TIM1) #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) +#endif /* TIM1 */ #if defined(SPI1) #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) -#endif +#endif /* SPI1 */ #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) #if defined(TIM17) #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) -#endif +#endif /* TIM17 */ #if defined(SAI1) #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) -#endif +#endif /* SAI1 */ /** * @} */ @@ -1049,14 +1078,16 @@ typedef struct * @brief Check whether the AHB1 peripheral clock is enabled or not. * @{ */ +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) != 0U) +#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U) #define __HAL_RCC_RAMCFG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) != 0U) #if defined(GTZC_TZSC) #define __HAL_RCC_GTZC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) != 0U) -#endif +#endif /* GTZC_TZSC */ #define __HAL_RCC_SRAM1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) != 0U) /** * @} @@ -1075,8 +1106,10 @@ typedef struct #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U) #if defined(SAES) #define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) != 0U) -#endif +#endif /* SAES */ +#if defined(HSEM) #define __HAL_RCC_HSEM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN) != 0U) +#endif /* HSEM */ #define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) != 0U) #define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) != 0U) /** @@ -1112,17 +1145,19 @@ typedef struct #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) #if defined(TIM3) #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) -#endif +#endif /* TIM3 */ +#if defined(WWDG) #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) +#endif /* WWDG */ #if defined(USART2) #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) -#endif +#endif /* USART2 */ #if defined(I2C1) #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U) -#endif +#endif /* I2C1 */ #if defined(LPTIM2) #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U) -#endif +#endif /* LPTIM2 */ /** * @} */ @@ -1131,18 +1166,20 @@ typedef struct * @brief Check whether the APB2 peripheral clock is enabled or not. * @{ */ + #if defined(TIM1) #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) +#endif /* TIM1 */ #if defined(SPI1) #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) -#endif +#endif /* SPI1 */ #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) #if defined(TIM17) #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) -#endif +#endif /* TIM17 */ #if defined(SAI1) #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) -#endif +#endif /* SAI1 */ /** * @} */ @@ -1167,12 +1204,16 @@ typedef struct * @{ */ #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU) +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) +#endif /* GPDMA1 */ #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) +#endif /* GPDMA1 */ #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) /** @@ -1193,10 +1234,11 @@ typedef struct #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) #if defined(SAES) #define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) -#endif +#endif /* SAES */ +#if defined(HSEM) #define __HAL_RCC_HSEM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HSEMRST) +#endif /* HSEM */ #define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) - #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) @@ -1207,8 +1249,10 @@ typedef struct #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) #if defined(SAES) #define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) -#endif +#endif /* SAES */ +#if defined(HSEM) #define __HAL_RCC_HSEM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HSEMRST) +#endif /* HSEM */ #define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) /** * @} @@ -1235,13 +1279,13 @@ typedef struct #define __HAL_RCC_RADIO_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_RADIORST) #if defined(PTACONV) #define __HAL_RCC_PTACONV_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_PTACONVRST) -#endif +#endif /* PTACONV */ #define __HAL_RCC_AHB5_RELEASE_RESET() WRITE_REG(RCC->AHB5RSTR, 0x00000000U) #define __HAL_RCC_RADIO_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_RADIORST) #if defined(PTACONV) #define __HAL_RCC_PTACONV_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_PTACONVRST) -#endif +#endif /* PTACONV */ /** * @} */ @@ -1257,16 +1301,16 @@ typedef struct #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) #if defined(TIM3) #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) -#endif +#endif /* TIM3 */ #if defined(USART2) #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) -#endif +#endif /* USART2 */ #if defined(I2C1) #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) -#endif +#endif /* I2C1 */ #if defined(LPTIM2) #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) -#endif +#endif /* LPTIM2 */ #define __HAL_RCC_APB1_RELEASE_RESET() do { \ WRITE_REG(RCC->APB1RSTR1, 0x00000000U); \ @@ -1275,16 +1319,16 @@ typedef struct #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) #if defined(TIM3) #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) -#endif +#endif /* TIM3 */ #if defined(USART2) #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) -#endif +#endif /* USART2 */ #if defined(I2C1) #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) -#endif +#endif /* I2C1 */ #if defined(LPTIM2) #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) -#endif +#endif /* LPTIM2 */ /** * @} */ @@ -1294,32 +1338,34 @@ typedef struct * @{ */ #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU) +#if defined(TIM1) #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) +#endif /* TIM1 */ #if defined(SPI1) #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) -#endif +#endif /* SPI1 */ #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) #if defined(TIM17) #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) -#endif +#endif /* TIM17 */ #if defined(SAI1) #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) -#endif +#endif /* SAI1 */ #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) #if defined(SPI1) #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) -#endif +#endif /* SPI1 */ #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) #if defined(TIM17) #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) -#endif +#endif /* TIM17 */ #if defined(SAI1) #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) -#endif +#endif /* SAI1 */ /** * @} */ @@ -1356,25 +1402,29 @@ typedef struct * is enabled only when a peripheral requests AHB clock. * @{ */ +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) +#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) #define __HAL_RCC_RAMCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) #if defined(GTZC_TZSC) #define __HAL_RCC_GTZC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) -#endif +#endif /* GTZC_TZSC */ #define __HAL_RCC_ICACHE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) +#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) #define __HAL_RCC_RAMCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) #if defined(GTZC_TZSC) #define __HAL_RCC_GTZC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) -#endif +#endif /* GTZC_TZSC */ #define __HAL_RCC_ICACHE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) /** @@ -1399,7 +1449,7 @@ typedef struct #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) #if defined(SAES) #define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SAESSMEN) -#endif +#endif /* SAES */ #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) @@ -1412,7 +1462,7 @@ typedef struct #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) #if defined(SAES) #define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SAESSMEN) -#endif +#endif /* SAES */ #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) /** @@ -1452,7 +1502,7 @@ typedef struct #if defined(PTACONV) #define __HAL_RCC_PTACONV_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5SMENR, RCC_AHB5SMENR_PTACONVSMEN) #define __HAL_RCC_PTACONV_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5SMENR, RCC_AHB5SMENR_PTACONVSMEN) -#endif +#endif /* PTACONV */ /** * @} */ @@ -1469,32 +1519,36 @@ typedef struct #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) #if defined(TIM3) #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) -#endif +#endif /* TIM3 */ +#if defined(WWDG) #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) +#endif /* WWDG */ #if defined(USART2) #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) -#endif +#endif /* USART2 */ #if defined(I2C1) #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) -#endif +#endif /* I2C1 */ #if defined(LPTIM2) #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) -#endif +#endif /* LPTIM2 */ #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) #if defined(TIM3) #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) -#endif +#endif /* TIM3 */ +#if defined(WWDG) #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) +#endif /* WWDG */ #if defined(USART2) #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) -#endif +#endif /* USART2 */ #if defined(I2C1) #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) -#endif +#endif /* I2C1 */ #if defined(LPTIM2) #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) -#endif +#endif /* LPTIM2 */ /** * @} */ @@ -1508,31 +1562,33 @@ typedef struct * is enabled only when a peripheral requests APB clock. * @{ */ +#if defined(TIM1) #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) +#endif /* TIM1 */ #if defined(SPI1) #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) -#endif +#endif /* SPI1 */ #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) #if defined(TIM17) #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) -#endif +#endif /* TIM17 */ #if defined(SAI1) #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) -#endif +#endif /* SAI1 */ #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) #if defined(SPI1) #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) -#endif +#endif /* SPI1 */ #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) #if defined(TIM17) #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) -#endif +#endif /* TIM17 */ #if defined(SAI1) #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) -#endif +#endif /* SAI1 */ /** * @} */ @@ -1569,14 +1625,16 @@ typedef struct * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) is enabled or not. * @{ */ +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) != 0U) +#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U) #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U) #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != 0U) #define __HAL_RCC_RAMCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) != 0U) #if defined(GTZC_TZSC) #define __HAL_RCC_GTZC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) != 0U) -#endif +#endif /* GTZC_TZSC */ #define __HAL_RCC_ICACHE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) != 0U) #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U) /** @@ -1596,7 +1654,7 @@ typedef struct #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U) #if defined(SAES) #define __HAL_RCC_SAES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SAESSMEN) != 0U) -#endif +#endif /* SAES */ #define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) != 0U) #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U) /** @@ -1620,7 +1678,7 @@ typedef struct #define __HAL_RCC_RADIO_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5SMENR, RCC_AHB5SMENR_RADIOSMEN) != 0U) #if defined(PTACONV) #define __HAL_RCC_PTACONV_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5SMENR, RCC_AHB5SMENR_PTACONVSMEN) != 0U) -#endif +#endif /* PTACONV */ /** * @} */ @@ -1632,17 +1690,19 @@ typedef struct #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U) #if defined(TIM3) #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U) -#endif +#endif /* TIM3 */ +#if defined(WWDG) #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U) +#endif /* WWDG */ #if defined(USART2) #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U) -#endif +#endif /* USART2 */ #if defined(I2C1) #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U) -#endif +#endif /* I2C1 */ #if defined(LPTIM2) #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != 0U) -#endif +#endif /* LPTIM2 */ /** * @} */ @@ -1651,18 +1711,20 @@ typedef struct * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. * @{ */ +#if defined(TIM1) #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U) +#endif /* TIM1 */ #if defined(SPI1) #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U) -#endif +#endif /* SPI1 */ #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U) #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U) #if defined(TIM17) #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U) -#endif +#endif /* TIM17 */ #if defined(SAI1) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U) -#endif +#endif /* SAI1 */ /** * @} */ @@ -2231,7 +2293,7 @@ typedef struct * @arg @ref RCC_FLAG_PINRST Pin reset * @arg @ref RCC_FLAG_SFTRST Software reset * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset - * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset + * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset(*) * @arg @ref RCC_FLAG_LPWRRST Low Power reset * (*) Feature not available on all devices of the family * @retval The new state of __FLAG__ (TRUE or FALSE). @@ -2370,7 +2432,7 @@ typedef struct #define IS_RCC_ITEM_ATTRIBUTES(__ITEM__) (((__ITEM__) != 0x00U) && (((__ITEM__) & ~RCC_ALL) == 0x00U)) -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define IS_RCC_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == RCC_SEC_PRIV) || \ ((__ATTRIBUTES__) == RCC_SEC_NPRIV) || \ ((__ATTRIBUTES__) == RCC_NSEC_PRIV) || \ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc_ex.h index 1bcbe2ff07..2742a0feb6 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc_ex.h @@ -844,7 +844,7 @@ uint32_t HAL_RCCEx_GetAudioSyncCaptureValue(void); * @{ */ /* Define used for IS_RCC_* macros below */ -#if defined (STM32WBA54xx) || defined (STM32WBA55xx) +#if defined (STM32WBA54xx) || defined (STM32WBA55xx) #if !defined (STM32WBAXX_SI_CUT1_0) #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_I2C1 | \ RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SYSTICK | \ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus_ex.h index 3447d277b6..bf8ff2b2cb 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus_ex.h @@ -92,9 +92,9 @@ typedef struct * @{ */ #if defined(I2C1) -#define SMBUS_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2 */ -#endif /* I2C1, I2C2 */ -#define SMBUS_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3, I2C4 */ +#define SMBUS_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1 */ +#endif /* I2C1 */ +#define SMBUS_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ #if defined(SMBUS_TRIG_GRP1) #define SMBUS_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x00000000U)) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim_ex.h index 2a13e15577..d4f95b7c90 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim_ex.h @@ -529,7 +529,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR8)))) #endif /* TIM3 */ -#if defined(TIM3) +#if defined(TIM3) #define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_ITR1) || \ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tsc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tsc.h index 256362df27..39eacb4d98 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tsc.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tsc.h @@ -139,6 +139,9 @@ enum #if defined(TSC_IOCCR_G7_IO1) TSC_GROUP7_IDX, #endif /* TSC_IOCCR_G7_IO1 */ +#if defined(TSC_IOCCR_G8_IO1) + TSC_GROUP8_IDX, +#endif /* TSC_IOCCR_G8_IO1 */ TSC_NB_OF_GROUPS }; @@ -360,6 +363,9 @@ when the selected signal is detected on the SYNC input pin) */ #if defined(TSC_IOCCR_G7_IO1) #define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX) #endif /* TSC_IOCCR_G7_IO1 */ +#if defined(TSC_IOCCR_G8_IO1) +#define TSC_GROUP8 (0x1UL << TSC_GROUP8_IDX) +#endif /* TSC_IOCCR_G8_IO1 */ #define TSC_GROUPX_NOT_SUPPORTED 0xFF000000UL /*!< TSC GroupX not supported */ @@ -390,6 +396,13 @@ when the selected signal is detected on the SYNC input pin) */ #define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */ #define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */ +#if defined(TSC_IOCCR_G6_IO3) +#define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */ +#define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */ +#else +#define TSC_GROUP6_IO3 TSC_GROUPX_NOT_SUPPORTED /*!< TSC Group6 IO3 not supported */ +#define TSC_GROUP6_IO4 TSC_GROUPX_NOT_SUPPORTED /*!< TSC Group6 IO4 not supported */ +#endif /* TSC_IOCCR_G6_IO3 */ #if defined(TSC_IOCCR_G7_IO1) #define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */ @@ -403,6 +416,19 @@ when the selected signal is detected on the SYNC input pin) */ #define TSC_GROUP7_IO3 TSC_GROUP7_IO1 /*!< TSC Group7 IO3 not supported */ #define TSC_GROUP7_IO4 TSC_GROUP7_IO1 /*!< TSC Group7 IO4 not supported */ #endif /* TSC_IOCCR_G7_IO1 */ +#if defined(TSC_IOCCR_G8_IO1) + +#define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1 /*!< TSC Group8 IO1 */ +#define TSC_GROUP8_IO2 TSC_IOCCR_G8_IO2 /*!< TSC Group8 IO2 */ +#define TSC_GROUP8_IO3 TSC_IOCCR_G8_IO3 /*!< TSC Group8 IO3 */ +#define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4 /*!< TSC Group8 IO4 */ +#else + +#define TSC_GROUP8_IO1 (uint32_t)(0x00000080UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group8 IO1 not supported */ +#define TSC_GROUP8_IO2 TSC_GROUP8_IO1 /*!< TSC Group8 IO2 not supported */ +#define TSC_GROUP8_IO3 TSC_GROUP8_IO1 /*!< TSC Group8 IO3 not supported */ +#define TSC_GROUP8_IO4 TSC_GROUP8_IO1 /*!< TSC Group8 IO4 not supported */ +#endif /* TSC_IOCCR_G8_IO1 */ /** * @} */ @@ -711,7 +737,9 @@ when the selected signal is detected on the SYNC input pin) */ #define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL)\ || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS))) -#define IS_TSC_GROUP(__VALUE__) (((__VALUE__) == 0UL) ||\ + +#define IS_TSC_GROUP(__VALUE__) ((((__VALUE__) & TSC_GROUPX_NOT_SUPPORTED) != TSC_GROUPX_NOT_SUPPORTED) && \ + (((__VALUE__) == 0UL) ||\ (((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\ (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\ (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\ @@ -734,10 +762,17 @@ when the selected signal is detected on the SYNC input pin) */ (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\ (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\ (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\ + (((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\ + (((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\ (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\ (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\ (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\ - (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4)) + (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4) ||\ + (((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\ + (((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\ + (((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\ + (((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4))) + /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart.h index ccfcceb943..672a232fd1 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart.h @@ -1231,7 +1231,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) /** @defgroup UART_Private_Macros UART Private Macros * @{ */ -/** @brief Get UART clok division factor from clock prescaler value. +/** @brief Get UART clock division factor from clock prescaler value. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval UART clock division factor */ @@ -1246,8 +1246,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart.h index 51708c5850..7613822ef7 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart.h @@ -708,8 +708,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ USART clock. diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_bus.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_bus.h index 50ffd2534f..7da948247d 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_bus.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_bus.h @@ -70,7 +70,9 @@ extern "C" { * @{ */ #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(GPDMA1) #define LL_AHB1_GRP1_PERIPH_GPDMA1 RCC_AHB1ENR_GPDMA1EN +#endif #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN @@ -134,7 +136,9 @@ extern "C" { #if defined(TIM3) #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN #endif /* TIM3 */ +#if defined(WWDG) #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN +#endif /* WWDG */ #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN #if defined(I2C1) #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN @@ -159,7 +163,9 @@ extern "C" { * @{ */ #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(TIM1) #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#endif /* TIM1 */ #if defined(SPI1) #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN #endif /* SPI1 */ @@ -207,7 +213,9 @@ extern "C" { */ /** * @brief Enable AHB1 peripherals clock. +#if defined(GPDMA1) * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_EnableClock\n +#endif * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n @@ -216,10 +224,12 @@ extern "C" { * AHB1ENR SRAM1EN LL_AHB1_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH +#if defined(GPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 @@ -238,7 +248,9 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) /** * @brief Check if AHB1 peripheral clock is enabled or not - * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_IsEnabledClock\n +#if defined(GPDMA1) + * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_IsEnabledClock +#endif * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n @@ -247,10 +259,12 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) * AHB1ENR SRAM1EN LL_AHB1_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH +#if defined(GPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 @@ -265,7 +279,9 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) /** * @brief Disable AHB1 peripherals clock. - * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_DisableClock\n +#if defined(GPDMA1) + * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_DisableClock +#endif * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n @@ -274,10 +290,12 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) * AHB1ENR SRAM1EN LL_AHB1_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH +#if defined(GPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 @@ -292,15 +310,20 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) /** * @brief Force AHB1 peripherals reset. +#if defined(GPDMA1) * @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ForceReset\n +#endif * AHB1RSTR CRCRSTR LL_AHB1_GRP1_ForceReset\n * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ForceReset\n * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 +#if defined(GPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG * @retval None */ @@ -311,15 +334,20 @@ __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) /** * @brief Release AHB1 peripherals reset. +#if defined(GPDMA1) * @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ReleaseReset\n +#endif * AHB1RSTR CRCRSTR LL_AHB1_GRP1_ReleaseReset\n * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ReleaseReset\n * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ReleaseReset\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 +#if defined(GPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG * @retval None */ @@ -330,7 +358,9 @@ __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) /** * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes +#if defined(GPDMA1) * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n +#endif * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n @@ -339,10 +369,13 @@ __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 +#if defined(GPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 @@ -361,7 +394,9 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) /** * @brief Check if AHB1 peripheral clocks in Sleep and Stop modes is enabled or not +#if defined(GPDMA1) * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n +#endif * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n * AHB1SMENR CRCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n * AHB1SMENR TSCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n @@ -370,10 +405,13 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 +#if defined(GPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 @@ -388,7 +426,9 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) /** * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes +#if defined(GPDMA1) * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n +#endif * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n @@ -397,10 +437,13 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 +#if defined(GPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 @@ -990,14 +1033,18 @@ __STATIC_INLINE void LL_AHB5_GRP1_DisableClockStopSleep(uint32_t Periphs) * @brief Enable APB1 peripherals clock. * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n +#if defined(WWDG) * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n +#endif * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +#if defined(WWDG) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*) +#endif * @arg @ref LL_APB1_GRP1_PERIPH_USART2 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) * @@ -1034,14 +1081,18 @@ __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) * @brief Check if APB1 peripheral clock is enabled or not * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n +#if defined(WWDG) * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n +#endif * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +#if defined(WWDG) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*) +#endif * @arg @ref LL_APB1_GRP1_PERIPH_USART2 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) * @@ -1077,7 +1128,9 @@ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +#if defined(WWDG) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*) +#endif * @arg @ref LL_APB1_GRP1_PERIPH_USART2 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) * @@ -1174,14 +1227,18 @@ __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) * @brief Enable APB1 peripheral clocks in Sleep and Stop modes * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n +#if defined(WWDG) * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n +#endif * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +#if defined(WWDG) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*) +#endif * @arg @ref LL_APB1_GRP1_PERIPH_USART2 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) * @@ -1201,14 +1258,18 @@ __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs) * @brief Check if APB1 peripheral clocks in Sleep and Stop modes is enabled or not * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n +#if defined(WWDG) * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n +#endif * APB1SMENR1 USART2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +#if defined(WWDG) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*) +#endif * @arg @ref LL_APB1_GRP1_PERIPH_USART2 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) * @@ -1224,14 +1285,18 @@ __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * @brief Disable APB1 peripheral clocks in Sleep and Stop modes * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n +#if defined(WWDG) * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n +#endif * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +#if defined(WWDG) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*) +#endif * @arg @ref LL_APB1_GRP1_PERIPH_USART2 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) * diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_cortex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_cortex.h index edb4f86e13..aa1db7a068 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_cortex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_cortex.h @@ -106,10 +106,10 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control CORTEX LL MPU HFNMI and PRIVILEGED Access control * @{ */ -#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U -#define LL_MPU_CTRL_HARDFAULT_NMI 2U -#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U -#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ /** * @} */ @@ -117,22 +117,28 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Attributes CORTEX LL MPU Attributes * @{ */ -#define LL_MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ -#define LL_MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ -#define LL_MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ -#define LL_MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ - -#define LL_MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ -#define LL_MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ -#define LL_MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ - -#define LL_MPU_TRANSIENT 0x0U /* Normal memory, transient. */ -#define LL_MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ - -#define LL_MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ -#define LL_MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ -#define LL_MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ -#define LL_MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ +/* Device memory attributes */ +#define LL_MPU_DEVICE_nGnRnE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */ +#define LL_MPU_DEVICE_nGnRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */ +#define LL_MPU_DEVICE_nGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */ +#define LL_MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */ + +/* Normal memory attributes */ +/* Non-cacheable memory attribute */ +#define LL_MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable */ + +/* Cacheable memory attributes: combination of cache write policy, transient and allocation */ +/* - cache write policy */ +#define LL_MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through */ +#define LL_MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back */ +/* - transient mode attribute */ +#define LL_MPU_TRANSIENT 0x0U /*!< Normal memory, transient */ +#define LL_MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient */ +/* - allocation attribute */ +#define LL_MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate */ +#define LL_MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate */ +#define LL_MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate */ +#define LL_MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate */ /** * @} */ @@ -149,8 +155,8 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Instruction_Access CORTEX LL MPU Instruction Access * @{ */ -#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) -#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) /*!< Execute attribute */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) /*!< Execute never attribute */ /** * @} */ @@ -158,9 +164,9 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Access_Shareable CORTEX LL MPU Instruction Access Shareable * @{ */ -#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) -#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) -#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) +#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) /*!< Not shareable attribute */ +#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) /*!< Outer shareable attribute */ +#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) /*!< Inner shareable attribute */ /** * @} */ @@ -168,10 +174,10 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes CORTEX LL MPU Region Permission Attributes * @{ */ -#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) -#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) -#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) -#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) +#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) /*!< Read/write privileged-only attribute */ +#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) /*!< Read/write privileged/unprivileged attribute */ +#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) /*!< Read-only privileged-only attribute */ +#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) /*!< Read-only privileged/unprivileged attribute */ /** * @} */ @@ -793,9 +799,6 @@ __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, u /* Set region index */ WRITE_REG(MPU->RNR, Region); - /* Set base address */ - MPU->RBAR |= Attributes; - /* Set region base address and region access attributes */ WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes)); diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_hsem.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_hsem.h index 9f61e76eda..9f6923db63 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_hsem.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_hsem.h @@ -92,23 +92,7 @@ extern "C" { #define LL_HSEM_SEMAPHORE_13 HSEM_IER_ISE13 #define LL_HSEM_SEMAPHORE_14 HSEM_IER_ISE14 #define LL_HSEM_SEMAPHORE_15 HSEM_IER_ISE15 -#define LL_HSEM_SEMAPHORE_16 HSEM_IER_ISE16 -#define LL_HSEM_SEMAPHORE_17 HSEM_IER_ISE17 -#define LL_HSEM_SEMAPHORE_18 HSEM_IER_ISE18 -#define LL_HSEM_SEMAPHORE_19 HSEM_IER_ISE19 -#define LL_HSEM_SEMAPHORE_20 HSEM_IER_ISE20 -#define LL_HSEM_SEMAPHORE_21 HSEM_IER_ISE21 -#define LL_HSEM_SEMAPHORE_22 HSEM_IER_ISE22 -#define LL_HSEM_SEMAPHORE_23 HSEM_IER_ISE23 -#define LL_HSEM_SEMAPHORE_24 HSEM_IER_ISE24 -#define LL_HSEM_SEMAPHORE_25 HSEM_IER_ISE25 -#define LL_HSEM_SEMAPHORE_26 HSEM_IER_ISE26 -#define LL_HSEM_SEMAPHORE_27 HSEM_IER_ISE27 -#define LL_HSEM_SEMAPHORE_28 HSEM_IER_ISE28 -#define LL_HSEM_SEMAPHORE_29 HSEM_IER_ISE29 -#define LL_HSEM_SEMAPHORE_30 HSEM_IER_ISE30 -#define LL_HSEM_SEMAPHORE_31 HSEM_IER_ISE31 -#define LL_HSEM_SEMAPHORE_ALL 0xFFFFFFFFU +#define LL_HSEM_SEMAPHORE_ALL 0x0000FFFFU /** * @} */ @@ -361,7 +345,6 @@ __STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uin * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval None */ @@ -391,7 +374,6 @@ __STATIC_INLINE void LL_HSEM_SetSemaphoreSecure(HSEM_TypeDef *HSEMx, uint32_t Se * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval None */ @@ -432,7 +414,6 @@ __STATIC_INLINE uint32_t LL_HSEM_GetSemaphoreSecure(const HSEM_TypeDef *HSEMx) * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval None */ @@ -462,7 +443,6 @@ __STATIC_INLINE void LL_HSEM_SetSemaphorePrivilege(HSEM_TypeDef *HSEMx, uint32_t * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval None */ @@ -512,22 +492,6 @@ __STATIC_INLINE uint32_t LL_HSEM_GetSemaphorePrivilege(const HSEM_TypeDef *HSEMx * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval None */ @@ -561,22 +525,6 @@ __STATIC_INLINE void LL_HSEM_EnableIT_IER(HSEM_TypeDef *HSEMx, uint32_t Semaphor * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval None */ @@ -610,22 +558,6 @@ __STATIC_INLINE void LL_HSEM_DisableIT_IER(HSEM_TypeDef *HSEMx, uint32_t Semapho * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ @@ -668,22 +600,6 @@ __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_IER(const HSEM_TypeDef *HSEMx, uint * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval None */ @@ -717,22 +633,6 @@ __STATIC_INLINE void LL_HSEM_ClearFlag_ICR(HSEM_TypeDef *HSEMx, uint32_t Semapho * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ @@ -766,22 +666,6 @@ __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_ISR(const HSEM_TypeDef *HSEMx, uin * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h index 2434996143..fec55e8434 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h @@ -356,9 +356,9 @@ typedef struct * @{ */ #if defined(I2C1) -#define LL_I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2 */ -#endif /* I2C1, I2C2 */ -#define LL_I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3, I2C4 */ +#define LL_I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1 */ +#endif /* I2C1 */ +#define LL_I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ #if defined(I2C_TRIG_GRP1) #define LL_I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x00000000U)) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rcc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rcc.h index 97e4f31033..10239a1cc2 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rcc.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rcc.h @@ -159,7 +159,9 @@ typedef struct #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */ #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software reset flag */ #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent watchdog reset flag */ +#if defined(WWDG) #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#endif /* defined(WWDG) */ #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-power reset flag */ /** * @} @@ -2927,6 +2929,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL); } +#if defined(WWDG) /** * @brief Check if RCC flag Window Watchdog reset is set or not. * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST @@ -2936,6 +2939,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) { return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL); } +#endif /* WWDG */ /** * @brief Check if RCC flag BOR reset is set or not. diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rng.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rng.h index efeec7000b..7d47a67f1c 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rng.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rng.h @@ -230,7 +230,8 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx) { - CLEAR_BIT(RNGx->CR, RNG_CR_CED); + MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_ENABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -241,7 +242,8 @@ __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx) { - SET_BIT(RNGx->CR, RNG_CR_CED); + MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_DISABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -331,7 +333,7 @@ __STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx) __STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx) { MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_CUSTOM_NIST | RNG_CR_CONDRST); - CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);; + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -442,7 +444,7 @@ __STATIC_INLINE uint32_t LL_RNG_GetConfig3(const RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider) { - MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, (Divider << RNG_CR_CLKDIV_Pos) | RNG_CR_CONDRST); + MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, Divider | RNG_CR_CONDRST); CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } @@ -672,6 +674,9 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledArdis(const RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG) { +#if defined(RNG_HTCR_NIST_VALUE) + /* For NIST compliance we can fin the recommended value in the application note AN4230 */ +#endif /* defined(RNG_HTCR_NIST_VALUE) */ WRITE_REG(RNGx->HTCR, HTCFG); } @@ -693,7 +698,7 @@ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(const RNG_TypeDef *RNGx) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct); +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct); void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_system.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_system.h index 5ceb48622b..8f9ce8b0d9 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_system.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_system.h @@ -84,6 +84,17 @@ extern "C" { * @} */ +#ifdef SYSCFG_CCCSR_EN2 +/** @defgroup SYSTEM_LL_EC_CS2 SYSCFG SYSCFG VddIO2 compensation cell Code selection + * @{ + */ +#define LL_SYSCFG_VDDIO2_CELL_CODE 0U /*VDDIO2 I/Os code from the cell (available in the SYSCFG_CCVR)*/ +#define LL_SYSCFG_VDDIO2_REGISTER_CODE SYSCFG_CCCSR_CS2 /*VDDIO2 I/Os code from the SYSCFG compensation cell code register (SYSCFG_CCCR)*/ +/** + * @} + */ +#endif /* SYSCFG_CCCSR_EN2 */ + /** @defgroup SYSTEM_LL_EC_ERASE_MEMORIES_STATUS SYSCFG MEMORIES ERASE * @{ */ @@ -634,7 +645,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationValue(void) * @rmtoll CCCR PCC1 LL_SYSCFG_SetPMOSVddCompensationCode * @param PMOSCode PMOS compensation code * This code is applied to the PMOS compensation cell when the CS1 bit of the - * SYSCFG_CMPCR is set + * SYSCFG_CCCSR is set * @retval None */ __STATIC_INLINE void LL_SYSCFG_SetPMOSVddCompensationCode(uint32_t PMOSCode) @@ -654,10 +665,10 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationCode(void) /** * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDD - * @rmtoll CCCR PCC2 LL_SYSCFG_SetNMOSVddCompensationCode + * @rmtoll CCCR NCC1 LL_SYSCFG_SetNMOSVddCompensationCode * @param NMOSCode NMOS compensation code - * This code is applied to the NMOS compensation cell when the CS2 bit of the - * SYSCFG_CMPCR is set + * This code is applied to the NMOS compensation cell when the CS1 bit of the + * SYSCFG_CCCSR is set * @retval None */ __STATIC_INLINE void LL_SYSCFG_SetNMOSVddCompensationCode(uint32_t NMOSCode) @@ -730,7 +741,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddCMPCR(void) */ __STATIC_INLINE void LL_SYSCFG_SetVddCellCompensationCode(uint32_t CompCode) { - SET_BIT(SYSCFG->CCCSR, CompCode); + MODIFY_REG(SYSCFG->CCCSR, SYSCFG_CCCSR_CS1, CompCode); } /** @@ -745,6 +756,145 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetVddCellCompensationCode(void) return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS1)); } +#ifdef SYSCFG_CCCSR_EN2 +/** + * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDDIO2 + * @rmtoll CCVR PCV2 LL_SYSCFG_GetPMOSVddIO2CompensationValue + * @retval Returned value is the PMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationValue(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV2)); +} + +/** + * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDDIO2 + * @rmtoll CCVR NCV2 LL_SYSCFG_GetNMOSVddIO2CompensationValue + * @retval Returned value is the NMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationValue(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV2)); +} + + +/** + * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2 + * @rmtoll CCCR PCC2 LL_SYSCFG_SetPMOSVddIO2CompensationCode + * @param PMOSCode PMOS compensation code + * This code is applied to the PMOS compensation cell when the CS2 bit of the + * SYSCFG_CCCSR is set + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetPMOSVddIO2CompensationCode(uint32_t PMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC2, PMOSCode << SYSCFG_CCCR_PCC2_Pos); +} + +/** + * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2 + * @rmtoll CCCR PCC2 LL_SYSCFG_GetPMOSVddIO2CompensationCode + * @retval Returned value is the PMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC2)); +} + +/** + * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2 + * @rmtoll CCCR NCC2 LL_SYSCFG_SetNMOSVddIO2CompensationCode + * @param NMOSCode NMOS compensation code + * This code is applied to the NMOS compensation cell when the CS2 bit of the + * SYSCFG_CCCSR is set + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetNMOSVddIO2CompensationCode(uint32_t NMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC2, NMOSCode << SYSCFG_CCCR_NCC2_Pos); +} + +/** + * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2 + * @rmtoll CCCR NCC2 LL_SYSCFG_GetNMOSVddIO2CompensationCode + * @retval Returned value is the VddIO2 compensation cell code for NMOS transistors + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC2)); +} + +/** + * @brief Enable the Compensation Cell of GPIO supplied by VDDIO2 + * @rmtoll CCCSR EN2 LL_SYSCFG_EnableVddIO2CompensationCell + * @note The VddIO2 compensation cell can be used only when the device supply + * voltage ranges from 1.71 to 3.6 V + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableVddIO2CompensationCell(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2); +} + +/** + * @brief Disable the Compensation Cell of GPIO supplied by VDDIO2 + * @rmtoll CCCSR EN2 LL_SYSCFG_EnableVddIO2CompensationCell + * @note The VddIO2 compensation cell can be used only when the device supply + * voltage ranges from 1.71 to 3.6 V + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableVddIO2CompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2); +} + +/** + * @brief Check if the Compensation Cell of GPIO supplied by VDDIO2 is enable + * @rmtoll CCCSR EN2 LL_SYSCFG_IsEnabled_VddIO2CompensationCell + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddIO2CompensationCell(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2) == SYSCFG_CCCSR_EN2) ? 1UL : 0UL); +} + +/** + * @brief Get Compensation Cell ready Flag of GPIO supplied by VDDIO2 + * @rmtoll CCCSR RDY2 LL_SYSCFG_IsActiveFlag_VddIO2CMPCR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddIO2CMPCR(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY2) == (SYSCFG_CCCSR_RDY2)) ? 1UL : 0UL); +} + +/** + * @brief Set the compensation cell code selection of GPIO supplied by VDDIO2 + * @rmtoll CCCSR CS2 LL_SYSCFG_SetVddIO2CellCompensationCode + * @param CompCode: Selects the code to be applied for the VddIO2 compensation cell + * This parameter can be one of the following values: + * @arg LL_SYSCFG_VDDIO2_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR) + * @arg LL_SYSCFG_VDDIO2_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR) + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetVddIO2CellCompensationCode(uint32_t CompCode) +{ + MODIFY_REG(SYSCFG->CCCSR, SYSCFG_CCCSR_CS2, CompCode); +} + +/** + * @brief Get the compensation cell code selection of GPIO supplied by VDDIO2 + * @rmtoll CCCSR CS2 LL_SYSCFG_GetVddIO2CellCompensationCode + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_VDDIO2_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) + * @arg LL_SYSCFG_VDDIO2_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR) + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetVddIO2CellCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS2)); +} +#endif /* SYSCFG_CCCSR_EN2 */ + /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_tim.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_tim.h index b54be94dd3..6f7c5aff8f 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_tim.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_tim.h @@ -6098,7 +6098,7 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T * @} */ -#endif /* TIM1 || TIM2 || TIM3 || TIM6 || TIM7 */ +#endif /* TIM1 || TIM2 || TIM3 || TIM16 || TIM17 */ /** * @} diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_utils.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_utils.h index c40d3eb39d..db35bbb41a 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_utils.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_utils.h @@ -157,12 +157,11 @@ typedef struct /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE * @{ */ -#define LL_UTILS_PACKAGETYPE_UQFN32 0x00000000U /*!< UQFN32 package type */ -#define LL_UTILS_PACKAGETYPE_UQFN48 0x00000001U /*!< UQFN48 package type */ -#define LL_UTILS_PACKAGETYPE_BGA59 0x00000002U /*!< BGA59 package type */ -#define LL_UTILS_PACKAGETYPE_UQFN32_SMPS 0x00000003U /*!< UQFN32 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_UQFN48_SMPS 0x00000004U /*!< UQFN48 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_BGA59_SMPS 0x00000005U /*!< BGA59 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000000U /*!< UFQFPN32 package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN48 0x00000002U /*!< UFQFPN48 package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP41_SMPS 0x00000009U /*!< WLCSP41 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN48_SMPS 0x0000000AU /*!< UFQFPN48 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA59 0x0000000BU /*!< UFBGA59 package type */ /** * @} */ @@ -223,12 +222,11 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void) /** * @brief Get Package type * @retval Returned value can be one of the following values: - * @arg @ref LL_UTILS_PACKAGETYPE_UQFN32 - * @arg @ref LL_UTILS_PACKAGETYPE_UQFN48 - * @arg @ref LL_UTILS_PACKAGETYPE_BGA59 - * @arg @ref LL_UTILS_PACKAGETYPE_UQFN32_SMPS - * @arg @ref LL_UTILS_PACKAGETYPE_UQFN48_SMPS - * @arg @ref LL_UTILS_PACKAGETYPE_BGA59_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN32 + * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48 + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP41_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA59 */ __STATIC_INLINE uint32_t LL_GetPackageType(void) { diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32WBAxx_HAL_Driver/Release_Notes.html index feb3a2c8b2..822e47089f 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Release_Notes.html @@ -40,10 +40,10 @@

Purpose

Update History

- +

Main Changes

-

Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices

+

Official Release of STM32CubeWBA Firmware package supporting STM32WBA50xx, STM32WBA52xx, STM32WBA54xx and STM32WBA55xx devices

Contents

Official Release of HAL/LL Drivers for STM32WBAxx serie

    @@ -60,6 +60,114 @@

    HAL Drivers updates

    • HAL CORTEX driver
        +
      • Add how to use MPU attributes
        • +
      • +
    • HAL CRC driver +
        +
      • Update HAL_CRC_DeInit() function to fix coverity warning
        • +
      • +
    • HAL GPIO driver +
        +
      • Update RF alternate function define to keep only one
        • +
      • +
    • HAL GTZC driver +
        +
      • Fixed overflow issue in HAL_GTZC_TZIC_GetFlag()
        • +
      • +
    • HAL RNG driver +
        +
      • Remove wrong implementation of the HAL_RNG_GenerateRandomNumber
        • +
      • Update the Check of valid random data
        • +
      • Update the flag in new check to avoid false timeout detection
        • +
      • Add CR, HTCR NIST values
        • +
      • +
    • HAL UART driver +
        +
      • Add HAL_UART_RXEVENT_IDLE event notification to user in case of HAL_UARTEx_ReceiveToIdle_DMA() use with Circular DMA, even if occurring just after TC event.
        • +
      • Correct wrong comment in HAL_UARTEx_DisableFifoMode() function
        • +
      • Align prescaler value used by default in UART_GET_DIV_FACTOR macro with RM.
        • +
      • +
    • HAL USART driver +
        +
      • Improve the visibility of the SPI function support in HAL USART description and comments.
        • +
      • Correct wrong comment in HAL_USARTEx_DisableFifoMode() function
        • +
      • Align prescaler value used by default in USART_GET_DIV_FACTOR macro with RM.
        • +
      • +
    +


    +

    +

    LL Drivers updates

    +
      +
    • LL CORTEX driver +
        +
      • Remove duplicate write of attributes in LL_MPU_ConfigRegion() function
        • +
      • Add how to use MPU attributes
        • +
      • +
    • LL EXTI driver +
        +
      • Update LL_EXTI_DeInit, do not reset security and privilege
        • +
      • +
    • LL HSEM driver +
        +
      • Update LL HSEM description and define to be aligned with the correct number of semaphores
        • +
      • +
    • LL RNG driver +
        +
      • Remove wrong implementation of LL_RNG APIs
        • +
      • Correction of Misra-C:2012 Rule-8.13 warning
        • +
      • Add CR, HTCR NIST values
        • +
      • +
    • LL UTILS driver +
        +
      • Update package type values
        • +
      • +
    +


    +

    +

    Supported Devices and boards

    +
      +
    • STM32WBA50xx, STM32WBA52xx, STM32WBA54xx and STM32WBA55xx devices
      • +
    • NUCLEO-WBA52CG, NUCLEO-WBA55CG and STM32WBA55G-DK1 boards
      • +
    +

    Backward compatibility

    +
      +
    • Not applicable
      • +
    +

    Known Limitations

    +
      +
    • None
      • +
    +

    Dependencies

    +
      +
    • None
      • +
    +

    Notes

    +
      +
    • None
      • +
    +
+
+
+ +
+

Main Changes

+

Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices

+

Contents

+

Official Release of HAL/LL Drivers for STM32WBAxx serie

+
    +
  • HAL/LL Drivers are available for all peripherals: +
      +
    • HAL: ADC, COMP, CORTEX, CRC, CRYP, DMA, EXTI, FLASH, GPIO, GTZC, HASH, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PKA, PWR, RAMCFG, RCC, RNG, RTC, SAI, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART, WWDG
      • +
    • LL: ADC, COMP, CRC, DMA, EXTI, GPIO, I2C, ICACHE, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS
      • +
    • +
  • Update HAL/LL drivers to include latest corrections
    • +
+


+

+

HAL Drivers updates

+
    +
  • HAL CORTEX driver +
    • Add functions to configure MPU region without enabling it
  • HAL I2C driver @@ -87,7 +195,7 @@

    HAL Drivers updates


-

LL Drivers updates

+

LL Drivers updates

  • LL LPUART driver
      @@ -96,24 +204,24 @@

      LL Drivers updates


    -

    Supported Devices and boards

    +

    Supported Devices and boards

    • STM32WBA52xx and STM32WBA55xx devices
    • NUCLEO-WBA52CG, NUCLEO-WBA55CG and STM32WBA55G-DK1 boards
    -

    Backward compatibility

    +

    Backward compatibility

    • Not applicable
    -

    Known Limitations

    +

    Known Limitations

    • None
    -

    Dependencies

    +

    Dependencies

    • None
    -

    Notes

    +

    Notes

    • None
    @@ -122,10 +230,10 @@

    Notes

    -

    Main Changes

    +

    Main Changes

    Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices

    -

    Contents

    -

    Official Release of HAL/LL Drivers for STM32WBAxx serie

    +

    Contents

    +

    Official Release of HAL/LL Drivers for STM32WBAxx serie

    • HAL/LL Drivers are available for all peripherals:
        @@ -141,7 +249,7 @@

        Official Relea


      -

      HAL Drivers updates

      +

      HAL Drivers updates

      • HAL CORTEX driver
          @@ -228,7 +336,7 @@

          HAL Drivers updates


        -

        LL Drivers updates

        +

        LL Drivers updates

        • LL GPIO driver
            @@ -253,24 +361,24 @@

            LL Drivers updates


          -

          Supported Devices and boards

          +

          Supported Devices and boards

          • STM32WBA52xx and STM32WBA55xx devices
          • NUCLEO-WBA52CG, NUCLEO-WBA55CG and STM32WBA55G-DK1 boards
          -

          Backward compatibility

          +

          Backward compatibility

          • Not applicable
          -

          Known Limitations

          +

          Known Limitations

          • None
          -

          Dependencies

          +

          Dependencies

          • None
          -

          Notes

          +

          Notes

          • None
          @@ -279,10 +387,10 @@

          Notes

          -

          Main Changes

          +

          Main Changes

          Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

          -

          Contents

          -

          Official Release of HAL/LL Drivers for STM32WBAxx serie

          +

          Contents

          +

          Official Release of HAL/LL Drivers for STM32WBAxx serie

          • HAL/LL Drivers are available for all peripherals:
              @@ -292,7 +400,7 @@

              Official Relea


            -

            HAL Drivers updates

            +

            HAL Drivers updates

            • HAL CORTEX driver
                @@ -353,7 +461,7 @@

                HAL Drivers updates


              -

              LL Drivers updates

              +

              LL Drivers updates

              • LL DMA driver
                  @@ -375,24 +483,24 @@

                  LL Drivers updates


                -

                Supported Devices and boards

                +

                Supported Devices and boards

                • STM32WBA52xx devices
                • NUCLEO-WBA52CG board
                -

                Backward compatibility

                +

                Backward compatibility

                • Not applicable
                -

                Known Limitations

                +

                Known Limitations

                • None
                -

                Dependencies

                +

                Dependencies

                • None
                -

                Notes

                +

                Notes

                • None
                @@ -401,9 +509,9 @@

                Notes

                -

                Main Changes

                +

                Main Changes

                First Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

                -

                Contents

                +

                Contents

                First Official Release of HAL/LL Drivers for STM32WBAxx serie

                • HAL/LL Drivers are available for all peripherals: @@ -414,24 +522,24 @@

                  First Offi


                -

                Supported Devices and boards

                +

                Supported Devices and boards

                • STM32WBA52xx devices
                • NUCLEO-WBA52CG board
                -

                Backward compatibility

                +

                Backward compatibility

                • Not applicable
                -

                Known Limitations

                +

                Known Limitations

                • None
                -

                Dependencies

                +

                Dependencies

                • None
                -

                Notes

                +

                Notes

                • None
                diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal.c index 1d5b8c19c7..e6e6736413 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal.c @@ -48,6 +48,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ + /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -559,6 +560,16 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void) =============================================================================== [..] This section provides functions allowing to: (+) Enable/Disable the I/O analog switch voltage booster + (+) Configure the Voltage reference buffer + (+) Enable/Disable the Voltage reference buffer + (+) Enable/Disbale the OTG PHY + (+) Configure the OTG PHY power down + (+) Select the OTG PHY reference clock + (+) Configure the OTG PHY disconnect/squelch threshold + (+) Configure the OTG PHY transmitter pre-emphasis current + (+) Enable/Disable the compensation cell + (+) Get the compensation cell ready status + (+) Configure/Get the code selection for the compensation cell @endverbatim * @{ @@ -571,7 +582,7 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void) */ void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void) { - SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); + MODIFY_REG(SYSCFG->CFGR1, (SYSCFG_CFGR1_BOOSTEN | SYSCFG_CFGR1_ANASWVDD), SYSCFG_CFGR1_BOOSTEN); } /** @@ -584,6 +595,237 @@ void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void) CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); } +/** + * @brief Enable the I/O analog switch supplied by VDD + * @note To be used when I/O analog switch voltage booster is not enabled + * @retval None + */ +void HAL_SYSCFG_EnableIOAnalogSwitchVdd(void) +{ + MODIFY_REG(SYSCFG->CFGR1, (SYSCFG_CFGR1_BOOSTEN | SYSCFG_CFGR1_ANASWVDD), SYSCFG_CFGR1_ANASWVDD); +} + +/** + * @brief Disable the I/O analog switch supplied by VDD + * @retval None + */ +void HAL_SYSCFG_DisableIOAnalogSwitchVdd(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); +} + + +#ifdef SYSCFG_OTGHSPHYCR_EN +/** + * @brief Enable the OTG PHY . + * @param OTGPHYConfig Defines the OTG PHY configuration. + This parameter can be one of @ref SYSCFG_OTG_PHY_Enable + * @retval None + */ +void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_CONFIG(OTGPHYConfig)); + + MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN, OTGPHYConfig); +} + +/** + * @brief Set the OTG PHY Power Down config. + * @param PowerDownConfig Defines the OTG PHY Power down configuration. + This parameter can be one of @ref SYSCFG_OTG_PHY_PowerDown + * @retval None + */ +void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(PowerDownConfig)); + + MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL, PowerDownConfig); +} + +/** + * @brief Set the OTG PHY reference clock selection. + * @param RefClkSelection Defines the OTG PHY reference clock selection. + This parameter can be one of the @ref SYSCFG_OTG_PHY_RefenceClockSelection + * @retval None + */ +void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClkSelection) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(RefClkSelection)); + + MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_CLKSEL, RefClkSelection); +} + +/** + * @brief Set the OTG PHY Disconnect Threshold. + * @param DisconnectThreshold Defines the voltage level for the threshold used to detect a disconnect event. + This parameter can be one of the @ref SYSCFG_OTG_PHYTUNER_DisconnectThreshold + * @retval None + */ +void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_DISCONNECT(DisconnectThreshold)); + + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE, DisconnectThreshold); +} + +/** + * @brief Set the OTG PHY Squelch Threshold. + * @param SquelchThreshold Defines the voltage level. + This parameter can be onez of the @ref SYSCFG_OTG_PHYTUNER_SquelchThreshold + + * @retval None + */ +void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_SQUELCH(SquelchThreshold)); + + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_SQRXTUNE, SquelchThreshold); +} + +/** + * @brief Set the OTG PHY transmitter pre-emphasis current. + * @param PreemphasisCurrent Defines the current configuration. + This parameter can be one of the @ref SYSCFG_OTG_PHYTUNER_PreemphasisCurrent + + * @retval None + */ +void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_PREEMPHASIS(PreemphasisCurrent)); + + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE, PreemphasisCurrent); +} +#endif /* SYSCFG_OTGHSPHYCR_EN */ + +/** + * @brief Enable the compensation cell + * @param Selection specifies the concerned compensation cell + * This parameter can the combination of the following values: + * @arg SYSCFG_IO_CELL Compensation cell for the VDD I/O power rail + * @arg SYSCFG_IO2_CELL Compensation cell for the VDDIO2 I/O power rail + * @retval None + */ +void HAL_SYSCFG_EnableCompensationCell(uint32_t Selection) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_COMPENSATION_CELL(Selection)); + + SET_BIT(SYSCFG->CCCSR, Selection); +} + +/** + * @brief Disable the compensation cell + * @param Selection specifies the concerned compensation cell + * This parameter can the combination of the following values: + * @arg SYSCFG_IO_CELL Compensation cell for the VDD I/O power rail + * @arg SYSCFG_IO2_CELL Compensation cell for the VDDIO2 I/O power rail + * @retval None + */ +void HAL_SYSCFG_DisableCompensationCell(uint32_t Selection) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_COMPENSATION_CELL(Selection)); + + MODIFY_REG(SYSCFG->CCCSR, Selection, 0U); +} + +/** + * @brief Get the compensation cell ready status + * @param Selection specifies the concerned compensation cell + * This parameter can one of the following values: + * @arg SYSCFG_IO_CELL_READY Compensation cell for the VDD I/O power rail + * @arg SYSCFG_IO2_CELL_READY Compensation cell for the VDDIO2 I/O power rail + * @retval Ready status (1 or 0) + */ +uint32_t HAL_SYSCFG_GetCompensationCellReadyStatus(uint32_t Selection) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_COMPENSATION_CELL_READY(Selection)); + + return (((SYSCFG->CCCSR & Selection) == 0U) ? 0UL : 1UL); +} + +/** + * @brief Configure the code selection for the compensation cell + * @param Selection specifies the concerned compensation cell + * This parameter can one of the following values: + * @arg SYSCFG_IO_CELL Compensation cell for the VDD I/O power rail + * @arg SYSCFG_IO2_CELL Compensation cell for the VDDIO2 I/O power rail + * @param Code code selection to be applied for the I/O compensation cell + * This parameter can be one of the following values: + * @arg SYSCFG_IO_CELL_CODE Code from the cell (available in the SYSCFG_CCVR) + * @arg SYSCFG_IO_REGISTER_CODE Code from the compensation cell code register (SYSCFG_CCCR) + * @param NmosValue In case SYSCFG_IO_REGISTER_CODE is selected, it provides the Nmos value + * to apply in range 0 to 15 else this parameter is not used + * @param PmosValue In case SYSCFG_IO_REGISTER_CODE is selected, it provides the Pmos value + * to apply in range 0 to 15 else this parameter is not used + * @retval None + */ +void HAL_SYSCFG_ConfigCompensationCell(uint32_t Selection, uint32_t Code, uint32_t NmosValue, uint32_t PmosValue) +{ + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_SYSCFG_COMPENSATION_CELL(Selection)); + assert_param(IS_SYSCFG_COMPENSATION_CELL_CODE(Code)); + + if (Code == SYSCFG_IO_REGISTER_CODE) + { + /* Check the parameters */ + assert_param(IS_SYSCFG_COMPENSATION_CELL_NMOS_VALUE(NmosValue)); + assert_param(IS_SYSCFG_COMPENSATION_CELL_PMOS_VALUE(PmosValue)); + + offset = ((Selection == SYSCFG_IO_CELL) ? 0U : 8U); + + MODIFY_REG(SYSCFG->CCCR, (0xFFU << offset), ((NmosValue << offset) | (PmosValue << (offset + 4U)))); + } + + MODIFY_REG(SYSCFG->CCCSR, (Selection << 1U), (Code << (POSITION_VAL(Selection) + 1U))); +} + +/** + * @brief Get the code selection for the compensation cell + * @param Selection specifies the concerned compensation cell + * This parameter can one of the following values: + * @arg SYSCFG_IO_CELL Compensation cell for the VDD I/O power rail + * @arg SYSCFG_IO2_CELL Compensation cell for the VDDIO2 I/O power rail + * @param pCode pointer code selection + * This parameter can be one of the following values: + * @arg SYSCFG_IO_CELL_CODE Code from the cell (available in the SYSCFG_CCVR) + * @arg SYSCFG_IO_REGISTER_CODE Code from the compensation cell code register (SYSCFG_CCCR) + * @param pNmosValue pointer to the Nmos value in range 0 to 15 + * @param pPmosValue pointer to the Pmos value in range 0 to 15 + * @retval HAL_OK (all values available) or HAL_ERROR (check parameters) + */ +HAL_StatusTypeDef HAL_SYSCFG_GetCompensationCell(uint32_t Selection, uint32_t *pCode, uint32_t *pNmosValue, + uint32_t *pPmosValue) +{ + uint32_t reg; + uint32_t offset; + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check parameters */ + if ((pCode != NULL) && (pNmosValue != NULL) && (pPmosValue != NULL)) + { + *pCode = ((SYSCFG->CCCSR & (Selection << 1U)) == 0U) ? SYSCFG_IO_CELL_CODE : SYSCFG_IO_REGISTER_CODE; + + reg = (*pCode == SYSCFG_IO_CELL_CODE) ? (SYSCFG->CCVR) : (SYSCFG->CCCR); + offset = ((Selection == SYSCFG_IO_CELL) ? 0U : 8U); + + *pNmosValue = ((reg >> offset) & 0xFU); + *pPmosValue = ((reg >> (offset + 4U)) & 0xFU); + + status = HAL_OK; + } + return status; +} + /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_cortex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_cortex.c index cfad3c53ee..c8654c2d8d 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_cortex.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_cortex.c @@ -48,25 +48,44 @@ [..] Setup SysTick Timer for time base. - (+) The SysTick clock source shall be configured with HAL_SYSTICK_CLKSourceConfig(). + (+) The SysTick clock source shall be configured with HAL_SYSTICK_CLKSourceConfig(). - (+) The SysTick IRQ priority shall be configured with HAL_NVIC_SetPriority(SysTick_IRQn,...). - The HAL_NVIC_SetPriority() calls the CMSIS NVIC_SetPriority() function. + (+) The SysTick IRQ priority shall be configured with HAL_NVIC_SetPriority(SysTick_IRQn,...). + The HAL_NVIC_SetPriority() calls the CMSIS NVIC_SetPriority() function. - (+) The HAL_SYSTICK_Config() function: + (+) The HAL_SYSTICK_Config() function: (++) Configures the SysTick Reload register with the value passed as function parameter. (++) Resets the SysTick Counter register. (++) Enables the SysTick Interrupt. (++) Starts the SysTick Counter. - (+) To adjust the SysTick time base, use the following formula: + (+) To adjust the SysTick time base, use the following formula: - Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) - (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function - (++) Reload Value should not exceed 0xFFFFFF + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF - (+) In case the HAL time base is the SysTick Timer, the HAL time base configuration must be completed - by calling the HAL_InitTick() function. + (+) In case the HAL time base is the SysTick Timer, the HAL time base configuration must be completed + by calling the HAL_InitTick() function. + + [..] + *** How to configure MPU regions using CORTEX HAL driver *** + ============================================================ + [..] + This section provides functions allowing to configure the Memory Protection Unit (MPU). + + (#) Disable the MPU using HAL_MPU_Disable(). + (#) Configure the necessary MPU memory attributes using HAL_MPU_ConfigMemoryAttributes(). + (#) Configure the necessary MPU regions using HAL_MPU_ConfigRegion() ennsuring that the MPU region configuration link to + the right MPU attributes number. + (#) Enable the MPU using HAL_MPU_Enable() function. + + -@- The memory management fault exception is enabled in HAL_MPU_Enable() function and the system will enter the memory + management fault handler MemManage_Handler() when an illegal memory access is performed. + -@- If the MPU has previously been programmed, disable the unused regions to prevent any previous region configuration + from affecting the new MPU configuration. + -@- MPU APIs ending with '_NS' allow to control the non-secure Memory Protection Unit (MPU_NS) from the secure context + and the same sequence as above applies to configure the non-secure MPU. @endverbatim ****************************************************************************** diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_crc.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_crc.c index f5c7641f69..1e4fb3d823 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_crc.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_crc.c @@ -200,7 +200,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) __HAL_CRC_DR_RESET(hcrc); /* Reset IDR register content */ - CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR); + CLEAR_REG(hcrc->Instance->IDR); /* DeInit the low level hardware */ HAL_CRC_MspDeInit(hcrc); diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_crc_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_crc_ex.c index 3678b1b5ca..ce816079c4 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_crc_ex.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_crc_ex.c @@ -210,8 +210,6 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_ } - - /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_gtzc.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_gtzc.c index ae65a395a3..c0cf9910fe 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_gtzc.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_gtzc.c @@ -560,12 +560,14 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, mpcbb_ptr = GTZC_MPCBB2; mem_size = GTZC_MEM_SIZE(SRAM2); } +#if defined(GTZC_MPCBB6) else { /* Here MemBaseAddress is inside SRAM6 (parameter already checked) */ mpcbb_ptr = GTZC_MPCBB6; mem_size = GTZC_MEM_SIZE(SRAM6); } +#endif /* GTZC_MPCBB6 */ /* translate mem_size in number of super-blocks */ size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE); @@ -631,11 +633,13 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, mpcbb_ptr = GTZC_MPCBB2; mem_size = GTZC_MEM_SIZE(SRAM2); } +#if defined(GTZC_MPCBB6) else { mpcbb_ptr = GTZC_MPCBB6; mem_size = GTZC_MEM_SIZE(SRAM6); } +#endif /* GTZC_MPCBB6 */ /* translate mem_size in number of super-blocks */ size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE); @@ -725,6 +729,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, base_address = SRAM2_BASE_S; } #endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#if defined(GTZC_MPCBB6) else if (((IS_ADDRESS_IN_NS(SRAM6, MemAddress)) && (IS_ADDRESS_IN_NS(SRAM6, end_address))) != 0U) { @@ -739,6 +744,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, base_address = SRAM6_BASE_S; } #endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* GTZC_MPCBB6 */ else { return HAL_ERROR; @@ -870,6 +876,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, base_address = SRAM2_BASE_S; } #endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#if defined(GTZC_MPCBB6) else if ((IS_ADDRESS_IN_NS(SRAM6, MemAddress)) && (IS_ADDRESS_IN_NS(SRAM6, end_address))) { @@ -884,6 +891,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, base_address = SRAM6_BASE_S; } #endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* GTZC_MPCBB6 */ else { return HAL_ERROR; @@ -963,6 +971,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCK; } +#if defined(GTZC_MPCBB6) else if ((IS_ADDRESS_IN(SRAM6, MemAddress)) && (IS_ADDRESS_IN(SRAM6, (MemAddress + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) @@ -972,6 +981,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, /* limitation: code not portable with memory > 512K */ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB6_S->CFGLOCK; } +#endif /* GTZC_MPCBB6 */ else { return HAL_ERROR; @@ -1056,6 +1066,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, /* limitation: code not portable with memory > 512K */ reg_mpcbb = GTZC_MPCBB2_S->CFGLOCK; } +#if defined(GTZC_MPCBB6) else if ((IS_ADDRESS_IN(SRAM6, MemAddress)) && (IS_ADDRESS_IN(SRAM6, (MemAddress + (NbSuperBlocks @@ -1066,6 +1077,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, /* limitation: code not portable with memory > 512K */ reg_mpcbb = GTZC_MPCBB6_S->CFGLOCK; } +#endif /* GTZC_MPCBB6 */ else { return HAL_ERROR; @@ -1102,10 +1114,12 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress) { SET_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } +#if defined(GTZC_MPCBB6) else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) { SET_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } +#endif /* GTZC_MPCBB6 */ else { return HAL_ERROR; @@ -1132,10 +1146,12 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress, { *pLockState = READ_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } +#if defined(GTZC_MPCBB6) else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) { *pLockState = READ_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } +#endif /* GTZC_MPCBB6 */ else { return HAL_ERROR; @@ -1287,7 +1303,7 @@ HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag) } reg_value = READ_REG(GTZC_TZIC->SR4); - for (i = 96U; i < 128U; i++) + for (i = 96U; i < GTZC_TZIC_PERIPH_NUMBER; i++) { pFlag[i] = (reg_value & (1UL << (i - 96U))) >> (i - 96U); } diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rcc_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rcc_ex.c index 53076faf4b..eb5248f48b 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rcc_ex.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rcc_ex.c @@ -239,6 +239,20 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *Peri /* Configure the AS clock source */ __HAL_RCC_AUDIOSYNC_CONFIG(PeriphClkInit->AudioSyncClockSelection); + + if (PeriphClkInit->AudioSyncClockSelection == RCC_ASCLKSOURCE_PLL1P) + { + /* Enable PLL1 PCLK output */ + __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL1_PCLK); + } + else if (PeriphClkInit->AudioSyncClockSelection == RCC_ASCLKSOURCE_PLL1Q) + { + __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL1_QCLK); + } + else + { + /* Do nothing ; for misra 15.7 error only */ + } } #endif @@ -340,15 +354,17 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *Peri /* Check if a backup domain reset is required */ if (tmpreg2 != RCC_RTCCLKSOURCE_DISABLE) { +#if defined(RCC_LSI2_SUPPORT) /* Save BDCR2 content */ tmpreg2 = RCC->BDCR2; - +#endif /* RCC_LSI2_SUPPORT */ /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); __HAL_RCC_BACKUPRESET_RELEASE(); - +#if defined(RCC_LSI2_SUPPORT) /* Restore previously saved BDCR2 */ RCC->BDCR2 = tmpreg2; +#endif /* RCC_LSI2_SUPPORT */ } /* Apply new RTC clock source selection */ @@ -627,6 +643,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) + #if defined(LPTIM2) case RCC_PERIPHCLK_LPTIM2: /* Get the current LPTIM2 source */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rng.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rng.c index 4b335fed2e..cbaa165f72 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rng.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rng.c @@ -200,6 +200,14 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Clock Error Detection Configuration when CONDRT bit is set to 1 */ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST | RNG_CR_RNG_CONFIG2, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST | (1U << RNG_CR_RNG_CONFIG2_Pos)); +#if defined(RNG_CR_NIST_VALUE) + /* Recommended value for NIST compliance, refer to application note AN4230 */ + WRITE_REG(hrng->Instance->CR, RNG_CR_NIST_VALUE); +#endif /* defined(RNG_CR_NIST_VALUE) */ +#if defined(RNG_HTCR_NIST_VALUE) + /* Recommended value for NIST compliance, refer to application note AN4230 */ + WRITE_REG(hrng->Instance->HTCR, RNG_HTCR_NIST_VALUE); +#endif /* defined(RNG_HTCR_NIST_VALUE) */ /* Writing bit CONDRST=0 */ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); @@ -234,12 +242,12 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Get tick */ tickstart = HAL_GetTick(); /* Check if data register contains valid random data */ - while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { /* New check to avoid false timeout detection in case of preemption */ - if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) { hrng->State = HAL_RNG_STATE_ERROR; hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; @@ -675,8 +683,6 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t /* Update the error code and status */ hrng->ErrorCode = HAL_RNG_ERROR_SEED; status = HAL_ERROR; - /* Clear bit DRDY */ - CLEAR_BIT(hrng->Instance->SR, RNG_FLAG_DRDY); } else /* No seed error */ { diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart.c index ba0d43cc7a..ce8899a170 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart.c @@ -2525,6 +2525,28 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } + else + { + /* If DMA is in Circular mode, Idle event is to be reported to user + even if occurring after a Transfer Complete event from DMA */ + if (nb_remaining_rx_data == huart->RxXferSize) + { + if (huart->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) + { + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } return; } else @@ -4599,6 +4621,7 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } @@ -4763,6 +4786,7 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart_ex.c index 266673617c..369f6ecfc3 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart_ex.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart_ex.c @@ -555,7 +555,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) /* Disable UART */ __HAL_UART_DISABLE(huart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); huart->FifoMode = UART_FIFOMODE_DISABLE; diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_usart.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_usart.c index 2cc064b0fa..a9d76e3d01 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_usart.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_usart.c @@ -144,7 +144,7 @@ */ /** @defgroup USART USART - * @brief HAL USART Synchronous module driver + * @brief HAL USART Synchronous SPI module driver * @{ */ @@ -227,8 +227,8 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); =============================================================================== [..] This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - (+) For the asynchronous mode only these parameters can be configured: + in synchronous SPI master/slave mode. + (+) For the synchronous SPI mode only these parameters can be configured: (++) Baud Rate (++) Word Length (++) Stop Bit @@ -240,7 +240,7 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); (++) Receiver/transmitter modes [..] - The HAL_USART_Init() function follows the USART synchronous configuration + The HAL_USART_Init() function follows the USART synchronous SPI configuration procedure (details for the procedure are available in reference manual). @endverbatim @@ -318,7 +318,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) return HAL_ERROR; } - /* In Synchronous mode, the following bits must be kept cleared: + /* In Synchronous SPI mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register - HDSEL, SCEN and IREN bits in the USART_CR3 register. */ @@ -659,11 +659,10 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ =============================================================================== ##### IO operation functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART synchronous + [..] This subsection provides a set of functions allowing to manage the USART synchronous SPI data transfers. - [..] The USART supports master mode only: it cannot receive or send data related to an input - clock (SCLK is always an output). + [..] The USART Synchronous SPI supports master and slave modes (SCLK as output or input). [..] @@ -3150,7 +3149,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits: * set CPOL bit according to husart->Init.CLKPolarity value * set CPHA bit according to husart->Init.CLKPhase value - * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only) + * set LBCL bit according to husart->Init.CLKLastBit value (used in USART Synchronous SPI master mode only) * set STOP[13:12] bits according to husart->Init.StopBits value */ tmpreg = (uint32_t)(USART_CLOCK_ENABLE); tmpreg |= (uint32_t)husart->Init.CLKLastBit; diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_usart_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_usart_ex.c index 2132f70a1f..d418c946e3 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_usart_ex.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_usart_ex.c @@ -364,7 +364,7 @@ HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) /* Disable USART */ __HAL_USART_DISABLE(husart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); husart->FifoMode = USART_FIFOMODE_DISABLE; diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_exti.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_exti.c index e47e04738e..77bf0a5322 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_exti.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_exti.c @@ -91,14 +91,6 @@ ErrorStatus LL_EXTI_DeInit(void) /* Pending register set to default reset values */ LL_EXTI_WriteReg(RPR1, 0xFFFFFFFFU); LL_EXTI_WriteReg(FPR1, 0xFFFFFFFFU); -#if defined(EXTI_PRIVCFGR1_PRIV0) - /* Privilege register set to default reset values */ - LL_EXTI_WriteReg(PRIVCFGR1, 0x00000000U); -#endif /* EXTI_PRIVCFGR1_PRIV0 */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - /* Secure register set to default reset values */ - LL_EXTI_WriteReg(SECCFGR1, 0x00000000U); -#endif /* __ARM_FEATURE_CMSE */ return SUCCESS; } diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rcc.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rcc.c index 49addc56d6..dfa271f71a 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rcc.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rcc.c @@ -557,7 +557,7 @@ uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) { case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */ #if defined(RCC_LSI2_SUPPORT) - if ((RCC->BDCR1& (RCC_BDCR1_LSI1ON | RCC_BDCR1_LSI2ON)) != 0U) + if ((RCC->BDCR1& (RCC_BDCR1_LSI1ON | RCC_BDCR1_LSI2ON)) != 0U) #else if (LL_RCC_LSI1_IsReady() != 0U) #endif @@ -597,7 +597,7 @@ uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) { case LL_RCC_LPTIM2_CLKSOURCE_LSI: /* LPTIM2 Clock is LSI Osc. */ #if defined(RCC_LSI2_SUPPORT) - if ((RCC->BDCR1& (RCC_BDCR1_LSI1ON | RCC_BDCR1_LSI2ON)) != 0U) + if ((RCC->BDCR1& (RCC_BDCR1_LSI1ON | RCC_BDCR1_LSI2ON)) != 0U) #else if (LL_RCC_LSI1_IsReady() != 0U) #endif @@ -733,7 +733,7 @@ uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource) case LL_RCC_RNG_CLKSOURCE_LSI: /* LSI clock used as RNG clock source */ #if defined(RCC_LSI2_SUPPORT) - if ((RCC->BDCR1& (RCC_BDCR1_LSI1ON | RCC_BDCR1_LSI2ON)) != 0U) + if ((RCC->BDCR1& (RCC_BDCR1_LSI1ON | RCC_BDCR1_LSI2ON)) != 0U) #else if (LL_RCC_LSI1_IsReady() != 0U) #endif diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rng.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rng.c index 9acccbf857..5c7fae44d6 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rng.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rng.c @@ -110,7 +110,7 @@ ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx) * - SUCCESS: RNG registers are initialized according to RNG_InitStruct content * - ERROR: not applicable */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct) +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct) { /* Check the parameters */ assert_param(IS_RNG_ALL_INSTANCE(RNGx)); diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_tim.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_tim.c index 801e1740ba..b280fb95af 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_tim.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_tim.c @@ -1337,7 +1337,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM * @} */ -#endif /* TIM1 || TIM2 || TIM3 || TIM6 || TIM7 */ +#endif /* TIM1 || TIM2 || TIM3 || TIM16 || TIM17 */ /** * @} diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index f80f46ba22..949125d1d2 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -18,7 +18,7 @@ * STM32MP1: 1.6.0 * STM32U5: 1.6.0 * STM32WB: 1.14.3 - * STM32WBA: 1.3.0 + * STM32WBA: 1.4.0 * STM32WL: 1.3.0 Release notes of each STM32YYxx HAL Drivers available here: From 673869b83ac10c9b531bb4fc816efdbb6ef5987e Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 19 Aug 2024 16:59:18 +0200 Subject: [PATCH 2/4] system(WBA): update STM32WBAxx CMSIS Drivers to v1.4.0 Included in STM32CubeWBA FW v1.4.1 Signed-off-by: Frederic Pillon --- .../ST/STM32WBAxx/Include/stm32wba50xx.h | 57 ++++++++------- .../ST/STM32WBAxx/Include/stm32wba52xx.h | 58 ++++++++------- .../ST/STM32WBAxx/Include/stm32wba54xx.h | 60 ++++++++------- .../ST/STM32WBAxx/Include/stm32wba55xx.h | 60 ++++++++------- .../Device/ST/STM32WBAxx/Include/stm32wbaxx.h | 2 +- .../Device/ST/STM32WBAxx/Release_Notes.html | 73 ++++++++++++++----- .../gcc/linker/STM32WBA50xx_FLASH.ld | 12 +-- .../Templates/gcc/linker/STM32WBA50xx_RAM.ld | 12 +-- .../gcc/linker/STM32WBA52xx_FLASH.ld | 12 +-- .../gcc/linker/STM32WBA52xx_FLASH_ns.ld | 12 +-- .../gcc/linker/STM32WBA52xx_FLASH_s.ld | 12 +-- .../Templates/gcc/linker/STM32WBA52xx_RAM.ld | 12 +-- .../gcc/linker/STM32WBA52xx_RAM_ns.ld | 12 +-- .../gcc/linker/STM32WBA52xx_RAM_s.ld | 12 +-- .../gcc/linker/STM32WBA54xx_FLASH.ld | 12 +-- .../gcc/linker/STM32WBA54xx_FLASH_ns.ld | 12 +-- .../gcc/linker/STM32WBA54xx_FLASH_s.ld | 12 +-- .../Templates/gcc/linker/STM32WBA54xx_RAM.ld | 12 +-- .../gcc/linker/STM32WBA54xx_RAM_ns.ld | 12 +-- .../gcc/linker/STM32WBA54xx_RAM_s.ld | 12 +-- .../gcc/linker/STM32WBA55xx_FLASH.ld | 12 +-- .../gcc/linker/STM32WBA55xx_FLASH_ns.ld | 12 +-- .../gcc/linker/STM32WBA55xx_FLASH_s.ld | 12 +-- .../Templates/gcc/linker/STM32WBA55xx_RAM.ld | 12 +-- .../gcc/linker/STM32WBA55xx_RAM_ns.ld | 12 +-- .../gcc/linker/STM32WBA55xx_RAM_s.ld | 12 +-- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 27 files changed, 320 insertions(+), 232 deletions(-) diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h index a7e35f80db..24a1a72994 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h @@ -253,14 +253,14 @@ typedef struct */ typedef struct { - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */ - __IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ - __IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ - __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ - uint32_t RESERVED1[4];/*!< Reserved, 0x14 - 0x20 */ - __IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */ - __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */ + __IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x14 - 0x20 */ + __IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */ } DBGMCU_TypeDef; /** @@ -617,11 +617,11 @@ typedef struct */ typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ uint32_t RESERVED; - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ } RNG_TypeDef; /* @@ -693,18 +693,18 @@ typedef struct */ typedef struct { - __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ - __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ - __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ - __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ - __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ - __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ - __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ - __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ - __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ - __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ - uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ - __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ } SYSCFG_TypeDef; /** @@ -4256,7 +4256,7 @@ typedef struct #define I2C_CR1_ADDRACLR_Pos (30U) #define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ #define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ -#define I2C_CR1_STOPFACLR_Pos (30U) +#define I2C_CR1_STOPFACLR_Pos (31U) #define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ #define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ @@ -4942,7 +4942,6 @@ typedef struct #define LPTIM_CCR2_CCR2_Msk (0xFFFFUL << LPTIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ #define LPTIM_CCR2_CCR2 LPTIM_CCR2_CCR2_Msk /*!< Compare register 2 */ - /******************************************************************************/ /* */ /* Public Key Accelerator (PKA) */ @@ -6669,6 +6668,9 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F02D00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) /******************************************************************************/ @@ -10293,7 +10295,8 @@ typedef struct /****************** TIM Instances : supporting OCxREF clear *******************/ #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ - ((INSTANCE) == TIM2_NS)) + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM16_NS)) /********* TIM Instances : supporting bitfield OCCS in SMCR register **********/ #define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h index b95d9163e3..b51658ff98 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h @@ -267,14 +267,14 @@ typedef struct */ typedef struct { - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */ - __IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ - __IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ - __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ - uint32_t RESERVED1[4];/*!< Reserved, 0x14 - 0x20 */ - __IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */ - __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */ + __IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x14 - 0x20 */ + __IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */ } DBGMCU_TypeDef; /** @@ -710,11 +710,11 @@ typedef struct */ typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ uint32_t RESERVED; - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ } RNG_TypeDef; /* @@ -787,18 +787,18 @@ typedef struct */ typedef struct { - __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ - __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ - __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ - __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ - __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ - __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ - __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ - __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ - __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ - __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ - uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ - __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ } SYSCFG_TypeDef; /** @@ -7856,7 +7856,7 @@ typedef struct #define I2C_CR1_ADDRACLR_Pos (30U) #define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ #define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ -#define I2C_CR1_STOPFACLR_Pos (30U) +#define I2C_CR1_STOPFACLR_Pos (31U) #define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ #define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ @@ -8542,7 +8542,6 @@ typedef struct #define LPTIM_CCR2_CCR2_Msk (0xFFFFUL << LPTIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ #define LPTIM_CCR2_CCR2 LPTIM_CCR2_CCR2_Msk /*!< Compare register 2 */ - /******************************************************************************/ /* */ /* Public Key Accelerator (PKA) */ @@ -10570,6 +10569,9 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F02D00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) /******************************************************************************/ @@ -14527,7 +14529,9 @@ typedef struct /****************** TIM Instances : supporting OCxREF clear *******************/ #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) /****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/ #define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h index b286ceb489..ec33cd994b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h @@ -284,14 +284,14 @@ typedef struct */ typedef struct { - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */ - __IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ - __IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ - __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ - uint32_t RESERVED1[4];/*!< Reserved, 0x14 - 0x20 */ - __IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */ - __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */ + __IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x14 - 0x20 */ + __IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */ } DBGMCU_TypeDef; /** @@ -749,11 +749,11 @@ typedef struct */ typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ uint32_t RESERVED; - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ } RNG_TypeDef; /* @@ -804,7 +804,7 @@ typedef struct typedef struct { __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ - uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ } SAI_TypeDef; @@ -849,18 +849,18 @@ typedef struct */ typedef struct { - __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ - __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ - __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ - __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ - __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ - __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ - __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ - __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ - __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ - __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ - uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ - __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ } SYSCFG_TypeDef; /** @@ -8090,7 +8090,7 @@ typedef struct #define I2C_CR1_ADDRACLR_Pos (30U) #define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ #define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ -#define I2C_CR1_STOPFACLR_Pos (30U) +#define I2C_CR1_STOPFACLR_Pos (31U) #define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ #define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ @@ -8776,7 +8776,6 @@ typedef struct #define LPTIM_CCR2_CCR2_Msk (0xFFFFUL << LPTIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ #define LPTIM_CCR2_CCR2 LPTIM_CCR2_CCR2_Msk /*!< Compare register 2 */ - /******************************************************************************/ /* */ /* Public Key Accelerator (PKA) */ @@ -10964,6 +10963,9 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F02D00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) /******************************************************************************/ @@ -15235,7 +15237,9 @@ typedef struct /****************** TIM Instances : supporting OCxREF clear *******************/ #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) /****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/ #define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h index 6f9850c513..05890e1b2a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h @@ -284,14 +284,14 @@ typedef struct */ typedef struct { - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */ - __IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ - __IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ - __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ - uint32_t RESERVED1[4];/*!< Reserved, 0x14 - 0x20 */ - __IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */ - __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */ + __IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x14 - 0x20 */ + __IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */ } DBGMCU_TypeDef; /** @@ -749,11 +749,11 @@ typedef struct */ typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ uint32_t RESERVED; - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ } RNG_TypeDef; /* @@ -804,7 +804,7 @@ typedef struct typedef struct { __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ - uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ } SAI_TypeDef; @@ -849,18 +849,18 @@ typedef struct */ typedef struct { - __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ - __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ - __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ - __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ - __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ - __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ - __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ - __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ - __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ - __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ - uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ - __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ } SYSCFG_TypeDef; /** @@ -8090,7 +8090,7 @@ typedef struct #define I2C_CR1_ADDRACLR_Pos (30U) #define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ #define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ -#define I2C_CR1_STOPFACLR_Pos (30U) +#define I2C_CR1_STOPFACLR_Pos (31U) #define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ #define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ @@ -8776,7 +8776,6 @@ typedef struct #define LPTIM_CCR2_CCR2_Msk (0xFFFFUL << LPTIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ #define LPTIM_CCR2_CCR2 LPTIM_CCR2_CCR2_Msk /*!< Compare register 2 */ - /******************************************************************************/ /* */ /* Public Key Accelerator (PKA) */ @@ -10982,6 +10981,9 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F02D00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) /******************************************************************************/ @@ -15253,7 +15255,9 @@ typedef struct /****************** TIM Instances : supporting OCxREF clear *******************/ #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) /****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/ #define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h index 975b686f75..5713869e8e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h @@ -79,7 +79,7 @@ * @brief CMSIS Device version number */ #define __STM32WBA_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WBA_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ +#define __STM32WBA_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ #define __STM32WBA_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WBA_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBA_CMSIS_VERSION ((__STM32WBA_CMSIS_VERSION_MAIN << 24U)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html index 461f337e15..8f716ba1a6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html @@ -30,7 +30,9 @@

                STM32WBAxx CMSIS

                Purpose

                This driver provides the CMSIS device for the STM32WBAxx products. This covers

                  +
                • STM32WBA50xx devices
                • STM32WBA52xx devices
                  • +
                • STM32WBA54xx devices
                • STM32WBA55xx devices

                This driver is composed of the description of the registers under “Include” directory.

                @@ -44,18 +46,18 @@

                Purpose

                Update History

                - +

                Main Changes

                -

                Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices

                +

                Official Release of STM32CubeWBA Firmware package supporting STM32WBA50xx, STM32WBA52xx, STM32WBA54xx and STM32WBA55xx devices

                Contents

                -

                Official Release of CMSIS devices drivers supporting STM32WBA52xx and STM32WBA55xx devices

                +

                Official Release of CMSIS devices drivers supporting STM32WBA50xx, STM32WBA52xx, STM32WBA54xx and STM32WBA55xx devices

                • Update CMSIS devices to include latest corrections
                    -
                  • Update IS_TIM_32B_COUNTER_INSTANCE macro to remove 16-bit counter TIM3
                    • -
                  • Update IS_TIM_OCXREF_CLEAR_INSTANCE macro as feature is supported by TIM16 and TIM17
                    • -
                  • Add IS_TIM_OCCS_INSTANCE macro for Secure context
                    • +
                  • Properly mark sections readonly for GCC
                    • +
                  • Add RNG (CR, HTCR) Nist Compliance Values
                    • +
                  • Update IS_TIM_OCXREF_CLEAR_INSTANCE macro to support of TIM16/TIM17


                @@ -75,18 +77,18 @@

                Notes

                - +

                Main Changes

                -

                Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices

                +

                Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices

                Contents

                -

                Official Release of CMSIS devices drivers supporting STM32WBA52xx and STM32WBA55xx devices

                +

                Official Release of CMSIS devices drivers supporting STM32WBA52xx and STM32WBA55xx devices

                • Update CMSIS devices to include latest corrections
                    -
                  • Add support of WKUP_S_IRQn and RCC_AUDIOSYNC_IRQn interrupts in CMSIS devices, startup_stm32wba5xxx.s and partition_stmwba5xxx.h files
                    • -
                  • Update Licensing header in partition_stm325xxx.h files based on partition_ARMCM33.h
                    • -
                  • Update declaration of g_pfnVectors size in gcc/startup_stm32wba5xxx.s files
                    • +
                  • Update IS_TIM_32B_COUNTER_INSTANCE macro to remove 16-bit counter TIM3
                    • +
                  • Update IS_TIM_OCXREF_CLEAR_INSTANCE macro as feature is supported by TIM16 and TIM17
                    • +
                  • Add IS_TIM_OCCS_INSTANCE macro for Secure context


                @@ -106,16 +108,18 @@

                Notes

                - +

                Main Changes

                -

                Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

                +

                Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices

                Contents

                -

                Official Release of CMSIS devices drivers supporting STM32WBA52xx devices

                +

                Official Release of CMSIS devices drivers supporting STM32WBA52xx and STM32WBA55xx devices

                • Update CMSIS devices to include latest corrections
                    -
                  • Align SAU region end address on Flash end address
                    • +
                  • Add support of WKUP_S_IRQn and RCC_AUDIOSYNC_IRQn interrupts in CMSIS devices, startup_stm32wba5xxx.s and partition_stmwba5xxx.h files
                    • +
                  • Update Licensing header in partition_stm325xxx.h files based on partition_ARMCM33.h
                    • +
                  • Update declaration of g_pfnVectors size in gcc/startup_stm32wba5xxx.s files


                @@ -135,17 +139,20 @@

                Notes

                - +

                Main Changes

                -

                First Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

                +

                Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

                Contents

                +

                Official Release of CMSIS devices drivers supporting STM32WBA52xx devices

                  -
                • First official release of CMSIS devices drivers +
                • Update CMSIS devices to include latest corrections
                    -
                  • Support of STM32WBA52xx devices
                    • +
                  • Align SAU region end address on Flash end address
                +


                +

                Known Limitations

                • None
                  • @@ -160,6 +167,32 @@

                  Notes

                +
                + +
                +

                Main Changes

                +

                First Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

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                Contents

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                • First official release of CMSIS devices drivers +
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                  • Support of STM32WBA52xx devices
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                Known Limitations

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                • None
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                Dependencies

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                • None
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                Notes

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                • None
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