diff --git a/CI/build/conf/cores_config.json b/CI/build/conf/cores_config.json index da8c02f958..69d96967cb 100644 --- a/CI/build/conf/cores_config.json +++ b/CI/build/conf/cores_config.json @@ -157,74 +157,73 @@ "GENERIC_G491MCSX", "GENERIC_G491MCTX", "GENERIC_G491MESX", "GENERIC_G491METX", "GENERIC_G491RCIX", "GENERIC_G491RCTX", "GENERIC_G491REIX", "GENERIC_G491RETX", "GENERIC_G491REYX", "GENERIC_G491VCTX", "GENERIC_G491VETX", "GENERIC_G4A1MESX", - "GENERIC_G4A1REIX", "GENERIC_G4A1RETX", "GENERIC_H563IIKXQ", "GENERIC_H563ZGTX", - "GENERIC_H563ZITX", "GENERIC_H723ZETX", "GENERIC_H723ZGTX", "GENERIC_H730ZBTX", - "GENERIC_H742IGKX", "GENERIC_H742IGTX", "GENERIC_H742IIKX", "GENERIC_H742IITX", - "GENERIC_H742VGHX", "GENERIC_H742VGTX", "GENERIC_H742VIHX", "GENERIC_H742VITX", - "GENERIC_H742ZGTX", "GENERIC_H742ZITX", "GENERIC_H743IGKX", "GENERIC_H743IGTX", - "GENERIC_H743IIKX", "GENERIC_H743IITX", "GENERIC_H743VGHX", "GENERIC_H743VGTX", - "GENERIC_H743VIHX", "GENERIC_H743VITX", "GENERIC_H743ZGTX", "GENERIC_H743ZITX", - "GENERIC_H747AGIX", "GENERIC_H747AIIX", "GENERIC_H747IGTX", "GENERIC_H747IITX", - "GENERIC_H750IBKX", "GENERIC_H750IBTX", "GENERIC_H750VBTX", "GENERIC_H750ZBTX", - "GENERIC_H753IIKX", "GENERIC_H753VIHX", "GENERIC_H753ZITX", "GENERIC_H757AIIX", - "GENERIC_L010F4PX", "GENERIC_L010K4TX", "GENERIC_L011D3PX", "GENERIC_L011D4PX", - "GENERIC_L011E3YX", "GENERIC_L011F3PX", "GENERIC_L011F3UX", "GENERIC_L011F4PX", - "GENERIC_L011F4UX", "GENERIC_L011G3UX", "GENERIC_L011G4UX", "GENERIC_L011K3TX", - "GENERIC_L011K3UX", "GENERIC_L011K4TX", "GENERIC_L011K4UX", "GENERIC_L031C4TX", - "GENERIC_L031C4UX", "GENERIC_L031C6TX", "GENERIC_L031C6UX", "GENERIC_L031E4YX", - "GENERIC_L031E6YX", "GENERIC_L031F4PX", "GENERIC_L031F6PX", "GENERIC_L031G4UX", - "GENERIC_L031G6UX", "GENERIC_L031K4TX", "GENERIC_L031K6TX", "GENERIC_L041C4TX", - "GENERIC_L041C6TX", "GENERIC_L051C6TX", "GENERIC_L051C6UX", "GENERIC_L051C8TX", - "GENERIC_L052C6TX", "GENERIC_L052C6UX", "GENERIC_L052C8TX", "GENERIC_L052C8UX", - "GENERIC_L052K6TX", "GENERIC_L052K8TX", "GENERIC_L052R6HX", "GENERIC_L052R6TX", - "GENERIC_L052R8HX", "GENERIC_L052R8TX", "GENERIC_L052T6YX", "GENERIC_L052T8YX", - "GENERIC_L053C6TX", "GENERIC_L053C6UX", "GENERIC_L053C8TX", "GENERIC_L053C8UX", - "GENERIC_L053R6HX", "GENERIC_L053R6TX", "GENERIC_L053R8TX", "GENERIC_L062C8UX", - "GENERIC_L063C8TX", "GENERIC_L072CBTX", "GENERIC_L072CBUX", "GENERIC_L072CBYX", - "GENERIC_L072CZEX", "GENERIC_L072CZTX", "GENERIC_L072CZUX", "GENERIC_L072CZYX", - "GENERIC_L072KBTX", "GENERIC_L072KBUX", "GENERIC_L072KZTX", "GENERIC_L072KZUX", - "GENERIC_L072RBHX", "GENERIC_L072RBIX", "GENERIC_L072RBTX", "GENERIC_L072RZHX", - "GENERIC_L072RZIX", "GENERIC_L072RZTX", "GENERIC_L072V8IX", "GENERIC_L072V8TX", - "GENERIC_L072VBIX", "GENERIC_L072VBTX", "GENERIC_L072VZIX", "GENERIC_L072VZTX", - "GENERIC_L073CBTX", "GENERIC_L073CBUX", "GENERIC_L073CZTX", "GENERIC_L073CZUX", - "GENERIC_L073CZYX", "GENERIC_L073RBHX", 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"GENERIC_L152CBUX", "GENERIC_L152RETX", - "GENERIC_L152ZDTX", "GENERIC_L412K8TX", "GENERIC_L412K8UX", "GENERIC_L412KBTX", - "GENERIC_L412KBUX", "GENERIC_L422KBTX", "GENERIC_L431RBIX", "GENERIC_L431RBTX", - "GENERIC_L431RBYX", "GENERIC_L431RCIX", "GENERIC_L431RCTX", "GENERIC_L432KBUX", - "GENERIC_L432KCUX", "GENERIC_L433CBTX", "GENERIC_L433CBUX", "GENERIC_L433CCTX", - "GENERIC_L433CCUX", "GENERIC_L433RBIX", "GENERIC_L433RBTX", "GENERIC_L433RBYX", - "GENERIC_L433RCIX", "GENERIC_L433RCTX", "GENERIC_L433RCYX", "GENERIC_L443CCTX", - "GENERIC_L443RCIX", "GENERIC_L443RCTX", "GENERIC_L452RCIX", "GENERIC_L452RCTX", - "GENERIC_L452RCYX", "GENERIC_L452REIX", "GENERIC_L452RETX", "GENERIC_L452REYX", - "GENERIC_L452REYXP", "GENERIC_L462REIX", "GENERIC_L462RETX", "GENERIC_L475RCTX", - "GENERIC_L475RETX", "GENERIC_L475RGTX", "GENERIC_L475VCTX", "GENERIC_L475VETX", - "GENERIC_L475VGTX", "GENERIC_L476RCTX", "GENERIC_L476RETX", "GENERIC_L476RGTX", - "GENERIC_L476VCTX", "GENERIC_L476VETX", "GENERIC_L476VGTX", "GENERIC_L496ZETX", - "GENERIC_L496ZGTX", "GENERIC_L496ZGTXP", "GENERIC_L4R5VGTX", "GENERIC_L4R5VITX", - "GENERIC_L4R5ZGTX", "GENERIC_L4R5ZGYX", "GENERIC_L4R5ZITX", "GENERIC_L4R5ZIYX", - "GENERIC_L4R7VITX", "GENERIC_L4R7ZITX", "GENERIC_L4R9ZGJX", "GENERIC_L4R9ZGYX", - "GENERIC_L4R9ZIJX", "GENERIC_L4R9ZIYX", "GENERIC_L4S5VITX", "GENERIC_L4S5ZITX", - "GENERIC_L4S5ZIYX", "GENERIC_L552ZCTXQ", "GENERIC_L552ZETXQ", "GENERIC_MP153AACX", - "GENERIC_MP153CACX", "GENERIC_MP153DACX", "GENERIC_MP153FACX", "GENERIC_MP157AACX", - "GENERIC_MP157CACX", "GENERIC_MP157DACX", "GENERIC_U575AGIXQ", "GENERIC_U575AIIXQ", - "GENERIC_U575ZGTXQ", "GENERIC_U575ZITXQ", "GENERIC_WB35CCUXA", "GENERIC_WB35CEUXA", - "GENERIC_WB55CCUX", "GENERIC_WB55CEUX", "GENERIC_WB55RCVX", "GENERIC_WB55REVX", - "GENERIC_WL54CCUX", "GENERIC_WL54JCIX", "GENERIC_WL55CCUX", "GENERIC_WL55JCIX", - "GENERIC_WLE4C8UX", "GENERIC_WLE4CBUX", "GENERIC_WLE4CCUX", "GENERIC_WLE4J8IX", - "GENERIC_WLE4JBIX", "GENERIC_WLE4JCIX", "GENERIC_WLE5C8UX", "GENERIC_WLE5CBUX", - "GENERIC_WLE5J8IX", "GENERIC_WLE5JBIX", + "GENERIC_G4A1REIX", "GENERIC_G4A1RETX", "GENERIC_H563ZGTX", "GENERIC_H723ZETX", + "GENERIC_H723ZGTX", "GENERIC_H730ZBTX", "GENERIC_H742IGKX", "GENERIC_H742IGTX", + "GENERIC_H742IIKX", "GENERIC_H742IITX", "GENERIC_H742VGHX", "GENERIC_H742VGTX", + "GENERIC_H742VIHX", "GENERIC_H742VITX", "GENERIC_H742ZGTX", "GENERIC_H742ZITX", + "GENERIC_H743IGKX", "GENERIC_H743IGTX", "GENERIC_H743IIKX", "GENERIC_H743IITX", + "GENERIC_H743VGHX", "GENERIC_H743VGTX", "GENERIC_H743VIHX", "GENERIC_H743VITX", + "GENERIC_H743ZGTX", "GENERIC_H743ZITX", "GENERIC_H747AGIX", "GENERIC_H747AIIX", + "GENERIC_H747IGTX", "GENERIC_H747IITX", "GENERIC_H750IBKX", "GENERIC_H750IBTX", + "GENERIC_H750VBTX", "GENERIC_H750ZBTX", "GENERIC_H753IIKX", "GENERIC_H753VIHX", + "GENERIC_H753ZITX", "GENERIC_H757AIIX", "GENERIC_L010F4PX", "GENERIC_L010K4TX", + "GENERIC_L011D3PX", "GENERIC_L011D4PX", "GENERIC_L011E3YX", "GENERIC_L011F3PX", + "GENERIC_L011F3UX", "GENERIC_L011F4PX", "GENERIC_L011F4UX", "GENERIC_L011G3UX", + "GENERIC_L011G4UX", "GENERIC_L011K3TX", "GENERIC_L011K3UX", "GENERIC_L011K4TX", + "GENERIC_L011K4UX", "GENERIC_L031C4TX", "GENERIC_L031C4UX", "GENERIC_L031C6TX", + "GENERIC_L031C6UX", "GENERIC_L031E4YX", "GENERIC_L031E6YX", "GENERIC_L031F4PX", + "GENERIC_L031F6PX", "GENERIC_L031G4UX", "GENERIC_L031G6UX", "GENERIC_L031K4TX", + "GENERIC_L031K6TX", "GENERIC_L041C4TX", "GENERIC_L041C6TX", "GENERIC_L051C6TX", + "GENERIC_L051C6UX", "GENERIC_L051C8TX", "GENERIC_L052C6TX", "GENERIC_L052C6UX", + "GENERIC_L052C8TX", "GENERIC_L052C8UX", "GENERIC_L052K6TX", "GENERIC_L052K8TX", + "GENERIC_L052R6HX", "GENERIC_L052R6TX", "GENERIC_L052R8HX", "GENERIC_L052R8TX", + "GENERIC_L052T6YX", "GENERIC_L052T8YX", "GENERIC_L053C6TX", "GENERIC_L053C6UX", + "GENERIC_L053C8TX", "GENERIC_L053C8UX", "GENERIC_L053R6HX", "GENERIC_L053R6TX", + "GENERIC_L053R8TX", "GENERIC_L062C8UX", "GENERIC_L063C8TX", "GENERIC_L072CBTX", + "GENERIC_L072CBUX", "GENERIC_L072CBYX", "GENERIC_L072CZEX", "GENERIC_L072CZTX", + "GENERIC_L072CZUX", "GENERIC_L072CZYX", "GENERIC_L072KBTX", "GENERIC_L072KBUX", + "GENERIC_L072KZTX", "GENERIC_L072KZUX", "GENERIC_L072RBHX", "GENERIC_L072RBIX", + "GENERIC_L072RBTX", "GENERIC_L072RZHX", "GENERIC_L072RZIX", "GENERIC_L072RZTX", + "GENERIC_L072V8IX", "GENERIC_L072V8TX", "GENERIC_L072VBIX", "GENERIC_L072VBTX", + "GENERIC_L072VZIX", "GENERIC_L072VZTX", "GENERIC_L073CBTX", "GENERIC_L073CBUX", + "GENERIC_L073CZTX", "GENERIC_L073CZUX", "GENERIC_L073CZYX", "GENERIC_L073RBHX", + "GENERIC_L073RBTX", "GENERIC_L073RZHX", "GENERIC_L073RZIX", "GENERIC_L073RZTX", + "GENERIC_L073V8IX", "GENERIC_L073V8TX", "GENERIC_L073VBIX", "GENERIC_L073VBTX", + "GENERIC_L073VZIX", "GENERIC_L073VZTX", "GENERIC_L082CZUX", "GENERIC_L082KBTX", + "GENERIC_L082KBUX", "GENERIC_L083CBTX", "GENERIC_L083CZTX", "GENERIC_L083RBHX", + "GENERIC_L083RBTX", "GENERIC_L083V8IX", "GENERIC_L083VBIX", "GENERIC_L083VBTX", + "GENERIC_L083VZIX", "GENERIC_L083VZTX", "GENERIC_L100C6UX", "GENERIC_L100C6UXA", + "GENERIC_L151C6TX", "GENERIC_L151C6TXA", "GENERIC_L151C6UX", "GENERIC_L151C6UXA", + "GENERIC_L151C8TX", "GENERIC_L151C8TXA", "GENERIC_L151C8UX", "GENERIC_L151C8UXA", + "GENERIC_L151CBTX", "GENERIC_L151CBTXA", "GENERIC_L151CBUX", "GENERIC_L151CBUXA", + "GENERIC_L151RETX", "GENERIC_L151ZDTX", "GENERIC_L152C6TX", "GENERIC_L152C6TXA", + "GENERIC_L152C6UX", "GENERIC_L152C6UXA", "GENERIC_L152C8TX", "GENERIC_L152C8TXA", + "GENERIC_L152C8UX", "GENERIC_L152C8UXA", "GENERIC_L152CBTX", "GENERIC_L152CBTXA", + "GENERIC_L152CBUX", "GENERIC_L152RETX", "GENERIC_L152ZDTX", "GENERIC_L412K8TX", + "GENERIC_L412K8UX", "GENERIC_L412KBTX", "GENERIC_L412KBUX", "GENERIC_L422KBTX", + "GENERIC_L431RBIX", "GENERIC_L431RBTX", "GENERIC_L431RBYX", "GENERIC_L431RCIX", + "GENERIC_L431RCTX", "GENERIC_L432KBUX", "GENERIC_L432KCUX", "GENERIC_L433CBTX", + "GENERIC_L433CBUX", "GENERIC_L433CCTX", "GENERIC_L433CCUX", "GENERIC_L433RBIX", + "GENERIC_L433RBTX", "GENERIC_L433RBYX", "GENERIC_L433RCIX", "GENERIC_L433RCTX", + "GENERIC_L433RCYX", "GENERIC_L443CCTX", "GENERIC_L443RCIX", "GENERIC_L443RCTX", + "GENERIC_L452RCIX", "GENERIC_L452RCTX", "GENERIC_L452RCYX", "GENERIC_L452REIX", + "GENERIC_L452RETX", "GENERIC_L452REYX", "GENERIC_L452REYXP", "GENERIC_L462REIX", + "GENERIC_L462RETX", "GENERIC_L475RCTX", "GENERIC_L475RETX", "GENERIC_L475RGTX", + "GENERIC_L475VCTX", "GENERIC_L475VETX", "GENERIC_L475VGTX", "GENERIC_L476RCTX", + "GENERIC_L476RETX", "GENERIC_L476RGTX", "GENERIC_L476VCTX", "GENERIC_L476VETX", + "GENERIC_L476VGTX", "GENERIC_L496ZETX", "GENERIC_L496ZGTX", "GENERIC_L496ZGTXP", + "GENERIC_L4R5VGTX", "GENERIC_L4R5VITX", "GENERIC_L4R5ZGTX", "GENERIC_L4R5ZGYX", + "GENERIC_L4R5ZITX", "GENERIC_L4R5ZIYX", "GENERIC_L4R7VITX", "GENERIC_L4R7ZITX", + "GENERIC_L4R9ZGJX", "GENERIC_L4R9ZGYX", "GENERIC_L4R9ZIJX", "GENERIC_L4R9ZIYX", + "GENERIC_L4S5VITX", "GENERIC_L4S5ZITX", "GENERIC_L4S5ZIYX", "GENERIC_L552ZCTXQ", + "GENERIC_L552ZETXQ", "GENERIC_MP153AACX", "GENERIC_MP153CACX", "GENERIC_MP153DACX", + "GENERIC_MP153FACX", "GENERIC_MP157AACX", "GENERIC_MP157CACX", "GENERIC_MP157DACX", + "GENERIC_U575AGIXQ", "GENERIC_U575AIIXQ", "GENERIC_U575ZGTXQ", "GENERIC_U575ZITXQ", + "GENERIC_WB35CCUXA", "GENERIC_WB35CEUXA", "GENERIC_WB55CCUX", "GENERIC_WB55CEUX", + "GENERIC_WB55RCVX", "GENERIC_WB55REVX", "GENERIC_WL54CCUX", "GENERIC_WL54JCIX", + "GENERIC_WL55CCUX", "GENERIC_WL55JCIX", "GENERIC_WLE4C8UX", "GENERIC_WLE4CBUX", + "GENERIC_WLE4CCUX", "GENERIC_WLE4J8IX", "GENERIC_WLE4JBIX", "GENERIC_WLE4JCIX", + "GENERIC_WLE5C8UX", "GENERIC_WLE5CBUX", "GENERIC_WLE5J8IX", "GENERIC_WLE5JBIX", "NUCLEO_H743ZI", "NUCLEO_L496ZG", "NUCLEO_L4R5ZI", diff --git a/CI/build/conf/cores_config_ci.json b/CI/build/conf/cores_config_ci.json index c921f6d550..b6afe92454 100644 --- a/CI/build/conf/cores_config_ci.json +++ b/CI/build/conf/cores_config_ci.json @@ -156,74 +156,73 @@ "GENERIC_G491MCSX", "GENERIC_G491MCTX", "GENERIC_G491MESX", "GENERIC_G491METX", "GENERIC_G491RCIX", "GENERIC_G491RCTX", "GENERIC_G491REIX", "GENERIC_G491RETX", "GENERIC_G491REYX", "GENERIC_G491VCTX", "GENERIC_G491VETX", "GENERIC_G4A1MESX", - "GENERIC_G4A1REIX", "GENERIC_G4A1RETX", "GENERIC_H563IIKXQ", "GENERIC_H563ZGTX", - "GENERIC_H563ZITX", "GENERIC_H723ZETX", "GENERIC_H723ZGTX", "GENERIC_H730ZBTX", - "GENERIC_H742IGKX", "GENERIC_H742IGTX", "GENERIC_H742IIKX", "GENERIC_H742IITX", - "GENERIC_H742VGHX", "GENERIC_H742VGTX", "GENERIC_H742VIHX", "GENERIC_H742VITX", - "GENERIC_H742ZGTX", "GENERIC_H742ZITX", "GENERIC_H743IGKX", "GENERIC_H743IGTX", - "GENERIC_H743IIKX", "GENERIC_H743IITX", "GENERIC_H743VGHX", "GENERIC_H743VGTX", - "GENERIC_H743VIHX", "GENERIC_H743VITX", "GENERIC_H743ZGTX", "GENERIC_H743ZITX", - "GENERIC_H747AGIX", "GENERIC_H747AIIX", "GENERIC_H747IGTX", "GENERIC_H747IITX", - "GENERIC_H750IBKX", "GENERIC_H750IBTX", "GENERIC_H750VBTX", "GENERIC_H750ZBTX", - "GENERIC_H753IIKX", "GENERIC_H753VIHX", "GENERIC_H753ZITX", "GENERIC_H757AIIX", - "GENERIC_L010F4PX", "GENERIC_L010K4TX", "GENERIC_L011D3PX", "GENERIC_L011D4PX", - "GENERIC_L011E3YX", "GENERIC_L011F3PX", "GENERIC_L011F3UX", "GENERIC_L011F4PX", - "GENERIC_L011F4UX", "GENERIC_L011G3UX", "GENERIC_L011G4UX", "GENERIC_L011K3TX", - "GENERIC_L011K3UX", "GENERIC_L011K4TX", "GENERIC_L011K4UX", "GENERIC_L031C4TX", - "GENERIC_L031C4UX", "GENERIC_L031C6TX", "GENERIC_L031C6UX", "GENERIC_L031E4YX", - "GENERIC_L031E6YX", "GENERIC_L031F4PX", "GENERIC_L031F6PX", "GENERIC_L031G4UX", - "GENERIC_L031G6UX", "GENERIC_L031K4TX", "GENERIC_L031K6TX", "GENERIC_L041C4TX", - "GENERIC_L041C6TX", "GENERIC_L051C6TX", "GENERIC_L051C6UX", "GENERIC_L051C8TX", - "GENERIC_L052C6TX", "GENERIC_L052C6UX", "GENERIC_L052C8TX", "GENERIC_L052C8UX", - "GENERIC_L052K6TX", "GENERIC_L052K8TX", "GENERIC_L052R6HX", "GENERIC_L052R6TX", - "GENERIC_L052R8HX", "GENERIC_L052R8TX", "GENERIC_L052T6YX", "GENERIC_L052T8YX", - "GENERIC_L053C6TX", "GENERIC_L053C6UX", "GENERIC_L053C8TX", "GENERIC_L053C8UX", - "GENERIC_L053R6HX", "GENERIC_L053R6TX", "GENERIC_L053R8TX", "GENERIC_L062C8UX", - "GENERIC_L063C8TX", "GENERIC_L072CBTX", "GENERIC_L072CBUX", "GENERIC_L072CBYX", - "GENERIC_L072CZEX", "GENERIC_L072CZTX", "GENERIC_L072CZUX", "GENERIC_L072CZYX", - "GENERIC_L072KBTX", "GENERIC_L072KBUX", "GENERIC_L072KZTX", "GENERIC_L072KZUX", - "GENERIC_L072RBHX", "GENERIC_L072RBIX", "GENERIC_L072RBTX", "GENERIC_L072RZHX", - "GENERIC_L072RZIX", "GENERIC_L072RZTX", "GENERIC_L072V8IX", "GENERIC_L072V8TX", - "GENERIC_L072VBIX", "GENERIC_L072VBTX", "GENERIC_L072VZIX", "GENERIC_L072VZTX", - "GENERIC_L073CBTX", "GENERIC_L073CBUX", "GENERIC_L073CZTX", "GENERIC_L073CZUX", - "GENERIC_L073CZYX", "GENERIC_L073RBHX", "GENERIC_L073RBTX", "GENERIC_L073RZHX", - "GENERIC_L073RZIX", "GENERIC_L073RZTX", "GENERIC_L073V8IX", "GENERIC_L073V8TX", - "GENERIC_L073VBIX", "GENERIC_L073VBTX", "GENERIC_L073VZIX", "GENERIC_L073VZTX", - "GENERIC_L082CZUX", "GENERIC_L082KBTX", "GENERIC_L082KBUX", "GENERIC_L083CBTX", - "GENERIC_L083CZTX", "GENERIC_L083RBHX", "GENERIC_L083RBTX", "GENERIC_L083V8IX", - "GENERIC_L083VBIX", "GENERIC_L083VBTX", "GENERIC_L083VZIX", "GENERIC_L083VZTX", - "GENERIC_L100C6UX", "GENERIC_L100C6UXA", "GENERIC_L151C6TX", "GENERIC_L151C6TXA", - "GENERIC_L151C6UX", "GENERIC_L151C6UXA", "GENERIC_L151C8TX", "GENERIC_L151C8TXA", - "GENERIC_L151C8UX", "GENERIC_L151C8UXA", "GENERIC_L151CBTX", "GENERIC_L151CBTXA", - "GENERIC_L151CBUX", "GENERIC_L151CBUXA", "GENERIC_L151RETX", "GENERIC_L151ZDTX", - "GENERIC_L152C6TX", "GENERIC_L152C6TXA", "GENERIC_L152C6UX", "GENERIC_L152C6UXA", - "GENERIC_L152C8TX", "GENERIC_L152C8TXA", "GENERIC_L152C8UX", "GENERIC_L152C8UXA", - "GENERIC_L152CBTX", "GENERIC_L152CBTXA", "GENERIC_L152CBUX", "GENERIC_L152RETX", - "GENERIC_L152ZDTX", "GENERIC_L412K8TX", "GENERIC_L412K8UX", "GENERIC_L412KBTX", - "GENERIC_L412KBUX", "GENERIC_L422KBTX", "GENERIC_L431RBIX", "GENERIC_L431RBTX", - "GENERIC_L431RBYX", "GENERIC_L431RCIX", "GENERIC_L431RCTX", "GENERIC_L432KBUX", - "GENERIC_L432KCUX", "GENERIC_L433CBTX", "GENERIC_L433CBUX", "GENERIC_L433CCTX", - "GENERIC_L433CCUX", "GENERIC_L433RBIX", "GENERIC_L433RBTX", "GENERIC_L433RBYX", - "GENERIC_L433RCIX", "GENERIC_L433RCTX", "GENERIC_L433RCYX", "GENERIC_L443CCTX", - "GENERIC_L443RCIX", "GENERIC_L443RCTX", "GENERIC_L452RCIX", "GENERIC_L452RCTX", - "GENERIC_L452RCYX", "GENERIC_L452REIX", "GENERIC_L452RETX", "GENERIC_L452REYX", - "GENERIC_L452REYXP", "GENERIC_L462REIX", "GENERIC_L462RETX", "GENERIC_L475RCTX", - "GENERIC_L475RETX", "GENERIC_L475RGTX", "GENERIC_L475VCTX", "GENERIC_L475VETX", - "GENERIC_L475VGTX", "GENERIC_L476RCTX", "GENERIC_L476RETX", "GENERIC_L476RGTX", - "GENERIC_L476VCTX", "GENERIC_L476VETX", "GENERIC_L476VGTX", "GENERIC_L496ZETX", - "GENERIC_L496ZGTX", "GENERIC_L496ZGTXP", "GENERIC_L4R5VGTX", "GENERIC_L4R5VITX", - "GENERIC_L4R5ZGTX", "GENERIC_L4R5ZGYX", "GENERIC_L4R5ZITX", "GENERIC_L4R5ZIYX", - "GENERIC_L4R7VITX", "GENERIC_L4R7ZITX", "GENERIC_L4R9ZGJX", "GENERIC_L4R9ZGYX", - "GENERIC_L4R9ZIJX", "GENERIC_L4R9ZIYX", "GENERIC_L4S5VITX", "GENERIC_L4S5ZITX", - "GENERIC_L4S5ZIYX", "GENERIC_L552ZCTXQ", "GENERIC_L552ZETXQ", "GENERIC_MP153AACX", - "GENERIC_MP153CACX", "GENERIC_MP153DACX", "GENERIC_MP153FACX", "GENERIC_MP157AACX", - "GENERIC_MP157CACX", "GENERIC_MP157DACX", "GENERIC_U575AGIXQ", "GENERIC_U575AIIXQ", - "GENERIC_U575ZGTXQ", "GENERIC_U575ZITXQ", "GENERIC_WB35CCUXA", "GENERIC_WB35CEUXA", - "GENERIC_WB55CCUX", "GENERIC_WB55CEUX", "GENERIC_WB55RCVX", "GENERIC_WB55REVX", - "GENERIC_WL54CCUX", "GENERIC_WL54JCIX", "GENERIC_WL55CCUX", "GENERIC_WL55JCIX", - "GENERIC_WLE4C8UX", "GENERIC_WLE4CBUX", "GENERIC_WLE4CCUX", "GENERIC_WLE4J8IX", - "GENERIC_WLE4JBIX", "GENERIC_WLE4JCIX", "GENERIC_WLE5C8UX", "GENERIC_WLE5CBUX", - "GENERIC_WLE5J8IX", "GENERIC_WLE5JBIX", + "GENERIC_G4A1REIX", "GENERIC_G4A1RETX", "GENERIC_H563ZGTX", "GENERIC_H723ZETX", + "GENERIC_H723ZGTX", "GENERIC_H730ZBTX", "GENERIC_H742IGKX", "GENERIC_H742IGTX", + "GENERIC_H742IIKX", "GENERIC_H742IITX", "GENERIC_H742VGHX", "GENERIC_H742VGTX", + "GENERIC_H742VIHX", "GENERIC_H742VITX", "GENERIC_H742ZGTX", "GENERIC_H742ZITX", + "GENERIC_H743IGKX", "GENERIC_H743IGTX", "GENERIC_H743IIKX", "GENERIC_H743IITX", + "GENERIC_H743VGHX", "GENERIC_H743VGTX", "GENERIC_H743VIHX", "GENERIC_H743VITX", + "GENERIC_H743ZGTX", "GENERIC_H743ZITX", "GENERIC_H747AGIX", "GENERIC_H747AIIX", + "GENERIC_H747IGTX", "GENERIC_H747IITX", "GENERIC_H750IBKX", "GENERIC_H750IBTX", + "GENERIC_H750VBTX", "GENERIC_H750ZBTX", "GENERIC_H753IIKX", "GENERIC_H753VIHX", + "GENERIC_H753ZITX", "GENERIC_H757AIIX", "GENERIC_L010F4PX", "GENERIC_L010K4TX", + "GENERIC_L011D3PX", "GENERIC_L011D4PX", "GENERIC_L011E3YX", "GENERIC_L011F3PX", + "GENERIC_L011F3UX", "GENERIC_L011F4PX", "GENERIC_L011F4UX", "GENERIC_L011G3UX", + "GENERIC_L011G4UX", "GENERIC_L011K3TX", "GENERIC_L011K3UX", "GENERIC_L011K4TX", + "GENERIC_L011K4UX", "GENERIC_L031C4TX", "GENERIC_L031C4UX", "GENERIC_L031C6TX", + "GENERIC_L031C6UX", "GENERIC_L031E4YX", "GENERIC_L031E6YX", "GENERIC_L031F4PX", + "GENERIC_L031F6PX", "GENERIC_L031G4UX", "GENERIC_L031G6UX", "GENERIC_L031K4TX", + "GENERIC_L031K6TX", "GENERIC_L041C4TX", "GENERIC_L041C6TX", "GENERIC_L051C6TX", + "GENERIC_L051C6UX", "GENERIC_L051C8TX", "GENERIC_L052C6TX", "GENERIC_L052C6UX", + "GENERIC_L052C8TX", "GENERIC_L052C8UX", "GENERIC_L052K6TX", "GENERIC_L052K8TX", + "GENERIC_L052R6HX", "GENERIC_L052R6TX", "GENERIC_L052R8HX", "GENERIC_L052R8TX", + "GENERIC_L052T6YX", "GENERIC_L052T8YX", "GENERIC_L053C6TX", "GENERIC_L053C6UX", + "GENERIC_L053C8TX", "GENERIC_L053C8UX", "GENERIC_L053R6HX", "GENERIC_L053R6TX", + "GENERIC_L053R8TX", "GENERIC_L062C8UX", "GENERIC_L063C8TX", "GENERIC_L072CBTX", + "GENERIC_L072CBUX", "GENERIC_L072CBYX", "GENERIC_L072CZEX", "GENERIC_L072CZTX", + "GENERIC_L072CZUX", "GENERIC_L072CZYX", "GENERIC_L072KBTX", "GENERIC_L072KBUX", + "GENERIC_L072KZTX", "GENERIC_L072KZUX", "GENERIC_L072RBHX", "GENERIC_L072RBIX", + "GENERIC_L072RBTX", "GENERIC_L072RZHX", "GENERIC_L072RZIX", "GENERIC_L072RZTX", + "GENERIC_L072V8IX", "GENERIC_L072V8TX", "GENERIC_L072VBIX", "GENERIC_L072VBTX", + "GENERIC_L072VZIX", "GENERIC_L072VZTX", "GENERIC_L073CBTX", "GENERIC_L073CBUX", + "GENERIC_L073CZTX", "GENERIC_L073CZUX", "GENERIC_L073CZYX", "GENERIC_L073RBHX", + "GENERIC_L073RBTX", "GENERIC_L073RZHX", "GENERIC_L073RZIX", "GENERIC_L073RZTX", + "GENERIC_L073V8IX", "GENERIC_L073V8TX", "GENERIC_L073VBIX", "GENERIC_L073VBTX", + "GENERIC_L073VZIX", "GENERIC_L073VZTX", "GENERIC_L082CZUX", "GENERIC_L082KBTX", + "GENERIC_L082KBUX", "GENERIC_L083CBTX", "GENERIC_L083CZTX", "GENERIC_L083RBHX", + "GENERIC_L083RBTX", "GENERIC_L083V8IX", "GENERIC_L083VBIX", "GENERIC_L083VBTX", + "GENERIC_L083VZIX", "GENERIC_L083VZTX", "GENERIC_L100C6UX", "GENERIC_L100C6UXA", + "GENERIC_L151C6TX", "GENERIC_L151C6TXA", "GENERIC_L151C6UX", "GENERIC_L151C6UXA", + "GENERIC_L151C8TX", "GENERIC_L151C8TXA", "GENERIC_L151C8UX", "GENERIC_L151C8UXA", + "GENERIC_L151CBTX", "GENERIC_L151CBTXA", "GENERIC_L151CBUX", "GENERIC_L151CBUXA", + "GENERIC_L151RETX", "GENERIC_L151ZDTX", "GENERIC_L152C6TX", "GENERIC_L152C6TXA", + "GENERIC_L152C6UX", "GENERIC_L152C6UXA", "GENERIC_L152C8TX", "GENERIC_L152C8TXA", + "GENERIC_L152C8UX", "GENERIC_L152C8UXA", "GENERIC_L152CBTX", "GENERIC_L152CBTXA", + "GENERIC_L152CBUX", "GENERIC_L152RETX", "GENERIC_L152ZDTX", "GENERIC_L412K8TX", + "GENERIC_L412K8UX", "GENERIC_L412KBTX", "GENERIC_L412KBUX", "GENERIC_L422KBTX", + "GENERIC_L431RBIX", "GENERIC_L431RBTX", "GENERIC_L431RBYX", "GENERIC_L431RCIX", + "GENERIC_L431RCTX", "GENERIC_L432KBUX", "GENERIC_L432KCUX", "GENERIC_L433CBTX", + "GENERIC_L433CBUX", "GENERIC_L433CCTX", "GENERIC_L433CCUX", "GENERIC_L433RBIX", + "GENERIC_L433RBTX", "GENERIC_L433RBYX", "GENERIC_L433RCIX", "GENERIC_L433RCTX", + "GENERIC_L433RCYX", "GENERIC_L443CCTX", "GENERIC_L443RCIX", "GENERIC_L443RCTX", + "GENERIC_L452RCIX", "GENERIC_L452RCTX", "GENERIC_L452RCYX", "GENERIC_L452REIX", + "GENERIC_L452RETX", "GENERIC_L452REYX", "GENERIC_L452REYXP", "GENERIC_L462REIX", + "GENERIC_L462RETX", "GENERIC_L475RCTX", "GENERIC_L475RETX", "GENERIC_L475RGTX", + "GENERIC_L475VCTX", "GENERIC_L475VETX", "GENERIC_L475VGTX", "GENERIC_L476RCTX", + "GENERIC_L476RETX", "GENERIC_L476RGTX", "GENERIC_L476VCTX", "GENERIC_L476VETX", + "GENERIC_L476VGTX", "GENERIC_L496ZETX", "GENERIC_L496ZGTX", "GENERIC_L496ZGTXP", + "GENERIC_L4R5VGTX", "GENERIC_L4R5VITX", "GENERIC_L4R5ZGTX", "GENERIC_L4R5ZGYX", + "GENERIC_L4R5ZITX", "GENERIC_L4R5ZIYX", "GENERIC_L4R7VITX", "GENERIC_L4R7ZITX", + "GENERIC_L4R9ZGJX", "GENERIC_L4R9ZGYX", "GENERIC_L4R9ZIJX", "GENERIC_L4R9ZIYX", + "GENERIC_L4S5VITX", "GENERIC_L4S5ZITX", "GENERIC_L4S5ZIYX", "GENERIC_L552ZCTXQ", + "GENERIC_L552ZETXQ", "GENERIC_MP153AACX", "GENERIC_MP153CACX", "GENERIC_MP153DACX", + "GENERIC_MP153FACX", "GENERIC_MP157AACX", "GENERIC_MP157CACX", "GENERIC_MP157DACX", + "GENERIC_U575AGIXQ", "GENERIC_U575AIIXQ", "GENERIC_U575ZGTXQ", "GENERIC_U575ZITXQ", + "GENERIC_WB35CCUXA", "GENERIC_WB35CEUXA", "GENERIC_WB55CCUX", "GENERIC_WB55CEUX", + "GENERIC_WB55RCVX", "GENERIC_WB55REVX", "GENERIC_WL54CCUX", "GENERIC_WL54JCIX", + "GENERIC_WL55CCUX", "GENERIC_WL55JCIX", "GENERIC_WLE4C8UX", "GENERIC_WLE4CBUX", + "GENERIC_WLE4CCUX", "GENERIC_WLE4J8IX", "GENERIC_WLE4JBIX", "GENERIC_WLE4JCIX", + "GENERIC_WLE5C8UX", "GENERIC_WLE5CBUX", "GENERIC_WLE5J8IX", "GENERIC_WLE5JBIX", "NUCLEO_H743ZI", "NUCLEO_L496ZG", "NUCLEO_L4R5ZI", diff --git a/boards.txt b/boards.txt index 15fec736e6..fe159da816 100644 --- a/boards.txt +++ b/boards.txt @@ -149,7 +149,7 @@ Nucleo_144.menu.pnum.NUCLEO_H563ZI.build.float-abi=-mfloat-abi=hard Nucleo_144.menu.pnum.NUCLEO_H563ZI.build.board=NUCLEO_H563ZI Nucleo_144.menu.pnum.NUCLEO_H563ZI.build.series=STM32H5xx Nucleo_144.menu.pnum.NUCLEO_H563ZI.build.product_line=STM32H563xx -Nucleo_144.menu.pnum.NUCLEO_H563ZI.build.variant=STM32H5xx/H563Z(G-I)T_H573ZIT +Nucleo_144.menu.pnum.NUCLEO_H563ZI.build.variant=STM32H5xx/H563Z(G-I)T Nucleo_144.menu.pnum.NUCLEO_H563ZI.build.cmsis_lib_gcc=arm_ARMv8MMLlfsp_math # NUCLEO H723ZG board @@ -1073,7 +1073,7 @@ Disco.menu.pnum.STM32H573I_DK.build.float-abi=-mfloat-abi=hard Disco.menu.pnum.STM32H573I_DK.build.board=STM32H573I_DK Disco.menu.pnum.STM32H573I_DK.build.series=STM32H5xx Disco.menu.pnum.STM32H573I_DK.build.product_line=STM32H573xx -Disco.menu.pnum.STM32H573I_DK.build.variant=STM32H5xx/H563IIKxQ_H573IIKxQ +Disco.menu.pnum.STM32H573I_DK.build.variant=STM32H5xx/H573IIKxQ Disco.menu.pnum.STM32H573I_DK.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS Disco.menu.pnum.STM32H573I_DK.build.cmsis_lib_gcc=arm_ARMv8MMLlfsp_math @@ -7294,7 +7294,7 @@ GenH5.menu.pnum.GENERIC_H563IIKXQ.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563IIKXQ.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563IIKXQ.build.board=GENERIC_H563IIKXQ GenH5.menu.pnum.GENERIC_H563IIKXQ.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563IIKXQ.build.variant=STM32H5xx/H563IIKxQ_H573IIKxQ +GenH5.menu.pnum.GENERIC_H563IIKXQ.build.variant=STM32H5xx/H563IIKxQ # Generic H563ZGTx GenH5.menu.pnum.GENERIC_H563ZGTX=Generic H563ZGTx @@ -7302,7 +7302,7 @@ GenH5.menu.pnum.GENERIC_H563ZGTX.upload.maximum_size=1048576 GenH5.menu.pnum.GENERIC_H563ZGTX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563ZGTX.build.board=GENERIC_H563ZGTX GenH5.menu.pnum.GENERIC_H563ZGTX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563ZGTX.build.variant=STM32H5xx/H563Z(G-I)T_H573ZIT +GenH5.menu.pnum.GENERIC_H563ZGTX.build.variant=STM32H5xx/H563Z(G-I)T # Generic H563ZITx GenH5.menu.pnum.GENERIC_H563ZITX=Generic H563ZITx @@ -7310,7 +7310,7 @@ GenH5.menu.pnum.GENERIC_H563ZITX.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563ZITX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563ZITX.build.board=GENERIC_H563ZITX GenH5.menu.pnum.GENERIC_H563ZITX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563ZITX.build.variant=STM32H5xx/H563Z(G-I)T_H573ZIT +GenH5.menu.pnum.GENERIC_H563ZITX.build.variant=STM32H5xx/H563Z(G-I)T # Generic H573IIKxQ GenH5.menu.pnum.GENERIC_H573IIKXQ=Generic H573IIKxQ @@ -7318,7 +7318,7 @@ GenH5.menu.pnum.GENERIC_H573IIKXQ.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H573IIKXQ.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H573IIKXQ.build.board=GENERIC_H573IIKXQ GenH5.menu.pnum.GENERIC_H573IIKXQ.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573IIKXQ.build.variant=STM32H5xx/H563IIKxQ_H573IIKxQ +GenH5.menu.pnum.GENERIC_H573IIKXQ.build.variant=STM32H5xx/H573IIKxQ # Generic H573ZITx GenH5.menu.pnum.GENERIC_H573ZITX=Generic H573ZITx @@ -7326,7 +7326,7 @@ GenH5.menu.pnum.GENERIC_H573ZITX.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H573ZITX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H573ZITX.build.board=GENERIC_H573ZITX GenH5.menu.pnum.GENERIC_H573ZITX.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573ZITX.build.variant=STM32H5xx/H563Z(G-I)T_H573ZIT +GenH5.menu.pnum.GENERIC_H573ZITX.build.variant=STM32H5xx/H573ZIT # Upload menu GenH5.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake index 379d245ff2..e25617cb69 100644 --- a/cmake/boards_db.cmake +++ b/cmake/boards_db.cmake @@ -74473,7 +74473,7 @@ target_compile_options(GENERIC_G4A1VETX_xusb_HSFS INTERFACE # GENERIC_H563IIKXQ # ----------------------------------------------------------------------------- -set(GENERIC_H563IIKXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H563IIKxQ_H573IIKxQ") +set(GENERIC_H563IIKXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H563IIKxQ") set(GENERIC_H563IIKXQ_MAXSIZE 2097152) set(GENERIC_H563IIKXQ_MAXDATASIZE 655360) set(GENERIC_H563IIKXQ_MCU cortex-m33) @@ -74558,7 +74558,7 @@ target_compile_options(GENERIC_H563IIKXQ_xusb_HSFS INTERFACE # GENERIC_H563ZGTX # ----------------------------------------------------------------------------- -set(GENERIC_H563ZGTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H563Z(G-I)T_H573ZIT") +set(GENERIC_H563ZGTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H563Z(G-I)T") set(GENERIC_H563ZGTX_MAXSIZE 1048576) set(GENERIC_H563ZGTX_MAXDATASIZE 655360) set(GENERIC_H563ZGTX_MCU cortex-m33) @@ -74643,7 +74643,7 @@ target_compile_options(GENERIC_H563ZGTX_xusb_HSFS INTERFACE # GENERIC_H563ZITX # ----------------------------------------------------------------------------- -set(GENERIC_H563ZITX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H563Z(G-I)T_H573ZIT") +set(GENERIC_H563ZITX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H563Z(G-I)T") set(GENERIC_H563ZITX_MAXSIZE 2097152) set(GENERIC_H563ZITX_MAXDATASIZE 655360) set(GENERIC_H563ZITX_MCU cortex-m33) @@ -74728,7 +74728,7 @@ target_compile_options(GENERIC_H563ZITX_xusb_HSFS INTERFACE # GENERIC_H573IIKXQ # ----------------------------------------------------------------------------- -set(GENERIC_H573IIKXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H563IIKxQ_H573IIKxQ") +set(GENERIC_H573IIKXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H573IIKxQ") set(GENERIC_H573IIKXQ_MAXSIZE 2097152) set(GENERIC_H573IIKXQ_MAXDATASIZE 655360) set(GENERIC_H573IIKXQ_MCU cortex-m33) @@ -74813,7 +74813,7 @@ target_compile_options(GENERIC_H573IIKXQ_xusb_HSFS INTERFACE # GENERIC_H573ZITX # ----------------------------------------------------------------------------- -set(GENERIC_H573ZITX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H563Z(G-I)T_H573ZIT") +set(GENERIC_H573ZITX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H573ZIT") set(GENERIC_H573ZITX_MAXSIZE 2097152) set(GENERIC_H573ZITX_MAXDATASIZE 655360) set(GENERIC_H573ZITX_MCU cortex-m33) @@ -102859,7 +102859,7 @@ target_compile_options(NUCLEO_G474RE_xusb_HSFS INTERFACE # NUCLEO_H563ZI # ----------------------------------------------------------------------------- -set(NUCLEO_H563ZI_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H563Z(G-I)T_H573ZIT") +set(NUCLEO_H563ZI_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H563Z(G-I)T") set(NUCLEO_H563ZI_MAXSIZE 2097152) set(NUCLEO_H563ZI_MAXDATASIZE 655360) set(NUCLEO_H563ZI_MCU cortex-m33) @@ -106712,7 +106712,7 @@ target_compile_options(STM32C0316_DK_xusb_HSFS INTERFACE # STM32H573I_DK # ----------------------------------------------------------------------------- -set(STM32H573I_DK_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H563IIKxQ_H573IIKxQ") +set(STM32H573I_DK_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H573IIKxQ") set(STM32H573I_DK_MAXSIZE 2097152) set(STM32H573I_DK_MAXDATASIZE 655360) set(STM32H573I_DK_MCU cortex-m33) diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h index 3b07d4403a..a8e7560bea 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h @@ -1356,6 +1356,7 @@ typedef struct __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; } NSSLIB_pFunc_TypeDef; + /** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */ @@ -10575,11 +10576,12 @@ typedef struct #define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ #define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ #define TAMP_ATCR1_ATCKSEL_Pos (16U) -#define TAMP_ATCR1_ATCKSEL_Msk (0x7UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00070000 */ +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ #define TAMP_ATCR1_ATPER_Pos (24U) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h562xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h562xx.h index b5631c24d3..ea69087317 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h562xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h562xx.h @@ -2111,6 +2111,7 @@ typedef struct __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; } NSSLIB_pFunc_TypeDef; + /** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */ @@ -15786,11 +15787,12 @@ typedef struct #define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ #define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ #define TAMP_ATCR1_ATCKSEL_Pos (16U) -#define TAMP_ATCR1_ATCKSEL_Msk (0x7UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00070000 */ +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ #define TAMP_ATCR1_ATPER_Pos (24U) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk @@ -21125,8 +21127,6 @@ typedef struct ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ - ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \ - ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ @@ -21254,15 +21254,9 @@ typedef struct ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /******************* TIM Instances : Timer input selection ********************/ -#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \ - ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S)|| \ - ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S)|| \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)|| \ ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)|| \ ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h563xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h563xx.h index e29094744d..1411530df1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h563xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h563xx.h @@ -2299,6 +2299,7 @@ typedef struct __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; } NSSLIB_pFunc_TypeDef; + /** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */ @@ -17882,11 +17883,12 @@ typedef struct #define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ #define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ #define TAMP_ATCR1_ATCKSEL_Pos (16U) -#define TAMP_ATCR1_ATCKSEL_Msk (0x7UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00070000 */ +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ #define TAMP_ATCR1_ATPER_Pos (24U) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk @@ -23261,8 +23263,6 @@ typedef struct ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ - ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \ - ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ @@ -23390,15 +23390,9 @@ typedef struct ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /******************* TIM Instances : Timer input selection ********************/ -#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \ - ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S)|| \ - ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S)|| \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)|| \ ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)|| \ ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h index eb531da13c..f681a555af 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h @@ -2394,6 +2394,31 @@ typedef struct __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; } NSSLIB_pFunc_TypeDef; +/* + * Certificate address description + */ +#define CERT_CHIP_PACK1_ADDR (0x0BF9FE00U) +#define CERT_CHIP_PACK1_SIZE (0x200U) +#define CERT_CHIP_PACK2_ADDR (0x0BF9FC00U) +#define CERT_CHIP_PACK2_SIZE (0x200U) + +#define CERT_CHIP_PACK_ADDR (CERT_CHIP_PACK2_ADDR) +#define CERT_CHIP_PACK_SIZE (CERT_CHIP_PACK1_SIZE + CERT_CHIP_PACK2_SIZE) + +#define CERT_ST_DUA_INIT_ATTEST_PUB_KEY_OFFSET (152U) +#define CERT_ST_DUA_INIT_ATTEST_PUB_KEY_ADDR (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_PUB_KEY_OFFSET) +#define CERT_ST_DUA_INIT_ATTEST_SIGN_OFFSET (216U) +#define CERT_ST_DUA_INIT_ATTEST_SIGN_ADDR (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_SIGN_OFFSET) +#define CERT_ST_DUA_INIT_ATTEST_SERIAL_OFFSET (484U) +#define CERT_ST_DUA_INIT_ATTEST_SERIAL_ADDR (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_SERIAL_OFFSET) + +#define CERT_ST_DUA_USER_PUB_KEY_OFFSET (12U) +#define CERT_ST_DUA_USER_PUB_KEY_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_PUB_KEY_OFFSET) +#define CERT_ST_DUA_USER_SIGN_OFFSET (76U) +#define CERT_ST_DUA_USER_SIGN_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_SIGN_OFFSET) +#define CERT_ST_DUA_USER_SERIAL_OFFSET (140U) +#define CERT_ST_DUA_USER_SERIAL_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_SERIAL_OFFSET) + /** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */ @@ -18439,11 +18464,12 @@ typedef struct #define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ #define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ #define TAMP_ATCR1_ATCKSEL_Pos (16U) -#define TAMP_ATCR1_ATCKSEL_Msk (0x7UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00070000 */ +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ #define TAMP_ATCR1_ATPER_Pos (24U) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk @@ -24186,8 +24212,6 @@ typedef struct ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ - ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \ - ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ @@ -24315,15 +24339,9 @@ typedef struct ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /******************* TIM Instances : Timer input selection ********************/ -#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \ - ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S)|| \ - ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S)|| \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)|| \ ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)|| \ ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h index 6695a97a22..889e7391b9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h @@ -78,10 +78,10 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number 1.0.0 + * @brief CMSIS Device version number 1.1.0 */ #define __STM32H5_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32H5_CMSIS_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32H5_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ #define __STM32H5_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32H5_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32H5_CMSIS_VERSION ((__STM32H5_CMSIS_VERSION_MAIN << 24U)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Release_Notes.html index ddc726d47e..ffd4574c6b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Release_Notes.html @@ -30,10 +30,21 @@

Release Notes for  STM32H5xx C

Update History

- +

Main Changes

    +
  • Add DUA addresses constants definitions for STM32H573xx devices only
    • +
  • Fix wrong definition of IS_TIM_CLOCKSOURCE_TIX_INSTANCE & IS_TIM_TISEL_INSTANCE macros
    • +
  • Update possible values of the ATCKSEL field of TAMP active tamper control register and update the mask accordingly.
    • +
+
+
+
+ +
+

Main Changes

+
  • First official release version of bits and registers definition aligned with RM0481 and RM0492 (STM32H5 reference manuals)
diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 083796585d..73c242a041 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -9,7 +9,7 @@ * STM32F7: 1.2.8 * STM32G0: 1.4.3 * STM32G4: 1.2.2 - * STM32H5: 1.0.0 + * STM32H5: 1.1.0 * STM32H7: 1.10.3 * STM32L0: 1.9.3 * STM32L1: 2.3.3 diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 733919f2a0..71e35d5cf7 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -37,16 +37,12 @@ extern "C" { #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR -#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1) +#if defined(STM32H7) || defined(STM32MP1) #define CRYP_DATATYPE_32B CRYP_NO_SWAP #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP #define CRYP_DATATYPE_1B CRYP_BIT_SWAP -#if defined(STM32U5) -#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF -#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF -#endif /* STM32U5 */ -#endif /* STM32U5 || STM32H7 || STM32MP1 */ +#endif /* STM32H7 || STM32MP1 */ /** * @} */ @@ -3931,6 +3927,12 @@ extern "C" { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) #endif /* STM32F1 */ +#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ + defined (STM32H7) || \ + defined (STM32L0) || defined (STM32L1) +#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG +#endif + #define IS_ALARM IS_RTC_ALARM #define IS_ALARM_MASK IS_RTC_ALARM_MASK #define IS_TAMPER IS_RTC_TAMPER diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h index 085223349c..66c540f990 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h @@ -218,10 +218,10 @@ extern HAL_TickFreqTypeDef uwTickFreq; /** @defgroup SBS_NextHDPL_Selection Next HDPL Selection * @{ */ -#define SBS_OBKHDPL_INCR_0 0x00U -#define SBS_OBKHDPL_INCR_1 SBS_NEXTHDPLCR_NEXTHDPL_0 -#define SBS_OBKHDPL_INCR_2 SBS_NEXTHDPLCR_NEXTHDPL_1 -#define SBS_OBKHDPL_INCR_3 SBS_NEXTHDPLCR_NEXTHDPL +#define SBS_OBKHDPL_INCR_0 0x00U /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ +#define SBS_OBKHDPL_INCR_1 SBS_NEXTHDPLCR_NEXTHDPL_0 /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ +#define SBS_OBKHDPL_INCR_2 SBS_NEXTHDPLCR_NEXTHDPL_1 /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ +#define SBS_OBKHDPL_INCR_3 SBS_NEXTHDPLCR_NEXTHDPL /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ /** * @} */ @@ -230,14 +230,24 @@ extern HAL_TickFreqTypeDef uwTickFreq; /** @defgroup SBS_HDPL_Value HDPL Value * @{ */ -#define SBS_HDPL_VALUE_0 0x000000B4U -#define SBS_HDPL_VALUE_1 0x00000051U -#define SBS_HDPL_VALUE_2 0x0000008AU -#define SBS_HDPL_VALUE_3 0x0000006FU +#define SBS_HDPL_VALUE_0 0x000000B4U /*!< Hide protection level 0 */ +#define SBS_HDPL_VALUE_1 0x00000051U /*!< Hide protection level 0 */ +#define SBS_HDPL_VALUE_2 0x0000008AU /*!< Hide protection level 0 */ +#define SBS_HDPL_VALUE_3 0x0000006FU /*!< Hide protection level 0 */ /** * @} */ +#if defined(SBS_DBGCR_DBG_AUTH_SEC) +/** @defgroup SBS_DEBUG_SEC_Value Debug sec Value + * @{ + */ +#define SBS_DEBUG_SEC_NSEC 0x000000B4U /*!< Debug opening for secure and non-secure */ +#define SBS_DEBUG_NSEC 0x0000003CU /*!< Debug opening for non-secure only */ +/** + * @} + */ +#endif /* SBS_DBGCR_DBG_AUTH_SEC */ /** @defgroup SBS_Lock_items SBS Lock items * @brief SBS items to set lock on @@ -255,7 +265,7 @@ extern HAL_TickFreqTypeDef uwTickFreq; code only) */ #define SBS_LOCK_ALL (SBS_MPU_NSEC|SBS_VTOR_NSEC|SBS_SAU|SBS_MPU_SEC|SBS_VTOR_AIRCR_SEC) /*!< All */ #else -#define SBS_LOCK_ALL (SBS_MPU_NSEC|SBS_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */ +#define SBS_LOCK_ALL (SBS_MPU_NSEC|SBS_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */ #endif /* __ARM_FEATURE_CMSE */ /** * @} @@ -646,6 +656,9 @@ extern HAL_TickFreqTypeDef uwTickFreq; (((__PIN__) & SBS_FASTMODEPLUS_PB8) == SBS_FASTMODEPLUS_PB8)) #endif /* SBS_FASTMODEPLUS_PB9 */ +#define IS_SBS_HDPL(__LEVEL__) (((__LEVEL__) == SBS_HDPL_VALUE_0) || ((__LEVEL__) == SBS_HDPL_VALUE_1) || \ + ((__LEVEL__) == SBS_HDPL_VALUE_2) || ((__LEVEL__) == SBS_HDPL_VALUE_3)) + #define IS_SBS_OBKHDPL_SELECTION(__SELECT__) (((__SELECT__) == SBS_OBKHDPL_INCR_0) || \ ((__SELECT__) == SBS_OBKHDPL_INCR_1) || \ ((__SELECT__) == SBS_OBKHDPL_INCR_2) || \ @@ -701,11 +714,11 @@ extern HAL_TickFreqTypeDef uwTickFreq; */ /* Initialization and de-initialization functions ******************************/ -HAL_StatusTypeDef HAL_Init(void); -HAL_StatusTypeDef HAL_DeInit(void); -void HAL_MspInit(void); -void HAL_MspDeInit(void); -HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); /** * @} @@ -716,20 +729,20 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); */ /* Peripheral Control functions ************************************************/ -void HAL_IncTick(void); -void HAL_Delay(uint32_t Delay); -uint32_t HAL_GetTick(void); -uint32_t HAL_GetTickPrio(void); -HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); -HAL_TickFreqTypeDef HAL_GetTickFreq(void); -void HAL_SuspendTick(void); -void HAL_ResumeTick(void); -uint32_t HAL_GetHalVersion(void); -uint32_t HAL_GetREVID(void); -uint32_t HAL_GetDEVID(void); -uint32_t HAL_GetUIDw0(void); -uint32_t HAL_GetUIDw1(void); -uint32_t HAL_GetUIDw2(void); +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); /** * @} @@ -740,10 +753,10 @@ uint32_t HAL_GetUIDw2(void); */ /* DBGMCU Peripheral Control functions *****************************************/ -void HAL_DBGMCU_EnableDBGStopMode(void); -void HAL_DBGMCU_DisableDBGStopMode(void); -void HAL_DBGMCU_EnableDBGStandbyMode(void); -void HAL_DBGMCU_DisableDBGStandbyMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); /** * @} @@ -753,47 +766,92 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void); * @{ */ -/* SBS Control functions ****************************************************/ - +/* VREFBUF Control functions ****************************************************/ #if defined(VREFBUF) -void HAL_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); -void HAL_VREFBUF_HighImpedanceConfig(uint32_t Mode); -void HAL_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); -HAL_StatusTypeDef HAL_EnableVREFBUF(void); -void HAL_DisableVREFBUF(void); +void HAL_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); +void HAL_VREFBUF_HighImpedanceConfig(uint32_t Mode); +void HAL_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); +HAL_StatusTypeDef HAL_EnableVREFBUF(void); +void HAL_DisableVREFBUF(void); #endif /* VREFBUF */ -void HAL_SBS_ETHInterfaceSelect(uint32_t SBS_ETHInterface); -void HAL_SBS_EnableVddIO1CompensationCell(void); -void HAL_SBS_DisableVddIO1CompensationCell(void); -void HAL_SBS_EnableVddIO2CompensationCell(void); -void HAL_SBS_DisableVddIO2CompensationCell(void); -void HAL_SBS_VDDCompensationCodeSelect(uint32_t SBS_CompCode); -void HAL_SBS_VDDIOCompensationCodeSelect(uint32_t SBS_CompCode); -uint32_t HAL_SBS_GetVddIO1CompensationCellReadyFlag(void); -uint32_t HAL_SBS_GetVddIO2CompensationCellReadyFlag(void); -void HAL_SBS_VDDCompensationCodeConfig(uint32_t SBS_PMOSCode, uint32_t SBS_NMOSCode); -void HAL_SBS_VDDIOCompensationCodeConfig(uint32_t SBS_PMOSCode, uint32_t SBS_NMOSCode); -uint32_t HAL_SBS_GetNMOSVddCompensationValue(void); -uint32_t HAL_SBS_GetPMOSVddCompensationValue(void); -uint32_t HAL_SBS_GetNMOSVddIO2CompensationValue(void); -uint32_t HAL_SBS_GetPMOSVddIO2CompensationValue(void); -void HAL_SBS_EPOCHSelection(uint32_t Epoch_Selection); -uint32_t HAL_SBS_GetEPOCHSelection(void); -void HAL_SBS_IncrementHDPLValue(void); -uint32_t HAL_SBS_GetHDPLValue(void); -void HAL_SBS_SetOBKHDPL(uint32_t OBKHDPL_Value); -uint32_t HAL_SBS_GetOBKHDPL(void); -void HAL_SBS_FLASH_EnableECCNMI(void); -void HAL_SBS_FLASH_DisableECCNMI(void); -uint32_t HAL_SBS_FLASH_ECCNMI_IsDisabled(void); +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group5 + * @{ + */ + +/* SBS System Configuration functions *******************************************/ +void HAL_SBS_ETHInterfaceSelect(uint32_t SBS_ETHInterface); +void HAL_SBS_EnableVddIO1CompensationCell(void); +void HAL_SBS_DisableVddIO1CompensationCell(void); +void HAL_SBS_EnableVddIO2CompensationCell(void); +void HAL_SBS_DisableVddIO2CompensationCell(void); +void HAL_SBS_VDDCompensationCodeSelect(uint32_t SBS_CompCode); +void HAL_SBS_VDDIOCompensationCodeSelect(uint32_t SBS_CompCode); +uint32_t HAL_SBS_GetVddIO1CompensationCellReadyFlag(void); +uint32_t HAL_SBS_GetVddIO2CompensationCellReadyFlag(void); +void HAL_SBS_VDDCompensationCodeConfig(uint32_t SBS_PMOSCode, uint32_t SBS_NMOSCode); +void HAL_SBS_VDDIOCompensationCodeConfig(uint32_t SBS_PMOSCode, uint32_t SBS_NMOSCode); +uint32_t HAL_SBS_GetNMOSVddCompensationValue(void); +uint32_t HAL_SBS_GetPMOSVddCompensationValue(void); +uint32_t HAL_SBS_GetNMOSVddIO2CompensationValue(void); +uint32_t HAL_SBS_GetPMOSVddIO2CompensationValue(void); +void HAL_SBS_FLASH_EnableECCNMI(void); +void HAL_SBS_FLASH_DisableECCNMI(void); +uint32_t HAL_SBS_FLASH_ECCNMI_IsDisabled(void); /** * @} */ +/** @addtogroup HAL_Exported_Functions_Group6 + * @{ + */ + +/* SBS Boot control functions ***************************************************/ +void HAL_SBS_IncrementHDPLValue(void); +uint32_t HAL_SBS_GetHDPLValue(void); -/** @addtogroup HAL_Exported_Functions_Group5 +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group7 + * @{ + */ + +/* SBS Hardware secure storage control functions ********************************/ +void HAL_SBS_EPOCHSelection(uint32_t Epoch_Selection); +uint32_t HAL_SBS_GetEPOCHSelection(void); +void HAL_SBS_SetOBKHDPL(uint32_t OBKHDPL_Value); +uint32_t HAL_SBS_GetOBKHDPL(void); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group8 + * @{ + */ + +/* SBS Debug control functions ***************************************************/ +void HAL_SBS_OpenAccessPort(void); +void HAL_SBS_OpenDebug(void); +HAL_StatusTypeDef HAL_SBS_ConfigDebugLevel(uint32_t Level); +uint32_t HAL_SBS_GetDebugLevel(void); +void HAL_SBS_LockDebugConfig(void); +void HAL_SBS_ConfigDebugSecurity(uint32_t Security); +uint32_t HAL_SBS_GetDebugSecurity(void); + +/** + * @} + */ + + +/** @addtogroup HAL_Exported_Functions_Group9 * @{ */ @@ -805,7 +863,7 @@ HAL_StatusTypeDef HAL_SBS_GetLock(uint32_t *pItem); * @} */ -/** @addtogroup HAL_Exported_Functions_Group6 +/** @addtogroup HAL_Exported_Functions_Group10 * @{ */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cryp.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cryp.h index e21c168d12..97b30ebac4 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cryp.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cryp.h @@ -77,7 +77,6 @@ typedef struct } CRYP_ConfigTypeDef; - /** * @brief CRYP State Structure definition */ @@ -92,6 +91,31 @@ typedef enum #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ } HAL_CRYP_STATETypeDef; +/** + * @brief CRYP Context Structure definition + */ + +typedef struct +{ + uint32_t DataType; /*!< This parameter can be a value of @ref CRYP_Data_Type */ + uint32_t KeySize; /*!< This parameter can be a value of @ref CRYP_Key_Size */ + uint32_t *pKey; /*!< The key used for encryption/decryption */ + uint32_t *pInitVect; /*!< The initialization vector, counter with CBC and CTR Algorithm */ + uint32_t Algorithm; /*!< This parameter can be a value of @ref CRYP_Algorithm_Mode */ + uint32_t DataWidthUnit; /*!< This parameter can be value of @ref CRYP_Data_Width_Unit */ + uint32_t KeyIVConfigSkip; /*!< This parameter can be a value of @ref CRYP_Configuration_Skip */ + uint32_t KeyMode; /*!< This parameter can be value of @ref CRYP_Key_Mode */ + uint32_t Phase; /*!< CRYP peripheral phase */ + uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag */ + uint32_t CR_Reg; /*!< CRYP CR register */ + uint32_t IER_Reg; /*!< CRYP IER register */ + uint32_t IVR0_Reg; /*!< CRYP IVR0 register */ + uint32_t IVR1_Reg; /*!< CRYP IVR1 register */ + uint32_t IVR2_Reg; /*!< CRYP IVR2 register */ + uint32_t IVR3_Reg; /*!< CRYP IVR3 register */ + +} CRYP_ContextTypeDef; + #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) /** * @brief HAL CRYP mode suspend definitions @@ -340,10 +364,15 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point * @{ */ -#define CRYP_NO_SWAP 0x00000000U /*!< 32-bit data type (no swapping) */ -#define CRYP_HALFWORD_SWAP AES_CR_DATATYPE_0 /*!< 16-bit data type (half-word swapping) */ -#define CRYP_BYTE_SWAP AES_CR_DATATYPE_1 /*!< 8-bit data type (byte swapping) */ -#define CRYP_BIT_SWAP AES_CR_DATATYPE /*!< 1-bit data type (bit swapping) */ +#define CRYP_DATATYPE_32B 0x00000000U +#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0 +#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 +#define CRYP_DATATYPE_1B AES_CR_DATATYPE + +#define CRYP_NO_SWAP CRYP_DATATYPE_32B /*!< 32-bit data type (no swapping) */ +#define CRYP_HALFWORD_SWAP CRYP_DATATYPE_16B /*!< 16-bit data type (half-word swapping) */ +#define CRYP_BYTE_SWAP CRYP_DATATYPE_8B /*!< 8-bit data type (byte swapping) */ +#define CRYP_BIT_SWAP CRYP_DATATYPE_1B /*!< 1-bit data type (bit swapping) */ /** * @} @@ -352,9 +381,9 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point /** @defgroup CRYP_Interrupt CRYP Interrupt * @{ */ -#define CRYP_IT_CCFIE AES_IER_CCFIE /*!< Computation Complete interrupt enable */ -#define CRYP_IT_RWEIE AES_IER_RWEIE /*!< Read or write Error interrupt enable */ -#define CRYP_IT_KEIE AES_IER_KEIE /*!< Key error interrupt enable */ +#define CRYP_IT_CCFIE AES_IER_CCFIE /*!< Computation Complete interrupt enable */ +#define CRYP_IT_RWEIE AES_IER_RWEIE /*!< Read or write Error interrupt enable */ +#define CRYP_IT_KEIE AES_IER_KEIE /*!< Key error interrupt enable */ #define CRYP_IT_RNGEIE AES_IER_RNGEIE /*!< Rng error interrupt enable */ /** @@ -365,15 +394,15 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point * @{ */ -#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden - also set when transferring a shared key from SAES peripheral */ -#define CRYP_FLAG_WRERR (AES_SR_WRERR | 0x80000000U) /*!< Write Error flag */ -#define CRYP_FLAG_RDERR (AES_SR_RDERR | 0x80000000U) /*!< Read error flag */ -#define CRYP_FLAG_CCF AES_ISR_CCF /*!< Computation completed flag as AES_ISR_CCF */ -#define CRYP_FLAG_KEYVALID AES_SR_KEYVALID /*!< Key Valid flag */ -#define CRYP_FLAG_KEIF AES_ISR_KEIF /*Key error interrupt flag */ -#define CRYP_FLAG_RWEIF AES_ISR_RWEIF /*Read or write error Interrupt flag */ -#define CRYP_FLAG_RNGEIF AES_ISR_RNGEIF /*RNG error interrupt flag */ +#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden also set when + transferring a shared key from SAES peripheral */ +#define CRYP_FLAG_WRERR (AES_SR_WRERR | 0x80000000U) /*!< Write Error flag */ +#define CRYP_FLAG_RDERR (AES_SR_RDERR | 0x80000000U) /*!< Read error flag */ +#define CRYP_FLAG_CCF AES_ISR_CCF /*!< Computation completed flag as AES_ISR_CCF */ +#define CRYP_FLAG_KEYVALID AES_SR_KEYVALID /*!< Key Valid flag */ +#define CRYP_FLAG_KEIF AES_ISR_KEIF /*!Instance->CR) & (__INTERRUPT__)) +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @addtogroup FMAC_Private_Constants + * @{ + */ + +#define FMAC_PARAM_P_MAX_IIR 64U /*!< Maximum value of P parameter with IIR */ +#define FMAC_PARAM_P_MAX_FIR 127U /*!< Maximum value of P parameter with FIR */ +#define FMAC_PARAM_P_MIN 2U /*!< Minimum value of P parameter */ +#define FMAC_PARAM_Q_MAX 63U /*!< Maximum value of Q parameter */ +#define FMAC_PARAM_Q_MIN 1U /*!< Minimum value of Q parameter */ +#define FMAC_PARAM_R_MAX 7U /*!< Maximum value of R parameter */ + /** * @} */ @@ -549,10 +565,12 @@ typedef struct * @param __FUNCTION__ ID of the filter function. * @retval SET (__P__ is a valid value) or RESET (__P__ is invalid) */ -#define IS_FMAC_PARAM_P(__FUNCTION__, __P__) ( (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) && \ - (((__P__) >= 2U) && ((__P__) <= 127U))) || \ - (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \ - (((__P__) >= 2U) && ((__P__) <= 64U))) ) +#define IS_FMAC_PARAM_P(__FUNCTION__, __P__) ((((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) && \ + (((__P__) >= FMAC_PARAM_P_MIN) && \ + ((__P__) <= FMAC_PARAM_P_MAX_FIR))) || \ + (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \ + (((__P__) >= FMAC_PARAM_P_MIN) && \ + ((__P__) <= FMAC_PARAM_P_MAX_IIR)))) /** * @brief Verify the FMAC filter parameter Q. @@ -562,7 +580,7 @@ typedef struct */ #define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) ( ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \ (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \ - (((__Q__) >= 1U) && ((__Q__) <= 63U))) ) + (((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))) ) /** * @brief Verify the FMAC filter parameter R. @@ -572,7 +590,7 @@ typedef struct */ #define IS_FMAC_PARAM_R(__FUNCTION__, __R__) ( (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \ ((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1)) && \ - ((__R__) <= 7U)) + ((__R__) <= FMAC_PARAM_R_MAX)) /** * @brief Verify the FMAC buffer access. diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c.h index 820003963c..692d125dcc 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c.h @@ -809,8 +809,8 @@ uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c); (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ (~I2C_CR2_RD_WRN)) : \ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ - (I2C_CR2_ADD10) | (I2C_CR2_START)) & \ - (~I2C_CR2_RD_WRN))) + (I2C_CR2_ADD10) | (I2C_CR2_START) | \ + (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN))) #define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i3c.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i3c.h index b3b452dc25..1d2fdeccad 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i3c.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i3c.h @@ -248,15 +248,16 @@ typedef enum */ typedef enum { - HAL_I3C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ - HAL_I3C_STATE_READY = 0x10U, /*!< Peripheral Initialized and ready for use */ - HAL_I3C_STATE_BUSY = 0x20U, /*!< An internal process is ongoing */ - HAL_I3C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ - HAL_I3C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ - HAL_I3C_STATE_BUSY_DAA = 0x24U, /*!< Dynamic address assignment process is ongoing */ - HAL_I3C_STATE_LISTEN = 0x30U, /*!< Listen process is ongoing */ - HAL_I3C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ - HAL_I3C_STATE_ERROR = 0xE0U, /*!< Error */ + HAL_I3C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I3C_STATE_READY = 0x10U, /*!< Peripheral Initialized and ready for use */ + HAL_I3C_STATE_BUSY = 0x20U, /*!< An internal process is ongoing */ + HAL_I3C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I3C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I3C_STATE_BUSY_TX_RX = 0x23U, /*!< Data Multiple Transfer process is ongoing */ + HAL_I3C_STATE_BUSY_DAA = 0x24U, /*!< Dynamic address assignment process is ongoing */ + HAL_I3C_STATE_LISTEN = 0x30U, /*!< Listen process is ongoing */ + HAL_I3C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + HAL_I3C_STATE_ERROR = 0xE0U, /*!< Error */ } HAL_I3C_StateTypeDef; /** @@ -428,40 +429,43 @@ typedef struct __I3C_HandleTypeDef #if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) void (* CtrlTxCpltCallback)(struct __I3C_HandleTypeDef *hi3c); - /*!< I3C Controller private data and CCC Tx Transfer complete callback */ + /*!< I3C Controller private data and CCC Tx Transfer complete callback */ void (* CtrlRxCpltCallback)(struct __I3C_HandleTypeDef *hi3c); - /*!< I3C Controller private data and CCC Rx Transfer completed callback */ + /*!< I3C Controller private data and CCC Rx Transfer completed callback */ + + void (* CtrlMultipleXferCpltCallback)(struct __I3C_HandleTypeDef *hi3c); + /*!< I3C Controller multiple Direct CCC, I3C private or I2C Transfer completed callback */ void (* CtrlDAACpltCallback)(struct __I3C_HandleTypeDef *hi3c); - /*!< I3C Controller Dynamic Address Assignment completed callback */ + /*!< I3C Controller Dynamic Address Assignment completed callback */ void (* TgtReqDynamicAddrCallback)(struct __I3C_HandleTypeDef *hi3c, uint64_t targetPayload); /*!< I3C Controller request dynamic address callback during Dynamic Address Assignment processus */ void (* TgtTxCpltCallback)(struct __I3C_HandleTypeDef *hi3c); - /*!< I3C Target private data Tx Transfer completed callback */ + /*!< I3C Target private data Tx Transfer completed callback */ void (* TgtRxCpltCallback)(struct __I3C_HandleTypeDef *hi3c); - /*!< I3C Target private data Rx Transfer completed callback */ + /*!< I3C Target private data Rx Transfer completed callback */ void (* TgtHotJoinCallback)(struct __I3C_HandleTypeDef *hi3c, uint8_t dynamicAddress); - /*!< I3C Target Hot-Join callback */ + /*!< I3C Target Hot-Join callback */ void (* NotifyCallback)(struct __I3C_HandleTypeDef *hi3c, uint32_t eventId); - /*!< I3C Target or Controller asynchronous events callback */ + /*!< I3C Target or Controller asynchronous events callback */ void (* ErrorCallback)(struct __I3C_HandleTypeDef *hi3c); - /*!< I3C Error callback */ + /*!< I3C Error callback */ void (* AbortCpltCallback)(struct __I3C_HandleTypeDef *hi3c); - /*!< I3C Abort complete callback */ + /*!< I3C Abort complete callback */ void (* MspInitCallback)(struct __I3C_HandleTypeDef *hi3c); - /*!< I3C Msp Init callback */ + /*!< I3C Msp Init callback */ void (* MspDeInitCallback)(struct __I3C_HandleTypeDef *hi3c); - /*!< I3C Msp DeInit callback */ + /*!< I3C Msp DeInit callback */ #endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ @@ -477,18 +481,32 @@ typedef struct __I3C_HandleTypeDef */ typedef enum { - HAL_I3C_CTRL_TX_COMPLETE_CB_ID = 0x00U, /*!< I3C Controller Tx Transfer completed callback ID */ - HAL_I3C_CTRL_RX_COMPLETE_CB_ID = 0x01U, /*!< I3C Controller Rx Transfer completed callback ID */ - HAL_I3C_CTRL_DAA_COMPLETE_CB_ID = 0x02U, /*!< I3C Controller Dynamic Address Assignment completed callback ID */ - HAL_I3C_TGT_REQ_DYNAMIC_ADDR_CB_ID = 0x03U, /*!< I3C Controller request dynamic address completed callback ID */ - HAL_I3C_TGT_TX_COMPLETE_CB_ID = 0x04U, /*!< I3C Target Tx Transfer completed callback ID */ - HAL_I3C_TGT_RX_COMPLETE_CB_ID = 0x05U, /*!< I3C Target Rx Transfer completed callback ID */ - HAL_I3C_TGT_HOTJOIN_CB_ID = 0x06U, /*!< I3C Target Hot-join notification callback ID */ - HAL_I3C_NOTIFY_CB_ID = 0x07U, /*!< I3C Target or Controller receive notification callback ID */ - HAL_I3C_ERROR_CB_ID = 0x08U, /*!< I3C Error callback ID */ - HAL_I3C_ABORT_CB_ID = 0x09U, /*!< I3C Abort callback ID */ - HAL_I3C_MSPINIT_CB_ID = 0x0AU, /*!< I3C Msp Init callback ID */ - HAL_I3C_MSPDEINIT_CB_ID = 0x0BU /*!< I3C Msp DeInit callback ID */ + /*!< I3C Controller Tx Transfer completed callback ID */ + HAL_I3C_CTRL_TX_COMPLETE_CB_ID = 0x00U, + /*!< I3C Controller Rx Transfer completed callback ID */ + HAL_I3C_CTRL_RX_COMPLETE_CB_ID = 0x01U, + /*!< I3C Controller Multiple Transfer completed callback ID */ + HAL_I3C_CTRL_MULTIPLE_XFER_COMPLETE_CB_ID = 0x02U, + /*!< I3C Controller Dynamic Address Assignment completed callback ID */ + HAL_I3C_CTRL_DAA_COMPLETE_CB_ID = 0x03U, + /*!< I3C Controller request dynamic address completed callback ID */ + HAL_I3C_TGT_REQ_DYNAMIC_ADDR_CB_ID = 0x04U, + /*!< I3C Target Tx Transfer completed callback ID */ + HAL_I3C_TGT_TX_COMPLETE_CB_ID = 0x05U, + /*!< I3C Target Rx Transfer completed callback ID */ + HAL_I3C_TGT_RX_COMPLETE_CB_ID = 0x06U, + /*!< I3C Target Hot-join notification callback ID */ + HAL_I3C_TGT_HOTJOIN_CB_ID = 0x07U, + /*!< I3C Target or Controller receive notification callback ID */ + HAL_I3C_NOTIFY_CB_ID = 0x08U, + /*!< I3C Error callback ID */ + HAL_I3C_ERROR_CB_ID = 0x09U, + /*!< I3C Abort callback ID */ + HAL_I3C_ABORT_CB_ID = 0x0AU, + /*!< I3C Msp Init callback ID */ + HAL_I3C_MSPINIT_CB_ID = 0x0BU, + /*!< I3C Msp DeInit callback ID */ + HAL_I3C_MSPDEINIT_CB_ID = 0x0CU } HAL_I3C_CallbackIDTypeDef; /** @@ -1028,6 +1046,7 @@ HAL_StatusTypeDef HAL_I3C_ActivateNotification(I3C_HandleTypeDef *hi3c, I3C_Xfer HAL_StatusTypeDef HAL_I3C_DeactivateNotification(I3C_HandleTypeDef *hi3c, uint32_t interruptMask); void HAL_I3C_CtrlTxCpltCallback(I3C_HandleTypeDef *hi3c); void HAL_I3C_CtrlRxCpltCallback(I3C_HandleTypeDef *hi3c); +void HAL_I3C_CtrlMultipleXferCpltCallback(I3C_HandleTypeDef *hi3c); void HAL_I3C_CtrlDAACpltCallback(I3C_HandleTypeDef *hi3c); void HAL_I3C_TgtReqDynamicAddrCallback(I3C_HandleTypeDef *hi3c, uint64_t targetPayload); void HAL_I3C_TgtTxCpltCallback(I3C_HandleTypeDef *hi3c); @@ -1118,6 +1137,12 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_Receive_IT(I3C_HandleTypeDef *hi3c, HAL_StatusTypeDef HAL_I3C_Ctrl_Receive_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData); +/* Controller multiple Direct CCC Command, I3C private or I2C transfer APIs */ +HAL_StatusTypeDef HAL_I3C_Ctrl_MultipleTransfer_IT(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData); +HAL_StatusTypeDef HAL_I3C_Ctrl_MultipleTransfer_DMA(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData); + /* Controller assign dynamic address APIs */ HAL_StatusTypeDef HAL_I3C_Ctrl_SetDynAddr(I3C_HandleTypeDef *hi3c, uint8_t devAddress); HAL_StatusTypeDef HAL_I3C_Ctrl_DynAddrAssign_IT(I3C_HandleTypeDef *hi3c, uint32_t dynOption); @@ -1125,6 +1150,15 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_DynAddrAssign(I3C_HandleTypeDef *hi3c, uint64_t *target_payload, uint32_t dynOption, uint32_t timeout); +/* Controller check device ready APIs */ +HAL_StatusTypeDef HAL_I3C_Ctrl_IsDeviceI3C_Ready(I3C_HandleTypeDef *hi3c, + uint8_t devAddress, + uint32_t trials, + uint32_t timeout); +HAL_StatusTypeDef HAL_I3C_Ctrl_IsDeviceI2C_Ready(I3C_HandleTypeDef *hi3c, + uint8_t devAddress, + uint32_t trials, + uint32_t timeout); /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_mmc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_mmc.h index b4e770deab..959c828c09 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_mmc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_mmc.h @@ -30,6 +30,7 @@ extern "C" { /** @addtogroup STM32H5xx_HAL_Driver * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) /** @addtogroup MMC * @{ @@ -808,6 +809,7 @@ HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc); /** * @} */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_mmc_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_mmc_ex.h index 69102f6de6..e5b17bd399 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_mmc_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_mmc_ex.h @@ -30,7 +30,7 @@ extern "C" { /** @addtogroup STM32H5xx_HAL_Driver * @{ */ - +#if defined (SDMMC1) || defined (SDMMC2) /** @addtogroup MMCEx * @brief SD HAL extended module driver * @{ @@ -109,6 +109,7 @@ void HAL_MMCEx_Write_DMALnkLstBufCpltCallback(MMC_HandleTypeDef *hmmc); /** * @} */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_nand.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_nand.h index c68509da3a..7b9b067abf 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_nand.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_nand.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2023 STMicroelectronics. + * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -24,10 +24,10 @@ extern "C" { #endif +#if defined(FMC_BANK3) /* Includes ------------------------------------------------------------------*/ #include "stm32h5xx_ll_fmc.h" -#if defined(FMC_BANK3) /** @addtogroup STM32H5xx_HAL_Driver * @{ @@ -105,7 +105,6 @@ typedef struct FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This parameter is mandatory for some NAND parts after the read command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. - Example: Toshiba THTH58BYG3S0HBAI6. This parameter could be ENABLE or DISABLE Please check the Read Mode sequence in the NAND device datasheet */ } NAND_DeviceConfigTypeDef; diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_nor.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_nor.h index e164338ae0..98b2ff9d11 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_nor.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_nor.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2023 STMicroelectronics. + * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -24,10 +24,10 @@ extern "C" { #endif +#if defined(FMC_BANK1) /* Includes ------------------------------------------------------------------*/ #include "stm32h5xx_ll_fmc.h" -#if defined(FMC_BANK1) /** @addtogroup STM32H5xx_HAL_Driver * @{ @@ -184,7 +184,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); -void HAL_NOR_MspWait(const NOR_HandleTypeDef *hnor, uint32_t Timeout); +void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout); /** * @} */ @@ -235,7 +235,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); /* NOR State functions ********************************************************/ HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor); -HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(const NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); +HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rtc_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rtc_ex.h index 31f1ec8ac1..006bc66197 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rtc_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rtc_ex.h @@ -630,14 +630,15 @@ typedef struct /** @defgroup RTCEx_ActiveTamper_Async_prescaler RTCEx Active_Tamper_Asynchronous_Prescaler clock Definitions * @{ */ -#define RTC_ATAMP_ASYNCPRES_RTCCLK 0U /*!< RTCCLK */ -#define RTC_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0 /*!< RTCCLK/2 */ -#define RTC_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1 /*!< RTCCLK/4 */ -#define RTC_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/8 */ -#define RTC_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2 /*!< RTCCLK/16 */ -#define RTC_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/32 */ -#define RTC_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1) /*!< RTCCLK/64 */ -#define RTC_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/128 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK 0U /*!< RTCCLK */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0 /*!< RTCCLK/2 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1 /*!< RTCCLK/4 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/8 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2 /*!< RTCCLK/16 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/32 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1) /*!< RTCCLK/64 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/128 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_2048 (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/2048 */ /** * @} */ @@ -1798,7 +1799,8 @@ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(const RTC_HandleTypeDef *hrtc, RTC_ ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_16) || \ ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_32) || \ ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_64) || \ - ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_128)) + ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_128) || \ + ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_2048)) #define IS_RTC_BKP(__BKP__) ((__BKP__) < RTC_BKP_NUMBER) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sd.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sd.h index d1112f14ca..334b98fa86 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sd.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sd.h @@ -33,6 +33,7 @@ extern "C" { /** @addtogroup STM32H5xx_HAL_Driver * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) /** @defgroup SD SD * @brief SD HAL module driver @@ -783,6 +784,7 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); /** * @} */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sd_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sd_ex.h index aabc6010ef..8661319be8 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sd_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sd_ex.h @@ -30,6 +30,7 @@ extern "C" { /** @addtogroup STM32H5xx_HAL_Driver * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) /** @addtogroup SDEx * @brief SD HAL extended module driver @@ -105,6 +106,7 @@ void HAL_SDEx_Write_DMALnkLstBufCpltCallback(SD_HandleTypeDef *hsd); /** * @} */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sdram.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sdram.h index d98cde3658..68a51ae328 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sdram.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sdram.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2023 STMicroelectronics. + * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -24,10 +24,10 @@ extern "C" { #endif +#if defined(FMC_Bank5_6_R) /* Includes ------------------------------------------------------------------*/ #include "stm32h5xx_ll_fmc.h" -#if defined(FMC_Bank5_6_R) /** @addtogroup STM32H5xx_HAL_Driver * @{ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sram.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sram.h index b40efcbeda..2f26fb89ee 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sram.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sram.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2023 STMicroelectronics. + * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -24,10 +24,10 @@ extern "C" { #endif +#if defined(FMC_BANK1) /* Includes ------------------------------------------------------------------*/ #include "stm32h5xx_ll_fmc.h" -#if defined(FMC_BANK1) /** @addtogroup STM32H5xx_HAL_Driver * @{ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim.h index 852e52037e..efaad2c6db 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim.h @@ -1928,6 +1928,10 @@ mode. ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ ((__PRESCALER__) == TIM_ICPSC_DIV8)) +#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \ + ((__CHANNEL__) != (TIM_CHANNEL_5)) && \ + ((__CHANNEL__) != (TIM_CHANNEL_6))) + #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ ((__MODE__) == TIM_OPMODE_REPETITIVE)) @@ -1954,10 +1958,8 @@ mode. #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2)) -#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \ - ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ - (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ - ((__PERIOD__) > 0U)) +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \ + ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U)) #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ @@ -2414,18 +2416,16 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, - uint32_t BurstLength); + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, - uint32_t BurstLength, uint32_t DataLength); + uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, - uint32_t BurstLength); + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, - uint32_t BurstLength, uint32_t DataLength); + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h index 8f18e06a9f..f9e48be433 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h @@ -144,7 +144,7 @@ typedef struct __USART_HandleTypeDef uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value + uint32_t SlaveMode; /*!< Enable/Disable USART SPI Slave Mode. This parameter can be a value of @ref USARTEx_Slave_Mode */ uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart_ex.h index 588aefa524..b6282e5e84 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart_ex.h @@ -45,7 +45,7 @@ extern "C" { * @{ */ #define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */ -#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ #define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */ /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h index 6d7dc70425..968068d28f 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h @@ -377,16 +377,16 @@ extern "C" { with which VrefInt has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ /* Temperature sensor */ -#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x08FFF814UL)) /* Address of parameter TS_CAL1: On STM32H7, +#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x08FFF814UL)) /* Address of parameter TS_CAL1: On STM32H5, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x08FFF818UL)) /* Address of parameter TS_CAL2: On STM32H7, - temperature sensor ADC raw data acquired at temperature 110 DegC +#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x08FFF818UL)) /* Address of parameter TS_CAL2: On STM32H5, + temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ #define TEMPSENSOR_CAL1_TEMP (30L) /* Temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ -#define TEMPSENSOR_CAL2_TEMP (110L) /* Temperature at which temperature sensor +#define TEMPSENSOR_CAL2_TEMP (130L) /* Temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ #define TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) value @@ -2098,8 +2098,8 @@ typedef struct /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART"). */ /* Unit: us */ -#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */ -#define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization +#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 26UL) /*!< Delay for temperature sensor stabilization time */ +#define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 26UL) /*!< Delay for temperature sensor buffer stabilization time (starting from ADC enable, refer to @ref LL_ADC_Enable()) */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_comp.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_comp.h index aa69a6f974..8802505c9a 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_comp.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_comp.h @@ -603,7 +603,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(const COMP_TypeDef *COM * @note After enable from off state, comparator requires a delay * to reach reach propagation delay specification. * Refer to device datasheet, parameter "tSTART". - * @rmtoll CFGR EN LL_COMP_Enable + * @rmtoll CFGR1 EN LL_COMP_Enable * @param COMPx Comparator instance * @retval None */ @@ -614,7 +614,7 @@ __STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx) /** * @brief Disable comparator instance. - * @rmtoll CFGR EN LL_COMP_Disable + * @rmtoll CFGR1 EN LL_COMP_Disable * @param COMPx Comparator instance * @retval None */ @@ -626,7 +626,7 @@ __STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx) /** * @brief Get comparator enable state * (0: COMP is disabled, 1: COMP is enabled) - * @rmtoll CFGR EN LL_COMP_IsEnabled + * @rmtoll CFGR1 EN LL_COMP_IsEnabled * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ @@ -639,7 +639,7 @@ __STATIC_INLINE uint32_t LL_COMP_IsEnabled(const COMP_TypeDef *COMPx) * @brief Lock comparator instance. * @note Once locked, comparator configuration can be accessed in read-only. * @note The only way to unlock the comparator is a device hardware reset. - * @rmtoll CFGR LOCK LL_COMP_Lock + * @rmtoll CFGR1 LOCK LL_COMP_Lock * @param COMPx Comparator instance * @retval None */ @@ -653,7 +653,7 @@ __STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx) * (0: COMP is unlocked, 1: COMP is locked). * @note Once locked, comparator configuration can be accessed in read-only. * @note The only way to unlock the comparator is a device hardware reset. - * @rmtoll CFGR LOCK LL_COMP_IsLocked + * @rmtoll CFGR1 LOCK LL_COMP_IsLocked * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ @@ -687,6 +687,77 @@ __STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(const COMP_TypeDef *COMPx) return (uint32_t)(READ_BIT(COMPx->SR, COMP_SR_C1VAL)); } +/** + * @} + */ + +/** @defgroup COMP_LL_EF_FLAG_Management Comparator flag Management + * @{ + */ + +/** + * @brief Get comparator output trigger flag (latched) + * @rmtoll SR C1IF LL_COMP_IsActiveFlag_OutputTrig + * @param COMPx Comparator instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_COMP_IsActiveFlag_OutputTrig(const COMP_TypeDef *COMPx) +{ + return ((READ_BIT(COMPx->SR, COMP_SR_C1IF) == (COMP_SR_C1IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear comparator comparator output trigger flag (latched) + * @rmtoll ICFR CC1IF LL_COMP_ClearFlag_OutputTrig + * @param COMPx Comparator instance + * @retval None + */ +__STATIC_INLINE void LL_COMP_ClearFlag_OutputTrig(COMP_TypeDef *COMPx) +{ + SET_BIT(COMPx->ICFR, COMP_ICFR_CC1IF); +} + +/** + * @} + */ + +/** @defgroup COMP_LL_EF_IT_Management Comparartor IT management + * @{ + */ + +/** + * @brief Enable comparator output trigger interrupt + * @rmtoll ICFR ITEN LL_COMP_EnableIT_OutputTrig + * @param COMPx Comparator instance + * @retval None + */ +__STATIC_INLINE void LL_COMP_EnableIT_OutputTrig(COMP_TypeDef *COMPx) +{ + SET_BIT(COMPx->CFGR1, COMP_CFGR1_ITEN); +} + +/** + * @brief Disable comparator output trigger interrupt + * @rmtoll ICFR ITEN LL_COMP_DisableIT_OutputTrig + * @param COMPx Comparator instance + * @retval None + */ +__STATIC_INLINE void LL_COMP_DisableIT_OutputTrig(COMP_TypeDef *COMPx) +{ + CLEAR_BIT(COMPx->CFGR1, COMP_CFGR1_ITEN); +} + +/** + * @brief Get comparator output trigger interrupt state + * @rmtoll ICFR ITEN LL_COMP_IsEnabledIT_OutputTrig + * @param COMPx Comparator instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_COMP_IsEnabledIT_OutputTrig(const COMP_TypeDef *COMPx) +{ + return ((READ_BIT(COMPx->CFGR1, COMP_CFGR1_ITEN) == (COMP_CFGR1_ITEN)) ? 1UL : 0UL); +} + /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h index cb4f9ed54b..e8bdd8fe6e 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h @@ -502,14 +502,15 @@ __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) */ __STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control) { + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */ + /* Enable the MPU*/ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control; - /* Ensure MPU settings take effects */ - __DSB(); - - /* Sequence instruction fetches using update settings */ - __ISB(); + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -525,14 +526,15 @@ __STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control) */ __STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control) { + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */ + /* Enable the MPU*/ MPU_NS->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control; - /* Ensure MPU settings take effects */ - __DSB(); - - /* Sequence instruction fetches using update settings */ - __ISB(); + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ } #endif /* __ARM_FEATURE_CMSE */ @@ -543,10 +545,15 @@ __STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control) */ __STATIC_INLINE void LL_MPU_Disable(void) { - /* Make sure outstanding transfers are done */ - __DMB(); + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */ + /* Disable MPU */ WRITE_REG(MPU->CTRL, 0U); + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -557,10 +564,15 @@ __STATIC_INLINE void LL_MPU_Disable(void) */ __STATIC_INLINE void LL_MPU_Disable_NS(void) { - /* Make sure outstanding transfers are done */ - __DMB(); + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */ + /* Disable MPU*/ WRITE_REG(MPU_NS->CTRL, 0U); + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ } #endif /* __ARM_FEATURE_CMSE */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dac.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dac.h index 5061a66aed..4cc02a242b 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dac.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dac.h @@ -561,12 +561,10 @@ typedef struct * @arg @ref LL_DAC_RESOLUTION_8B * @retval DAC conversion data (unit: digital value) */ -#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ - __DAC_VOLTAGE__,\ - __DAC_RESOLUTION__) \ -((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ - / (__VREFANALOG_VOLTAGE__) \ -) +#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \ + ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ + / (__VREFANALOG_VOLTAGE__) \ + ) /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_fmc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_fmc.h index 233859af52..e406764d43 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_fmc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_fmc.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2023 STMicroelectronics. + * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_i3c.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_i3c.h index b677a44615..b534c071a1 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_i3c.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_i3c.h @@ -751,7 +751,7 @@ __STATIC_INLINE void LL_I3C_DisableArbitrationHeader(I3C_TypeDef *I3Cx) */ __STATIC_INLINE uint32_t LL_I3C_IsEnabledArbitrationHeader(const I3C_TypeDef *I3Cx) { - return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_NOARBH) == (I3C_CFGR_NOARBH)) ? 1UL : 0UL); + return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_NOARBH) == (I3C_CFGR_NOARBH)) ? 0UL : 1UL); } /** @@ -901,10 +901,10 @@ __STATIC_INLINE uint32_t LL_I3C_IsEnabledHJAck(const I3C_TypeDef *I3Cx) /** * @brief Get the data register address used for DMA transfer * @rmtoll TDR TDB0 LL_I3C_DMA_GetRegAddr\n - * TDWR TDWR LL_I3C_DMA_GetRegAddr - * RDR RXRB0 LL_I3C_DMA_GetRegAddr - * RDWR RDWR LL_I3C_DMA_GetRegAddr - * SR SR LL_I3C_DMA_GetRegAddr + * TDWR TDWR LL_I3C_DMA_GetRegAddr\n + * RDR RXRB0 LL_I3C_DMA_GetRegAddr\n + * RDWR RDWR LL_I3C_DMA_GetRegAddr\n + * SR SR LL_I3C_DMA_GetRegAddr\n * CR CR LL_I3C_DMA_GetRegAddr * @param I3Cx I3C Instance * @param Direction This parameter can be one of the following values: @@ -2401,15 +2401,14 @@ __STATIC_INLINE void LL_I3C_RequestTransfer(I3C_TypeDef *I3Cx) __STATIC_INLINE void LL_I3C_ControllerHandleMessage(I3C_TypeDef *I3Cx, uint32_t TargetAddr, uint32_t TransferSize, uint32_t Direction, uint32_t MessageType, uint32_t EndMode) { - MODIFY_REG(I3Cx->CR, I3C_CR_ADD | I3C_CR_DCNT | I3C_CR_RNW | I3C_CR_MTYPE | I3C_CR_MEND, \ - (TargetAddr << I3C_CR_ADD_Pos) | TransferSize | Direction | MessageType | EndMode); + WRITE_REG(I3Cx->CR, ((TargetAddr << I3C_CR_ADD_Pos) | TransferSize | Direction | MessageType | EndMode) \ + & (I3C_CR_ADD | I3C_CR_DCNT | I3C_CR_RNW | I3C_CR_MTYPE | I3C_CR_MEND)); } /** * @brief Handles I3C Common Command Code content on the I3C Bus as Controller. - * @rmtoll CR ADD LL_I3C_ControllerHandleCCC\n + * @rmtoll CR CCC LL_I3C_ControllerHandleCCC\n * CR DCNT LL_I3C_ControllerHandleCCC\n - * CR RNW LL_I3C_ControllerHandleCCC\n * CR MTYPE LL_I3C_ControllerHandleCCC\n * CR MEND LL_I3C_ControllerHandleCCC * @param I3Cx I3C Instance. @@ -2425,9 +2424,8 @@ __STATIC_INLINE void LL_I3C_ControllerHandleMessage(I3C_TypeDef *I3Cx, uint32_t __STATIC_INLINE void LL_I3C_ControllerHandleCCC(I3C_TypeDef *I3Cx, uint32_t CCCValue, uint32_t AddByteSize, uint32_t EndMode) { - MODIFY_REG(I3Cx->CR, I3C_CR_CCC | I3C_CR_DCNT | I3C_CR_MTYPE | I3C_CR_MEND, \ - (CCCValue << I3C_CR_CCC_Pos) | AddByteSize | EndMode | LL_I3C_CONTROLLER_MTYPE_CCC); - + WRITE_REG(I3Cx->CR, ((CCCValue << I3C_CR_CCC_Pos) | AddByteSize | EndMode | LL_I3C_CONTROLLER_MTYPE_CCC) \ + & (I3C_CR_CCC | I3C_CR_DCNT | I3C_CR_MTYPE | I3C_CR_MEND)); } /** @@ -2445,7 +2443,7 @@ __STATIC_INLINE void LL_I3C_ControllerHandleCCC(I3C_TypeDef *I3Cx, uint32_t CCCV */ __STATIC_INLINE void LL_I3C_TargetHandleMessage(I3C_TypeDef *I3Cx, uint32_t MessageType, uint32_t IBISize) { - MODIFY_REG(I3Cx->CR, I3C_CR_MTYPE | I3C_CR_DCNT, MessageType | IBISize); + WRITE_REG(I3Cx->CR, (MessageType | IBISize) & (I3C_CR_DCNT | I3C_CR_MTYPE)); } /** @@ -2476,7 +2474,7 @@ __STATIC_INLINE uint8_t LL_I3C_ReceiveData8(const I3C_TypeDef *I3Cx) */ __STATIC_INLINE void LL_I3C_TransmitData8(I3C_TypeDef *I3Cx, uint8_t Data) { - MODIFY_REG(I3Cx->TDR, I3C_TDR_TDB0, Data); + WRITE_REG(I3Cx->TDR, Data); } /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rng.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rng.h index d3349c4d4e..d0a531cc76 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rng.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rng.h @@ -318,7 +318,8 @@ __STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(const RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx) { - CLEAR_BIT(RNGx->CR, RNG_CR_NISTC); + MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_NIST_COMPLIANT | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -329,7 +330,8 @@ __STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx) { - SET_BIT(RNGx->CR, RNG_CR_NISTC); + MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_CUSTOM_NIST | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);; } /** @@ -352,7 +354,8 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(const RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1) { - MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1, Config1 << RNG_CR_RNG_CONFIG1_Pos); + MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1 | RNG_CR_CONDRST, (Config1 << RNG_CR_RNG_CONFIG1_Pos) | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -375,7 +378,8 @@ __STATIC_INLINE uint32_t LL_RNG_GetConfig1(const RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2) { - MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2, Config2 << RNG_CR_RNG_CONFIG2_Pos); + MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2 | RNG_CR_CONDRST, (Config2 << RNG_CR_RNG_CONFIG2_Pos) | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -398,7 +402,8 @@ __STATIC_INLINE uint32_t LL_RNG_GetConfig2(const RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3) { - MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3, Config3 << RNG_CR_RNG_CONFIG3_Pos); + MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3 | RNG_CR_CONDRST, (Config3 << RNG_CR_RNG_CONFIG3_Pos) | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -437,7 +442,8 @@ __STATIC_INLINE uint32_t LL_RNG_GetConfig3(const RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider) { - MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV, Divider << RNG_CR_CLKDIV_Pos); + MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, (Divider << RNG_CR_CLKDIV_Pos) | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -626,7 +632,8 @@ __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_EnableArdis(RNG_TypeDef *RNGx) { - CLEAR_BIT(RNGx->CR, RNG_CR_ARDIS); + MODIFY_REG(RNGx->CR, RNG_CR_ARDIS | RNG_CR_CONDRST, LL_RNG_ARDIS_ENABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -637,7 +644,8 @@ __STATIC_INLINE void LL_RNG_EnableArdis(RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_DisableArdis(RNG_TypeDef *RNGx) { - SET_BIT(RNGx->CR, RNG_CR_ARDIS); + MODIFY_REG(RNGx->CR, RNG_CR_ARDIS | RNG_CR_CONDRST, LL_RNG_ARDIS_DISABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rtc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rtc.h index 0a874ef650..2a32e36572 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rtc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rtc.h @@ -349,8 +349,8 @@ typedef struct /** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE * @{ */ -#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0U /*!< RTC_ALARM is open-drain output */ -#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is push-pull output */ +#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0U /*!< RTC_ALARM is push-pull output */ +#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is open-drain output */ /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_sdmmc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_sdmmc.h index f5a3aa5450..190f1acaf1 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_sdmmc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_sdmmc.h @@ -30,7 +30,7 @@ extern "C" { /** @addtogroup STM32H5xx_Driver * @{ */ - +#if defined (SDMMC1) || defined (SDMMC2) /** @addtogroup SDMMC_LL * @{ */ @@ -313,9 +313,14 @@ typedef struct #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) -#ifndef SDMMC_DATATIMEOUT +#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (ms) */ #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) #endif /* SDMMC_DATATIMEOUT */ + +#ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */ +#define SDMMC_SWDATATIMEOUT SDMMC_DATATIMEOUT +#endif /* SDMMC_SWDATATIMEOUT */ + #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U) #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U) @@ -1145,7 +1150,7 @@ uint32_t SDMMC_DMALinkedList_DisableCircularMode(SDMMC_DMALinkedListTypeDef *pLi /** * @} */ - +#endif /* SDMMC1 || SDMMC2 */ /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h index d9d84b83d2..1654520d5a 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h @@ -56,7 +56,13 @@ extern "C" { /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants * @{ */ - +#define LL_SBS_HDPL_INCREMENT_VALUE 0x6AU /*!< Define used for the HDPL increment */ +#define LL_SBS_DBG_UNLOCK (0xB4U << SBS_DBGCR_DBG_UNLOCK_Pos) /*!< Define used to unlock debug */ +#define LL_SBS_ACCESS_PORT_UNLOCK 0xB4U /*!< Define used to unlock access port */ +#define LL_SBS_DBG_CONFIG_LOCK 0xC3U /*!< Define used to lock debug configuration */ +#define LL_SBS_DBG_CONFIG_UNLOCK 0xB4U /*!< Define used to unlock debug configuration */ +#define LL_SBS_DEBUG_SEC_NSEC 0xB4U /*!< Define used to open debug for secure and non-secure */ +#define LL_SBS_DEBUG_NSEC 0x3CU /*!< Define used to open debug for non-secure only */ /** * @} */ @@ -154,10 +160,10 @@ extern "C" { /** @defgroup SYSTEM_LL_SBS_NextHDPL_Selection Next HDPL Selection * @{ */ -#define LL_SBS_OBKHDPL_INCR_0 0x00000000U -#define LL_SBS_OBKHDPL_INCR_1 SBS_NEXTHDPLCR_NEXTHDPL_0 -#define LL_SBS_OBKHDPL_INCR_2 SBS_NEXTHDPLCR_NEXTHDPL_1 -#define LL_SBS_OBKHDPL_INCR_3 SBS_NEXTHDPLCR_NEXTHDPL +#define LL_SBS_OBKHDPL_INCR_0 0x00000000U /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ +#define LL_SBS_OBKHDPL_INCR_1 SBS_NEXTHDPLCR_NEXTHDPL_0 /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ +#define LL_SBS_OBKHDPL_INCR_2 SBS_NEXTHDPLCR_NEXTHDPL_1 /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ +#define LL_SBS_OBKHDPL_INCR_3 SBS_NEXTHDPLCR_NEXTHDPL /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ /** * @} */ @@ -165,10 +171,10 @@ extern "C" { /** @defgroup SYSTEM_LL_SBS_HDPL_Value HDPL Value * @{ */ -#define LL_SBS_HDPL_VALUE_0 0x000000B4U -#define LL_SBS_HDPL_VALUE_1 0x00000051U -#define LL_SBS_HDPL_VALUE_2 0x0000008AU -#define LL_SBS_HDPL_VALUE_3 0x0000006FU +#define LL_SBS_HDPL_VALUE_0 0x000000B4U /*!< Hide protection level 0 */ +#define LL_SBS_HDPL_VALUE_1 0x00000051U /*!< Hide protection level 1 */ +#define LL_SBS_HDPL_VALUE_2 0x0000008AU /*!< Hide protection level 2 */ +#define LL_SBS_HDPL_VALUE_3 0x0000006FU /*!< Hide protection level 3 */ /** * @} */ @@ -703,7 +709,7 @@ __STATIC_INLINE void LL_SBS_FLASH_EnableECCNMI(void) */ __STATIC_INLINE void LL_SBS_IncrementHDPLValue(void) { - MODIFY_REG(SBS->HDPLCR, SBS_HDPLCR_INCR_HDPL, 0x00000006AU); + MODIFY_REG(SBS->HDPLCR, SBS_HDPLCR_INCR_HDPL, LL_SBS_HDPL_INCREMENT_VALUE); } /** @@ -758,6 +764,130 @@ __STATIC_INLINE uint32_t LL_SBS_GetOBKHDPL(void) * @} */ +/** @defgroup SYSTEM_LL_SBS_EF_Debug_Control Debug Control + * @{ + */ + +/** + * @brief Set the authenticated debug hide protection level + * @rmtoll SBS_DBGCR DBG_AUTH_HDPL LL_SBS_SetAuthDbgHDPL + * @param Level This parameter can be one of the following values: + * @arg @ref LL_SBS_HDPL_VALUE_1 + * @arg @ref LL_SBS_HDPL_VALUE_2 + * @arg @ref LL_SBS_HDPL_VALUE_3 + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetAuthDbgHDPL(uint32_t Level) +{ + MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_HDPL, (Level << SBS_DBGCR_DBG_AUTH_HDPL_Pos)); +} + +/** + * @brief Get current hide protection level + * @rmtoll SBS_DBGCR DBG_AUTH_HDPL LL_SBS_GetAuthDbgHDPL + * @retval Returned value is the hide protection level where the authenticated debug is opened: + * @arg @ref LL_SBS_HDPL_VALUE_1 + * @arg @ref LL_SBS_HDPL_VALUE_2 + * @arg @ref LL_SBS_HDPL_VALUE_3 + */ +__STATIC_INLINE uint32_t LL_SBS_GetAuthDbgHDPL(void) +{ + return (uint32_t)(READ_BIT(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_HDPL) >> SBS_DBGCR_DBG_AUTH_HDPL_Pos); +} + +#if defined(SBS_DBGCR_DBG_AUTH_SEC) +/** + * @brief Configure the authenticated debug security access. + * @rmtoll SBS_DBGCR DBG_AUTH_SEC LL_SBS_SetAuthDbgSec + * @param Control debug opening secure/non-secure or non-secure only + * This parameter can be one of the following values: + * @arg LL_SBS_DEBUG_SEC_NSEC: debug opening for secure and non-secure. + * @arg LL_SBS_DEBUG_NSEC: debug opening for non-secure only. + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetAuthDbgSec(uint32_t Security) +{ + MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_SEC, (Security << SBS_DBGCR_DBG_AUTH_SEC_Pos)); +} + +/** + * @brief Get the current value of the hide protection level. + * @rmtoll SBS_DBGCR DBG_AUTH_SEC LL_SBS_GetAuthDbgSec + * @note This function can be only used when device state is Closed. + * @retval Returned value can be one of the following values: + * @arg SBS_DEBUG_SEC_NSEC: debug opening for secure and non-secure. + * @arg any other value: debug opening for non-secure only. + */ +__STATIC_INLINE uint32_t LL_SBS_GetAuthDbgSec(void) +{ + return ((SBS->DBGCR & SBS_DBGCR_DBG_AUTH_SEC) >> SBS_DBGCR_DBG_AUTH_SEC_Pos); +} + +#endif /* SBS_DBGCR_DBG_AUTH_SEC */ + +/** + * @brief Unlock the debug + * @rmtoll SBS_DBGCR DBG_UNLOCK LL_SBS_UnlockDebug + * @retval None + */ +__STATIC_INLINE void LL_SBS_UnlockDebug(void) +{ + MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_UNLOCK, LL_SBS_DBG_UNLOCK); +} + +/** + * @brief Check if the debug is unlocked + * @rmtoll SBS_DBGCR DBG_UNLOCK LL_SBS_IsUnlockedDebug + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsUnlockedDebug(void) +{ + return ((READ_BIT(SBS->DBGCR, SBS_DBGCR_DBG_UNLOCK) == LL_SBS_DBG_UNLOCK) ? 1UL : 0UL); +} + +/** + * @brief Unlock the access port + * @rmtoll SBS_DBGCR AP_UNLOCK LL_SBS_UnlockAccessPort + * @retval None + */ +__STATIC_INLINE void LL_SBS_UnlockAccessPort(void) +{ + MODIFY_REG(SBS->DBGCR, SBS_DBGCR_AP_UNLOCK, LL_SBS_ACCESS_PORT_UNLOCK); +} + +/** + * @brief Check if the access port is unlocked + * @rmtoll SBS_DBGCR AP_UNLOCK LL_SBS_IsUnlockedAccessPort + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsUnlockedAccessPort(void) +{ + return ((READ_BIT(SBS->DBGCR, SBS_DBGCR_AP_UNLOCK) == LL_SBS_ACCESS_PORT_UNLOCK) ? 1UL : 0UL); +} + +/** + * @brief Lock the debug configuration + * @rmtoll SBS_DBGLOCKR DBGCFG_LOCK LL_SBS_LockDebugConfig + * @retval None + */ +__STATIC_INLINE void LL_SBS_LockDebugConfig(void) +{ + MODIFY_REG(SBS->DBGLOCKR, SBS_DBGLOCKR_DBGCFG_LOCK, LL_SBS_DBG_CONFIG_LOCK); +} + +/** + * @brief Check if the debug configuration is locked + * @rmtoll SBS_DBGLOCKR DBGCFG_LOCK LL_SBS_IsLockedDebugConfig + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsLockedDebugConfig(void) +{ + return ((READ_BIT(SBS->DBGLOCKR, SBS_DBGLOCKR_DBGCFG_LOCK) != LL_SBS_DBG_CONFIG_UNLOCK) ? 1UL : 0UL); +} + +/** + * @} + */ /** @defgroup SYSTEM_LL_SBS_EF_lock_Management lock Management * @{ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_tim.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_tim.h index 6cbb922a3e..bae316791b 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_tim.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_tim.h @@ -1016,11 +1016,11 @@ typedef struct #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */ #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */ #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */ -#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */ -#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */ -#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */ -#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */ -#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */ +#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */ +#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */ +#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */ +#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */ +#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */ #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */ #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */ #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */ @@ -1062,7 +1062,7 @@ typedef struct #define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_3 ) /*!< ETR input is connected to TIM5 ETR */ #endif /* TIM5 */ #if defined(ETH_NS) -#define LL_TIM_TIM2_ETRSOURCE_ETH_PPS (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_3 ) /*!< ETR input is connected to ETH PPS */ +#define LL_TIM_TIM2_ETRSOURCE_ETH_PPS (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_3 ) /*!< ETR input is connected to ETH PPS */ #endif /* ETH_NS */ /** * @} @@ -1083,7 +1083,7 @@ typedef struct #define LL_TIM_TIM3_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */ #endif /* TIM5 */ #if defined(ETH_NS) -#define LL_TIM_TIM3_ETRSOURCE_ETH_PPS (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_3 ) /*!< ETR input is connected to ETH PPS */ +#define LL_TIM_TIM3_ETRSOURCE_ETH_PPS (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_3 ) /*!< ETR input is connected to ETH PPS */ #endif /* ETH_NS */ /** * @} @@ -1094,8 +1094,8 @@ typedef struct * @{ */ #define LL_TIM_TIM4_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ -#define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */ -#define LL_TIM_TIM4_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */ +#define LL_TIM_TIM4_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */ +#define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */ #define LL_TIM_TIM4_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */ /** * @} @@ -1320,7 +1320,7 @@ typedef struct #define LL_TIM_DMABURST_LENGTH_23TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 23 registers starting from the DMA burst base address */ #define LL_TIM_DMABURST_LENGTH_24TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 24 registers starting from the DMA burst base address */ #define LL_TIM_DMABURST_LENGTH_25TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3) /*!< Transfer is done to 25 registers starting from the DMA burst base address */ -#define LL_TIM_DMABURST_LENGTH_26TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 26 registers starting from the DMA burst base address */ +#define LL_TIM_DMABURST_LENGTH_26TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 26 registers starting from the DMA burst base address */ /** * @} */ @@ -3896,9 +3896,7 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * TIM1: any combination of ETR_RMP where * * @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO - @if STM32H503xx * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1 (*) - @endif * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 @@ -3906,9 +3904,7 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * TIM2: any combination of ETR_RMP where * * @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO - @if STM32H503xx * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1 (*) - @endif * @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE * @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSA (*) * @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (*) @@ -3921,9 +3917,7 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * TIM3: any combination of ETR_RMP where * * @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO - @if STM32H503xx * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1 (*) - @endif * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (*) * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM5_ETR (*) @@ -3932,8 +3926,8 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * TIM4: any combination of ETR_RMP where (**) * * @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO + * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM2_ETR * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR - * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM4_ETR * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR * * TIM5: any combination of ETR_RMP where (**) @@ -4357,9 +4351,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 * @param Source This parameter can be one of the following values: * @arg @ref LL_TIM_BKIN_SOURCE_BKIN - @if STM32H503xx * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*) - @endif * * (*) Value not defined in all devices. * @retval None @@ -4384,9 +4376,7 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 * @param Source This parameter can be one of the following values: * @arg @ref LL_TIM_BKIN_SOURCE_BKIN - @if STM32H503xx * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*) - @endif * * (*) Value not defined in all devices. * @retval None @@ -4411,9 +4401,7 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 * @param Source This parameter can be one of the following values: * @arg @ref LL_TIM_BKIN_SOURCE_BKIN - @if STM32H503xx * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*) - @endif * @param Polarity This parameter can be one of the following values: * @arg @ref LL_TIM_BKIN_POLARITY_LOW * @arg @ref LL_TIM_BKIN_POLARITY_HIGH @@ -6268,8 +6256,7 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T * @} */ -#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 \ - || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */ +#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */ /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32H5xx_HAL_Driver/Release_Notes.html index 69e16ce14f..0b35839fc3 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32H5xx_HAL_Driver/Release_Notes.html @@ -40,11 +40,79 @@

Purpose

Update History

- +

Main Changes

    -
  • First official release of HAL and LL drivers for STM32H573xx / STM32H563xx / STM32H562xx / STM32H503xx devices
    • +

  • Maintenance Release of HAL and LL drivers for STM32H573xx / STM32H563xx / STM32H562xx / STM32H503xx devices

    +
      +
    • HAL drivers : +
        +
      • HAL CRYP driver: +
          +
        • Add management of interleave mode with new APIs : +
            +
          • HAL_CRYP_SaveContext() and HAL_CRYP_RestoreContext().
            • +
          • Add CRYP_ContextTypeDef CRYP Context Structure.
            • +
          • +
        • +
      • HAL Generic driver: +
          +
        • [SBS] Add APIs for Debug Control: +
            +
          • HAL_SBS_OpenAccessPort()
            • +
          • HAL_SBS_OpenDebug()
            • +
          • HAL_SBS_ConfigDebugLevel() / HAL_SBS_GetDebugLevel()
            • +
          • HAL_SBS_LockDebugConfig()
            • +
          • HAL_SBS_ConfigDebugSecurity() / HAL_SBS_GetDebugSecurity()
            • +
          • +
        • +
      • HAL I2C driver: +
          +
        • Update I2C_ITMasterCplt() to fix issue related to TX IRQ not being disabled after data transfer.
          • +
        • Fix issue related to HAL_I2C_IsDeviceReady().
          • +
        • Fix issue related to switching from 10 bits to 7 bits addressing modes.
          • +
        • +
      • HAL I3C driver: +
          +
        • Fix arbitration header disabling when using HAL_I3C_AddDescToFrame() with successive options.
          • +
        • Add multiple transfer for Sensor Communication and Multiple CCC RX/TX command with the same interface.
          • +
        • Add Interface to check the availability of I2C or I3C device in the Bus.
          • +
        • +
      • HAL RTC Driver: +
          +
        • Update possible values of Active tamper RTC asynchronous prescaler clock selection field.
          • +
        • +
      • HAL SAI Driver: +
          +
        • Reorder the call to SAI_Disable() to fix issue in HAL SAI abort and DMA stop functions.
          • +
        • +
      • HAL TIMER driver: +
          +
        • Fix of issue related to channel being systematically disabled by HAL_TIM_OC_ConfigChannel() API.
          • +
        • Fix assert check in HAL_TIM_OC_Start_IT().
          • +
        • Enhance performance by removing multiple volatile reads or writes in interrupt handler.
          • +
        • +
      • +
    • LL drivers : +
        +
      • LL SYSTEM driver: +
          +
        • [SBS] Add APIs for Debug Control: +
            +
          • LL_SBS_SetAuthDbgHDPL() / LL_SBS_GetAuthDbgHDPL()
            • +
          • LL_SBS_SetAuthDbgSec() / LL_SBS_GetAuthDbgSec()
            • +
          • LL_SBS_UnlockDebug() / LL_SBS_IsUnlockedDebug()
            • +
          • LL_SBS_UnlockAccessPort() / LL_SBS_IsUnlockedAccessPort()
            • +
          • LL_SBS_LockDebugConfig() / LL_SBS_IsLockedDebugConfig()
            • +
          • +
        • +
      • LL RTC Driver: +
          +
        • Update possible values of Active tamper RTC asynchronous prescaler clock selection field.
          • +
        • +
      • +

Known Limitations

    @@ -52,6 +120,23 @@

    Known Limitations

Backward compatibility

    +
  • No compatibility break
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • First official release of HAL and LL drivers for STM32H573xx / STM32H563xx / STM32H562xx / STM32H503xx devices
    • +
+

Known Limitations

+
    +
  • None
    • +
+

Backward compatibility

+
  • Not Applicable
diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c index ebc241e631..b07887a4df 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c @@ -48,10 +48,10 @@ /* Private typedef ---------------------------------------------------------------------------------------------------*/ /* Private define ----------------------------------------------------------------------------------------------------*/ /** - * @brief STM32H5xx HAL Driver version number 1.0.0 + * @brief STM32H5xx HAL Driver version number 1.1.0 */ #define __STM32H5XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32H5XX_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ +#define __STM32H5XX_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ #define __STM32H5XX_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32H5XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32H5XX_HAL_VERSION ((__STM32H5XX_HAL_VERSION_MAIN << 24U)\ @@ -63,6 +63,13 @@ #define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms */ #endif /* VREFBUF */ +/* Value used to increment hide protection level */ +#define SBS_HDPL_INCREMENT_VALUE (uint8_t)0x6A + +/* Value used to lock/unlock debug functionalities */ +#define SBS_DEBUG_LOCK_VALUE (uint8_t)0xC3 +#define SBS_DEBUG_UNLOCK_VALUE (uint8_t)0xB4 + /* Private macro -----------------------------------------------------------------------------------------------------*/ /* Private variables -------------------------------------------------------------------------------------------------*/ /* Exported variables ------------------------------------------------------------------------------------------------*/ @@ -534,12 +541,12 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void) * @} */ -/** @defgroup HAL_Exported_Functions_Group4 HAL SBS configuration functions - * @brief HAL SBS configuration functions +/** @defgroup HAL_Exported_Functions_Group4 HAL VREFBUF Control functions + * @brief HAL VREFBUF Control functions * @verbatim ======================================================================================================================= - ##### HAL SBS configuration functions ##### + ##### HAL VREFBUF Control functions ##### ======================================================================================================================= [..] This section provides functions allowing to: (+) Configure the Voltage reference buffer @@ -636,6 +643,29 @@ void HAL_DisableVREFBUF(void) } #endif /* VREFBUF */ +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group5 HAL SBS configuration functions + * @brief HAL SBS configuration functions + * +@verbatim + ======================================================================================================================= + ##### HAL SBS configuration functions ##### + ======================================================================================================================= + [..] This section provides functions allowing to: + (+) Select the Ethernet PHY Interface + (+) Enable/Disable the VDD I/Os Compensation Cell + (+) Code selection/configuration for the VDD I/O Compensation cell + (+) Get ready flag status of VDD I/Os Compensation cell + (+) Get PMOS/NMOS compensation value of the I/Os supplied by VDD + (+) Enable/Disable the NMI in case of double ECC error in FLASH Interface + +@endverbatim + * @{ + */ + #if defined(SBS_PMCR_ETH_SEL_PHY) /** * @brief Ethernet PHY Interface Selection either MII or RMII @@ -747,7 +777,7 @@ uint32_t HAL_SBS_GetVddIO2CompensationCellReadyFlag(void) } /** - * @brief Code selection for the VDD I/O Compensation cell + * @brief Code configuration for the VDD I/O Compensation cell * @param SBS_PMOSCode: PMOS compensation code * This code is applied to the VDD I/O compensation cell when the CS1 bit of the * SBS_CCSR is set @@ -766,7 +796,7 @@ void HAL_SBS_VDDCompensationCodeConfig(uint32_t SBS_PMOSCode, uint32_t SBS_NMOSC } /** - * @brief Code selection for the VDDIO I/O Compensation cell + * @brief Code configuration for the VDDIO I/O Compensation cell * @param SBS_PMOSCode: PMOS compensation code * This code is applied to the VDDIO I/O compensation cell when the CS2 bit of the * SBS_CCSR is set @@ -821,36 +851,54 @@ uint32_t HAL_SBS_GetPMOSVddIO2CompensationValue(void) return (uint32_t)(READ_BIT(SBS->CCVALR, SBS_CCVALR_APSRC2) >> SBS_CCVALR_APSRC2_Pos); } -#if defined(SBS_EPOCHSELCR_EPOCH_SEL) /** - * @brief Select EPOCH security sent to SAES IP to encrypt/decrypt keys - * @param Epoch_Selection: Select EPOCH security - * This parameter can be one of the following values: - * @arg SBS_EPOCH_SEL_SECURE : EPOCH secure selected. - * @arg SBS_EPOCH_SEL_NONSECURE : EPOCH non secure selected. - * @arg SBS_EPOCH_SEL_PUFCHECK : EPOCH all zeros for PUF integrity check. + * @brief Disable the NMI in case of double ECC error in FLASH Interface. + * * @retval None */ -void HAL_SBS_EPOCHSelection(uint32_t Epoch_Selection) +void HAL_SBS_FLASH_DisableECCNMI(void) { - /* Check the parameter */ - assert_param(IS_SBS_EPOCH_SELECTION(Epoch_Selection)); + SET_BIT(SBS->ECCNMIR, SBS_ECCNMIR_ECCNMI_MASK_EN); +} - MODIFY_REG(SBS->EPOCHSELCR, SBS_EPOCHSELCR_EPOCH_SEL, (uint32_t)(Epoch_Selection)); +/** + * @brief Enable the NMI in case of double ECC error in FLASH Interface. + * + * @retval None + */ +void HAL_SBS_FLASH_EnableECCNMI(void) +{ + CLEAR_BIT(SBS->ECCNMIR, SBS_ECCNMIR_ECCNMI_MASK_EN); } /** - * @brief Get EPOCH security selection - * @retval Returned value can be one of the following values: - * @arg SBS_EPOCH_SEL_SECURE : EPOCH secure selected. - * @arg SBS_EPOCH_SEL_NONSECURE : EPOCH non secure selected. - * @arg SBS_EPOCH_SEL_PUFCHECK : EPOCH all zeros for PUF integrity check. + * @brief Check if the NMI is Enabled in case of double ECC error in FLASH Interface. + * + * @retval State of bit (1 or 0). */ -uint32_t HAL_SBS_GetEPOCHSelection(void) +uint32_t HAL_SBS_FLASH_ECCNMI_IsDisabled(void) { - return (uint32_t)(READ_BIT(SBS->EPOCHSELCR, SBS_EPOCHSELCR_EPOCH_SEL)); + return ((READ_BIT(SBS->ECCNMIR, SBS_ECCNMIR_ECCNMI_MASK_EN) == SBS_ECCNMIR_ECCNMI_MASK_EN) ? 1UL : 0UL); } -#endif /* SBS_EPOCHSELCR_EPOCH_SEL */ + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group6 HAL SBS Boot control functions + * @brief HAL SBS Boot functions + * +@verbatim + ======================================================================================================================= + ##### HAL SBS Boot control functions ##### + ======================================================================================================================= + [..] This section provides functions allowing to: + (+) Increment the HDPL value + (+) Get the HDPL value + +@endverbatim + * @{ + */ /** * @brief Increment by 1 the HDPL value @@ -858,7 +906,7 @@ uint32_t HAL_SBS_GetEPOCHSelection(void) */ void HAL_SBS_IncrementHDPLValue(void) { - MODIFY_REG(SBS->HDPLCR, SBS_HDPLCR_INCR_HDPL, 0x00000006AU); + MODIFY_REG(SBS->HDPLCR, SBS_HDPLCR_INCR_HDPL, SBS_HDPL_INCREMENT_VALUE); } /** @@ -876,6 +924,57 @@ uint32_t HAL_SBS_GetHDPLValue(void) return (uint32_t)(READ_BIT(SBS->HDPLSR, SBS_HDPLSR_HDPL)); } +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group7 HAL SBS Hardware secure storage control functions + * @brief HAL SBS Hardware secure storage functions + * +@verbatim + ======================================================================================================================= + ##### HAL SBS Hardware secure storage control functions ##### + ======================================================================================================================= + [..] This section provides functions allowing to: + (+) Select EPOCH security sent to SAES IP + (+) Set/Get EPOCH security selection + (+) Set/Get the OBK-HDPL Value + +@endverbatim + * @{ + */ + +#if defined(SBS_EPOCHSELCR_EPOCH_SEL) +/** + * @brief Select EPOCH security sent to SAES IP to encrypt/decrypt keys + * @param Epoch_Selection: Select EPOCH security + * This parameter can be one of the following values: + * @arg SBS_EPOCH_SEL_SECURE : EPOCH secure selected. + * @arg SBS_EPOCH_SEL_NONSECURE : EPOCH non secure selected. + * @arg SBS_EPOCH_SEL_PUFCHECK : EPOCH all zeros for PUF integrity check. + * @retval None + */ +void HAL_SBS_EPOCHSelection(uint32_t Epoch_Selection) +{ + /* Check the parameter */ + assert_param(IS_SBS_EPOCH_SELECTION(Epoch_Selection)); + + MODIFY_REG(SBS->EPOCHSELCR, SBS_EPOCHSELCR_EPOCH_SEL, (uint32_t)(Epoch_Selection)); +} + +/** + * @brief Get EPOCH security selection + * @retval Returned value can be one of the following values: + * @arg SBS_EPOCH_SEL_SECURE : EPOCH secure selected. + * @arg SBS_EPOCH_SEL_NONSECURE : EPOCH non secure selected. + * @arg SBS_EPOCH_SEL_PUFCHECK : EPOCH all zeros for PUF integrity check. + */ +uint32_t HAL_SBS_GetEPOCHSelection(void) +{ + return (uint32_t)(READ_BIT(SBS->EPOCHSELCR, SBS_EPOCHSELCR_EPOCH_SEL)); +} +#endif /* SBS_EPOCHSELCR_EPOCH_SEL */ + #if defined(SBS_NEXTHDPLCR_NEXTHDPL) /** * @brief Set the OBK-HDPL Value. @@ -911,41 +1010,126 @@ uint32_t HAL_SBS_GetOBKHDPL(void) #endif /* SBS_NEXTHDPLCR_NEXTHDPL */ /** - * @brief Disable the NMI in case of double ECC error in FLASH Interface. + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group8 HAL SBS Debug control functions + * @brief HAL SBS Debug functions * +@verbatim + ======================================================================================================================= + ##### SBS Debug control functions ##### + ======================================================================================================================= + [..] This section provides functions allowing to: + (+) Open the device access port + (+) Open the debug + (+) Configure the authenticated debug HDPL + (+) Get the current value of the hide protection level + (+) Lock the access to the debug control register + (+) Configure/Get the authenticated debug security access + +@endverbatim + * @{ + */ + +/** + * @brief Open the device access port. + * @note This function can be only used when device state is Closed. * @retval None */ -void HAL_SBS_FLASH_DisableECCNMI(void) +void HAL_SBS_OpenAccessPort(void) { - SET_BIT(SBS->ECCNMIR, SBS_ECCNMIR_ECCNMI_MASK_EN); + MODIFY_REG(SBS->DBGCR, SBS_DBGCR_AP_UNLOCK, SBS_DEBUG_UNLOCK_VALUE); } /** - * @brief Enable the NMI in case of double ECC error in FLASH Interface. - * + * @brief Open the debug when the hide protection level is authorized. + * @note This function can be only used when device state is Closed. * @retval None */ -void HAL_SBS_FLASH_EnableECCNMI(void) +void HAL_SBS_OpenDebug(void) { - CLEAR_BIT(SBS->ECCNMIR, SBS_ECCNMIR_ECCNMI_MASK_EN); + MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_UNLOCK, (SBS_DEBUG_UNLOCK_VALUE << SBS_DBGCR_DBG_UNLOCK_Pos)); } /** - * @brief Check if the NMI is Enabled in case of double ECC error in FLASH Interface. - * - * @retval State of bit (1 or 0). + * @brief Configure the authenticated debug hide protection level. + * @note This function can be only used when device state is Closed. + * @param Level Hide protection level where the authenticated debug opens + * This value is one of @ref SBS_HDPL_Value (except SBS_HDPL_VALUE_0) + * @retval HAL_OK if parameter is correct + * HAL_ERROR otherwise */ -uint32_t HAL_SBS_FLASH_ECCNMI_IsDisabled(void) +HAL_StatusTypeDef HAL_SBS_ConfigDebugLevel(uint32_t Level) { - return ((READ_BIT(SBS->ECCNMIR, SBS_ECCNMIR_ECCNMI_MASK_EN) == SBS_ECCNMIR_ECCNMI_MASK_EN) ? 1UL : 0UL); + /* Check the parameter */ + assert_param(IS_SBS_HDPL(Level)); + + if (Level != SBS_HDPL_VALUE_0) + { + MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_HDPL, (Level << SBS_DBGCR_DBG_AUTH_HDPL_Pos)); + return HAL_OK; + } + else + { + return HAL_ERROR; + } } +/** + * @brief Get the current value of the hide protection level. + * @note This function can be only used when device state is Closed. + * @retval Current hide protection level + * This value is one of @ref SBS_HDPL_Value + */ +uint32_t HAL_SBS_GetDebugLevel(void) +{ + return ((SBS->DBGCR & SBS_DBGCR_DBG_AUTH_HDPL) >> SBS_DBGCR_DBG_AUTH_HDPL_Pos); +} + +/** + * @brief Lock the access to the debug control register. + * @note This function can be only used when device state is Closed. + * @note locking the current debug configuration is released only by a reset. + * @retval None + */ +void HAL_SBS_LockDebugConfig(void) +{ + MODIFY_REG(SBS->DBGLOCKR, SBS_DBGLOCKR_DBGCFG_LOCK, SBS_DEBUG_LOCK_VALUE); +} + +#if defined(SBS_DBGCR_DBG_AUTH_SEC) +/** + * @brief Configure the authenticated debug security access. + * @param Control debug opening secure/non-secure or non-secure only + * This parameter can be one of the following values: + * @arg SBS_DEBUG_SEC_NSEC: debug opening for secure and non-secure. + * @arg SBS_DEBUG_NSEC: debug opening for non-secure only. + * @retval None + */ +void HAL_SBS_ConfigDebugSecurity(uint32_t Security) +{ + MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_SEC, (Security << SBS_DBGCR_DBG_AUTH_SEC_Pos)); +} + +/** + * @brief Get the current value of the hide protection level. + * @note This function can be only used when device state is Closed. + * @retval Returned value can be one of the following values: + * @arg SBS_DEBUG_SEC_NSEC: debug opening for secure and non-secure. + * @arg SBS_DEBUG_NSEC: debug opening for non-secure only. + */ +uint32_t HAL_SBS_GetDebugSecurity(void) +{ + return ((SBS->DBGCR & SBS_DBGCR_DBG_AUTH_SEC) >> SBS_DBGCR_DBG_AUTH_SEC_Pos); +} +#endif /* SBS_DBGCR_DBG_AUTH_SEC */ /** * @} */ -/** @defgroup HAL_Exported_Functions_Group5 HAL SBS lock management functions +/** @defgroup HAL_Exported_Functions_Group9 HAL SBS lock management functions * @brief SBS lock management functions. * @verbatim @@ -1014,7 +1198,7 @@ HAL_StatusTypeDef HAL_SBS_GetLock(uint32_t *pItem) * @} */ -/** @defgroup HAL_Exported_Functions_Group6 HAL SBS attributes management functions +/** @defgroup HAL_Exported_Functions_Group10 HAL SBS attributes management functions * @brief SBS attributes management functions. * @verbatim diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c index 716f0548fb..996430e2cb 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c @@ -488,6 +488,8 @@ __weak void HAL_SYSTICK_Callback(void) */ void HAL_MPU_Enable(uint32_t MPU_Control) { + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */ + /* Enable the MPU */ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; @@ -495,9 +497,9 @@ void HAL_MPU_Enable(uint32_t MPU_Control) SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; /* Follow ARM recommendation with */ - /* - Data Memory Barrier and Instruction Synchronization to insure MPU usage */ - __DMB(); /* Force memory writes before continuing */ - __ISB(); /* Flush and refill pipeline with updated permissions */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -514,6 +516,8 @@ void HAL_MPU_Enable(uint32_t MPU_Control) */ void HAL_MPU_Enable_NS(uint32_t MPU_Control) { + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */ + /* Enable the MPU */ MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; @@ -521,9 +525,9 @@ void HAL_MPU_Enable_NS(uint32_t MPU_Control) SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; /* Follow ARM recommendation with */ - /* - Data Memory Barrier and Instruction Synchronization to insure MPU usage */ - __DMB(); /* Force memory writes before continuing */ - __ISB(); /* Flush and refill pipeline with updated permissions */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ } #endif /* __ARM_FEATURE_CMSE */ @@ -535,8 +539,16 @@ void HAL_MPU_Disable(void) { __DMB(); /* Force any outstanding transfers to complete before disabling MPU */ + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + /* Disable the MPU */ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -548,8 +560,16 @@ void HAL_MPU_Disable_NS(void) { __DMB(); /* Force any outstanding transfers to complete before disabling MPU */ + /* Disable fault exceptions */ + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + /* Disable the MPU */ MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ } #endif /* __ARM_FEATURE_CMSE */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp.c index 88a27b90be..e712ccc5e6 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp.c @@ -306,10 +306,10 @@ * @{ */ #define CRYP_GENERAL_TIMEOUT 82U -#define CRYP_TIMEOUT_KEYPREPARATION 82U /* The latency of key preparation operation is 82 clock cycles.*/ -#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey +#define CRYP_TIMEOUT_KEYPREPARATION 82U /*!< The latency of key preparation operation is 82 clock cycles.*/ +#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /*!< The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/ -#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/ +#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /*!< The latency of GCM/CCM header phase is 290 clock cycles.*/ #define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */ #define CRYP_PHASE_PROCESS 0x00000002U /*!< CRYP peripheral is in processing phase */ @@ -421,6 +421,9 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp); (+) Data Type : 32,16, 8 or 1bit (+) AlgoMode : ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard. (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef + (+) For interleave mode, API HAL_CRYP_SaveContext and HAL_CRYP_RestoreContext to be used to save then Restore CRYP + configuration and parameters. CRYP_IVCONFIG_ONCE should be selected for KeyIVConfigSkip parameter. + Only polling mode is supported, interleave mode should be used with HAL_CRYP_Encrypt and HAL_CRYP_Decrypt API. @endverbatim * @{ @@ -436,7 +439,9 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp); HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) { uint32_t cr_value; +#if defined(SAES) uint32_t tickstart; +#endif /* SAES */ /* Check the CRYP handle allocation */ if (hcryp == NULL) @@ -869,33 +874,34 @@ HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRY { HAL_StatusTypeDef status = HAL_OK; + if (hcryp->State == HAL_CRYP_STATE_READY) { switch (CallbackID) { case HAL_CRYP_INPUT_COMPLETE_CB_ID : - hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */ + hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /*!< Legacy weak InCpltCallback */ break; case HAL_CRYP_OUTPUT_COMPLETE_CB_ID : - hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */ + hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /*!< Legacy weak OutCpltCallback */ break; case HAL_CRYP_ERROR_CB_ID : - hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */ + hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /*!< Legacy weak ErrorCallback */ break; case HAL_CRYP_MSPINIT_CB_ID : - hcryp->MspInitCallback = HAL_CRYP_MspInit; + hcryp->MspInitCallback = HAL_CRYP_MspInit; /*!< Legacy weak MspInit */ break; case HAL_CRYP_MSPDEINIT_CB_ID : - hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; + hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /*!< Legacy weak MspDeInit */ break; default : /* Update the error code */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;/*!< Legacy weak ERROR INVALID CALLBACK */ /* Return error status */ status = HAL_ERROR; break; @@ -1112,6 +1118,120 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp) } #endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */ +/** + * @brief CRYP peripheral parameters storage when processing Interleaved mode . + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pcont pointer to a CRYP_ContextTypeDef structure where CRYP parameters will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_SaveContext(CRYP_HandleTypeDef *hcryp, CRYP_ContextTypeDef *pcont) +{ + /* Check the CRYP handle allocation */ + if ((hcryp == NULL) || (pcont == NULL)) + { + return HAL_ERROR; + } + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Save CRYP handle parameters */ + pcont->DataType = (uint32_t)(hcryp->Init.DataType); + pcont->KeySize = (uint32_t)(hcryp->Init.KeySize); + pcont->pKey = hcryp->Init.pKey; + pcont->pInitVect = hcryp->Init.pInitVect; + pcont->Algorithm = (uint32_t)(hcryp->Init.Algorithm); + pcont->DataWidthUnit = (uint32_t)(hcryp->Init.DataWidthUnit); + pcont->KeyIVConfigSkip = (uint32_t)(hcryp->Init.KeyIVConfigSkip); + pcont->KeyMode = (uint32_t)(hcryp->Init.KeyMode); + pcont->Phase = (uint32_t)(hcryp->Phase); + pcont->KeyIVConfig = (uint32_t)(hcryp->KeyIVConfig); + + /* Save CRYP CR register content */ + pcont->CR_Reg = READ_REG(hcryp->Instance->CR); + + /* Save IER register content */ + pcont->IER_Reg = READ_BIT(hcryp->Instance->IER, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + + if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \ + (hcryp->Init.Algorithm == CRYP_AES_CTR)) + { + /* Save Initialisation Vector registers */ + pcont->IVR0_Reg = READ_REG(hcryp->Instance->IVR0); + pcont->IVR1_Reg = READ_REG(hcryp->Instance->IVR1); + pcont->IVR2_Reg = READ_REG(hcryp->Instance->IVR2); + pcont->IVR3_Reg = READ_REG(hcryp->Instance->IVR3); + } + + /* To load Key for next piece of message */ + hcryp->KeyIVConfig = 0; + + return HAL_OK; + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + return HAL_ERROR; + } + +} + +/** + * @brief Restore CRYP parameters needed for Interleaved mode. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pcont pointer to a CRYP_ContextTypeDef structure that contains CRYP parameters stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_RestoreContext(CRYP_HandleTypeDef *hcryp, CRYP_ContextTypeDef *pcont) +{ + /* Check the CRYP handle allocation */ + if ((hcryp == NULL) || (pcont == NULL)) + { + return HAL_ERROR; + } + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Restore CRYP handle parameters */ + hcryp->Init.DataType = pcont->DataType; + hcryp->Init.KeySize = pcont->KeySize; + hcryp->Init.pKey = pcont->pKey; + hcryp->Init.pInitVect = pcont->pInitVect; + hcryp->Init.Algorithm = pcont->Algorithm; + hcryp->Init.DataWidthUnit = pcont->DataWidthUnit; + hcryp->Init.KeyIVConfigSkip = pcont->KeyIVConfigSkip; + hcryp->Init.KeyMode = pcont->KeyMode; + hcryp->Phase = pcont->Phase; + hcryp->KeyIVConfig = pcont->KeyIVConfig; + + /* Restore CRYP CR register content */ + WRITE_REG(hcryp->Instance->CR, (uint32_t)(pcont->CR_Reg)); + + /* Restore CRYP IER register content */ + WRITE_REG(hcryp->Instance->IER, (uint32_t)(pcont->IER_Reg)); + + if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \ + (hcryp->Init.Algorithm == CRYP_AES_CTR)) + { + /* Restore Initialisation Vector registers */ + WRITE_REG(hcryp->Instance->IVR0, (uint32_t)(pcont->IVR0_Reg)); + WRITE_REG(hcryp->Instance->IVR1, (uint32_t)(pcont->IVR1_Reg)); + WRITE_REG(hcryp->Instance->IVR2, (uint32_t)(pcont->IVR2_Reg)); + WRITE_REG(hcryp->Instance->IVR3, (uint32_t)(pcont->IVR3_Reg)); + } + return HAL_OK; + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + return HAL_ERROR; + } +} + /** * @} */ @@ -2035,7 +2155,7 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ uint32_t tickstart; - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + if ((hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) || (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE)) { if (hcryp->KeyIVConfig == 1U) { @@ -2052,57 +2172,80 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti } } - if ((dokeyivconfig == 1U) && (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)) + if (dokeyivconfig == 1U) { - if (hcryp->Instance == AES) + if ((hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) || \ + (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ALWAYS)) { - /* Set the Key */ - if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) - { - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - } - else /* After sharing the key, AES should set KMOD[1:0] to 00.*/ - { - hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; - } - } - else - { - /* We should re-write Key, in the case where we change key after first operation */ - if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + if (hcryp->Instance == AES) { /* Set the Key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /* After sharing the key, AES should set KMOD[1:0] to 00.*/ + { + hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; + } } - /* Get tick */ - tickstart = HAL_GetTick(); - - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_KEYVALID)) + else { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) + /* We should re-write Key, in the case where we change key after first operation */ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + /* Get tick */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_KEYVALID)) { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - __HAL_UNLOCK(hcryp); - return HAL_ERROR; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } } } } + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector */ + CRYP_SetIV(hcryp); + } } - if (hcryp->Init.Algorithm != CRYP_AES_ECB) + /* key & IV configuration for CBC and CTR in interleave mode */ + if (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE) { - /* Set the Initialization Vector */ - CRYP_SetIV(hcryp); + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ + CRYP_SetIV(hcryp); + } } } /* If (dokeyivconfig == 1U) */ - + else + { + /* interleave mode Key configuration */ + if (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + } /* Peripheral Key configuration to not do, IV to configure for CBC */ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYNOCONFIG) { @@ -2227,10 +2370,6 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp) if (hcryp->Size != 0U) { - - /* Enable computation complete flag and Key, Read and Write error interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); - /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); @@ -2243,6 +2382,9 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; + + /* Enable computation complete flag and Key, Read and Write error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); } else { @@ -2266,7 +2408,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti uint16_t outcount; /* Temporary CrypOutCount Value */ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + if ((hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) || (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE)) { if (hcryp->KeyIVConfig == 1U) { @@ -2295,7 +2437,8 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); /* Set the Key */ - if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + if ((hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) || \ + (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ALWAYS)) { if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) { @@ -2307,6 +2450,17 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti } } + /* interleave mode Key configuration */ + else if (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else + { + /* Nothing to do */ + } + /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); @@ -2388,7 +2542,47 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti } } /* if (dokeyivconfig == 1U) */ + else /* if (dokeyivconfig == 0U) */ + { + /* interleave mode Key configuration */ + if (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE) + { + if (hcryp->Instance == AES) + { + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/ + { + /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_NORMAL); + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else /*Algorithm CTR */ + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + } + } + + } /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -2404,7 +2598,6 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti incount = hcryp->CrypInCount; outcount = hcryp->CrypOutCount; } - /* Disable CRYP */ __HAL_CRYP_DISABLE(hcryp); @@ -2576,9 +2769,6 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) hcryp->Phase = CRYP_PHASE_PROCESS; if (hcryp->Size != 0U) { - /* Enable computation complete flag and error interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); - /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); @@ -2591,6 +2781,9 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; + + /* Enable computation complete flag and error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); } else { diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp_ex.c index b0bba39b4b..3637c02260 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp_ex.c @@ -369,6 +369,10 @@ HAL_StatusTypeDef HAL_CRYPEx_WrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInput /* AES decryption */ status = CRYPEx_KeyEncrypt(hcryp, Timeout); break; + case CRYP_AES_CTR: + /* AES Key generation */ + status = CRYPEx_KeyGeneration(hcryp, Timeout); + break; default: hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; status = HAL_ERROR; @@ -389,7 +393,7 @@ HAL_StatusTypeDef HAL_CRYPEx_WrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInput * @brief Unwrap (Decrypt) application keys. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInput Pointer to the Key buffer to decrypt in case of ECB or CBC. + * @param pInput Pointer to the Key buffer to decrypt or generated key in case of CTR. * @param Timeout Specify Timeout value * @retval HAL status */ @@ -461,7 +465,7 @@ HAL_StatusTypeDef HAL_CRYPEx_UnwrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInp ============================================================================== ##### Encrypt and Decrypt Shared key functions ##### ============================================================================== - [..] This section provides API allowing to Encrypt/Decrypt Shared key + [..] This section provides API allowing to Encrypt and Decrypt Shared key @endverbatim * @{ @@ -514,6 +518,10 @@ HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_ /* AES decryption */ status = CRYPEx_KeyEncrypt(hcryp, Timeout); break; + case CRYP_AES_CTR: + /* AES CTR key generation */ + status = CRYPEx_KeyGeneration(hcryp, Timeout); + break; default: hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; status = HAL_ERROR; @@ -574,6 +582,10 @@ HAL_StatusTypeDef HAL_CRYPEx_DecryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_ /* AES decryption */ status = CRYPEx_KeyDecrypt(hcryp, Timeout); break; + case CRYP_AES_CTR: + /* AES CTR key generation */ + status = CRYPEx_KeyGeneration(hcryp, Timeout); + break; default: hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; status = HAL_ERROR; diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dac.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dac.c index f47c41a9aa..79388cd6b2 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dac.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dac.c @@ -365,7 +365,7 @@ */ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) { - /* Check DAC handle */ + /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; @@ -426,7 +426,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac) { - /* Check DAC handle */ + /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; @@ -530,6 +530,13 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac) HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) { __IO uint32_t wait_loop_index; + + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -594,6 +601,12 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) */ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -633,6 +646,12 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, c DMA_NodeConfTypeDef node_conf; __IO uint32_t wait_loop_index; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); @@ -899,6 +918,12 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, c */ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -1025,6 +1050,12 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, ui { __IO uint32_t tmp = 0UL; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); @@ -1150,6 +1181,9 @@ uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel) { uint32_t result; + /* Check the DAC peripheral handle */ + assert_param(hdac != NULL); + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -1193,6 +1227,12 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, uint32_t hclkfreq; uint32_t connectOnChip; + /* Check the DAC peripheral handle and channel configuration struct */ + if ((hdac == NULL) || (sConfig == NULL)) + { + return HAL_ERROR; + } + /* Check the DAC parameters */ assert_param(IS_DAC_HIGH_FREQUENCY_MODE(sConfig->DAC_HighFrequency)); assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); @@ -1502,6 +1542,12 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call { HAL_StatusTypeDef status = HAL_OK; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + if (pCallback == NULL) { /* Update the error code */ @@ -1607,6 +1653,12 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca { HAL_StatusTypeDef status = HAL_OK; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + if (hdac->State == HAL_DAC_STATE_READY) { switch (CallbackID) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dac_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dac_ex.c index 6cc5d7e981..8ba7fbfc74 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dac_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dac_ex.c @@ -129,6 +129,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac) uint32_t tmp_swtrig = 0UL; __IO uint32_t wait_loop_index; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Process locked */ __HAL_LOCK(hdac); @@ -180,6 +186,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1); @@ -217,6 +229,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Chan __IO uint32_t wait_loop_index; uint32_t LengthInBytes; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); @@ -392,6 +410,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Chann { HAL_StatusTypeDef status; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Disable the selected DAC channel DMA request */ CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2 | DAC_CR_DMAEN1); @@ -463,6 +487,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Chann */ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); @@ -513,6 +543,12 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32 */ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); @@ -558,6 +594,12 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Align uint32_t data; uint32_t tmp; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_ALIGN(Alignment)); assert_param(IS_DAC_DATA(Data1)); @@ -665,7 +707,6 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo { HAL_StatusTypeDef status = HAL_OK; - __IO uint32_t tmp; uint32_t trimmingvalue; uint32_t delta; __IO uint32_t wait_loop_index; @@ -678,7 +719,7 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo /* Check the DAC handle allocation */ /* Check if DAC running */ - if (hdac == NULL) + if ((hdac == NULL) || (sConfig == NULL)) { status = HAL_ERROR; } @@ -702,20 +743,6 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo /* Set mode in MCR for calibration */ MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U); - /* Set DAC Channel1 DHR register to the middle value */ - tmp = (uint32_t)hdac->Instance; - - if (Channel == DAC_CHANNEL_1) - { - tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R); - } - else - { - tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R); - } - - *(__IO uint32_t *) tmp = 0x0800UL; - /* Enable the selected DAC channel calibration */ /* i.e. set DAC_CR_CENx bit */ SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL))); @@ -813,8 +840,8 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_Channel assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue)); - /* Check the DAC handle allocation */ - if (hdac == NULL) + /* Check the DAC handle and channel configuration struct allocation */ + if ((hdac == NULL) || (sConfig == NULL)) { status = HAL_ERROR; } diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hash.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hash.c index 189d9631ae..9c09db3fcc 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hash.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hash.c @@ -441,11 +441,11 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) * @param hhash HASH handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: - * @arg @ref HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID - * @arg @ref HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID - * @arg @ref HAL_HASH_ERROR_CB_ID HASH error Callback ID - * @arg @ref HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID - * @arg @ref HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID + * @arg HAL_HASH_INPUTCPLT_CB_ID input completion callback ID + * @arg HAL_HASH_DGSTCPLT_CB_ID digest computation completion callback ID + * @arg HAL_HASH_ERROR_CB_ID error callback ID + * @arg HAL_HASH_MSPINIT_CB_ID MspInit callback ID + * @arg HAL_HASH_MSPDEINIT_CB_ID MspDeInit callback ID * @param pCallback pointer to the Callback function * @retval status */ @@ -530,11 +530,11 @@ HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_ * @param hhash HASH handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: - * @arg @ref HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID - * @arg @ref HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID - * @arg @ref HAL_HASH_ERROR_CB_ID HASH error Callback ID - * @arg @ref HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID - * @arg @ref HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID + * @arg HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID + * @arg HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID + * @arg HAL_HASH_ERROR_CB_ID HASH error Callback ID + * @arg HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID + * @arg HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID * @retval status */ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID) @@ -2226,9 +2226,11 @@ HAL_StatusTypeDef HAL_HASH_HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8 void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) { HAL_StatusTypeDef status; + uint32_t itsource = hhash->Instance->IMR; + uint32_t itflag = hhash->Instance->SR; /* If digest is ready */ - if (__HAL_HASH_GET_FLAG(hhash, HASH_FLAG_DCIS)) + if ((itflag & HASH_FLAG_DCIS) == HASH_FLAG_DCIS) { /* Read the digest */ HASH_GetDigest(hhash, hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH(hhash)); @@ -2250,9 +2252,9 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) } /* If Peripheral ready to accept new data */ - if (__HAL_HASH_GET_FLAG(hhash, HASH_FLAG_DINIS)) + if ((itflag & HASH_FLAG_DINIS) == HASH_FLAG_DINIS) { - if (__HAL_HASH_GET_IT_SOURCE(hhash, HASH_IT_DINI)) + if ((itsource & HASH_IT_DINI) == HASH_IT_DINI) { status = HASH_WriteData_IT(hhash); if (status != HAL_OK) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c index e0275727a3..27673574c2 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c @@ -614,7 +614,12 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) /* Configure I2Cx: Addressing Master mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { - hi2c->Instance->CR2 = (I2C_CR2_ADD10); + SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + } + else + { + /* Clear the I2C ADD10 bit */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); @@ -2234,11 +2239,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); } return HAL_OK; @@ -2872,6 +2877,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ + hi2c->XferSize = 0U; hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; @@ -2993,11 +2999,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT)); + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; } @@ -3473,22 +3479,6 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - /* Check if the maximum allowed number of trials has been reached */ - if (I2C_Trials == Trials) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - /* Increment Trials */ I2C_Trials++; } while (I2C_Trials < Trials); @@ -4079,11 +4069,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); } return HAL_OK; @@ -5400,6 +5390,12 @@ static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { direction = I2C_GENERATE_START_READ; @@ -5767,6 +5763,9 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + /* Enable only Error interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); @@ -5809,6 +5808,12 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable only Error and NACK interrupt for data transfer */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { direction = I2C_GENERATE_START_READ; @@ -6506,6 +6511,11 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; } + else if (tmpstate == HAL_I2C_STATE_LISTEN) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_NONE; + } else { /* Do nothing */ @@ -7532,13 +7542,13 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { - /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } @@ -7566,13 +7576,13 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { - /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } @@ -7588,7 +7598,7 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); } - if ((hi2c->XferISR != I2C_Mem_ISR_DMA) && (InterruptRequest == I2C_XFER_RELOAD_IT)) + if (InterruptRequest == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i3c.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i3c.c index 89de38ccf4..1d43699e5c 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i3c.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i3c.c @@ -128,6 +128,9 @@ an IO operation interface One element of the frame descriptor correspond to one frame to manage through IO operation. + (#) To check if I3C target device is ready for communication, use the function HAL_I3C_Ctrl_IsDeviceI3C_Ready() + + (#) To check if I2C target device is ready for communication, use the function HAL_I3C_Ctrl_IsDeviceI2C_Ready() (#) For I3C IO operations, three operation modes are available within this driver : @@ -175,6 +178,11 @@ using HAL_I3C_Ctrl_Receive_IT() or HAL_I3C_Ctrl_Receive_DMA() (+) At reception end of transfer, HAL_I3C_CtrlRxCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I3C_CtrlRxCpltCallback() + (+) Transfer in multiple direction (transmit/receive) in controller mode a Common Command Code in a direct + communication or an amount of private data in an I2C or I3C communication in non-blocking mode using + HAL_I3C_Ctrl_MultipleTransfer_IT() or HAL_I3C_Ctrl_MultipleTransfer_DMA() + (+) At the end of transfer, HAL_I3C_CtrlMultipleXferCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I3C_CtrlMultipleXferCpltCallback() (+) Transmit in target mode an amount of private data in an I3C communication in non-blocking mode using HAL_I3C_Tgt_Transmit_IT() or HAL_I3C_Tgt_Transmit_DMA() (+) At transmission end of transfer, HAL_I3C_TgtTxCpltCallback() is executed and users can @@ -232,6 +240,8 @@ Function HAL_I3C_RegisterCallback() allows to register following callbacks: (+) CtrlTxCpltCallback : callback for Controller transmission CCC, I3C private or I2C end of transfer. (+) CtrlRxCpltCallback : callback for Controller reception CCC, I3C private or I2C end of transfer. + (+) CtrlMultipleXferCpltCallback : callback for Controller multiple Direct CCC, I3C private or I2C + end of transfer. (+) CtrlDAACpltCallback : callback for Controller Enter Dynamic Address Assignment end of transfer. (+) TgtTxCpltCallback : callback for Target transmission I3C private end of transfer. (+) TgtRxCpltCallback : callback for Target reception I3C private end of transfer. @@ -258,6 +268,8 @@ This function allows to reset following callbacks: (+) CtrlTxCpltCallback : callback for Controller transmission CCC, I3C private or I2C end of transfer. (+) CtrlRxCpltCallback : callback for Controller reception CCC, I3C private or I2C end of transfer. + (+) CtrlMultipleXferCpltCallback : callback for Controller multiple Direct CCC, I3C private or I2C + end of transfer. (+) CtrlDAACpltCallback : callback for Controller Enter Dynamic Address Assignment end of transfer. (+) TgtTxCpltCallback : callback for Target transmission I3C private end of transfer. (+) TgtRxCpltCallback : callback for Target reception I3C private end of transfer. @@ -328,7 +340,7 @@ #define I3C_XFER_TARGET_IBI (0x00000040U) #define I3C_XFER_CONTROLLER_TX_IT (0x00000080U) #define I3C_XFER_CONTROLLER_RX_IT (0x00000100U) -#define I3C_XFER_CONTROLLER_RX_CCC_IT (0x00000200U) +#define I3C_XFER_CONTROLLER_RX_CCC_IT (0x00000400U) #define I3C_XFER_CONTROLLER_DAA_IT (0x00001000U) /* Private defines for control buffer prior preparation */ @@ -347,6 +359,19 @@ /* Private macro -----------------------------------------------------------------------------------------------------*/ /* Private variables -------------------------------------------------------------------------------------------------*/ +/** @addtogroup I3C_Private_Variables + * @{ + */ +/* Structure containing address device and message type used for the private function I3C_Ctrl_IsDevice_Ready() */ +typedef struct +{ + uint8_t Address; /* Dynamic or Static target Address */ + uint32_t MessageType; /* Message Type */ + +} I3C_DeviceTypeDef; +/** + * @} + */ /* Private function prototypes ---------------------------------------------------------------------------------------*/ /** @addtogroup I3C_Private_Functions @@ -365,9 +390,15 @@ static HAL_StatusTypeDef I3C_Tgt_CtrlRole_ISR(struct __I3C_HandleTypeDef *hi3c, static HAL_StatusTypeDef I3C_Tgt_IBI_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources); static HAL_StatusTypeDef I3C_Ctrl_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources); static HAL_StatusTypeDef I3C_Ctrl_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources); +static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_ISR(struct __I3C_HandleTypeDef *hi3c, + uint32_t itFlags, + uint32_t itSources); #if defined(HAL_DMA_MODULE_ENABLED) static HAL_StatusTypeDef I3C_Ctrl_Tx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources); static HAL_StatusTypeDef I3C_Ctrl_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources); +static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, + uint32_t itFlags, + uint32_t itSources); #endif /* HAL_DMA_MODULE_ENABLED */ static HAL_StatusTypeDef I3C_Ctrl_DAA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources); static HAL_StatusTypeDef I3C_Abort_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources); @@ -391,10 +422,22 @@ static void I3C_DMAError(DMA_HandleTypeDef *hdma); #endif /* HAL_DMA_MODULE_ENABLED */ static void I3C_Enable_IRQ(I3C_HandleTypeDef *hi3c, uint32_t InterruptRequest); static void I3C_Disable_IRQ(I3C_HandleTypeDef *hi3c, uint32_t InterruptRequest); -static HAL_StatusTypeDef I3C_TxBuffer_PriorPreparation(I3C_HandleTypeDef *hi3c, uint8_t counter, uint32_t option); +static HAL_StatusTypeDef I3C_Xfer_PriorPreparation(I3C_HandleTypeDef *hi3c, uint8_t counter, uint32_t option); +static uint32_t I3C_FillTxBuffer_CCC(I3C_HandleTypeDef *hi3c, + uint32_t indexDesc, + uint32_t txSize, + uint32_t txCurrentIndex); +static uint32_t I3C_FillTxBuffer_Private(I3C_HandleTypeDef *hi3c, + uint32_t indexDesc, + uint32_t txSize, + uint32_t txCurrentIndex); static HAL_StatusTypeDef I3C_ControlBuffer_PriorPreparation(I3C_HandleTypeDef *hi3c, uint8_t counter, uint32_t option); +static HAL_StatusTypeDef I3C_Ctrl_IsDevice_Ready(I3C_HandleTypeDef *hi3c, + const I3C_DeviceTypeDef *pDevice, + uint32_t trials, + uint32_t timeout); static void I3C_TreatErrorCallback(I3C_HandleTypeDef *hi3c); /** * @} @@ -470,16 +513,28 @@ HAL_StatusTypeDef HAL_I3C_Init(I3C_HandleTypeDef *hi3c) { #if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) /* Init the I3C Callback settings */ - hi3c->CtrlTxCpltCallback = HAL_I3C_CtrlTxCpltCallback; /* Legacy weak CtrlTxCpltCallback */ - hi3c->CtrlRxCpltCallback = HAL_I3C_CtrlRxCpltCallback; /* Legacy weak CtrlRxCpltCallback */ - hi3c->CtrlDAACpltCallback = HAL_I3C_CtrlDAACpltCallback; /* Legacy weak CtrlDAACpltCallback */ - hi3c->TgtReqDynamicAddrCallback = HAL_I3C_TgtReqDynamicAddrCallback; /* Legacy weak TgtReqDynamicAddrCallback */ - hi3c->TgtTxCpltCallback = HAL_I3C_TgtTxCpltCallback; /* Legacy weak TgtTxCpltCallback */ - hi3c->TgtRxCpltCallback = HAL_I3C_TgtRxCpltCallback; /* Legacy weak TgtRxCpltCallback */ - hi3c->TgtHotJoinCallback = HAL_I3C_TgtHotJoinCallback; /* Legacy weak TgtHotJoinCallback */ - hi3c->NotifyCallback = HAL_I3C_NotifyCallback; /* Legacy weak NotifyCallback */ - hi3c->ErrorCallback = HAL_I3C_ErrorCallback; /* Legacy weak ErrorCallback */ - hi3c->AbortCpltCallback = HAL_I3C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + /* Legacy weak CtrlTxCpltCallback */ + hi3c->CtrlTxCpltCallback = HAL_I3C_CtrlTxCpltCallback; + /* Legacy weak CtrlRxCpltCallback */ + hi3c->CtrlRxCpltCallback = HAL_I3C_CtrlRxCpltCallback; + /* Legacy weak CtrlMultipleXferCpltCallback */ + hi3c->CtrlMultipleXferCpltCallback = HAL_I3C_CtrlMultipleXferCpltCallback; + /* Legacy weak CtrlDAACpltCallback */ + hi3c->CtrlDAACpltCallback = HAL_I3C_CtrlDAACpltCallback; + /* Legacy weak TgtReqDynamicAddrCallback */ + hi3c->TgtReqDynamicAddrCallback = HAL_I3C_TgtReqDynamicAddrCallback; + /* Legacy weak TgtTxCpltCallback */ + hi3c->TgtTxCpltCallback = HAL_I3C_TgtTxCpltCallback; + /* Legacy weak TgtRxCpltCallback */ + hi3c->TgtRxCpltCallback = HAL_I3C_TgtRxCpltCallback; + /* Legacy weak TgtHotJoinCallback */ + hi3c->TgtHotJoinCallback = HAL_I3C_TgtHotJoinCallback; + /* Legacy weak NotifyCallback */ + hi3c->NotifyCallback = HAL_I3C_NotifyCallback; + /* Legacy weak ErrorCallback */ + hi3c->ErrorCallback = HAL_I3C_ErrorCallback; + /* Legacy weak AbortCpltCallback */ + hi3c->AbortCpltCallback = HAL_I3C_AbortCpltCallback; /* Check on the MSP init callback */ if (hi3c->MspInitCallback == NULL) @@ -664,6 +719,8 @@ __weak void HAL_I3C_MspDeInit(I3C_HandleTypeDef *hi3c) Tx CCC transfer is completed. (++) Users must implement HAL_I3C_CtrlRxCpltCallback() function when the reception of private data or Rx CCC transfer is completed. + (++) Users must implement HAL_I3C_CtrlMultipleXferCpltCallback() function when the multiple + transfer of CCC, I3C private or I2C transfer is completed. (++) Users must implement HAL_I3C_CtrlDAACpltCallback() function when Dynamic Address Assignment procedure is completed. (++) Users must implement HAL_I3C_TgtReqDynamicAddrCallback() function in the controller application @@ -701,6 +758,7 @@ __weak void HAL_I3C_MspDeInit(I3C_HandleTypeDef *hi3c) * This parameter can be one of the following values: * @arg @ref HAL_I3C_CTRL_TX_COMPLETE_CB_ID * @arg @ref HAL_I3C_CTRL_RX_COMPLETE_CB_ID + * @arg @ref HAL_I3C_CTRL_MULTIPLE_XFER_COMPLETE_CB_ID * @arg @ref HAL_I3C_CTRL_DAA_COMPLETE_CB_ID * @arg @ref HAL_I3C_TGT_TX_COMPLETE_CB_ID * @arg @ref HAL_I3C_TGT_RX_COMPLETE_CB_ID @@ -742,6 +800,10 @@ HAL_StatusTypeDef HAL_I3C_RegisterCallback(I3C_HandleTypeDef *hi3c, hi3c->CtrlRxCpltCallback = pCallback; break; + case HAL_I3C_CTRL_MULTIPLE_XFER_COMPLETE_CB_ID : + hi3c->CtrlMultipleXferCpltCallback = pCallback; + break; + case HAL_I3C_CTRL_DAA_COMPLETE_CB_ID : hi3c->CtrlDAACpltCallback = pCallback; break; @@ -931,6 +993,7 @@ HAL_StatusTypeDef HAL_I3C_RegisterTgtHotJoinCallback(I3C_HandleTypeDef *hi3c, * This parameter can be one of the following values: * @arg @ref HAL_I3C_CTRL_TX_COMPLETE_CB_ID * @arg @ref HAL_I3C_CTRL_RX_COMPLETE_CB_ID + * @arg @ref HAL_I3C_CTRL_MULTIPLE_XFER_COMPLETE_CB_ID * @arg @ref HAL_I3C_CTRL_DAA_COMPLETE_CB_ID * @arg @ref HAL_I3C_TGT_REQ_DYNAMIC_ADDR_CB_ID * @arg @ref HAL_I3C_TGT_TX_COMPLETE_CB_ID @@ -959,51 +1022,68 @@ HAL_StatusTypeDef HAL_I3C_UnRegisterCallback(I3C_HandleTypeDef *hi3c, HAL_I3C_Ca switch (callbackID) { case HAL_I3C_CTRL_TX_COMPLETE_CB_ID : - hi3c->CtrlTxCpltCallback = HAL_I3C_CtrlTxCpltCallback; /* Legacy weak CtrlTxCpltCallback */ + /* Legacy weak CtrlTxCpltCallback */ + hi3c->CtrlTxCpltCallback = HAL_I3C_CtrlTxCpltCallback; break; case HAL_I3C_CTRL_RX_COMPLETE_CB_ID : - hi3c->CtrlRxCpltCallback = HAL_I3C_CtrlRxCpltCallback; /* Legacy weak CtrlRxCpltCallback */ + /* Legacy weak CtrlRxCpltCallback */ + hi3c->CtrlRxCpltCallback = HAL_I3C_CtrlRxCpltCallback; + break; + + case HAL_I3C_CTRL_MULTIPLE_XFER_COMPLETE_CB_ID : + /* Legacy weak CtrlMultipleXferCpltCallback */ + hi3c->CtrlMultipleXferCpltCallback = HAL_I3C_CtrlMultipleXferCpltCallback; break; case HAL_I3C_CTRL_DAA_COMPLETE_CB_ID : - hi3c->CtrlDAACpltCallback = HAL_I3C_CtrlDAACpltCallback; /* Legacy weak CtrlDAACpltCallback */ + /* Legacy weak CtrlDAACpltCallback */ + hi3c->CtrlDAACpltCallback = HAL_I3C_CtrlDAACpltCallback; break; case HAL_I3C_TGT_REQ_DYNAMIC_ADDR_CB_ID : - hi3c->TgtReqDynamicAddrCallback = HAL_I3C_TgtReqDynamicAddrCallback;/*Legacy weak TgtReqDynamicAddrCallback */ + /*Legacy weak TgtReqDynamicAddrCallback */ + hi3c->TgtReqDynamicAddrCallback = HAL_I3C_TgtReqDynamicAddrCallback; break; case HAL_I3C_TGT_TX_COMPLETE_CB_ID : - hi3c->TgtTxCpltCallback = HAL_I3C_TgtTxCpltCallback; /* Legacy weak TgtTxCpltCallback */ + /* Legacy weak TgtTxCpltCallback */ + hi3c->TgtTxCpltCallback = HAL_I3C_TgtTxCpltCallback; break; case HAL_I3C_TGT_RX_COMPLETE_CB_ID : - hi3c->TgtRxCpltCallback = HAL_I3C_TgtRxCpltCallback; /* Legacy weak TgtRxCpltCallback */ + /* Legacy weak TgtRxCpltCallback */ + hi3c->TgtRxCpltCallback = HAL_I3C_TgtRxCpltCallback; break; case HAL_I3C_TGT_HOTJOIN_CB_ID : - hi3c->TgtHotJoinCallback = HAL_I3C_TgtHotJoinCallback; /* Legacy weak TgtHotJoinCallback */ + /* Legacy weak TgtHotJoinCallback */ + hi3c->TgtHotJoinCallback = HAL_I3C_TgtHotJoinCallback; break; case HAL_I3C_NOTIFY_CB_ID : - hi3c->NotifyCallback = HAL_I3C_NotifyCallback; /* Legacy weak NotifyCallback */ + /* Legacy weak NotifyCallback */ + hi3c->NotifyCallback = HAL_I3C_NotifyCallback; break; case HAL_I3C_ERROR_CB_ID : - hi3c->ErrorCallback = HAL_I3C_ErrorCallback; /* Legacy weak ErrorCallback */ + /* Legacy weak ErrorCallback */ + hi3c->ErrorCallback = HAL_I3C_ErrorCallback; break; case HAL_I3C_ABORT_CB_ID : - hi3c->AbortCpltCallback = HAL_I3C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + /* Legacy weak AbortCpltCallback */ + hi3c->AbortCpltCallback = HAL_I3C_AbortCpltCallback; break; case HAL_I3C_MSPINIT_CB_ID : - hi3c->MspInitCallback = HAL_I3C_MspInit; /* Legacy weak MspInit */ + /* Legacy weak MspInit */ + hi3c->MspInitCallback = HAL_I3C_MspInit; break; case HAL_I3C_MSPDEINIT_CB_ID : - hi3c->MspDeInitCallback = HAL_I3C_MspDeInit; /* Legacy weak MspDeInit */ + /* Legacy weak MspDeInit */ + hi3c->MspDeInitCallback = HAL_I3C_MspDeInit; break; default : @@ -1017,11 +1097,13 @@ HAL_StatusTypeDef HAL_I3C_UnRegisterCallback(I3C_HandleTypeDef *hi3c, HAL_I3C_Ca switch (callbackID) { case HAL_I3C_MSPINIT_CB_ID : - hi3c->MspInitCallback = HAL_I3C_MspInit; /* Legacy weak MspInit */ + /* Legacy weak MspInit */ + hi3c->MspInitCallback = HAL_I3C_MspInit; break; case HAL_I3C_MSPDEINIT_CB_ID : - hi3c->MspDeInitCallback = HAL_I3C_MspDeInit; /* Legacy weak MspDeInit */ + /* Legacy weak MspDeInit */ + hi3c->MspDeInitCallback = HAL_I3C_MspDeInit; break; default : @@ -1107,7 +1189,6 @@ HAL_StatusTypeDef HAL_I3C_ActivateNotification(I3C_HandleTypeDef *hi3c, I3C_Xfer hi3c->ptrRxFunc = &I3C_ReceiveWordTreatment; } } - /* Store the target event treatment function */ hi3c->XferISR = I3C_Tgt_Event_ISR; } @@ -1124,7 +1205,6 @@ HAL_StatusTypeDef HAL_I3C_ActivateNotification(I3C_HandleTypeDef *hi3c, I3C_Xfer /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk of I3C interrupt handle execution before current process unlock */ - /* Enable selected notifications */ I3C_Enable_IRQ(hi3c, (interruptMask | I3C_XFER_LISTEN_IT)); } @@ -1215,6 +1295,22 @@ __weak void HAL_I3C_CtrlRxCpltCallback(I3C_HandleTypeDef *hi3c) */ } +/** + * @brief Controller multiple Direct CCC Command, I3C private or I2C transfer Complete callback. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @retval None + */ +__weak void HAL_I3C_CtrlMultipleXferCpltCallback(I3C_HandleTypeDef *hi3c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi3c); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I3C_CtrlMultipleXferCpltCallback could be implemented in the user file + */ +} + /** * @brief Controller dynamic address assignment Complete callback. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information @@ -1911,6 +2007,8 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_ConfigBusDevices(I3C_HandleTypeDef *hi3 * @note This function must be called before initiate any communication transfer. This function help the preparation * of the full transfer usecase in a transfer descriptor which contained different buffer pointers * and their associated size through I3C_XferTypeDef. + * @note The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains + * multiple transmission frames. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. * @param pCCCDesc : [IN] Pointer to an I3C_CCCTypeDef structure that contains the CCC descriptor information. @@ -1930,7 +2028,6 @@ HAL_StatusTypeDef HAL_I3C_AddDescToFrame(I3C_HandleTypeDef *hi3c, { HAL_I3C_StateTypeDef handle_state; HAL_StatusTypeDef status = HAL_OK; - uint32_t direction = HAL_I3C_DIRECTION_WRITE; /* check on the handle */ if (hi3c == NULL) @@ -1947,22 +2044,23 @@ HAL_StatusTypeDef HAL_I3C_AddDescToFrame(I3C_HandleTypeDef *hi3c, hi3c->pCCCDesc = pCCCDesc; hi3c->pPrivateDesc = pPrivateDesc; hi3c->pXferData = pXferData; + hi3c->RxXferCount = 0; + hi3c->TxXferCount = 0; /* Prepare Direction, and Check on user parameters */ if (((option & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_CCC) || ((option & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_DIRECT)) { /* Check on user parameters */ - if ((pCCCDesc == NULL) || (pXferData == NULL) || (nbFrame < 1U)) + if ((pCCCDesc == NULL) || + (pXferData == NULL) || + (nbFrame < 1U) || + (((option & (I3C_OPERATION_TYPE_MASK | I3C_DEFINE_BYTE_MASK)) == \ + (LL_I3C_CONTROLLER_MTYPE_DIRECT | I3C_DEFINE_BYTE_MASK)) && (pCCCDesc->CCCBuf.Size == 0U))) { hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; status = HAL_ERROR; } - else - { - /* Update direction of frame */ - direction = hi3c->pCCCDesc->Direction; - } } else { @@ -1972,11 +2070,6 @@ HAL_StatusTypeDef HAL_I3C_AddDescToFrame(I3C_HandleTypeDef *hi3c, hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; status = HAL_ERROR; } - else - { - /* Update direction of frame */ - direction = hi3c->pPrivateDesc->Direction; - } } if (status == HAL_OK) @@ -1991,16 +2084,10 @@ HAL_StatusTypeDef HAL_I3C_AddDescToFrame(I3C_HandleTypeDef *hi3c, status = HAL_ERROR; } - /* Compute TxBuffer if CCC defining byte or direction Write */ - if (((direction == HAL_I3C_DIRECTION_WRITE) && (pXferData->TxBuf.pBuffer != NULL)) || - (((option & I3C_DEFINE_BYTE_MASK) != 0U) && (direction == HAL_I3C_DIRECTION_READ))) + /* I3C Tx Buffer prior preparation, set and check RxCount */ + if (I3C_Xfer_PriorPreparation(hi3c, nbFrame, option) != HAL_OK) { - /* I3C Tx Buffer prior preparation */ - if (I3C_TxBuffer_PriorPreparation(hi3c, nbFrame, option) != HAL_OK) - { - hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; - status = HAL_ERROR; - } + status = HAL_ERROR; } } else @@ -2375,12 +2462,18 @@ HAL_StatusTypeDef HAL_I3C_GetConfigFifo(I3C_HandleTypeDef *hi3c, I3C_FifoConfTyp (+) Call the function HAL_I3C_Ctrl_Receive() to receive private data in polling mode. (+) Call the function HAL_I3C_Ctrl_Receive_IT() to receive private data in interrupt mode. (+) Call the function HAL_I3C_Ctrl_Receive_DMA() to receive private data in DMA mode. + (+) Call the function HAL_I3C_Ctrl_MultipleTransfer_IT() to transfer I3C or I2C private data or CCC command + in multiple direction in interrupt mode. + (+) Call the function HAL_I3C_Ctrl_MultipleTransfer_DMA() to transfer I3C or I2C private data or CCC command + in multiple direction in DMA mode. (+) Call the function HAL_I3C_Ctrl_DynAddrAssign() to send a broadcast ENTDAA CCC command in polling mode. (+) Call the function HAL_I3C_Ctrl_DynAddrAssign_IT() to send a broadcast ENTDAA CCC command in interrupt mode. (+) Call the function HAL_I3C_Ctrl_SetDynAddr() to set, asscociate the target dynamic address during the Dynamic Address Assignment processus. + (+) Call the function HAL_I3C_Ctrl_IsDeviceI3C_Ready() to check if I3C target device is ready. + (+) Call the function HAL_I3C_Ctrl_IsDeviceI2C_Ready() to check if I2C target device is ready. (+) Those functions are called only when mode is Controller. @@ -2391,6 +2484,8 @@ HAL_StatusTypeDef HAL_I3C_GetConfigFifo(I3C_HandleTypeDef *hi3c, I3C_FifoConfTyp /** * @brief Controller transmit direct write or a broadcast CCC command in polling mode. * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. + * @note The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains + * multiple transmission frames. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers @@ -2423,7 +2518,8 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC(I3C_HandleTypeDef *hi3c, handle_state = hi3c->State; /* Check on user parameters */ - if (pXferData == NULL) + if ((pXferData == NULL) || + ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U))) { hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -2552,6 +2648,8 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC(I3C_HandleTypeDef *hi3c, /** * @brief Controller transmit direct write or a broadcast CCC command in interrupt mode. * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. + * @note The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains + * multiple transmission frames. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers @@ -2580,7 +2678,8 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC_IT(I3C_HandleTypeDef *hi3c, handle_state = hi3c->State; /* Check on user parameters */ - if (pXferData == NULL) + if ((pXferData == NULL) || + ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U))) { hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -2634,6 +2733,8 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC_IT(I3C_HandleTypeDef *hi3c, /** * @brief Controller transmit direct write or a broadcast CCC command in DMA mode. * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. + * @note The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains + * multiple transmission frames. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers @@ -2665,7 +2766,8 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC_DMA(I3C_HandleTypeDef *hi3c, handle_state = hi3c->State; /* Check on user parameters */ - if (pXferData == NULL) + if ((pXferData == NULL) || + ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U))) { hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -2823,7 +2925,7 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC_DMA(I3C_HandleTypeDef *hi3c, /** * @brief Controller transmit direct read CCC command in polling mode. * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. - * @note The RxBufferSize must be equal to the sum of all RxBufferSize exist in the descriptor. + * @note The RxBuf.Size must be equal to the sum of all RxBuf.Size exist in the descriptor. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers @@ -2857,7 +2959,9 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC(I3C_HandleTypeDef *hi3c, handle_state = hi3c->State; /* Check on user parameters */ - if ((pXferData == NULL) || (pXferData->RxBuf.pBuffer == NULL)) + if ((pXferData == NULL) || + (pXferData->RxBuf.pBuffer == NULL) || + ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U))) { hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -3008,7 +3112,7 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC(I3C_HandleTypeDef *hi3c, /** * @brief Controller transmit direct read CCC command in interrupt mode. * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. - * @note The RxBufferSize must be equal to the sum of all RxBufferSize exist in the descriptor. + * @note The RxBuf.Size must be equal to the sum of all RxBuf.Size exist in the descriptor. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers @@ -3038,7 +3142,9 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC_IT(I3C_HandleTypeDef *hi3c, handle_state = hi3c->State; /* Check on user parameters */ - if ((pXferData == NULL) || (pXferData->RxBuf.pBuffer == NULL)) + if ((pXferData == NULL) || + (pXferData->RxBuf.pBuffer == NULL) || + ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U))) { hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -3142,7 +3248,9 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC_DMA(I3C_HandleTypeDef *hi3c, handle_state = hi3c->State; /* Check on user parameters */ - if ((pXferData == NULL) || (pXferData->RxBuf.pBuffer == NULL)) + if ((pXferData == NULL) || + (pXferData->RxBuf.pBuffer == NULL) || + ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U))) { hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -3362,7 +3470,9 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC_DMA(I3C_HandleTypeDef *hi3c, /** * @brief Controller private write in polling mode. * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. - * @note The TxBufferSize must be equal to the sum of all TxBufferSize exist in the descriptor. + * @note The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains + * multiple transmission frames. + * @note The TxBuf.Size must be equal to the sum of all TxBuf.Size exist in the descriptor. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers @@ -3395,7 +3505,8 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit(I3C_HandleTypeDef *hi3c, handle_state = hi3c->State; /* Check on user parameters */ - if (pXferData == NULL) + if ((pXferData == NULL) || + ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U))) { hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -3524,7 +3635,9 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit(I3C_HandleTypeDef *hi3c, /** * @brief Controller private write in interrupt mode. * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. - * @note The TxBufferSize must be equal to the sum of all TxBufferSize exist in the descriptor. + * @note The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains + * multiple transmission frames. + * @note The TxBuf.Size must be equal to the sum of all TxBuf.Size exist in the descriptor. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers @@ -3553,7 +3666,8 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit_IT(I3C_HandleTypeDef *hi3c, handle_state = hi3c->State; /* Check on user parameters */ - if (pXferData == NULL) + if ((pXferData == NULL) || + ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U))) { hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -3608,7 +3722,9 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit_IT(I3C_HandleTypeDef *hi3c, /** * @brief Controller private write in DMA mode. * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. - * @note The TxBufferSize must be equal to the sum of all TxBufferSize exist in the descriptor. + * @note The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains + * multiple transmission frames. + * @note The TxBuf.Size must be equal to the sum of all TxBuf.Size exist in the descriptor. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers @@ -3640,7 +3756,8 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit_DMA(I3C_HandleTypeDef *hi3c, handle_state = hi3c->State; /* Check on user parameters */ - if (pXferData == NULL) + if ((pXferData == NULL) || + ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U))) { hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -3799,7 +3916,7 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit_DMA(I3C_HandleTypeDef *hi3c, /** * @brief Controller private read in polling mode. * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. - * @note The RxBufferSize must be equal to the sum of all RxBufferSize exist in the descriptor. + * @note The RxBuf.Size must be equal to the sum of all RxBuf.Size exist in the descriptor. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required reception buffers @@ -3961,7 +4078,7 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_Receive(I3C_HandleTypeDef *hi3c, /** * @brief Controller private read in interrupt mode. * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. - * @note The RxBufferSize must be equal to the sum of all RxSize exist in the descriptor. + * @note The RxBuf.Size must be equal to the sum of all RxBuf.Size exist in the descriptor. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required reception buffers @@ -4045,7 +4162,7 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_Receive_IT(I3C_HandleTypeDef *hi3c, /** * @brief Controller private read in DMA mode. * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. - * @note The RxBufferSize must be equal to the sum of all RxSize exist in the descriptor. + * @note The RxBuf.Size must be equal to the sum of all RxBuf.Size exist in the descriptor. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required reception buffers @@ -4235,27 +4352,26 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_Receive_DMA(I3C_HandleTypeDef *hi3c, #endif /* HAL_DMA_MODULE_ENABLED */ /** - * @brief Controller assign dynamic address (send a broadcast ENTDAA CCC command) in polling mode. - * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration - * information for the specified I3C. - * @param target_payload : [IN/OUT] Pointer to the returned target payload value. - * @param dynOption : [IN] Parameter indicates the Dynamic address assignment option. - * It can be one value of @ref I3C_DYNAMIC_ADDRESS_OPTION_DEFINITION. - * @param timeout : [IN] Timeout duration in millisecond. - * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + * @brief Controller multiple Direct CCC Command, I3C private or I2C transfer in interrupt mode. + * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. + * @note The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains + * multiple transmission frames. + * @note This function must be called to transfer read/write I3C or I2C private data or a direct read/write CCC. + * @note The TxBuf.Size must be equal to the sum of all TxBuf.Size exist in the descriptor. + * @note The RxBuf.Size must be equal to the sum of all RxBuf.Size exist in the descriptor. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmit and receive + * buffers (control buffer, data buffers and status buffer). + * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ -HAL_StatusTypeDef HAL_I3C_Ctrl_DynAddrAssign(I3C_HandleTypeDef *hi3c, - uint64_t *target_payload, - uint32_t dynOption, - uint32_t timeout) +HAL_StatusTypeDef HAL_I3C_Ctrl_MultipleTransfer_IT(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData) { - uint32_t tickstart; HAL_I3C_StateTypeDef handle_state; HAL_StatusTypeDef status = HAL_OK; - /* check on parameters */ - assert_param(IS_I3C_ENTDAA_OPTION(dynOption)); - /* check on the handle */ if (hi3c == NULL) { @@ -4270,7 +4386,10 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_DynAddrAssign(I3C_HandleTypeDef *hi3c, /* Get I3C handle state */ handle_state = hi3c->State; - if (target_payload == NULL) + /* Check on user parameters */ + if ((pXferData == NULL) || + ((pXferData->RxBuf.pBuffer == NULL) && (hi3c->RxXferCount != 0U)) || + ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U))) { hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -4281,145 +4400,82 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_DynAddrAssign(I3C_HandleTypeDef *hi3c, hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; status = HAL_ERROR; } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } else { - /* Launch a RSTDAA procedure before launch ENTDAA */ - if ((dynOption == I3C_RSTDAA_THEN_ENTDAA) && - ((handle_state == HAL_I3C_STATE_READY) || (handle_state == HAL_I3C_STATE_LISTEN))) - { - /* Set handle transfer parameters */ - hi3c->ErrorCode = HAL_I3C_ERROR_NONE; - hi3c->State = HAL_I3C_STATE_BUSY_DAA; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - /* Enable arbitration header */ - LL_I3C_EnableArbitrationHeader(hi3c->Instance); - - /* Write CCC information in the control register */ - LL_I3C_ControllerHandleCCC(hi3c->Instance, I3C_BROADCAST_RSTDAA, 0U, LL_I3C_GENERATE_STOP); - - /* Wait Frame completion flag */ - status = I3C_WaitOnFlagUntilTimeout(hi3c, HAL_I3C_FLAG_FCF, RESET, timeout, tickstart); - - /* Clear frame complete flag */ - if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET) - { - LL_I3C_ClearFlag_FC(hi3c->Instance); - } - - /* Check on error flag */ - if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET) - { - /* Clear error flag */ - LL_I3C_ClearFlag_ERR(hi3c->Instance); - - /* Update handle error code parameter */ - I3C_GetErrorSources(hi3c); - - status = HAL_ERROR; - } + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY_TX_RX; + hi3c->pXferData = pXferData; + hi3c->TxXferCount = hi3c->pXferData->TxBuf.Size; + hi3c->RxXferCount = hi3c->pXferData->RxBuf.Size; + hi3c->XferISR = I3C_Ctrl_Multiple_Xfer_ISR; - /* Update handle state parameter */ - I3C_StateUpdate(hi3c); + /* Check on the Tx threshold to know the Tx treatment process : byte or word */ + if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4) + { + /* Set byte treatment function pointer */ + hi3c->ptrTxFunc = &I3C_TransmitByteTreatment; } - - if (status == HAL_OK) + else { - /* check on the State */ - if ((handle_state == HAL_I3C_STATE_READY) || (handle_state == HAL_I3C_STATE_LISTEN) || - (handle_state == HAL_I3C_STATE_BUSY_DAA)) - { - /* Check on the state */ - if (handle_state != HAL_I3C_STATE_BUSY_DAA) - { - /* Set handle transfer parameters */ - hi3c->ErrorCode = HAL_I3C_ERROR_NONE; - hi3c->State = HAL_I3C_STATE_BUSY_DAA; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - /* Enable arbitration header */ - LL_I3C_EnableArbitrationHeader(hi3c->Instance); - - /* Write CCC information in the control register */ - LL_I3C_ControllerHandleCCC(hi3c->Instance, I3C_BROADCAST_ENTDAA, 0U, LL_I3C_GENERATE_STOP); - } - else - { - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - } + /* Set word treatment function pointer */ + hi3c->ptrTxFunc = &I3C_TransmitWordTreatment; + } - /* Wait frame complete flag or TX FIFO not full flag until timeout */ - status = I3C_WaitOnDAAUntilTimeout(hi3c, timeout, tickstart); + /* Check on the Rx threshold to know the Rx treatment process : byte or word */ + if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4) + { + /* Set byte treatment function pointer */ + hi3c->ptrRxFunc = &I3C_ReceiveByteTreatment; + } + else + { + /* Set word treatment function pointer */ + hi3c->ptrRxFunc = &I3C_ReceiveWordTreatment; + } - /* Check TX FIFO not full flag */ - if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_TXFNFF) == SET) - { - /* Check on the Rx FIFO threshold to know the Rx treatment process : byte or word */ - if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4) - { - /* For loop to get target payload */ - for (uint32_t index = 0U; index < 8U; index++) - { - /* Retrieve payload byte by byte */ - *target_payload |= (uint64_t)((uint64_t)LL_I3C_ReceiveData8(hi3c->Instance) << (index * 8U)); - } - } - else - { - /* Retrieve first 32 bits payload */ - *target_payload = (uint64_t)LL_I3C_ReceiveData32(hi3c->Instance); + /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk + of I3C interrupt handle execution before current process unlock */ - /* Retrieve second 32 bits payload */ - *target_payload |= (uint64_t)((uint64_t)LL_I3C_ReceiveData32(hi3c->Instance) << 32U); - } + /* Enable Tx and Rx process interrupts */ + I3C_Enable_IRQ(hi3c, (I3C_XFER_CONTROLLER_TX_IT | I3C_XFER_CONTROLLER_RX_IT)); - status = HAL_BUSY; - } - /* Check on frame complete flag */ - else - { - /* Clear frame complete flag */ - if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET) - { - /* Clear frame complete flag */ - LL_I3C_ClearFlag_FC(hi3c->Instance); - } - /* Update handle state parameter */ - I3C_StateUpdate(hi3c); - } - } - else - { - hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; - status = HAL_ERROR; - } - } + /* Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); } } - return status; } +#if defined(HAL_DMA_MODULE_ENABLED) /** - * @brief Controller assign dynamic address (send a broadcast ENTDAA CCC command) in interrupt mode. + * @brief Controller multiple Direct CCC Command, I3C private or I2C transfer in DMA mode. + * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. + * @note The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains + * multiple transmission frames. + * @note The TxBuf.Size must be equal to the sum of all TxBuf.Size exist in the descriptor. + * @note The RxBuf.Size must be equal to the sum of all RxBuf.Size exist in the descriptor. + * @note This function must be called to transfer read/write private data or a direct read/write CCC command. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. - * @param dynOption : [IN] Parameter indicates the Dynamic address assignment option. - * It can be one value of @ref I3C_DYNAMIC_ADDRESS_OPTION_DEFINITION. + * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmit and receive + * buffers(control buffer, data buffer and status buffer). + * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ -HAL_StatusTypeDef HAL_I3C_Ctrl_DynAddrAssign_IT(I3C_HandleTypeDef *hi3c, uint32_t dynOption) +HAL_StatusTypeDef HAL_I3C_Ctrl_MultipleTransfer_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData) { + HAL_StatusTypeDef control_dma_status; + HAL_StatusTypeDef tx_dma_status = HAL_OK; + HAL_StatusTypeDef rx_dma_status = HAL_OK; HAL_I3C_StateTypeDef handle_state; HAL_StatusTypeDef status = HAL_OK; - - /* check on parameters */ - assert_param(IS_I3C_ENTDAA_OPTION(dynOption)); + uint32_t size_align_word; /* check on the handle */ if (hi3c == NULL) @@ -4435,8 +4491,22 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_DynAddrAssign_IT(I3C_HandleTypeDef *hi3c, uint32_ /* Get I3C handle state */ handle_state = hi3c->State; + /* Check on user parameters */ + if ((pXferData == NULL) || + ((pXferData->RxBuf.pBuffer == NULL) && (hi3c->RxXferCount != 0U)) || + ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U))) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* Check on hdmatx, hdmarx and hdmacr handle */ + else if ((hi3c->hdmatx == NULL) || (hi3c->hdmacr == NULL) || (hi3c->hdmarx == NULL)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_DMA_PARAM; + status = HAL_ERROR; + } /* check on the Mode */ - if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) { hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; status = HAL_ERROR; @@ -4449,24 +4519,436 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_DynAddrAssign_IT(I3C_HandleTypeDef *hi3c, uint32_ else { /* Set handle transfer parameters */ - hi3c->ErrorCode = HAL_I3C_ERROR_NONE; - hi3c->State = HAL_I3C_STATE_BUSY_DAA; - hi3c->XferISR = I3C_Ctrl_DAA_ISR; + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY_TX_RX; + hi3c->pXferData = pXferData; + hi3c->RxXferCount = hi3c->pXferData->RxBuf.Size; + hi3c->TxXferCount = hi3c->pXferData->TxBuf.Size; + hi3c->XferISR = I3C_Ctrl_Multiple_Xfer_DMA_ISR; - /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk - of I3C interrupt handle execution before current process unlock */ + /*------------------------------------ I3C DMA channel for Control Data -------------------------------------*/ + /* Set the I3C DMA transfer complete callback */ + hi3c->hdmacr->XferCpltCallback = I3C_DMAControlTransmitCplt; - /* Enable Dynamic Address Assignment process interrupts */ - I3C_Enable_IRQ(hi3c, I3C_XFER_CONTROLLER_DAA_IT); + /* Set the DMA error callback */ + hi3c->hdmacr->XferErrorCallback = I3C_DMAError; - /* Enable arbitration header */ - LL_I3C_EnableArbitrationHeader(hi3c->Instance); + /* Set the unused DMA callbacks to NULL */ + hi3c->hdmacr->XferHalfCpltCallback = NULL; + hi3c->hdmacr->XferAbortCallback = NULL; - /* Launch a RSTDAA procedure before launch ENTDAA */ - if (dynOption == I3C_RSTDAA_THEN_ENTDAA) - { - /* Write RSTDAA CCC information in the control register */ - LL_I3C_ControllerHandleCCC(hi3c->Instance, I3C_BROADCAST_RSTDAA, 0U, LL_I3C_GENERATE_RESTART); + /* assert that DMA source and destination width are configured in word */ + assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmacr->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmacr->Init.DestDataWidth)); + + /* Enable the control data DMA channel */ + control_dma_status = HAL_DMA_Start_IT(hi3c->hdmacr, (uint32_t)hi3c->pXferData->CtrlBuf.pBuffer, + (uint32_t)&hi3c->Instance->CR, (hi3c->ControlXferCount * 4U)); + + /*------------------------------------ I3C DMA channel for the Rx Data --------------------------------*/ + /* Check if Rx counter different from zero */ + if (hi3c->RxXferCount != 0U) + { + /* Set the I3C DMA transfer complete callback */ + hi3c->hdmarx->XferCpltCallback = I3C_DMADataReceiveCplt; + + /* Set the DMA error callback */ + hi3c->hdmarx->XferErrorCallback = I3C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi3c->hdmarx->XferHalfCpltCallback = NULL; + hi3c->hdmarx->XferAbortCallback = NULL; + + /* Check on the Rx threshold to know the Rx treatment process : byte or word */ + if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4) + { + /* assert that DMA source and destination width are configured in byte */ + assert_param(IS_I3C_DMASOURCEBYTE_VALUE(hi3c->hdmarx->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONBYTE_VALUE(hi3c->hdmarx->Init.DestDataWidth)); + + /* Enable the Rx data DMA channel */ + rx_dma_status = HAL_DMA_Start_IT(hi3c->hdmarx, (uint32_t)&hi3c->Instance->RDR, + (uint32_t)hi3c->pXferData->RxBuf.pBuffer, hi3c->pXferData->RxBuf.Size); + } + else + { + /* assert that DMA source and destination width are configured in word */ + assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmarx->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmarx->Init.DestDataWidth)); + + /* Check to align data size in words */ + if ((hi3c->pXferData->RxBuf.Size % 4U) == 0U) + { + /* Keep the same size */ + size_align_word = hi3c->pXferData->RxBuf.Size; + } + else + { + /* Modify size to be multiple of 4 */ + size_align_word = ((hi3c->pXferData->RxBuf.Size + 4U) - (hi3c->pXferData->RxBuf.Size % 4U)); + } + + /* Enable the Rx data DMA channel */ + rx_dma_status = HAL_DMA_Start_IT(hi3c->hdmarx, (uint32_t)&hi3c->Instance->RDWR, + (uint32_t)hi3c->pXferData->RxBuf.pBuffer, size_align_word); + } + } + + /*------------------------------------ I3C DMA channel for the Tx Data --------------------------------*/ + /* Check if Tx counter different from zero */ + if (hi3c->TxXferCount != 0U) + { + /* Set the I3C DMA transfer complete callback */ + hi3c->hdmatx->XferCpltCallback = I3C_DMADataTransmitCplt; + + /* Set the DMA error callback */ + hi3c->hdmatx->XferErrorCallback = I3C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi3c->hdmatx->XferHalfCpltCallback = NULL; + hi3c->hdmatx->XferAbortCallback = NULL; + + /* Check on the Tx threshold to know the Tx treatment process : byte or word */ + if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4) + { + /* assert that DMA source and destination width are configured in byte */ + assert_param(IS_I3C_DMASOURCEBYTE_VALUE(hi3c->hdmatx->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONBYTE_VALUE(hi3c->hdmatx->Init.DestDataWidth)); + + /* Enable the Tx data DMA channel */ + tx_dma_status = HAL_DMA_Start_IT(hi3c->hdmatx, (uint32_t)hi3c->pXferData->TxBuf.pBuffer, + (uint32_t)&hi3c->Instance->TDR, hi3c->pXferData->TxBuf.Size); + } + else + { + /* assert that DMA source and destination width are configured in word */ + assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmatx->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmatx->Init.DestDataWidth)); + + /* Check to align data size in words */ + if ((hi3c->pXferData->TxBuf.Size % 4U) == 0U) + { + /* Keep the same size */ + size_align_word = hi3c->pXferData->TxBuf.Size; + } + else + { + /* Modify size to be multiple of 4 */ + size_align_word = ((hi3c->pXferData->TxBuf.Size + 4U) - (hi3c->pXferData->TxBuf.Size % 4U)); + } + + /* Enable the Tx data DMA channel */ + tx_dma_status = HAL_DMA_Start_IT(hi3c->hdmatx, (uint32_t)hi3c->pXferData->TxBuf.pBuffer, + (uint32_t)&hi3c->Instance->TDWR, size_align_word); + } + } + + /* Check if DMA process is well started */ + if ((control_dma_status == HAL_OK) && (tx_dma_status == HAL_OK) && (rx_dma_status == HAL_OK)) + { + /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk + of I3C interrupt handle execution before current process unlock */ + + /* Enable Tx process interrupts */ + I3C_Enable_IRQ(hi3c, I3C_XFER_DMA); + + /* Update the number of remaining data bytes */ + hi3c->ControlXferCount = 0U; + + /* Enable control DMA Request */ + LL_I3C_EnableDMAReq_Control(hi3c->Instance); + + /* Check if Rx counter different from zero */ + if (hi3c->RxXferCount != 0U) + { + /* Update the number of remaining data bytes */ + hi3c->RxXferCount = 0U; + + /* Enable Rx data DMA Request */ + LL_I3C_EnableDMAReq_RX(hi3c->Instance); + } + + /* Check if Tx counter different from zero */ + if (hi3c->TxXferCount != 0U) + { + /* Update the number of remaining data bytes */ + hi3c->TxXferCount = 0U; + + /* Enable Tx data DMA Request */ + LL_I3C_EnableDMAReq_TX(hi3c->Instance); + } + + /* Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + else + { + /* Set callback to NULL if DMA started */ + if (HAL_DMA_Abort(hi3c->hdmacr) == HAL_OK) + { + hi3c->hdmacr->XferCpltCallback = NULL; + hi3c->hdmacr->XferErrorCallback = NULL; + } + + /* Set callback to NULL if DMA started */ + if (HAL_DMA_Abort(hi3c->hdmatx) == HAL_OK) + { + hi3c->hdmatx->XferCpltCallback = NULL; + hi3c->hdmatx->XferErrorCallback = NULL; + } + + /* Set callback to NULL if DMA started */ + if (HAL_DMA_Abort(hi3c->hdmarx) == HAL_OK) + { + hi3c->hdmarx->XferCpltCallback = NULL; + hi3c->hdmarx->XferErrorCallback = NULL; + } + + hi3c->ErrorCode = HAL_I3C_ERROR_DMA; + status = HAL_ERROR; + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + } + } + } + return status; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Controller assign dynamic address (send a broadcast ENTDAA CCC command) in polling mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @param target_payload : [IN/OUT] Pointer to the returned target payload value. + * @param dynOption : [IN] Parameter indicates the Dynamic address assignment option. + * It can be one value of @ref I3C_DYNAMIC_ADDRESS_OPTION_DEFINITION. + * @param timeout : [IN] Timeout duration in millisecond. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_DynAddrAssign(I3C_HandleTypeDef *hi3c, + uint64_t *target_payload, + uint32_t dynOption, + uint32_t timeout) +{ + uint32_t tickstart; + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + + /* check on parameters */ + assert_param(IS_I3C_ENTDAA_OPTION(dynOption)); + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + if (target_payload == NULL) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* check on the Mode */ + else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Launch a RSTDAA procedure before launch ENTDAA */ + if ((dynOption == I3C_RSTDAA_THEN_ENTDAA) && + ((handle_state == HAL_I3C_STATE_READY) || (handle_state == HAL_I3C_STATE_LISTEN))) + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY_DAA; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Enable arbitration header */ + LL_I3C_EnableArbitrationHeader(hi3c->Instance); + + /* Write CCC information in the control register */ + LL_I3C_ControllerHandleCCC(hi3c->Instance, I3C_BROADCAST_RSTDAA, 0U, LL_I3C_GENERATE_STOP); + + /* Wait Frame completion flag */ + status = I3C_WaitOnFlagUntilTimeout(hi3c, HAL_I3C_FLAG_FCF, RESET, timeout, tickstart); + + /* Clear frame complete flag */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET) + { + LL_I3C_ClearFlag_FC(hi3c->Instance); + } + + /* Check on error flag */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET) + { + /* Clear error flag */ + LL_I3C_ClearFlag_ERR(hi3c->Instance); + + /* Update handle error code parameter */ + I3C_GetErrorSources(hi3c); + + status = HAL_ERROR; + } + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + } + + if (status == HAL_OK) + { + /* check on the State */ + if ((handle_state == HAL_I3C_STATE_READY) || (handle_state == HAL_I3C_STATE_LISTEN) || + (handle_state == HAL_I3C_STATE_BUSY_DAA)) + { + /* Check on the state */ + if (handle_state != HAL_I3C_STATE_BUSY_DAA) + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY_DAA; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Enable arbitration header */ + LL_I3C_EnableArbitrationHeader(hi3c->Instance); + + /* Write CCC information in the control register */ + LL_I3C_ControllerHandleCCC(hi3c->Instance, I3C_BROADCAST_ENTDAA, 0U, LL_I3C_GENERATE_STOP); + } + else + { + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + } + + /* Wait frame complete flag or TX FIFO not full flag until timeout */ + status = I3C_WaitOnDAAUntilTimeout(hi3c, timeout, tickstart); + + /* Check TX FIFO not full flag */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_TXFNFF) == SET) + { + /* Check on the Rx FIFO threshold to know the Rx treatment process : byte or word */ + if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4) + { + /* For loop to get target payload */ + for (uint32_t index = 0U; index < 8U; index++) + { + /* Retrieve payload byte by byte */ + *target_payload |= (uint64_t)((uint64_t)LL_I3C_ReceiveData8(hi3c->Instance) << (index * 8U)); + } + } + else + { + /* Retrieve first 32 bits payload */ + *target_payload = (uint64_t)LL_I3C_ReceiveData32(hi3c->Instance); + + /* Retrieve second 32 bits payload */ + *target_payload |= (uint64_t)((uint64_t)LL_I3C_ReceiveData32(hi3c->Instance) << 32U); + } + + status = HAL_BUSY; + } + /* Check on frame complete flag */ + else + { + /* Clear frame complete flag */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + } + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + } + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + } + } + } + + return status; +} + +/** + * @brief Controller assign dynamic address (send a broadcast ENTDAA CCC command) in interrupt mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param dynOption : [IN] Parameter indicates the Dynamic address assignment option. + * It can be one value of @ref I3C_DYNAMIC_ADDRESS_OPTION_DEFINITION. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_DynAddrAssign_IT(I3C_HandleTypeDef *hi3c, uint32_t dynOption) +{ + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + + /* check on parameters */ + assert_param(IS_I3C_ENTDAA_OPTION(dynOption)); + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* check on the Mode */ + if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY_DAA; + hi3c->XferISR = I3C_Ctrl_DAA_ISR; + + /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk + of I3C interrupt handle execution before current process unlock */ + + /* Enable Dynamic Address Assignment process interrupts */ + I3C_Enable_IRQ(hi3c, I3C_XFER_CONTROLLER_DAA_IT); + + /* Enable arbitration header */ + LL_I3C_EnableArbitrationHeader(hi3c->Instance); + + /* Launch a RSTDAA procedure before launch ENTDAA */ + if (dynOption == I3C_RSTDAA_THEN_ENTDAA) + { + /* Write RSTDAA CCC information in the control register */ + LL_I3C_ControllerHandleCCC(hi3c->Instance, I3C_BROADCAST_RSTDAA, 0U, LL_I3C_GENERATE_RESTART); } else { @@ -4511,6 +4993,88 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_SetDynAddr(I3C_HandleTypeDef *hi3c, uint8_t devAd return status; } + +/** + * @brief Check if I3C target device is ready for communication. + * @param hi3c : [IN] Pointer to a I3C_HandleTypeDef structure that contains + * the configuration information for the specified I3C. + * @param devAddress : [IN] Value of the device dynamic address. + * @param trials : [IN] Number of trials + * @param timeout : [IN] Timeout duration + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_IsDeviceI3C_Ready(I3C_HandleTypeDef *hi3c, + uint8_t devAddress, + uint32_t trials, + uint32_t timeout) +{ + I3C_DeviceTypeDef device; + HAL_StatusTypeDef status; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Initiate a device address */ + device.Address = devAddress; + + /* Initiate a message type */ + device.MessageType = LL_I3C_CONTROLLER_MTYPE_PRIVATE; + + /* Check if the device is ready*/ + status = I3C_Ctrl_IsDevice_Ready(hi3c, &device, trials, timeout); + } + + return status; +} + +/** + * @brief Check if I2C target device is ready for communication. + * @param hi3c : [IN] Pointer to a I3C_HandleTypeDef structure that contains + * the configuration information for the specified I3C. + * @param devAddress : [IN] Value of the device dynamic address. + * @param trials : [IN] Number of trials + * @param timeout : [IN] Timeout duration + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_IsDeviceI2C_Ready(I3C_HandleTypeDef *hi3c, + uint8_t devAddress, + uint32_t trials, + uint32_t timeout) +{ + I3C_DeviceTypeDef device; + HAL_StatusTypeDef status; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Initiate a device address */ + device.Address = devAddress; + + /* Initiate a message type */ + device.MessageType = LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C; + + /* Check if the device is ready*/ + status = I3C_Ctrl_IsDevice_Ready(hi3c, &device, trials, timeout); + } + + return status; +} /** * @} */ @@ -4545,13 +5109,12 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_SetDynAddr(I3C_HandleTypeDef *hi3c, uint8_t devAd /** * @brief Target transmit private data in polling mode. - * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. * @note Target FIFO preload data is forced within this API for timing purpose. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers - * information (Pointer to the Tx buffer (pTxBuffer) and size of data - * to transmit in bytes (TxBufferSize)). + * information (Pointer to the Tx buffer (TxBuf.pBuffer) and size of data + * to transmit in bytes (TxBuf.Size)). * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). * @param timeout : [IN] Timeout duration in millisecond. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. @@ -4561,6 +5124,7 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; HAL_I3C_StateTypeDef handle_state; + uint32_t it_source; /* check on the handle */ if (hi3c == NULL) @@ -4573,6 +5137,8 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); assert_param(IS_I3C_MODE(hi3c->Mode)); + it_source = READ_REG(hi3c->Instance->IER); + /* Get I3C handle state */ handle_state = hi3c->State; @@ -4593,6 +5159,13 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef { status = HAL_BUSY; } + /* check if DEF or GRP CCC notifications are enabled */ + else if ((I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_DEFIE) != RESET) || + (I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_GRPIE) != RESET)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } /* Verify the dynamic address validity */ else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U) { @@ -4681,12 +5254,11 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef /** * @brief Target transmit private data in interrupt mode. - * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers - * information (Pointer to the Tx buffer (pTxBuffer) and size of data - * to transmit in bytes (TxBufferSize)). + * information (Pointer to the Tx buffer (TxBuf.pBuffer) and size of data + * to transmit in bytes (TxBuf.Size)). * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ @@ -4694,6 +5266,7 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeD { HAL_I3C_StateTypeDef handle_state; HAL_StatusTypeDef status = HAL_OK; + uint32_t it_source; /* check on the handle */ if (hi3c == NULL) @@ -4706,6 +5279,8 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeD assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); assert_param(IS_I3C_MODE(hi3c->Mode)); + it_source = READ_REG(hi3c->Instance->IER); + /* Get I3C handle state */ handle_state = hi3c->State; @@ -4726,6 +5301,13 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeD { status = HAL_BUSY; } + /* check if DEF and GRP CCC notifications are enabled */ + else if ((I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_DEFIE) != RESET) || + (I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_GRPIE) != RESET)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } /* Verify the dynamic address validity */ else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U) { @@ -4771,12 +5353,11 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeD #if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Target transmit private data in DMA mode. - * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers - * information (Pointer to the Tx buffer (pTxBuffer) and size of data - * to transmit in bytes (TxBufferSize)). + * information (Pointer to the Tx buffer (TxBuf.pBuffer) and size of data + * to transmit in bytes (TxBuf.Size)). * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ @@ -4786,6 +5367,7 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_DMA(I3C_HandleTypeDef *hi3c, I3C_XferType HAL_I3C_StateTypeDef handle_state; HAL_StatusTypeDef status = HAL_OK; uint32_t size_align_word; + uint32_t it_source; /* check on the handle */ if (hi3c == NULL) @@ -4798,6 +5380,8 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_DMA(I3C_HandleTypeDef *hi3c, I3C_XferType assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); assert_param(IS_I3C_MODE(hi3c->Mode)); + it_source = READ_REG(hi3c->Instance->IER); + /* Get I3C handle state */ handle_state = hi3c->State; @@ -4824,6 +5408,13 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_DMA(I3C_HandleTypeDef *hi3c, I3C_XferType { status = HAL_BUSY; } + /* check if DEF and GRP CCC notifications are enabled */ + else if ((I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_DEFIE) != RESET) || + (I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_GRPIE) != RESET)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } /* Verify the dynamic address validity */ else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U) { @@ -4923,12 +5514,11 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_DMA(I3C_HandleTypeDef *hi3c, I3C_XferType /** * @brief Target receive private data in polling mode. - * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required reception buffers - * information (Pointer to the Rx buffer (pRxBuffer) and size of data - * to be received in bytes (RxBufferSize)). + * information (Pointer to the Rx buffer (RxBuf.pBuffer) and size of data + * to be received in bytes (RxBuf.Size)). * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). * @param timeout : [IN] Timeout duration in millisecond. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. @@ -4938,6 +5528,7 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Receive(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef * uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; HAL_I3C_StateTypeDef handle_state; + uint32_t it_source; /* check on the handle */ if (hi3c == NULL) @@ -4950,6 +5541,8 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Receive(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef * assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); assert_param(IS_I3C_MODE(hi3c->Mode)); + it_source = READ_REG(hi3c->Instance->IER); + /* Get I3C handle state */ handle_state = hi3c->State; @@ -4970,6 +5563,13 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Receive(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef * { status = HAL_BUSY; } + /* check if DEF and GRP CCC notifications are enabled */ + else if ((I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_DEFIE) != RESET) || + (I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_GRPIE) != RESET)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } /* Verify the dynamic address validity */ else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U) { @@ -5057,12 +5657,11 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Receive(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef * /** * @brief Target receive private data in interrupt mode. - * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required reception buffers - * information (Pointer to the Rx buffer (pRxBuffer) and size of data - * to be received in bytes (RxBufferSize)). + * information (Pointer to the Rx buffer (RxBuf.pBuffer) and size of data + * to be received in bytes (RxBuf.Size)). * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ @@ -5070,6 +5669,7 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Receive_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDe { HAL_I3C_StateTypeDef handle_state; HAL_StatusTypeDef status = HAL_OK; + uint32_t it_source; /* check on the handle */ if (hi3c == NULL) @@ -5082,6 +5682,8 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Receive_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDe assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); assert_param(IS_I3C_MODE(hi3c->Mode)); + it_source = READ_REG(hi3c->Instance->IER); + /* Get I3C handle state */ handle_state = hi3c->State; @@ -5102,6 +5704,13 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Receive_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDe { status = HAL_BUSY; } + /* check if DEF and GRP CCC notifications are enabled */ + else if ((I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_DEFIE) != RESET) || + (I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_GRPIE) != RESET)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } /* Verify the dynamic address validity */ else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U) { @@ -5143,12 +5752,11 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Receive_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDe #if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Target receive private data in DMA mode. - * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required reception buffers - * information (Pointer to the Rx buffer (pRxBuffer) and size of data - * to be received in bytes (RxBufferSize)). + * information (Pointer to the Rx buffer (RxBuf.pBuffer) and size of data + * to be received in bytes (RxBuf.Size)). * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ @@ -5158,6 +5766,7 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Receive_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeD HAL_I3C_StateTypeDef handle_state; HAL_StatusTypeDef status = HAL_OK; uint32_t size_align_word; + uint32_t it_source; /* check on the handle */ if (hi3c == NULL) @@ -5170,6 +5779,8 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Receive_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeD assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); assert_param(IS_I3C_MODE(hi3c->Mode)); + it_source = READ_REG(hi3c->Instance->IER); + /* Get I3C handle state */ handle_state = hi3c->State; @@ -5199,6 +5810,13 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Receive_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeD { status = HAL_BUSY; } + /* check if DEF and GRP CCC notifications are enabled */ + else if ((I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_DEFIE) != RESET) || + (I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_GRPIE) != RESET)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } /* Verify the dynamic address validity */ else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U) { @@ -6850,10 +7468,100 @@ static HAL_StatusTypeDef I3C_Ctrl_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint3 if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_TXFNFF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_TXFNFIE) != RESET)) { - if (hi3c->TxXferCount > 0U) + if (hi3c->TxXferCount > 0U) + { + /* Call Transmit treatment function */ + hi3c->ptrTxFunc(hi3c); + } + } + + /* I3C target frame complete event Check */ + if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_FCF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_FCIE) != RESET)) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + + if (hi3c->ControlXferCount == 0U) + { + /* Disable Rx process interrupts */ + I3C_Disable_IRQ(hi3c, I3C_XFER_CONTROLLER_RX_CCC_IT); + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + + /* Call the receive complete callback */ +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + hi3c->CtrlRxCpltCallback(hi3c); +#else + HAL_I3C_CtrlRxCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + + /* Call the receive complete callback */ +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + hi3c->CtrlRxCpltCallback(hi3c); +#else + HAL_I3C_CtrlRxCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + + /* Then Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + } + } + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handles controller multiple transmission/reception in interrupt mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itFlags : [IN] Interrupt flags to handle. + * @param itSources : [IN] Interrupt sources enabled. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_ISR(struct __I3C_HandleTypeDef *hi3c, + uint32_t itFlags, + uint32_t itSources) +{ + /* Check that a Tx/Rx process is ongoing */ + if (hi3c->State == HAL_I3C_STATE_BUSY_TX_RX) + { + /* Check if Control FIFO requests data */ + if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_CFNFF) != RESET) && + (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_CFNFIE) != RESET)) + { + if (hi3c->ControlXferCount > 0U) + { + /* Call control data treatment function */ + I3C_ControlDataTreatment(hi3c); + } + } + + /* I3C Tx FIFO not full interrupt Check */ + if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_TXFNFF) != RESET) && + (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_TXFNFIE) != RESET)) + { + if (hi3c->TxXferCount > 0U) + { + /* Call Transmit treatment function */ + hi3c->ptrTxFunc(hi3c); + } + } + + /* I3C Rx FIFO not empty interrupt Check */ + if ((I3C_CHECK_FLAG(itFlags, HAL_I3C_FLAG_RXFNEF) != RESET) && + (I3C_CHECK_IT_SOURCE(itSources, HAL_I3C_IT_RXFNEIE) != RESET)) + { + if (hi3c->RxXferCount > 0U) { - /* Call Transmit treatment function */ - hi3c->ptrTxFunc(hi3c); + /* Call receive treatment function */ + hi3c->ptrRxFunc(hi3c); } } @@ -6865,6 +7573,9 @@ static HAL_StatusTypeDef I3C_Ctrl_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint3 if (hi3c->ControlXferCount == 0U) { + /* Disable Tx process interrupts */ + I3C_Disable_IRQ(hi3c, I3C_XFER_CONTROLLER_TX_IT); + /* Disable Rx process interrupts */ I3C_Disable_IRQ(hi3c, I3C_XFER_CONTROLLER_RX_CCC_IT); @@ -6873,24 +7584,17 @@ static HAL_StatusTypeDef I3C_Ctrl_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint3 hi3c->ErrorCode = HAL_I3C_ERROR_NONE; - /* Call the receive complete callback */ + /* Call the transmit, receive complete callback to inform upper layer of End of Transfer */ #if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) - hi3c->CtrlRxCpltCallback(hi3c); + hi3c->CtrlMultipleXferCpltCallback(hi3c); #else - HAL_I3C_CtrlRxCpltCallback(hi3c); + HAL_I3C_CtrlMultipleXferCpltCallback(hi3c); #endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ } else { hi3c->ErrorCode = HAL_I3C_ERROR_NONE; - /* Call the receive complete callback */ -#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) - hi3c->CtrlRxCpltCallback(hi3c); -#else - HAL_I3C_CtrlRxCpltCallback(hi3c); -#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ - /* Then Initiate a Start condition */ LL_I3C_RequestTransfer(hi3c->Instance); } @@ -7116,6 +7820,83 @@ static HAL_StatusTypeDef I3C_Ctrl_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, u } return HAL_OK; } + +/** + * @brief Interrupt Sub-Routine which handles controller multiple receive and transmit data in DMA mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itFlags : [IN] Interrupt flags to handle. + * @param itSources : [IN] Interrupt sources enabled. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, + uint32_t itFlags, + uint32_t itSources) +{ + /* Check that an Rx or Tx process is ongoing */ + if (hi3c->State == HAL_I3C_STATE_BUSY_TX_RX) + { + /* I3C target frame complete event Check */ + if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_FCF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_FCIE) != RESET)) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + + if (I3C_GET_DMA_REMAIN_DATA(hi3c->hdmacr) == 0U) + { + /* Check if all data bytes are received or transmitted */ + if (I3C_GET_DMA_REMAIN_DATA(hi3c->hdmarx) == 0U) + { + if (I3C_GET_DMA_REMAIN_DATA(hi3c->hdmatx) == 0U) + { + /* Disable transfer Tx/Rx process interrupts */ + I3C_Disable_IRQ(hi3c, I3C_XFER_DMA); + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + + /* Update the number of remaining data bytes */ + hi3c->RxXferCount = 0U; + + /* Update the number of remaining data bytes */ + hi3c->TxXferCount = 0U; + + /* Call controller transmit, receive complete callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + hi3c->CtrlMultipleXferCpltCallback(hi3c); +#else + HAL_I3C_CtrlMultipleXferCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_SIZE; + + /* Call error treatment function */ + I3C_ErrorTreatment(hi3c); + } + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_SIZE; + + /* Call error treatment function */ + I3C_ErrorTreatment(hi3c); + } + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + + /* Then Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + } + } + return HAL_OK; +} #endif /* HAL_DMA_MODULE_ENABLED */ /** @@ -7574,90 +8355,249 @@ static void I3C_GetErrorSources(I3C_HandleTypeDef *hi3c) } /** - * @brief I3C Tx buffer prior preparation. + * @brief I3C transfer prior preparation. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration * information for the specified I3C. * @param counter : [IN] Number of devices or commands to treat. * @param option : [IN] Parameter indicates the transfer option. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ -static HAL_StatusTypeDef I3C_TxBuffer_PriorPreparation(I3C_HandleTypeDef *hi3c, uint8_t counter, uint32_t option) +static HAL_StatusTypeDef I3C_Xfer_PriorPreparation(I3C_HandleTypeDef *hi3c, uint8_t counter, uint32_t option) { - HAL_StatusTypeDef status = HAL_OK; - uint32_t size = 0U; - uint32_t global_index = 0U; + HAL_StatusTypeDef status = HAL_OK; + uint32_t current_tx_index = 0U; + uint32_t global_tx_size = 0U; + uint32_t global_rx_size = 0U; + uint32_t nb_tx_frame = 0U; + uint32_t direction; - /* Check on the Tx buffer pointer */ - if (hi3c->pXferData->TxBuf.pBuffer == NULL) - { - status = HAL_ERROR; - } - else + for (uint32_t descr_index = 0U; descr_index < counter; descr_index++) { - /* For loop to get the global Tx transfer size */ - for (uint32_t descr_index = 0U; descr_index < counter; descr_index++) + /* Direct CCC command */ + if ((option & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_DIRECT) { - /* Check if private or CCC transfer */ - if (((option & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_DIRECT) || - ((option & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_CCC)) + /* Update direction of frame */ + direction = hi3c->pCCCDesc[descr_index].Direction; + + /* Direction read with Define byte */ + if (((option & I3C_DEFINE_BYTE_MASK) != 0U) && (direction == HAL_I3C_DIRECTION_READ)) + { + nb_tx_frame += 1U; + + global_tx_size += 1U; + + global_rx_size += hi3c->pCCCDesc[descr_index].CCCBuf.Size - 1U; + + /* Check on the global size and on the Tx buffer pointer */ + if ((global_tx_size > hi3c->pXferData->TxBuf.Size) || \ + (current_tx_index > hi3c->pXferData->TxBuf.Size) || \ + (hi3c->pXferData->TxBuf.pBuffer == NULL)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + + status = HAL_ERROR; + } + else + { + /* Fill global Tx buffer with data and update the current index of the Tx buffer */ + current_tx_index = I3C_FillTxBuffer_CCC(hi3c, descr_index, 1U, current_tx_index); + } + } + else if (direction == HAL_I3C_DIRECTION_WRITE) { - size += hi3c->pCCCDesc[descr_index].CCCBuf.Size; + nb_tx_frame += 1U; + + global_tx_size += hi3c->pCCCDesc[descr_index].CCCBuf.Size; + + /* Check on the global size and on the Tx buffer pointer */ + if ((global_tx_size > hi3c->pXferData->TxBuf.Size) || \ + (current_tx_index > hi3c->pXferData->TxBuf.Size) || \ + (hi3c->pXferData->TxBuf.pBuffer == NULL)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; - /* In case of defining byte and direction read, remove size of RX part in the CCCBuf.Size - to retrieve the size of defining byte */ - if (((option & I3C_DEFINE_BYTE_MASK) != 0U) && - (hi3c->pCCCDesc[descr_index].Direction == HAL_I3C_DIRECTION_READ)) + status = HAL_ERROR; + } + else { - size -= hi3c->pXferData->RxBuf.Size; + /* Fill global Tx buffer with data and update the current index of the Tx buffer */ + current_tx_index = I3C_FillTxBuffer_CCC(hi3c, + descr_index, + hi3c->pCCCDesc[descr_index].CCCBuf.Size, + current_tx_index); } } + /* Direction read without Define byte */ else { - size += hi3c->pPrivateDesc[descr_index].TxBuf.Size; + global_rx_size += hi3c->pCCCDesc[descr_index].CCCBuf.Size; } } - - /* Check on the global size */ - if (size > hi3c->pXferData->TxBuf.Size) + /* Broadcast CCC command */ + else if ((option & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_CCC) { - status = HAL_ERROR; + /* Update direction of frame */ + direction = hi3c->pCCCDesc[descr_index].Direction; + + if (direction == HAL_I3C_DIRECTION_WRITE) + { + nb_tx_frame += 1U; + + global_tx_size += hi3c->pCCCDesc[descr_index].CCCBuf.Size; + + /* Check on the global size and on the Tx buffer pointer */ + if ((global_tx_size > hi3c->pXferData->TxBuf.Size) || \ + (current_tx_index > hi3c->pXferData->TxBuf.Size) || \ + (hi3c->pXferData->TxBuf.pBuffer == NULL)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + + status = HAL_ERROR; + } + else + { + /* Fill global Tx buffer with data and update the current index of the Tx buffer */ + current_tx_index = I3C_FillTxBuffer_CCC(hi3c, + descr_index, + hi3c->pCCCDesc[descr_index].CCCBuf.Size, + current_tx_index); + } + } + else + { + status = HAL_ERROR; + } } + /* Private */ else { - /* Fill global Tx buffer with data */ - for (uint32_t descr_index = 0U; descr_index < counter; descr_index++) + /* Update direction of frame */ + direction = hi3c->pPrivateDesc[descr_index].Direction; + + if (direction == HAL_I3C_DIRECTION_WRITE) { - /* Check if private or CCC transfer */ - if (((option & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_DIRECT) || - ((option & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_CCC)) + nb_tx_frame += 1U; + + global_tx_size += hi3c->pPrivateDesc[descr_index].TxBuf.Size; + + /* Check on the global size and on the Tx buffer pointer */ + if ((global_tx_size > hi3c->pXferData->TxBuf.Size) || \ + (current_tx_index > hi3c->pXferData->TxBuf.Size) || \ + (hi3c->pXferData->TxBuf.pBuffer == NULL)) { - for (uint32_t tx_index = 0U; tx_index < hi3c->pCCCDesc[descr_index].CCCBuf.Size; tx_index++) - { - hi3c->pXferData->TxBuf.pBuffer[global_index] = hi3c->pCCCDesc[descr_index].CCCBuf.pBuffer[tx_index]; - global_index++; - } + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + + status = HAL_ERROR; } else { - for (uint32_t tx_index = 0U; tx_index < hi3c->pPrivateDesc[descr_index].TxBuf.Size; tx_index++) - { - hi3c->pXferData->TxBuf.pBuffer[global_index] = hi3c->pPrivateDesc[descr_index].TxBuf.pBuffer[tx_index]; - global_index++; - } + /* Fill global Tx buffer with data and update the current index of the Tx buffer */ + current_tx_index = I3C_FillTxBuffer_Private(hi3c, + descr_index, + hi3c->pPrivateDesc[descr_index].TxBuf.Size, + current_tx_index); } } + else + { + global_rx_size += hi3c->pPrivateDesc[descr_index].RxBuf.Size; + } } - if (status == HAL_OK) + /* Check if there is an error in the Tx Buffer*/ + if (status == HAL_ERROR) { - /* Set handle transfer parameters */ - hi3c->TxXferCount = size; + break; + } + } + + if (status == HAL_OK) + { + /* Check on the Tx threshold and the number of Tx frame */ + if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_4_4) + { + /* LL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains + multiple transmission frames */ + if (nb_tx_frame > 1U) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + } + } + + if (status == HAL_OK) + { + /* Check on the size Rx buffer */ + if (global_rx_size > hi3c->pXferData->RxBuf.Size) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + hi3c->RxXferCount = global_rx_size; } + + /* Set handle transfer parameters */ + hi3c->TxXferCount = global_tx_size; } return status; } +/** + * @brief I3C fill Tx Buffer with data from CCC Descriptor. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @param indexDesc : [IN] Index of descriptor. + * @param txSize : [IN] Size of Tx data. + * @param txCurrentIndex : [IN] Current Index of TxBuffer. + * @retval index_tx : [OUT] New current Index of TxBuffer. + */ +static uint32_t I3C_FillTxBuffer_CCC(I3C_HandleTypeDef *hi3c, + uint32_t indexDesc, + uint32_t txSize, + uint32_t txCurrentIndex) +{ + uint32_t index_tx = txCurrentIndex; + + for (uint32_t index = 0U; index < txSize; index++) + { + hi3c->pXferData->TxBuf.pBuffer[index_tx] = hi3c->pCCCDesc[indexDesc].CCCBuf.pBuffer[index]; + + index_tx++; + } + + return index_tx; +} + +/** + * @brief I3C fill Tx Buffer with data from Private Descriptor. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @param indexDesc : [IN] Index of descriptor. + * @param txSize : [IN] Size of Tx data. + * @param txCurrentIndex : [IN] Current Index of TxBuffer. + * @retval index_tx : [OUT] New current Index of TxBuffer. + */ +static uint32_t I3C_FillTxBuffer_Private(I3C_HandleTypeDef *hi3c, + uint32_t indexDesc, + uint32_t txSize, + uint32_t txCurrentIndex) +{ + uint32_t index_tx = txCurrentIndex; + + for (uint32_t index = 0U; index < txSize; index++) + { + hi3c->pXferData->TxBuf.pBuffer[index_tx] = hi3c->pPrivateDesc[indexDesc].TxBuf.pBuffer[index]; + + index_tx++; + } + + return index_tx; +} + /** * @brief I3C Control buffer prior preparation. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration @@ -7694,6 +8634,11 @@ static HAL_StatusTypeDef I3C_ControlBuffer_PriorPreparation(I3C_HandleTypeDef *h /* Disable arbitration header */ LL_I3C_DisableArbitrationHeader(hi3c->Instance); } + else + { + /* Enable arbitration header */ + LL_I3C_EnableArbitrationHeader(hi3c->Instance); + } /* Check on the operation type */ if ((option & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_CCC) @@ -7750,7 +8695,7 @@ static HAL_StatusTypeDef I3C_ControlBuffer_PriorPreparation(I3C_HandleTypeDef *h /* Step 2 : update control buffer value for target address */ hi3c->pXferData->CtrlBuf.pBuffer[index + 1U] = (((uint32_t)hi3c->pCCCDesc[index / 2U].CCCBuf.Size - nb_define_bytes) | - hi3c->pCCCDesc->Direction | + hi3c->pCCCDesc[index / 2U].Direction | ((uint32_t)hi3c->pCCCDesc[index / 2U].TargetAddr << I3C_CR_ADD_Pos) | LL_I3C_CONTROLLER_MTYPE_DIRECT | stop_condition); } @@ -7763,7 +8708,7 @@ static HAL_StatusTypeDef I3C_ControlBuffer_PriorPreparation(I3C_HandleTypeDef *h /* At the last device we should generate a stop condition */ hi3c->pXferData->CtrlBuf.pBuffer[index + 1U] = (((uint32_t)hi3c->pCCCDesc[index / 2U].CCCBuf.Size - nb_define_bytes) | - hi3c->pCCCDesc->Direction | + hi3c->pCCCDesc[index / 2U].Direction | ((uint32_t)hi3c->pCCCDesc[index / 2U].TargetAddr << I3C_CR_ADD_Pos) | LL_I3C_CONTROLLER_MTYPE_DIRECT | LL_I3C_GENERATE_STOP); } @@ -7824,6 +8769,128 @@ static HAL_StatusTypeDef I3C_ControlBuffer_PriorPreparation(I3C_HandleTypeDef *h return status; } +/** + * @brief Check if target device is ready for communication. + * @param hi3c : Pointer to a I3C_HandleTypeDef structure that contains + * the configuration information for the specified I3C. + * @param pDevice : [IN] Structure to define the device address and the device type. + * @param trials : [IN] Number of trials + * @param timeout : [IN] Timeout duration + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Ctrl_IsDevice_Ready(I3C_HandleTypeDef *hi3c, + const I3C_DeviceTypeDef *pDevice, + uint32_t trials, + uint32_t timeout) +{ + __IO uint32_t I3C_Trials = 0UL; + __IO uint32_t exit_condition; + uint32_t CR_tmp; + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + HAL_I3C_StateTypeDef handle_state; + uint32_t arbitration_previous_state; + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* check on the Mode */ + if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY; + + /* Before modify the arbitration, get the current arbitration state */ + arbitration_previous_state = LL_I3C_IsEnabledArbitrationHeader(hi3c->Instance); + + /* Disable arbitration header */ + LL_I3C_DisableArbitrationHeader(hi3c->Instance); + + CR_tmp = (HAL_I3C_DIRECTION_WRITE | + ((uint32_t)pDevice->Address << I3C_CR_ADD_Pos) | + pDevice->MessageType | LL_I3C_GENERATE_STOP); + + do + { + /* Initiate a start condition by writing in the CR register */ + WRITE_REG(hi3c->Instance->CR, CR_tmp); + + /* Calculate exit_condition value based on Frame complete and error flags */ + exit_condition = (READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF)); + + tickstart = HAL_GetTick(); + + while (exit_condition == 0U) + { + if (timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U)) + { + /* Update I3C error code */ + hi3c->ErrorCode |= HAL_I3C_ERROR_TIMEOUT; + status = HAL_TIMEOUT; + + break; + } + } + /* Calculate exit_condition value based on Frame complete and error flags */ + exit_condition = (READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF)); + } + + if (status == HAL_OK) + { + /* Check if the FCF flag has been set */ + if (__HAL_I3C_GET_FLAG(hi3c, I3C_EVR_FCF) == SET) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + + /* Device is ready */ + break; + } + else + { + /* Clear ERR flag */ + LL_I3C_ClearFlag_ERR(hi3c->Instance); + } + } + + /* Increment Trials */ + I3C_Trials++; + + } while ((I3C_Trials < trials) && (status == HAL_OK)); + + /* Device is not ready */ + if (trials == I3C_Trials) + { + hi3c->ErrorCode = HAL_I3C_ERROR_ADDRESS_NACK; + status = HAL_ERROR; + } + + /* update state to Previous state */ + I3C_StateUpdate(hi3c); + + /* Check if previous arbitration state is enabled */ + if (arbitration_previous_state == 1U) + { + LL_I3C_EnableArbitrationHeader(hi3c->Instance); + } + } + + return status; +} + /** * @brief Manage the enabling of Interrupts. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_irda.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_irda.c index cc01344ea3..aa3b34c5b5 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_irda.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_irda.c @@ -142,7 +142,7 @@ [..] Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -159,10 +159,10 @@ [..] By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak functions: examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init() + reset to the legacy weak functions in the HAL_IRDA_Init() and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -179,7 +179,7 @@ [..] When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim ****************************************************************************** @@ -466,7 +466,7 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) /** * @brief Register a User IRDA Callback - * To be used instead of the weak predefined callback + * To be used to override the weak predefined callback * @note The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET * to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID * @param hirda irda handle diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_mmc.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_mmc.c index e26a54996b..2b6c22cb98 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_mmc.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_mmc.c @@ -251,6 +251,7 @@ * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) #ifdef HAL_MMC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ @@ -4298,6 +4299,7 @@ __weak void HAL_MMCEx_Write_DMALnkLstBufCpltCallback(MMC_HandleTypeDef *hmmc) */ #endif /* HAL_MMC_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_mmc_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_mmc_ex.c index bbf6a9e3cd..a40a12bfee 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_mmc_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_mmc_ex.c @@ -45,6 +45,7 @@ * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) #ifdef HAL_MMC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ @@ -436,6 +437,7 @@ HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc, M */ #endif /* HAL_MMC_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nand.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nand.c index ca0a6aedaf..ff123ebce2 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nand.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nand.c @@ -9,7 +9,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2023 STMicroelectronics. + * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -77,15 +77,15 @@ and a pointer to the user callback function. Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) MspInitCallback : NAND MspInit. (+) MspDeInitCallback : NAND MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_NAND_Init + reset to the legacy weak (overridden) functions in the HAL_NAND_Init and HAL_NAND_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -100,7 +100,7 @@ When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -1901,7 +1901,7 @@ uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeD #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) /** * @brief Register a User NAND Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hnand : NAND handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: @@ -1921,9 +1921,6 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_ return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hnand); - if (hnand->State == HAL_NAND_STATE_READY) { switch (CallbackId) @@ -1965,14 +1962,12 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hnand); return status; } /** * @brief Unregister a User NAND Callback - * NAND Callback is redirected to the weak (surcharged) predefined callback + * NAND Callback is redirected to the weak predefined callback * @param hnand : NAND handle * @param CallbackId : ID of the callback to be unregistered * This parameter can be one of the following values: @@ -1985,9 +1980,6 @@ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAN { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hnand); - if (hnand->State == HAL_NAND_STATE_READY) { switch (CallbackId) @@ -2029,8 +2021,6 @@ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAN status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hnand); return status; } #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nor.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nor.c index 4fb9f9eb60..517c6fa684 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nor.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nor.c @@ -9,7 +9,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2023 STMicroelectronics. + * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -74,15 +74,15 @@ and a pointer to the user callback function. Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) MspInitCallback : NOR MspInit. (+) MspDeInitCallback : NOR MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_NOR_Init + reset to the legacy weak (overridden) functions in the HAL_NOR_Init and HAL_NOR_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -97,7 +97,7 @@ When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -409,7 +409,7 @@ __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor) * @param Timeout Maximum timeout value * @retval None */ -__weak void HAL_NOR_MspWait(const NOR_HandleTypeDef *hnor, uint32_t Timeout) +__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) { /* Prevent unused argument(s) compilation warning */ UNUSED(hnor); @@ -1312,7 +1312,7 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) /** * @brief Register a User NOR Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hnor : NOR handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: @@ -1332,9 +1332,6 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Call return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hnor); - state = hnor->State; if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) { @@ -1358,14 +1355,12 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hnor); return status; } /** * @brief Unregister a User NOR Callback - * NOR Callback is redirected to the weak (surcharged) predefined callback + * NOR Callback is redirected to the weak predefined callback * @param hnor : NOR handle * @param CallbackId : ID of the callback to be unregistered * This parameter can be one of the following values: @@ -1378,9 +1373,6 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Ca HAL_StatusTypeDef status = HAL_OK; HAL_NOR_StateTypeDef state; - /* Process locked */ - __HAL_LOCK(hnor); - state = hnor->State; if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) { @@ -1404,8 +1396,6 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hnor); return status; } #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */ @@ -1536,7 +1526,7 @@ HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor) * @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR * or HAL_NOR_STATUS_TIMEOUT */ -HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(const NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) +HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) { HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING; uint16_t tmpsr1; diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c index c87b8376f3..0fc1114968 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c @@ -753,18 +753,19 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng) void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) { uint32_t rngclockerror = 0U; + uint32_t itflag = hrng->Instance->SR; /* RNG clock error interrupt occurred */ - if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) + if ((itflag & RNG_IT_CEI) == RNG_IT_CEI) { /* Update the error code */ hrng->ErrorCode = HAL_RNG_ERROR_CLOCK; rngclockerror = 1U; } - else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + else if ((itflag & RNG_IT_SEI) == RNG_IT_SEI) { /* Check if Seed Error Current Status (SECS) is set */ - if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) == RESET) + if ((itflag & RNG_FLAG_SECS) != RNG_FLAG_SECS) { /* RNG IP performed the reset automatically (auto-reset) */ /* Clear bit SEIS */ @@ -804,7 +805,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) } /* Check RNG data ready interrupt occurred */ - if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET) + if ((itflag & RNG_IT_DRDY) == RNG_IT_DRDY) { /* Generate random number once, so disable the IT */ __HAL_RNG_DISABLE_IT(hrng); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng_ex.c index 809bf72aca..c0fe2f2816 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng_ex.c @@ -77,7 +77,7 @@ * RNG_ConfigTypeDef. * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. - * @param pConf: pointer to a RNG_ConfigTypeDef structure that contains + * @param pConf pointer to a RNG_ConfigTypeDef structure that contains * the configuration information for RNG module * @retval HAL status @@ -173,7 +173,7 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigT * RNG_ConfigTypeDef. * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. - * @param pConf: pointer to a RNG_ConfigTypeDef structure that contains + * @param pConf pointer to a RNG_ConfigTypeDef structure that contains * the configuration information for RNG module * @retval HAL status diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai.c index 8007490ce7..c0805263a4 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai.c @@ -1382,6 +1382,12 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) /* Process Locked */ __HAL_LOCK(hsai); + /* Disable SAI peripheral */ + if (SAI_Disable(hsai) != HAL_OK) + { + status = HAL_ERROR; + } + /* Disable the SAI DMA request */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; @@ -1413,12 +1419,6 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) } } - /* Disable SAI peripheral */ - if (SAI_Disable(hsai) != HAL_OK) - { - status = HAL_ERROR; - } - /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); @@ -1444,6 +1444,12 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) /* Process Locked */ __HAL_LOCK(hsai); + /* Disable SAI peripheral */ + if (SAI_Disable(hsai) != HAL_OK) + { + status = HAL_ERROR; + } + /* Check SAI DMA is enabled or not */ if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) { @@ -1483,12 +1489,6 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) hsai->Instance->IMR = 0; hsai->Instance->CLRFR = 0xFFFFFFFFU; - /* Disable SAI peripheral */ - if (SAI_Disable(hsai) != HAL_OK) - { - status = HAL_ERROR; - } - /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd.c index ba9116ca57..1ba5e096d9 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd.c @@ -259,6 +259,7 @@ * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) #ifdef HAL_SD_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ @@ -435,7 +436,7 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) tickstart = HAL_GetTick(); while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State = HAL_SD_STATE_READY; @@ -2808,7 +2809,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t tickstart = HAL_GetTick(); while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State = HAL_SD_STATE_READY; @@ -2891,7 +2892,7 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) { while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State = HAL_SD_STATE_READY; @@ -2904,7 +2905,7 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) { while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State = HAL_SD_STATE_READY; @@ -2917,7 +2918,7 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) { while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State = HAL_SD_STATE_READY; @@ -3213,7 +3214,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /* Check to CKSTOP */ while ((hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3243,7 +3244,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /* Check VSWEND Flag */ while ((hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3351,7 +3352,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) } } - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3379,7 +3380,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) *pData = SDMMC_ReadFIFO(hsd->Instance); pData++; - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3570,7 +3571,7 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) } - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3745,7 +3746,7 @@ uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode) loop ++; } - if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - Timeout) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State = HAL_SD_STATE_READY; @@ -3861,7 +3862,7 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd, uint32_t UltraHighSpeed loop ++; } - if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - Timeout) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State = HAL_SD_STATE_READY; @@ -3988,7 +3989,7 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd) loop ++; } - if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - Timeout) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State = HAL_SD_STATE_READY; @@ -4086,6 +4087,7 @@ __weak void HAL_SDEx_Write_DMALnkLstBufCpltCallback(SD_HandleTypeDef *hsd) */ #endif /* HAL_SD_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd_ex.c index e2b6f13112..7689a0b70c 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd_ex.c @@ -44,6 +44,7 @@ * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) #ifdef HAL_SD_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ @@ -381,6 +382,7 @@ HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd, SDMM */ #endif /* HAL_SD_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sdram.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sdram.c index fc19bf7a25..16e05f8df7 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sdram.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sdram.c @@ -9,7 +9,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2023 STMicroelectronics. + * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -82,15 +82,15 @@ and a pointer to the user callback function. Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) MspInitCallback : SDRAM MspInit. (+) MspDeInitCallback : SDRAM MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SDRAM_Init + reset to the legacy weak (overridden) functions in the HAL_SDRAM_Init and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -105,7 +105,7 @@ When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -912,7 +912,7 @@ HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) /** * @brief Register a User SDRAM Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hsdram : SDRAM handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: @@ -933,9 +933,6 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SD return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsdram); - state = hsdram->State; if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) { @@ -978,14 +975,12 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SD status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsdram); return status; } /** * @brief Unregister a User SDRAM Callback - * SDRAM Callback is redirected to the weak (surcharged) predefined callback + * SDRAM Callback is redirected to the weak predefined callback * @param hsdram : SDRAM handle * @param CallbackId : ID of the callback to be unregistered * This parameter can be one of the following values: @@ -1001,9 +996,6 @@ HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_ HAL_StatusTypeDef status = HAL_OK; HAL_SDRAM_StateTypeDef state; - /* Process locked */ - __HAL_LOCK(hsdram); - state = hsdram->State; if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) { @@ -1052,14 +1044,12 @@ HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsdram); return status; } /** * @brief Register a User SDRAM Callback for DMA transfers - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hsdram : SDRAM handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smartcard.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smartcard.c index 8400b87ed8..da61bcf8d6 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smartcard.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smartcard.c @@ -136,7 +136,7 @@ [..] Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -153,10 +153,10 @@ [..] By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak functions: examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init() + reset to the legacy weak functions in the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -173,7 +173,7 @@ [..] When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim @@ -469,7 +469,7 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) /** * @brief Register a User SMARTCARD Callback - * To be used instead of the weak predefined callback + * To be used to override the weak predefined callback * @note The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init() * in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID * and HAL_SMARTCARD_MSPDEINIT_CB_ID diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smbus.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smbus.c index 3d21c46d2c..22254296b3 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smbus.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smbus.c @@ -987,8 +987,15 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) { - hsmbus->XferSize--; - hsmbus->XferCount--; + if (hsmbus->XferSize > 0U) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + else + { + return HAL_ERROR; + } } } diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c index 8829d36f7f..0769a12e44 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c @@ -9,7 +9,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2023 STMicroelectronics. + * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -83,15 +83,15 @@ and a pointer to the user callback function. Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) MspInitCallback : SRAM MspInit. (+) MspDeInitCallback : SRAM MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SRAM_Init + reset to the legacy weak (overridden) functions in the HAL_SRAM_Init and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -106,7 +106,7 @@ When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -861,7 +861,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) /** * @brief Register a User SRAM Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hsram : SRAM handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: @@ -881,9 +881,6 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_ return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsram); - state = hsram->State; if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED)) { @@ -907,14 +904,12 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsram); return status; } /** * @brief Unregister a User SRAM Callback - * SRAM Callback is redirected to the weak (surcharged) predefined callback + * SRAM Callback is redirected to the weak predefined callback * @param hsram : SRAM handle * @param CallbackId : ID of the callback to be unregistered * This parameter can be one of the following values: @@ -929,9 +924,6 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRA HAL_StatusTypeDef status = HAL_OK; HAL_SRAM_StateTypeDef state; - /* Process locked */ - __HAL_LOCK(hsram); - state = hsram->State; if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) { @@ -977,14 +969,12 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRA status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsram); return status; } /** * @brief Register a User SRAM Callback for DMA transfers - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hsram : SRAM handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c index 884a730fce..cdae141f78 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c @@ -900,7 +900,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) uint32_t tmpsmcr; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) @@ -992,7 +992,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { @@ -1071,7 +1071,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel uint32_t tmpsmcr; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Set the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) @@ -1233,7 +1233,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { @@ -1569,7 +1569,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel uint32_t tmpsmcr; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) @@ -1661,7 +1661,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { @@ -1740,7 +1740,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe uint32_t tmpsmcr; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Set the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) @@ -1901,7 +1901,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { @@ -2145,7 +2145,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) @@ -2193,7 +2193,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Disable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); @@ -2229,7 +2229,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) @@ -2317,7 +2317,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { @@ -2393,7 +2393,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); /* Set the TIM channel state */ @@ -2548,7 +2548,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); /* Disable the Input Capture channel */ @@ -3845,10 +3845,13 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { + uint32_t itsource = htim->Instance->DIER; + uint32_t itflag = htim->Instance->SR; + /* Capture compare 1 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); @@ -3879,9 +3882,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* Capture compare 2 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; @@ -3909,9 +3912,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* Capture compare 3 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; @@ -3939,9 +3942,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* Capture compare 4 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; @@ -3969,9 +3972,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Update event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) @@ -3982,9 +3985,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Break input event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) @@ -3995,9 +3998,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Break2 input event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) + if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) @@ -4008,9 +4011,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Trigger detection event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) @@ -4021,9 +4024,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM commutation event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) @@ -4034,9 +4037,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Encoder index event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_IDX) != RESET) + if ((itflag & (TIM_FLAG_IDX)) == (TIM_FLAG_IDX)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_IDX) != RESET) + if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX)) { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IDX); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) @@ -4047,9 +4050,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Direction change event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_DIR) != RESET) + if ((itflag & (TIM_FLAG_DIR)) == (TIM_FLAG_DIR)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_DIR) != RESET) + if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR)) { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_DIR); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) @@ -4060,9 +4063,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Index error event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_IERR) != RESET) + if ((itflag & (TIM_FLAG_IERR)) == (TIM_FLAG_IERR)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_IERR) != RESET) + if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR)) { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IERR); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) @@ -4073,9 +4076,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Transition error event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TERR) != RESET) + if ((itflag & (TIM_FLAG_TERR)) == (TIM_FLAG_TERR)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TERR) != RESET) + if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR)) { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_TERR); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) @@ -4630,8 +4633,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, - uint32_t BurstLength) + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength) { HAL_StatusTypeDef status = HAL_OK; uint32_t BlockDataLength = 0; @@ -4777,7 +4779,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t */ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, - uint32_t BurstLength, uint32_t DataLength) + uint32_t BurstLength, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpDBSS = 0; @@ -5084,8 +5086,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, - uint32_t BurstLength) + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { HAL_StatusTypeDef status = HAL_OK; uint32_t BlockDataLength = 0; @@ -5230,8 +5231,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, - uint32_t BurstLength, uint32_t DataLength) + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpDBSS = 0; @@ -7354,11 +7355,12 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7429,11 +7431,12 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7505,11 +7508,12 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7579,11 +7583,12 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7657,11 +7662,12 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ @@ -7710,11 +7716,12 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ @@ -7908,9 +7915,9 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC1E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Select the Input */ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) @@ -7998,9 +8005,9 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; @@ -8037,9 +8044,9 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; @@ -8081,9 +8088,9 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccer; /* Disable the Channel 3: Reset the CC3E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC3E; tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC3S; @@ -8129,9 +8136,9 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccer; /* Disable the Channel 4: Reset the CC4E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC4E; tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S; diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c index 96738b96c1..d367dbf284 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c @@ -107,7 +107,7 @@ [..] Use function HAL_UART_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -131,10 +131,10 @@ [..] By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak functions: examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_UART_Init() + reset to the legacy weak functions in the HAL_UART_Init() and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -151,7 +151,7 @@ [..] When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim @@ -350,15 +350,17 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* In asynchronous mode, the following bits must be kept cleared: @@ -415,15 +417,17 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* In half-duplex mode, the following bits must be kept cleared: @@ -501,15 +505,17 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* In LIN mode, the following bits must be kept cleared: @@ -585,15 +591,17 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* In multiprocessor mode, the following bits must be kept cleared: @@ -698,7 +706,7 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /** * @brief Register a User UART Callback - * To be used instead of the weak predefined callback + * To be used to override the weak predefined callback * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID @@ -3270,6 +3278,13 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + } + /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) { @@ -3291,13 +3306,6 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); } - /* if required, configure RX/TX pins swap */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) - { - assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); - } - /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) { diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c index aaf39462d0..551ad99fe2 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c @@ -211,15 +211,17 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c index 6a10553333..273c50b849 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c @@ -91,7 +91,7 @@ [..] Use function HAL_USART_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -109,10 +109,10 @@ [..] By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak functions: examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_USART_Init() + reset to the legacy weak functions in the HAL_USART_Init() and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -129,7 +129,7 @@ [..] When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim @@ -408,7 +408,7 @@ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) /** * @brief Register a User USART Callback - * To be used instead of the weak predefined callback + * To be used to override the weak predefined callback * @note The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET * to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID * @param husart usart handle diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dac.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dac.c index a721f41bba..4583232d48 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dac.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dac.c @@ -46,91 +46,91 @@ * @{ */ #define IS_LL_DAC_CHANNEL(__DAC_CHANNEL__) \ - ( ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ - || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \ + (((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ + || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \ ) #if defined(TIM8) /* Devices STM32H563/H573xx */ -#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ - (((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_CH1) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM2_CH1) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ +#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ + ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_CH1) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM2_CH1) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ ) #else /* Devices STM32H503xx */ #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ - (((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_CH1) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM2_CH1) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ + ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_CH1) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM2_CH1) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ ) #endif /* Devices STM32H563/H573xx or STM32H503xx */ #define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \ - ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \ - || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ - || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ + (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \ + || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ + || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ ) #define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__) \ ( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ - && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \ + && (((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \ ) \ ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ - && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \ + && (((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \ ) \ ) #define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \ - ( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \ - || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \ + (((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \ + || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \ ) #define IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__) \ - ( ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO) \ - || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \ + (((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO) \ + || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \ ) #define IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__) \ - ( ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL) \ - || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \ + (((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL) \ + || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \ ) /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmc.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmc.c index 0e047d3fea..0105b3cce9 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmc.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmc.c @@ -13,7 +13,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2023 STMicroelectronics. + * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -60,7 +60,8 @@ /** @addtogroup STM32H5xx_HAL_Driver * @{ */ -#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED) +#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\ + || defined(HAL_SRAM_MODULE_ENABLED) /** @defgroup FMC_LL FMC Low Layer * @brief FMC driver modules diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_sdmmc.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_sdmmc.c index 553bea8b46..5ecc55c77b 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_sdmmc.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_sdmmc.c @@ -162,6 +162,7 @@ * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) #if defined (HAL_SD_MODULE_ENABLED) || defined (HAL_MMC_MODULE_ENABLED) /* Private typedef -----------------------------------------------------------*/ @@ -1872,6 +1873,7 @@ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) */ #endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_tim.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_tim.c index 6fbb08eede..7059879738 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_tim.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_tim.c @@ -795,7 +795,6 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); - MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); @@ -1410,8 +1409,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM * @} */ -#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 \ - || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */ +#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */ /** * @} diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index dd386f0d45..f9d1620321 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -9,7 +9,7 @@ * STM32F7: 1.3.0 * STM32G0: 1.4.4 * STM32G4: 1.2.2 - * STM32H5: 1.0.0 + * STM32H5: 1.1.0 * STM32H7: 1.11.1 * STM32L0: 1.10.6 * STM32L1: 1.4.5 diff --git a/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c b/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c index e8949a0fb6..f6bc0386ae 100644 --- a/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c +++ b/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503CBTx.xml, STM32H503CBUx.xml - * CubeMX DB release 6.0.80 + * CubeMX DB release 6.0.90 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H503EBY/PeripheralPins.c b/variants/STM32H5xx/H503EBY/PeripheralPins.c index f69841d140..5afaedf6f3 100644 --- a/variants/STM32H5xx/H503EBY/PeripheralPins.c +++ b/variants/STM32H5xx/H503EBY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503EBYx.xml - * CubeMX DB release 6.0.80 + * CubeMX DB release 6.0.90 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H503KBU/PeripheralPins.c b/variants/STM32H5xx/H503KBU/PeripheralPins.c index e78a2853cd..25cab80aa4 100644 --- a/variants/STM32H5xx/H503KBU/PeripheralPins.c +++ b/variants/STM32H5xx/H503KBU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503KBUx.xml - * CubeMX DB release 6.0.80 + * CubeMX DB release 6.0.90 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H503RBT/PeripheralPins.c b/variants/STM32H5xx/H503RBT/PeripheralPins.c index 25e98902c5..1e36de03c6 100644 --- a/variants/STM32H5xx/H503RBT/PeripheralPins.c +++ b/variants/STM32H5xx/H503RBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503RBTx.xml - * CubeMX DB release 6.0.80 + * CubeMX DB release 6.0.90 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c b/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c index fe850f5877..532cc28305 100644 --- a/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c +++ b/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562AGIx.xml, STM32H562AIIx.xml - * CubeMX DB release 6.0.80 + * CubeMX DB release 6.0.90 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -647,11 +647,11 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { //*** USB *** #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB_DRD_FS[] = { - {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c b/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c index 128dd2a58c..cd29035a1f 100644 --- a/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c +++ b/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H562IGKx.xml, STM32H562IGTx.xml * STM32H562IIKx.xml, STM32H562IITx.xml - * CubeMX DB release 6.0.80 + * CubeMX DB release 6.0.90 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -656,11 +656,11 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { //*** USB *** #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB_DRD_FS[] = { - {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c index 8564410406..abdd5e6de5 100644 --- a/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c +++ b/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562RGTx.xml, STM32H562RITx.xml - * CubeMX DB release 6.0.80 + * CubeMX DB release 6.0.90 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -443,11 +443,11 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { //*** USB *** #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB_DRD_FS[] = { - {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c b/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c index 9f3f438ce6..d5b567e1a7 100644 --- a/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c +++ b/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562RGVx.xml, STM32H562RIVx.xml - * CubeMX DB release 6.0.80 + * CubeMX DB release 6.0.90 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -463,11 +463,11 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { //*** USB *** #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB_DRD_FS[] = { - {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c index 139d13fe7a..2f936e3a7a 100644 --- a/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c +++ b/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562VGTx.xml, STM32H562VITx.xml - * CubeMX DB release 6.0.80 + * CubeMX DB release 6.0.90 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -532,11 +532,11 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { //*** USB *** #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB_DRD_FS[] = { - {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c index 8e2c396deb..522dea4447 100644 --- a/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c +++ b/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562ZGTx.xml, STM32H562ZITx.xml - * CubeMX DB release 6.0.80 + * CubeMX DB release 6.0.90 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -597,11 +597,11 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { //*** USB *** #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB_DRD_FS[] = { - {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H563A(G-I)I_H573AII/CMakeLists.txt b/variants/STM32H5xx/H563A(G-I)I/CMakeLists.txt similarity index 100% rename from variants/STM32H5xx/H563A(G-I)I_H573AII/CMakeLists.txt rename to variants/STM32H5xx/H563A(G-I)I/CMakeLists.txt diff --git a/variants/STM32H5xx/H563A(G-I)I/PeripheralPins.c b/variants/STM32H5xx/H563A(G-I)I/PeripheralPins.c new file mode 100644 index 0000000000..27dd73dcd4 --- /dev/null +++ b/variants/STM32H5xx/H563A(G-I)I/PeripheralPins.c @@ -0,0 +1,827 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32H563AGIx.xml, STM32H563AIIx.xml + * CubeMX DB release 6.0.90 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 + {PF_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 + {PF_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 + {PF_13, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 + {PF_14, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_15, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PG_6, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PH_5, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PH_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_5, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PG_7, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PH_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PH_11, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PF_15, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PG_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PH_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PF_5, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PG_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PH_11, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N + {PF_6, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PF_7, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PF_8, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PF_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PF_9, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PF_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PH_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PH_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PH_6_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PH_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PH_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PH_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PH_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PH_10_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PH_10_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PH_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PH_11_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PH_11_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PH_12, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PH_12_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 4, 1)}, // TIM8_CH4N + {PH_13, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PI_0, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PI_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PI_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PI_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_15, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_2, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_3, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, + {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PE_10, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_3, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PF_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_1, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PG_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PG_12, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {PG_14, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PH_13, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PH_13_ALT1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART8)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_7, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_14, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_0, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_2, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, + {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PE_9, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_4, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PF_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_6, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PG_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PG_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_11, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {PH_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PC_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_13, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PD_15, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_7, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_11, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PG_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_14, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_15_ALT1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_14, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_8, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_5, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PF_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_13, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {PG_13_ALT1, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PF_11, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + {PG_14, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PH_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PI_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PH_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PI_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PC_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_13, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PH_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PI_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_8, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PG_10, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PH_5, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PI_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_9, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PH_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PE_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PH_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** ETHERNET *** + +#ifdef HAL_ETH_MODULE_ENABLED +WEAK const PinMap PinMap_Ethernet[] = { + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER + {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PH_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + {PH_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL + {PH_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 + {PH_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 + {NC, NP, 0} +}; +#endif + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PD_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PF_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PD_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PF_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {PE_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {PF_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 + {PD_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PF_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PE_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PH_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 + {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PE_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PH_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 + {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PE_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PG_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PG_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PF_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_NCS + {PG_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PA_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CMD + {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CK + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {PD_6, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PB_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D0 + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PG_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D1 + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {PG_10, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D2 + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {PG_11, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D3 + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {PG_12, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA5[] = { + {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 + {PC_6_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6 + {PG_13, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {PC_7_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7 + {PG_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN + {PB_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CDIR[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CDIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H563A(G-I)I_H573AII/PinNamesVar.h b/variants/STM32H5xx/H563A(G-I)I/PinNamesVar.h similarity index 100% rename from variants/STM32H5xx/H563A(G-I)I_H573AII/PinNamesVar.h rename to variants/STM32H5xx/H563A(G-I)I/PinNamesVar.h diff --git a/variants/STM32H5xx/H563A(G-I)I_H573AII/boards_entry.txt b/variants/STM32H5xx/H563A(G-I)I/boards_entry.txt similarity index 70% rename from variants/STM32H5xx/H563A(G-I)I_H573AII/boards_entry.txt rename to variants/STM32H5xx/H563A(G-I)I/boards_entry.txt index a6d0f8a4b3..65884e8614 100644 --- a/variants/STM32H5xx/H563A(G-I)I_H573AII/boards_entry.txt +++ b/variants/STM32H5xx/H563A(G-I)I/boards_entry.txt @@ -9,7 +9,7 @@ GenH5.menu.pnum.GENERIC_H563AGIX.upload.maximum_size=1048576 GenH5.menu.pnum.GENERIC_H563AGIX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563AGIX.build.board=GENERIC_H563AGIX GenH5.menu.pnum.GENERIC_H563AGIX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563AGIX.build.variant=STM32H5xx/H563A(G-I)I_H573AII +GenH5.menu.pnum.GENERIC_H563AGIX.build.variant=STM32H5xx/H563A(G-I)I # Generic H563AIIx GenH5.menu.pnum.GENERIC_H563AIIX=Generic H563AIIx @@ -17,13 +17,5 @@ GenH5.menu.pnum.GENERIC_H563AIIX.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563AIIX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563AIIX.build.board=GENERIC_H563AIIX GenH5.menu.pnum.GENERIC_H563AIIX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563AIIX.build.variant=STM32H5xx/H563A(G-I)I_H573AII - -# Generic H573AIIx -GenH5.menu.pnum.GENERIC_H573AIIX=Generic H573AIIx -GenH5.menu.pnum.GENERIC_H573AIIX.upload.maximum_size=2097152 -GenH5.menu.pnum.GENERIC_H573AIIX.upload.maximum_data_size=655360 -GenH5.menu.pnum.GENERIC_H573AIIX.build.board=GENERIC_H573AIIX -GenH5.menu.pnum.GENERIC_H573AIIX.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573AIIX.build.variant=STM32H5xx/H563A(G-I)I_H573AII +GenH5.menu.pnum.GENERIC_H563AIIX.build.variant=STM32H5xx/H563A(G-I)I diff --git a/variants/STM32H5xx/H563A(G-I)I_H573AII/generic_clock.c b/variants/STM32H5xx/H563A(G-I)I/generic_clock.c similarity index 94% rename from variants/STM32H5xx/H563A(G-I)I_H573AII/generic_clock.c rename to variants/STM32H5xx/H563A(G-I)I/generic_clock.c index 5bee13d537..a70d6bdff6 100644 --- a/variants/STM32H5xx/H563A(G-I)I_H573AII/generic_clock.c +++ b/variants/STM32H5xx/H563A(G-I)I/generic_clock.c @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563AGIX) || defined(ARDUINO_GENERIC_H563AIIX) ||\ - defined(ARDUINO_GENERIC_H573AIIX) +#if defined(ARDUINO_GENERIC_H563AGIX) || defined(ARDUINO_GENERIC_H563AIIX) #include "pins_arduino.h" /** diff --git a/variants/STM32H5xx/H563A(G-I)I_H573AII/variant_generic.cpp b/variants/STM32H5xx/H563A(G-I)I/variant_generic.cpp similarity index 98% rename from variants/STM32H5xx/H563A(G-I)I_H573AII/variant_generic.cpp rename to variants/STM32H5xx/H563A(G-I)I/variant_generic.cpp index 493eed1506..e87b94786a 100644 --- a/variants/STM32H5xx/H563A(G-I)I_H573AII/variant_generic.cpp +++ b/variants/STM32H5xx/H563A(G-I)I/variant_generic.cpp @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563AGIX) || defined(ARDUINO_GENERIC_H563AIIX) ||\ - defined(ARDUINO_GENERIC_H573AIIX) +#if defined(ARDUINO_GENERIC_H563AGIX) || defined(ARDUINO_GENERIC_H563AIIX) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32H5xx/H563A(G-I)I_H573AII/variant_generic.h b/variants/STM32H5xx/H563A(G-I)I/variant_generic.h similarity index 100% rename from variants/STM32H5xx/H563A(G-I)I_H573AII/variant_generic.h rename to variants/STM32H5xx/H563A(G-I)I/variant_generic.h diff --git a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/CMakeLists.txt b/variants/STM32H5xx/H563AIIxQ/CMakeLists.txt similarity index 100% rename from variants/STM32H5xx/H563AIIxQ_H573AIIxQ/CMakeLists.txt rename to variants/STM32H5xx/H563AIIxQ/CMakeLists.txt diff --git a/variants/STM32H5xx/H563AIIxQ/PeripheralPins.c b/variants/STM32H5xx/H563AIIxQ/PeripheralPins.c new file mode 100644 index 0000000000..daa191ba12 --- /dev/null +++ b/variants/STM32H5xx/H563AIIxQ/PeripheralPins.c @@ -0,0 +1,816 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32H563AIIxQ.xml + * CubeMX DB release 6.0.90 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 + {PF_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 + {PF_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 + {PF_13, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 + {PF_14, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_15, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PG_6, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PH_5, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PH_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_5, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PG_7, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PH_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PH_11, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PF_15, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PG_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PH_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PF_5, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PG_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PH_11, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N + {PF_6, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PF_7, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PF_8, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PF_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PF_9, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PF_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PH_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PH_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PH_6_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PH_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PH_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PH_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PH_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PH_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_9_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PH_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PH_10_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PH_10_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PH_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PH_11_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PH_11_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PH_12, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PH_12_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 4, 1)}, // TIM8_CH4N + {PH_13, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PI_0, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PI_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PI_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PI_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PI_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_15, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_2, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_3, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, + {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PE_10, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_3, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PF_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_1, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PG_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PG_12, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {PH_13, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PH_13_ALT1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART8)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_7, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_14, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_0, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_2, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, + {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PE_9, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_4, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PF_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_6, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PG_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PG_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PH_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PC_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_13, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PD_15, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_7, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_15_ALT1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_14, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_8, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_5, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PF_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PF_11, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + {PH_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PI_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PH_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PI_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PC_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PH_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PI_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_8, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PG_10, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PH_5, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PH_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PI_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_9, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PH_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PE_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PH_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** ETHERNET *** + +#ifdef HAL_ETH_MODULE_ENABLED +WEAK const PinMap PinMap_Ethernet[] = { + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER + {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PH_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + {PH_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL + {PH_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 + {PH_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 + {NC, NP, 0} +}; +#endif + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PD_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PF_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PD_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PF_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {PE_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {PF_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 + {PD_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PF_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PE_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PH_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 + {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PE_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PH_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 + {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PE_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PG_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PF_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_NCS + {PG_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PA_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CMD + {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CK + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {PD_6, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PB_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D0 + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PG_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D1 + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {PG_10, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D2 + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D3 + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {PG_12, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA5[] = { + {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 + {PC_6_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {PC_7_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN + {PB_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CDIR[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CDIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PinNamesVar.h b/variants/STM32H5xx/H563AIIxQ/PinNamesVar.h similarity index 100% rename from variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PinNamesVar.h rename to variants/STM32H5xx/H563AIIxQ/PinNamesVar.h diff --git a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/boards_entry.txt b/variants/STM32H5xx/H563AIIxQ/boards_entry.txt similarity index 59% rename from variants/STM32H5xx/H563AIIxQ_H573AIIxQ/boards_entry.txt rename to variants/STM32H5xx/H563AIIxQ/boards_entry.txt index 1e9e8114db..9797c155d5 100644 --- a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/boards_entry.txt +++ b/variants/STM32H5xx/H563AIIxQ/boards_entry.txt @@ -9,13 +9,5 @@ GenH5.menu.pnum.GENERIC_H563AIIXQ.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563AIIXQ.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563AIIXQ.build.board=GENERIC_H563AIIXQ GenH5.menu.pnum.GENERIC_H563AIIXQ.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563AIIXQ.build.variant=STM32H5xx/H563AIIxQ_H573AIIxQ - -# Generic H573AIIxQ -GenH5.menu.pnum.GENERIC_H573AIIXQ=Generic H573AIIxQ -GenH5.menu.pnum.GENERIC_H573AIIXQ.upload.maximum_size=2097152 -GenH5.menu.pnum.GENERIC_H573AIIXQ.upload.maximum_data_size=655360 -GenH5.menu.pnum.GENERIC_H573AIIXQ.build.board=GENERIC_H573AIIXQ -GenH5.menu.pnum.GENERIC_H573AIIXQ.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573AIIXQ.build.variant=STM32H5xx/H563AIIxQ_H573AIIxQ +GenH5.menu.pnum.GENERIC_H563AIIXQ.build.variant=STM32H5xx/H563AIIxQ diff --git a/variants/STM32H5xx/H563IITxQ_H573IITxQ/generic_clock.c b/variants/STM32H5xx/H563AIIxQ/generic_clock.c similarity index 91% rename from variants/STM32H5xx/H563IITxQ_H573IITxQ/generic_clock.c rename to variants/STM32H5xx/H563AIIxQ/generic_clock.c index 7719cc5de0..8659be2dce 100644 --- a/variants/STM32H5xx/H563IITxQ_H573IITxQ/generic_clock.c +++ b/variants/STM32H5xx/H563AIIxQ/generic_clock.c @@ -10,7 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563IITXQ) || defined(ARDUINO_GENERIC_H573IITXQ) +#if defined(ARDUINO_GENERIC_H563AIIXQ) #include "pins_arduino.h" /** diff --git a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/variant_generic.cpp b/variants/STM32H5xx/H563AIIxQ/variant_generic.cpp similarity index 97% rename from variants/STM32H5xx/H563AIIxQ_H573AIIxQ/variant_generic.cpp rename to variants/STM32H5xx/H563AIIxQ/variant_generic.cpp index 83bb5a4b95..880f7ce59c 100644 --- a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/variant_generic.cpp +++ b/variants/STM32H5xx/H563AIIxQ/variant_generic.cpp @@ -10,7 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563AIIXQ) || defined(ARDUINO_GENERIC_H573AIIXQ) +#if defined(ARDUINO_GENERIC_H563AIIXQ) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/variant_generic.h b/variants/STM32H5xx/H563AIIxQ/variant_generic.h similarity index 100% rename from variants/STM32H5xx/H563AIIxQ_H573AIIxQ/variant_generic.h rename to variants/STM32H5xx/H563AIIxQ/variant_generic.h diff --git a/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/CMakeLists.txt b/variants/STM32H5xx/H563I(G-I)(K-T)/CMakeLists.txt similarity index 100% rename from variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/CMakeLists.txt rename to variants/STM32H5xx/H563I(G-I)(K-T)/CMakeLists.txt diff --git a/variants/STM32H5xx/H563I(G-I)(K-T)/PeripheralPins.c b/variants/STM32H5xx/H563I(G-I)(K-T)/PeripheralPins.c new file mode 100644 index 0000000000..1877ad1f9b --- /dev/null +++ b/variants/STM32H5xx/H563I(G-I)(K-T)/PeripheralPins.c @@ -0,0 +1,837 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32H563IGKx.xml, STM32H563IGTx.xml + * STM32H563IIKx.xml, STM32H563IITx.xml + * CubeMX DB release 6.0.90 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 + {PF_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 + {PF_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 + {PF_13, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 + {PF_14, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_15, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PG_6, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PH_5, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PH_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_5, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PG_7, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PH_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PH_11, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PF_15, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PG_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PH_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PF_5, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PG_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PH_11, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N + {PF_6, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PF_7, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PF_8, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PF_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PF_9, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PF_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PH_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PH_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PH_6_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PH_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PH_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PH_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PH_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PH_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_9_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PH_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PH_10_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PH_10_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PH_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PH_11_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PH_11_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PH_12, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PH_12_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 4, 1)}, // TIM8_CH4N + {PH_13, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PI_0, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PI_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PI_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PI_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PI_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_15, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_2, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_3, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, + {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PE_10, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_3, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PF_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_1, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PG_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PG_12, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {PG_14, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PH_13, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PH_13_ALT1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART8)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_7, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_14, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_0, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_2, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, + {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PE_9, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_4, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PF_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_6, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PG_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PG_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_11, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {PH_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PI_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PC_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_13, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PD_15, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_7, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_11, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PG_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_14, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_15_ALT1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_14, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_8, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_5, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PF_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_13, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {PG_13_ALT1, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PF_11, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + {PG_14, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PH_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PI_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PH_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PI_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PC_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_13, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PH_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PI_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_8, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PG_10, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PH_5, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PH_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PI_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_9, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PH_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PI_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PI_10, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PE_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PH_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** ETHERNET *** + +#ifdef HAL_ETH_MODULE_ENABLED +WEAK const PinMap PinMap_Ethernet[] = { + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER + {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PH_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + {PH_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL + {PH_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 + {PH_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 + {PI_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER + {NC, NP, 0} +}; +#endif + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PD_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PF_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PD_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PF_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {PE_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {PF_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 + {PD_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PF_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PE_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PH_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 + {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PE_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PH_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 + {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PE_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PG_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PG_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PF_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_NCS + {PG_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PA_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CMD + {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CK + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {PD_6, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PB_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D0 + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PG_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D1 + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {PG_10, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D2 + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {PG_11, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D3 + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {PG_12, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA5[] = { + {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 + {PC_6_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6 + {PG_13, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {PC_7_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7 + {PG_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN + {PB_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CDIR[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CDIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/PinNamesVar.h b/variants/STM32H5xx/H563I(G-I)(K-T)/PinNamesVar.h similarity index 100% rename from variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/PinNamesVar.h rename to variants/STM32H5xx/H563I(G-I)(K-T)/PinNamesVar.h diff --git a/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/boards_entry.txt b/variants/STM32H5xx/H563I(G-I)(K-T)/boards_entry.txt similarity index 66% rename from variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/boards_entry.txt rename to variants/STM32H5xx/H563I(G-I)(K-T)/boards_entry.txt index 796d2d201a..e54004a38d 100644 --- a/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/boards_entry.txt +++ b/variants/STM32H5xx/H563I(G-I)(K-T)/boards_entry.txt @@ -9,7 +9,7 @@ GenH5.menu.pnum.GENERIC_H563IGKX.upload.maximum_size=1048576 GenH5.menu.pnum.GENERIC_H563IGKX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563IGKX.build.board=GENERIC_H563IGKX GenH5.menu.pnum.GENERIC_H563IGKX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563IGKX.build.variant=STM32H5xx/H563I(G-I)(K-T)_H573II(K-T) +GenH5.menu.pnum.GENERIC_H563IGKX.build.variant=STM32H5xx/H563I(G-I)(K-T) # Generic H563IGTx GenH5.menu.pnum.GENERIC_H563IGTX=Generic H563IGTx @@ -17,7 +17,7 @@ GenH5.menu.pnum.GENERIC_H563IGTX.upload.maximum_size=1048576 GenH5.menu.pnum.GENERIC_H563IGTX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563IGTX.build.board=GENERIC_H563IGTX GenH5.menu.pnum.GENERIC_H563IGTX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563IGTX.build.variant=STM32H5xx/H563I(G-I)(K-T)_H573II(K-T) +GenH5.menu.pnum.GENERIC_H563IGTX.build.variant=STM32H5xx/H563I(G-I)(K-T) # Generic H563IIKx GenH5.menu.pnum.GENERIC_H563IIKX=Generic H563IIKx @@ -25,7 +25,7 @@ GenH5.menu.pnum.GENERIC_H563IIKX.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563IIKX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563IIKX.build.board=GENERIC_H563IIKX GenH5.menu.pnum.GENERIC_H563IIKX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563IIKX.build.variant=STM32H5xx/H563I(G-I)(K-T)_H573II(K-T) +GenH5.menu.pnum.GENERIC_H563IIKX.build.variant=STM32H5xx/H563I(G-I)(K-T) # Generic H563IITx GenH5.menu.pnum.GENERIC_H563IITX=Generic H563IITx @@ -33,21 +33,5 @@ GenH5.menu.pnum.GENERIC_H563IITX.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563IITX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563IITX.build.board=GENERIC_H563IITX GenH5.menu.pnum.GENERIC_H563IITX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563IITX.build.variant=STM32H5xx/H563I(G-I)(K-T)_H573II(K-T) - -# Generic H573IIKx -GenH5.menu.pnum.GENERIC_H573IIKX=Generic H573IIKx -GenH5.menu.pnum.GENERIC_H573IIKX.upload.maximum_size=2097152 -GenH5.menu.pnum.GENERIC_H573IIKX.upload.maximum_data_size=655360 -GenH5.menu.pnum.GENERIC_H573IIKX.build.board=GENERIC_H573IIKX -GenH5.menu.pnum.GENERIC_H573IIKX.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573IIKX.build.variant=STM32H5xx/H563I(G-I)(K-T)_H573II(K-T) - -# Generic H573IITx -GenH5.menu.pnum.GENERIC_H573IITX=Generic H573IITx -GenH5.menu.pnum.GENERIC_H573IITX.upload.maximum_size=2097152 -GenH5.menu.pnum.GENERIC_H573IITX.upload.maximum_data_size=655360 -GenH5.menu.pnum.GENERIC_H573IITX.build.board=GENERIC_H573IITX -GenH5.menu.pnum.GENERIC_H573IITX.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573IITX.build.variant=STM32H5xx/H563I(G-I)(K-T)_H573II(K-T) +GenH5.menu.pnum.GENERIC_H563IITX.build.variant=STM32H5xx/H563I(G-I)(K-T) diff --git a/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/generic_clock.c b/variants/STM32H5xx/H563I(G-I)(K-T)/generic_clock.c similarity index 91% rename from variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/generic_clock.c rename to variants/STM32H5xx/H563I(G-I)(K-T)/generic_clock.c index 941ef32ee7..00fee101c2 100644 --- a/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/generic_clock.c +++ b/variants/STM32H5xx/H563I(G-I)(K-T)/generic_clock.c @@ -11,8 +11,7 @@ ******************************************************************************* */ #if defined(ARDUINO_GENERIC_H563IGKX) || defined(ARDUINO_GENERIC_H563IGTX) ||\ - defined(ARDUINO_GENERIC_H563IIKX) || defined(ARDUINO_GENERIC_H563IITX) ||\ - defined(ARDUINO_GENERIC_H573IIKX) || defined(ARDUINO_GENERIC_H573IITX) + defined(ARDUINO_GENERIC_H563IIKX) || defined(ARDUINO_GENERIC_H563IITX) #include "pins_arduino.h" /** diff --git a/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/variant_generic.cpp b/variants/STM32H5xx/H563I(G-I)(K-T)/variant_generic.cpp similarity index 97% rename from variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/variant_generic.cpp rename to variants/STM32H5xx/H563I(G-I)(K-T)/variant_generic.cpp index 6e4b482a27..6c09ffed3a 100644 --- a/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/variant_generic.cpp +++ b/variants/STM32H5xx/H563I(G-I)(K-T)/variant_generic.cpp @@ -11,8 +11,7 @@ ******************************************************************************* */ #if defined(ARDUINO_GENERIC_H563IGKX) || defined(ARDUINO_GENERIC_H563IGTX) ||\ - defined(ARDUINO_GENERIC_H563IIKX) || defined(ARDUINO_GENERIC_H563IITX) ||\ - defined(ARDUINO_GENERIC_H573IIKX) || defined(ARDUINO_GENERIC_H573IITX) + defined(ARDUINO_GENERIC_H563IIKX) || defined(ARDUINO_GENERIC_H563IITX) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/variant_generic.h b/variants/STM32H5xx/H563I(G-I)(K-T)/variant_generic.h similarity index 100% rename from variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/variant_generic.h rename to variants/STM32H5xx/H563I(G-I)(K-T)/variant_generic.h diff --git a/variants/STM32H5xx/H563IITxQ_H573IITxQ/CMakeLists.txt b/variants/STM32H5xx/H563IIKxQ/CMakeLists.txt similarity index 100% rename from variants/STM32H5xx/H563IITxQ_H573IITxQ/CMakeLists.txt rename to variants/STM32H5xx/H563IIKxQ/CMakeLists.txt diff --git a/variants/STM32H5xx/H563IIKxQ/PeripheralPins.c b/variants/STM32H5xx/H563IIKxQ/PeripheralPins.c new file mode 100644 index 0000000000..8781fb9713 --- /dev/null +++ b/variants/STM32H5xx/H563IIKxQ/PeripheralPins.c @@ -0,0 +1,834 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32H563IIKxQ.xml + * CubeMX DB release 6.0.90 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 + {PF_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 + {PF_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 + {PF_13, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 + {PF_14, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_15, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PG_6, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PH_5, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PH_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_5, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PG_7, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PH_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PH_11, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PF_15, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PG_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PH_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PF_5, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PG_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PH_11, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N + {PF_6, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PF_7, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PF_8, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PF_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PF_9, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PF_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PH_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PH_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PH_6_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PH_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PH_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PH_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PH_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PH_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_9_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PH_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PH_10_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PH_10_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PH_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PH_11_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PH_11_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PH_12, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PH_12_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 4, 1)}, // TIM8_CH4N + {PH_13, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PI_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PI_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PI_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PI_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_15, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_2, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_3, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, + {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PE_10, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_3, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PF_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_1, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PG_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PG_12, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {PG_14, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PH_13, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PH_13_ALT1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART8)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_7, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_14, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_0, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_2, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, + {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PE_9, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_4, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PF_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_6, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PG_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PG_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_11, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {PH_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PI_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PC_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_13, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PD_15, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_7, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_11, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PG_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_14, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_15_ALT1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_14, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_8, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_5, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PF_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_13, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {PG_13_ALT1, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PF_11, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + {PG_14, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PH_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PI_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PH_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PI_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PC_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_13, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PH_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PI_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_8, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PG_10, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PH_5, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PH_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_9, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PH_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PI_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PI_10, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PE_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PH_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** ETHERNET *** + +#ifdef HAL_ETH_MODULE_ENABLED +WEAK const PinMap PinMap_Ethernet[] = { + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER + {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PH_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + {PH_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL + {PH_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 + {PH_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 + {PI_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER + {NC, NP, 0} +}; +#endif + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PD_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PF_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PD_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PF_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {PE_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {PF_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 + {PD_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PF_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PE_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PH_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 + {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PE_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PH_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 + {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PE_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PG_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PG_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PF_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_NCS + {PG_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PA_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CMD + {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CK + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {PD_6, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PB_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D0 + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PG_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D1 + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {PG_10, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D2 + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {PG_11, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D3 + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {PG_12, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA5[] = { + {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 + {PC_6_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6 + {PG_13, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {PC_7_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7 + {PG_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN + {PB_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CDIR[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CDIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PinNamesVar.h b/variants/STM32H5xx/H563IIKxQ/PinNamesVar.h similarity index 100% rename from variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PinNamesVar.h rename to variants/STM32H5xx/H563IIKxQ/PinNamesVar.h diff --git a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/boards_entry.txt b/variants/STM32H5xx/H563IIKxQ/boards_entry.txt similarity index 59% rename from variants/STM32H5xx/H563IIKxQ_H573IIKxQ/boards_entry.txt rename to variants/STM32H5xx/H563IIKxQ/boards_entry.txt index 4bba114ae0..8783be74c9 100644 --- a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/boards_entry.txt +++ b/variants/STM32H5xx/H563IIKxQ/boards_entry.txt @@ -9,13 +9,5 @@ GenH5.menu.pnum.GENERIC_H563IIKXQ.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563IIKXQ.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563IIKXQ.build.board=GENERIC_H563IIKXQ GenH5.menu.pnum.GENERIC_H563IIKXQ.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563IIKXQ.build.variant=STM32H5xx/H563IIKxQ_H573IIKxQ - -# Generic H573IIKxQ -GenH5.menu.pnum.GENERIC_H573IIKXQ=Generic H573IIKxQ -GenH5.menu.pnum.GENERIC_H573IIKXQ.upload.maximum_size=2097152 -GenH5.menu.pnum.GENERIC_H573IIKXQ.upload.maximum_data_size=655360 -GenH5.menu.pnum.GENERIC_H573IIKXQ.build.board=GENERIC_H573IIKXQ -GenH5.menu.pnum.GENERIC_H573IIKXQ.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573IIKXQ.build.variant=STM32H5xx/H563IIKxQ_H573IIKxQ +GenH5.menu.pnum.GENERIC_H563IIKXQ.build.variant=STM32H5xx/H563IIKxQ diff --git a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/generic_clock.c b/variants/STM32H5xx/H563IIKxQ/generic_clock.c similarity index 97% rename from variants/STM32H5xx/H563IIKxQ_H573IIKxQ/generic_clock.c rename to variants/STM32H5xx/H563IIKxQ/generic_clock.c index 708820d6df..68a5da81e2 100644 --- a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/generic_clock.c +++ b/variants/STM32H5xx/H563IIKxQ/generic_clock.c @@ -10,7 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563IIKXQ) || defined(ARDUINO_GENERIC_H573IIKXQ) +#if defined(ARDUINO_GENERIC_H563IIKXQ) #include "pins_arduino.h" /** diff --git a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/ldscript.ld b/variants/STM32H5xx/H563IIKxQ/ldscript.ld similarity index 100% rename from variants/STM32H5xx/H563IIKxQ_H573IIKxQ/ldscript.ld rename to variants/STM32H5xx/H563IIKxQ/ldscript.ld diff --git a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_generic.cpp b/variants/STM32H5xx/H563IIKxQ/variant_generic.cpp similarity index 97% rename from variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_generic.cpp rename to variants/STM32H5xx/H563IIKxQ/variant_generic.cpp index 3c7f322f5d..58977c2352 100644 --- a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_generic.cpp +++ b/variants/STM32H5xx/H563IIKxQ/variant_generic.cpp @@ -10,7 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563IIKXQ) || defined(ARDUINO_GENERIC_H573IIKXQ) +#if defined(ARDUINO_GENERIC_H563IIKXQ) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_generic.h b/variants/STM32H5xx/H563IIKxQ/variant_generic.h similarity index 100% rename from variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_generic.h rename to variants/STM32H5xx/H563IIKxQ/variant_generic.h diff --git a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/CMakeLists.txt b/variants/STM32H5xx/H563IITxQ/CMakeLists.txt similarity index 100% rename from variants/STM32H5xx/H563MIYxQ_H573MIYxQ/CMakeLists.txt rename to variants/STM32H5xx/H563IITxQ/CMakeLists.txt diff --git a/variants/STM32H5xx/H563IITxQ/PeripheralPins.c b/variants/STM32H5xx/H563IITxQ/PeripheralPins.c new file mode 100644 index 0000000000..bff5fbcc78 --- /dev/null +++ b/variants/STM32H5xx/H563IITxQ/PeripheralPins.c @@ -0,0 +1,828 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32H563IITxQ.xml + * CubeMX DB release 6.0.90 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 + {PF_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 + {PF_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 + {PF_13, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 + {PF_14, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_15, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PG_6, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PH_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_5, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PG_7, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PH_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PH_11, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PF_15, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PG_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PH_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PF_5, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PG_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PH_11, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N + {PF_6, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PF_7, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PF_8, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PF_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PF_9, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PF_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PH_6, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PH_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PH_6_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PH_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PH_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PH_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_9_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PH_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PH_10_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PH_10_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PH_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PH_11_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PH_11_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PH_12, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PH_12_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 4, 1)}, // TIM8_CH4N + {PH_13, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PI_0, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PI_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PI_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PI_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PI_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_15, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_2, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_3, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, + {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PE_10, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_3, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PF_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_1, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PG_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PG_12, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {PG_14, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PH_13, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PH_13_ALT1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART8)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_7, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_14, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_0, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_2, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, + {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PE_9, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_4, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PF_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_6, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PG_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PG_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_11, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {PH_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PI_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PC_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_13, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PD_15, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_7, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_11, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PG_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_14, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_15_ALT1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_14, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_8, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_5, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PF_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_13, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {PG_13_ALT1, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PF_11, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + {PG_14, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PI_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PH_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PI_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PC_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_13, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PH_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PI_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_8, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PG_10, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PH_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PI_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_9, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PH_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PI_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PI_10, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PE_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PH_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** ETHERNET *** + +#ifdef HAL_ETH_MODULE_ENABLED +WEAK const PinMap PinMap_Ethernet[] = { + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER + {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PH_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + {PH_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL + {PH_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 + {PH_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 + {PI_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER + {NC, NP, 0} +}; +#endif + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PD_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PF_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PD_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PF_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {PE_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {PF_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 + {PD_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PF_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PE_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PH_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 + {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PE_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PH_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 + {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PE_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PG_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PG_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_NCS + {PG_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PA_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CMD + {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CK + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {PD_6, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PB_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D0 + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PG_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D1 + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {PG_10, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D2 + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {PG_11, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D3 + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {PG_12, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA5[] = { + {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 + {PC_6_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6 + {PG_13, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {PC_7_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7 + {PG_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN + {PB_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CDIR[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CDIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H563IITxQ_H573IITxQ/PinNamesVar.h b/variants/STM32H5xx/H563IITxQ/PinNamesVar.h similarity index 100% rename from variants/STM32H5xx/H563IITxQ_H573IITxQ/PinNamesVar.h rename to variants/STM32H5xx/H563IITxQ/PinNamesVar.h diff --git a/variants/STM32H5xx/H563IITxQ_H573IITxQ/boards_entry.txt b/variants/STM32H5xx/H563IITxQ/boards_entry.txt similarity index 59% rename from variants/STM32H5xx/H563IITxQ_H573IITxQ/boards_entry.txt rename to variants/STM32H5xx/H563IITxQ/boards_entry.txt index f6d0d1569c..97a0ea5b98 100644 --- a/variants/STM32H5xx/H563IITxQ_H573IITxQ/boards_entry.txt +++ b/variants/STM32H5xx/H563IITxQ/boards_entry.txt @@ -9,13 +9,5 @@ GenH5.menu.pnum.GENERIC_H563IITXQ.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563IITXQ.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563IITXQ.build.board=GENERIC_H563IITXQ GenH5.menu.pnum.GENERIC_H563IITXQ.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563IITXQ.build.variant=STM32H5xx/H563IITxQ_H573IITxQ - -# Generic H573IITxQ -GenH5.menu.pnum.GENERIC_H573IITXQ=Generic H573IITxQ -GenH5.menu.pnum.GENERIC_H573IITXQ.upload.maximum_size=2097152 -GenH5.menu.pnum.GENERIC_H573IITXQ.upload.maximum_data_size=655360 -GenH5.menu.pnum.GENERIC_H573IITXQ.build.board=GENERIC_H573IITXQ -GenH5.menu.pnum.GENERIC_H573IITXQ.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573IITXQ.build.variant=STM32H5xx/H563IITxQ_H573IITxQ +GenH5.menu.pnum.GENERIC_H563IITXQ.build.variant=STM32H5xx/H563IITxQ diff --git a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/generic_clock.c b/variants/STM32H5xx/H563IITxQ/generic_clock.c similarity index 91% rename from variants/STM32H5xx/H563MIYxQ_H573MIYxQ/generic_clock.c rename to variants/STM32H5xx/H563IITxQ/generic_clock.c index 273a5c2e75..c7322cb46f 100644 --- a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/generic_clock.c +++ b/variants/STM32H5xx/H563IITxQ/generic_clock.c @@ -10,7 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563MIYXQ) || defined(ARDUINO_GENERIC_H573MIYXQ) +#if defined(ARDUINO_GENERIC_H563IITXQ) #include "pins_arduino.h" /** diff --git a/variants/STM32H5xx/H563IITxQ_H573IITxQ/variant_generic.cpp b/variants/STM32H5xx/H563IITxQ/variant_generic.cpp similarity index 97% rename from variants/STM32H5xx/H563IITxQ_H573IITxQ/variant_generic.cpp rename to variants/STM32H5xx/H563IITxQ/variant_generic.cpp index d723d86caa..6e4b701bd8 100644 --- a/variants/STM32H5xx/H563IITxQ_H573IITxQ/variant_generic.cpp +++ b/variants/STM32H5xx/H563IITxQ/variant_generic.cpp @@ -10,7 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563IITXQ) || defined(ARDUINO_GENERIC_H573IITXQ) +#if defined(ARDUINO_GENERIC_H563IITXQ) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32H5xx/H563IITxQ_H573IITxQ/variant_generic.h b/variants/STM32H5xx/H563IITxQ/variant_generic.h similarity index 100% rename from variants/STM32H5xx/H563IITxQ_H573IITxQ/variant_generic.h rename to variants/STM32H5xx/H563IITxQ/variant_generic.h diff --git a/variants/STM32H5xx/H563R(G-I)T_H573RIT/CMakeLists.txt b/variants/STM32H5xx/H563MIYxQ/CMakeLists.txt similarity index 100% rename from variants/STM32H5xx/H563R(G-I)T_H573RIT/CMakeLists.txt rename to variants/STM32H5xx/H563MIYxQ/CMakeLists.txt diff --git a/variants/STM32H5xx/H563MIYxQ/PeripheralPins.c b/variants/STM32H5xx/H563MIYxQ/PeripheralPins.c new file mode 100644 index 0000000000..4f39380c58 --- /dev/null +++ b/variants/STM32H5xx/H563MIYxQ/PeripheralPins.c @@ -0,0 +1,603 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32H563MIYxQ.xml + * CubeMX DB release 6.0.90 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_15, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PE_10, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_7, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_14, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PE_9, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PC_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PE_7, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_15_ALT1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_8, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PC_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** ETHERNET *** + +#ifdef HAL_ETH_MODULE_ENABLED +WEAK const PinMap PinMap_Ethernet[] = { + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {NC, NP, 0} +}; +#endif + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PE_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 + {PE_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 + {PE_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PinNamesVar.h b/variants/STM32H5xx/H563MIYxQ/PinNamesVar.h similarity index 100% rename from variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PinNamesVar.h rename to variants/STM32H5xx/H563MIYxQ/PinNamesVar.h diff --git a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/boards_entry.txt b/variants/STM32H5xx/H563MIYxQ/boards_entry.txt similarity index 59% rename from variants/STM32H5xx/H563MIYxQ_H573MIYxQ/boards_entry.txt rename to variants/STM32H5xx/H563MIYxQ/boards_entry.txt index b6a151fc07..21ec764406 100644 --- a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/boards_entry.txt +++ b/variants/STM32H5xx/H563MIYxQ/boards_entry.txt @@ -9,13 +9,5 @@ GenH5.menu.pnum.GENERIC_H563MIYXQ.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563MIYXQ.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563MIYXQ.build.board=GENERIC_H563MIYXQ GenH5.menu.pnum.GENERIC_H563MIYXQ.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563MIYXQ.build.variant=STM32H5xx/H563MIYxQ_H573MIYxQ - -# Generic H573MIYxQ -GenH5.menu.pnum.GENERIC_H573MIYXQ=Generic H573MIYxQ -GenH5.menu.pnum.GENERIC_H573MIYXQ.upload.maximum_size=2097152 -GenH5.menu.pnum.GENERIC_H573MIYXQ.upload.maximum_data_size=655360 -GenH5.menu.pnum.GENERIC_H573MIYXQ.build.board=GENERIC_H573MIYXQ -GenH5.menu.pnum.GENERIC_H573MIYXQ.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573MIYXQ.build.variant=STM32H5xx/H563MIYxQ_H573MIYxQ +GenH5.menu.pnum.GENERIC_H563MIYXQ.build.variant=STM32H5xx/H563MIYxQ diff --git a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/generic_clock.c b/variants/STM32H5xx/H563MIYxQ/generic_clock.c similarity index 91% rename from variants/STM32H5xx/H563AIIxQ_H573AIIxQ/generic_clock.c rename to variants/STM32H5xx/H563MIYxQ/generic_clock.c index c2db916941..01bd75bd49 100644 --- a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/generic_clock.c +++ b/variants/STM32H5xx/H563MIYxQ/generic_clock.c @@ -10,7 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563AIIXQ) || defined(ARDUINO_GENERIC_H573AIIXQ) +#if defined(ARDUINO_GENERIC_H563MIYXQ) #include "pins_arduino.h" /** diff --git a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/variant_generic.cpp b/variants/STM32H5xx/H563MIYxQ/variant_generic.cpp similarity index 96% rename from variants/STM32H5xx/H563MIYxQ_H573MIYxQ/variant_generic.cpp rename to variants/STM32H5xx/H563MIYxQ/variant_generic.cpp index ff92840911..8691ee0278 100644 --- a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/variant_generic.cpp +++ b/variants/STM32H5xx/H563MIYxQ/variant_generic.cpp @@ -10,7 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563MIYXQ) || defined(ARDUINO_GENERIC_H573MIYXQ) +#if defined(ARDUINO_GENERIC_H563MIYXQ) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/variant_generic.h b/variants/STM32H5xx/H563MIYxQ/variant_generic.h similarity index 100% rename from variants/STM32H5xx/H563MIYxQ_H573MIYxQ/variant_generic.h rename to variants/STM32H5xx/H563MIYxQ/variant_generic.h diff --git a/variants/STM32H5xx/H563R(G-I)V_H573RIV/CMakeLists.txt b/variants/STM32H5xx/H563R(G-I)T/CMakeLists.txt similarity index 100% rename from variants/STM32H5xx/H563R(G-I)V_H573RIV/CMakeLists.txt rename to variants/STM32H5xx/H563R(G-I)T/CMakeLists.txt diff --git a/variants/STM32H5xx/H563R(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H563R(G-I)T/PeripheralPins.c new file mode 100644 index 0000000000..f1ed25238e --- /dev/null +++ b/variants/STM32H5xx/H563R(G-I)T/PeripheralPins.c @@ -0,0 +1,576 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32H563RGTx.xml, STM32H563RITx.xml + * CubeMX DB release 6.0.90 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_7, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_15_ALT1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PC_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {NC, NP, 0} +}; +#endif + +//*** ETHERNET *** + +#ifdef HAL_ETH_MODULE_ENABLED +WEAK const PinMap PinMap_Ethernet[] = { + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {NC, NP, 0} +}; +#endif + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H563R(G-I)T_H573RIT/PinNamesVar.h b/variants/STM32H5xx/H563R(G-I)T/PinNamesVar.h similarity index 100% rename from variants/STM32H5xx/H563R(G-I)T_H573RIT/PinNamesVar.h rename to variants/STM32H5xx/H563R(G-I)T/PinNamesVar.h diff --git a/variants/STM32H5xx/H563R(G-I)T_H573RIT/boards_entry.txt b/variants/STM32H5xx/H563R(G-I)T/boards_entry.txt similarity index 70% rename from variants/STM32H5xx/H563R(G-I)T_H573RIT/boards_entry.txt rename to variants/STM32H5xx/H563R(G-I)T/boards_entry.txt index ac5a9663f4..f7f0eb2ff5 100644 --- a/variants/STM32H5xx/H563R(G-I)T_H573RIT/boards_entry.txt +++ b/variants/STM32H5xx/H563R(G-I)T/boards_entry.txt @@ -9,7 +9,7 @@ GenH5.menu.pnum.GENERIC_H563RGTX.upload.maximum_size=1048576 GenH5.menu.pnum.GENERIC_H563RGTX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563RGTX.build.board=GENERIC_H563RGTX GenH5.menu.pnum.GENERIC_H563RGTX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563RGTX.build.variant=STM32H5xx/H563R(G-I)T_H573RIT +GenH5.menu.pnum.GENERIC_H563RGTX.build.variant=STM32H5xx/H563R(G-I)T # Generic H563RITx GenH5.menu.pnum.GENERIC_H563RITX=Generic H563RITx @@ -17,13 +17,5 @@ GenH5.menu.pnum.GENERIC_H563RITX.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563RITX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563RITX.build.board=GENERIC_H563RITX GenH5.menu.pnum.GENERIC_H563RITX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563RITX.build.variant=STM32H5xx/H563R(G-I)T_H573RIT - -# Generic H573RITx -GenH5.menu.pnum.GENERIC_H573RITX=Generic H573RITx -GenH5.menu.pnum.GENERIC_H573RITX.upload.maximum_size=2097152 -GenH5.menu.pnum.GENERIC_H573RITX.upload.maximum_data_size=655360 -GenH5.menu.pnum.GENERIC_H573RITX.build.board=GENERIC_H573RITX -GenH5.menu.pnum.GENERIC_H573RITX.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573RITX.build.variant=STM32H5xx/H563R(G-I)T_H573RIT +GenH5.menu.pnum.GENERIC_H563RITX.build.variant=STM32H5xx/H563R(G-I)T diff --git a/variants/STM32H5xx/H563R(G-I)T_H573RIT/generic_clock.c b/variants/STM32H5xx/H563R(G-I)T/generic_clock.c similarity index 94% rename from variants/STM32H5xx/H563R(G-I)T_H573RIT/generic_clock.c rename to variants/STM32H5xx/H563R(G-I)T/generic_clock.c index f68f7375d1..42890297f9 100644 --- a/variants/STM32H5xx/H563R(G-I)T_H573RIT/generic_clock.c +++ b/variants/STM32H5xx/H563R(G-I)T/generic_clock.c @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563RGTX) || defined(ARDUINO_GENERIC_H563RITX) ||\ - defined(ARDUINO_GENERIC_H573RITX) +#if defined(ARDUINO_GENERIC_H563RGTX) || defined(ARDUINO_GENERIC_H563RITX) #include "pins_arduino.h" /** diff --git a/variants/STM32H5xx/H563R(G-I)T_H573RIT/variant_generic.cpp b/variants/STM32H5xx/H563R(G-I)T/variant_generic.cpp similarity index 97% rename from variants/STM32H5xx/H563R(G-I)T_H573RIT/variant_generic.cpp rename to variants/STM32H5xx/H563R(G-I)T/variant_generic.cpp index 366177811b..1bcad42048 100644 --- a/variants/STM32H5xx/H563R(G-I)T_H573RIT/variant_generic.cpp +++ b/variants/STM32H5xx/H563R(G-I)T/variant_generic.cpp @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563RGTX) || defined(ARDUINO_GENERIC_H563RITX) ||\ - defined(ARDUINO_GENERIC_H573RITX) +#if defined(ARDUINO_GENERIC_H563RGTX) || defined(ARDUINO_GENERIC_H563RITX) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32H5xx/H563R(G-I)T_H573RIT/variant_generic.h b/variants/STM32H5xx/H563R(G-I)T/variant_generic.h similarity index 100% rename from variants/STM32H5xx/H563R(G-I)T_H573RIT/variant_generic.h rename to variants/STM32H5xx/H563R(G-I)T/variant_generic.h diff --git a/variants/STM32H5xx/H563V(G-I)T_H573VIT/CMakeLists.txt b/variants/STM32H5xx/H563R(G-I)V/CMakeLists.txt similarity index 100% rename from variants/STM32H5xx/H563V(G-I)T_H573VIT/CMakeLists.txt rename to variants/STM32H5xx/H563R(G-I)V/CMakeLists.txt diff --git a/variants/STM32H5xx/H563R(G-I)V/PeripheralPins.c b/variants/STM32H5xx/H563R(G-I)V/PeripheralPins.c new file mode 100644 index 0000000000..e6f0f32818 --- /dev/null +++ b/variants/STM32H5xx/H563R(G-I)V/PeripheralPins.c @@ -0,0 +1,610 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32H563RGVx.xml, STM32H563RIVx.xml + * CubeMX DB release 6.0.90 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_7, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_15_ALT1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PC_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {NC, NP, 0} +}; +#endif + +//*** ETHERNET *** + +#ifdef HAL_ETH_MODULE_ENABLED +WEAK const PinMap PinMap_Ethernet[] = { + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER + {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {NC, NP, 0} +}; +#endif + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PD_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PD_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA5[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CDIR[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CDIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H563R(G-I)V_H573RIV/PinNamesVar.h b/variants/STM32H5xx/H563R(G-I)V/PinNamesVar.h similarity index 100% rename from variants/STM32H5xx/H563R(G-I)V_H573RIV/PinNamesVar.h rename to variants/STM32H5xx/H563R(G-I)V/PinNamesVar.h diff --git a/variants/STM32H5xx/H563R(G-I)V_H573RIV/boards_entry.txt b/variants/STM32H5xx/H563R(G-I)V/boards_entry.txt similarity index 70% rename from variants/STM32H5xx/H563R(G-I)V_H573RIV/boards_entry.txt rename to variants/STM32H5xx/H563R(G-I)V/boards_entry.txt index bc69ec98dd..11cbf3b8d3 100644 --- a/variants/STM32H5xx/H563R(G-I)V_H573RIV/boards_entry.txt +++ b/variants/STM32H5xx/H563R(G-I)V/boards_entry.txt @@ -9,7 +9,7 @@ GenH5.menu.pnum.GENERIC_H563RGVX.upload.maximum_size=1048576 GenH5.menu.pnum.GENERIC_H563RGVX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563RGVX.build.board=GENERIC_H563RGVX GenH5.menu.pnum.GENERIC_H563RGVX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563RGVX.build.variant=STM32H5xx/H563R(G-I)V_H573RIV +GenH5.menu.pnum.GENERIC_H563RGVX.build.variant=STM32H5xx/H563R(G-I)V # Generic H563RIVx GenH5.menu.pnum.GENERIC_H563RIVX=Generic H563RIVx @@ -17,13 +17,5 @@ GenH5.menu.pnum.GENERIC_H563RIVX.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563RIVX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563RIVX.build.board=GENERIC_H563RIVX GenH5.menu.pnum.GENERIC_H563RIVX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563RIVX.build.variant=STM32H5xx/H563R(G-I)V_H573RIV - -# Generic H573RIVx -GenH5.menu.pnum.GENERIC_H573RIVX=Generic H573RIVx -GenH5.menu.pnum.GENERIC_H573RIVX.upload.maximum_size=2097152 -GenH5.menu.pnum.GENERIC_H573RIVX.upload.maximum_data_size=655360 -GenH5.menu.pnum.GENERIC_H573RIVX.build.board=GENERIC_H573RIVX -GenH5.menu.pnum.GENERIC_H573RIVX.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573RIVX.build.variant=STM32H5xx/H563R(G-I)V_H573RIV +GenH5.menu.pnum.GENERIC_H563RIVX.build.variant=STM32H5xx/H563R(G-I)V diff --git a/variants/STM32H5xx/H563R(G-I)V_H573RIV/generic_clock.c b/variants/STM32H5xx/H563R(G-I)V/generic_clock.c similarity index 94% rename from variants/STM32H5xx/H563R(G-I)V_H573RIV/generic_clock.c rename to variants/STM32H5xx/H563R(G-I)V/generic_clock.c index 7af96324c1..cf925e7f1a 100644 --- a/variants/STM32H5xx/H563R(G-I)V_H573RIV/generic_clock.c +++ b/variants/STM32H5xx/H563R(G-I)V/generic_clock.c @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563RGVX) || defined(ARDUINO_GENERIC_H563RIVX) ||\ - defined(ARDUINO_GENERIC_H573RIVX) +#if defined(ARDUINO_GENERIC_H563RGVX) || defined(ARDUINO_GENERIC_H563RIVX) #include "pins_arduino.h" /** diff --git a/variants/STM32H5xx/H563R(G-I)V_H573RIV/variant_generic.cpp b/variants/STM32H5xx/H563R(G-I)V/variant_generic.cpp similarity index 97% rename from variants/STM32H5xx/H563R(G-I)V_H573RIV/variant_generic.cpp rename to variants/STM32H5xx/H563R(G-I)V/variant_generic.cpp index 77c0f3dfc5..29051985d9 100644 --- a/variants/STM32H5xx/H563R(G-I)V_H573RIV/variant_generic.cpp +++ b/variants/STM32H5xx/H563R(G-I)V/variant_generic.cpp @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563RGVX) || defined(ARDUINO_GENERIC_H563RIVX) ||\ - defined(ARDUINO_GENERIC_H573RIVX) +#if defined(ARDUINO_GENERIC_H563RGVX) || defined(ARDUINO_GENERIC_H563RIVX) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32H5xx/H563R(G-I)V_H573RIV/variant_generic.h b/variants/STM32H5xx/H563R(G-I)V/variant_generic.h similarity index 100% rename from variants/STM32H5xx/H563R(G-I)V_H573RIV/variant_generic.h rename to variants/STM32H5xx/H563R(G-I)V/variant_generic.h diff --git a/variants/STM32H5xx/H563V(G-I)T/CMakeLists.txt b/variants/STM32H5xx/H563V(G-I)T/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H563V(G-I)T/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H563V(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H563V(G-I)T/PeripheralPins.c new file mode 100644 index 0000000000..b567ba3517 --- /dev/null +++ b/variants/STM32H5xx/H563V(G-I)T/PeripheralPins.c @@ -0,0 +1,681 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32H563VGTx.xml, STM32H563VITx.xml + * CubeMX DB release 6.0.90 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_15, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_2, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_3, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, + {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PE_10, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_7, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_14, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_0, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_2, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, + {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PE_9, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PC_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_13, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PD_15, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_7, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_15_ALT1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_14, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_8, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PC_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_9, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** ETHERNET *** + +#ifdef HAL_ETH_MODULE_ENABLED +WEAK const PinMap PinMap_Ethernet[] = { + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {NC, NP, 0} +}; +#endif + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PD_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PD_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {PE_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 + {PD_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PE_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 + {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PE_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 + {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PE_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA5[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CDIR[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CDIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H563V(G-I)T_H573VIT/PinNamesVar.h b/variants/STM32H5xx/H563V(G-I)T/PinNamesVar.h similarity index 100% rename from variants/STM32H5xx/H563V(G-I)T_H573VIT/PinNamesVar.h rename to variants/STM32H5xx/H563V(G-I)T/PinNamesVar.h diff --git a/variants/STM32H5xx/H563V(G-I)T_H573VIT/boards_entry.txt b/variants/STM32H5xx/H563V(G-I)T/boards_entry.txt similarity index 70% rename from variants/STM32H5xx/H563V(G-I)T_H573VIT/boards_entry.txt rename to variants/STM32H5xx/H563V(G-I)T/boards_entry.txt index c5410e37ae..9675a61afd 100644 --- a/variants/STM32H5xx/H563V(G-I)T_H573VIT/boards_entry.txt +++ b/variants/STM32H5xx/H563V(G-I)T/boards_entry.txt @@ -9,7 +9,7 @@ GenH5.menu.pnum.GENERIC_H563VGTX.upload.maximum_size=1048576 GenH5.menu.pnum.GENERIC_H563VGTX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563VGTX.build.board=GENERIC_H563VGTX GenH5.menu.pnum.GENERIC_H563VGTX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563VGTX.build.variant=STM32H5xx/H563V(G-I)T_H573VIT +GenH5.menu.pnum.GENERIC_H563VGTX.build.variant=STM32H5xx/H563V(G-I)T # Generic H563VITx GenH5.menu.pnum.GENERIC_H563VITX=Generic H563VITx @@ -17,13 +17,5 @@ GenH5.menu.pnum.GENERIC_H563VITX.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563VITX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563VITX.build.board=GENERIC_H563VITX GenH5.menu.pnum.GENERIC_H563VITX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563VITX.build.variant=STM32H5xx/H563V(G-I)T_H573VIT - -# Generic H573VITx -GenH5.menu.pnum.GENERIC_H573VITX=Generic H573VITx -GenH5.menu.pnum.GENERIC_H573VITX.upload.maximum_size=2097152 -GenH5.menu.pnum.GENERIC_H573VITX.upload.maximum_data_size=655360 -GenH5.menu.pnum.GENERIC_H573VITX.build.board=GENERIC_H573VITX -GenH5.menu.pnum.GENERIC_H573VITX.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573VITX.build.variant=STM32H5xx/H563V(G-I)T_H573VIT +GenH5.menu.pnum.GENERIC_H563VITX.build.variant=STM32H5xx/H563V(G-I)T diff --git a/variants/STM32H5xx/H563V(G-I)T_H573VIT/generic_clock.c b/variants/STM32H5xx/H563V(G-I)T/generic_clock.c similarity index 94% rename from variants/STM32H5xx/H563V(G-I)T_H573VIT/generic_clock.c rename to variants/STM32H5xx/H563V(G-I)T/generic_clock.c index bb368dae15..3e9b12c850 100644 --- a/variants/STM32H5xx/H563V(G-I)T_H573VIT/generic_clock.c +++ b/variants/STM32H5xx/H563V(G-I)T/generic_clock.c @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563VGTX) || defined(ARDUINO_GENERIC_H563VITX) ||\ - defined(ARDUINO_GENERIC_H573VITX) +#if defined(ARDUINO_GENERIC_H563VGTX) || defined(ARDUINO_GENERIC_H563VITX) #include "pins_arduino.h" /** diff --git a/variants/STM32H5xx/H563V(G-I)T_H573VIT/variant_generic.cpp b/variants/STM32H5xx/H563V(G-I)T/variant_generic.cpp similarity index 97% rename from variants/STM32H5xx/H563V(G-I)T_H573VIT/variant_generic.cpp rename to variants/STM32H5xx/H563V(G-I)T/variant_generic.cpp index 87bd517067..eacd6f1846 100644 --- a/variants/STM32H5xx/H563V(G-I)T_H573VIT/variant_generic.cpp +++ b/variants/STM32H5xx/H563V(G-I)T/variant_generic.cpp @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563VGTX) || defined(ARDUINO_GENERIC_H563VITX) ||\ - defined(ARDUINO_GENERIC_H573VITX) +#if defined(ARDUINO_GENERIC_H563VGTX) || defined(ARDUINO_GENERIC_H563VITX) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32H5xx/H563V(G-I)T_H573VIT/variant_generic.h b/variants/STM32H5xx/H563V(G-I)T/variant_generic.h similarity index 100% rename from variants/STM32H5xx/H563V(G-I)T_H573VIT/variant_generic.h rename to variants/STM32H5xx/H563V(G-I)T/variant_generic.h diff --git a/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c b/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c index 84a53e1b71..07669a16c0 100644 --- a/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563VITxQ.xml, STM32H573VITxQ.xml - * CubeMX DB release 6.0.80 + * CubeMX DB release 6.0.90 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -529,11 +529,11 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { //*** USB *** #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB_DRD_FS[] = { - {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/CMakeLists.txt b/variants/STM32H5xx/H563Z(G-I)T/CMakeLists.txt similarity index 100% rename from variants/STM32H5xx/H563Z(G-I)T_H573ZIT/CMakeLists.txt rename to variants/STM32H5xx/H563Z(G-I)T/CMakeLists.txt diff --git a/variants/STM32H5xx/H563Z(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H563Z(G-I)T/PeripheralPins.c new file mode 100644 index 0000000000..188db7d196 --- /dev/null +++ b/variants/STM32H5xx/H563Z(G-I)T/PeripheralPins.c @@ -0,0 +1,772 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32H563ZGTx.xml, STM32H563ZITx.xml + * CubeMX DB release 6.0.90 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 + {PF_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 + {PF_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 + {PF_13, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 + {PF_14, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_15, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PG_6, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_5, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PG_7, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PF_15, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PG_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PF_5, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PG_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N + {PF_6, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PF_7, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PF_8, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PF_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PF_9, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PF_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_15, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_2, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_3, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, + {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PE_10, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_3, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PF_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_1, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PG_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PG_12, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {PG_14, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_7, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_14, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_0, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_2, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, + {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PE_9, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_4, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PF_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_6, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PG_2, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PG_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_11, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PC_5, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_13, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PD_15, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_7, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_11, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PG_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_14, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_3, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_15_ALT1, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_0, UART9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_14, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_8, UART12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_5, USART11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PF_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_13, USART10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {PG_13_ALT1, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_7_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PF_11, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + {PG_14, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_6_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_5_ALT1, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_3_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PC_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_13, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_4_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15_ALT2, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_8, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PG_10, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_9, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** ETHERNET *** + +#ifdef HAL_ETH_MODULE_ENABLED +WEAK const PinMap PinMap_Ethernet[] = { + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {NC, NP, 0} +}; +#endif + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PD_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PF_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PD_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PF_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {PE_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {PF_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 + {PD_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PF_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PE_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 + {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PE_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 + {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PE_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PG_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PG_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PF_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_NCS + {PG_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PA_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CMD + {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SDMMC2)}, // SDMMC2_CK + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {PD_6, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PB_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D0 + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PG_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D1 + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {PG_10, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D2 + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {PG_11, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_SDMMC2)}, // SDMMC2_D3 + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {PG_12, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA5[] = { + {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 + {PC_6_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6 + {PG_13, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {PC_7_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7 + {PG_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {PB_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN + {PB_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CDIR[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CDIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PinNamesVar.h b/variants/STM32H5xx/H563Z(G-I)T/PinNamesVar.h similarity index 100% rename from variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PinNamesVar.h rename to variants/STM32H5xx/H563Z(G-I)T/PinNamesVar.h diff --git a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/boards_entry.txt b/variants/STM32H5xx/H563Z(G-I)T/boards_entry.txt similarity index 70% rename from variants/STM32H5xx/H563Z(G-I)T_H573ZIT/boards_entry.txt rename to variants/STM32H5xx/H563Z(G-I)T/boards_entry.txt index d6797dc89a..7229d74d12 100644 --- a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/boards_entry.txt +++ b/variants/STM32H5xx/H563Z(G-I)T/boards_entry.txt @@ -9,7 +9,7 @@ GenH5.menu.pnum.GENERIC_H563ZGTX.upload.maximum_size=1048576 GenH5.menu.pnum.GENERIC_H563ZGTX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563ZGTX.build.board=GENERIC_H563ZGTX GenH5.menu.pnum.GENERIC_H563ZGTX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563ZGTX.build.variant=STM32H5xx/H563Z(G-I)T_H573ZIT +GenH5.menu.pnum.GENERIC_H563ZGTX.build.variant=STM32H5xx/H563Z(G-I)T # Generic H563ZITx GenH5.menu.pnum.GENERIC_H563ZITX=Generic H563ZITx @@ -17,13 +17,5 @@ GenH5.menu.pnum.GENERIC_H563ZITX.upload.maximum_size=2097152 GenH5.menu.pnum.GENERIC_H563ZITX.upload.maximum_data_size=655360 GenH5.menu.pnum.GENERIC_H563ZITX.build.board=GENERIC_H563ZITX GenH5.menu.pnum.GENERIC_H563ZITX.build.product_line=STM32H563xx -GenH5.menu.pnum.GENERIC_H563ZITX.build.variant=STM32H5xx/H563Z(G-I)T_H573ZIT - -# Generic H573ZITx -GenH5.menu.pnum.GENERIC_H573ZITX=Generic H573ZITx -GenH5.menu.pnum.GENERIC_H573ZITX.upload.maximum_size=2097152 -GenH5.menu.pnum.GENERIC_H573ZITX.upload.maximum_data_size=655360 -GenH5.menu.pnum.GENERIC_H573ZITX.build.board=GENERIC_H573ZITX -GenH5.menu.pnum.GENERIC_H573ZITX.build.product_line=STM32H573xx -GenH5.menu.pnum.GENERIC_H573ZITX.build.variant=STM32H5xx/H563Z(G-I)T_H573ZIT +GenH5.menu.pnum.GENERIC_H563ZITX.build.variant=STM32H5xx/H563Z(G-I)T diff --git a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/generic_clock.c b/variants/STM32H5xx/H563Z(G-I)T/generic_clock.c similarity index 98% rename from variants/STM32H5xx/H563Z(G-I)T_H573ZIT/generic_clock.c rename to variants/STM32H5xx/H563Z(G-I)T/generic_clock.c index 884d196ddf..98da0c36cb 100644 --- a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/generic_clock.c +++ b/variants/STM32H5xx/H563Z(G-I)T/generic_clock.c @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563ZGTX) || defined(ARDUINO_GENERIC_H563ZITX) ||\ - defined(ARDUINO_GENERIC_H573ZITX) +#if defined(ARDUINO_GENERIC_H563ZGTX) || defined(ARDUINO_GENERIC_H563ZITX) #include "pins_arduino.h" /** diff --git a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/ldscript.ld b/variants/STM32H5xx/H563Z(G-I)T/ldscript.ld similarity index 100% rename from variants/STM32H5xx/H563Z(G-I)T_H573ZIT/ldscript.ld rename to variants/STM32H5xx/H563Z(G-I)T/ldscript.ld diff --git a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.cpp b/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp similarity index 100% rename from variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.cpp rename to variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp diff --git a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.h b/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.h similarity index 100% rename from variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.h rename to variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.h diff --git a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_generic.cpp b/variants/STM32H5xx/H563Z(G-I)T/variant_generic.cpp similarity index 98% rename from variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_generic.cpp rename to variants/STM32H5xx/H563Z(G-I)T/variant_generic.cpp index 01933f196d..3eeee9322f 100644 --- a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_generic.cpp +++ b/variants/STM32H5xx/H563Z(G-I)T/variant_generic.cpp @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H563ZGTX) || defined(ARDUINO_GENERIC_H563ZITX) ||\ - defined(ARDUINO_GENERIC_H573ZITX) +#if defined(ARDUINO_GENERIC_H563ZGTX) || defined(ARDUINO_GENERIC_H563ZITX) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_generic.h b/variants/STM32H5xx/H563Z(G-I)T/variant_generic.h similarity index 100% rename from variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_generic.h rename to variants/STM32H5xx/H563Z(G-I)T/variant_generic.h diff --git a/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c b/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c index ada2b93dd8..b82cdc3e5b 100644 --- a/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563ZITxQ.xml, STM32H573ZITxQ.xml - * CubeMX DB release 6.0.80 + * CubeMX DB release 6.0.90 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -593,11 +593,11 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { //*** USB *** #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB_DRD_FS[] = { - {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H573AII/CMakeLists.txt b/variants/STM32H5xx/H573AII/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H573AII/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H563A(G-I)I_H573AII/PeripheralPins.c b/variants/STM32H5xx/H573AII/PeripheralPins.c similarity index 99% rename from variants/STM32H5xx/H563A(G-I)I_H573AII/PeripheralPins.c rename to variants/STM32H5xx/H573AII/PeripheralPins.c index 9b46b0539d..b0383fc271 100644 --- a/variants/STM32H5xx/H563A(G-I)I_H573AII/PeripheralPins.c +++ b/variants/STM32H5xx/H573AII/PeripheralPins.c @@ -11,9 +11,8 @@ ******************************************************************************* */ /* - * Automatically generated from STM32H563AGIx.xml, STM32H563AIIx.xml - * STM32H573AIIx.xml - * CubeMX DB release 6.0.80 + * Automatically generated from STM32H573AIIx.xml + * CubeMX DB release 6.0.90 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -695,11 +694,11 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { //*** USB *** #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB_DRD_FS[] = { - {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H573AII/PinNamesVar.h b/variants/STM32H5xx/H573AII/PinNamesVar.h new file mode 100644 index 0000000000..f6532dee66 --- /dev/null +++ b/variants/STM32H5xx/H573AII/PinNamesVar.h @@ -0,0 +1,98 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_4_ALT2 = PB_4 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_5_ALT2 = PB_5 | ALT2, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PF_8_ALT1 = PF_8 | ALT1, +PF_9_ALT1 = PF_9 | ALT1, +PG_13_ALT1 = PG_13 | ALT1, +PH_6_ALT1 = PH_6 | ALT1, +PH_6_ALT2 = PH_6 | ALT2, +PH_7_ALT1 = PH_7 | ALT1, +PH_8_ALT1 = PH_8 | ALT1, +PH_10_ALT1 = PH_10 | ALT1, +PH_10_ALT2 = PH_10 | ALT2, +PH_11_ALT1 = PH_11 | ALT1, +PH_11_ALT2 = PH_11 | ALT2, +PH_12_ALT1 = PH_12 | ALT1, +PH_13_ALT1 = PH_13 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PI_8, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = PD_3, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32H5xx/H573AII/boards_entry.txt b/variants/STM32H5xx/H573AII/boards_entry.txt new file mode 100644 index 0000000000..a3cc636d79 --- /dev/null +++ b/variants/STM32H5xx/H573AII/boards_entry.txt @@ -0,0 +1,13 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic H573AIIx +GenH5.menu.pnum.GENERIC_H573AIIX=Generic H573AIIx +GenH5.menu.pnum.GENERIC_H573AIIX.upload.maximum_size=2097152 +GenH5.menu.pnum.GENERIC_H573AIIX.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H573AIIX.build.board=GENERIC_H573AIIX +GenH5.menu.pnum.GENERIC_H573AIIX.build.product_line=STM32H573xx +GenH5.menu.pnum.GENERIC_H573AIIX.build.variant=STM32H5xx/H573AII + diff --git a/variants/STM32H5xx/H573AII/generic_clock.c b/variants/STM32H5xx/H573AII/generic_clock.c new file mode 100644 index 0000000000..5f8d6405cc --- /dev/null +++ b/variants/STM32H5xx/H573AII/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H573AIIX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573AII/variant_generic.cpp b/variants/STM32H5xx/H573AII/variant_generic.cpp new file mode 100644 index 0000000000..e257da6d6f --- /dev/null +++ b/variants/STM32H5xx/H573AII/variant_generic.cpp @@ -0,0 +1,180 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H573AIIX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_11, // D27 + PB_12, // D28 + PB_13, // D29 + PB_14, // D30 + PB_15, // D31 + PC_0, // D32/A10 + PC_1, // D33/A11 + PC_2, // D34/A12 + PC_3, // D35/A13 + PC_4, // D36/A14 + PC_5, // D37/A15 + PC_6, // D38 + PC_7, // D39 + PC_8, // D40 + PC_9, // D41 + PC_10, // D42 + PC_11, // D43 + PC_12, // D44 + PC_13, // D45 + PC_14, // D46 + PC_15, // D47 + PD_0, // D48 + PD_1, // D49 + PD_2, // D50 + PD_3, // D51 + PD_4, // D52 + PD_5, // D53 + PD_6, // D54 + PD_7, // D55 + PD_8, // D56 + PD_9, // D57 + PD_10, // D58 + PD_11, // D59 + PD_12, // D60 + PD_13, // D61 + PD_14, // D62 + PD_15, // D63 + PE_0, // D64 + PE_1, // D65 + PE_2, // D66 + PE_3, // D67 + PE_4, // D68 + PE_5, // D69 + PE_6, // D70 + PE_7, // D71 + PE_8, // D72 + PE_9, // D73 + PE_10, // D74 + PE_11, // D75 + PE_12, // D76 + PE_13, // D77 + PE_14, // D78 + PE_15, // D79 + PF_0, // D80 + PF_1, // D81 + PF_2, // D82 + PF_3, // D83 + PF_4, // D84 + PF_5, // D85 + PF_6, // D86 + PF_7, // D87 + PF_8, // D88 + PF_9, // D89 + PF_10, // D90 + PF_11, // D91/A16 + PF_12, // D92/A17 + PF_13, // D93/A18 + PF_14, // D94/A19 + PF_15, // D95 + PG_0, // D96 + PG_1, // D97 + PG_2, // D98 + PG_3, // D99 + PG_4, // D100 + PG_5, // D101 + PG_6, // D102 + PG_7, // D103 + PG_8, // D104 + PG_9, // D105 + PG_10, // D106 + PG_11, // D107 + PG_12, // D108 + PG_13, // D109 + PG_14, // D110 + PG_15, // D111 + PH_0, // D112 + PH_1, // D113 + PH_2, // D114 + PH_3, // D115 + PH_4, // D116 + PH_5, // D117 + PH_6, // D118 + PH_7, // D119 + PH_8, // D120 + PH_10, // D121 + PH_11, // D122 + PH_12, // D123 + PH_13, // D124 + PH_14, // D125 + PH_15, // D126 + PI_0, // D127 + PI_1, // D128 + PI_2, // D129 + PI_3, // D130 + PI_4, // D131 + PI_6, // D132 + PI_7, // D133 + PI_8, // D134 + PI_11 // D135 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 32, // A10, PC0 + 33, // A11, PC1 + 34, // A12, PC2 + 35, // A13, PC3 + 36, // A14, PC4 + 37, // A15, PC5 + 91, // A16, PF11 + 92, // A17, PF12 + 93, // A18, PF13 + 94 // A19, PF14 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573AII/variant_generic.h b/variants/STM32H5xx/H573AII/variant_generic.h new file mode 100644 index 0000000000..01e8b7bcbf --- /dev/null +++ b/variants/STM32H5xx/H573AII/variant_generic.h @@ -0,0 +1,328 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 27 +#define PB12 28 +#define PB13 29 +#define PB14 30 +#define PB15 31 +#define PC0 PIN_A10 +#define PC1 PIN_A11 +#define PC2 PIN_A12 +#define PC3 PIN_A13 +#define PC4 PIN_A14 +#define PC5 PIN_A15 +#define PC6 38 +#define PC7 39 +#define PC8 40 +#define PC9 41 +#define PC10 42 +#define PC11 43 +#define PC12 44 +#define PC13 45 +#define PC14 46 +#define PC15 47 +#define PD0 48 +#define PD1 49 +#define PD2 50 +#define PD3 51 +#define PD4 52 +#define PD5 53 +#define PD6 54 +#define PD7 55 +#define PD8 56 +#define PD9 57 +#define PD10 58 +#define PD11 59 +#define PD12 60 +#define PD13 61 +#define PD14 62 +#define PD15 63 +#define PE0 64 +#define PE1 65 +#define PE2 66 +#define PE3 67 +#define PE4 68 +#define PE5 69 +#define PE6 70 +#define PE7 71 +#define PE8 72 +#define PE9 73 +#define PE10 74 +#define PE11 75 +#define PE12 76 +#define PE13 77 +#define PE14 78 +#define PE15 79 +#define PF0 80 +#define PF1 81 +#define PF2 82 +#define PF3 83 +#define PF4 84 +#define PF5 85 +#define PF6 86 +#define PF7 87 +#define PF8 88 +#define PF9 89 +#define PF10 90 +#define PF11 PIN_A16 +#define PF12 PIN_A17 +#define PF13 PIN_A18 +#define PF14 PIN_A19 +#define PF15 95 +#define PG0 96 +#define PG1 97 +#define PG2 98 +#define PG3 99 +#define PG4 100 +#define PG5 101 +#define PG6 102 +#define PG7 103 +#define PG8 104 +#define PG9 105 +#define PG10 106 +#define PG11 107 +#define PG12 108 +#define PG13 109 +#define PG14 110 +#define PG15 111 +#define PH0 112 +#define PH1 113 +#define PH2 114 +#define PH3 115 +#define PH4 116 +#define PH5 117 +#define PH6 118 +#define PH7 119 +#define PH8 120 +#define PH10 121 +#define PH11 122 +#define PH12 123 +#define PH13 124 +#define PH14 125 +#define PH15 126 +#define PI0 127 +#define PI1 128 +#define PI2 129 +#define PI3 130 +#define PI4 131 +#define PI6 132 +#define PI7 133 +#define PI8 134 +#define PI11 135 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB4_ALT2 (PB4 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB5_ALT2 (PB5 | ALT2) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PF8_ALT1 (PF8 | ALT1) +#define PF9_ALT1 (PF9 | ALT1) +#define PG13_ALT1 (PG13 | ALT1) +#define PH6_ALT1 (PH6 | ALT1) +#define PH6_ALT2 (PH6 | ALT2) +#define PH7_ALT1 (PH7 | ALT1) +#define PH8_ALT1 (PH8 | ALT1) +#define PH10_ALT1 (PH10 | ALT1) +#define PH10_ALT2 (PH10 | ALT2) +#define PH11_ALT1 (PH11 | ALT1) +#define PH11_ALT2 (PH11 | ALT2) +#define PH12_ALT1 (PH12 | ALT1) +#define PH13_ALT1 (PH13 | ALT1) + +#define NUM_DIGITAL_PINS 136 +#define NUM_ANALOG_INPUTS 20 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PG10 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB10 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_ETH_MODULE_DISABLED) + #define HAL_ETH_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32H5xx/H573AIIxQ/CMakeLists.txt b/variants/STM32H5xx/H573AIIxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H573AIIxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PeripheralPins.c b/variants/STM32H5xx/H573AIIxQ/PeripheralPins.c similarity index 99% rename from variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PeripheralPins.c rename to variants/STM32H5xx/H573AIIxQ/PeripheralPins.c index 74dbe01d7c..0dcf374ca1 100644 --- a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H573AIIxQ/PeripheralPins.c @@ -11,8 +11,8 @@ ******************************************************************************* */ /* - * Automatically generated from STM32H563AIIxQ.xml, STM32H573AIIxQ.xml - * CubeMX DB release 6.0.80 + * Automatically generated from STM32H573AIIxQ.xml + * CubeMX DB release 6.0.90 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -686,11 +686,11 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { //*** USB *** #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB_DRD_FS[] = { - {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H573AIIxQ/PinNamesVar.h b/variants/STM32H5xx/H573AIIxQ/PinNamesVar.h new file mode 100644 index 0000000000..912e35d030 --- /dev/null +++ b/variants/STM32H5xx/H573AIIxQ/PinNamesVar.h @@ -0,0 +1,99 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_4_ALT2 = PB_4 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_5_ALT2 = PB_5 | ALT2, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PF_8_ALT1 = PF_8 | ALT1, +PF_9_ALT1 = PF_9 | ALT1, +PH_6_ALT1 = PH_6 | ALT1, +PH_6_ALT2 = PH_6 | ALT2, +PH_7_ALT1 = PH_7 | ALT1, +PH_8_ALT1 = PH_8 | ALT1, +PH_9_ALT1 = PH_9 | ALT1, +PH_9_ALT2 = PH_9 | ALT2, +PH_10_ALT1 = PH_10 | ALT1, +PH_10_ALT2 = PH_10 | ALT2, +PH_11_ALT1 = PH_11 | ALT1, +PH_11_ALT2 = PH_11 | ALT2, +PH_12_ALT1 = PH_12 | ALT1, +PH_13_ALT1 = PH_13 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PI_8, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = PD_3, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32H5xx/H573AIIxQ/boards_entry.txt b/variants/STM32H5xx/H573AIIxQ/boards_entry.txt new file mode 100644 index 0000000000..37e8fc73cc --- /dev/null +++ b/variants/STM32H5xx/H573AIIxQ/boards_entry.txt @@ -0,0 +1,13 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic H573AIIxQ +GenH5.menu.pnum.GENERIC_H573AIIXQ=Generic H573AIIxQ +GenH5.menu.pnum.GENERIC_H573AIIXQ.upload.maximum_size=2097152 +GenH5.menu.pnum.GENERIC_H573AIIXQ.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H573AIIXQ.build.board=GENERIC_H573AIIXQ +GenH5.menu.pnum.GENERIC_H573AIIXQ.build.product_line=STM32H573xx +GenH5.menu.pnum.GENERIC_H573AIIXQ.build.variant=STM32H5xx/H573AIIxQ + diff --git a/variants/STM32H5xx/H573AIIxQ/generic_clock.c b/variants/STM32H5xx/H573AIIxQ/generic_clock.c new file mode 100644 index 0000000000..fd1d9d9049 --- /dev/null +++ b/variants/STM32H5xx/H573AIIxQ/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H573AIIXQ) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573AIIxQ/variant_generic.cpp b/variants/STM32H5xx/H573AIIxQ/variant_generic.cpp new file mode 100644 index 0000000000..ff8922f953 --- /dev/null +++ b/variants/STM32H5xx/H573AIIxQ/variant_generic.cpp @@ -0,0 +1,178 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H573AIIXQ) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_11, // D27 + PB_12, // D28 + PB_13, // D29 + PB_14, // D30 + PB_15, // D31 + PC_0, // D32/A10 + PC_1, // D33/A11 + PC_2, // D34/A12 + PC_3, // D35/A13 + PC_4, // D36/A14 + PC_5, // D37/A15 + PC_6, // D38 + PC_7, // D39 + PC_8, // D40 + PC_9, // D41 + PC_10, // D42 + PC_11, // D43 + PC_12, // D44 + PC_13, // D45 + PC_14, // D46 + PC_15, // D47 + PD_0, // D48 + PD_1, // D49 + PD_2, // D50 + PD_3, // D51 + PD_4, // D52 + PD_5, // D53 + PD_6, // D54 + PD_7, // D55 + PD_8, // D56 + PD_9, // D57 + PD_10, // D58 + PD_11, // D59 + PD_12, // D60 + PD_13, // D61 + PD_14, // D62 + PD_15, // D63 + PE_0, // D64 + PE_1, // D65 + PE_2, // D66 + PE_3, // D67 + PE_4, // D68 + PE_5, // D69 + PE_6, // D70 + PE_7, // D71 + PE_8, // D72 + PE_9, // D73 + PE_10, // D74 + PE_11, // D75 + PE_12, // D76 + PE_13, // D77 + PE_14, // D78 + PE_15, // D79 + PF_0, // D80 + PF_1, // D81 + PF_2, // D82 + PF_3, // D83 + PF_4, // D84 + PF_5, // D85 + PF_6, // D86 + PF_7, // D87 + PF_8, // D88 + PF_9, // D89 + PF_10, // D90 + PF_11, // D91/A16 + PF_12, // D92/A17 + PF_13, // D93/A18 + PF_14, // D94/A19 + PF_15, // D95 + PG_0, // D96 + PG_1, // D97 + PG_2, // D98 + PG_3, // D99 + PG_4, // D100 + PG_5, // D101 + PG_6, // D102 + PG_7, // D103 + PG_8, // D104 + PG_9, // D105 + PG_10, // D106 + PG_12, // D107 + PG_15, // D108 + PH_0, // D109 + PH_1, // D110 + PH_2, // D111 + PH_3, // D112 + PH_4, // D113 + PH_5, // D114 + PH_6, // D115 + PH_7, // D116 + PH_8, // D117 + PH_9, // D118 + PH_10, // D119 + PH_11, // D120 + PH_12, // D121 + PH_13, // D122 + PH_14, // D123 + PH_15, // D124 + PI_0, // D125 + PI_1, // D126 + PI_2, // D127 + PI_3, // D128 + PI_4, // D129 + PI_5, // D130 + PI_6, // D131 + PI_7, // D132 + PI_8 // D133 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 32, // A10, PC0 + 33, // A11, PC1 + 34, // A12, PC2 + 35, // A13, PC3 + 36, // A14, PC4 + 37, // A15, PC5 + 91, // A16, PF11 + 92, // A17, PF12 + 93, // A18, PF13 + 94 // A19, PF14 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573AIIxQ/variant_generic.h b/variants/STM32H5xx/H573AIIxQ/variant_generic.h new file mode 100644 index 0000000000..79e19270e2 --- /dev/null +++ b/variants/STM32H5xx/H573AIIxQ/variant_generic.h @@ -0,0 +1,327 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 27 +#define PB12 28 +#define PB13 29 +#define PB14 30 +#define PB15 31 +#define PC0 PIN_A10 +#define PC1 PIN_A11 +#define PC2 PIN_A12 +#define PC3 PIN_A13 +#define PC4 PIN_A14 +#define PC5 PIN_A15 +#define PC6 38 +#define PC7 39 +#define PC8 40 +#define PC9 41 +#define PC10 42 +#define PC11 43 +#define PC12 44 +#define PC13 45 +#define PC14 46 +#define PC15 47 +#define PD0 48 +#define PD1 49 +#define PD2 50 +#define PD3 51 +#define PD4 52 +#define PD5 53 +#define PD6 54 +#define PD7 55 +#define PD8 56 +#define PD9 57 +#define PD10 58 +#define PD11 59 +#define PD12 60 +#define PD13 61 +#define PD14 62 +#define PD15 63 +#define PE0 64 +#define PE1 65 +#define PE2 66 +#define PE3 67 +#define PE4 68 +#define PE5 69 +#define PE6 70 +#define PE7 71 +#define PE8 72 +#define PE9 73 +#define PE10 74 +#define PE11 75 +#define PE12 76 +#define PE13 77 +#define PE14 78 +#define PE15 79 +#define PF0 80 +#define PF1 81 +#define PF2 82 +#define PF3 83 +#define PF4 84 +#define PF5 85 +#define PF6 86 +#define PF7 87 +#define PF8 88 +#define PF9 89 +#define PF10 90 +#define PF11 PIN_A16 +#define PF12 PIN_A17 +#define PF13 PIN_A18 +#define PF14 PIN_A19 +#define PF15 95 +#define PG0 96 +#define PG1 97 +#define PG2 98 +#define PG3 99 +#define PG4 100 +#define PG5 101 +#define PG6 102 +#define PG7 103 +#define PG8 104 +#define PG9 105 +#define PG10 106 +#define PG12 107 +#define PG15 108 +#define PH0 109 +#define PH1 110 +#define PH2 111 +#define PH3 112 +#define PH4 113 +#define PH5 114 +#define PH6 115 +#define PH7 116 +#define PH8 117 +#define PH9 118 +#define PH10 119 +#define PH11 120 +#define PH12 121 +#define PH13 122 +#define PH14 123 +#define PH15 124 +#define PI0 125 +#define PI1 126 +#define PI2 127 +#define PI3 128 +#define PI4 129 +#define PI5 130 +#define PI6 131 +#define PI7 132 +#define PI8 133 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB4_ALT2 (PB4 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB5_ALT2 (PB5 | ALT2) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PF8_ALT1 (PF8 | ALT1) +#define PF9_ALT1 (PF9 | ALT1) +#define PH6_ALT1 (PH6 | ALT1) +#define PH6_ALT2 (PH6 | ALT2) +#define PH7_ALT1 (PH7 | ALT1) +#define PH8_ALT1 (PH8 | ALT1) +#define PH9_ALT1 (PH9 | ALT1) +#define PH9_ALT2 (PH9 | ALT2) +#define PH10_ALT1 (PH10 | ALT1) +#define PH10_ALT2 (PH10 | ALT2) +#define PH11_ALT1 (PH11 | ALT1) +#define PH11_ALT2 (PH11 | ALT2) +#define PH12_ALT1 (PH12 | ALT1) +#define PH13_ALT1 (PH13 | ALT1) + +#define NUM_DIGITAL_PINS 134 +#define NUM_ANALOG_INPUTS 20 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PG10 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB10 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_ETH_MODULE_DISABLED) + #define HAL_ETH_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32H5xx/H573II(K-T)/CMakeLists.txt b/variants/STM32H5xx/H573II(K-T)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H573II(K-T)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/PeripheralPins.c b/variants/STM32H5xx/H573II(K-T)/PeripheralPins.c similarity index 99% rename from variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/PeripheralPins.c rename to variants/STM32H5xx/H573II(K-T)/PeripheralPins.c index 30eb154187..c58830e04e 100644 --- a/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/PeripheralPins.c +++ b/variants/STM32H5xx/H573II(K-T)/PeripheralPins.c @@ -11,10 +11,8 @@ ******************************************************************************* */ /* - * Automatically generated from STM32H563IGKx.xml, STM32H563IGTx.xml - * STM32H563IIKx.xml, STM32H563IITx.xml - * STM32H573IIKx.xml, STM32H573IITx.xml - * CubeMX DB release 6.0.80 + * Automatically generated from STM32H573IIKx.xml, STM32H573IITx.xml + * CubeMX DB release 6.0.90 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -705,11 +703,11 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { //*** USB *** #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB_DRD_FS[] = { - {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H573II(K-T)/PinNamesVar.h b/variants/STM32H5xx/H573II(K-T)/PinNamesVar.h new file mode 100644 index 0000000000..ddf97db984 --- /dev/null +++ b/variants/STM32H5xx/H573II(K-T)/PinNamesVar.h @@ -0,0 +1,100 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_4_ALT2 = PB_4 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_5_ALT2 = PB_5 | ALT2, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PF_8_ALT1 = PF_8 | ALT1, +PF_9_ALT1 = PF_9 | ALT1, +PG_13_ALT1 = PG_13 | ALT1, +PH_6_ALT1 = PH_6 | ALT1, +PH_6_ALT2 = PH_6 | ALT2, +PH_7_ALT1 = PH_7 | ALT1, +PH_8_ALT1 = PH_8 | ALT1, +PH_9_ALT1 = PH_9 | ALT1, +PH_9_ALT2 = PH_9 | ALT2, +PH_10_ALT1 = PH_10 | ALT1, +PH_10_ALT2 = PH_10 | ALT2, +PH_11_ALT1 = PH_11 | ALT1, +PH_11_ALT2 = PH_11 | ALT2, +PH_12_ALT1 = PH_12 | ALT1, +PH_13_ALT1 = PH_13 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PI_8, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = PD_3, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32H5xx/H573II(K-T)/boards_entry.txt b/variants/STM32H5xx/H573II(K-T)/boards_entry.txt new file mode 100644 index 0000000000..48980a45cc --- /dev/null +++ b/variants/STM32H5xx/H573II(K-T)/boards_entry.txt @@ -0,0 +1,21 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic H573IIKx +GenH5.menu.pnum.GENERIC_H573IIKX=Generic H573IIKx +GenH5.menu.pnum.GENERIC_H573IIKX.upload.maximum_size=2097152 +GenH5.menu.pnum.GENERIC_H573IIKX.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H573IIKX.build.board=GENERIC_H573IIKX +GenH5.menu.pnum.GENERIC_H573IIKX.build.product_line=STM32H573xx +GenH5.menu.pnum.GENERIC_H573IIKX.build.variant=STM32H5xx/H573II(K-T) + +# Generic H573IITx +GenH5.menu.pnum.GENERIC_H573IITX=Generic H573IITx +GenH5.menu.pnum.GENERIC_H573IITX.upload.maximum_size=2097152 +GenH5.menu.pnum.GENERIC_H573IITX.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H573IITX.build.board=GENERIC_H573IITX +GenH5.menu.pnum.GENERIC_H573IITX.build.product_line=STM32H573xx +GenH5.menu.pnum.GENERIC_H573IITX.build.variant=STM32H5xx/H573II(K-T) + diff --git a/variants/STM32H5xx/H573II(K-T)/generic_clock.c b/variants/STM32H5xx/H573II(K-T)/generic_clock.c new file mode 100644 index 0000000000..64ecc3ca7f --- /dev/null +++ b/variants/STM32H5xx/H573II(K-T)/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H573IIKX) || defined(ARDUINO_GENERIC_H573IITX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573II(K-T)/variant_generic.cpp b/variants/STM32H5xx/H573II(K-T)/variant_generic.cpp new file mode 100644 index 0000000000..348ecea665 --- /dev/null +++ b/variants/STM32H5xx/H573II(K-T)/variant_generic.cpp @@ -0,0 +1,184 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H573IIKX) || defined(ARDUINO_GENERIC_H573IITX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_11, // D27 + PB_12, // D28 + PB_13, // D29 + PB_14, // D30 + PB_15, // D31 + PC_0, // D32/A10 + PC_1, // D33/A11 + PC_2, // D34/A12 + PC_3, // D35/A13 + PC_4, // D36/A14 + PC_5, // D37/A15 + PC_6, // D38 + PC_7, // D39 + PC_8, // D40 + PC_9, // D41 + PC_10, // D42 + PC_11, // D43 + PC_12, // D44 + PC_13, // D45 + PC_14, // D46 + PC_15, // D47 + PD_0, // D48 + PD_1, // D49 + PD_2, // D50 + PD_3, // D51 + PD_4, // D52 + PD_5, // D53 + PD_6, // D54 + PD_7, // D55 + PD_8, // D56 + PD_9, // D57 + PD_10, // D58 + PD_11, // D59 + PD_12, // D60 + PD_13, // D61 + PD_14, // D62 + PD_15, // D63 + PE_0, // D64 + PE_1, // D65 + PE_2, // D66 + PE_3, // D67 + PE_4, // D68 + PE_5, // D69 + PE_6, // D70 + PE_7, // D71 + PE_8, // D72 + PE_9, // D73 + PE_10, // D74 + PE_11, // D75 + PE_12, // D76 + PE_13, // D77 + PE_14, // D78 + PE_15, // D79 + PF_0, // D80 + PF_1, // D81 + PF_2, // D82 + PF_3, // D83 + PF_4, // D84 + PF_5, // D85 + PF_6, // D86 + PF_7, // D87 + PF_8, // D88 + PF_9, // D89 + PF_10, // D90 + PF_11, // D91/A16 + PF_12, // D92/A17 + PF_13, // D93/A18 + PF_14, // D94/A19 + PF_15, // D95 + PG_0, // D96 + PG_1, // D97 + PG_2, // D98 + PG_3, // D99 + PG_4, // D100 + PG_5, // D101 + PG_6, // D102 + PG_7, // D103 + PG_8, // D104 + PG_9, // D105 + PG_10, // D106 + PG_11, // D107 + PG_12, // D108 + PG_13, // D109 + PG_14, // D110 + PG_15, // D111 + PH_0, // D112 + PH_1, // D113 + PH_2, // D114 + PH_3, // D115 + PH_4, // D116 + PH_5, // D117 + PH_6, // D118 + PH_7, // D119 + PH_8, // D120 + PH_9, // D121 + PH_10, // D122 + PH_11, // D123 + PH_12, // D124 + PH_13, // D125 + PH_14, // D126 + PH_15, // D127 + PI_0, // D128 + PI_1, // D129 + PI_2, // D130 + PI_3, // D131 + PI_4, // D132 + PI_5, // D133 + PI_6, // D134 + PI_7, // D135 + PI_8, // D136 + PI_9, // D137 + PI_10, // D138 + PI_11 // D139 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 32, // A10, PC0 + 33, // A11, PC1 + 34, // A12, PC2 + 35, // A13, PC3 + 36, // A14, PC4 + 37, // A15, PC5 + 91, // A16, PF11 + 92, // A17, PF12 + 93, // A18, PF13 + 94 // A19, PF14 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573II(K-T)/variant_generic.h b/variants/STM32H5xx/H573II(K-T)/variant_generic.h new file mode 100644 index 0000000000..d8b1e831b5 --- /dev/null +++ b/variants/STM32H5xx/H573II(K-T)/variant_generic.h @@ -0,0 +1,334 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 27 +#define PB12 28 +#define PB13 29 +#define PB14 30 +#define PB15 31 +#define PC0 PIN_A10 +#define PC1 PIN_A11 +#define PC2 PIN_A12 +#define PC3 PIN_A13 +#define PC4 PIN_A14 +#define PC5 PIN_A15 +#define PC6 38 +#define PC7 39 +#define PC8 40 +#define PC9 41 +#define PC10 42 +#define PC11 43 +#define PC12 44 +#define PC13 45 +#define PC14 46 +#define PC15 47 +#define PD0 48 +#define PD1 49 +#define PD2 50 +#define PD3 51 +#define PD4 52 +#define PD5 53 +#define PD6 54 +#define PD7 55 +#define PD8 56 +#define PD9 57 +#define PD10 58 +#define PD11 59 +#define PD12 60 +#define PD13 61 +#define PD14 62 +#define PD15 63 +#define PE0 64 +#define PE1 65 +#define PE2 66 +#define PE3 67 +#define PE4 68 +#define PE5 69 +#define PE6 70 +#define PE7 71 +#define PE8 72 +#define PE9 73 +#define PE10 74 +#define PE11 75 +#define PE12 76 +#define PE13 77 +#define PE14 78 +#define PE15 79 +#define PF0 80 +#define PF1 81 +#define PF2 82 +#define PF3 83 +#define PF4 84 +#define PF5 85 +#define PF6 86 +#define PF7 87 +#define PF8 88 +#define PF9 89 +#define PF10 90 +#define PF11 PIN_A16 +#define PF12 PIN_A17 +#define PF13 PIN_A18 +#define PF14 PIN_A19 +#define PF15 95 +#define PG0 96 +#define PG1 97 +#define PG2 98 +#define PG3 99 +#define PG4 100 +#define PG5 101 +#define PG6 102 +#define PG7 103 +#define PG8 104 +#define PG9 105 +#define PG10 106 +#define PG11 107 +#define PG12 108 +#define PG13 109 +#define PG14 110 +#define PG15 111 +#define PH0 112 +#define PH1 113 +#define PH2 114 +#define PH3 115 +#define PH4 116 +#define PH5 117 +#define PH6 118 +#define PH7 119 +#define PH8 120 +#define PH9 121 +#define PH10 122 +#define PH11 123 +#define PH12 124 +#define PH13 125 +#define PH14 126 +#define PH15 127 +#define PI0 128 +#define PI1 129 +#define PI2 130 +#define PI3 131 +#define PI4 132 +#define PI5 133 +#define PI6 134 +#define PI7 135 +#define PI8 136 +#define PI9 137 +#define PI10 138 +#define PI11 139 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB4_ALT2 (PB4 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB5_ALT2 (PB5 | ALT2) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PF8_ALT1 (PF8 | ALT1) +#define PF9_ALT1 (PF9 | ALT1) +#define PG13_ALT1 (PG13 | ALT1) +#define PH6_ALT1 (PH6 | ALT1) +#define PH6_ALT2 (PH6 | ALT2) +#define PH7_ALT1 (PH7 | ALT1) +#define PH8_ALT1 (PH8 | ALT1) +#define PH9_ALT1 (PH9 | ALT1) +#define PH9_ALT2 (PH9 | ALT2) +#define PH10_ALT1 (PH10 | ALT1) +#define PH10_ALT2 (PH10 | ALT2) +#define PH11_ALT1 (PH11 | ALT1) +#define PH11_ALT2 (PH11 | ALT2) +#define PH12_ALT1 (PH12 | ALT1) +#define PH13_ALT1 (PH13 | ALT1) + +#define NUM_DIGITAL_PINS 140 +#define NUM_ANALOG_INPUTS 20 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PG10 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB10 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_ETH_MODULE_DISABLED) + #define HAL_ETH_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/CMakeLists.txt b/variants/STM32H5xx/H573IIKxQ/CMakeLists.txt similarity index 100% rename from variants/STM32H5xx/H563IIKxQ_H573IIKxQ/CMakeLists.txt rename to variants/STM32H5xx/H573IIKxQ/CMakeLists.txt diff --git a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins.c b/variants/STM32H5xx/H573IIKxQ/PeripheralPins.c similarity index 99% rename from variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins.c rename to variants/STM32H5xx/H573IIKxQ/PeripheralPins.c index 589ee1bb9d..b2b6217ee9 100644 --- a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H573IIKxQ/PeripheralPins.c @@ -11,8 +11,8 @@ ******************************************************************************* */ /* - * Automatically generated from STM32H563IIKxQ.xml, STM32H573IIKxQ.xml - * CubeMX DB release 6.0.80 + * Automatically generated from STM32H573IIKxQ.xml + * CubeMX DB release 6.0.90 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -701,11 +701,11 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { //*** USB *** #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB_DRD_FS[] = { - {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins_STM32H573I_DK.c b/variants/STM32H5xx/H573IIKxQ/PeripheralPins_STM32H573I_DK.c similarity index 99% rename from variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins_STM32H573I_DK.c rename to variants/STM32H5xx/H573IIKxQ/PeripheralPins_STM32H573I_DK.c index a9923dd322..4328e33d63 100644 --- a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins_STM32H573I_DK.c +++ b/variants/STM32H5xx/H573IIKxQ/PeripheralPins_STM32H573I_DK.c @@ -11,8 +11,8 @@ ******************************************************************************* */ /* - * Automatically generated from STM32H563IIKxQ.xml, STM32H573IIKxQ.xml - * CubeMX DB release 6.0.80 + * Automatically generated from STM32H573IIKxQ.xml + * CubeMX DB release 6.0.90 */ #if defined(ARDUINO_STM32H573I_DK) #include "Arduino.h" diff --git a/variants/STM32H5xx/H573IIKxQ/PinNamesVar.h b/variants/STM32H5xx/H573IIKxQ/PinNamesVar.h new file mode 100644 index 0000000000..ddf97db984 --- /dev/null +++ b/variants/STM32H5xx/H573IIKxQ/PinNamesVar.h @@ -0,0 +1,100 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_4_ALT2 = PB_4 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_5_ALT2 = PB_5 | ALT2, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PF_8_ALT1 = PF_8 | ALT1, +PF_9_ALT1 = PF_9 | ALT1, +PG_13_ALT1 = PG_13 | ALT1, +PH_6_ALT1 = PH_6 | ALT1, +PH_6_ALT2 = PH_6 | ALT2, +PH_7_ALT1 = PH_7 | ALT1, +PH_8_ALT1 = PH_8 | ALT1, +PH_9_ALT1 = PH_9 | ALT1, +PH_9_ALT2 = PH_9 | ALT2, +PH_10_ALT1 = PH_10 | ALT1, +PH_10_ALT2 = PH_10 | ALT2, +PH_11_ALT1 = PH_11 | ALT1, +PH_11_ALT2 = PH_11 | ALT2, +PH_12_ALT1 = PH_12 | ALT1, +PH_13_ALT1 = PH_13 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PI_8, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = PD_3, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32H5xx/H573IIKxQ/boards_entry.txt b/variants/STM32H5xx/H573IIKxQ/boards_entry.txt new file mode 100644 index 0000000000..b5e321c3b8 --- /dev/null +++ b/variants/STM32H5xx/H573IIKxQ/boards_entry.txt @@ -0,0 +1,13 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic H573IIKxQ +GenH5.menu.pnum.GENERIC_H573IIKXQ=Generic H573IIKxQ +GenH5.menu.pnum.GENERIC_H573IIKXQ.upload.maximum_size=2097152 +GenH5.menu.pnum.GENERIC_H573IIKXQ.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H573IIKXQ.build.board=GENERIC_H573IIKXQ +GenH5.menu.pnum.GENERIC_H573IIKXQ.build.product_line=STM32H573xx +GenH5.menu.pnum.GENERIC_H573IIKXQ.build.variant=STM32H5xx/H573IIKxQ + diff --git a/variants/STM32H5xx/H573IIKxQ/generic_clock.c b/variants/STM32H5xx/H573IIKxQ/generic_clock.c new file mode 100644 index 0000000000..2f63be49ff --- /dev/null +++ b/variants/STM32H5xx/H573IIKxQ/generic_clock.c @@ -0,0 +1,90 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H573IIKXQ) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI + | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_CSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV2; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.CSIState = RCC_CSI_ON; + RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 125; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 4; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 + | RCC_CLOCKTYPE_PCLK3; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 + | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 + | RCC_PERIPHCLK_USB; + PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; + PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573IIKxQ/ldscript.ld b/variants/STM32H5xx/H573IIKxQ/ldscript.ld new file mode 100644 index 0000000000..7ed43755cb --- /dev/null +++ b/variants/STM32H5xx/H573IIKxQ/ldscript.ld @@ -0,0 +1,185 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32H573IIKxQ Device from STM32H5 series +** 2048Kbytes FLASH +** 640Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE + FLASH (rx) : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_STM32H573I_DK.cpp b/variants/STM32H5xx/H573IIKxQ/variant_STM32H573I_DK.cpp similarity index 100% rename from variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_STM32H573I_DK.cpp rename to variants/STM32H5xx/H573IIKxQ/variant_STM32H573I_DK.cpp diff --git a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_STM32H573I_DK.h b/variants/STM32H5xx/H573IIKxQ/variant_STM32H573I_DK.h similarity index 100% rename from variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_STM32H573I_DK.h rename to variants/STM32H5xx/H573IIKxQ/variant_STM32H573I_DK.h diff --git a/variants/STM32H5xx/H573IIKxQ/variant_generic.cpp b/variants/STM32H5xx/H573IIKxQ/variant_generic.cpp new file mode 100644 index 0000000000..fc373d83ca --- /dev/null +++ b/variants/STM32H5xx/H573IIKxQ/variant_generic.cpp @@ -0,0 +1,183 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H573IIKXQ) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_11, // D27 + PB_12, // D28 + PB_13, // D29 + PB_14, // D30 + PB_15, // D31 + PC_0, // D32/A10 + PC_1, // D33/A11 + PC_2, // D34/A12 + PC_3, // D35/A13 + PC_4, // D36/A14 + PC_5, // D37/A15 + PC_6, // D38 + PC_7, // D39 + PC_8, // D40 + PC_9, // D41 + PC_10, // D42 + PC_11, // D43 + PC_12, // D44 + PC_13, // D45 + PC_14, // D46 + PC_15, // D47 + PD_0, // D48 + PD_1, // D49 + PD_2, // D50 + PD_3, // D51 + PD_4, // D52 + PD_5, // D53 + PD_6, // D54 + PD_7, // D55 + PD_8, // D56 + PD_9, // D57 + PD_10, // D58 + PD_11, // D59 + PD_12, // D60 + PD_13, // D61 + PD_14, // D62 + PD_15, // D63 + PE_0, // D64 + PE_1, // D65 + PE_2, // D66 + PE_3, // D67 + PE_4, // D68 + PE_5, // D69 + PE_6, // D70 + PE_7, // D71 + PE_8, // D72 + PE_9, // D73 + PE_10, // D74 + PE_11, // D75 + PE_12, // D76 + PE_13, // D77 + PE_14, // D78 + PE_15, // D79 + PF_0, // D80 + PF_1, // D81 + PF_2, // D82 + PF_3, // D83 + PF_4, // D84 + PF_5, // D85 + PF_6, // D86 + PF_7, // D87 + PF_8, // D88 + PF_9, // D89 + PF_10, // D90 + PF_11, // D91/A16 + PF_12, // D92/A17 + PF_13, // D93/A18 + PF_14, // D94/A19 + PF_15, // D95 + PG_0, // D96 + PG_1, // D97 + PG_2, // D98 + PG_3, // D99 + PG_4, // D100 + PG_5, // D101 + PG_6, // D102 + PG_7, // D103 + PG_8, // D104 + PG_9, // D105 + PG_10, // D106 + PG_11, // D107 + PG_12, // D108 + PG_13, // D109 + PG_14, // D110 + PG_15, // D111 + PH_0, // D112 + PH_1, // D113 + PH_2, // D114 + PH_3, // D115 + PH_4, // D116 + PH_5, // D117 + PH_6, // D118 + PH_7, // D119 + PH_8, // D120 + PH_9, // D121 + PH_10, // D122 + PH_11, // D123 + PH_12, // D124 + PH_13, // D125 + PH_14, // D126 + PH_15, // D127 + PI_1, // D128 + PI_2, // D129 + PI_3, // D130 + PI_4, // D131 + PI_5, // D132 + PI_6, // D133 + PI_7, // D134 + PI_8, // D135 + PI_9, // D136 + PI_10, // D137 + PI_11 // D138 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 32, // A10, PC0 + 33, // A11, PC1 + 34, // A12, PC2 + 35, // A13, PC3 + 36, // A14, PC4 + 37, // A15, PC5 + 91, // A16, PF11 + 92, // A17, PF12 + 93, // A18, PF13 + 94 // A19, PF14 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573IIKxQ/variant_generic.h b/variants/STM32H5xx/H573IIKxQ/variant_generic.h new file mode 100644 index 0000000000..84d49d2c34 --- /dev/null +++ b/variants/STM32H5xx/H573IIKxQ/variant_generic.h @@ -0,0 +1,333 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 27 +#define PB12 28 +#define PB13 29 +#define PB14 30 +#define PB15 31 +#define PC0 PIN_A10 +#define PC1 PIN_A11 +#define PC2 PIN_A12 +#define PC3 PIN_A13 +#define PC4 PIN_A14 +#define PC5 PIN_A15 +#define PC6 38 +#define PC7 39 +#define PC8 40 +#define PC9 41 +#define PC10 42 +#define PC11 43 +#define PC12 44 +#define PC13 45 +#define PC14 46 +#define PC15 47 +#define PD0 48 +#define PD1 49 +#define PD2 50 +#define PD3 51 +#define PD4 52 +#define PD5 53 +#define PD6 54 +#define PD7 55 +#define PD8 56 +#define PD9 57 +#define PD10 58 +#define PD11 59 +#define PD12 60 +#define PD13 61 +#define PD14 62 +#define PD15 63 +#define PE0 64 +#define PE1 65 +#define PE2 66 +#define PE3 67 +#define PE4 68 +#define PE5 69 +#define PE6 70 +#define PE7 71 +#define PE8 72 +#define PE9 73 +#define PE10 74 +#define PE11 75 +#define PE12 76 +#define PE13 77 +#define PE14 78 +#define PE15 79 +#define PF0 80 +#define PF1 81 +#define PF2 82 +#define PF3 83 +#define PF4 84 +#define PF5 85 +#define PF6 86 +#define PF7 87 +#define PF8 88 +#define PF9 89 +#define PF10 90 +#define PF11 PIN_A16 +#define PF12 PIN_A17 +#define PF13 PIN_A18 +#define PF14 PIN_A19 +#define PF15 95 +#define PG0 96 +#define PG1 97 +#define PG2 98 +#define PG3 99 +#define PG4 100 +#define PG5 101 +#define PG6 102 +#define PG7 103 +#define PG8 104 +#define PG9 105 +#define PG10 106 +#define PG11 107 +#define PG12 108 +#define PG13 109 +#define PG14 110 +#define PG15 111 +#define PH0 112 +#define PH1 113 +#define PH2 114 +#define PH3 115 +#define PH4 116 +#define PH5 117 +#define PH6 118 +#define PH7 119 +#define PH8 120 +#define PH9 121 +#define PH10 122 +#define PH11 123 +#define PH12 124 +#define PH13 125 +#define PH14 126 +#define PH15 127 +#define PI1 128 +#define PI2 129 +#define PI3 130 +#define PI4 131 +#define PI5 132 +#define PI6 133 +#define PI7 134 +#define PI8 135 +#define PI9 136 +#define PI10 137 +#define PI11 138 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB4_ALT2 (PB4 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB5_ALT2 (PB5 | ALT2) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PF8_ALT1 (PF8 | ALT1) +#define PF9_ALT1 (PF9 | ALT1) +#define PG13_ALT1 (PG13 | ALT1) +#define PH6_ALT1 (PH6 | ALT1) +#define PH6_ALT2 (PH6 | ALT2) +#define PH7_ALT1 (PH7 | ALT1) +#define PH8_ALT1 (PH8 | ALT1) +#define PH9_ALT1 (PH9 | ALT1) +#define PH9_ALT2 (PH9 | ALT2) +#define PH10_ALT1 (PH10 | ALT1) +#define PH10_ALT2 (PH10 | ALT2) +#define PH11_ALT1 (PH11 | ALT1) +#define PH11_ALT2 (PH11 | ALT2) +#define PH12_ALT1 (PH12 | ALT1) +#define PH13_ALT1 (PH13 | ALT1) + +#define NUM_DIGITAL_PINS 139 +#define NUM_ANALOG_INPUTS 20 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PG10 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB10 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_ETH_MODULE_DISABLED) + #define HAL_ETH_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32H5xx/H573IITxQ/CMakeLists.txt b/variants/STM32H5xx/H573IITxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H573IITxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H563IITxQ_H573IITxQ/PeripheralPins.c b/variants/STM32H5xx/H573IITxQ/PeripheralPins.c similarity index 99% rename from variants/STM32H5xx/H563IITxQ_H573IITxQ/PeripheralPins.c rename to variants/STM32H5xx/H573IITxQ/PeripheralPins.c index aa9f1ca02e..2146cd5ea4 100644 --- a/variants/STM32H5xx/H563IITxQ_H573IITxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H573IITxQ/PeripheralPins.c @@ -11,8 +11,8 @@ ******************************************************************************* */ /* - * Automatically generated from STM32H563IITxQ.xml, STM32H573IITxQ.xml - * CubeMX DB release 6.0.80 + * Automatically generated from STM32H573IITxQ.xml + * CubeMX DB release 6.0.90 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -695,11 +695,11 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { //*** USB *** #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB_DRD_FS[] = { - {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H573IITxQ/PinNamesVar.h b/variants/STM32H5xx/H573IITxQ/PinNamesVar.h new file mode 100644 index 0000000000..e57cfd85f3 --- /dev/null +++ b/variants/STM32H5xx/H573IITxQ/PinNamesVar.h @@ -0,0 +1,99 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_4_ALT2 = PB_4 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_5_ALT2 = PB_5 | ALT2, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PF_8_ALT1 = PF_8 | ALT1, +PF_9_ALT1 = PF_9 | ALT1, +PG_13_ALT1 = PG_13 | ALT1, +PH_6_ALT1 = PH_6 | ALT1, +PH_6_ALT2 = PH_6 | ALT2, +PH_7_ALT1 = PH_7 | ALT1, +PH_9_ALT1 = PH_9 | ALT1, +PH_9_ALT2 = PH_9 | ALT2, +PH_10_ALT1 = PH_10 | ALT1, +PH_10_ALT2 = PH_10 | ALT2, +PH_11_ALT1 = PH_11 | ALT1, +PH_11_ALT2 = PH_11 | ALT2, +PH_12_ALT1 = PH_12 | ALT1, +PH_13_ALT1 = PH_13 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PI_8, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = PD_3, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32H5xx/H573IITxQ/boards_entry.txt b/variants/STM32H5xx/H573IITxQ/boards_entry.txt new file mode 100644 index 0000000000..e377e73172 --- /dev/null +++ b/variants/STM32H5xx/H573IITxQ/boards_entry.txt @@ -0,0 +1,13 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic H573IITxQ +GenH5.menu.pnum.GENERIC_H573IITXQ=Generic H573IITxQ +GenH5.menu.pnum.GENERIC_H573IITXQ.upload.maximum_size=2097152 +GenH5.menu.pnum.GENERIC_H573IITXQ.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H573IITXQ.build.board=GENERIC_H573IITXQ +GenH5.menu.pnum.GENERIC_H573IITXQ.build.product_line=STM32H573xx +GenH5.menu.pnum.GENERIC_H573IITXQ.build.variant=STM32H5xx/H573IITxQ + diff --git a/variants/STM32H5xx/H573IITxQ/generic_clock.c b/variants/STM32H5xx/H573IITxQ/generic_clock.c new file mode 100644 index 0000000000..e61cf9c1ce --- /dev/null +++ b/variants/STM32H5xx/H573IITxQ/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H573IITXQ) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573IITxQ/variant_generic.cpp b/variants/STM32H5xx/H573IITxQ/variant_generic.cpp new file mode 100644 index 0000000000..2c34bbc623 --- /dev/null +++ b/variants/STM32H5xx/H573IITxQ/variant_generic.cpp @@ -0,0 +1,180 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H573IITXQ) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_11, // D27 + PB_12, // D28 + PB_13, // D29 + PB_14, // D30 + PB_15, // D31 + PC_0, // D32/A10 + PC_1, // D33/A11 + PC_2, // D34/A12 + PC_3, // D35/A13 + PC_4, // D36/A14 + PC_5, // D37/A15 + PC_6, // D38 + PC_7, // D39 + PC_8, // D40 + PC_9, // D41 + PC_10, // D42 + PC_11, // D43 + PC_12, // D44 + PC_13, // D45 + PC_14, // D46 + PC_15, // D47 + PD_0, // D48 + PD_1, // D49 + PD_2, // D50 + PD_3, // D51 + PD_4, // D52 + PD_5, // D53 + PD_6, // D54 + PD_7, // D55 + PD_8, // D56 + PD_9, // D57 + PD_10, // D58 + PD_11, // D59 + PD_12, // D60 + PD_13, // D61 + PD_14, // D62 + PD_15, // D63 + PE_0, // D64 + PE_1, // D65 + PE_2, // D66 + PE_3, // D67 + PE_4, // D68 + PE_5, // D69 + PE_6, // D70 + PE_7, // D71 + PE_8, // D72 + PE_9, // D73 + PE_10, // D74 + PE_11, // D75 + PE_12, // D76 + PE_13, // D77 + PE_14, // D78 + PE_15, // D79 + PF_0, // D80 + PF_1, // D81 + PF_2, // D82 + PF_3, // D83 + PF_4, // D84 + PF_5, // D85 + PF_6, // D86 + PF_7, // D87 + PF_8, // D88 + PF_9, // D89 + PF_11, // D90/A16 + PF_12, // D91/A17 + PF_13, // D92/A18 + PF_14, // D93/A19 + PF_15, // D94 + PG_0, // D95 + PG_1, // D96 + PG_2, // D97 + PG_3, // D98 + PG_4, // D99 + PG_5, // D100 + PG_6, // D101 + PG_7, // D102 + PG_8, // D103 + PG_9, // D104 + PG_10, // D105 + PG_11, // D106 + PG_12, // D107 + PG_13, // D108 + PG_14, // D109 + PG_15, // D110 + PH_0, // D111 + PH_1, // D112 + PH_2, // D113 + PH_3, // D114 + PH_6, // D115 + PH_7, // D116 + PH_9, // D117 + PH_10, // D118 + PH_11, // D119 + PH_12, // D120 + PH_13, // D121 + PH_14, // D122 + PH_15, // D123 + PI_0, // D124 + PI_1, // D125 + PI_2, // D126 + PI_3, // D127 + PI_4, // D128 + PI_5, // D129 + PI_6, // D130 + PI_7, // D131 + PI_8, // D132 + PI_9, // D133 + PI_10, // D134 + PI_11 // D135 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 32, // A10, PC0 + 33, // A11, PC1 + 34, // A12, PC2 + 35, // A13, PC3 + 36, // A14, PC4 + 37, // A15, PC5 + 90, // A16, PF11 + 91, // A17, PF12 + 92, // A18, PF13 + 93 // A19, PF14 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573IITxQ/variant_generic.h b/variants/STM32H5xx/H573IITxQ/variant_generic.h new file mode 100644 index 0000000000..5d9ed6afa9 --- /dev/null +++ b/variants/STM32H5xx/H573IITxQ/variant_generic.h @@ -0,0 +1,329 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 27 +#define PB12 28 +#define PB13 29 +#define PB14 30 +#define PB15 31 +#define PC0 PIN_A10 +#define PC1 PIN_A11 +#define PC2 PIN_A12 +#define PC3 PIN_A13 +#define PC4 PIN_A14 +#define PC5 PIN_A15 +#define PC6 38 +#define PC7 39 +#define PC8 40 +#define PC9 41 +#define PC10 42 +#define PC11 43 +#define PC12 44 +#define PC13 45 +#define PC14 46 +#define PC15 47 +#define PD0 48 +#define PD1 49 +#define PD2 50 +#define PD3 51 +#define PD4 52 +#define PD5 53 +#define PD6 54 +#define PD7 55 +#define PD8 56 +#define PD9 57 +#define PD10 58 +#define PD11 59 +#define PD12 60 +#define PD13 61 +#define PD14 62 +#define PD15 63 +#define PE0 64 +#define PE1 65 +#define PE2 66 +#define PE3 67 +#define PE4 68 +#define PE5 69 +#define PE6 70 +#define PE7 71 +#define PE8 72 +#define PE9 73 +#define PE10 74 +#define PE11 75 +#define PE12 76 +#define PE13 77 +#define PE14 78 +#define PE15 79 +#define PF0 80 +#define PF1 81 +#define PF2 82 +#define PF3 83 +#define PF4 84 +#define PF5 85 +#define PF6 86 +#define PF7 87 +#define PF8 88 +#define PF9 89 +#define PF11 PIN_A16 +#define PF12 PIN_A17 +#define PF13 PIN_A18 +#define PF14 PIN_A19 +#define PF15 94 +#define PG0 95 +#define PG1 96 +#define PG2 97 +#define PG3 98 +#define PG4 99 +#define PG5 100 +#define PG6 101 +#define PG7 102 +#define PG8 103 +#define PG9 104 +#define PG10 105 +#define PG11 106 +#define PG12 107 +#define PG13 108 +#define PG14 109 +#define PG15 110 +#define PH0 111 +#define PH1 112 +#define PH2 113 +#define PH3 114 +#define PH6 115 +#define PH7 116 +#define PH9 117 +#define PH10 118 +#define PH11 119 +#define PH12 120 +#define PH13 121 +#define PH14 122 +#define PH15 123 +#define PI0 124 +#define PI1 125 +#define PI2 126 +#define PI3 127 +#define PI4 128 +#define PI5 129 +#define PI6 130 +#define PI7 131 +#define PI8 132 +#define PI9 133 +#define PI10 134 +#define PI11 135 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB4_ALT2 (PB4 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB5_ALT2 (PB5 | ALT2) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PF8_ALT1 (PF8 | ALT1) +#define PF9_ALT1 (PF9 | ALT1) +#define PG13_ALT1 (PG13 | ALT1) +#define PH6_ALT1 (PH6 | ALT1) +#define PH6_ALT2 (PH6 | ALT2) +#define PH7_ALT1 (PH7 | ALT1) +#define PH9_ALT1 (PH9 | ALT1) +#define PH9_ALT2 (PH9 | ALT2) +#define PH10_ALT1 (PH10 | ALT1) +#define PH10_ALT2 (PH10 | ALT2) +#define PH11_ALT1 (PH11 | ALT1) +#define PH11_ALT2 (PH11 | ALT2) +#define PH12_ALT1 (PH12 | ALT1) +#define PH13_ALT1 (PH13 | ALT1) + +#define NUM_DIGITAL_PINS 136 +#define NUM_ANALOG_INPUTS 20 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PG10 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB10 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_ETH_MODULE_DISABLED) + #define HAL_ETH_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32H5xx/H573MIYxQ/CMakeLists.txt b/variants/STM32H5xx/H573MIYxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H573MIYxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PeripheralPins.c b/variants/STM32H5xx/H573MIYxQ/PeripheralPins.c similarity index 98% rename from variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PeripheralPins.c rename to variants/STM32H5xx/H573MIYxQ/PeripheralPins.c index 9d9e3fb42b..cb329e045e 100644 --- a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H573MIYxQ/PeripheralPins.c @@ -11,8 +11,8 @@ ******************************************************************************* */ /* - * Automatically generated from STM32H563MIYxQ.xml, STM32H573MIYxQ.xml - * CubeMX DB release 6.0.80 + * Automatically generated from STM32H573MIYxQ.xml + * CubeMX DB release 6.0.90 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -505,11 +505,11 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { //*** USB *** #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB_DRD_FS[] = { - {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H573MIYxQ/PinNamesVar.h b/variants/STM32H5xx/H573MIYxQ/PinNamesVar.h new file mode 100644 index 0000000000..c06b9e6d50 --- /dev/null +++ b/variants/STM32H5xx/H573MIYxQ/PinNamesVar.h @@ -0,0 +1,84 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_4_ALT2 = PB_4 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_5_ALT2 = PB_5 | ALT2, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32H5xx/H573MIYxQ/boards_entry.txt b/variants/STM32H5xx/H573MIYxQ/boards_entry.txt new file mode 100644 index 0000000000..833c1152b3 --- /dev/null +++ b/variants/STM32H5xx/H573MIYxQ/boards_entry.txt @@ -0,0 +1,13 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic H573MIYxQ +GenH5.menu.pnum.GENERIC_H573MIYXQ=Generic H573MIYxQ +GenH5.menu.pnum.GENERIC_H573MIYXQ.upload.maximum_size=2097152 +GenH5.menu.pnum.GENERIC_H573MIYXQ.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H573MIYXQ.build.board=GENERIC_H573MIYXQ +GenH5.menu.pnum.GENERIC_H573MIYXQ.build.product_line=STM32H573xx +GenH5.menu.pnum.GENERIC_H573MIYXQ.build.variant=STM32H5xx/H573MIYxQ + diff --git a/variants/STM32H5xx/H573MIYxQ/generic_clock.c b/variants/STM32H5xx/H573MIYxQ/generic_clock.c new file mode 100644 index 0000000000..0635225e0c --- /dev/null +++ b/variants/STM32H5xx/H573MIYxQ/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H573MIYXQ) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573MIYxQ/variant_generic.cpp b/variants/STM32H5xx/H573MIYxQ/variant_generic.cpp new file mode 100644 index 0000000000..0f52f3f205 --- /dev/null +++ b/variants/STM32H5xx/H573MIYxQ/variant_generic.cpp @@ -0,0 +1,97 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H573MIYXQ) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_10, // D25 + PB_12, // D26 + PB_13, // D27 + PB_14, // D28 + PB_15, // D29 + PC_0, // D30/A10 + PC_1, // D31/A11 + PC_2, // D32/A12 + PC_3, // D33/A13 + PC_4, // D34/A14 + PC_5, // D35/A15 + PC_6, // D36 + PC_7, // D37 + PC_8, // D38 + PC_9, // D39 + PC_10, // D40 + PC_11, // D41 + PC_12, // D42 + PC_13, // D43 + PC_14, // D44 + PC_15, // D45 + PD_0, // D46 + PD_1, // D47 + PD_2, // D48 + PD_14, // D49 + PD_15, // D50 + PE_7, // D51 + PE_8, // D52 + PE_9, // D53 + PE_10, // D54 + PH_0, // D55 + PH_1 // D56 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 30, // A10, PC0 + 31, // A11, PC1 + 32, // A12, PC2 + 33, // A13, PC3 + 34, // A14, PC4 + 35 // A15, PC5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573MIYxQ/variant_generic.h b/variants/STM32H5xx/H573MIYxQ/variant_generic.h new file mode 100644 index 0000000000..70f49431b0 --- /dev/null +++ b/variants/STM32H5xx/H573MIYxQ/variant_generic.h @@ -0,0 +1,238 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB10 25 +#define PB12 26 +#define PB13 27 +#define PB14 28 +#define PB15 29 +#define PC0 PIN_A10 +#define PC1 PIN_A11 +#define PC2 PIN_A12 +#define PC3 PIN_A13 +#define PC4 PIN_A14 +#define PC5 PIN_A15 +#define PC6 36 +#define PC7 37 +#define PC8 38 +#define PC9 39 +#define PC10 40 +#define PC11 41 +#define PC12 42 +#define PC13 43 +#define PC14 44 +#define PC15 45 +#define PD0 46 +#define PD1 47 +#define PD2 48 +#define PD14 49 +#define PD15 50 +#define PE7 51 +#define PE8 52 +#define PE9 53 +#define PE10 54 +#define PH0 55 +#define PH1 56 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB4_ALT2 (PB4 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB5_ALT2 (PB5 | ALT2) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 57 +#define NUM_ANALOG_INPUTS 16 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB10 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// SDMMC signals not available +#define SDMMC_CDIR_NA + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_ETH_MODULE_DISABLED) + #define HAL_ETH_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32H5xx/H573RIT/CMakeLists.txt b/variants/STM32H5xx/H573RIT/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H573RIT/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H563R(G-I)T_H573RIT/PeripheralPins.c b/variants/STM32H5xx/H573RIT/PeripheralPins.c similarity index 98% rename from variants/STM32H5xx/H563R(G-I)T_H573RIT/PeripheralPins.c rename to variants/STM32H5xx/H573RIT/PeripheralPins.c index a65b6561bd..efa34c71a9 100644 --- a/variants/STM32H5xx/H563R(G-I)T_H573RIT/PeripheralPins.c +++ b/variants/STM32H5xx/H573RIT/PeripheralPins.c @@ -11,9 +11,8 @@ ******************************************************************************* */ /* - * Automatically generated from STM32H563RGTx.xml, STM32H563RITx.xml - * STM32H573RITx.xml - * CubeMX DB release 6.0.80 + * Automatically generated from STM32H573RITx.xml + * CubeMX DB release 6.0.90 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -479,11 +478,11 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { //*** USB *** #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB_DRD_FS[] = { - {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H573RIT/PinNamesVar.h b/variants/STM32H5xx/H573RIT/PinNamesVar.h new file mode 100644 index 0000000000..c06b9e6d50 --- /dev/null +++ b/variants/STM32H5xx/H573RIT/PinNamesVar.h @@ -0,0 +1,84 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_4_ALT2 = PB_4 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_5_ALT2 = PB_5 | ALT2, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32H5xx/H573RIT/boards_entry.txt b/variants/STM32H5xx/H573RIT/boards_entry.txt new file mode 100644 index 0000000000..70654bdc5d --- /dev/null +++ b/variants/STM32H5xx/H573RIT/boards_entry.txt @@ -0,0 +1,13 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic H573RITx +GenH5.menu.pnum.GENERIC_H573RITX=Generic H573RITx +GenH5.menu.pnum.GENERIC_H573RITX.upload.maximum_size=2097152 +GenH5.menu.pnum.GENERIC_H573RITX.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H573RITX.build.board=GENERIC_H573RITX +GenH5.menu.pnum.GENERIC_H573RITX.build.product_line=STM32H573xx +GenH5.menu.pnum.GENERIC_H573RITX.build.variant=STM32H5xx/H573RIT + diff --git a/variants/STM32H5xx/H573RIT/generic_clock.c b/variants/STM32H5xx/H573RIT/generic_clock.c new file mode 100644 index 0000000000..a6f79ede55 --- /dev/null +++ b/variants/STM32H5xx/H573RIT/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H573RITX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573RIT/variant_generic.cpp b/variants/STM32H5xx/H573RIT/variant_generic.cpp new file mode 100644 index 0000000000..6b8a4158f8 --- /dev/null +++ b/variants/STM32H5xx/H573RIT/variant_generic.cpp @@ -0,0 +1,89 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H573RITX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_10, // D25 + PB_12, // D26 + PB_13, // D27 + PB_14, // D28 + PB_15, // D29 + PC_0, // D30/A10 + PC_1, // D31/A11 + PC_2, // D32/A12 + PC_3, // D33/A13 + PC_4, // D34/A14 + PC_5, // D35/A15 + PC_6, // D36 + PC_7, // D37 + PC_8, // D38 + PC_9, // D39 + PC_10, // D40 + PC_11, // D41 + PC_12, // D42 + PC_13, // D43 + PC_14, // D44 + PC_15, // D45 + PD_2, // D46 + PH_0, // D47 + PH_1 // D48 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 30, // A10, PC0 + 31, // A11, PC1 + 32, // A12, PC2 + 33, // A13, PC3 + 34, // A14, PC4 + 35 // A15, PC5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573RIT/variant_generic.h b/variants/STM32H5xx/H573RIT/variant_generic.h new file mode 100644 index 0000000000..5a73f7757a --- /dev/null +++ b/variants/STM32H5xx/H573RIT/variant_generic.h @@ -0,0 +1,230 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB10 25 +#define PB12 26 +#define PB13 27 +#define PB14 28 +#define PB15 29 +#define PC0 PIN_A10 +#define PC1 PIN_A11 +#define PC2 PIN_A12 +#define PC3 PIN_A13 +#define PC4 PIN_A14 +#define PC5 PIN_A15 +#define PC6 36 +#define PC7 37 +#define PC8 38 +#define PC9 39 +#define PC10 40 +#define PC11 41 +#define PC12 42 +#define PC13 43 +#define PC14 44 +#define PC15 45 +#define PD2 46 +#define PH0 47 +#define PH1 48 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB4_ALT2 (PB4 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB5_ALT2 (PB5 | ALT2) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 49 +#define NUM_ANALOG_INPUTS 16 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB10 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// SDMMC signals not available +#define SDMMC_CDIR_NA + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_ETH_MODULE_DISABLED) + #define HAL_ETH_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32H5xx/H573RIV/CMakeLists.txt b/variants/STM32H5xx/H573RIV/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H573RIV/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H563R(G-I)V_H573RIV/PeripheralPins.c b/variants/STM32H5xx/H573RIV/PeripheralPins.c similarity index 98% rename from variants/STM32H5xx/H563R(G-I)V_H573RIV/PeripheralPins.c rename to variants/STM32H5xx/H573RIV/PeripheralPins.c index c6f5b8f657..8ed83a895c 100644 --- a/variants/STM32H5xx/H563R(G-I)V_H573RIV/PeripheralPins.c +++ b/variants/STM32H5xx/H573RIV/PeripheralPins.c @@ -11,9 +11,8 @@ ******************************************************************************* */ /* - * Automatically generated from STM32H563RGVx.xml, STM32H563RIVx.xml - * STM32H573RIVx.xml - * CubeMX DB release 6.0.80 + * Automatically generated from STM32H573RIVx.xml + * CubeMX DB release 6.0.90 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -500,11 +499,11 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { //*** USB *** #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB_DRD_FS[] = { - {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H573RIV/PinNamesVar.h b/variants/STM32H5xx/H573RIV/PinNamesVar.h new file mode 100644 index 0000000000..1ee6296ec3 --- /dev/null +++ b/variants/STM32H5xx/H573RIV/PinNamesVar.h @@ -0,0 +1,85 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_4_ALT2 = PB_4 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_5_ALT2 = PB_5 | ALT2, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32H5xx/H573RIV/boards_entry.txt b/variants/STM32H5xx/H573RIV/boards_entry.txt new file mode 100644 index 0000000000..2c0c35462f --- /dev/null +++ b/variants/STM32H5xx/H573RIV/boards_entry.txt @@ -0,0 +1,13 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic H573RIVx +GenH5.menu.pnum.GENERIC_H573RIVX=Generic H573RIVx +GenH5.menu.pnum.GENERIC_H573RIVX.upload.maximum_size=2097152 +GenH5.menu.pnum.GENERIC_H573RIVX.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H573RIVX.build.board=GENERIC_H573RIVX +GenH5.menu.pnum.GENERIC_H573RIVX.build.product_line=STM32H573xx +GenH5.menu.pnum.GENERIC_H573RIVX.build.variant=STM32H5xx/H573RIV + diff --git a/variants/STM32H5xx/H573RIV/generic_clock.c b/variants/STM32H5xx/H573RIV/generic_clock.c new file mode 100644 index 0000000000..e4587f4e08 --- /dev/null +++ b/variants/STM32H5xx/H573RIV/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H573RIVX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573RIV/variant_generic.cpp b/variants/STM32H5xx/H573RIV/variant_generic.cpp new file mode 100644 index 0000000000..deaba50874 --- /dev/null +++ b/variants/STM32H5xx/H573RIV/variant_generic.cpp @@ -0,0 +1,93 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H573RIVX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_11, // D27 + PB_12, // D28 + PB_13, // D29 + PB_14, // D30 + PB_15, // D31 + PC_0, // D32/A10 + PC_1, // D33/A11 + PC_2, // D34/A12 + PC_3, // D35/A13 + PC_4, // D36/A14 + PC_5, // D37/A15 + PC_6, // D38 + PC_7, // D39 + PC_8, // D40 + PC_9, // D41 + PC_10, // D42 + PC_11, // D43 + PC_12, // D44 + PC_13, // D45 + PC_14, // D46 + PC_15, // D47 + PD_11, // D48 + PD_12, // D49 + PE_0, // D50 + PH_0, // D51 + PH_1 // D52 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 32, // A10, PC0 + 33, // A11, PC1 + 34, // A12, PC2 + 35, // A13, PC3 + 36, // A14, PC4 + 37 // A15, PC5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573RIV/variant_generic.h b/variants/STM32H5xx/H573RIV/variant_generic.h new file mode 100644 index 0000000000..34c02d73af --- /dev/null +++ b/variants/STM32H5xx/H573RIV/variant_generic.h @@ -0,0 +1,232 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 27 +#define PB12 28 +#define PB13 29 +#define PB14 30 +#define PB15 31 +#define PC0 PIN_A10 +#define PC1 PIN_A11 +#define PC2 PIN_A12 +#define PC3 PIN_A13 +#define PC4 PIN_A14 +#define PC5 PIN_A15 +#define PC6 38 +#define PC7 39 +#define PC8 40 +#define PC9 41 +#define PC10 42 +#define PC11 43 +#define PC12 44 +#define PC13 45 +#define PC14 46 +#define PC15 47 +#define PD11 48 +#define PD12 49 +#define PE0 50 +#define PH0 51 +#define PH1 52 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB4_ALT2 (PB4 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB5_ALT2 (PB5 | ALT2) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 53 +#define NUM_ANALOG_INPUTS 16 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB10 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_ETH_MODULE_DISABLED) + #define HAL_ETH_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32H5xx/H573VIT/CMakeLists.txt b/variants/STM32H5xx/H573VIT/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H573VIT/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H563V(G-I)T_H573VIT/PeripheralPins.c b/variants/STM32H5xx/H573VIT/PeripheralPins.c similarity index 98% rename from variants/STM32H5xx/H563V(G-I)T_H573VIT/PeripheralPins.c rename to variants/STM32H5xx/H573VIT/PeripheralPins.c index e68b52bd5a..16dc6127d9 100644 --- a/variants/STM32H5xx/H563V(G-I)T_H573VIT/PeripheralPins.c +++ b/variants/STM32H5xx/H573VIT/PeripheralPins.c @@ -11,9 +11,8 @@ ******************************************************************************* */ /* - * Automatically generated from STM32H563VGTx.xml, STM32H563VITx.xml - * STM32H573VITx.xml - * CubeMX DB release 6.0.80 + * Automatically generated from STM32H573VITx.xml + * CubeMX DB release 6.0.90 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -570,11 +569,11 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { //*** USB *** #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB_DRD_FS[] = { - {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H573VIT/PinNamesVar.h b/variants/STM32H5xx/H573VIT/PinNamesVar.h new file mode 100644 index 0000000000..118d5c80d2 --- /dev/null +++ b/variants/STM32H5xx/H573VIT/PinNamesVar.h @@ -0,0 +1,85 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_4_ALT2 = PB_4 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_5_ALT2 = PB_5 | ALT2, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = PD_3, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32H5xx/H573VIT/boards_entry.txt b/variants/STM32H5xx/H573VIT/boards_entry.txt new file mode 100644 index 0000000000..3e62eb15a5 --- /dev/null +++ b/variants/STM32H5xx/H573VIT/boards_entry.txt @@ -0,0 +1,13 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic H573VITx +GenH5.menu.pnum.GENERIC_H573VITX=Generic H573VITx +GenH5.menu.pnum.GENERIC_H573VITX.upload.maximum_size=2097152 +GenH5.menu.pnum.GENERIC_H573VITX.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H573VITX.build.board=GENERIC_H573VITX +GenH5.menu.pnum.GENERIC_H573VITX.build.product_line=STM32H573xx +GenH5.menu.pnum.GENERIC_H573VITX.build.variant=STM32H5xx/H573VIT + diff --git a/variants/STM32H5xx/H573VIT/generic_clock.c b/variants/STM32H5xx/H573VIT/generic_clock.c new file mode 100644 index 0000000000..21ac09faa6 --- /dev/null +++ b/variants/STM32H5xx/H573VIT/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H573VITX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573VIT/variant_generic.cpp b/variants/STM32H5xx/H573VIT/variant_generic.cpp new file mode 100644 index 0000000000..c6a0c12914 --- /dev/null +++ b/variants/STM32H5xx/H573VIT/variant_generic.cpp @@ -0,0 +1,120 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H573VITX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A10 + PC_1, // D32/A11 + PC_2, // D33/A12 + PC_3, // D34/A13 + PC_4, // D35/A14 + PC_5, // D36/A15 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_0, // D47 + PD_1, // D48 + PD_2, // D49 + PD_3, // D50 + PD_4, // D51 + PD_5, // D52 + PD_6, // D53 + PD_7, // D54 + PD_8, // D55 + PD_9, // D56 + PD_10, // D57 + PD_11, // D58 + PD_12, // D59 + PD_13, // D60 + PD_14, // D61 + PD_15, // D62 + PE_0, // D63 + PE_2, // D64 + PE_3, // D65 + PE_4, // D66 + PE_5, // D67 + PE_6, // D68 + PE_7, // D69 + PE_8, // D70 + PE_9, // D71 + PE_10, // D72 + PE_11, // D73 + PE_12, // D74 + PE_13, // D75 + PE_14, // D76 + PE_15, // D77 + PH_0, // D78 + PH_1 // D79 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 31, // A10, PC0 + 32, // A11, PC1 + 33, // A12, PC2 + 34, // A13, PC3 + 35, // A14, PC4 + 36 // A15, PC5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573VIT/variant_generic.h b/variants/STM32H5xx/H573VIT/variant_generic.h new file mode 100644 index 0000000000..2ddfafc68c --- /dev/null +++ b/variants/STM32H5xx/H573VIT/variant_generic.h @@ -0,0 +1,259 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A10 +#define PC1 PIN_A11 +#define PC2 PIN_A12 +#define PC3 PIN_A13 +#define PC4 PIN_A14 +#define PC5 PIN_A15 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD0 47 +#define PD1 48 +#define PD2 49 +#define PD3 50 +#define PD4 51 +#define PD5 52 +#define PD6 53 +#define PD7 54 +#define PD8 55 +#define PD9 56 +#define PD10 57 +#define PD11 58 +#define PD12 59 +#define PD13 60 +#define PD14 61 +#define PD15 62 +#define PE0 63 +#define PE2 64 +#define PE3 65 +#define PE4 66 +#define PE5 67 +#define PE6 68 +#define PE7 69 +#define PE8 70 +#define PE9 71 +#define PE10 72 +#define PE11 73 +#define PE12 74 +#define PE13 75 +#define PE14 76 +#define PE15 77 +#define PH0 78 +#define PH1 79 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB4_ALT2 (PB4 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB5_ALT2 (PB5 | ALT2) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 80 +#define NUM_ANALOG_INPUTS 16 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB10 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_ETH_MODULE_DISABLED) + #define HAL_ETH_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32H5xx/H573ZIT/CMakeLists.txt b/variants/STM32H5xx/H573ZIT/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H573ZIT/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PeripheralPins.c b/variants/STM32H5xx/H573ZIT/PeripheralPins.c similarity index 99% rename from variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PeripheralPins.c rename to variants/STM32H5xx/H573ZIT/PeripheralPins.c index 156f64e6e8..5c1e4c5f46 100644 --- a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PeripheralPins.c +++ b/variants/STM32H5xx/H573ZIT/PeripheralPins.c @@ -11,9 +11,8 @@ ******************************************************************************* */ /* - * Automatically generated from STM32H563ZGTx.xml, STM32H563ZITx.xml - * STM32H573ZITx.xml - * CubeMX DB release 6.0.80 + * Automatically generated from STM32H573ZITx.xml + * CubeMX DB release 6.0.90 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -640,11 +639,11 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { //*** USB *** #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) -WEAK const PinMap PinMap_USB_DRD_FS[] = { - {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP - {NC, NP, 0} +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} }; #endif diff --git a/variants/STM32H5xx/H573ZIT/PinNamesVar.h b/variants/STM32H5xx/H573ZIT/PinNamesVar.h new file mode 100644 index 0000000000..df96a15ce4 --- /dev/null +++ b/variants/STM32H5xx/H573ZIT/PinNamesVar.h @@ -0,0 +1,88 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_4_ALT2 = PA_4 | ALT2, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_4_ALT2 = PB_4 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_5_ALT2 = PB_5 | ALT2, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PF_8_ALT1 = PF_8 | ALT1, +PF_9_ALT1 = PF_9 | ALT1, +PG_13_ALT1 = PG_13 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = PD_3, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32H5xx/H573ZIT/boards_entry.txt b/variants/STM32H5xx/H573ZIT/boards_entry.txt new file mode 100644 index 0000000000..59ac286e27 --- /dev/null +++ b/variants/STM32H5xx/H573ZIT/boards_entry.txt @@ -0,0 +1,13 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic H573ZITx +GenH5.menu.pnum.GENERIC_H573ZITX=Generic H573ZITx +GenH5.menu.pnum.GENERIC_H573ZITX.upload.maximum_size=2097152 +GenH5.menu.pnum.GENERIC_H573ZITX.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H573ZITX.build.board=GENERIC_H573ZITX +GenH5.menu.pnum.GENERIC_H573ZITX.build.product_line=STM32H573xx +GenH5.menu.pnum.GENERIC_H573ZITX.build.variant=STM32H5xx/H573ZIT + diff --git a/variants/STM32H5xx/H573ZIT/generic_clock.c b/variants/STM32H5xx/H573ZIT/generic_clock.c new file mode 100644 index 0000000000..13ee132a5e --- /dev/null +++ b/variants/STM32H5xx/H573ZIT/generic_clock.c @@ -0,0 +1,89 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H573ZITX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI + | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_CSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV2; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.CSIState = RCC_CSI_ON; + RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 125; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 + | RCC_CLOCKTYPE_PCLK3; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 + | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 + | RCC_PERIPHCLK_USB; + PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; + PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573ZIT/ldscript.ld b/variants/STM32H5xx/H573ZIT/ldscript.ld new file mode 100644 index 0000000000..a1ced4e188 --- /dev/null +++ b/variants/STM32H5xx/H573ZIT/ldscript.ld @@ -0,0 +1,185 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32H563ZITx Device from STM32H5 series +** 2048Kbytes FLASH +** 640Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE + FLASH (rx) : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/variants/STM32H5xx/H573ZIT/variant_generic.cpp b/variants/STM32H5xx/H573ZIT/variant_generic.cpp new file mode 100644 index 0000000000..922235bc8f --- /dev/null +++ b/variants/STM32H5xx/H573ZIT/variant_generic.cpp @@ -0,0 +1,156 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H573ZITX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A10 + PC_1, // D32/A11 + PC_2, // D33/A12 + PC_3, // D34/A13 + PC_4, // D35/A14 + PC_5, // D36/A15 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_0, // D47 + PD_1, // D48 + PD_2, // D49 + PD_3, // D50 + PD_4, // D51 + PD_5, // D52 + PD_6, // D53 + PD_7, // D54 + PD_8, // D55 + PD_9, // D56 + PD_10, // D57 + PD_11, // D58 + PD_12, // D59 + PD_13, // D60 + PD_14, // D61 + PD_15, // D62 + PE_0, // D63 + PE_2, // D64 + PE_3, // D65 + PE_4, // D66 + PE_5, // D67 + PE_6, // D68 + PE_7, // D69 + PE_8, // D70 + PE_9, // D71 + PE_10, // D72 + PE_11, // D73 + PE_12, // D74 + PE_13, // D75 + PE_14, // D76 + PE_15, // D77 + PF_0, // D78 + PF_1, // D79 + PF_2, // D80 + PF_3, // D81 + PF_4, // D82 + PF_5, // D83 + PF_6, // D84 + PF_7, // D85 + PF_8, // D86 + PF_9, // D87 + PF_10, // D88 + PF_11, // D89/A16 + PF_12, // D90/A17 + PF_13, // D91/A18 + PF_14, // D92/A19 + PF_15, // D93 + PG_0, // D94 + PG_1, // D95 + PG_2, // D96 + PG_3, // D97 + PG_4, // D98 + PG_5, // D99 + PG_6, // D100 + PG_7, // D101 + PG_8, // D102 + PG_9, // D103 + PG_10, // D104 + PG_11, // D105 + PG_12, // D106 + PG_13, // D107 + PG_14, // D108 + PG_15, // D109 + PH_0, // D110 + PH_1 // D111 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 31, // A10, PC0 + 32, // A11, PC1 + 33, // A12, PC2 + 34, // A13, PC3 + 35, // A14, PC4 + 36, // A15, PC5 + 89, // A16, PF11 + 90, // A17, PF12 + 91, // A18, PF13 + 92 // A19, PF14 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H573ZIT/variant_generic.h b/variants/STM32H5xx/H573ZIT/variant_generic.h new file mode 100644 index 0000000000..a3c4588c43 --- /dev/null +++ b/variants/STM32H5xx/H573ZIT/variant_generic.h @@ -0,0 +1,294 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A10 +#define PC1 PIN_A11 +#define PC2 PIN_A12 +#define PC3 PIN_A13 +#define PC4 PIN_A14 +#define PC5 PIN_A15 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD0 47 +#define PD1 48 +#define PD2 49 +#define PD3 50 +#define PD4 51 +#define PD5 52 +#define PD6 53 +#define PD7 54 +#define PD8 55 +#define PD9 56 +#define PD10 57 +#define PD11 58 +#define PD12 59 +#define PD13 60 +#define PD14 61 +#define PD15 62 +#define PE0 63 +#define PE2 64 +#define PE3 65 +#define PE4 66 +#define PE5 67 +#define PE6 68 +#define PE7 69 +#define PE8 70 +#define PE9 71 +#define PE10 72 +#define PE11 73 +#define PE12 74 +#define PE13 75 +#define PE14 76 +#define PE15 77 +#define PF0 78 +#define PF1 79 +#define PF2 80 +#define PF3 81 +#define PF4 82 +#define PF5 83 +#define PF6 84 +#define PF7 85 +#define PF8 86 +#define PF9 87 +#define PF10 88 +#define PF11 PIN_A16 +#define PF12 PIN_A17 +#define PF13 PIN_A18 +#define PF14 PIN_A19 +#define PF15 93 +#define PG0 94 +#define PG1 95 +#define PG2 96 +#define PG3 97 +#define PG4 98 +#define PG5 99 +#define PG6 100 +#define PG7 101 +#define PG8 102 +#define PG9 103 +#define PG10 104 +#define PG11 105 +#define PG12 106 +#define PG13 107 +#define PG14 108 +#define PG15 109 +#define PH0 110 +#define PH1 111 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB4_ALT2 (PB4 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB5_ALT2 (PB5 | ALT2) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PF8_ALT1 (PF8 | ALT1) +#define PF9_ALT1 (PF9 | ALT1) +#define PG13_ALT1 (PG13 | ALT1) + +#define NUM_DIGITAL_PINS 112 +#define NUM_ANALOG_INPUTS 20 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PG10 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB10 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_ETH_MODULE_DISABLED) + #define HAL_ETH_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif